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qlge: Add serdes reg blocks dump to firmware dump.
[deliverable/linux.git] / drivers / net / qlge / qlge_dbg.c
CommitLineData
c4e84bde
RM		 1#include "qlge.h"
2
24bb55b4
RM		 3/* Read a NIC register from the alternate function. */
4static u32 ql_read_other_func_reg(struct ql_adapter *qdev,
5 u32 reg)
6{
7 u32 register_to_read;
8 u32 reg_val;
9 unsigned int status = 0;
10
11 register_to_read = MPI_NIC_REG_BLOCK
12 | MPI_NIC_READ
13 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
14 | reg;
15 status = ql_read_mpi_reg(qdev, register_to_read, &reg_val);
16 if (status != 0)
17 return 0xffffffff;
18
19 return reg_val;
20}
a61f8026 21
a48c86fd
RM		 22/* Write a NIC register from the alternate function. */
23static int ql_write_other_func_reg(struct ql_adapter *qdev,
24 u32 reg, u32 reg_val)
25{
26 u32 register_to_read;
27 int status = 0;
28
29 register_to_read = MPI_NIC_REG_BLOCK
30 | MPI_NIC_READ
31 | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT)
32 | reg;
33 status = ql_write_mpi_reg(qdev, register_to_read, reg_val);
34
35 return status;
36}
37
38static int ql_wait_other_func_reg_rdy(struct ql_adapter *qdev, u32 reg,
39 u32 bit, u32 err_bit)
40{
41 u32 temp;
42 int count = 10;
43
44 while (count) {
45 temp = ql_read_other_func_reg(qdev, reg);
46
47 /* check for errors */
48 if (temp & err_bit)
49 return -1;
50 else if (temp & bit)
51 return 0;
52 mdelay(10);
53 count--;
54 }
55 return -1;
56}
57
58static int ql_read_other_func_serdes_reg(struct ql_adapter *qdev, u32 reg,
59 u32 *data)
60{
61 int status;
62
63 /* wait for reg to come ready */
64 status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
65 XG_SERDES_ADDR_RDY, 0);
66 if (status)
67 goto exit;
68
69 /* set up for reg read */
70 ql_write_other_func_reg(qdev, XG_SERDES_ADDR/4, reg | PROC_ADDR_R);
71
72 /* wait for reg to come ready */
73 status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4,
74 XG_SERDES_ADDR_RDY, 0);
75 if (status)
76 goto exit;
77
78 /* get the data */
79 *data = ql_read_other_func_reg(qdev, (XG_SERDES_DATA / 4));
80exit:
81 return status;
82}
83
84/* Read out the SERDES registers */
85static int ql_read_serdes_reg(struct ql_adapter *qdev, u32 reg, u32 * data)
86{
87 int status;
88
89 /* wait for reg to come ready */
90 status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
91 if (status)
92 goto exit;
93
94 /* set up for reg read */
95 ql_write32(qdev, XG_SERDES_ADDR, reg | PROC_ADDR_R);
96
97 /* wait for reg to come ready */
98 status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0);
99 if (status)
100 goto exit;
101
102 /* get the data */
103 *data = ql_read32(qdev, XG_SERDES_DATA);
104exit:
105 return status;
106}
107
108static void ql_get_both_serdes(struct ql_adapter *qdev, u32 addr,
109 u32 *direct_ptr, u32 *indirect_ptr,
110 unsigned int direct_valid, unsigned int indirect_valid)
111{
112 unsigned int status;
113
114 status = 1;
115 if (direct_valid)
116 status = ql_read_serdes_reg(qdev, addr, direct_ptr);
117 /* Dead fill any failures or invalids. */
118 if (status)
119 *direct_ptr = 0xDEADBEEF;
120
121 status = 1;
122 if (indirect_valid)
123 status = ql_read_other_func_serdes_reg(
124 qdev, addr, indirect_ptr);
125 /* Dead fill any failures or invalids. */
126 if (status)
127 *indirect_ptr = 0xDEADBEEF;
128}
129
130static int ql_get_serdes_regs(struct ql_adapter *qdev,
131 struct ql_mpi_coredump *mpi_coredump)
132{
133 int status;
134 unsigned int xfi_direct_valid, xfi_indirect_valid, xaui_direct_valid;
135 unsigned int xaui_indirect_valid, i;
136 u32 *direct_ptr, temp;
137 u32 *indirect_ptr;
138
139 xfi_direct_valid = xfi_indirect_valid = 0;
140 xaui_direct_valid = xaui_indirect_valid = 1;
141
142 /* The XAUI needs to be read out per port */
143 if (qdev->func & 1) {
144 /* We are NIC 2 */
145 status = ql_read_other_func_serdes_reg(qdev,
146 XG_SERDES_XAUI_HSS_PCS_START, &temp);
147 if (status)
148 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
149 if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
150 XG_SERDES_ADDR_XAUI_PWR_DOWN)
151 xaui_indirect_valid = 0;
152
153 status = ql_read_serdes_reg(qdev,
154 XG_SERDES_XAUI_HSS_PCS_START, &temp);
155 if (status)
156 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
157
158 if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
159 XG_SERDES_ADDR_XAUI_PWR_DOWN)
160 xaui_direct_valid = 0;
161 } else {
162 /* We are NIC 1 */
163 status = ql_read_other_func_serdes_reg(qdev,
164 XG_SERDES_XAUI_HSS_PCS_START, &temp);
165 if (status)
166 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
167 if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
168 XG_SERDES_ADDR_XAUI_PWR_DOWN)
169 xaui_indirect_valid = 0;
170
171 status = ql_read_serdes_reg(qdev,
172 XG_SERDES_XAUI_HSS_PCS_START, &temp);
173 if (status)
174 temp = XG_SERDES_ADDR_XAUI_PWR_DOWN;
175 if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) ==
176 XG_SERDES_ADDR_XAUI_PWR_DOWN)
177 xaui_direct_valid = 0;
178 }
179
180 /*
181 * XFI register is shared so only need to read one
182 * functions and then check the bits.
183 */
184 status = ql_read_serdes_reg(qdev, XG_SERDES_ADDR_STS, &temp);
185 if (status)
186 temp = 0;
187
188 if ((temp & XG_SERDES_ADDR_XFI1_PWR_UP) ==
189 XG_SERDES_ADDR_XFI1_PWR_UP) {
190 /* now see if i'm NIC 1 or NIC 2 */
191 if (qdev->func & 1)
192 /* I'm NIC 2, so the indirect (NIC1) xfi is up. */
193 xfi_indirect_valid = 1;
194 else
195 xfi_direct_valid = 1;
196 }
197 if ((temp & XG_SERDES_ADDR_XFI2_PWR_UP) ==
198 XG_SERDES_ADDR_XFI2_PWR_UP) {
199 /* now see if i'm NIC 1 or NIC 2 */
200 if (qdev->func & 1)
201 /* I'm NIC 2, so the indirect (NIC1) xfi is up. */
202 xfi_direct_valid = 1;
203 else
204 xfi_indirect_valid = 1;
205 }
206
207 /* Get XAUI_AN register block. */
208 if (qdev->func & 1) {
209 /* Function 2 is direct */
210 direct_ptr = mpi_coredump->serdes2_xaui_an;
211 indirect_ptr = mpi_coredump->serdes_xaui_an;
212 } else {
213 /* Function 1 is direct */
214 direct_ptr = mpi_coredump->serdes_xaui_an;
215 indirect_ptr = mpi_coredump->serdes2_xaui_an;
216 }
217
218 for (i = 0; i <= 0x000000034; i += 4, direct_ptr++, indirect_ptr++)
219 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
220 xaui_direct_valid, xaui_indirect_valid);
221
222 /* Get XAUI_HSS_PCS register block. */
223 if (qdev->func & 1) {
224 direct_ptr =
225 mpi_coredump->serdes2_xaui_hss_pcs;
226 indirect_ptr =
227 mpi_coredump->serdes_xaui_hss_pcs;
228 } else {
229 direct_ptr =
230 mpi_coredump->serdes_xaui_hss_pcs;
231 indirect_ptr =
232 mpi_coredump->serdes2_xaui_hss_pcs;
233 }
234
235 for (i = 0x800; i <= 0x880; i += 4, direct_ptr++, indirect_ptr++)
236 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
237 xaui_direct_valid, xaui_indirect_valid);
238
239 /* Get XAUI_XFI_AN register block. */
240 if (qdev->func & 1) {
241 direct_ptr = mpi_coredump->serdes2_xfi_an;
242 indirect_ptr = mpi_coredump->serdes_xfi_an;
243 } else {
244 direct_ptr = mpi_coredump->serdes_xfi_an;
245 indirect_ptr = mpi_coredump->serdes2_xfi_an;
246 }
247
248 for (i = 0x1000; i <= 0x1034; i += 4, direct_ptr++, indirect_ptr++)
249 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
250 xfi_direct_valid, xfi_indirect_valid);
251
252 /* Get XAUI_XFI_TRAIN register block. */
253 if (qdev->func & 1) {
254 direct_ptr = mpi_coredump->serdes2_xfi_train;
255 indirect_ptr =
256 mpi_coredump->serdes_xfi_train;
257 } else {
258 direct_ptr = mpi_coredump->serdes_xfi_train;
259 indirect_ptr =
260 mpi_coredump->serdes2_xfi_train;
261 }
262
263 for (i = 0x1050; i <= 0x107c; i += 4, direct_ptr++, indirect_ptr++)
264 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
265 xfi_direct_valid, xfi_indirect_valid);
266
267 /* Get XAUI_XFI_HSS_PCS register block. */
268 if (qdev->func & 1) {
269 direct_ptr =
270 mpi_coredump->serdes2_xfi_hss_pcs;
271 indirect_ptr =
272 mpi_coredump->serdes_xfi_hss_pcs;
273 } else {
274 direct_ptr =
275 mpi_coredump->serdes_xfi_hss_pcs;
276 indirect_ptr =
277 mpi_coredump->serdes2_xfi_hss_pcs;
278 }
279
280 for (i = 0x1800; i <= 0x1838; i += 4, direct_ptr++, indirect_ptr++)
281 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
282 xfi_direct_valid, xfi_indirect_valid);
283
284 /* Get XAUI_XFI_HSS_TX register block. */
285 if (qdev->func & 1) {
286 direct_ptr =
287 mpi_coredump->serdes2_xfi_hss_tx;
288 indirect_ptr =
289 mpi_coredump->serdes_xfi_hss_tx;
290 } else {
291 direct_ptr = mpi_coredump->serdes_xfi_hss_tx;
292 indirect_ptr =
293 mpi_coredump->serdes2_xfi_hss_tx;
294 }
295 for (i = 0x1c00; i <= 0x1c1f; i++, direct_ptr++, indirect_ptr++)
296 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
297 xfi_direct_valid, xfi_indirect_valid);
298
299 /* Get XAUI_XFI_HSS_RX register block. */
300 if (qdev->func & 1) {
301 direct_ptr =
302 mpi_coredump->serdes2_xfi_hss_rx;
303 indirect_ptr =
304 mpi_coredump->serdes_xfi_hss_rx;
305 } else {
306 direct_ptr = mpi_coredump->serdes_xfi_hss_rx;
307 indirect_ptr =
308 mpi_coredump->serdes2_xfi_hss_rx;
309 }
310
311 for (i = 0x1c40; i <= 0x1c5f; i++, direct_ptr++, indirect_ptr++)
312 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
313 xfi_direct_valid, xfi_indirect_valid);
314
315
316 /* Get XAUI_XFI_HSS_PLL register block. */
317 if (qdev->func & 1) {
318 direct_ptr =
319 mpi_coredump->serdes2_xfi_hss_pll;
320 indirect_ptr =
321 mpi_coredump->serdes_xfi_hss_pll;
322 } else {
323 direct_ptr =
324 mpi_coredump->serdes_xfi_hss_pll;
325 indirect_ptr =
326 mpi_coredump->serdes2_xfi_hss_pll;
327 }
328 for (i = 0x1e00; i <= 0x1e1f; i++, direct_ptr++, indirect_ptr++)
329 ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr,
330 xfi_direct_valid, xfi_indirect_valid);
331 return 0;
332}
333
a61f8026
RM		 334static int ql_get_ets_regs(struct ql_adapter *qdev, u32 * buf)
335{
336 int status = 0;
337 int i;
338
339 for (i = 0; i < 8; i++, buf++) {
340 ql_write32(qdev, NIC_ETS, i << 29 | 0x08000000);
341 *buf = ql_read32(qdev, NIC_ETS);
342 }
343
344 for (i = 0; i < 2; i++, buf++) {
345 ql_write32(qdev, CNA_ETS, i << 29 | 0x08000000);
346 *buf = ql_read32(qdev, CNA_ETS);
347 }
348
349 return status;
350}
351
352static void ql_get_intr_states(struct ql_adapter *qdev, u32 * buf)
353{
354 int i;
355
356 for (i = 0; i < qdev->rx_ring_count; i++, buf++) {
357 ql_write32(qdev, INTR_EN,
358 qdev->intr_context[i].intr_read_mask);
359 *buf = ql_read32(qdev, INTR_EN);
360 }
361}
362
363static int ql_get_cam_entries(struct ql_adapter *qdev, u32 * buf)
364{
365 int i, status;
366 u32 value[3];
367
368 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
369 if (status)
370 return status;
371
372 for (i = 0; i < 16; i++) {
373 status = ql_get_mac_addr_reg(qdev,
374 MAC_ADDR_TYPE_CAM_MAC, i, value);
375 if (status) {
376 QPRINTK(qdev, DRV, ERR,
377 "Failed read of mac index register.\n");
378 goto err;
379 }
380 *buf++ = value[0]; /* lower MAC address */
381 *buf++ = value[1]; /* upper MAC address */
382 *buf++ = value[2]; /* output */
383 }
384 for (i = 0; i < 32; i++) {
385 status = ql_get_mac_addr_reg(qdev,
386 MAC_ADDR_TYPE_MULTI_MAC, i, value);
387 if (status) {
388 QPRINTK(qdev, DRV, ERR,
389 "Failed read of mac index register.\n");
390 goto err;
391 }
392 *buf++ = value[0]; /* lower Mcast address */
393 *buf++ = value[1]; /* upper Mcast address */
394 }
395err:
396 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
397 return status;
398}
399
400static int ql_get_routing_entries(struct ql_adapter *qdev, u32 * buf)
401{
402 int status;
403 u32 value, i;
404
405 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
406 if (status)
407 return status;
408
409 for (i = 0; i < 16; i++) {
410 status = ql_get_routing_reg(qdev, i, &value);
411 if (status) {
412 QPRINTK(qdev, DRV, ERR,
413 "Failed read of routing index register.\n");
414 goto err;
415 } else {
416 *buf++ = value;
417 }
418 }
419err:
420 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
421 return status;
422}
423
8aae2600
RM		 424/* Read the MPI Processor shadow registers */
425static int ql_get_mpi_shadow_regs(struct ql_adapter *qdev, u32 * buf)
426{
427 u32 i;
428 int status;
429
430 for (i = 0; i < MPI_CORE_SH_REGS_CNT; i++, buf++) {
431 status = ql_write_mpi_reg(qdev, RISC_124,
432 (SHADOW_OFFSET | i << SHADOW_REG_SHIFT));
433 if (status)
434 goto end;
435 status = ql_read_mpi_reg(qdev, RISC_127, buf);
436 if (status)
437 goto end;
438 }
439end:
440 return status;
441}
442
443/* Read the MPI Processor core registers */
444static int ql_get_mpi_regs(struct ql_adapter *qdev, u32 * buf,
445 u32 offset, u32 count)
446{
447 int i, status = 0;
448 for (i = 0; i < count; i++, buf++) {
449 status = ql_read_mpi_reg(qdev, offset + i, buf);
450 if (status)
451 return status;
452 }
453 return status;
454}
455
c89ec8b9
RM		 456/* Read the ASIC probe dump */
457static unsigned int *ql_get_probe(struct ql_adapter *qdev, u32 clock,
458 u32 valid, u32 *buf)
459{
460 u32 module, mux_sel, probe, lo_val, hi_val;
461
462 for (module = 0; module < PRB_MX_ADDR_MAX_MODS; module++) {
463 if (!((valid >> module) & 1))
464 continue;
465 for (mux_sel = 0; mux_sel < PRB_MX_ADDR_MAX_MUX; mux_sel++) {
466 probe = clock
467 | PRB_MX_ADDR_ARE
468 | mux_sel
469 | (module << PRB_MX_ADDR_MOD_SEL_SHIFT);
470 ql_write32(qdev, PRB_MX_ADDR, probe);
471 lo_val = ql_read32(qdev, PRB_MX_DATA);
472 if (mux_sel == 0) {
473 *buf = probe;
474 buf++;
475 }
476 probe |= PRB_MX_ADDR_UP;
477 ql_write32(qdev, PRB_MX_ADDR, probe);
478 hi_val = ql_read32(qdev, PRB_MX_DATA);
479 *buf = lo_val;
480 buf++;
481 *buf = hi_val;
482 buf++;
483 }
484 }
485 return buf;
486}
487
488static int ql_get_probe_dump(struct ql_adapter *qdev, unsigned int *buf)
489{
490 /* First we have to enable the probe mux */
491 ql_write_mpi_reg(qdev, MPI_TEST_FUNC_PRB_CTL, MPI_TEST_FUNC_PRB_EN);
492 buf = ql_get_probe(qdev, PRB_MX_ADDR_SYS_CLOCK,
493 PRB_MX_ADDR_VALID_SYS_MOD, buf);
494 buf = ql_get_probe(qdev, PRB_MX_ADDR_PCI_CLOCK,
495 PRB_MX_ADDR_VALID_PCI_MOD, buf);
496 buf = ql_get_probe(qdev, PRB_MX_ADDR_XGM_CLOCK,
497 PRB_MX_ADDR_VALID_XGM_MOD, buf);
498 buf = ql_get_probe(qdev, PRB_MX_ADDR_FC_CLOCK,
499 PRB_MX_ADDR_VALID_FC_MOD, buf);
500 return 0;
501
502}
8aae2600
RM		 503
504/* Read out the routing index registers */
505static int ql_get_routing_index_registers(struct ql_adapter *qdev, u32 *buf)
506{
507 int status;
508 u32 type, index, index_max;
509 u32 result_index;
510 u32 result_data;
511 u32 val;
512
513 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
514 if (status)
515 return status;
516
517 for (type = 0; type < 4; type++) {
518 if (type < 2)
519 index_max = 8;
520 else
521 index_max = 16;
522 for (index = 0; index < index_max; index++) {
523 val = RT_IDX_RS
524 | (type << RT_IDX_TYPE_SHIFT)
525 | (index << RT_IDX_IDX_SHIFT);
526 ql_write32(qdev, RT_IDX, val);
527 result_index = 0;
528 while ((result_index & RT_IDX_MR) == 0)
529 result_index = ql_read32(qdev, RT_IDX);
530 result_data = ql_read32(qdev, RT_DATA);
531 *buf = type;
532 buf++;
533 *buf = index;
534 buf++;
535 *buf = result_index;
536 buf++;
537 *buf = result_data;
538 buf++;
539 }
540 }
541 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
542 return status;
543}
544
545/* Read out the MAC protocol registers */
546static void ql_get_mac_protocol_registers(struct ql_adapter *qdev, u32 *buf)
547{
548 u32 result_index, result_data;
549 u32 type;
550 u32 index;
551 u32 offset;
552 u32 val;
553 u32 initial_val = MAC_ADDR_RS;
554 u32 max_index;
555 u32 max_offset;
556
557 for (type = 0; type < MAC_ADDR_TYPE_COUNT; type++) {
558 switch (type) {
559
560 case 0: /* CAM */
561 initial_val |= MAC_ADDR_ADR;
562 max_index = MAC_ADDR_MAX_CAM_ENTRIES;
563 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
564 break;
565 case 1: /* Multicast MAC Address */
566 max_index = MAC_ADDR_MAX_CAM_WCOUNT;
567 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
568 break;
569 case 2: /* VLAN filter mask */
570 case 3: /* MC filter mask */
571 max_index = MAC_ADDR_MAX_CAM_WCOUNT;
572 max_offset = MAC_ADDR_MAX_CAM_WCOUNT;
573 break;
574 case 4: /* FC MAC addresses */
575 max_index = MAC_ADDR_MAX_FC_MAC_ENTRIES;
576 max_offset = MAC_ADDR_MAX_FC_MAC_WCOUNT;
577 break;
578 case 5: /* Mgmt MAC addresses */
579 max_index = MAC_ADDR_MAX_MGMT_MAC_ENTRIES;
580 max_offset = MAC_ADDR_MAX_MGMT_MAC_WCOUNT;
581 break;
582 case 6: /* Mgmt VLAN addresses */
583 max_index = MAC_ADDR_MAX_MGMT_VLAN_ENTRIES;
584 max_offset = MAC_ADDR_MAX_MGMT_VLAN_WCOUNT;
585 break;
586 case 7: /* Mgmt IPv4 address */
587 max_index = MAC_ADDR_MAX_MGMT_V4_ENTRIES;
588 max_offset = MAC_ADDR_MAX_MGMT_V4_WCOUNT;
589 break;
590 case 8: /* Mgmt IPv6 address */
591 max_index = MAC_ADDR_MAX_MGMT_V6_ENTRIES;
592 max_offset = MAC_ADDR_MAX_MGMT_V6_WCOUNT;
593 break;
594 case 9: /* Mgmt TCP/UDP Dest port */
595 max_index = MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES;
596 max_offset = MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT;
597 break;
598 default:
599 printk(KERN_ERR"Bad type!!! 0x%08x\n", type);
600 max_index = 0;
601 max_offset = 0;
602 break;
603 }
604 for (index = 0; index < max_index; index++) {
605 for (offset = 0; offset < max_offset; offset++) {
606 val = initial_val
607 | (type << MAC_ADDR_TYPE_SHIFT)
608 | (index << MAC_ADDR_IDX_SHIFT)
609 | (offset);
610 ql_write32(qdev, MAC_ADDR_IDX, val);
611 result_index = 0;
612 while ((result_index & MAC_ADDR_MR) == 0) {
613 result_index = ql_read32(qdev,
614 MAC_ADDR_IDX);
615 }
616 result_data = ql_read32(qdev, MAC_ADDR_DATA);
617 *buf = result_index;
618 buf++;
619 *buf = result_data;
620 buf++;
621 }
622 }
623 }
624}
625
626static void ql_get_sem_registers(struct ql_adapter *qdev, u32 *buf)
627{
628 u32 func_num, reg, reg_val;
629 int status;
630
631 for (func_num = 0; func_num < MAX_SEMAPHORE_FUNCTIONS ; func_num++) {
632 reg = MPI_NIC_REG_BLOCK
633 | (func_num << MPI_NIC_FUNCTION_SHIFT)
634 | (SEM / 4);
635 status = ql_read_mpi_reg(qdev, reg, &reg_val);
636 *buf = reg_val;
637 /* if the read failed then dead fill the element. */
638 if (!status)
639 *buf = 0xdeadbeef;
640 buf++;
641 }
642}
643
a61f8026
RM		 644/* Create a coredump segment header */
645static void ql_build_coredump_seg_header(
646 struct mpi_coredump_segment_header *seg_hdr,
647 u32 seg_number, u32 seg_size, u8 *desc)
648{
649 memset(seg_hdr, 0, sizeof(struct mpi_coredump_segment_header));
650 seg_hdr->cookie = MPI_COREDUMP_COOKIE;
651 seg_hdr->segNum = seg_number;
652 seg_hdr->segSize = seg_size;
653 memcpy(seg_hdr->description, desc, (sizeof(seg_hdr->description)) - 1);
654}
655
8aae2600
RM		 656/*
657 * This function should be called when a coredump / probedump
658 * is to be extracted from the HBA. It is assumed there is a
659 * qdev structure that contains the base address of the register
660 * space for this function as well as a coredump structure that
661 * will contain the dump.
662 */
663int ql_core_dump(struct ql_adapter *qdev, struct ql_mpi_coredump *mpi_coredump)
664{
665 int status;
666 int i;
667
668 if (!mpi_coredump) {
669 QPRINTK(qdev, DRV, ERR,
670 "No memory available.\n");
671 return -ENOMEM;
672 }
673
674 /* Try to get the spinlock, but dont worry if
675 * it isn't available. If the firmware died it
676 * might be holding the sem.
677 */
678 ql_sem_spinlock(qdev, SEM_PROC_REG_MASK);
679
680 status = ql_pause_mpi_risc(qdev);
681 if (status) {
682 QPRINTK(qdev, DRV, ERR,
683 "Failed RISC pause. Status = 0x%.08x\n", status);
684 goto err;
685 }
686
687 /* Insert the global header */
688 memset(&(mpi_coredump->mpi_global_header), 0,
689 sizeof(struct mpi_coredump_global_header));
690 mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
691 mpi_coredump->mpi_global_header.headerSize =
692 sizeof(struct mpi_coredump_global_header);
693 mpi_coredump->mpi_global_header.imageSize =
694 sizeof(struct ql_mpi_coredump);
695 memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump",
696 sizeof(mpi_coredump->mpi_global_header.idString));
697
698 /* Get generic NIC reg dump */
699 ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
700 NIC1_CONTROL_SEG_NUM,
701 sizeof(struct mpi_coredump_segment_header) +
702 sizeof(mpi_coredump->nic_regs), "NIC1 Registers");
703
24bb55b4
RM		 704 ql_build_coredump_seg_header(&mpi_coredump->nic2_regs_seg_hdr,
705 NIC2_CONTROL_SEG_NUM,
706 sizeof(struct mpi_coredump_segment_header) +
707 sizeof(mpi_coredump->nic2_regs), "NIC2 Registers");
708
8aae2600
RM		 709 if (qdev->func & 1) {
710 /* Odd means our function is NIC 2 */
711 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
712 mpi_coredump->nic2_regs[i] =
713 ql_read32(qdev, i * sizeof(u32));
24bb55b4
RM		 714
715 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
716 mpi_coredump->nic_regs[i] =
717 ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
8aae2600
RM		 718 } else {
719 /* Even means our function is NIC 1 */
720 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
721 mpi_coredump->nic_regs[i] =
722 ql_read32(qdev, i * sizeof(u32));
24bb55b4
RM		 723 for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++)
724 mpi_coredump->nic2_regs[i] =
725 ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4);
8aae2600
RM		 726 }
727
a48c86fd
RM		 728 /* Rev C. Step 20a */
729 ql_build_coredump_seg_header(&mpi_coredump->xaui_an_hdr,
730 XAUI_AN_SEG_NUM,
731 sizeof(struct mpi_coredump_segment_header) +
732 sizeof(mpi_coredump->serdes_xaui_an),
733 "XAUI AN Registers");
734
735 /* Rev C. Step 20b */
736 ql_build_coredump_seg_header(&mpi_coredump->xaui_hss_pcs_hdr,
737 XAUI_HSS_PCS_SEG_NUM,
738 sizeof(struct mpi_coredump_segment_header) +
739 sizeof(mpi_coredump->serdes_xaui_hss_pcs),
740 "XAUI HSS PCS Registers");
741
742 ql_build_coredump_seg_header(&mpi_coredump->xfi_an_hdr, XFI_AN_SEG_NUM,
743 sizeof(struct mpi_coredump_segment_header) +
744 sizeof(mpi_coredump->serdes_xfi_an),
745 "XFI AN Registers");
746
747 ql_build_coredump_seg_header(&mpi_coredump->xfi_train_hdr,
748 XFI_TRAIN_SEG_NUM,
749 sizeof(struct mpi_coredump_segment_header) +
750 sizeof(mpi_coredump->serdes_xfi_train),
751 "XFI TRAIN Registers");
752
753 ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pcs_hdr,
754 XFI_HSS_PCS_SEG_NUM,
755 sizeof(struct mpi_coredump_segment_header) +
756 sizeof(mpi_coredump->serdes_xfi_hss_pcs),
757 "XFI HSS PCS Registers");
758
759 ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_tx_hdr,
760 XFI_HSS_TX_SEG_NUM,
761 sizeof(struct mpi_coredump_segment_header) +
762 sizeof(mpi_coredump->serdes_xfi_hss_tx),
763 "XFI HSS TX Registers");
764
765 ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_rx_hdr,
766 XFI_HSS_RX_SEG_NUM,
767 sizeof(struct mpi_coredump_segment_header) +
768 sizeof(mpi_coredump->serdes_xfi_hss_rx),
769 "XFI HSS RX Registers");
770
771 ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pll_hdr,
772 XFI_HSS_PLL_SEG_NUM,
773 sizeof(struct mpi_coredump_segment_header) +
774 sizeof(mpi_coredump->serdes_xfi_hss_pll),
775 "XFI HSS PLL Registers");
776
777 ql_build_coredump_seg_header(&mpi_coredump->xaui2_an_hdr,
778 XAUI2_AN_SEG_NUM,
779 sizeof(struct mpi_coredump_segment_header) +
780 sizeof(mpi_coredump->serdes2_xaui_an),
781 "XAUI2 AN Registers");
782
783 ql_build_coredump_seg_header(&mpi_coredump->xaui2_hss_pcs_hdr,
784 XAUI2_HSS_PCS_SEG_NUM,
785 sizeof(struct mpi_coredump_segment_header) +
786 sizeof(mpi_coredump->serdes2_xaui_hss_pcs),
787 "XAUI2 HSS PCS Registers");
788
789 ql_build_coredump_seg_header(&mpi_coredump->xfi2_an_hdr,
790 XFI2_AN_SEG_NUM,
791 sizeof(struct mpi_coredump_segment_header) +
792 sizeof(mpi_coredump->serdes2_xfi_an),
793 "XFI2 AN Registers");
794
795 ql_build_coredump_seg_header(&mpi_coredump->xfi2_train_hdr,
796 XFI2_TRAIN_SEG_NUM,
797 sizeof(struct mpi_coredump_segment_header) +
798 sizeof(mpi_coredump->serdes2_xfi_train),
799 "XFI2 TRAIN Registers");
800
801 ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pcs_hdr,
802 XFI2_HSS_PCS_SEG_NUM,
803 sizeof(struct mpi_coredump_segment_header) +
804 sizeof(mpi_coredump->serdes2_xfi_hss_pcs),
805 "XFI2 HSS PCS Registers");
806
807 ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_tx_hdr,
808 XFI2_HSS_TX_SEG_NUM,
809 sizeof(struct mpi_coredump_segment_header) +
810 sizeof(mpi_coredump->serdes2_xfi_hss_tx),
811 "XFI2 HSS TX Registers");
812
813 ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_rx_hdr,
814 XFI2_HSS_RX_SEG_NUM,
815 sizeof(struct mpi_coredump_segment_header) +
816 sizeof(mpi_coredump->serdes2_xfi_hss_rx),
817 "XFI2 HSS RX Registers");
818
819 ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pll_hdr,
820 XFI2_HSS_PLL_SEG_NUM,
821 sizeof(struct mpi_coredump_segment_header) +
822 sizeof(mpi_coredump->serdes2_xfi_hss_pll),
823 "XFI2 HSS PLL Registers");
824
825 status = ql_get_serdes_regs(qdev, mpi_coredump);
826 if (status) {
827 QPRINTK(qdev, DRV, ERR,
828 "Failed Dump of Serdes Registers. Status = 0x%.08x\n",
829 status);
830 goto err;
831 }
832
8aae2600
RM		 833 ql_build_coredump_seg_header(&mpi_coredump->core_regs_seg_hdr,
834 CORE_SEG_NUM,
835 sizeof(mpi_coredump->core_regs_seg_hdr) +
836 sizeof(mpi_coredump->mpi_core_regs) +
837 sizeof(mpi_coredump->mpi_core_sh_regs),
838 "Core Registers");
839
840 /* Get the MPI Core Registers */
841 status = ql_get_mpi_regs(qdev, &mpi_coredump->mpi_core_regs[0],
842 MPI_CORE_REGS_ADDR, MPI_CORE_REGS_CNT);
843 if (status)
844 goto err;
845 /* Get the 16 MPI shadow registers */
846 status = ql_get_mpi_shadow_regs(qdev,
847 &mpi_coredump->mpi_core_sh_regs[0]);
848 if (status)
849 goto err;
850
851 /* Get the Test Logic Registers */
852 ql_build_coredump_seg_header(&mpi_coredump->test_logic_regs_seg_hdr,
853 TEST_LOGIC_SEG_NUM,
854 sizeof(struct mpi_coredump_segment_header)
855 + sizeof(mpi_coredump->test_logic_regs),
856 "Test Logic Regs");
857 status = ql_get_mpi_regs(qdev, &mpi_coredump->test_logic_regs[0],
858 TEST_REGS_ADDR, TEST_REGS_CNT);
859 if (status)
860 goto err;
861
862 /* Get the RMII Registers */
863 ql_build_coredump_seg_header(&mpi_coredump->rmii_regs_seg_hdr,
864 RMII_SEG_NUM,
865 sizeof(struct mpi_coredump_segment_header)
866 + sizeof(mpi_coredump->rmii_regs),
867 "RMII Registers");
868 status = ql_get_mpi_regs(qdev, &mpi_coredump->rmii_regs[0],
869 RMII_REGS_ADDR, RMII_REGS_CNT);
870 if (status)
871 goto err;
872
873 /* Get the FCMAC1 Registers */
874 ql_build_coredump_seg_header(&mpi_coredump->fcmac1_regs_seg_hdr,
875 FCMAC1_SEG_NUM,
876 sizeof(struct mpi_coredump_segment_header)
877 + sizeof(mpi_coredump->fcmac1_regs),
878 "FCMAC1 Registers");
879 status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac1_regs[0],
880 FCMAC1_REGS_ADDR, FCMAC_REGS_CNT);
881 if (status)
882 goto err;
883
884 /* Get the FCMAC2 Registers */
885
886 ql_build_coredump_seg_header(&mpi_coredump->fcmac2_regs_seg_hdr,
887 FCMAC2_SEG_NUM,
888 sizeof(struct mpi_coredump_segment_header)
889 + sizeof(mpi_coredump->fcmac2_regs),
890 "FCMAC2 Registers");
891
892 status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac2_regs[0],
893 FCMAC2_REGS_ADDR, FCMAC_REGS_CNT);
894 if (status)
895 goto err;
896
897 /* Get the FC1 MBX Registers */
898 ql_build_coredump_seg_header(&mpi_coredump->fc1_mbx_regs_seg_hdr,
899 FC1_MBOX_SEG_NUM,
900 sizeof(struct mpi_coredump_segment_header)
901 + sizeof(mpi_coredump->fc1_mbx_regs),
902 "FC1 MBox Regs");
903 status = ql_get_mpi_regs(qdev, &mpi_coredump->fc1_mbx_regs[0],
904 FC1_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
905 if (status)
906 goto err;
907
908 /* Get the IDE Registers */
909 ql_build_coredump_seg_header(&mpi_coredump->ide_regs_seg_hdr,
910 IDE_SEG_NUM,
911 sizeof(struct mpi_coredump_segment_header)
912 + sizeof(mpi_coredump->ide_regs),
913 "IDE Registers");
914 status = ql_get_mpi_regs(qdev, &mpi_coredump->ide_regs[0],
915 IDE_REGS_ADDR, IDE_REGS_CNT);
916 if (status)
917 goto err;
918
919 /* Get the NIC1 MBX Registers */
920 ql_build_coredump_seg_header(&mpi_coredump->nic1_mbx_regs_seg_hdr,
921 NIC1_MBOX_SEG_NUM,
922 sizeof(struct mpi_coredump_segment_header)
923 + sizeof(mpi_coredump->nic1_mbx_regs),
924 "NIC1 MBox Regs");
925 status = ql_get_mpi_regs(qdev, &mpi_coredump->nic1_mbx_regs[0],
926 NIC1_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
927 if (status)
928 goto err;
929
930 /* Get the SMBus Registers */
931 ql_build_coredump_seg_header(&mpi_coredump->smbus_regs_seg_hdr,
932 SMBUS_SEG_NUM,
933 sizeof(struct mpi_coredump_segment_header)
934 + sizeof(mpi_coredump->smbus_regs),
935 "SMBus Registers");
936 status = ql_get_mpi_regs(qdev, &mpi_coredump->smbus_regs[0],
937 SMBUS_REGS_ADDR, SMBUS_REGS_CNT);
938 if (status)
939 goto err;
940
941 /* Get the FC2 MBX Registers */
942 ql_build_coredump_seg_header(&mpi_coredump->fc2_mbx_regs_seg_hdr,
943 FC2_MBOX_SEG_NUM,
944 sizeof(struct mpi_coredump_segment_header)
945 + sizeof(mpi_coredump->fc2_mbx_regs),
946 "FC2 MBox Regs");
947 status = ql_get_mpi_regs(qdev, &mpi_coredump->fc2_mbx_regs[0],
948 FC2_MBX_REGS_ADDR, FC_MBX_REGS_CNT);
949 if (status)
950 goto err;
951
952 /* Get the NIC2 MBX Registers */
953 ql_build_coredump_seg_header(&mpi_coredump->nic2_mbx_regs_seg_hdr,
954 NIC2_MBOX_SEG_NUM,
955 sizeof(struct mpi_coredump_segment_header)
956 + sizeof(mpi_coredump->nic2_mbx_regs),
957 "NIC2 MBox Regs");
958 status = ql_get_mpi_regs(qdev, &mpi_coredump->nic2_mbx_regs[0],
959 NIC2_MBX_REGS_ADDR, NIC_MBX_REGS_CNT);
960 if (status)
961 goto err;
962
963 /* Get the I2C Registers */
964 ql_build_coredump_seg_header(&mpi_coredump->i2c_regs_seg_hdr,
965 I2C_SEG_NUM,
966 sizeof(struct mpi_coredump_segment_header)
967 + sizeof(mpi_coredump->i2c_regs),
968 "I2C Registers");
969 status = ql_get_mpi_regs(qdev, &mpi_coredump->i2c_regs[0],
970 I2C_REGS_ADDR, I2C_REGS_CNT);
971 if (status)
972 goto err;
973
974 /* Get the MEMC Registers */
975 ql_build_coredump_seg_header(&mpi_coredump->memc_regs_seg_hdr,
976 MEMC_SEG_NUM,
977 sizeof(struct mpi_coredump_segment_header)
978 + sizeof(mpi_coredump->memc_regs),
979 "MEMC Registers");
980 status = ql_get_mpi_regs(qdev, &mpi_coredump->memc_regs[0],
981 MEMC_REGS_ADDR, MEMC_REGS_CNT);
982 if (status)
983 goto err;
984
985 /* Get the PBus Registers */
986 ql_build_coredump_seg_header(&mpi_coredump->pbus_regs_seg_hdr,
987 PBUS_SEG_NUM,
988 sizeof(struct mpi_coredump_segment_header)
989 + sizeof(mpi_coredump->pbus_regs),
990 "PBUS Registers");
991 status = ql_get_mpi_regs(qdev, &mpi_coredump->pbus_regs[0],
992 PBUS_REGS_ADDR, PBUS_REGS_CNT);
993 if (status)
994 goto err;
995
996 /* Get the MDE Registers */
997 ql_build_coredump_seg_header(&mpi_coredump->mde_regs_seg_hdr,
998 MDE_SEG_NUM,
999 sizeof(struct mpi_coredump_segment_header)
1000 + sizeof(mpi_coredump->mde_regs),
1001 "MDE Registers");
1002 status = ql_get_mpi_regs(qdev, &mpi_coredump->mde_regs[0],
1003 MDE_REGS_ADDR, MDE_REGS_CNT);
1004 if (status)
1005 goto err;
1006
1007 ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
1008 MISC_NIC_INFO_SEG_NUM,
1009 sizeof(struct mpi_coredump_segment_header)
1010 + sizeof(mpi_coredump->misc_nic_info),
1011 "MISC NIC INFO");
1012 mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
1013 mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
1014 mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
1015 mpi_coredump->misc_nic_info.function = qdev->func;
1016
1017 /* Segment 31 */
1018 /* Get indexed register values. */
1019 ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
1020 INTR_STATES_SEG_NUM,
1021 sizeof(struct mpi_coredump_segment_header)
1022 + sizeof(mpi_coredump->intr_states),
1023 "INTR States");
1024 ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
1025
1026 ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
1027 CAM_ENTRIES_SEG_NUM,
1028 sizeof(struct mpi_coredump_segment_header)
1029 + sizeof(mpi_coredump->cam_entries),
1030 "CAM Entries");
1031 status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
1032 if (status)
1033 goto err;
1034
1035 ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
1036 ROUTING_WORDS_SEG_NUM,
1037 sizeof(struct mpi_coredump_segment_header)
1038 + sizeof(mpi_coredump->nic_routing_words),
1039 "Routing Words");
1040 status = ql_get_routing_entries(qdev,
1041 &mpi_coredump->nic_routing_words[0]);
1042 if (status)
1043 goto err;
1044
1045 /* Segment 34 (Rev C. step 23) */
1046 ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
1047 ETS_SEG_NUM,
1048 sizeof(struct mpi_coredump_segment_header)
1049 + sizeof(mpi_coredump->ets),
1050 "ETS Registers");
1051 status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
1052 if (status)
1053 goto err;
1054
c89ec8b9
RM		 1055 ql_build_coredump_seg_header(&mpi_coredump->probe_dump_seg_hdr,
1056 PROBE_DUMP_SEG_NUM,
1057 sizeof(struct mpi_coredump_segment_header)
1058 + sizeof(mpi_coredump->probe_dump),
1059 "Probe Dump");
1060 ql_get_probe_dump(qdev, &mpi_coredump->probe_dump[0]);
1061
8aae2600
RM		 1062 ql_build_coredump_seg_header(&mpi_coredump->routing_reg_seg_hdr,
1063 ROUTING_INDEX_SEG_NUM,
1064 sizeof(struct mpi_coredump_segment_header)
1065 + sizeof(mpi_coredump->routing_regs),
1066 "Routing Regs");
1067 status = ql_get_routing_index_registers(qdev,
1068 &mpi_coredump->routing_regs[0]);
1069 if (status)
1070 goto err;
1071
1072 ql_build_coredump_seg_header(&mpi_coredump->mac_prot_reg_seg_hdr,
1073 MAC_PROTOCOL_SEG_NUM,
1074 sizeof(struct mpi_coredump_segment_header)
1075 + sizeof(mpi_coredump->mac_prot_regs),
1076 "MAC Prot Regs");
1077 ql_get_mac_protocol_registers(qdev, &mpi_coredump->mac_prot_regs[0]);
1078
1079 /* Get the semaphore registers for all 5 functions */
1080 ql_build_coredump_seg_header(&mpi_coredump->sem_regs_seg_hdr,
1081 SEM_REGS_SEG_NUM,
1082 sizeof(struct mpi_coredump_segment_header) +
1083 sizeof(mpi_coredump->sem_regs), "Sem Registers");
1084
1085 ql_get_sem_registers(qdev, &mpi_coredump->sem_regs[0]);
1086
1087 /* Prevent the mpi restarting while we dump the memory.*/
1088 ql_write_mpi_reg(qdev, MPI_TEST_FUNC_RST_STS, MPI_TEST_FUNC_RST_FRC);
1089
1090 /* clear the pause */
1091 status = ql_unpause_mpi_risc(qdev);
1092 if (status) {
1093 QPRINTK(qdev, DRV, ERR,
1094 "Failed RISC unpause. Status = 0x%.08x\n", status);
1095 goto err;
1096 }
2c1f73c3
RM		 1097
1098 /* Reset the RISC so we can dump RAM */
1099 status = ql_hard_reset_mpi_risc(qdev);
1100 if (status) {
1101 QPRINTK(qdev, DRV, ERR,
1102 "Failed RISC reset. Status = 0x%.08x\n", status);
1103 goto err;
1104 }
1105
1106 ql_build_coredump_seg_header(&mpi_coredump->code_ram_seg_hdr,
1107 WCS_RAM_SEG_NUM,
1108 sizeof(struct mpi_coredump_segment_header)
1109 + sizeof(mpi_coredump->code_ram),
1110 "WCS RAM");
1111 status = ql_dump_risc_ram_area(qdev, &mpi_coredump->code_ram[0],
1112 CODE_RAM_ADDR, CODE_RAM_CNT);
1113 if (status) {
1114 QPRINTK(qdev, DRV, ERR,
1115 "Failed Dump of CODE RAM. Status = 0x%.08x\n", status);
1116 goto err;
1117 }
1118
1119 /* Insert the segment header */
1120 ql_build_coredump_seg_header(&mpi_coredump->memc_ram_seg_hdr,
1121 MEMC_RAM_SEG_NUM,
1122 sizeof(struct mpi_coredump_segment_header)
1123 + sizeof(mpi_coredump->memc_ram),
1124 "MEMC RAM");
1125 status = ql_dump_risc_ram_area(qdev, &mpi_coredump->memc_ram[0],
1126 MEMC_RAM_ADDR, MEMC_RAM_CNT);
1127 if (status) {
1128 QPRINTK(qdev, DRV, ERR,
1129 "Failed Dump of MEMC RAM. Status = 0x%.08x\n", status);
1130 goto err;
1131 }
8aae2600
RM		 1132err:
1133 ql_sem_unlock(qdev, SEM_PROC_REG_MASK); /* does flush too */
1134 return status;
1135
1136}
1137
a61f8026
RM		 1138void ql_gen_reg_dump(struct ql_adapter *qdev,
1139 struct ql_reg_dump *mpi_coredump)
1140{
1141 int i, status;
1142
1143
1144 memset(&(mpi_coredump->mpi_global_header), 0,
1145 sizeof(struct mpi_coredump_global_header));
1146 mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE;
1147 mpi_coredump->mpi_global_header.headerSize =
1148 sizeof(struct mpi_coredump_global_header);
1149 mpi_coredump->mpi_global_header.imageSize =
1150 sizeof(struct ql_reg_dump);
1151 memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump",
1152 sizeof(mpi_coredump->mpi_global_header.idString));
1153
1154
1155 /* segment 16 */
1156 ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr,
1157 MISC_NIC_INFO_SEG_NUM,
1158 sizeof(struct mpi_coredump_segment_header)
1159 + sizeof(mpi_coredump->misc_nic_info),
1160 "MISC NIC INFO");
1161 mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count;
1162 mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count;
1163 mpi_coredump->misc_nic_info.intr_count = qdev->intr_count;
1164 mpi_coredump->misc_nic_info.function = qdev->func;
1165
1166 /* Segment 16, Rev C. Step 18 */
1167 ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr,
1168 NIC1_CONTROL_SEG_NUM,
1169 sizeof(struct mpi_coredump_segment_header)
1170 + sizeof(mpi_coredump->nic_regs),
1171 "NIC Registers");
1172 /* Get generic reg dump */
1173 for (i = 0; i < 64; i++)
1174 mpi_coredump->nic_regs[i] = ql_read32(qdev, i * sizeof(u32));
1175
1176 /* Segment 31 */
1177 /* Get indexed register values. */
1178 ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr,
1179 INTR_STATES_SEG_NUM,
1180 sizeof(struct mpi_coredump_segment_header)
1181 + sizeof(mpi_coredump->intr_states),
1182 "INTR States");
1183 ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]);
1184
1185 ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr,
1186 CAM_ENTRIES_SEG_NUM,
1187 sizeof(struct mpi_coredump_segment_header)
1188 + sizeof(mpi_coredump->cam_entries),
1189 "CAM Entries");
1190 status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]);
1191 if (status)
1192 return;
1193
1194 ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr,
1195 ROUTING_WORDS_SEG_NUM,
1196 sizeof(struct mpi_coredump_segment_header)
1197 + sizeof(mpi_coredump->nic_routing_words),
1198 "Routing Words");
1199 status = ql_get_routing_entries(qdev,
1200 &mpi_coredump->nic_routing_words[0]);
1201 if (status)
1202 return;
1203
1204 /* Segment 34 (Rev C. step 23) */
1205 ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr,
1206 ETS_SEG_NUM,
1207 sizeof(struct mpi_coredump_segment_header)
1208 + sizeof(mpi_coredump->ets),
1209 "ETS Registers");
1210 status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]);
1211 if (status)
1212 return;
1213}
1214
8aae2600
RM		 1215/* Coredump to messages log file using separate worker thread */
1216void ql_mpi_core_to_log(struct work_struct *work)
1217{
1218 struct ql_adapter *qdev =
1219 container_of(work, struct ql_adapter, mpi_core_to_log.work);
1220 u32 *tmp, count;
1221 int i;
1222
1223 count = sizeof(struct ql_mpi_coredump) / sizeof(u32);
1224 tmp = (u32 *)qdev->mpi_coredump;
1225 QPRINTK(qdev, DRV, DEBUG, "Core is dumping to log file!\n");
1226
1227 for (i = 0; i < count; i += 8) {
1228 printk(KERN_ERR "%.08x: %.08x %.08x %.08x %.08x %.08x "
1229 "%.08x %.08x %.08x \n", i,
1230 tmp[i + 0],
1231 tmp[i + 1],
1232 tmp[i + 2],
1233 tmp[i + 3],
1234 tmp[i + 4],
1235 tmp[i + 5],
1236 tmp[i + 6],
1237 tmp[i + 7]);
1238 msleep(5);
1239 }
1240}
1241
c4e84bde
RM		 1242#ifdef QL_REG_DUMP
1243static void ql_dump_intr_states(struct ql_adapter *qdev)
1244{
1245 int i;
1246 u32 value;
1247 for (i = 0; i < qdev->intr_count; i++) {
1248 ql_write32(qdev, INTR_EN, qdev->intr_context[i].intr_read_mask);
1249 value = ql_read32(qdev, INTR_EN);
1250 printk(KERN_ERR PFX
1251 "%s: Interrupt %d is %s.\n",
1252 qdev->ndev->name, i,
1253 (value & INTR_EN_EN ? "enabled" : "disabled"));
1254 }
1255}
1256
1257void ql_dump_xgmac_control_regs(struct ql_adapter *qdev)
1258{
1259 u32 data;
1260 if (ql_sem_spinlock(qdev, qdev->xg_sem_mask)) {
1261 printk(KERN_ERR "%s: Couldn't get xgmac sem.\n", __func__);
1262 return;
1263 }
1264 ql_read_xgmac_reg(qdev, PAUSE_SRC_LO, &data);
1265 printk(KERN_ERR PFX "%s: PAUSE_SRC_LO = 0x%.08x.\n", qdev->ndev->name,
1266 data);
1267 ql_read_xgmac_reg(qdev, PAUSE_SRC_HI, &data);
1268 printk(KERN_ERR PFX "%s: PAUSE_SRC_HI = 0x%.08x.\n", qdev->ndev->name,
1269 data);
1270 ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
1271 printk(KERN_ERR PFX "%s: GLOBAL_CFG = 0x%.08x.\n", qdev->ndev->name,
1272 data);
1273 ql_read_xgmac_reg(qdev, TX_CFG, &data);
1274 printk(KERN_ERR PFX "%s: TX_CFG = 0x%.08x.\n", qdev->ndev->name, data);
1275 ql_read_xgmac_reg(qdev, RX_CFG, &data);
1276 printk(KERN_ERR PFX "%s: RX_CFG = 0x%.08x.\n", qdev->ndev->name, data);
1277 ql_read_xgmac_reg(qdev, FLOW_CTL, &data);
1278 printk(KERN_ERR PFX "%s: FLOW_CTL = 0x%.08x.\n", qdev->ndev->name,
1279 data);
1280 ql_read_xgmac_reg(qdev, PAUSE_OPCODE, &data);
1281 printk(KERN_ERR PFX "%s: PAUSE_OPCODE = 0x%.08x.\n", qdev->ndev->name,
1282 data);
1283 ql_read_xgmac_reg(qdev, PAUSE_TIMER, &data);
1284 printk(KERN_ERR PFX "%s: PAUSE_TIMER = 0x%.08x.\n", qdev->ndev->name,
1285 data);
1286 ql_read_xgmac_reg(qdev, PAUSE_FRM_DEST_LO, &data);
1287 printk(KERN_ERR PFX "%s: PAUSE_FRM_DEST_LO = 0x%.08x.\n",
1288 qdev->ndev->name, data);
1289 ql_read_xgmac_reg(qdev, PAUSE_FRM_DEST_HI, &data);
1290 printk(KERN_ERR PFX "%s: PAUSE_FRM_DEST_HI = 0x%.08x.\n",
1291 qdev->ndev->name, data);
1292 ql_read_xgmac_reg(qdev, MAC_TX_PARAMS, &data);
1293 printk(KERN_ERR PFX "%s: MAC_TX_PARAMS = 0x%.08x.\n", qdev->ndev->name,
1294 data);
1295 ql_read_xgmac_reg(qdev, MAC_RX_PARAMS, &data);
1296 printk(KERN_ERR PFX "%s: MAC_RX_PARAMS = 0x%.08x.\n", qdev->ndev->name,
1297 data);
1298 ql_read_xgmac_reg(qdev, MAC_SYS_INT, &data);
1299 printk(KERN_ERR PFX "%s: MAC_SYS_INT = 0x%.08x.\n", qdev->ndev->name,
1300 data);
1301 ql_read_xgmac_reg(qdev, MAC_SYS_INT_MASK, &data);
1302 printk(KERN_ERR PFX "%s: MAC_SYS_INT_MASK = 0x%.08x.\n",
1303 qdev->ndev->name, data);
1304 ql_read_xgmac_reg(qdev, MAC_MGMT_INT, &data);
1305 printk(KERN_ERR PFX "%s: MAC_MGMT_INT = 0x%.08x.\n", qdev->ndev->name,
1306 data);
1307 ql_read_xgmac_reg(qdev, MAC_MGMT_IN_MASK, &data);
1308 printk(KERN_ERR PFX "%s: MAC_MGMT_IN_MASK = 0x%.08x.\n",
1309 qdev->ndev->name, data);
1310 ql_read_xgmac_reg(qdev, EXT_ARB_MODE, &data);
1311 printk(KERN_ERR PFX "%s: EXT_ARB_MODE = 0x%.08x.\n", qdev->ndev->name,
1312 data);
1313 ql_sem_unlock(qdev, qdev->xg_sem_mask);
1314
1315}
1316
1317static void ql_dump_ets_regs(struct ql_adapter *qdev)
1318{
1319}
1320
1321static void ql_dump_cam_entries(struct ql_adapter *qdev)
1322{
1323 int i;
1324 u32 value[3];
cc288f54
RM		 1325
1326 i = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1327 if (i)
1328 return;
c4e84bde
RM		 1329 for (i = 0; i < 4; i++) {
1330 if (ql_get_mac_addr_reg(qdev, MAC_ADDR_TYPE_CAM_MAC, i, value)) {
1331 printk(KERN_ERR PFX
1332 "%s: Failed read of mac index register.\n",
1333 __func__);
1334 return;
1335 } else {
1336 if (value[0])
1337 printk(KERN_ERR PFX
1338 "%s: CAM index %d CAM Lookup Lower = 0x%.08x:%.08x, Output = 0x%.08x.\n",
1339 qdev->ndev->name, i, value[1], value[0],
1340 value[2]);
1341 }
1342 }
1343 for (i = 0; i < 32; i++) {
1344 if (ql_get_mac_addr_reg
1345 (qdev, MAC_ADDR_TYPE_MULTI_MAC, i, value)) {
1346 printk(KERN_ERR PFX
1347 "%s: Failed read of mac index register.\n",
1348 __func__);
1349 return;
1350 } else {
1351 if (value[0])
1352 printk(KERN_ERR PFX
1353 "%s: MCAST index %d CAM Lookup Lower = 0x%.08x:%.08x.\n",
1354 qdev->ndev->name, i, value[1], value[0]);
1355 }
1356 }
cc288f54 1357 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
c4e84bde
RM		 1358}
1359
1360void ql_dump_routing_entries(struct ql_adapter *qdev)
1361{
1362 int i;
1363 u32 value;
cc288f54
RM		 1364 i = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
1365 if (i)
1366 return;
c4e84bde
RM		 1367 for (i = 0; i < 16; i++) {
1368 value = 0;
1369 if (ql_get_routing_reg(qdev, i, &value)) {
1370 printk(KERN_ERR PFX
1371 "%s: Failed read of routing index register.\n",
1372 __func__);
1373 return;
1374 } else {
1375 if (value)
1376 printk(KERN_ERR PFX
1377 "%s: Routing Mask %d = 0x%.08x.\n",
1378 qdev->ndev->name, i, value);
1379 }
1380 }
cc288f54 1381 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
c4e84bde
RM		 1382}
1383
1384void ql_dump_regs(struct ql_adapter *qdev)
1385{
1386 printk(KERN_ERR PFX "reg dump for function #%d.\n", qdev->func);
1387 printk(KERN_ERR PFX "SYS = 0x%x.\n",
1388 ql_read32(qdev, SYS));
1389 printk(KERN_ERR PFX "RST_FO = 0x%x.\n",
1390 ql_read32(qdev, RST_FO));
1391 printk(KERN_ERR PFX "FSC = 0x%x.\n",
1392 ql_read32(qdev, FSC));
1393 printk(KERN_ERR PFX "CSR = 0x%x.\n",
1394 ql_read32(qdev, CSR));
1395 printk(KERN_ERR PFX "ICB_RID = 0x%x.\n",
1396 ql_read32(qdev, ICB_RID));
1397 printk(KERN_ERR PFX "ICB_L = 0x%x.\n",
1398 ql_read32(qdev, ICB_L));
1399 printk(KERN_ERR PFX "ICB_H = 0x%x.\n",
1400 ql_read32(qdev, ICB_H));
1401 printk(KERN_ERR PFX "CFG = 0x%x.\n",
1402 ql_read32(qdev, CFG));
1403 printk(KERN_ERR PFX "BIOS_ADDR = 0x%x.\n",
1404 ql_read32(qdev, BIOS_ADDR));
1405 printk(KERN_ERR PFX "STS = 0x%x.\n",
1406 ql_read32(qdev, STS));
1407 printk(KERN_ERR PFX "INTR_EN = 0x%x.\n",
1408 ql_read32(qdev, INTR_EN));
1409 printk(KERN_ERR PFX "INTR_MASK = 0x%x.\n",
1410 ql_read32(qdev, INTR_MASK));
1411 printk(KERN_ERR PFX "ISR1 = 0x%x.\n",
1412 ql_read32(qdev, ISR1));
1413 printk(KERN_ERR PFX "ISR2 = 0x%x.\n",
1414 ql_read32(qdev, ISR2));
1415 printk(KERN_ERR PFX "ISR3 = 0x%x.\n",
1416 ql_read32(qdev, ISR3));
1417 printk(KERN_ERR PFX "ISR4 = 0x%x.\n",
1418 ql_read32(qdev, ISR4));
1419 printk(KERN_ERR PFX "REV_ID = 0x%x.\n",
1420 ql_read32(qdev, REV_ID));
1421 printk(KERN_ERR PFX "FRC_ECC_ERR = 0x%x.\n",
1422 ql_read32(qdev, FRC_ECC_ERR));
1423 printk(KERN_ERR PFX "ERR_STS = 0x%x.\n",
1424 ql_read32(qdev, ERR_STS));
1425 printk(KERN_ERR PFX "RAM_DBG_ADDR = 0x%x.\n",
1426 ql_read32(qdev, RAM_DBG_ADDR));
1427 printk(KERN_ERR PFX "RAM_DBG_DATA = 0x%x.\n",
1428 ql_read32(qdev, RAM_DBG_DATA));
1429 printk(KERN_ERR PFX "ECC_ERR_CNT = 0x%x.\n",
1430 ql_read32(qdev, ECC_ERR_CNT));
1431 printk(KERN_ERR PFX "SEM = 0x%x.\n",
1432 ql_read32(qdev, SEM));
1433 printk(KERN_ERR PFX "GPIO_1 = 0x%x.\n",
1434 ql_read32(qdev, GPIO_1));
1435 printk(KERN_ERR PFX "GPIO_2 = 0x%x.\n",
1436 ql_read32(qdev, GPIO_2));
1437 printk(KERN_ERR PFX "GPIO_3 = 0x%x.\n",
1438 ql_read32(qdev, GPIO_3));
1439 printk(KERN_ERR PFX "XGMAC_ADDR = 0x%x.\n",
1440 ql_read32(qdev, XGMAC_ADDR));
1441 printk(KERN_ERR PFX "XGMAC_DATA = 0x%x.\n",
1442 ql_read32(qdev, XGMAC_DATA));
1443 printk(KERN_ERR PFX "NIC_ETS = 0x%x.\n",
1444 ql_read32(qdev, NIC_ETS));
1445 printk(KERN_ERR PFX "CNA_ETS = 0x%x.\n",
1446 ql_read32(qdev, CNA_ETS));
1447 printk(KERN_ERR PFX "FLASH_ADDR = 0x%x.\n",
1448 ql_read32(qdev, FLASH_ADDR));
1449 printk(KERN_ERR PFX "FLASH_DATA = 0x%x.\n",
1450 ql_read32(qdev, FLASH_DATA));
1451 printk(KERN_ERR PFX "CQ_STOP = 0x%x.\n",
1452 ql_read32(qdev, CQ_STOP));
1453 printk(KERN_ERR PFX "PAGE_TBL_RID = 0x%x.\n",
1454 ql_read32(qdev, PAGE_TBL_RID));
1455 printk(KERN_ERR PFX "WQ_PAGE_TBL_LO = 0x%x.\n",
1456 ql_read32(qdev, WQ_PAGE_TBL_LO));
1457 printk(KERN_ERR PFX "WQ_PAGE_TBL_HI = 0x%x.\n",
1458 ql_read32(qdev, WQ_PAGE_TBL_HI));
1459 printk(KERN_ERR PFX "CQ_PAGE_TBL_LO = 0x%x.\n",
1460 ql_read32(qdev, CQ_PAGE_TBL_LO));
1461 printk(KERN_ERR PFX "CQ_PAGE_TBL_HI = 0x%x.\n",
1462 ql_read32(qdev, CQ_PAGE_TBL_HI));
1463 printk(KERN_ERR PFX "COS_DFLT_CQ1 = 0x%x.\n",
1464 ql_read32(qdev, COS_DFLT_CQ1));
1465 printk(KERN_ERR PFX "COS_DFLT_CQ2 = 0x%x.\n",
1466 ql_read32(qdev, COS_DFLT_CQ2));
1467 printk(KERN_ERR PFX "SPLT_HDR = 0x%x.\n",
1468 ql_read32(qdev, SPLT_HDR));
1469 printk(KERN_ERR PFX "FC_PAUSE_THRES = 0x%x.\n",
1470 ql_read32(qdev, FC_PAUSE_THRES));
1471 printk(KERN_ERR PFX "NIC_PAUSE_THRES = 0x%x.\n",
1472 ql_read32(qdev, NIC_PAUSE_THRES));
1473 printk(KERN_ERR PFX "FC_ETHERTYPE = 0x%x.\n",
1474 ql_read32(qdev, FC_ETHERTYPE));
1475 printk(KERN_ERR PFX "FC_RCV_CFG = 0x%x.\n",
1476 ql_read32(qdev, FC_RCV_CFG));
1477 printk(KERN_ERR PFX "NIC_RCV_CFG = 0x%x.\n",
1478 ql_read32(qdev, NIC_RCV_CFG));
1479 printk(KERN_ERR PFX "FC_COS_TAGS = 0x%x.\n",
1480 ql_read32(qdev, FC_COS_TAGS));
1481 printk(KERN_ERR PFX "NIC_COS_TAGS = 0x%x.\n",
1482 ql_read32(qdev, NIC_COS_TAGS));
1483 printk(KERN_ERR PFX "MGMT_RCV_CFG = 0x%x.\n",
1484 ql_read32(qdev, MGMT_RCV_CFG));
1485 printk(KERN_ERR PFX "XG_SERDES_ADDR = 0x%x.\n",
1486 ql_read32(qdev, XG_SERDES_ADDR));
1487 printk(KERN_ERR PFX "XG_SERDES_DATA = 0x%x.\n",
1488 ql_read32(qdev, XG_SERDES_DATA));
1489 printk(KERN_ERR PFX "PRB_MX_ADDR = 0x%x.\n",
1490 ql_read32(qdev, PRB_MX_ADDR));
1491 printk(KERN_ERR PFX "PRB_MX_DATA = 0x%x.\n",
1492 ql_read32(qdev, PRB_MX_DATA));
1493 ql_dump_intr_states(qdev);
1494 ql_dump_xgmac_control_regs(qdev);
1495 ql_dump_ets_regs(qdev);
1496 ql_dump_cam_entries(qdev);
1497 ql_dump_routing_entries(qdev);
1498}
1499#endif
1500
1501#ifdef QL_STAT_DUMP
1502void ql_dump_stat(struct ql_adapter *qdev)
1503{
1504 printk(KERN_ERR "%s: Enter.\n", __func__);
1505 printk(KERN_ERR "tx_pkts = %ld\n",
1506 (unsigned long)qdev->nic_stats.tx_pkts);
1507 printk(KERN_ERR "tx_bytes = %ld\n",
1508 (unsigned long)qdev->nic_stats.tx_bytes);
1509 printk(KERN_ERR "tx_mcast_pkts = %ld.\n",
1510 (unsigned long)qdev->nic_stats.tx_mcast_pkts);
1511 printk(KERN_ERR "tx_bcast_pkts = %ld.\n",
1512 (unsigned long)qdev->nic_stats.tx_bcast_pkts);
1513 printk(KERN_ERR "tx_ucast_pkts = %ld.\n",
1514 (unsigned long)qdev->nic_stats.tx_ucast_pkts);
1515 printk(KERN_ERR "tx_ctl_pkts = %ld.\n",
1516 (unsigned long)qdev->nic_stats.tx_ctl_pkts);
1517 printk(KERN_ERR "tx_pause_pkts = %ld.\n",
1518 (unsigned long)qdev->nic_stats.tx_pause_pkts);
1519 printk(KERN_ERR "tx_64_pkt = %ld.\n",
1520 (unsigned long)qdev->nic_stats.tx_64_pkt);
1521 printk(KERN_ERR "tx_65_to_127_pkt = %ld.\n",
1522 (unsigned long)qdev->nic_stats.tx_65_to_127_pkt);
1523 printk(KERN_ERR "tx_128_to_255_pkt = %ld.\n",
1524 (unsigned long)qdev->nic_stats.tx_128_to_255_pkt);
1525 printk(KERN_ERR "tx_256_511_pkt = %ld.\n",
1526 (unsigned long)qdev->nic_stats.tx_256_511_pkt);
1527 printk(KERN_ERR "tx_512_to_1023_pkt = %ld.\n",
1528 (unsigned long)qdev->nic_stats.tx_512_to_1023_pkt);
1529 printk(KERN_ERR "tx_1024_to_1518_pkt = %ld.\n",
1530 (unsigned long)qdev->nic_stats.tx_1024_to_1518_pkt);
1531 printk(KERN_ERR "tx_1519_to_max_pkt = %ld.\n",
1532 (unsigned long)qdev->nic_stats.tx_1519_to_max_pkt);
1533 printk(KERN_ERR "tx_undersize_pkt = %ld.\n",
1534 (unsigned long)qdev->nic_stats.tx_undersize_pkt);
1535 printk(KERN_ERR "tx_oversize_pkt = %ld.\n",
1536 (unsigned long)qdev->nic_stats.tx_oversize_pkt);
1537 printk(KERN_ERR "rx_bytes = %ld.\n",
1538 (unsigned long)qdev->nic_stats.rx_bytes);
1539 printk(KERN_ERR "rx_bytes_ok = %ld.\n",
1540 (unsigned long)qdev->nic_stats.rx_bytes_ok);
1541 printk(KERN_ERR "rx_pkts = %ld.\n",
1542 (unsigned long)qdev->nic_stats.rx_pkts);
1543 printk(KERN_ERR "rx_pkts_ok = %ld.\n",
1544 (unsigned long)qdev->nic_stats.rx_pkts_ok);
1545 printk(KERN_ERR "rx_bcast_pkts = %ld.\n",
1546 (unsigned long)qdev->nic_stats.rx_bcast_pkts);
1547 printk(KERN_ERR "rx_mcast_pkts = %ld.\n",
1548 (unsigned long)qdev->nic_stats.rx_mcast_pkts);
1549 printk(KERN_ERR "rx_ucast_pkts = %ld.\n",
1550 (unsigned long)qdev->nic_stats.rx_ucast_pkts);
1551 printk(KERN_ERR "rx_undersize_pkts = %ld.\n",
1552 (unsigned long)qdev->nic_stats.rx_undersize_pkts);
1553 printk(KERN_ERR "rx_oversize_pkts = %ld.\n",
1554 (unsigned long)qdev->nic_stats.rx_oversize_pkts);
1555 printk(KERN_ERR "rx_jabber_pkts = %ld.\n",
1556 (unsigned long)qdev->nic_stats.rx_jabber_pkts);
1557 printk(KERN_ERR "rx_undersize_fcerr_pkts = %ld.\n",
1558 (unsigned long)qdev->nic_stats.rx_undersize_fcerr_pkts);
1559 printk(KERN_ERR "rx_drop_events = %ld.\n",
1560 (unsigned long)qdev->nic_stats.rx_drop_events);
1561 printk(KERN_ERR "rx_fcerr_pkts = %ld.\n",
1562 (unsigned long)qdev->nic_stats.rx_fcerr_pkts);
1563 printk(KERN_ERR "rx_align_err = %ld.\n",
1564 (unsigned long)qdev->nic_stats.rx_align_err);
1565 printk(KERN_ERR "rx_symbol_err = %ld.\n",
1566 (unsigned long)qdev->nic_stats.rx_symbol_err);
1567 printk(KERN_ERR "rx_mac_err = %ld.\n",
1568 (unsigned long)qdev->nic_stats.rx_mac_err);
1569 printk(KERN_ERR "rx_ctl_pkts = %ld.\n",
1570 (unsigned long)qdev->nic_stats.rx_ctl_pkts);
1571 printk(KERN_ERR "rx_pause_pkts = %ld.\n",
1572 (unsigned long)qdev->nic_stats.rx_pause_pkts);
1573 printk(KERN_ERR "rx_64_pkts = %ld.\n",
1574 (unsigned long)qdev->nic_stats.rx_64_pkts);
1575 printk(KERN_ERR "rx_65_to_127_pkts = %ld.\n",
1576 (unsigned long)qdev->nic_stats.rx_65_to_127_pkts);
1577 printk(KERN_ERR "rx_128_255_pkts = %ld.\n",
1578 (unsigned long)qdev->nic_stats.rx_128_255_pkts);
1579 printk(KERN_ERR "rx_256_511_pkts = %ld.\n",
1580 (unsigned long)qdev->nic_stats.rx_256_511_pkts);
1581 printk(KERN_ERR "rx_512_to_1023_pkts = %ld.\n",
1582 (unsigned long)qdev->nic_stats.rx_512_to_1023_pkts);
1583 printk(KERN_ERR "rx_1024_to_1518_pkts = %ld.\n",
1584 (unsigned long)qdev->nic_stats.rx_1024_to_1518_pkts);
1585 printk(KERN_ERR "rx_1519_to_max_pkts = %ld.\n",
1586 (unsigned long)qdev->nic_stats.rx_1519_to_max_pkts);
1587 printk(KERN_ERR "rx_len_err_pkts = %ld.\n",
1588 (unsigned long)qdev->nic_stats.rx_len_err_pkts);
1589};
1590#endif
1591
1592#ifdef QL_DEV_DUMP
1593void ql_dump_qdev(struct ql_adapter *qdev)
1594{
1595 int i;
1596 printk(KERN_ERR PFX "qdev->flags = %lx.\n",
1597 qdev->flags);
1598 printk(KERN_ERR PFX "qdev->vlgrp = %p.\n",
1599 qdev->vlgrp);
1600 printk(KERN_ERR PFX "qdev->pdev = %p.\n",
1601 qdev->pdev);
1602 printk(KERN_ERR PFX "qdev->ndev = %p.\n",
1603 qdev->ndev);
1604 printk(KERN_ERR PFX "qdev->chip_rev_id = %d.\n",
1605 qdev->chip_rev_id);
1606 printk(KERN_ERR PFX "qdev->reg_base = %p.\n",
1607 qdev->reg_base);
1608 printk(KERN_ERR PFX "qdev->doorbell_area = %p.\n",
1609 qdev->doorbell_area);
1610 printk(KERN_ERR PFX "qdev->doorbell_area_size = %d.\n",
1611 qdev->doorbell_area_size);
1612 printk(KERN_ERR PFX "msg_enable = %x.\n",
1613 qdev->msg_enable);
1614 printk(KERN_ERR PFX "qdev->rx_ring_shadow_reg_area = %p.\n",
1615 qdev->rx_ring_shadow_reg_area);
53159d06
DM		 1616 printk(KERN_ERR PFX "qdev->rx_ring_shadow_reg_dma = %llx.\n",
1617 (unsigned long long) qdev->rx_ring_shadow_reg_dma);
c4e84bde
RM		 1618 printk(KERN_ERR PFX "qdev->tx_ring_shadow_reg_area = %p.\n",
1619 qdev->tx_ring_shadow_reg_area);
53159d06
DM		 1620 printk(KERN_ERR PFX "qdev->tx_ring_shadow_reg_dma = %llx.\n",
1621 (unsigned long long) qdev->tx_ring_shadow_reg_dma);
c4e84bde
RM		 1622 printk(KERN_ERR PFX "qdev->intr_count = %d.\n",
1623 qdev->intr_count);
1624 if (qdev->msi_x_entry)
1625 for (i = 0; i < qdev->intr_count; i++) {
1626 printk(KERN_ERR PFX
1627 "msi_x_entry.[%d]vector = %d.\n", i,
1628 qdev->msi_x_entry[i].vector);
1629 printk(KERN_ERR PFX
1630 "msi_x_entry.[%d]entry = %d.\n", i,
1631 qdev->msi_x_entry[i].entry);
1632 }
1633 for (i = 0; i < qdev->intr_count; i++) {
1634 printk(KERN_ERR PFX
1635 "intr_context[%d].qdev = %p.\n", i,
1636 qdev->intr_context[i].qdev);
1637 printk(KERN_ERR PFX
1638 "intr_context[%d].intr = %d.\n", i,
1639 qdev->intr_context[i].intr);
1640 printk(KERN_ERR PFX
1641 "intr_context[%d].hooked = %d.\n", i,
1642 qdev->intr_context[i].hooked);
1643 printk(KERN_ERR PFX
1644 "intr_context[%d].intr_en_mask = 0x%08x.\n", i,
1645 qdev->intr_context[i].intr_en_mask);
1646 printk(KERN_ERR PFX
1647 "intr_context[%d].intr_dis_mask = 0x%08x.\n", i,
1648 qdev->intr_context[i].intr_dis_mask);
1649 printk(KERN_ERR PFX
1650 "intr_context[%d].intr_read_mask = 0x%08x.\n", i,
1651 qdev->intr_context[i].intr_read_mask);
1652 }
1653 printk(KERN_ERR PFX "qdev->tx_ring_count = %d.\n", qdev->tx_ring_count);
1654 printk(KERN_ERR PFX "qdev->rx_ring_count = %d.\n", qdev->rx_ring_count);
1655 printk(KERN_ERR PFX "qdev->ring_mem_size = %d.\n", qdev->ring_mem_size);
1656 printk(KERN_ERR PFX "qdev->ring_mem = %p.\n", qdev->ring_mem);
1657 printk(KERN_ERR PFX "qdev->intr_count = %d.\n", qdev->intr_count);
1658 printk(KERN_ERR PFX "qdev->tx_ring = %p.\n",
1659 qdev->tx_ring);
c4e84bde
RM		 1660 printk(KERN_ERR PFX "qdev->rss_ring_count = %d.\n",
1661 qdev->rss_ring_count);
1662 printk(KERN_ERR PFX "qdev->rx_ring = %p.\n", qdev->rx_ring);
1663 printk(KERN_ERR PFX "qdev->default_rx_queue = %d.\n",
1664 qdev->default_rx_queue);
1665 printk(KERN_ERR PFX "qdev->xg_sem_mask = 0x%08x.\n",
1666 qdev->xg_sem_mask);
1667 printk(KERN_ERR PFX "qdev->port_link_up = 0x%08x.\n",
1668 qdev->port_link_up);
1669 printk(KERN_ERR PFX "qdev->port_init = 0x%08x.\n",
1670 qdev->port_init);
1671
1672}
1673#endif
1674
1675#ifdef QL_CB_DUMP
1676void ql_dump_wqicb(struct wqicb *wqicb)
1677{
1678 printk(KERN_ERR PFX "Dumping wqicb stuff...\n");
1679 printk(KERN_ERR PFX "wqicb->len = 0x%x.\n", le16_to_cpu(wqicb->len));
1680 printk(KERN_ERR PFX "wqicb->flags = %x.\n", le16_to_cpu(wqicb->flags));
1681 printk(KERN_ERR PFX "wqicb->cq_id_rss = %d.\n",
1682 le16_to_cpu(wqicb->cq_id_rss));
1683 printk(KERN_ERR PFX "wqicb->rid = 0x%x.\n", le16_to_cpu(wqicb->rid));
97345524
RM		 1684 printk(KERN_ERR PFX "wqicb->wq_addr = 0x%llx.\n",
1685 (unsigned long long) le64_to_cpu(wqicb->addr));
1686 printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr = 0x%llx.\n",
1687 (unsigned long long) le64_to_cpu(wqicb->cnsmr_idx_addr));
c4e84bde
RM		 1688}
1689
1690void ql_dump_tx_ring(struct tx_ring *tx_ring)
1691{
1692 if (tx_ring == NULL)
1693 return;
1694 printk(KERN_ERR PFX
1695 "===================== Dumping tx_ring %d ===============.\n",
1696 tx_ring->wq_id);
1697 printk(KERN_ERR PFX "tx_ring->base = %p.\n", tx_ring->wq_base);
1698 printk(KERN_ERR PFX "tx_ring->base_dma = 0x%llx.\n",
53159d06 1699 (unsigned long long) tx_ring->wq_base_dma);
ba7cd3ba
RM		 1700 printk(KERN_ERR PFX
1701 "tx_ring->cnsmr_idx_sh_reg, addr = 0x%p, value = %d.\n",
1702 tx_ring->cnsmr_idx_sh_reg,
1703 tx_ring->cnsmr_idx_sh_reg
1704 ? ql_read_sh_reg(tx_ring->cnsmr_idx_sh_reg) : 0);
c4e84bde
RM		 1705 printk(KERN_ERR PFX "tx_ring->size = %d.\n", tx_ring->wq_size);
1706 printk(KERN_ERR PFX "tx_ring->len = %d.\n", tx_ring->wq_len);
1707 printk(KERN_ERR PFX "tx_ring->prod_idx_db_reg = %p.\n",
1708 tx_ring->prod_idx_db_reg);
1709 printk(KERN_ERR PFX "tx_ring->valid_db_reg = %p.\n",
1710 tx_ring->valid_db_reg);
1711 printk(KERN_ERR PFX "tx_ring->prod_idx = %d.\n", tx_ring->prod_idx);
1712 printk(KERN_ERR PFX "tx_ring->cq_id = %d.\n", tx_ring->cq_id);
1713 printk(KERN_ERR PFX "tx_ring->wq_id = %d.\n", tx_ring->wq_id);
1714 printk(KERN_ERR PFX "tx_ring->q = %p.\n", tx_ring->q);
1715 printk(KERN_ERR PFX "tx_ring->tx_count = %d.\n",
1716 atomic_read(&tx_ring->tx_count));
1717}
1718
1719void ql_dump_ricb(struct ricb *ricb)
1720{
1721 int i;
1722 printk(KERN_ERR PFX
1723 "===================== Dumping ricb ===============.\n");
1724 printk(KERN_ERR PFX "Dumping ricb stuff...\n");
1725
1726 printk(KERN_ERR PFX "ricb->base_cq = %d.\n", ricb->base_cq & 0x1f);
1727 printk(KERN_ERR PFX "ricb->flags = %s%s%s%s%s%s%s%s%s.\n",
1728 ricb->base_cq & RSS_L4K ? "RSS_L4K " : "",
1729 ricb->flags & RSS_L6K ? "RSS_L6K " : "",
1730 ricb->flags & RSS_LI ? "RSS_LI " : "",
1731 ricb->flags & RSS_LB ? "RSS_LB " : "",
1732 ricb->flags & RSS_LM ? "RSS_LM " : "",
1733 ricb->flags & RSS_RI4 ? "RSS_RI4 " : "",
1734 ricb->flags & RSS_RT4 ? "RSS_RT4 " : "",
1735 ricb->flags & RSS_RI6 ? "RSS_RI6 " : "",
1736 ricb->flags & RSS_RT6 ? "RSS_RT6 " : "");
1737 printk(KERN_ERR PFX "ricb->mask = 0x%.04x.\n", le16_to_cpu(ricb->mask));
1738 for (i = 0; i < 16; i++)
1739 printk(KERN_ERR PFX "ricb->hash_cq_id[%d] = 0x%.08x.\n", i,
1740 le32_to_cpu(ricb->hash_cq_id[i]));
1741 for (i = 0; i < 10; i++)
1742 printk(KERN_ERR PFX "ricb->ipv6_hash_key[%d] = 0x%.08x.\n", i,
1743 le32_to_cpu(ricb->ipv6_hash_key[i]));
1744 for (i = 0; i < 4; i++)
1745 printk(KERN_ERR PFX "ricb->ipv4_hash_key[%d] = 0x%.08x.\n", i,
1746 le32_to_cpu(ricb->ipv4_hash_key[i]));
1747}
1748
1749void ql_dump_cqicb(struct cqicb *cqicb)
1750{
1751 printk(KERN_ERR PFX "Dumping cqicb stuff...\n");
1752
1753 printk(KERN_ERR PFX "cqicb->msix_vect = %d.\n", cqicb->msix_vect);
1754 printk(KERN_ERR PFX "cqicb->flags = %x.\n", cqicb->flags);
1755 printk(KERN_ERR PFX "cqicb->len = %d.\n", le16_to_cpu(cqicb->len));
97345524
RM		 1756 printk(KERN_ERR PFX "cqicb->addr = 0x%llx.\n",
1757 (unsigned long long) le64_to_cpu(cqicb->addr));
1758 printk(KERN_ERR PFX "cqicb->prod_idx_addr = 0x%llx.\n",
1759 (unsigned long long) le64_to_cpu(cqicb->prod_idx_addr));
c4e84bde
RM		 1760 printk(KERN_ERR PFX "cqicb->pkt_delay = 0x%.04x.\n",
1761 le16_to_cpu(cqicb->pkt_delay));
1762 printk(KERN_ERR PFX "cqicb->irq_delay = 0x%.04x.\n",
1763 le16_to_cpu(cqicb->irq_delay));
97345524
RM		 1764 printk(KERN_ERR PFX "cqicb->lbq_addr = 0x%llx.\n",
1765 (unsigned long long) le64_to_cpu(cqicb->lbq_addr));
c4e84bde
RM		 1766 printk(KERN_ERR PFX "cqicb->lbq_buf_size = 0x%.04x.\n",
1767 le16_to_cpu(cqicb->lbq_buf_size));
1768 printk(KERN_ERR PFX "cqicb->lbq_len = 0x%.04x.\n",
1769 le16_to_cpu(cqicb->lbq_len));
97345524
RM		 1770 printk(KERN_ERR PFX "cqicb->sbq_addr = 0x%llx.\n",
1771 (unsigned long long) le64_to_cpu(cqicb->sbq_addr));
c4e84bde
RM		 1772 printk(KERN_ERR PFX "cqicb->sbq_buf_size = 0x%.04x.\n",
1773 le16_to_cpu(cqicb->sbq_buf_size));
1774 printk(KERN_ERR PFX "cqicb->sbq_len = 0x%.04x.\n",
1775 le16_to_cpu(cqicb->sbq_len));
1776}
1777
1778void ql_dump_rx_ring(struct rx_ring *rx_ring)
1779{
1780 if (rx_ring == NULL)
1781 return;
1782 printk(KERN_ERR PFX
1783 "===================== Dumping rx_ring %d ===============.\n",
1784 rx_ring->cq_id);
1785 printk(KERN_ERR PFX "Dumping rx_ring %d, type = %s%s%s.\n",
1786 rx_ring->cq_id, rx_ring->type == DEFAULT_Q ? "DEFAULT" : "",
1787 rx_ring->type == TX_Q ? "OUTBOUND COMPLETIONS" : "",
1788 rx_ring->type == RX_Q ? "INBOUND_COMPLETIONS" : "");
1789 printk(KERN_ERR PFX "rx_ring->cqicb = %p.\n", &rx_ring->cqicb);
1790 printk(KERN_ERR PFX "rx_ring->cq_base = %p.\n", rx_ring->cq_base);
1791 printk(KERN_ERR PFX "rx_ring->cq_base_dma = %llx.\n",
53159d06 1792 (unsigned long long) rx_ring->cq_base_dma);
c4e84bde
RM		 1793 printk(KERN_ERR PFX "rx_ring->cq_size = %d.\n", rx_ring->cq_size);
1794 printk(KERN_ERR PFX "rx_ring->cq_len = %d.\n", rx_ring->cq_len);
1795 printk(KERN_ERR PFX
ba7cd3ba 1796 "rx_ring->prod_idx_sh_reg, addr = 0x%p, value = %d.\n",
c4e84bde 1797 rx_ring->prod_idx_sh_reg,
ba7cd3ba
RM		 1798 rx_ring->prod_idx_sh_reg
1799 ? ql_read_sh_reg(rx_ring->prod_idx_sh_reg) : 0);
c4e84bde 1800 printk(KERN_ERR PFX "rx_ring->prod_idx_sh_reg_dma = %llx.\n",
53159d06 1801 (unsigned long long) rx_ring->prod_idx_sh_reg_dma);
c4e84bde
RM		 1802 printk(KERN_ERR PFX "rx_ring->cnsmr_idx_db_reg = %p.\n",
1803 rx_ring->cnsmr_idx_db_reg);
1804 printk(KERN_ERR PFX "rx_ring->cnsmr_idx = %d.\n", rx_ring->cnsmr_idx);
1805 printk(KERN_ERR PFX "rx_ring->curr_entry = %p.\n", rx_ring->curr_entry);
1806 printk(KERN_ERR PFX "rx_ring->valid_db_reg = %p.\n",
1807 rx_ring->valid_db_reg);
1808
1809 printk(KERN_ERR PFX "rx_ring->lbq_base = %p.\n", rx_ring->lbq_base);
1810 printk(KERN_ERR PFX "rx_ring->lbq_base_dma = %llx.\n",
53159d06 1811 (unsigned long long) rx_ring->lbq_base_dma);
c4e84bde
RM		 1812 printk(KERN_ERR PFX "rx_ring->lbq_base_indirect = %p.\n",
1813 rx_ring->lbq_base_indirect);
1814 printk(KERN_ERR PFX "rx_ring->lbq_base_indirect_dma = %llx.\n",
53159d06 1815 (unsigned long long) rx_ring->lbq_base_indirect_dma);
c4e84bde
RM		 1816 printk(KERN_ERR PFX "rx_ring->lbq = %p.\n", rx_ring->lbq);
1817 printk(KERN_ERR PFX "rx_ring->lbq_len = %d.\n", rx_ring->lbq_len);
1818 printk(KERN_ERR PFX "rx_ring->lbq_size = %d.\n", rx_ring->lbq_size);
1819 printk(KERN_ERR PFX "rx_ring->lbq_prod_idx_db_reg = %p.\n",
1820 rx_ring->lbq_prod_idx_db_reg);
1821 printk(KERN_ERR PFX "rx_ring->lbq_prod_idx = %d.\n",
1822 rx_ring->lbq_prod_idx);
1823 printk(KERN_ERR PFX "rx_ring->lbq_curr_idx = %d.\n",
1824 rx_ring->lbq_curr_idx);
1825 printk(KERN_ERR PFX "rx_ring->lbq_clean_idx = %d.\n",
1826 rx_ring->lbq_clean_idx);
1827 printk(KERN_ERR PFX "rx_ring->lbq_free_cnt = %d.\n",
1828 rx_ring->lbq_free_cnt);
1829 printk(KERN_ERR PFX "rx_ring->lbq_buf_size = %d.\n",
1830 rx_ring->lbq_buf_size);
1831
1832 printk(KERN_ERR PFX "rx_ring->sbq_base = %p.\n", rx_ring->sbq_base);
1833 printk(KERN_ERR PFX "rx_ring->sbq_base_dma = %llx.\n",
53159d06 1834 (unsigned long long) rx_ring->sbq_base_dma);
c4e84bde
RM		 1835 printk(KERN_ERR PFX "rx_ring->sbq_base_indirect = %p.\n",
1836 rx_ring->sbq_base_indirect);
1837 printk(KERN_ERR PFX "rx_ring->sbq_base_indirect_dma = %llx.\n",
53159d06 1838 (unsigned long long) rx_ring->sbq_base_indirect_dma);
c4e84bde
RM		 1839 printk(KERN_ERR PFX "rx_ring->sbq = %p.\n", rx_ring->sbq);
1840 printk(KERN_ERR PFX "rx_ring->sbq_len = %d.\n", rx_ring->sbq_len);
1841 printk(KERN_ERR PFX "rx_ring->sbq_size = %d.\n", rx_ring->sbq_size);
1842 printk(KERN_ERR PFX "rx_ring->sbq_prod_idx_db_reg addr = %p.\n",
1843 rx_ring->sbq_prod_idx_db_reg);
1844 printk(KERN_ERR PFX "rx_ring->sbq_prod_idx = %d.\n",
1845 rx_ring->sbq_prod_idx);
1846 printk(KERN_ERR PFX "rx_ring->sbq_curr_idx = %d.\n",
1847 rx_ring->sbq_curr_idx);
1848 printk(KERN_ERR PFX "rx_ring->sbq_clean_idx = %d.\n",
1849 rx_ring->sbq_clean_idx);
1850 printk(KERN_ERR PFX "rx_ring->sbq_free_cnt = %d.\n",
1851 rx_ring->sbq_free_cnt);
1852 printk(KERN_ERR PFX "rx_ring->sbq_buf_size = %d.\n",
1853 rx_ring->sbq_buf_size);
1854 printk(KERN_ERR PFX "rx_ring->cq_id = %d.\n", rx_ring->cq_id);
1855 printk(KERN_ERR PFX "rx_ring->irq = %d.\n", rx_ring->irq);
1856 printk(KERN_ERR PFX "rx_ring->cpu = %d.\n", rx_ring->cpu);
1857 printk(KERN_ERR PFX "rx_ring->qdev = %p.\n", rx_ring->qdev);
1858}
1859
1860void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id)
1861{
1862 void *ptr;
1863
1864 printk(KERN_ERR PFX "%s: Enter.\n", __func__);
1865
1866 ptr = kmalloc(size, GFP_ATOMIC);
1867 if (ptr == NULL) {
1868 printk(KERN_ERR PFX "%s: Couldn't allocate a buffer.\n",
1869 __func__);
1870 return;
1871 }
1872
1873 if (ql_write_cfg(qdev, ptr, size, bit, q_id)) {
1874 printk(KERN_ERR "%s: Failed to upload control block!\n",
1875 __func__);
1876 goto fail_it;
1877 }
1878 switch (bit) {
1879 case CFG_DRQ:
1880 ql_dump_wqicb((struct wqicb *)ptr);
1881 break;
1882 case CFG_DCQ:
1883 ql_dump_cqicb((struct cqicb *)ptr);
1884 break;
1885 case CFG_DR:
1886 ql_dump_ricb((struct ricb *)ptr);
1887 break;
1888 default:
1889 printk(KERN_ERR PFX "%s: Invalid bit value = %x.\n",
1890 __func__, bit);
1891 break;
1892 }
1893fail_it:
1894 kfree(ptr);
1895}
1896#endif
1897
1898#ifdef QL_OB_DUMP
1899void ql_dump_tx_desc(struct tx_buf_desc *tbd)
1900{
1901 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
1902 le64_to_cpu((u64) tbd->addr));
1903 printk(KERN_ERR PFX "tbd->len = %d\n",
1904 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
1905 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
1906 tbd->len & TX_DESC_C ? "C" : ".",
1907 tbd->len & TX_DESC_E ? "E" : ".");
1908 tbd++;
1909 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
1910 le64_to_cpu((u64) tbd->addr));
1911 printk(KERN_ERR PFX "tbd->len = %d\n",
1912 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
1913 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
1914 tbd->len & TX_DESC_C ? "C" : ".",
1915 tbd->len & TX_DESC_E ? "E" : ".");
1916 tbd++;
1917 printk(KERN_ERR PFX "tbd->addr = 0x%llx\n",
1918 le64_to_cpu((u64) tbd->addr));
1919 printk(KERN_ERR PFX "tbd->len = %d\n",
1920 le32_to_cpu(tbd->len & TX_DESC_LEN_MASK));
1921 printk(KERN_ERR PFX "tbd->flags = %s %s\n",
1922 tbd->len & TX_DESC_C ? "C" : ".",
1923 tbd->len & TX_DESC_E ? "E" : ".");
1924
1925}
1926
1927void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb)
1928{
1929 struct ob_mac_tso_iocb_req *ob_mac_tso_iocb =
1930 (struct ob_mac_tso_iocb_req *)ob_mac_iocb;
1931 struct tx_buf_desc *tbd;
1932 u16 frame_len;
1933
1934 printk(KERN_ERR PFX "%s\n", __func__);
1935 printk(KERN_ERR PFX "opcode = %s\n",
1936 (ob_mac_iocb->opcode == OPCODE_OB_MAC_IOCB) ? "MAC" : "TSO");
1937 printk(KERN_ERR PFX "flags1 = %s %s %s %s %s\n",
1938 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_OI ? "OI" : "",
1939 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_I ? "I" : "",
1940 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_D ? "D" : "",
1941 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_IP4 ? "IP4" : "",
1942 ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_IP6 ? "IP6" : "");
1943 printk(KERN_ERR PFX "flags2 = %s %s %s\n",
1944 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_LSO ? "LSO" : "",
1945 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_UC ? "UC" : "",
1946 ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_TC ? "TC" : "");
1947 printk(KERN_ERR PFX "flags3 = %s %s %s \n",
1948 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_IC ? "IC" : "",
1949 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_DFP ? "DFP" : "",
1950 ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_V ? "V" : "");
1951 printk(KERN_ERR PFX "tid = %x\n", ob_mac_iocb->tid);
1952 printk(KERN_ERR PFX "txq_idx = %d\n", ob_mac_iocb->txq_idx);
1953 printk(KERN_ERR PFX "vlan_tci = %x\n", ob_mac_tso_iocb->vlan_tci);
1954 if (ob_mac_iocb->opcode == OPCODE_OB_MAC_TSO_IOCB) {
1955 printk(KERN_ERR PFX "frame_len = %d\n",
1956 le32_to_cpu(ob_mac_tso_iocb->frame_len));
1957 printk(KERN_ERR PFX "mss = %d\n",
1958 le16_to_cpu(ob_mac_tso_iocb->mss));
1959 printk(KERN_ERR PFX "prot_hdr_len = %d\n",
1960 le16_to_cpu(ob_mac_tso_iocb->total_hdrs_len));
1961 printk(KERN_ERR PFX "hdr_offset = 0x%.04x\n",
1962 le16_to_cpu(ob_mac_tso_iocb->net_trans_offset));
1963 frame_len = le32_to_cpu(ob_mac_tso_iocb->frame_len);
1964 } else {
1965 printk(KERN_ERR PFX "frame_len = %d\n",
1966 le16_to_cpu(ob_mac_iocb->frame_len));
1967 frame_len = le16_to_cpu(ob_mac_iocb->frame_len);
1968 }
1969 tbd = &ob_mac_iocb->tbd[0];
1970 ql_dump_tx_desc(tbd);
1971}
1972
1973void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp)
1974{
1975 printk(KERN_ERR PFX "%s\n", __func__);
1976 printk(KERN_ERR PFX "opcode = %d\n", ob_mac_rsp->opcode);
1977 printk(KERN_ERR PFX "flags = %s %s %s %s %s %s %s\n",
1978 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_OI ? "OI" : ".",
1979 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_I ? "I" : ".",
1980 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_E ? "E" : ".",
1981 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_S ? "S" : ".",
1982 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_L ? "L" : ".",
1983 ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_P ? "P" : ".",
1984 ob_mac_rsp->flags2 & OB_MAC_IOCB_RSP_B ? "B" : ".");
1985 printk(KERN_ERR PFX "tid = %x\n", ob_mac_rsp->tid);
1986}
1987#endif
1988
1989#ifdef QL_IB_DUMP
1990void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp)
1991{
1992 printk(KERN_ERR PFX "%s\n", __func__);
1993 printk(KERN_ERR PFX "opcode = 0x%x\n", ib_mac_rsp->opcode);
1994 printk(KERN_ERR PFX "flags1 = %s%s%s%s%s%s\n",
1995 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_OI ? "OI " : "",
1996 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_I ? "I " : "",
1997 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_TE ? "TE " : "",
1998 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU ? "NU " : "",
1999 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_IE ? "IE " : "",
2000 ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_B ? "B " : "");
2001
2002 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK)
2003 printk(KERN_ERR PFX "%s%s%s Multicast.\n",
2004 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2005 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
2006 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2007 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
2008 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
2009 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
2010
2011 printk(KERN_ERR PFX "flags2 = %s%s%s%s%s\n",
2012 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) ? "P " : "",
2013 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ? "V " : "",
2014 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) ? "U " : "",
2015 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ? "T " : "",
2016 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_FO) ? "FO " : "");
2017
2018 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK)
2019 printk(KERN_ERR PFX "%s%s%s%s%s error.\n",
2020 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2021 IB_MAC_IOCB_RSP_ERR_OVERSIZE ? "oversize" : "",
2022 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2023 IB_MAC_IOCB_RSP_ERR_UNDERSIZE ? "undersize" : "",
2024 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2025 IB_MAC_IOCB_RSP_ERR_PREAMBLE ? "preamble" : "",
2026 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2027 IB_MAC_IOCB_RSP_ERR_FRAME_LEN ? "frame length" : "",
2028 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) ==
2029 IB_MAC_IOCB_RSP_ERR_CRC ? "CRC" : "");
2030
2031 printk(KERN_ERR PFX "flags3 = %s%s.\n",
2032 ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS ? "DS " : "",
2033 ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL ? "DL " : "");
2034
2035 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK)
2036 printk(KERN_ERR PFX "RSS flags = %s%s%s%s.\n",
2037 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
2038 IB_MAC_IOCB_RSP_M_IPV4) ? "IPv4 RSS" : "",
2039 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
2040 IB_MAC_IOCB_RSP_M_IPV6) ? "IPv6 RSS " : "",
2041 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
2042 IB_MAC_IOCB_RSP_M_TCP_V4) ? "TCP/IPv4 RSS" : "",
2043 ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) ==
2044 IB_MAC_IOCB_RSP_M_TCP_V6) ? "TCP/IPv6 RSS" : "");
2045
2046 printk(KERN_ERR PFX "data_len = %d\n",
2047 le32_to_cpu(ib_mac_rsp->data_len));
97345524
RM		 2048 printk(KERN_ERR PFX "data_addr = 0x%llx\n",
2049 (unsigned long long) le64_to_cpu(ib_mac_rsp->data_addr));
c4e84bde
RM		 2050 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK)
2051 printk(KERN_ERR PFX "rss = %x\n",
2052 le32_to_cpu(ib_mac_rsp->rss));
2053 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)
2054 printk(KERN_ERR PFX "vlan_id = %x\n",
2055 le16_to_cpu(ib_mac_rsp->vlan_id));
2056
2057 printk(KERN_ERR PFX "flags4 = %s%s%s.\n",
a303ce09
RM		 2058 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV ? "HV " : "",
2059 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS ? "HS " : "",
2060 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HL ? "HL " : "");
2061
2062 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
c4e84bde
RM		 2063 printk(KERN_ERR PFX "hdr length = %d.\n",
2064 le32_to_cpu(ib_mac_rsp->hdr_len));
97345524
RM		 2065 printk(KERN_ERR PFX "hdr addr = 0x%llx.\n",
2066 (unsigned long long) le64_to_cpu(ib_mac_rsp->hdr_addr));
c4e84bde
RM		 2067 }
2068}
2069#endif
2070
2071#ifdef QL_ALL_DUMP
2072void ql_dump_all(struct ql_adapter *qdev)
2073{
2074 int i;
2075
2076 QL_DUMP_REGS(qdev);
2077 QL_DUMP_QDEV(qdev);
2078 for (i = 0; i < qdev->tx_ring_count; i++) {
2079 QL_DUMP_TX_RING(&qdev->tx_ring[i]);
2080 QL_DUMP_WQICB((struct wqicb *)&qdev->tx_ring[i]);
2081 }
2082 for (i = 0; i < qdev->rx_ring_count; i++) {
2083 QL_DUMP_RX_RING(&qdev->rx_ring[i]);
2084 QL_DUMP_CQICB((struct cqicb *)&qdev->rx_ring[i]);
2085 }
2086}
2087#endif
Linux kernel - Deliverables
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