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dm9601: trivial comment fixes
[deliverable/linux.git] / drivers / net / r6040.c
CommitLineData
7a47dd7a
SW		 1/*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
5ac5d616 6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7a47dd7a
SW		 7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23*/
24
25#include <linux/kernel.h>
26#include <linux/module.h>
7a47dd7a
SW		 27#include <linux/moduleparam.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
34#include <linux/pci.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/mii.h>
41#include <linux/ethtool.h>
42#include <linux/crc32.h>
43#include <linux/spinlock.h>
092427be
JG		 44#include <linux/bitops.h>
45#include <linux/io.h>
46#include <linux/irq.h>
47#include <linux/uaccess.h>
7a47dd7a
SW		 48
49#include <asm/processor.h>
7a47dd7a
SW		 50
51#define DRV_NAME "r6040"
ba1cd541
FF		 52#define DRV_VERSION "0.23"
53#define DRV_RELDATE "05May2009"
7a47dd7a
SW		 54
55/* PHY CHIP Address */
56#define PHY1_ADDR 1 /* For MAC1 */
2a30ca8b 57#define PHY2_ADDR 3 /* For MAC2 */
7a47dd7a
SW		 58#define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
59#define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
60
61/* Time in jiffies before concluding the transmitter is hung. */
5ac5d616 62#define TX_TIMEOUT (6000 * HZ / 1000)
7a47dd7a
SW		 63
64/* RDC MAC I/O Size */
65#define R6040_IO_SIZE 256
66
67/* MAX RDC MAC */
68#define MAX_MAC 2
69
70/* MAC registers */
71#define MCR0 0x00 /* Control register 0 */
72#define MCR1 0x04 /* Control register 1 */
73#define MAC_RST 0x0001 /* Reset the MAC */
74#define MBCR 0x08 /* Bus control */
75#define MT_ICR 0x0C /* TX interrupt control */
76#define MR_ICR 0x10 /* RX interrupt control */
77#define MTPR 0x14 /* TX poll command register */
78#define MR_BSR 0x18 /* RX buffer size */
79#define MR_DCR 0x1A /* RX descriptor control */
80#define MLSR 0x1C /* Last status */
81#define MMDIO 0x20 /* MDIO control register */
82#define MDIO_WRITE 0x4000 /* MDIO write */
83#define MDIO_READ 0x2000 /* MDIO read */
84#define MMRD 0x24 /* MDIO read data register */
85#define MMWD 0x28 /* MDIO write data register */
86#define MTD_SA0 0x2C /* TX descriptor start address 0 */
87#define MTD_SA1 0x30 /* TX descriptor start address 1 */
88#define MRD_SA0 0x34 /* RX descriptor start address 0 */
89#define MRD_SA1 0x38 /* RX descriptor start address 1 */
90#define MISR 0x3C /* Status register */
91#define MIER 0x40 /* INT enable register */
92#define MSK_INT 0x0000 /* Mask off interrupts */
3d254348
FF		 93#define RX_FINISH 0x0001 /* RX finished */
94#define RX_NO_DESC 0x0002 /* No RX descriptor available */
95#define RX_FIFO_FULL 0x0004 /* RX FIFO full */
96#define RX_EARLY 0x0008 /* RX early */
97#define TX_FINISH 0x0010 /* TX finished */
98#define TX_EARLY 0x0080 /* TX early */
99#define EVENT_OVRFL 0x0100 /* Event counter overflow */
100#define LINK_CHANGED 0x0200 /* PHY link changed */
7a47dd7a
SW		 101#define ME_CISR 0x44 /* Event counter INT status */
102#define ME_CIER 0x48 /* Event counter INT enable */
103#define MR_CNT 0x50 /* Successfully received packet counter */
104#define ME_CNT0 0x52 /* Event counter 0 */
105#define ME_CNT1 0x54 /* Event counter 1 */
106#define ME_CNT2 0x56 /* Event counter 2 */
107#define ME_CNT3 0x58 /* Event counter 3 */
108#define MT_CNT 0x5A /* Successfully transmit packet counter */
109#define ME_CNT4 0x5C /* Event counter 4 */
110#define MP_CNT 0x5E /* Pause frame counter register */
111#define MAR0 0x60 /* Hash table 0 */
112#define MAR1 0x62 /* Hash table 1 */
113#define MAR2 0x64 /* Hash table 2 */
114#define MAR3 0x66 /* Hash table 3 */
115#define MID_0L 0x68 /* Multicast address MID0 Low */
116#define MID_0M 0x6A /* Multicast address MID0 Medium */
117#define MID_0H 0x6C /* Multicast address MID0 High */
118#define MID_1L 0x70 /* MID1 Low */
119#define MID_1M 0x72 /* MID1 Medium */
120#define MID_1H 0x74 /* MID1 High */
121#define MID_2L 0x78 /* MID2 Low */
122#define MID_2M 0x7A /* MID2 Medium */
123#define MID_2H 0x7C /* MID2 High */
124#define MID_3L 0x80 /* MID3 Low */
125#define MID_3M 0x82 /* MID3 Medium */
126#define MID_3H 0x84 /* MID3 High */
127#define PHY_CC 0x88 /* PHY status change configuration register */
128#define PHY_ST 0x8A /* PHY status register */
129#define MAC_SM 0xAC /* MAC status machine */
130#define MAC_ID 0xBE /* Identifier register */
131
132#define TX_DCNT 0x80 /* TX descriptor count */
133#define RX_DCNT 0x80 /* RX descriptor count */
134#define MAX_BUF_SIZE 0x600
6c323103
FR		 135#define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
136#define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
7a47dd7a
SW		 137#define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
138#define MCAST_MAX 4 /* Max number multicast addresses to filter */
139
32f565df
FF		 140/* Descriptor status */
141#define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
142#define DSC_RX_OK 0x4000 /* RX was successful */
143#define DSC_RX_ERR 0x0800 /* RX PHY error */
144#define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
145#define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
146#define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
147#define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
148#define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
149#define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
150#define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
151#define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
152#define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
153#define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
154
7a47dd7a
SW		 155/* PHY settings */
156#define ICPLUS_PHY_ID 0x0243
157
158MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
159 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
160 "Florian Fainelli <florian@openwrt.org>");
161MODULE_LICENSE("GPL");
162MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
bc4de260 163MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
7a47dd7a 164
3d254348 165/* RX and TX interrupts that we handle */
e24ddf3a
FF		 166#define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
167#define TX_INTS (TX_FINISH)
168#define INT_MASK (RX_INTS | TX_INTS)
7a47dd7a
SW		 169
170struct r6040_descriptor {
171 u16 status, len; /* 0-3 */
172 __le32 buf; /* 4-7 */
173 __le32 ndesc; /* 8-B */
174 u32 rev1; /* C-F */
175 char *vbufp; /* 10-13 */
176 struct r6040_descriptor *vndescp; /* 14-17 */
177 struct sk_buff *skb_ptr; /* 18-1B */
178 u32 rev2; /* 1C-1F */
179} __attribute__((aligned(32)));
180
181struct r6040_private {
182 spinlock_t lock; /* driver lock */
183 struct timer_list timer;
184 struct pci_dev *pdev;
185 struct r6040_descriptor *rx_insert_ptr;
186 struct r6040_descriptor *rx_remove_ptr;
187 struct r6040_descriptor *tx_insert_ptr;
188 struct r6040_descriptor *tx_remove_ptr;
6c323103
FR		 189 struct r6040_descriptor *rx_ring;
190 struct r6040_descriptor *tx_ring;
191 dma_addr_t rx_ring_dma;
192 dma_addr_t tx_ring_dma;
9ca28dc4 193 u16 tx_free_desc, phy_addr, phy_mode;
7a47dd7a 194 u16 mcr0, mcr1;
7a47dd7a
SW		 195 u16 switch_sig;
196 struct net_device *dev;
197 struct mii_if_info mii_if;
198 struct napi_struct napi;
7a47dd7a
SW		 199 void __iomem *base;
200};
201
202static char version[] __devinitdata = KERN_INFO DRV_NAME
203 ": RDC R6040 NAPI net driver,"
9a48ce84 204 "version "DRV_VERSION " (" DRV_RELDATE ")";
7a47dd7a 205
092427be 206static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
7a47dd7a
SW		 207
208/* Read a word data from PHY Chip */
c6e69bb9 209static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
7a47dd7a
SW		 210{
211 int limit = 2048;
212 u16 cmd;
213
214 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
215 /* Wait for the read bit to be cleared */
216 while (limit--) {
217 cmd = ioread16(ioaddr + MMDIO);
11e5e8f5 218 if (!(cmd & MDIO_READ))
7a47dd7a
SW		 219 break;
220 }
221
222 return ioread16(ioaddr + MMRD);
223}
224
225/* Write a word data from PHY Chip */
c6e69bb9 226static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
7a47dd7a
SW		 227{
228 int limit = 2048;
229 u16 cmd;
230
231 iowrite16(val, ioaddr + MMWD);
232 /* Write the command to the MDIO bus */
233 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
234 /* Wait for the write bit to be cleared */
235 while (limit--) {
236 cmd = ioread16(ioaddr + MMDIO);
11e5e8f5 237 if (!(cmd & MDIO_WRITE))
7a47dd7a
SW		 238 break;
239 }
240}
241
c6e69bb9 242static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg)
7a47dd7a
SW		 243{
244 struct r6040_private *lp = netdev_priv(dev);
245 void __iomem *ioaddr = lp->base;
246
c6e69bb9 247 return (r6040_phy_read(ioaddr, lp->phy_addr, reg));
7a47dd7a
SW		 248}
249
c6e69bb9 250static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val)
7a47dd7a
SW		 251{
252 struct r6040_private *lp = netdev_priv(dev);
253 void __iomem *ioaddr = lp->base;
254
c6e69bb9 255 r6040_phy_write(ioaddr, lp->phy_addr, reg, val);
7a47dd7a
SW		 256}
257
b4f1255d
FF		 258static void r6040_free_txbufs(struct net_device *dev)
259{
260 struct r6040_private *lp = netdev_priv(dev);
261 int i;
262
263 for (i = 0; i < TX_DCNT; i++) {
264 if (lp->tx_insert_ptr->skb_ptr) {
ed773b4a
AV		 265 pci_unmap_single(lp->pdev,
266 le32_to_cpu(lp->tx_insert_ptr->buf),
b4f1255d
FF		 267 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
268 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
3b060be0 269 lp->tx_insert_ptr->skb_ptr = NULL;
b4f1255d
FF		 270 }
271 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
272 }
273}
274
275static void r6040_free_rxbufs(struct net_device *dev)
276{
277 struct r6040_private *lp = netdev_priv(dev);
278 int i;
279
280 for (i = 0; i < RX_DCNT; i++) {
281 if (lp->rx_insert_ptr->skb_ptr) {
ed773b4a
AV		 282 pci_unmap_single(lp->pdev,
283 le32_to_cpu(lp->rx_insert_ptr->buf),
b4f1255d
FF		 284 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
285 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
286 lp->rx_insert_ptr->skb_ptr = NULL;
287 }
288 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
289 }
290}
291
b4f1255d
FF		 292static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
293 dma_addr_t desc_dma, int size)
294{
295 struct r6040_descriptor *desc = desc_ring;
296 dma_addr_t mapping = desc_dma;
297
298 while (size-- > 0) {
3f6602ad 299 mapping += sizeof(*desc);
b4f1255d
FF		 300 desc->ndesc = cpu_to_le32(mapping);
301 desc->vndescp = desc + 1;
302 desc++;
303 }
304 desc--;
305 desc->ndesc = cpu_to_le32(desc_dma);
306 desc->vndescp = desc_ring;
307}
308
3d463419 309static void r6040_init_txbufs(struct net_device *dev)
b4f1255d
FF		 310{
311 struct r6040_private *lp = netdev_priv(dev);
b4f1255d
FF		 312
313 lp->tx_free_desc = TX_DCNT;
314
315 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
316 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
b4f1255d
FF		 317}
318
3d463419 319static int r6040_alloc_rxbufs(struct net_device *dev)
b4f1255d
FF		 320{
321 struct r6040_private *lp = netdev_priv(dev);
3d463419
FF		 322 struct r6040_descriptor *desc;
323 struct sk_buff *skb;
324 int rc;
b4f1255d
FF		 325
326 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
327 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
328
3d463419
FF		 329 /* Allocate skbs for the rx descriptors */
330 desc = lp->rx_ring;
331 do {
332 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
333 if (!skb) {
9a48ce84 334 printk(KERN_ERR DRV_NAME "%s: failed to alloc skb for rx\n", dev->name);
3d463419
FF		 335 rc = -ENOMEM;
336 goto err_exit;
337 }
338 desc->skb_ptr = skb;
339 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
340 desc->skb_ptr->data,
341 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
32f565df 342 desc->status = DSC_OWNER_MAC;
3d463419
FF		 343 desc = desc->vndescp;
344 } while (desc != lp->rx_ring);
345
346 return 0;
347
348err_exit:
349 /* Deallocate all previously allocated skbs */
350 r6040_free_rxbufs(dev);
351 return rc;
fec3a23b
FF		 352}
353
354static void r6040_init_mac_regs(struct net_device *dev)
355{
356 struct r6040_private *lp = netdev_priv(dev);
357 void __iomem *ioaddr = lp->base;
358 int limit = 2048;
359 u16 cmd;
360
361 /* Mask Off Interrupt */
362 iowrite16(MSK_INT, ioaddr + MIER);
363
364 /* Reset RDC MAC */
365 iowrite16(MAC_RST, ioaddr + MCR1);
366 while (limit--) {
367 cmd = ioread16(ioaddr + MCR1);
368 if (cmd & 0x1)
369 break;
370 }
371 /* Reset internal state machine */
372 iowrite16(2, ioaddr + MAC_SM);
373 iowrite16(0, ioaddr + MAC_SM);
c1d69937 374 mdelay(5);
fec3a23b
FF		 375
376 /* MAC Bus Control Register */
377 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
378
379 /* Buffer Size Register */
380 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
381
382 /* Write TX ring start address */
383 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
384 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
b4f1255d 385
fec3a23b 386 /* Write RX ring start address */
b4f1255d
FF		 387 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
388 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
fec3a23b
FF		 389
390 /* Set interrupt waiting time and packet numbers */
31718ded
FF		 391 iowrite16(0, ioaddr + MT_ICR);
392 iowrite16(0, ioaddr + MR_ICR);
fec3a23b
FF		 393
394 /* Enable interrupts */
395 iowrite16(INT_MASK, ioaddr + MIER);
396
397 /* Enable TX and RX */
398 iowrite16(lp->mcr0 | 0x0002, ioaddr);
399
400 /* Let TX poll the descriptors
401 * we may got called by r6040_tx_timeout which has left
402 * some unsent tx buffers */
403 iowrite16(0x01, ioaddr + MTPR);
b4f1255d 404}
7a47dd7a 405
106adf3c
FF		 406static void r6040_tx_timeout(struct net_device *dev)
407{
408 struct r6040_private *priv = netdev_priv(dev);
409 void __iomem *ioaddr = priv->base;
410
fec3a23b
FF		 411 printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x "
412 "status %4.4x, PHY status %4.4x\n",
106adf3c 413 dev->name, ioread16(ioaddr + MIER),
fec3a23b 414 ioread16(ioaddr + MISR),
c6e69bb9 415 r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR));
106adf3c 416
106adf3c 417 dev->stats.tx_errors++;
fec3a23b
FF		 418
419 /* Reset MAC and re-init all registers */
420 r6040_init_mac_regs(dev);
106adf3c
FF		 421}
422
7a47dd7a
SW		 423static struct net_device_stats *r6040_get_stats(struct net_device *dev)
424{
425 struct r6040_private *priv = netdev_priv(dev);
426 void __iomem *ioaddr = priv->base;
427 unsigned long flags;
428
429 spin_lock_irqsave(&priv->lock, flags);
d248fd77
FF		 430 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
431 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
7a47dd7a
SW		 432 spin_unlock_irqrestore(&priv->lock, flags);
433
d248fd77 434 return &dev->stats;
7a47dd7a
SW		 435}
436
437/* Stop RDC MAC and Free the allocated resource */
438static void r6040_down(struct net_device *dev)
439{
440 struct r6040_private *lp = netdev_priv(dev);
441 void __iomem *ioaddr = lp->base;
7a47dd7a
SW		 442 int limit = 2048;
443 u16 *adrp;
444 u16 cmd;
445
446 /* Stop MAC */
447 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
448 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
449 while (limit--) {
450 cmd = ioread16(ioaddr + MCR1);
451 if (cmd & 0x1)
452 break;
453 }
454
455 /* Restore MAC Address to MIDx */
456 adrp = (u16 *) dev->dev_addr;
457 iowrite16(adrp[0], ioaddr + MID_0L);
458 iowrite16(adrp[1], ioaddr + MID_0M);
459 iowrite16(adrp[2], ioaddr + MID_0H);
7a47dd7a
SW		 460}
461
5ac5d616 462static int r6040_close(struct net_device *dev)
7a47dd7a
SW		 463{
464 struct r6040_private *lp = netdev_priv(dev);
58854c6b 465 struct pci_dev *pdev = lp->pdev;
7a47dd7a
SW		 466
467 /* deleted timer */
468 del_timer_sync(&lp->timer);
469
470 spin_lock_irq(&lp->lock);
129cf9a7 471 napi_disable(&lp->napi);
7a47dd7a
SW		 472 netif_stop_queue(dev);
473 r6040_down(dev);
58854c6b
FF		 474
475 free_irq(dev->irq, dev);
476
477 /* Free RX buffer */
478 r6040_free_rxbufs(dev);
479
480 /* Free TX buffer */
481 r6040_free_txbufs(dev);
482
7a47dd7a
SW		 483 spin_unlock_irq(&lp->lock);
484
58854c6b
FF		 485 /* Free Descriptor memory */
486 if (lp->rx_ring) {
487 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
5b5103ec 488 lp->rx_ring = NULL;
58854c6b
FF		 489 }
490
491 if (lp->tx_ring) {
492 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
5b5103ec 493 lp->tx_ring = NULL;
58854c6b
FF		 494 }
495
7a47dd7a
SW		 496 return 0;
497}
498
499/* Status of PHY CHIP */
c6e69bb9 500static int r6040_phy_mode_chk(struct net_device *dev)
7a47dd7a
SW		 501{
502 struct r6040_private *lp = netdev_priv(dev);
503 void __iomem *ioaddr = lp->base;
504 int phy_dat;
505
506 /* PHY Link Status Check */
c6e69bb9 507 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
7a47dd7a
SW		 508 if (!(phy_dat & 0x4))
509 phy_dat = 0x8000; /* Link Failed, full duplex */
510
511 /* PHY Chip Auto-Negotiation Status */
c6e69bb9 512 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1);
7a47dd7a
SW		 513 if (phy_dat & 0x0020) {
514 /* Auto Negotiation Mode */
c6e69bb9
FF		 515 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5);
516 phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4);
7a47dd7a
SW		 517 if (phy_dat & 0x140)
518 /* Force full duplex */
519 phy_dat = 0x8000;
520 else
521 phy_dat = 0;
522 } else {
523 /* Force Mode */
c6e69bb9 524 phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0);
7a47dd7a
SW		 525 if (phy_dat & 0x100)
526 phy_dat = 0x8000;
527 else
528 phy_dat = 0x0000;
529 }
530
531 return phy_dat;
532};
533
534static void r6040_set_carrier(struct mii_if_info *mii)
535{
c6e69bb9 536 if (r6040_phy_mode_chk(mii->dev)) {
7a47dd7a
SW		 537 /* autoneg is off: Link is always assumed to be up */
538 if (!netif_carrier_ok(mii->dev))
539 netif_carrier_on(mii->dev);
540 } else
c6e69bb9 541 r6040_phy_mode_chk(mii->dev);
7a47dd7a
SW		 542}
543
544static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
545{
546 struct r6040_private *lp = netdev_priv(dev);
5ac5d616 547 struct mii_ioctl_data *data = if_mii(rq);
7a47dd7a
SW		 548 int rc;
549
550 if (!netif_running(dev))
551 return -EINVAL;
552 spin_lock_irq(&lp->lock);
553 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
554 spin_unlock_irq(&lp->lock);
555 r6040_set_carrier(&lp->mii_if);
556 return rc;
557}
558
559static int r6040_rx(struct net_device *dev, int limit)
560{
561 struct r6040_private *priv = netdev_priv(dev);
9ca28dc4
FF		 562 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
563 struct sk_buff *skb_ptr, *new_skb;
564 int count = 0;
7a47dd7a
SW		 565 u16 err;
566
9ca28dc4 567 /* Limit not reached and the descriptor belongs to the CPU */
32f565df 568 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
9ca28dc4
FF		 569 /* Read the descriptor status */
570 err = descptr->status;
571 /* Global error status set */
32f565df 572 if (err & DSC_RX_ERR) {
9ca28dc4 573 /* RX dribble */
32f565df 574 if (err & DSC_RX_ERR_DRI)
9ca28dc4
FF		 575 dev->stats.rx_frame_errors++;
576 /* Buffer lenght exceeded */
32f565df 577 if (err & DSC_RX_ERR_BUF)
9ca28dc4
FF		 578 dev->stats.rx_length_errors++;
579 /* Packet too long */
32f565df 580 if (err & DSC_RX_ERR_LONG)
9ca28dc4
FF		 581 dev->stats.rx_length_errors++;
582 /* Packet < 64 bytes */
32f565df 583 if (err & DSC_RX_ERR_RUNT)
9ca28dc4
FF		 584 dev->stats.rx_length_errors++;
585 /* CRC error */
32f565df 586 if (err & DSC_RX_ERR_CRC) {
9ca28dc4
FF		 587 spin_lock(&priv->lock);
588 dev->stats.rx_crc_errors++;
589 spin_unlock(&priv->lock);
7a47dd7a 590 }
9ca28dc4
FF		 591 goto next_descr;
592 }
593
594 /* Packet successfully received */
595 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
596 if (!new_skb) {
597 dev->stats.rx_dropped++;
598 goto next_descr;
7a47dd7a 599 }
9ca28dc4
FF		 600 skb_ptr = descptr->skb_ptr;
601 skb_ptr->dev = priv->dev;
602
603 /* Do not count the CRC */
604 skb_put(skb_ptr, descptr->len - 4);
605 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
606 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
607 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
608
609 /* Send to upper layer */
610 netif_receive_skb(skb_ptr);
9ca28dc4
FF		 611 dev->stats.rx_packets++;
612 dev->stats.rx_bytes += descptr->len - 4;
613
614 /* put new skb into descriptor */
615 descptr->skb_ptr = new_skb;
616 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
617 descptr->skb_ptr->data,
618 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
619
620next_descr:
621 /* put the descriptor back to the MAC */
32f565df 622 descptr->status = DSC_OWNER_MAC;
9ca28dc4
FF		 623 descptr = descptr->vndescp;
624 count++;
7a47dd7a 625 }
9ca28dc4 626 priv->rx_remove_ptr = descptr;
7a47dd7a
SW		 627
628 return count;
629}
630
631static void r6040_tx(struct net_device *dev)
632{
633 struct r6040_private *priv = netdev_priv(dev);
634 struct r6040_descriptor *descptr;
635 void __iomem *ioaddr = priv->base;
636 struct sk_buff *skb_ptr;
637 u16 err;
638
639 spin_lock(&priv->lock);
640 descptr = priv->tx_remove_ptr;
641 while (priv->tx_free_desc < TX_DCNT) {
642 /* Check for errors */
643 err = ioread16(ioaddr + MLSR);
644
d248fd77
FF		 645 if (err & 0x0200)
646 dev->stats.rx_fifo_errors++;
647 if (err & (0x2000 | 0x4000))
648 dev->stats.tx_carrier_errors++;
7a47dd7a 649
32f565df 650 if (descptr->status & DSC_OWNER_MAC)
ec6d2d45 651 break; /* Not complete */
7a47dd7a 652 skb_ptr = descptr->skb_ptr;
ed773b4a 653 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
7a47dd7a
SW		 654 skb_ptr->len, PCI_DMA_TODEVICE);
655 /* Free buffer */
656 dev_kfree_skb_irq(skb_ptr);
657 descptr->skb_ptr = NULL;
658 /* To next descriptor */
659 descptr = descptr->vndescp;
660 priv->tx_free_desc++;
661 }
662 priv->tx_remove_ptr = descptr;
663
664 if (priv->tx_free_desc)
665 netif_wake_queue(dev);
666 spin_unlock(&priv->lock);
667}
668
669static int r6040_poll(struct napi_struct *napi, int budget)
670{
671 struct r6040_private *priv =
672 container_of(napi, struct r6040_private, napi);
673 struct net_device *dev = priv->dev;
674 void __iomem *ioaddr = priv->base;
675 int work_done;
676
677 work_done = r6040_rx(dev, budget);
678
679 if (work_done < budget) {
288379f0 680 napi_complete(napi);
7a47dd7a 681 /* Enable RX interrupt */
e24ddf3a 682 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
7a47dd7a
SW		 683 }
684 return work_done;
685}
686
687/* The RDC interrupt handler. */
688static irqreturn_t r6040_interrupt(int irq, void *dev_id)
689{
690 struct net_device *dev = dev_id;
691 struct r6040_private *lp = netdev_priv(dev);
692 void __iomem *ioaddr = lp->base;
3e7c469f 693 u16 misr, status;
7a47dd7a 694
3e7c469f
JC		 695 /* Save MIER */
696 misr = ioread16(ioaddr + MIER);
7a47dd7a
SW		 697 /* Mask off RDC MAC interrupt */
698 iowrite16(MSK_INT, ioaddr + MIER);
699 /* Read MISR status and clear */
700 status = ioread16(ioaddr + MISR);
701
702 if (status == 0x0000 || status == 0xffff)
703 return IRQ_NONE;
704
705 /* RX interrupt request */
e24ddf3a
FF		 706 if (status & RX_INTS) {
707 if (status & RX_NO_DESC) {
708 /* RX descriptor unavailable */
709 dev->stats.rx_dropped++;
710 dev->stats.rx_missed_errors++;
711 }
712 if (status & RX_FIFO_FULL)
713 dev->stats.rx_fifo_errors++;
714
3d254348 715 /* Mask off RX interrupt */
3e7c469f 716 misr &= ~RX_INTS;
288379f0 717 napi_schedule(&lp->napi);
7a47dd7a
SW		 718 }
719
720 /* TX interrupt request */
e24ddf3a 721 if (status & TX_INTS)
7a47dd7a
SW		 722 r6040_tx(dev);
723
3e7c469f
JC		 724 /* Restore RDC MAC interrupt */
725 iowrite16(misr, ioaddr + MIER);
726
ec6d2d45 727 return IRQ_HANDLED;
7a47dd7a
SW		 728}
729
730#ifdef CONFIG_NET_POLL_CONTROLLER
731static void r6040_poll_controller(struct net_device *dev)
732{
733 disable_irq(dev->irq);
5ac5d616 734 r6040_interrupt(dev->irq, dev);
7a47dd7a
SW		 735 enable_irq(dev->irq);
736}
737#endif
738
7a47dd7a 739/* Init RDC MAC */
3d463419 740static int r6040_up(struct net_device *dev)
7a47dd7a
SW		 741{
742 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a 743 void __iomem *ioaddr = lp->base;
3d463419 744 int ret;
c8014fe1
FF		 745 u16 val;
746
747 /* Check presence of a second PHY */
748 val = r6040_phy_read(ioaddr, lp->phy_addr, 2);
749 if (val == 0xFFFF) {
750 printk(KERN_ERR DRV_NAME " no second PHY attached\n");
751 return -EIO;
752 }
7a47dd7a 753
b4f1255d 754 /* Initialise and alloc RX/TX buffers */
3d463419
FF		 755 r6040_init_txbufs(dev);
756 ret = r6040_alloc_rxbufs(dev);
757 if (ret)
758 return ret;
7a47dd7a 759
7a47dd7a 760 /* Read the PHY ID */
c6e69bb9 761 lp->switch_sig = r6040_phy_read(ioaddr, 0, 2);
7a47dd7a
SW		 762
763 if (lp->switch_sig == ICPLUS_PHY_ID) {
c6e69bb9 764 r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
7a47dd7a
SW		 765 lp->phy_mode = 0x8000;
766 } else {
767 /* PHY Mode Check */
c6e69bb9
FF		 768 r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
769 r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
7a47dd7a
SW		 770
771 if (PHY_MODE == 0x3100)
c6e69bb9 772 lp->phy_mode = r6040_phy_mode_chk(dev);
7a47dd7a
SW		 773 else
774 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
775 }
7a47dd7a 776
fec3a23b 777 /* Set duplex mode */
7a47dd7a 778 lp->mcr0 |= lp->phy_mode;
7a47dd7a
SW		 779
780 /* improve performance (by RDC guys) */
c6e69bb9
FF		 781 r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
782 r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
783 r6040_phy_write(ioaddr, 0, 19, 0x0000);
784 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
7a47dd7a 785
fec3a23b
FF		 786 /* Initialize all MAC registers */
787 r6040_init_mac_regs(dev);
3d463419
FF		 788
789 return 0;
7a47dd7a
SW		 790}
791
792/*
793 A periodic timer routine
794 Polling PHY Chip Link Status
795*/
796static void r6040_timer(unsigned long data)
797{
798 struct net_device *dev = (struct net_device *)data;
e6a9ea10 799 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 800 void __iomem *ioaddr = lp->base;
801 u16 phy_mode;
802
803 /* Polling PHY Chip Status */
804 if (PHY_MODE == 0x3100)
c6e69bb9 805 phy_mode = r6040_phy_mode_chk(dev);
7a47dd7a
SW		 806 else
807 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
808
809 if (phy_mode != lp->phy_mode) {
810 lp->phy_mode = phy_mode;
811 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
812 iowrite16(lp->mcr0, ioaddr);
813 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
814 }
815
816 /* Timer active again */
208aefa2 817 mod_timer(&lp->timer, round_jiffies(jiffies + HZ));
7a47dd7a
SW		 818}
819
820/* Read/set MAC address routines */
821static void r6040_mac_address(struct net_device *dev)
822{
823 struct r6040_private *lp = netdev_priv(dev);
824 void __iomem *ioaddr = lp->base;
825 u16 *adrp;
826
827 /* MAC operation register */
828 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
829 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
830 iowrite16(0, ioaddr + MAC_SM);
c1d69937 831 mdelay(5);
7a47dd7a
SW		 832
833 /* Restore MAC Address */
834 adrp = (u16 *) dev->dev_addr;
835 iowrite16(adrp[0], ioaddr + MID_0L);
836 iowrite16(adrp[1], ioaddr + MID_0M);
837 iowrite16(adrp[2], ioaddr + MID_0H);
838}
839
5ac5d616 840static int r6040_open(struct net_device *dev)
7a47dd7a 841{
5ac5d616 842 struct r6040_private *lp = netdev_priv(dev);
7a47dd7a
SW		 843 int ret;
844
845 /* Request IRQ and Register interrupt handler */
846 ret = request_irq(dev->irq, &r6040_interrupt,
847 IRQF_SHARED, dev->name, dev);
848 if (ret)
849 return ret;
850
851 /* Set MAC address */
852 r6040_mac_address(dev);
853
854 /* Allocate Descriptor memory */
6c323103
FR		 855 lp->rx_ring =
856 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
857 if (!lp->rx_ring)
7a47dd7a
SW		 858 return -ENOMEM;
859
6c323103
FR		 860 lp->tx_ring =
861 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
862 if (!lp->tx_ring) {
863 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
864 lp->rx_ring_dma);
865 return -ENOMEM;
866 }
867
3d463419
FF		 868 ret = r6040_up(dev);
869 if (ret) {
870 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
871 lp->tx_ring_dma);
872 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
873 lp->rx_ring_dma);
874 return ret;
875 }
7a47dd7a
SW		 876
877 napi_enable(&lp->napi);
878 netif_start_queue(dev);
879
106adf3c
FF		 880 /* set and active a timer process */
881 setup_timer(&lp->timer, r6040_timer, (unsigned long) dev);
882 if (lp->switch_sig != ICPLUS_PHY_ID)
883 mod_timer(&lp->timer, jiffies + HZ);
7a47dd7a
SW		 884 return 0;
885}
886
5ac5d616 887static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
7a47dd7a
SW		 888{
889 struct r6040_private *lp = netdev_priv(dev);
890 struct r6040_descriptor *descptr;
891 void __iomem *ioaddr = lp->base;
892 unsigned long flags;
092427be 893 int ret = NETDEV_TX_OK;
7a47dd7a
SW		 894
895 /* Critical Section */
896 spin_lock_irqsave(&lp->lock, flags);
897
898 /* TX resource check */
899 if (!lp->tx_free_desc) {
900 spin_unlock_irqrestore(&lp->lock, flags);
092427be 901 netif_stop_queue(dev);
7a47dd7a 902 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
092427be 903 ret = NETDEV_TX_BUSY;
7a47dd7a
SW		 904 return ret;
905 }
906
907 /* Statistic Counter */
908 dev->stats.tx_packets++;
909 dev->stats.tx_bytes += skb->len;
910 /* Set TX descriptor & Transmit it */
911 lp->tx_free_desc--;
912 descptr = lp->tx_insert_ptr;
913 if (skb->len < MISR)
914 descptr->len = MISR;
915 else
916 descptr->len = skb->len;
917
918 descptr->skb_ptr = skb;
919 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
920 skb->data, skb->len, PCI_DMA_TODEVICE));
32f565df 921 descptr->status = DSC_OWNER_MAC;
7a47dd7a
SW		 922 /* Trigger the MAC to check the TX descriptor */
923 iowrite16(0x01, ioaddr + MTPR);
924 lp->tx_insert_ptr = descptr->vndescp;
925
926 /* If no tx resource, stop */
927 if (!lp->tx_free_desc)
928 netif_stop_queue(dev);
929
930 dev->trans_start = jiffies;
931 spin_unlock_irqrestore(&lp->lock, flags);
932 return ret;
933}
934
5ac5d616 935static void r6040_multicast_list(struct net_device *dev)
7a47dd7a
SW		 936{
937 struct r6040_private *lp = netdev_priv(dev);
938 void __iomem *ioaddr = lp->base;
939 u16 *adrp;
940 u16 reg;
941 unsigned long flags;
942 struct dev_mc_list *dmi = dev->mc_list;
943 int i;
944
945 /* MAC Address */
946 adrp = (u16 *)dev->dev_addr;
947 iowrite16(adrp[0], ioaddr + MID_0L);
948 iowrite16(adrp[1], ioaddr + MID_0M);
949 iowrite16(adrp[2], ioaddr + MID_0H);
950
951 /* Promiscous Mode */
952 spin_lock_irqsave(&lp->lock, flags);
953
954 /* Clear AMCP & PROM bits */
955 reg = ioread16(ioaddr) & ~0x0120;
956 if (dev->flags & IFF_PROMISC) {
957 reg |= 0x0020;
958 lp->mcr0 |= 0x0020;
959 }
960 /* Too many multicast addresses
961 * accept all traffic */
962 else if ((dev->mc_count > MCAST_MAX)
963 || (dev->flags & IFF_ALLMULTI))
964 reg |= 0x0020;
965
966 iowrite16(reg, ioaddr);
967 spin_unlock_irqrestore(&lp->lock, flags);
968
969 /* Build the hash table */
970 if (dev->mc_count > MCAST_MAX) {
971 u16 hash_table[4];
972 u32 crc;
973
974 for (i = 0; i < 4; i++)
975 hash_table[i] = 0;
976
977 for (i = 0; i < dev->mc_count; i++) {
978 char *addrs = dmi->dmi_addr;
979
980 dmi = dmi->next;
981
982 if (!(*addrs & 1))
983 continue;
984
985 crc = ether_crc_le(6, addrs);
986 crc >>= 26;
987 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
988 }
989 /* Write the index of the hash table */
990 for (i = 0; i < 4; i++)
991 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
992 /* Fill the MAC hash tables with their values */
993 iowrite16(hash_table[0], ioaddr + MAR0);
994 iowrite16(hash_table[1], ioaddr + MAR1);
995 iowrite16(hash_table[2], ioaddr + MAR2);
996 iowrite16(hash_table[3], ioaddr + MAR3);
997 }
998 /* Multicast Address 1~4 case */
999 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
1000 adrp = (u16 *)dmi->dmi_addr;
1001 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
1002 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
1003 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
1004 dmi = dmi->next;
1005 }
1006 for (i = dev->mc_count; i < MCAST_MAX; i++) {
1007 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
1008 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
1009 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
1010 }
1011}
1012
1013static void netdev_get_drvinfo(struct net_device *dev,
1014 struct ethtool_drvinfo *info)
1015{
1016 struct r6040_private *rp = netdev_priv(dev);
1017
1018 strcpy(info->driver, DRV_NAME);
1019 strcpy(info->version, DRV_VERSION);
1020 strcpy(info->bus_info, pci_name(rp->pdev));
1021}
1022
1023static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1024{
1025 struct r6040_private *rp = netdev_priv(dev);
1026 int rc;
1027
1028 spin_lock_irq(&rp->lock);
1029 rc = mii_ethtool_gset(&rp->mii_if, cmd);
092427be 1030 spin_unlock_irq(&rp->lock);
7a47dd7a
SW		 1031
1032 return rc;
1033}
1034
1035static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1036{
1037 struct r6040_private *rp = netdev_priv(dev);
1038 int rc;
1039
1040 spin_lock_irq(&rp->lock);
1041 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1042 spin_unlock_irq(&rp->lock);
1043 r6040_set_carrier(&rp->mii_if);
1044
1045 return rc;
1046}
1047
1048static u32 netdev_get_link(struct net_device *dev)
1049{
1050 struct r6040_private *rp = netdev_priv(dev);
1051
1052 return mii_link_ok(&rp->mii_if);
1053}
1054
a7bd89cb 1055static const struct ethtool_ops netdev_ethtool_ops = {
7a47dd7a
SW		 1056 .get_drvinfo = netdev_get_drvinfo,
1057 .get_settings = netdev_get_settings,
1058 .set_settings = netdev_set_settings,
1059 .get_link = netdev_get_link,
1060};
1061
a7bd89cb
SH		 1062static const struct net_device_ops r6040_netdev_ops = {
1063 .ndo_open = r6040_open,
1064 .ndo_stop = r6040_close,
1065 .ndo_start_xmit = r6040_start_xmit,
1066 .ndo_get_stats = r6040_get_stats,
1067 .ndo_set_multicast_list = r6040_multicast_list,
1068 .ndo_change_mtu = eth_change_mtu,
1069 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 1070 .ndo_set_mac_address = eth_mac_addr,
a7bd89cb
SH		 1071 .ndo_do_ioctl = r6040_ioctl,
1072 .ndo_tx_timeout = r6040_tx_timeout,
1073#ifdef CONFIG_NET_POLL_CONTROLLER
1074 .ndo_poll_controller = r6040_poll_controller,
1075#endif
1076};
1077
7a47dd7a
SW		 1078static int __devinit r6040_init_one(struct pci_dev *pdev,
1079 const struct pci_device_id *ent)
1080{
1081 struct net_device *dev;
1082 struct r6040_private *lp;
1083 void __iomem *ioaddr;
1084 int err, io_size = R6040_IO_SIZE;
1085 static int card_idx = -1;
1086 int bar = 0;
1087 long pioaddr;
1088 u16 *adrp;
1089
1090 printk(KERN_INFO "%s\n", version);
1091
1092 err = pci_enable_device(pdev);
1093 if (err)
b0e45390 1094 goto err_out;
7a47dd7a
SW		 1095
1096 /* this should always be supported */
284901a9 1097 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
b0e45390 1098 if (err) {
9a48ce84 1099 printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
7a47dd7a 1100 "not supported by the card\n");
b0e45390 1101 goto err_out;
7a47dd7a 1102 }
284901a9 1103 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
b0e45390 1104 if (err) {
9a48ce84 1105 printk(KERN_ERR DRV_NAME ": 32-bit PCI DMA addresses"
092427be 1106 "not supported by the card\n");
b0e45390 1107 goto err_out;
092427be 1108 }
7a47dd7a
SW		 1109
1110 /* IO Size check */
1111 if (pci_resource_len(pdev, 0) < io_size) {
9a48ce84 1112 printk(KERN_ERR DRV_NAME ": Insufficient PCI resources, aborting\n");
b0e45390
FF		 1113 err = -EIO;
1114 goto err_out;
7a47dd7a
SW		 1115 }
1116
1117 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
1118 pci_set_master(pdev);
1119
1120 dev = alloc_etherdev(sizeof(struct r6040_private));
1121 if (!dev) {
9a48ce84 1122 printk(KERN_ERR DRV_NAME ": Failed to allocate etherdev\n");
b0e45390
FF		 1123 err = -ENOMEM;
1124 goto err_out;
7a47dd7a
SW		 1125 }
1126 SET_NETDEV_DEV(dev, &pdev->dev);
1127 lp = netdev_priv(dev);
7a47dd7a 1128
b0e45390
FF		 1129 err = pci_request_regions(pdev, DRV_NAME);
1130
1131 if (err) {
7a47dd7a 1132 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
b0e45390 1133 goto err_out_free_dev;
7a47dd7a
SW		 1134 }
1135
1136 ioaddr = pci_iomap(pdev, bar, io_size);
1137 if (!ioaddr) {
9a48ce84 1138 printk(KERN_ERR DRV_NAME ": ioremap failed for device %s\n",
7a47dd7a 1139 pci_name(pdev));
b0e45390
FF		 1140 err = -EIO;
1141 goto err_out_free_res;
7a47dd7a 1142 }
84314bf9
FF		 1143 /* If PHY status change register is still set to zero it means the
1144 * bootloader didn't initialize it */
1145 if (ioread16(ioaddr + PHY_CC) == 0)
1146 iowrite16(0x9f07, ioaddr + PHY_CC);
7a47dd7a
SW		 1147
1148 /* Init system & device */
7a47dd7a
SW		 1149 lp->base = ioaddr;
1150 dev->irq = pdev->irq;
1151
1152 spin_lock_init(&lp->lock);
1153 pci_set_drvdata(pdev, dev);
1154
1155 /* Set MAC address */
1156 card_idx++;
1157
1158 adrp = (u16 *)dev->dev_addr;
1159 adrp[0] = ioread16(ioaddr + MID_0L);
1160 adrp[1] = ioread16(ioaddr + MID_0M);
1161 adrp[2] = ioread16(ioaddr + MID_0H);
1162
1d2b1a76
FF		 1163 /* Some bootloader/BIOSes do not initialize
1164 * MAC address, warn about that */
9f113618
FF		 1165 if (!(adrp[0] || adrp[1] || adrp[2])) {
1166 printk(KERN_WARNING DRV_NAME ": MAC address not initialized, generating random\n");
1167 random_ether_addr(dev->dev_addr);
1168 }
1d2b1a76 1169
7a47dd7a
SW		 1170 /* Link new device into r6040_root_dev */
1171 lp->pdev = pdev;
129cf9a7 1172 lp->dev = dev;
7a47dd7a
SW		 1173
1174 /* Init RDC private data */
1175 lp->mcr0 = 0x1002;
1176 lp->phy_addr = phy_table[card_idx];
1177 lp->switch_sig = 0;
1178
1179 /* The RDC-specific entries in the device structure. */
a7bd89cb 1180 dev->netdev_ops = &r6040_netdev_ops;
7a47dd7a 1181 dev->ethtool_ops = &netdev_ethtool_ops;
7a47dd7a 1182 dev->watchdog_timeo = TX_TIMEOUT;
a7bd89cb 1183
7a47dd7a
SW		 1184 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1185 lp->mii_if.dev = dev;
c6e69bb9
FF		 1186 lp->mii_if.mdio_read = r6040_mdio_read;
1187 lp->mii_if.mdio_write = r6040_mdio_write;
7a47dd7a
SW		 1188 lp->mii_if.phy_id = lp->phy_addr;
1189 lp->mii_if.phy_id_mask = 0x1f;
1190 lp->mii_if.reg_num_mask = 0x1f;
1191
1192 /* Register net device. After this dev->name assign */
1193 err = register_netdev(dev);
1194 if (err) {
1195 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
b0e45390 1196 goto err_out_unmap;
7a47dd7a
SW		 1197 }
1198 return 0;
1199
b0e45390
FF		 1200err_out_unmap:
1201 pci_iounmap(pdev, ioaddr);
1202err_out_free_res:
7a47dd7a 1203 pci_release_regions(pdev);
b0e45390 1204err_out_free_dev:
7a47dd7a 1205 free_netdev(dev);
b0e45390 1206err_out:
7a47dd7a
SW		 1207 return err;
1208}
1209
1210static void __devexit r6040_remove_one(struct pci_dev *pdev)
1211{
1212 struct net_device *dev = pci_get_drvdata(pdev);
1213
1214 unregister_netdev(dev);
1215 pci_release_regions(pdev);
1216 free_netdev(dev);
1217 pci_disable_device(pdev);
1218 pci_set_drvdata(pdev, NULL);
1219}
1220
1221
1222static struct pci_device_id r6040_pci_tbl[] = {
5ac5d616
FR		 1223 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1224 { 0 }
7a47dd7a
SW		 1225};
1226MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1227
1228static struct pci_driver r6040_driver = {
5ac5d616 1229 .name = DRV_NAME,
7a47dd7a
SW		 1230 .id_table = r6040_pci_tbl,
1231 .probe = r6040_init_one,
1232 .remove = __devexit_p(r6040_remove_one),
1233};
1234
1235
1236static int __init r6040_init(void)
1237{
1238 return pci_register_driver(&r6040_driver);
1239}
1240
1241
1242static void __exit r6040_cleanup(void)
1243{
1244 pci_unregister_driver(&r6040_driver);
1245}
1246
1247module_init(r6040_init);
1248module_exit(r6040_cleanup);
Linux kernel - Deliverables
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