Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | ||
99f252b0 | 27 | #include <asm/system.h> |
1da177e4 LT |
28 | #include <asm/io.h> |
29 | #include <asm/irq.h> | |
30 | ||
865c652d | 31 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
32 | #define MODULENAME "r8169" |
33 | #define PFX MODULENAME ": " | |
34 | ||
35 | #ifdef RTL8169_DEBUG | |
36 | #define assert(expr) \ | |
5b0384f4 FR |
37 | if (!(expr)) { \ |
38 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 39 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 40 | } |
06fa7358 JP |
41 | #define dprintk(fmt, args...) \ |
42 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
43 | #else |
44 | #define assert(expr) do {} while (0) | |
45 | #define dprintk(fmt, args...) do {} while (0) | |
46 | #endif /* RTL8169_DEBUG */ | |
47 | ||
b57b7e5a | 48 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 49 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 50 | |
1da177e4 LT |
51 | #define TX_BUFFS_AVAIL(tp) \ |
52 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
53 | ||
1da177e4 LT |
54 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
55 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 56 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
57 | |
58 | /* MAC address length */ | |
59 | #define MAC_ADDR_LEN 6 | |
60 | ||
9c14ceaf | 61 | #define MAX_READ_REQUEST_SHIFT 12 |
1da177e4 LT |
62 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
63 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
64 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
07d3f51f | 65 | #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
1da177e4 LT |
66 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
67 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
68 | ||
69 | #define R8169_REGS_SIZE 256 | |
70 | #define R8169_NAPI_WEIGHT 64 | |
71 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
72 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
73 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
74 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
75 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
76 | ||
77 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
78 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
79 | ||
ea8dbdd1 | 80 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
81 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | |
e1564ec9 FR |
82 | #define RTL_EEPROM_SIG_ADDR 0x0000 |
83 | ||
1da177e4 LT |
84 | /* write/read MMIO register */ |
85 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
86 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
87 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
88 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
89 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
90 | #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) | |
91 | ||
92 | enum mac_version { | |
f21b75e9 | 93 | RTL_GIGA_MAC_NONE = 0x00, |
ba6eb6ee FR |
94 | RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
95 | RTL_GIGA_MAC_VER_02 = 0x02, // 8169S | |
96 | RTL_GIGA_MAC_VER_03 = 0x03, // 8110S | |
97 | RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB | |
98 | RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd | |
6dccd16b | 99 | RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
2857ffb7 FR |
100 | RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
101 | RTL_GIGA_MAC_VER_08 = 0x08, // 8102e | |
102 | RTL_GIGA_MAC_VER_09 = 0x09, // 8102e | |
103 | RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e | |
2dd99530 | 104 | RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
e3cf0cc0 FR |
105 | RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
106 | RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb | |
107 | RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? | |
108 | RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? | |
109 | RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec | |
110 | RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf | |
111 | RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP | |
112 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C | |
197ff761 | 113 | RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
6fb07058 | 114 | RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
ef3386f0 | 115 | RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
7f3e3d3a | 116 | RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP |
5b538df9 FR |
117 | RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP |
118 | RTL_GIGA_MAC_VER_25 = 0x19 // 8168D | |
1da177e4 LT |
119 | }; |
120 | ||
1da177e4 LT |
121 | #define _R(NAME,MAC,MASK) \ |
122 | { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } | |
123 | ||
3c6bee1d | 124 | static const struct { |
1da177e4 LT |
125 | const char *name; |
126 | u8 mac_version; | |
127 | u32 RxConfigMask; /* Clears the bits supported by this chip */ | |
128 | } rtl_chip_info[] = { | |
ba6eb6ee FR |
129 | _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
130 | _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S | |
131 | _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S | |
132 | _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB | |
133 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd | |
6dccd16b | 134 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
2857ffb7 FR |
135 | _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
136 | _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E | |
137 | _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E | |
138 | _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E | |
bcf0bf90 FR |
139 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
140 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E | |
141 | _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 | |
142 | _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 | |
e3cf0cc0 FR |
143 | _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
144 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E | |
145 | _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E | |
146 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E | |
147 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E | |
197ff761 | 148 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
6fb07058 | 149 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
ef3386f0 | 150 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
7f3e3d3a | 151 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E |
5b538df9 FR |
152 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E |
153 | _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E | |
1da177e4 LT |
154 | }; |
155 | #undef _R | |
156 | ||
bcf0bf90 FR |
157 | enum cfg_version { |
158 | RTL_CFG_0 = 0x00, | |
159 | RTL_CFG_1, | |
160 | RTL_CFG_2 | |
161 | }; | |
162 | ||
07ce4064 FR |
163 | static void rtl_hw_start_8169(struct net_device *); |
164 | static void rtl_hw_start_8168(struct net_device *); | |
165 | static void rtl_hw_start_8101(struct net_device *); | |
166 | ||
1da177e4 | 167 | static struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 168 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 169 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 170 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 171 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
172 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
173 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
bc1660b5 | 174 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
175 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
176 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
177 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
178 | { 0x0001, 0x8168, |
179 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
180 | {0,}, |
181 | }; | |
182 | ||
183 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
184 | ||
185 | static int rx_copybreak = 200; | |
186 | static int use_dac; | |
b57b7e5a SH |
187 | static struct { |
188 | u32 msg_enable; | |
189 | } debug = { -1 }; | |
1da177e4 | 190 | |
07d3f51f FR |
191 | enum rtl_registers { |
192 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 193 | MAC4 = 4, |
07d3f51f FR |
194 | MAR0 = 8, /* Multicast filter. */ |
195 | CounterAddrLow = 0x10, | |
196 | CounterAddrHigh = 0x14, | |
197 | TxDescStartAddrLow = 0x20, | |
198 | TxDescStartAddrHigh = 0x24, | |
199 | TxHDescStartAddrLow = 0x28, | |
200 | TxHDescStartAddrHigh = 0x2c, | |
201 | FLASH = 0x30, | |
202 | ERSR = 0x36, | |
203 | ChipCmd = 0x37, | |
204 | TxPoll = 0x38, | |
205 | IntrMask = 0x3c, | |
206 | IntrStatus = 0x3e, | |
207 | TxConfig = 0x40, | |
208 | RxConfig = 0x44, | |
209 | RxMissed = 0x4c, | |
210 | Cfg9346 = 0x50, | |
211 | Config0 = 0x51, | |
212 | Config1 = 0x52, | |
213 | Config2 = 0x53, | |
214 | Config3 = 0x54, | |
215 | Config4 = 0x55, | |
216 | Config5 = 0x56, | |
217 | MultiIntr = 0x5c, | |
218 | PHYAR = 0x60, | |
07d3f51f FR |
219 | PHYstatus = 0x6c, |
220 | RxMaxSize = 0xda, | |
221 | CPlusCmd = 0xe0, | |
222 | IntrMitigate = 0xe2, | |
223 | RxDescAddrLow = 0xe4, | |
224 | RxDescAddrHigh = 0xe8, | |
225 | EarlyTxThres = 0xec, | |
226 | FuncEvent = 0xf0, | |
227 | FuncEventMask = 0xf4, | |
228 | FuncPresetState = 0xf8, | |
229 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
230 | }; |
231 | ||
f162a5d1 FR |
232 | enum rtl8110_registers { |
233 | TBICSR = 0x64, | |
234 | TBI_ANAR = 0x68, | |
235 | TBI_LPAR = 0x6a, | |
236 | }; | |
237 | ||
238 | enum rtl8168_8101_registers { | |
239 | CSIDR = 0x64, | |
240 | CSIAR = 0x68, | |
241 | #define CSIAR_FLAG 0x80000000 | |
242 | #define CSIAR_WRITE_CMD 0x80000000 | |
243 | #define CSIAR_BYTE_ENABLE 0x0f | |
244 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
245 | #define CSIAR_ADDR_MASK 0x0fff | |
246 | ||
247 | EPHYAR = 0x80, | |
248 | #define EPHYAR_FLAG 0x80000000 | |
249 | #define EPHYAR_WRITE_CMD 0x80000000 | |
250 | #define EPHYAR_REG_MASK 0x1f | |
251 | #define EPHYAR_REG_SHIFT 16 | |
252 | #define EPHYAR_DATA_MASK 0xffff | |
253 | DBG_REG = 0xd1, | |
254 | #define FIX_NAK_1 (1 << 4) | |
255 | #define FIX_NAK_2 (1 << 3) | |
256 | }; | |
257 | ||
07d3f51f | 258 | enum rtl_register_content { |
1da177e4 | 259 | /* InterruptStatusBits */ |
07d3f51f FR |
260 | SYSErr = 0x8000, |
261 | PCSTimeout = 0x4000, | |
262 | SWInt = 0x0100, | |
263 | TxDescUnavail = 0x0080, | |
264 | RxFIFOOver = 0x0040, | |
265 | LinkChg = 0x0020, | |
266 | RxOverflow = 0x0010, | |
267 | TxErr = 0x0008, | |
268 | TxOK = 0x0004, | |
269 | RxErr = 0x0002, | |
270 | RxOK = 0x0001, | |
1da177e4 LT |
271 | |
272 | /* RxStatusDesc */ | |
9dccf611 FR |
273 | RxFOVF = (1 << 23), |
274 | RxRWT = (1 << 22), | |
275 | RxRES = (1 << 21), | |
276 | RxRUNT = (1 << 20), | |
277 | RxCRC = (1 << 19), | |
1da177e4 LT |
278 | |
279 | /* ChipCmdBits */ | |
07d3f51f FR |
280 | CmdReset = 0x10, |
281 | CmdRxEnb = 0x08, | |
282 | CmdTxEnb = 0x04, | |
283 | RxBufEmpty = 0x01, | |
1da177e4 | 284 | |
275391a4 FR |
285 | /* TXPoll register p.5 */ |
286 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
287 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
288 | FSWInt = 0x01, /* Forced software interrupt */ | |
289 | ||
1da177e4 | 290 | /* Cfg9346Bits */ |
07d3f51f FR |
291 | Cfg9346_Lock = 0x00, |
292 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
293 | |
294 | /* rx_mode_bits */ | |
07d3f51f FR |
295 | AcceptErr = 0x20, |
296 | AcceptRunt = 0x10, | |
297 | AcceptBroadcast = 0x08, | |
298 | AcceptMulticast = 0x04, | |
299 | AcceptMyPhys = 0x02, | |
300 | AcceptAllPhys = 0x01, | |
1da177e4 LT |
301 | |
302 | /* RxConfigBits */ | |
07d3f51f FR |
303 | RxCfgFIFOShift = 13, |
304 | RxCfgDMAShift = 8, | |
1da177e4 LT |
305 | |
306 | /* TxConfigBits */ | |
307 | TxInterFrameGapShift = 24, | |
308 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
309 | ||
5d06a99f | 310 | /* Config1 register p.24 */ |
f162a5d1 FR |
311 | LEDS1 = (1 << 7), |
312 | LEDS0 = (1 << 6), | |
fbac58fc | 313 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
f162a5d1 FR |
314 | Speed_down = (1 << 4), |
315 | MEMMAP = (1 << 3), | |
316 | IOMAP = (1 << 2), | |
317 | VPD = (1 << 1), | |
5d06a99f FR |
318 | PMEnable = (1 << 0), /* Power Management Enable */ |
319 | ||
6dccd16b FR |
320 | /* Config2 register p. 25 */ |
321 | PCI_Clock_66MHz = 0x01, | |
322 | PCI_Clock_33MHz = 0x00, | |
323 | ||
61a4dcc2 FR |
324 | /* Config3 register p.25 */ |
325 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
326 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
f162a5d1 | 327 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 328 | |
5d06a99f | 329 | /* Config5 register p.27 */ |
61a4dcc2 FR |
330 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
331 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
332 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
333 | LanWake = (1 << 1), /* LanWake enable/disable */ | |
5d06a99f FR |
334 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
335 | ||
1da177e4 LT |
336 | /* TBICSR p.28 */ |
337 | TBIReset = 0x80000000, | |
338 | TBILoopback = 0x40000000, | |
339 | TBINwEnable = 0x20000000, | |
340 | TBINwRestart = 0x10000000, | |
341 | TBILinkOk = 0x02000000, | |
342 | TBINwComplete = 0x01000000, | |
343 | ||
344 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
345 | EnableBist = (1 << 15), // 8168 8101 |
346 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
347 | Normal_mode = (1 << 13), // unused | |
348 | Force_half_dup = (1 << 12), // 8168 8101 | |
349 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
350 | Force_txflow_en = (1 << 10), // 8168 8101 | |
351 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
352 | ASF = (1 << 8), // 8168 8101 | |
353 | PktCntrDisable = (1 << 7), // 8168 8101 | |
354 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
355 | RxVlan = (1 << 6), |
356 | RxChkSum = (1 << 5), | |
357 | PCIDAC = (1 << 4), | |
358 | PCIMulRW = (1 << 3), | |
0e485150 FR |
359 | INTT_0 = 0x0000, // 8168 |
360 | INTT_1 = 0x0001, // 8168 | |
361 | INTT_2 = 0x0002, // 8168 | |
362 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
363 | |
364 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
365 | TBI_Enable = 0x80, |
366 | TxFlowCtrl = 0x40, | |
367 | RxFlowCtrl = 0x20, | |
368 | _1000bpsF = 0x10, | |
369 | _100bps = 0x08, | |
370 | _10bps = 0x04, | |
371 | LinkStatus = 0x02, | |
372 | FullDup = 0x01, | |
1da177e4 | 373 | |
1da177e4 | 374 | /* _TBICSRBit */ |
07d3f51f | 375 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
376 | |
377 | /* DumpCounterCommand */ | |
07d3f51f | 378 | CounterDump = 0x8, |
1da177e4 LT |
379 | }; |
380 | ||
07d3f51f | 381 | enum desc_status_bit { |
1da177e4 LT |
382 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
383 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
384 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
385 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
386 | ||
387 | /* Tx private */ | |
388 | LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ | |
389 | MSSShift = 16, /* MSS value position */ | |
390 | MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ | |
391 | IPCS = (1 << 18), /* Calculate IP checksum */ | |
392 | UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ | |
393 | TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ | |
394 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
395 | ||
396 | /* Rx private */ | |
397 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
398 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
399 | ||
400 | #define RxProtoUDP (PID1) | |
401 | #define RxProtoTCP (PID0) | |
402 | #define RxProtoIP (PID1 | PID0) | |
403 | #define RxProtoMask RxProtoIP | |
404 | ||
405 | IPFail = (1 << 16), /* IP checksum failed */ | |
406 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
407 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
408 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
409 | }; | |
410 | ||
411 | #define RsvdMask 0x3fffc000 | |
412 | ||
413 | struct TxDesc { | |
6cccd6e7 REB |
414 | __le32 opts1; |
415 | __le32 opts2; | |
416 | __le64 addr; | |
1da177e4 LT |
417 | }; |
418 | ||
419 | struct RxDesc { | |
6cccd6e7 REB |
420 | __le32 opts1; |
421 | __le32 opts2; | |
422 | __le64 addr; | |
1da177e4 LT |
423 | }; |
424 | ||
425 | struct ring_info { | |
426 | struct sk_buff *skb; | |
427 | u32 len; | |
428 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
429 | }; | |
430 | ||
f23e7fda | 431 | enum features { |
ccdffb9a FR |
432 | RTL_FEATURE_WOL = (1 << 0), |
433 | RTL_FEATURE_MSI = (1 << 1), | |
434 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
435 | }; |
436 | ||
355423d0 IV |
437 | struct rtl8169_counters { |
438 | __le64 tx_packets; | |
439 | __le64 rx_packets; | |
440 | __le64 tx_errors; | |
441 | __le32 rx_errors; | |
442 | __le16 rx_missed; | |
443 | __le16 align_errors; | |
444 | __le32 tx_one_collision; | |
445 | __le32 tx_multi_collision; | |
446 | __le64 rx_unicast; | |
447 | __le64 rx_broadcast; | |
448 | __le32 rx_multicast; | |
449 | __le16 tx_aborted; | |
450 | __le16 tx_underun; | |
451 | }; | |
452 | ||
1da177e4 LT |
453 | struct rtl8169_private { |
454 | void __iomem *mmio_addr; /* memory map physical address */ | |
455 | struct pci_dev *pci_dev; /* Index of PCI device */ | |
c4028958 | 456 | struct net_device *dev; |
bea3348e | 457 | struct napi_struct napi; |
1da177e4 | 458 | spinlock_t lock; /* spin lock flag */ |
b57b7e5a | 459 | u32 msg_enable; |
1da177e4 LT |
460 | int chipset; |
461 | int mac_version; | |
1da177e4 LT |
462 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
463 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
464 | u32 dirty_rx; | |
465 | u32 dirty_tx; | |
466 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
467 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
468 | dma_addr_t TxPhyAddr; | |
469 | dma_addr_t RxPhyAddr; | |
470 | struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ | |
471 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ | |
bcf0bf90 | 472 | unsigned align; |
1da177e4 LT |
473 | unsigned rx_buf_sz; |
474 | struct timer_list timer; | |
475 | u16 cp_cmd; | |
0e485150 FR |
476 | u16 intr_event; |
477 | u16 napi_event; | |
1da177e4 | 478 | u16 intr_mask; |
1da177e4 LT |
479 | int phy_1000_ctrl_reg; |
480 | #ifdef CONFIG_R8169_VLAN | |
481 | struct vlan_group *vlgrp; | |
482 | #endif | |
483 | int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); | |
ccdffb9a | 484 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
1da177e4 | 485 | void (*phy_reset_enable)(void __iomem *); |
07ce4064 | 486 | void (*hw_start)(struct net_device *); |
1da177e4 LT |
487 | unsigned int (*phy_reset_pending)(void __iomem *); |
488 | unsigned int (*link_ok)(void __iomem *); | |
8b4ab28d | 489 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
9c14ceaf | 490 | int pcie_cap; |
c4028958 | 491 | struct delayed_work task; |
f23e7fda | 492 | unsigned features; |
ccdffb9a FR |
493 | |
494 | struct mii_if_info mii; | |
355423d0 | 495 | struct rtl8169_counters counters; |
1da177e4 LT |
496 | }; |
497 | ||
979b6c13 | 498 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 499 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 500 | module_param(rx_copybreak, int, 0); |
1b7efd58 | 501 | MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
1da177e4 LT |
502 | module_param(use_dac, int, 0); |
503 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); | |
b57b7e5a SH |
504 | module_param_named(debug, debug.msg_enable, int, 0); |
505 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
506 | MODULE_LICENSE("GPL"); |
507 | MODULE_VERSION(RTL8169_VERSION); | |
508 | ||
509 | static int rtl8169_open(struct net_device *dev); | |
61357325 SH |
510 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
511 | struct net_device *dev); | |
7d12e780 | 512 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
1da177e4 | 513 | static int rtl8169_init_ring(struct net_device *dev); |
07ce4064 | 514 | static void rtl_hw_start(struct net_device *dev); |
1da177e4 | 515 | static int rtl8169_close(struct net_device *dev); |
07ce4064 | 516 | static void rtl_set_rx_mode(struct net_device *dev); |
1da177e4 | 517 | static void rtl8169_tx_timeout(struct net_device *dev); |
4dcb7d33 | 518 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
1da177e4 | 519 | static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
bea3348e | 520 | void __iomem *, u32 budget); |
4dcb7d33 | 521 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
1da177e4 | 522 | static void rtl8169_down(struct net_device *dev); |
99f252b0 | 523 | static void rtl8169_rx_clear(struct rtl8169_private *tp); |
bea3348e | 524 | static int rtl8169_poll(struct napi_struct *napi, int budget); |
1da177e4 | 525 | |
1da177e4 | 526 | static const unsigned int rtl8169_rx_config = |
5b0384f4 | 527 | (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
1da177e4 | 528 | |
07d3f51f | 529 | static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
1da177e4 LT |
530 | { |
531 | int i; | |
532 | ||
a6baf3af | 533 | RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 534 | |
2371408c | 535 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
536 | /* |
537 | * Check if the RTL8169 has completed writing to the specified | |
538 | * MII register. | |
539 | */ | |
5b0384f4 | 540 | if (!(RTL_R32(PHYAR) & 0x80000000)) |
1da177e4 | 541 | break; |
2371408c | 542 | udelay(25); |
1da177e4 LT |
543 | } |
544 | } | |
545 | ||
07d3f51f | 546 | static int mdio_read(void __iomem *ioaddr, int reg_addr) |
1da177e4 LT |
547 | { |
548 | int i, value = -1; | |
549 | ||
a6baf3af | 550 | RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
1da177e4 | 551 | |
2371408c | 552 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
553 | /* |
554 | * Check if the RTL8169 has completed retrieving data from | |
555 | * the specified MII register. | |
556 | */ | |
1da177e4 | 557 | if (RTL_R32(PHYAR) & 0x80000000) { |
a6baf3af | 558 | value = RTL_R32(PHYAR) & 0xffff; |
1da177e4 LT |
559 | break; |
560 | } | |
2371408c | 561 | udelay(25); |
1da177e4 LT |
562 | } |
563 | return value; | |
564 | } | |
565 | ||
dacf8154 FR |
566 | static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) |
567 | { | |
568 | mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); | |
569 | } | |
570 | ||
ccdffb9a FR |
571 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
572 | int val) | |
573 | { | |
574 | struct rtl8169_private *tp = netdev_priv(dev); | |
575 | void __iomem *ioaddr = tp->mmio_addr; | |
576 | ||
577 | mdio_write(ioaddr, location, val); | |
578 | } | |
579 | ||
580 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
581 | { | |
582 | struct rtl8169_private *tp = netdev_priv(dev); | |
583 | void __iomem *ioaddr = tp->mmio_addr; | |
584 | ||
585 | return mdio_read(ioaddr, location); | |
586 | } | |
587 | ||
dacf8154 FR |
588 | static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
589 | { | |
590 | unsigned int i; | |
591 | ||
592 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
593 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
594 | ||
595 | for (i = 0; i < 100; i++) { | |
596 | if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) | |
597 | break; | |
598 | udelay(10); | |
599 | } | |
600 | } | |
601 | ||
602 | static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) | |
603 | { | |
604 | u16 value = 0xffff; | |
605 | unsigned int i; | |
606 | ||
607 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
608 | ||
609 | for (i = 0; i < 100; i++) { | |
610 | if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { | |
611 | value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; | |
612 | break; | |
613 | } | |
614 | udelay(10); | |
615 | } | |
616 | ||
617 | return value; | |
618 | } | |
619 | ||
620 | static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) | |
621 | { | |
622 | unsigned int i; | |
623 | ||
624 | RTL_W32(CSIDR, value); | |
625 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
626 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
627 | ||
628 | for (i = 0; i < 100; i++) { | |
629 | if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) | |
630 | break; | |
631 | udelay(10); | |
632 | } | |
633 | } | |
634 | ||
635 | static u32 rtl_csi_read(void __iomem *ioaddr, int addr) | |
636 | { | |
637 | u32 value = ~0x00; | |
638 | unsigned int i; | |
639 | ||
640 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
641 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
642 | ||
643 | for (i = 0; i < 100; i++) { | |
644 | if (RTL_R32(CSIAR) & CSIAR_FLAG) { | |
645 | value = RTL_R32(CSIDR); | |
646 | break; | |
647 | } | |
648 | udelay(10); | |
649 | } | |
650 | ||
651 | return value; | |
652 | } | |
653 | ||
1da177e4 LT |
654 | static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
655 | { | |
656 | RTL_W16(IntrMask, 0x0000); | |
657 | ||
658 | RTL_W16(IntrStatus, 0xffff); | |
659 | } | |
660 | ||
661 | static void rtl8169_asic_down(void __iomem *ioaddr) | |
662 | { | |
663 | RTL_W8(ChipCmd, 0x00); | |
664 | rtl8169_irq_mask_and_ack(ioaddr); | |
665 | RTL_R16(CPlusCmd); | |
666 | } | |
667 | ||
668 | static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) | |
669 | { | |
670 | return RTL_R32(TBICSR) & TBIReset; | |
671 | } | |
672 | ||
673 | static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) | |
674 | { | |
64e4bfb4 | 675 | return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
676 | } |
677 | ||
678 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
679 | { | |
680 | return RTL_R32(TBICSR) & TBILinkOk; | |
681 | } | |
682 | ||
683 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
684 | { | |
685 | return RTL_R8(PHYstatus) & LinkStatus; | |
686 | } | |
687 | ||
688 | static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) | |
689 | { | |
690 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); | |
691 | } | |
692 | ||
693 | static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) | |
694 | { | |
695 | unsigned int val; | |
696 | ||
9e0db8ef FR |
697 | val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
698 | mdio_write(ioaddr, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
699 | } |
700 | ||
701 | static void rtl8169_check_link_status(struct net_device *dev, | |
07d3f51f FR |
702 | struct rtl8169_private *tp, |
703 | void __iomem *ioaddr) | |
1da177e4 LT |
704 | { |
705 | unsigned long flags; | |
706 | ||
707 | spin_lock_irqsave(&tp->lock, flags); | |
708 | if (tp->link_ok(ioaddr)) { | |
709 | netif_carrier_on(dev); | |
b57b7e5a SH |
710 | if (netif_msg_ifup(tp)) |
711 | printk(KERN_INFO PFX "%s: link up\n", dev->name); | |
712 | } else { | |
713 | if (netif_msg_ifdown(tp)) | |
714 | printk(KERN_INFO PFX "%s: link down\n", dev->name); | |
1da177e4 | 715 | netif_carrier_off(dev); |
b57b7e5a | 716 | } |
1da177e4 LT |
717 | spin_unlock_irqrestore(&tp->lock, flags); |
718 | } | |
719 | ||
61a4dcc2 FR |
720 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
721 | { | |
722 | struct rtl8169_private *tp = netdev_priv(dev); | |
723 | void __iomem *ioaddr = tp->mmio_addr; | |
724 | u8 options; | |
725 | ||
726 | wol->wolopts = 0; | |
727 | ||
728 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) | |
729 | wol->supported = WAKE_ANY; | |
730 | ||
731 | spin_lock_irq(&tp->lock); | |
732 | ||
733 | options = RTL_R8(Config1); | |
734 | if (!(options & PMEnable)) | |
735 | goto out_unlock; | |
736 | ||
737 | options = RTL_R8(Config3); | |
738 | if (options & LinkUp) | |
739 | wol->wolopts |= WAKE_PHY; | |
740 | if (options & MagicPacket) | |
741 | wol->wolopts |= WAKE_MAGIC; | |
742 | ||
743 | options = RTL_R8(Config5); | |
744 | if (options & UWF) | |
745 | wol->wolopts |= WAKE_UCAST; | |
746 | if (options & BWF) | |
5b0384f4 | 747 | wol->wolopts |= WAKE_BCAST; |
61a4dcc2 | 748 | if (options & MWF) |
5b0384f4 | 749 | wol->wolopts |= WAKE_MCAST; |
61a4dcc2 FR |
750 | |
751 | out_unlock: | |
752 | spin_unlock_irq(&tp->lock); | |
753 | } | |
754 | ||
755 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
756 | { | |
757 | struct rtl8169_private *tp = netdev_priv(dev); | |
758 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 759 | unsigned int i; |
61a4dcc2 FR |
760 | static struct { |
761 | u32 opt; | |
762 | u16 reg; | |
763 | u8 mask; | |
764 | } cfg[] = { | |
765 | { WAKE_ANY, Config1, PMEnable }, | |
766 | { WAKE_PHY, Config3, LinkUp }, | |
767 | { WAKE_MAGIC, Config3, MagicPacket }, | |
768 | { WAKE_UCAST, Config5, UWF }, | |
769 | { WAKE_BCAST, Config5, BWF }, | |
770 | { WAKE_MCAST, Config5, MWF }, | |
771 | { WAKE_ANY, Config5, LanWake } | |
772 | }; | |
773 | ||
774 | spin_lock_irq(&tp->lock); | |
775 | ||
776 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
777 | ||
778 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
779 | u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; | |
780 | if (wol->wolopts & cfg[i].opt) | |
781 | options |= cfg[i].mask; | |
782 | RTL_W8(cfg[i].reg, options); | |
783 | } | |
784 | ||
785 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
786 | ||
f23e7fda FR |
787 | if (wol->wolopts) |
788 | tp->features |= RTL_FEATURE_WOL; | |
789 | else | |
790 | tp->features &= ~RTL_FEATURE_WOL; | |
8b76ab39 | 791 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
61a4dcc2 FR |
792 | |
793 | spin_unlock_irq(&tp->lock); | |
794 | ||
795 | return 0; | |
796 | } | |
797 | ||
1da177e4 LT |
798 | static void rtl8169_get_drvinfo(struct net_device *dev, |
799 | struct ethtool_drvinfo *info) | |
800 | { | |
801 | struct rtl8169_private *tp = netdev_priv(dev); | |
802 | ||
803 | strcpy(info->driver, MODULENAME); | |
804 | strcpy(info->version, RTL8169_VERSION); | |
805 | strcpy(info->bus_info, pci_name(tp->pci_dev)); | |
806 | } | |
807 | ||
808 | static int rtl8169_get_regs_len(struct net_device *dev) | |
809 | { | |
810 | return R8169_REGS_SIZE; | |
811 | } | |
812 | ||
813 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
814 | u8 autoneg, u16 speed, u8 duplex) | |
815 | { | |
816 | struct rtl8169_private *tp = netdev_priv(dev); | |
817 | void __iomem *ioaddr = tp->mmio_addr; | |
818 | int ret = 0; | |
819 | u32 reg; | |
820 | ||
821 | reg = RTL_R32(TBICSR); | |
822 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
823 | (duplex == DUPLEX_FULL)) { | |
824 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
825 | } else if (autoneg == AUTONEG_ENABLE) | |
826 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
827 | else { | |
b57b7e5a SH |
828 | if (netif_msg_link(tp)) { |
829 | printk(KERN_WARNING "%s: " | |
830 | "incorrect speed setting refused in TBI mode\n", | |
831 | dev->name); | |
832 | } | |
1da177e4 LT |
833 | ret = -EOPNOTSUPP; |
834 | } | |
835 | ||
836 | return ret; | |
837 | } | |
838 | ||
839 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
840 | u8 autoneg, u16 speed, u8 duplex) | |
841 | { | |
842 | struct rtl8169_private *tp = netdev_priv(dev); | |
843 | void __iomem *ioaddr = tp->mmio_addr; | |
3577aa1b | 844 | int giga_ctrl, bmcr; |
1da177e4 LT |
845 | |
846 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 847 | int auto_nego; |
848 | ||
849 | auto_nego = mdio_read(ioaddr, MII_ADVERTISE); | |
64e4bfb4 FR |
850 | auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
851 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
3577aa1b | 852 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 853 | |
3577aa1b | 854 | giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); |
855 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
bcf0bf90 | 856 | |
3577aa1b | 857 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
858 | if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && | |
859 | (tp->mac_version != RTL_GIGA_MAC_VER_08) && | |
860 | (tp->mac_version != RTL_GIGA_MAC_VER_09) && | |
861 | (tp->mac_version != RTL_GIGA_MAC_VER_10) && | |
862 | (tp->mac_version != RTL_GIGA_MAC_VER_13) && | |
863 | (tp->mac_version != RTL_GIGA_MAC_VER_14) && | |
864 | (tp->mac_version != RTL_GIGA_MAC_VER_15) && | |
865 | (tp->mac_version != RTL_GIGA_MAC_VER_16)) { | |
866 | giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
867 | } else if (netif_msg_link(tp)) { | |
bcf0bf90 FR |
868 | printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", |
869 | dev->name); | |
870 | } | |
1da177e4 | 871 | |
3577aa1b | 872 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
873 | ||
874 | if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || | |
875 | (tp->mac_version == RTL_GIGA_MAC_VER_12) || | |
876 | (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { | |
877 | /* | |
878 | * Wake up the PHY. | |
879 | * Vendor specific (0x1f) and reserved (0x0e) MII | |
880 | * registers. | |
881 | */ | |
882 | mdio_write(ioaddr, 0x1f, 0x0000); | |
883 | mdio_write(ioaddr, 0x0e, 0x0000); | |
884 | } | |
885 | ||
886 | mdio_write(ioaddr, MII_ADVERTISE, auto_nego); | |
887 | mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); | |
888 | } else { | |
889 | giga_ctrl = 0; | |
890 | ||
891 | if (speed == SPEED_10) | |
892 | bmcr = 0; | |
893 | else if (speed == SPEED_100) | |
894 | bmcr = BMCR_SPEED100; | |
895 | else | |
896 | return -EINVAL; | |
897 | ||
898 | if (duplex == DUPLEX_FULL) | |
899 | bmcr |= BMCR_FULLDPLX; | |
623a1593 | 900 | |
2584fbc3 | 901 | mdio_write(ioaddr, 0x1f, 0x0000); |
2584fbc3 RS |
902 | } |
903 | ||
1da177e4 LT |
904 | tp->phy_1000_ctrl_reg = giga_ctrl; |
905 | ||
3577aa1b | 906 | mdio_write(ioaddr, MII_BMCR, bmcr); |
907 | ||
908 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
909 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
910 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { | |
911 | mdio_write(ioaddr, 0x17, 0x2138); | |
912 | mdio_write(ioaddr, 0x0e, 0x0260); | |
913 | } else { | |
914 | mdio_write(ioaddr, 0x17, 0x2108); | |
915 | mdio_write(ioaddr, 0x0e, 0x0000); | |
916 | } | |
917 | } | |
918 | ||
1da177e4 LT |
919 | return 0; |
920 | } | |
921 | ||
922 | static int rtl8169_set_speed(struct net_device *dev, | |
923 | u8 autoneg, u16 speed, u8 duplex) | |
924 | { | |
925 | struct rtl8169_private *tp = netdev_priv(dev); | |
926 | int ret; | |
927 | ||
928 | ret = tp->set_speed(dev, autoneg, speed, duplex); | |
929 | ||
64e4bfb4 | 930 | if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
931 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
932 | ||
933 | return ret; | |
934 | } | |
935 | ||
936 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
937 | { | |
938 | struct rtl8169_private *tp = netdev_priv(dev); | |
939 | unsigned long flags; | |
940 | int ret; | |
941 | ||
942 | spin_lock_irqsave(&tp->lock, flags); | |
943 | ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); | |
944 | spin_unlock_irqrestore(&tp->lock, flags); | |
5b0384f4 | 945 | |
1da177e4 LT |
946 | return ret; |
947 | } | |
948 | ||
949 | static u32 rtl8169_get_rx_csum(struct net_device *dev) | |
950 | { | |
951 | struct rtl8169_private *tp = netdev_priv(dev); | |
952 | ||
953 | return tp->cp_cmd & RxChkSum; | |
954 | } | |
955 | ||
956 | static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) | |
957 | { | |
958 | struct rtl8169_private *tp = netdev_priv(dev); | |
959 | void __iomem *ioaddr = tp->mmio_addr; | |
960 | unsigned long flags; | |
961 | ||
962 | spin_lock_irqsave(&tp->lock, flags); | |
963 | ||
964 | if (data) | |
965 | tp->cp_cmd |= RxChkSum; | |
966 | else | |
967 | tp->cp_cmd &= ~RxChkSum; | |
968 | ||
969 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
970 | RTL_R16(CPlusCmd); | |
971 | ||
972 | spin_unlock_irqrestore(&tp->lock, flags); | |
973 | ||
974 | return 0; | |
975 | } | |
976 | ||
977 | #ifdef CONFIG_R8169_VLAN | |
978 | ||
979 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, | |
980 | struct sk_buff *skb) | |
981 | { | |
982 | return (tp->vlgrp && vlan_tx_tag_present(skb)) ? | |
983 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; | |
984 | } | |
985 | ||
986 | static void rtl8169_vlan_rx_register(struct net_device *dev, | |
987 | struct vlan_group *grp) | |
988 | { | |
989 | struct rtl8169_private *tp = netdev_priv(dev); | |
990 | void __iomem *ioaddr = tp->mmio_addr; | |
991 | unsigned long flags; | |
992 | ||
993 | spin_lock_irqsave(&tp->lock, flags); | |
994 | tp->vlgrp = grp; | |
995 | if (tp->vlgrp) | |
996 | tp->cp_cmd |= RxVlan; | |
997 | else | |
998 | tp->cp_cmd &= ~RxVlan; | |
999 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
1000 | RTL_R16(CPlusCmd); | |
1001 | spin_unlock_irqrestore(&tp->lock, flags); | |
1002 | } | |
1003 | ||
1da177e4 LT |
1004 | static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
1005 | struct sk_buff *skb) | |
1006 | { | |
1007 | u32 opts2 = le32_to_cpu(desc->opts2); | |
865c652d | 1008 | struct vlan_group *vlgrp = tp->vlgrp; |
1da177e4 LT |
1009 | int ret; |
1010 | ||
865c652d FR |
1011 | if (vlgrp && (opts2 & RxVlanTag)) { |
1012 | vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff)); | |
1da177e4 LT |
1013 | ret = 0; |
1014 | } else | |
1015 | ret = -1; | |
1016 | desc->opts2 = 0; | |
1017 | return ret; | |
1018 | } | |
1019 | ||
1020 | #else /* !CONFIG_R8169_VLAN */ | |
1021 | ||
1022 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, | |
1023 | struct sk_buff *skb) | |
1024 | { | |
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, | |
1029 | struct sk_buff *skb) | |
1030 | { | |
1031 | return -1; | |
1032 | } | |
1033 | ||
1034 | #endif | |
1035 | ||
ccdffb9a | 1036 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1037 | { |
1038 | struct rtl8169_private *tp = netdev_priv(dev); | |
1039 | void __iomem *ioaddr = tp->mmio_addr; | |
1040 | u32 status; | |
1041 | ||
1042 | cmd->supported = | |
1043 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1044 | cmd->port = PORT_FIBRE; | |
1045 | cmd->transceiver = XCVR_INTERNAL; | |
1046 | ||
1047 | status = RTL_R32(TBICSR); | |
1048 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1049 | cmd->autoneg = !!(status & TBINwEnable); | |
1050 | ||
1051 | cmd->speed = SPEED_1000; | |
1052 | cmd->duplex = DUPLEX_FULL; /* Always set */ | |
ccdffb9a FR |
1053 | |
1054 | return 0; | |
1da177e4 LT |
1055 | } |
1056 | ||
ccdffb9a | 1057 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1058 | { |
1059 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1060 | |
1061 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1062 | } |
1063 | ||
1064 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1065 | { | |
1066 | struct rtl8169_private *tp = netdev_priv(dev); | |
1067 | unsigned long flags; | |
ccdffb9a | 1068 | int rc; |
1da177e4 LT |
1069 | |
1070 | spin_lock_irqsave(&tp->lock, flags); | |
1071 | ||
ccdffb9a | 1072 | rc = tp->get_settings(dev, cmd); |
1da177e4 LT |
1073 | |
1074 | spin_unlock_irqrestore(&tp->lock, flags); | |
ccdffb9a | 1075 | return rc; |
1da177e4 LT |
1076 | } |
1077 | ||
1078 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1079 | void *p) | |
1080 | { | |
5b0384f4 FR |
1081 | struct rtl8169_private *tp = netdev_priv(dev); |
1082 | unsigned long flags; | |
1da177e4 | 1083 | |
5b0384f4 FR |
1084 | if (regs->len > R8169_REGS_SIZE) |
1085 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 1086 | |
5b0384f4 FR |
1087 | spin_lock_irqsave(&tp->lock, flags); |
1088 | memcpy_fromio(p, tp->mmio_addr, regs->len); | |
1089 | spin_unlock_irqrestore(&tp->lock, flags); | |
1da177e4 LT |
1090 | } |
1091 | ||
b57b7e5a SH |
1092 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1093 | { | |
1094 | struct rtl8169_private *tp = netdev_priv(dev); | |
1095 | ||
1096 | return tp->msg_enable; | |
1097 | } | |
1098 | ||
1099 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1100 | { | |
1101 | struct rtl8169_private *tp = netdev_priv(dev); | |
1102 | ||
1103 | tp->msg_enable = value; | |
1104 | } | |
1105 | ||
d4a3a0fc SH |
1106 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1107 | "tx_packets", | |
1108 | "rx_packets", | |
1109 | "tx_errors", | |
1110 | "rx_errors", | |
1111 | "rx_missed", | |
1112 | "align_errors", | |
1113 | "tx_single_collisions", | |
1114 | "tx_multi_collisions", | |
1115 | "unicast", | |
1116 | "broadcast", | |
1117 | "multicast", | |
1118 | "tx_aborted", | |
1119 | "tx_underrun", | |
1120 | }; | |
1121 | ||
b9f2c044 | 1122 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1123 | { |
b9f2c044 JG |
1124 | switch (sset) { |
1125 | case ETH_SS_STATS: | |
1126 | return ARRAY_SIZE(rtl8169_gstrings); | |
1127 | default: | |
1128 | return -EOPNOTSUPP; | |
1129 | } | |
d4a3a0fc SH |
1130 | } |
1131 | ||
355423d0 | 1132 | static void rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
1133 | { |
1134 | struct rtl8169_private *tp = netdev_priv(dev); | |
1135 | void __iomem *ioaddr = tp->mmio_addr; | |
1136 | struct rtl8169_counters *counters; | |
1137 | dma_addr_t paddr; | |
1138 | u32 cmd; | |
355423d0 | 1139 | int wait = 1000; |
d4a3a0fc | 1140 | |
355423d0 IV |
1141 | /* |
1142 | * Some chips are unable to dump tally counters when the receiver | |
1143 | * is disabled. | |
1144 | */ | |
1145 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
1146 | return; | |
d4a3a0fc SH |
1147 | |
1148 | counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); | |
1149 | if (!counters) | |
1150 | return; | |
1151 | ||
1152 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
284901a9 | 1153 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
d4a3a0fc SH |
1154 | RTL_W32(CounterAddrLow, cmd); |
1155 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1156 | ||
355423d0 IV |
1157 | while (wait--) { |
1158 | if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { | |
1159 | /* copy updated counters */ | |
1160 | memcpy(&tp->counters, counters, sizeof(*counters)); | |
d4a3a0fc | 1161 | break; |
355423d0 IV |
1162 | } |
1163 | udelay(10); | |
d4a3a0fc SH |
1164 | } |
1165 | ||
1166 | RTL_W32(CounterAddrLow, 0); | |
1167 | RTL_W32(CounterAddrHigh, 0); | |
1168 | ||
d4a3a0fc SH |
1169 | pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); |
1170 | } | |
1171 | ||
355423d0 IV |
1172 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
1173 | struct ethtool_stats *stats, u64 *data) | |
1174 | { | |
1175 | struct rtl8169_private *tp = netdev_priv(dev); | |
1176 | ||
1177 | ASSERT_RTNL(); | |
1178 | ||
1179 | rtl8169_update_counters(dev); | |
1180 | ||
1181 | data[0] = le64_to_cpu(tp->counters.tx_packets); | |
1182 | data[1] = le64_to_cpu(tp->counters.rx_packets); | |
1183 | data[2] = le64_to_cpu(tp->counters.tx_errors); | |
1184 | data[3] = le32_to_cpu(tp->counters.rx_errors); | |
1185 | data[4] = le16_to_cpu(tp->counters.rx_missed); | |
1186 | data[5] = le16_to_cpu(tp->counters.align_errors); | |
1187 | data[6] = le32_to_cpu(tp->counters.tx_one_collision); | |
1188 | data[7] = le32_to_cpu(tp->counters.tx_multi_collision); | |
1189 | data[8] = le64_to_cpu(tp->counters.rx_unicast); | |
1190 | data[9] = le64_to_cpu(tp->counters.rx_broadcast); | |
1191 | data[10] = le32_to_cpu(tp->counters.rx_multicast); | |
1192 | data[11] = le16_to_cpu(tp->counters.tx_aborted); | |
1193 | data[12] = le16_to_cpu(tp->counters.tx_underun); | |
1194 | } | |
1195 | ||
d4a3a0fc SH |
1196 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
1197 | { | |
1198 | switch(stringset) { | |
1199 | case ETH_SS_STATS: | |
1200 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1201 | break; | |
1202 | } | |
1203 | } | |
1204 | ||
7282d491 | 1205 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1206 | .get_drvinfo = rtl8169_get_drvinfo, |
1207 | .get_regs_len = rtl8169_get_regs_len, | |
1208 | .get_link = ethtool_op_get_link, | |
1209 | .get_settings = rtl8169_get_settings, | |
1210 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1211 | .get_msglevel = rtl8169_get_msglevel, |
1212 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 LT |
1213 | .get_rx_csum = rtl8169_get_rx_csum, |
1214 | .set_rx_csum = rtl8169_set_rx_csum, | |
1da177e4 | 1215 | .set_tx_csum = ethtool_op_set_tx_csum, |
1da177e4 | 1216 | .set_sg = ethtool_op_set_sg, |
1da177e4 LT |
1217 | .set_tso = ethtool_op_set_tso, |
1218 | .get_regs = rtl8169_get_regs, | |
61a4dcc2 FR |
1219 | .get_wol = rtl8169_get_wol, |
1220 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1221 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1222 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1223 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
1da177e4 LT |
1224 | }; |
1225 | ||
07d3f51f FR |
1226 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
1227 | void __iomem *ioaddr) | |
1da177e4 | 1228 | { |
0e485150 FR |
1229 | /* |
1230 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1231 | * but they can be identified more specifically through the test below | |
1232 | * if needed: | |
1233 | * | |
1234 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1235 | * |
1236 | * Same thing for the 8101Eb and the 8101Ec: | |
1237 | * | |
1238 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1239 | */ |
1da177e4 LT |
1240 | const struct { |
1241 | u32 mask; | |
e3cf0cc0 | 1242 | u32 val; |
1da177e4 LT |
1243 | int mac_version; |
1244 | } mac_info[] = { | |
5b538df9 FR |
1245 | /* 8168D family. */ |
1246 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 }, | |
1247 | ||
ef808d50 | 1248 | /* 8168C family. */ |
7f3e3d3a | 1249 | { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 1250 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 1251 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 1252 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
1253 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1254 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 1255 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 1256 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 1257 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
1258 | |
1259 | /* 8168B family. */ | |
1260 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1261 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1262 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1263 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1264 | ||
1265 | /* 8101 family. */ | |
2857ffb7 FR |
1266 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
1267 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
1268 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
1269 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
1270 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
1271 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 1272 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 1273 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 1274 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
1275 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
1276 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
1277 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
1278 | /* FIXME: where did these entries come from ? -- FR */ | |
1279 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1280 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1281 | ||
1282 | /* 8110 family. */ | |
1283 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1284 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1285 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1286 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1287 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
1288 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
1289 | ||
f21b75e9 JD |
1290 | /* Catch-all */ |
1291 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
1da177e4 LT |
1292 | }, *p = mac_info; |
1293 | u32 reg; | |
1294 | ||
e3cf0cc0 FR |
1295 | reg = RTL_R32(TxConfig); |
1296 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
1297 | p++; |
1298 | tp->mac_version = p->mac_version; | |
1299 | } | |
1300 | ||
1301 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
1302 | { | |
bcf0bf90 | 1303 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
1304 | } |
1305 | ||
867763c1 FR |
1306 | struct phy_reg { |
1307 | u16 reg; | |
1308 | u16 val; | |
1309 | }; | |
1310 | ||
1311 | static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) | |
1312 | { | |
1313 | while (len-- > 0) { | |
1314 | mdio_write(ioaddr, regs->reg, regs->val); | |
1315 | regs++; | |
1316 | } | |
1317 | } | |
1318 | ||
5615d9f1 | 1319 | static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
1da177e4 | 1320 | { |
0b9b571d | 1321 | struct phy_reg phy_reg_init[] = { |
1322 | { 0x1f, 0x0001 }, | |
1323 | { 0x06, 0x006e }, | |
1324 | { 0x08, 0x0708 }, | |
1325 | { 0x15, 0x4000 }, | |
1326 | { 0x18, 0x65c7 }, | |
1da177e4 | 1327 | |
0b9b571d | 1328 | { 0x1f, 0x0001 }, |
1329 | { 0x03, 0x00a1 }, | |
1330 | { 0x02, 0x0008 }, | |
1331 | { 0x01, 0x0120 }, | |
1332 | { 0x00, 0x1000 }, | |
1333 | { 0x04, 0x0800 }, | |
1334 | { 0x04, 0x0000 }, | |
1da177e4 | 1335 | |
0b9b571d | 1336 | { 0x03, 0xff41 }, |
1337 | { 0x02, 0xdf60 }, | |
1338 | { 0x01, 0x0140 }, | |
1339 | { 0x00, 0x0077 }, | |
1340 | { 0x04, 0x7800 }, | |
1341 | { 0x04, 0x7000 }, | |
1342 | ||
1343 | { 0x03, 0x802f }, | |
1344 | { 0x02, 0x4f02 }, | |
1345 | { 0x01, 0x0409 }, | |
1346 | { 0x00, 0xf0f9 }, | |
1347 | { 0x04, 0x9800 }, | |
1348 | { 0x04, 0x9000 }, | |
1349 | ||
1350 | { 0x03, 0xdf01 }, | |
1351 | { 0x02, 0xdf20 }, | |
1352 | { 0x01, 0xff95 }, | |
1353 | { 0x00, 0xba00 }, | |
1354 | { 0x04, 0xa800 }, | |
1355 | { 0x04, 0xa000 }, | |
1356 | ||
1357 | { 0x03, 0xff41 }, | |
1358 | { 0x02, 0xdf20 }, | |
1359 | { 0x01, 0x0140 }, | |
1360 | { 0x00, 0x00bb }, | |
1361 | { 0x04, 0xb800 }, | |
1362 | { 0x04, 0xb000 }, | |
1363 | ||
1364 | { 0x03, 0xdf41 }, | |
1365 | { 0x02, 0xdc60 }, | |
1366 | { 0x01, 0x6340 }, | |
1367 | { 0x00, 0x007d }, | |
1368 | { 0x04, 0xd800 }, | |
1369 | { 0x04, 0xd000 }, | |
1370 | ||
1371 | { 0x03, 0xdf01 }, | |
1372 | { 0x02, 0xdf20 }, | |
1373 | { 0x01, 0x100a }, | |
1374 | { 0x00, 0xa0ff }, | |
1375 | { 0x04, 0xf800 }, | |
1376 | { 0x04, 0xf000 }, | |
1377 | ||
1378 | { 0x1f, 0x0000 }, | |
1379 | { 0x0b, 0x0000 }, | |
1380 | { 0x00, 0x9200 } | |
1381 | }; | |
1da177e4 | 1382 | |
0b9b571d | 1383 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
1384 | } |
1385 | ||
5615d9f1 FR |
1386 | static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
1387 | { | |
a441d7b6 FR |
1388 | struct phy_reg phy_reg_init[] = { |
1389 | { 0x1f, 0x0002 }, | |
1390 | { 0x01, 0x90d0 }, | |
1391 | { 0x1f, 0x0000 } | |
1392 | }; | |
1393 | ||
1394 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
5615d9f1 FR |
1395 | } |
1396 | ||
2e955856 | 1397 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp, |
1398 | void __iomem *ioaddr) | |
1399 | { | |
1400 | struct pci_dev *pdev = tp->pci_dev; | |
1401 | u16 vendor_id, device_id; | |
1402 | ||
1403 | pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id); | |
1404 | pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id); | |
1405 | ||
1406 | if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000)) | |
1407 | return; | |
1408 | ||
1409 | mdio_write(ioaddr, 0x1f, 0x0001); | |
1410 | mdio_write(ioaddr, 0x10, 0xf01b); | |
1411 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1412 | } | |
1413 | ||
1414 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, | |
1415 | void __iomem *ioaddr) | |
1416 | { | |
1417 | struct phy_reg phy_reg_init[] = { | |
1418 | { 0x1f, 0x0001 }, | |
1419 | { 0x04, 0x0000 }, | |
1420 | { 0x03, 0x00a1 }, | |
1421 | { 0x02, 0x0008 }, | |
1422 | { 0x01, 0x0120 }, | |
1423 | { 0x00, 0x1000 }, | |
1424 | { 0x04, 0x0800 }, | |
1425 | { 0x04, 0x9000 }, | |
1426 | { 0x03, 0x802f }, | |
1427 | { 0x02, 0x4f02 }, | |
1428 | { 0x01, 0x0409 }, | |
1429 | { 0x00, 0xf099 }, | |
1430 | { 0x04, 0x9800 }, | |
1431 | { 0x04, 0xa000 }, | |
1432 | { 0x03, 0xdf01 }, | |
1433 | { 0x02, 0xdf20 }, | |
1434 | { 0x01, 0xff95 }, | |
1435 | { 0x00, 0xba00 }, | |
1436 | { 0x04, 0xa800 }, | |
1437 | { 0x04, 0xf000 }, | |
1438 | { 0x03, 0xdf01 }, | |
1439 | { 0x02, 0xdf20 }, | |
1440 | { 0x01, 0x101a }, | |
1441 | { 0x00, 0xa0ff }, | |
1442 | { 0x04, 0xf800 }, | |
1443 | { 0x04, 0x0000 }, | |
1444 | { 0x1f, 0x0000 }, | |
1445 | ||
1446 | { 0x1f, 0x0001 }, | |
1447 | { 0x10, 0xf41b }, | |
1448 | { 0x14, 0xfb54 }, | |
1449 | { 0x18, 0xf5c7 }, | |
1450 | { 0x1f, 0x0000 }, | |
1451 | ||
1452 | { 0x1f, 0x0001 }, | |
1453 | { 0x17, 0x0cc0 }, | |
1454 | { 0x1f, 0x0000 } | |
1455 | }; | |
1456 | ||
1457 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1458 | ||
1459 | rtl8169scd_hw_phy_config_quirk(tp, ioaddr); | |
1460 | } | |
1461 | ||
8c7006aa | 1462 | static void rtl8169sce_hw_phy_config(void __iomem *ioaddr) |
1463 | { | |
1464 | struct phy_reg phy_reg_init[] = { | |
1465 | { 0x1f, 0x0001 }, | |
1466 | { 0x04, 0x0000 }, | |
1467 | { 0x03, 0x00a1 }, | |
1468 | { 0x02, 0x0008 }, | |
1469 | { 0x01, 0x0120 }, | |
1470 | { 0x00, 0x1000 }, | |
1471 | { 0x04, 0x0800 }, | |
1472 | { 0x04, 0x9000 }, | |
1473 | { 0x03, 0x802f }, | |
1474 | { 0x02, 0x4f02 }, | |
1475 | { 0x01, 0x0409 }, | |
1476 | { 0x00, 0xf099 }, | |
1477 | { 0x04, 0x9800 }, | |
1478 | { 0x04, 0xa000 }, | |
1479 | { 0x03, 0xdf01 }, | |
1480 | { 0x02, 0xdf20 }, | |
1481 | { 0x01, 0xff95 }, | |
1482 | { 0x00, 0xba00 }, | |
1483 | { 0x04, 0xa800 }, | |
1484 | { 0x04, 0xf000 }, | |
1485 | { 0x03, 0xdf01 }, | |
1486 | { 0x02, 0xdf20 }, | |
1487 | { 0x01, 0x101a }, | |
1488 | { 0x00, 0xa0ff }, | |
1489 | { 0x04, 0xf800 }, | |
1490 | { 0x04, 0x0000 }, | |
1491 | { 0x1f, 0x0000 }, | |
1492 | ||
1493 | { 0x1f, 0x0001 }, | |
1494 | { 0x0b, 0x8480 }, | |
1495 | { 0x1f, 0x0000 }, | |
1496 | ||
1497 | { 0x1f, 0x0001 }, | |
1498 | { 0x18, 0x67c7 }, | |
1499 | { 0x04, 0x2000 }, | |
1500 | { 0x03, 0x002f }, | |
1501 | { 0x02, 0x4360 }, | |
1502 | { 0x01, 0x0109 }, | |
1503 | { 0x00, 0x3022 }, | |
1504 | { 0x04, 0x2800 }, | |
1505 | { 0x1f, 0x0000 }, | |
1506 | ||
1507 | { 0x1f, 0x0001 }, | |
1508 | { 0x17, 0x0cc0 }, | |
1509 | { 0x1f, 0x0000 } | |
1510 | }; | |
1511 | ||
1512 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1513 | } | |
1514 | ||
236b8082 FR |
1515 | static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) |
1516 | { | |
1517 | struct phy_reg phy_reg_init[] = { | |
1518 | { 0x10, 0xf41b }, | |
1519 | { 0x1f, 0x0000 } | |
1520 | }; | |
1521 | ||
1522 | mdio_write(ioaddr, 0x1f, 0x0001); | |
1523 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1524 | ||
1525 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1526 | } | |
1527 | ||
1528 | static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) | |
1529 | { | |
1530 | struct phy_reg phy_reg_init[] = { | |
1531 | { 0x1f, 0x0001 }, | |
1532 | { 0x10, 0xf41b }, | |
1533 | { 0x1f, 0x0000 } | |
1534 | }; | |
1535 | ||
1536 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1537 | } | |
1538 | ||
ef3386f0 | 1539 | static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) |
867763c1 FR |
1540 | { |
1541 | struct phy_reg phy_reg_init[] = { | |
1542 | { 0x1f, 0x0000 }, | |
1543 | { 0x1d, 0x0f00 }, | |
1544 | { 0x1f, 0x0002 }, | |
1545 | { 0x0c, 0x1ec8 }, | |
1546 | { 0x1f, 0x0000 } | |
1547 | }; | |
1548 | ||
1549 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1550 | } | |
1551 | ||
ef3386f0 FR |
1552 | static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) |
1553 | { | |
1554 | struct phy_reg phy_reg_init[] = { | |
1555 | { 0x1f, 0x0001 }, | |
1556 | { 0x1d, 0x3d98 }, | |
1557 | { 0x1f, 0x0000 } | |
1558 | }; | |
1559 | ||
1560 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1561 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1562 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1563 | ||
1564 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1565 | } | |
1566 | ||
219a1e9d | 1567 | static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) |
867763c1 FR |
1568 | { |
1569 | struct phy_reg phy_reg_init[] = { | |
a3f80671 FR |
1570 | { 0x1f, 0x0001 }, |
1571 | { 0x12, 0x2300 }, | |
867763c1 FR |
1572 | { 0x1f, 0x0002 }, |
1573 | { 0x00, 0x88d4 }, | |
1574 | { 0x01, 0x82b1 }, | |
1575 | { 0x03, 0x7002 }, | |
1576 | { 0x08, 0x9e30 }, | |
1577 | { 0x09, 0x01f0 }, | |
1578 | { 0x0a, 0x5500 }, | |
1579 | { 0x0c, 0x00c8 }, | |
1580 | { 0x1f, 0x0003 }, | |
1581 | { 0x12, 0xc096 }, | |
1582 | { 0x16, 0x000a }, | |
f50d4275 FR |
1583 | { 0x1f, 0x0000 }, |
1584 | { 0x1f, 0x0000 }, | |
1585 | { 0x09, 0x2000 }, | |
1586 | { 0x09, 0x0000 } | |
867763c1 FR |
1587 | }; |
1588 | ||
1589 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
f50d4275 FR |
1590 | |
1591 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1592 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1593 | mdio_write(ioaddr, 0x1f, 0x0000); | |
867763c1 FR |
1594 | } |
1595 | ||
219a1e9d | 1596 | static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) |
7da97ec9 FR |
1597 | { |
1598 | struct phy_reg phy_reg_init[] = { | |
f50d4275 | 1599 | { 0x1f, 0x0001 }, |
7da97ec9 | 1600 | { 0x12, 0x2300 }, |
f50d4275 FR |
1601 | { 0x03, 0x802f }, |
1602 | { 0x02, 0x4f02 }, | |
1603 | { 0x01, 0x0409 }, | |
1604 | { 0x00, 0xf099 }, | |
1605 | { 0x04, 0x9800 }, | |
1606 | { 0x04, 0x9000 }, | |
1607 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
1608 | { 0x1f, 0x0002 }, |
1609 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
1610 | { 0x06, 0x0761 }, |
1611 | { 0x1f, 0x0003 }, | |
1612 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
1613 | { 0x1f, 0x0000 } |
1614 | }; | |
1615 | ||
1616 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
f50d4275 FR |
1617 | |
1618 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1619 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1620 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1621 | mdio_write(ioaddr, 0x1f, 0x0000); | |
7da97ec9 FR |
1622 | } |
1623 | ||
197ff761 FR |
1624 | static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) |
1625 | { | |
1626 | struct phy_reg phy_reg_init[] = { | |
1627 | { 0x1f, 0x0001 }, | |
1628 | { 0x12, 0x2300 }, | |
1629 | { 0x1d, 0x3d98 }, | |
1630 | { 0x1f, 0x0002 }, | |
1631 | { 0x0c, 0x7eb8 }, | |
1632 | { 0x06, 0x5461 }, | |
1633 | { 0x1f, 0x0003 }, | |
1634 | { 0x16, 0x0f0a }, | |
1635 | { 0x1f, 0x0000 } | |
1636 | }; | |
1637 | ||
1638 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1639 | ||
1640 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1641 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1642 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1643 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1644 | } | |
1645 | ||
6fb07058 FR |
1646 | static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) |
1647 | { | |
1648 | rtl8168c_3_hw_phy_config(ioaddr); | |
1649 | } | |
1650 | ||
5b538df9 FR |
1651 | static void rtl8168d_hw_phy_config(void __iomem *ioaddr) |
1652 | { | |
1653 | struct phy_reg phy_reg_init_0[] = { | |
1654 | { 0x1f, 0x0001 }, | |
1655 | { 0x09, 0x2770 }, | |
1656 | { 0x08, 0x04d0 }, | |
1657 | { 0x0b, 0xad15 }, | |
1658 | { 0x0c, 0x5bf0 }, | |
1659 | { 0x1c, 0xf101 }, | |
1660 | { 0x1f, 0x0003 }, | |
1661 | { 0x14, 0x94d7 }, | |
1662 | { 0x12, 0xf4d6 }, | |
1663 | { 0x09, 0xca0f }, | |
1664 | { 0x1f, 0x0002 }, | |
1665 | { 0x0b, 0x0b10 }, | |
1666 | { 0x0c, 0xd1f7 }, | |
1667 | { 0x1f, 0x0002 }, | |
1668 | { 0x06, 0x5461 }, | |
1669 | { 0x1f, 0x0002 }, | |
1670 | { 0x05, 0x6662 }, | |
1671 | { 0x1f, 0x0000 }, | |
1672 | { 0x14, 0x0060 }, | |
1673 | { 0x1f, 0x0000 }, | |
1674 | { 0x0d, 0xf8a0 }, | |
1675 | { 0x1f, 0x0005 }, | |
1676 | { 0x05, 0xffc2 } | |
1677 | }; | |
1678 | ||
1679 | rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); | |
1680 | ||
1681 | if (mdio_read(ioaddr, 0x06) == 0xc400) { | |
1682 | struct phy_reg phy_reg_init_1[] = { | |
1683 | { 0x1f, 0x0005 }, | |
1684 | { 0x01, 0x0300 }, | |
1685 | { 0x1f, 0x0000 }, | |
1686 | { 0x11, 0x401c }, | |
1687 | { 0x16, 0x4100 }, | |
1688 | { 0x1f, 0x0005 }, | |
1689 | { 0x07, 0x0010 }, | |
1690 | { 0x05, 0x83dc }, | |
1691 | { 0x06, 0x087d }, | |
1692 | { 0x05, 0x8300 }, | |
1693 | { 0x06, 0x0101 }, | |
1694 | { 0x06, 0x05f8 }, | |
1695 | { 0x06, 0xf9fa }, | |
1696 | { 0x06, 0xfbef }, | |
1697 | { 0x06, 0x79e2 }, | |
1698 | { 0x06, 0x835f }, | |
1699 | { 0x06, 0xe0f8 }, | |
1700 | { 0x06, 0x9ae1 }, | |
1701 | { 0x06, 0xf89b }, | |
1702 | { 0x06, 0xef31 }, | |
1703 | { 0x06, 0x3b65 }, | |
1704 | { 0x06, 0xaa07 }, | |
1705 | { 0x06, 0x81e4 }, | |
1706 | { 0x06, 0xf89a }, | |
1707 | { 0x06, 0xe5f8 }, | |
1708 | { 0x06, 0x9baf }, | |
1709 | { 0x06, 0x06ae }, | |
1710 | { 0x05, 0x83dc }, | |
1711 | { 0x06, 0x8300 }, | |
1712 | }; | |
1713 | ||
1714 | rtl_phy_write(ioaddr, phy_reg_init_1, | |
1715 | ARRAY_SIZE(phy_reg_init_1)); | |
1716 | } | |
1717 | ||
1718 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1719 | } | |
1720 | ||
2857ffb7 FR |
1721 | static void rtl8102e_hw_phy_config(void __iomem *ioaddr) |
1722 | { | |
1723 | struct phy_reg phy_reg_init[] = { | |
1724 | { 0x1f, 0x0003 }, | |
1725 | { 0x08, 0x441d }, | |
1726 | { 0x01, 0x9100 }, | |
1727 | { 0x1f, 0x0000 } | |
1728 | }; | |
1729 | ||
1730 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1731 | mdio_patch(ioaddr, 0x11, 1 << 12); | |
1732 | mdio_patch(ioaddr, 0x19, 1 << 13); | |
85910a8e | 1733 | mdio_patch(ioaddr, 0x10, 1 << 15); |
2857ffb7 FR |
1734 | |
1735 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1736 | } | |
1737 | ||
5615d9f1 FR |
1738 | static void rtl_hw_phy_config(struct net_device *dev) |
1739 | { | |
1740 | struct rtl8169_private *tp = netdev_priv(dev); | |
1741 | void __iomem *ioaddr = tp->mmio_addr; | |
1742 | ||
1743 | rtl8169_print_mac_version(tp); | |
1744 | ||
1745 | switch (tp->mac_version) { | |
1746 | case RTL_GIGA_MAC_VER_01: | |
1747 | break; | |
1748 | case RTL_GIGA_MAC_VER_02: | |
1749 | case RTL_GIGA_MAC_VER_03: | |
1750 | rtl8169s_hw_phy_config(ioaddr); | |
1751 | break; | |
1752 | case RTL_GIGA_MAC_VER_04: | |
1753 | rtl8169sb_hw_phy_config(ioaddr); | |
1754 | break; | |
2e955856 | 1755 | case RTL_GIGA_MAC_VER_05: |
1756 | rtl8169scd_hw_phy_config(tp, ioaddr); | |
1757 | break; | |
8c7006aa | 1758 | case RTL_GIGA_MAC_VER_06: |
1759 | rtl8169sce_hw_phy_config(ioaddr); | |
1760 | break; | |
2857ffb7 FR |
1761 | case RTL_GIGA_MAC_VER_07: |
1762 | case RTL_GIGA_MAC_VER_08: | |
1763 | case RTL_GIGA_MAC_VER_09: | |
1764 | rtl8102e_hw_phy_config(ioaddr); | |
1765 | break; | |
236b8082 FR |
1766 | case RTL_GIGA_MAC_VER_11: |
1767 | rtl8168bb_hw_phy_config(ioaddr); | |
1768 | break; | |
1769 | case RTL_GIGA_MAC_VER_12: | |
1770 | rtl8168bef_hw_phy_config(ioaddr); | |
1771 | break; | |
1772 | case RTL_GIGA_MAC_VER_17: | |
1773 | rtl8168bef_hw_phy_config(ioaddr); | |
1774 | break; | |
867763c1 | 1775 | case RTL_GIGA_MAC_VER_18: |
ef3386f0 | 1776 | rtl8168cp_1_hw_phy_config(ioaddr); |
867763c1 FR |
1777 | break; |
1778 | case RTL_GIGA_MAC_VER_19: | |
219a1e9d | 1779 | rtl8168c_1_hw_phy_config(ioaddr); |
867763c1 | 1780 | break; |
7da97ec9 | 1781 | case RTL_GIGA_MAC_VER_20: |
219a1e9d | 1782 | rtl8168c_2_hw_phy_config(ioaddr); |
7da97ec9 | 1783 | break; |
197ff761 FR |
1784 | case RTL_GIGA_MAC_VER_21: |
1785 | rtl8168c_3_hw_phy_config(ioaddr); | |
1786 | break; | |
6fb07058 FR |
1787 | case RTL_GIGA_MAC_VER_22: |
1788 | rtl8168c_4_hw_phy_config(ioaddr); | |
1789 | break; | |
ef3386f0 | 1790 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 1791 | case RTL_GIGA_MAC_VER_24: |
ef3386f0 FR |
1792 | rtl8168cp_2_hw_phy_config(ioaddr); |
1793 | break; | |
5b538df9 FR |
1794 | case RTL_GIGA_MAC_VER_25: |
1795 | rtl8168d_hw_phy_config(ioaddr); | |
1796 | break; | |
ef3386f0 | 1797 | |
5615d9f1 FR |
1798 | default: |
1799 | break; | |
1800 | } | |
1801 | } | |
1802 | ||
1da177e4 LT |
1803 | static void rtl8169_phy_timer(unsigned long __opaque) |
1804 | { | |
1805 | struct net_device *dev = (struct net_device *)__opaque; | |
1806 | struct rtl8169_private *tp = netdev_priv(dev); | |
1807 | struct timer_list *timer = &tp->timer; | |
1808 | void __iomem *ioaddr = tp->mmio_addr; | |
1809 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
1810 | ||
bcf0bf90 | 1811 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 1812 | |
64e4bfb4 | 1813 | if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
1814 | return; |
1815 | ||
1816 | spin_lock_irq(&tp->lock); | |
1817 | ||
1818 | if (tp->phy_reset_pending(ioaddr)) { | |
5b0384f4 | 1819 | /* |
1da177e4 LT |
1820 | * A busy loop could burn quite a few cycles on nowadays CPU. |
1821 | * Let's delay the execution of the timer for a few ticks. | |
1822 | */ | |
1823 | timeout = HZ/10; | |
1824 | goto out_mod_timer; | |
1825 | } | |
1826 | ||
1827 | if (tp->link_ok(ioaddr)) | |
1828 | goto out_unlock; | |
1829 | ||
b57b7e5a SH |
1830 | if (netif_msg_link(tp)) |
1831 | printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); | |
1da177e4 LT |
1832 | |
1833 | tp->phy_reset_enable(ioaddr); | |
1834 | ||
1835 | out_mod_timer: | |
1836 | mod_timer(timer, jiffies + timeout); | |
1837 | out_unlock: | |
1838 | spin_unlock_irq(&tp->lock); | |
1839 | } | |
1840 | ||
1841 | static inline void rtl8169_delete_timer(struct net_device *dev) | |
1842 | { | |
1843 | struct rtl8169_private *tp = netdev_priv(dev); | |
1844 | struct timer_list *timer = &tp->timer; | |
1845 | ||
e179bb7b | 1846 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
1847 | return; |
1848 | ||
1849 | del_timer_sync(timer); | |
1850 | } | |
1851 | ||
1852 | static inline void rtl8169_request_timer(struct net_device *dev) | |
1853 | { | |
1854 | struct rtl8169_private *tp = netdev_priv(dev); | |
1855 | struct timer_list *timer = &tp->timer; | |
1856 | ||
e179bb7b | 1857 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
1858 | return; |
1859 | ||
2efa53f3 | 1860 | mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
1da177e4 LT |
1861 | } |
1862 | ||
1863 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1864 | /* | |
1865 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1866 | * without having to re-enable interrupts. It's not called while | |
1867 | * the interrupt routine is executing. | |
1868 | */ | |
1869 | static void rtl8169_netpoll(struct net_device *dev) | |
1870 | { | |
1871 | struct rtl8169_private *tp = netdev_priv(dev); | |
1872 | struct pci_dev *pdev = tp->pci_dev; | |
1873 | ||
1874 | disable_irq(pdev->irq); | |
7d12e780 | 1875 | rtl8169_interrupt(pdev->irq, dev); |
1da177e4 LT |
1876 | enable_irq(pdev->irq); |
1877 | } | |
1878 | #endif | |
1879 | ||
1880 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, | |
1881 | void __iomem *ioaddr) | |
1882 | { | |
1883 | iounmap(ioaddr); | |
1884 | pci_release_regions(pdev); | |
1885 | pci_disable_device(pdev); | |
1886 | free_netdev(dev); | |
1887 | } | |
1888 | ||
bf793295 FR |
1889 | static void rtl8169_phy_reset(struct net_device *dev, |
1890 | struct rtl8169_private *tp) | |
1891 | { | |
1892 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 1893 | unsigned int i; |
bf793295 FR |
1894 | |
1895 | tp->phy_reset_enable(ioaddr); | |
1896 | for (i = 0; i < 100; i++) { | |
1897 | if (!tp->phy_reset_pending(ioaddr)) | |
1898 | return; | |
1899 | msleep(1); | |
1900 | } | |
1901 | if (netif_msg_link(tp)) | |
1902 | printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); | |
1903 | } | |
1904 | ||
4ff96fa6 FR |
1905 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
1906 | { | |
1907 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 1908 | |
5615d9f1 | 1909 | rtl_hw_phy_config(dev); |
4ff96fa6 | 1910 | |
77332894 MS |
1911 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
1912 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
1913 | RTL_W8(0x82, 0x01); | |
1914 | } | |
4ff96fa6 | 1915 | |
6dccd16b FR |
1916 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
1917 | ||
1918 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
1919 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 1920 | |
bcf0bf90 | 1921 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
1922 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
1923 | RTL_W8(0x82, 0x01); | |
1924 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
1925 | mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 | |
1926 | } | |
1927 | ||
bf793295 FR |
1928 | rtl8169_phy_reset(dev, tp); |
1929 | ||
901dda2b FR |
1930 | /* |
1931 | * rtl8169_set_speed_xmii takes good care of the Fast Ethernet | |
1932 | * only 8101. Don't panic. | |
1933 | */ | |
1934 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); | |
4ff96fa6 FR |
1935 | |
1936 | if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) | |
1937 | printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); | |
1938 | } | |
1939 | ||
773d2021 FR |
1940 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
1941 | { | |
1942 | void __iomem *ioaddr = tp->mmio_addr; | |
1943 | u32 high; | |
1944 | u32 low; | |
1945 | ||
1946 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
1947 | high = addr[4] | (addr[5] << 8); | |
1948 | ||
1949 | spin_lock_irq(&tp->lock); | |
1950 | ||
1951 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
1952 | RTL_W32(MAC0, low); | |
1953 | RTL_W32(MAC4, high); | |
1954 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
1955 | ||
1956 | spin_unlock_irq(&tp->lock); | |
1957 | } | |
1958 | ||
1959 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
1960 | { | |
1961 | struct rtl8169_private *tp = netdev_priv(dev); | |
1962 | struct sockaddr *addr = p; | |
1963 | ||
1964 | if (!is_valid_ether_addr(addr->sa_data)) | |
1965 | return -EADDRNOTAVAIL; | |
1966 | ||
1967 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
1968 | ||
1969 | rtl_rar_set(tp, dev->dev_addr); | |
1970 | ||
1971 | return 0; | |
1972 | } | |
1973 | ||
5f787a1a FR |
1974 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1975 | { | |
1976 | struct rtl8169_private *tp = netdev_priv(dev); | |
1977 | struct mii_ioctl_data *data = if_mii(ifr); | |
1978 | ||
8b4ab28d FR |
1979 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
1980 | } | |
5f787a1a | 1981 | |
8b4ab28d FR |
1982 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
1983 | { | |
5f787a1a FR |
1984 | switch (cmd) { |
1985 | case SIOCGMIIPHY: | |
1986 | data->phy_id = 32; /* Internal PHY */ | |
1987 | return 0; | |
1988 | ||
1989 | case SIOCGMIIREG: | |
1990 | data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); | |
1991 | return 0; | |
1992 | ||
1993 | case SIOCSMIIREG: | |
5f787a1a FR |
1994 | mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); |
1995 | return 0; | |
1996 | } | |
1997 | return -EOPNOTSUPP; | |
1998 | } | |
1999 | ||
8b4ab28d FR |
2000 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
2001 | { | |
2002 | return -EOPNOTSUPP; | |
2003 | } | |
2004 | ||
0e485150 FR |
2005 | static const struct rtl_cfg_info { |
2006 | void (*hw_start)(struct net_device *); | |
2007 | unsigned int region; | |
2008 | unsigned int align; | |
2009 | u16 intr_event; | |
2010 | u16 napi_event; | |
ccdffb9a | 2011 | unsigned features; |
f21b75e9 | 2012 | u8 default_ver; |
0e485150 FR |
2013 | } rtl_cfg_infos [] = { |
2014 | [RTL_CFG_0] = { | |
2015 | .hw_start = rtl_hw_start_8169, | |
2016 | .region = 1, | |
e9f63f30 | 2017 | .align = 0, |
0e485150 FR |
2018 | .intr_event = SYSErr | LinkChg | RxOverflow | |
2019 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 2020 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2021 | .features = RTL_FEATURE_GMII, |
2022 | .default_ver = RTL_GIGA_MAC_VER_01, | |
0e485150 FR |
2023 | }, |
2024 | [RTL_CFG_1] = { | |
2025 | .hw_start = rtl_hw_start_8168, | |
2026 | .region = 2, | |
2027 | .align = 8, | |
2028 | .intr_event = SYSErr | LinkChg | RxOverflow | | |
2029 | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 2030 | .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2031 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
2032 | .default_ver = RTL_GIGA_MAC_VER_11, | |
0e485150 FR |
2033 | }, |
2034 | [RTL_CFG_2] = { | |
2035 | .hw_start = rtl_hw_start_8101, | |
2036 | .region = 2, | |
2037 | .align = 8, | |
2038 | .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | | |
2039 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 2040 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2041 | .features = RTL_FEATURE_MSI, |
2042 | .default_ver = RTL_GIGA_MAC_VER_13, | |
0e485150 FR |
2043 | } |
2044 | }; | |
2045 | ||
fbac58fc FR |
2046 | /* Cfg9346_Unlock assumed. */ |
2047 | static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, | |
2048 | const struct rtl_cfg_info *cfg) | |
2049 | { | |
2050 | unsigned msi = 0; | |
2051 | u8 cfg2; | |
2052 | ||
2053 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
ccdffb9a | 2054 | if (cfg->features & RTL_FEATURE_MSI) { |
fbac58fc FR |
2055 | if (pci_enable_msi(pdev)) { |
2056 | dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); | |
2057 | } else { | |
2058 | cfg2 |= MSIEnable; | |
2059 | msi = RTL_FEATURE_MSI; | |
2060 | } | |
2061 | } | |
2062 | RTL_W8(Config2, cfg2); | |
2063 | return msi; | |
2064 | } | |
2065 | ||
2066 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) | |
2067 | { | |
2068 | if (tp->features & RTL_FEATURE_MSI) { | |
2069 | pci_disable_msi(pdev); | |
2070 | tp->features &= ~RTL_FEATURE_MSI; | |
2071 | } | |
2072 | } | |
2073 | ||
8b4ab28d FR |
2074 | static const struct net_device_ops rtl8169_netdev_ops = { |
2075 | .ndo_open = rtl8169_open, | |
2076 | .ndo_stop = rtl8169_close, | |
2077 | .ndo_get_stats = rtl8169_get_stats, | |
00829823 | 2078 | .ndo_start_xmit = rtl8169_start_xmit, |
8b4ab28d FR |
2079 | .ndo_tx_timeout = rtl8169_tx_timeout, |
2080 | .ndo_validate_addr = eth_validate_addr, | |
2081 | .ndo_change_mtu = rtl8169_change_mtu, | |
2082 | .ndo_set_mac_address = rtl_set_mac_address, | |
2083 | .ndo_do_ioctl = rtl8169_ioctl, | |
2084 | .ndo_set_multicast_list = rtl_set_rx_mode, | |
2085 | #ifdef CONFIG_R8169_VLAN | |
2086 | .ndo_vlan_rx_register = rtl8169_vlan_rx_register, | |
2087 | #endif | |
2088 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2089 | .ndo_poll_controller = rtl8169_netpoll, | |
2090 | #endif | |
2091 | ||
2092 | }; | |
2093 | ||
1da177e4 | 2094 | static int __devinit |
4ff96fa6 | 2095 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 2096 | { |
0e485150 FR |
2097 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
2098 | const unsigned int region = cfg->region; | |
1da177e4 | 2099 | struct rtl8169_private *tp; |
ccdffb9a | 2100 | struct mii_if_info *mii; |
4ff96fa6 FR |
2101 | struct net_device *dev; |
2102 | void __iomem *ioaddr; | |
07d3f51f FR |
2103 | unsigned int i; |
2104 | int rc; | |
1da177e4 | 2105 | |
4ff96fa6 FR |
2106 | if (netif_msg_drv(&debug)) { |
2107 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
2108 | MODULENAME, RTL8169_VERSION); | |
2109 | } | |
1da177e4 | 2110 | |
1da177e4 | 2111 | dev = alloc_etherdev(sizeof (*tp)); |
4ff96fa6 | 2112 | if (!dev) { |
b57b7e5a | 2113 | if (netif_msg_drv(&debug)) |
9b91cf9d | 2114 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
4ff96fa6 FR |
2115 | rc = -ENOMEM; |
2116 | goto out; | |
1da177e4 LT |
2117 | } |
2118 | ||
1da177e4 | 2119 | SET_NETDEV_DEV(dev, &pdev->dev); |
8b4ab28d | 2120 | dev->netdev_ops = &rtl8169_netdev_ops; |
1da177e4 | 2121 | tp = netdev_priv(dev); |
c4028958 | 2122 | tp->dev = dev; |
21e197f2 | 2123 | tp->pci_dev = pdev; |
b57b7e5a | 2124 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
1da177e4 | 2125 | |
ccdffb9a FR |
2126 | mii = &tp->mii; |
2127 | mii->dev = dev; | |
2128 | mii->mdio_read = rtl_mdio_read; | |
2129 | mii->mdio_write = rtl_mdio_write; | |
2130 | mii->phy_id_mask = 0x1f; | |
2131 | mii->reg_num_mask = 0x1f; | |
2132 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
2133 | ||
1da177e4 LT |
2134 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
2135 | rc = pci_enable_device(pdev); | |
b57b7e5a | 2136 | if (rc < 0) { |
2e8a538d | 2137 | if (netif_msg_probe(tp)) |
9b91cf9d | 2138 | dev_err(&pdev->dev, "enable failure\n"); |
4ff96fa6 | 2139 | goto err_out_free_dev_1; |
1da177e4 LT |
2140 | } |
2141 | ||
2142 | rc = pci_set_mwi(pdev); | |
2143 | if (rc < 0) | |
4ff96fa6 | 2144 | goto err_out_disable_2; |
1da177e4 | 2145 | |
1da177e4 | 2146 | /* make sure PCI base addr 1 is MMIO */ |
bcf0bf90 | 2147 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
4ff96fa6 | 2148 | if (netif_msg_probe(tp)) { |
9b91cf9d | 2149 | dev_err(&pdev->dev, |
bcf0bf90 FR |
2150 | "region #%d not an MMIO resource, aborting\n", |
2151 | region); | |
4ff96fa6 | 2152 | } |
1da177e4 | 2153 | rc = -ENODEV; |
4ff96fa6 | 2154 | goto err_out_mwi_3; |
1da177e4 | 2155 | } |
4ff96fa6 | 2156 | |
1da177e4 | 2157 | /* check for weird/broken PCI region reporting */ |
bcf0bf90 | 2158 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
4ff96fa6 | 2159 | if (netif_msg_probe(tp)) { |
9b91cf9d | 2160 | dev_err(&pdev->dev, |
4ff96fa6 FR |
2161 | "Invalid PCI region size(s), aborting\n"); |
2162 | } | |
1da177e4 | 2163 | rc = -ENODEV; |
4ff96fa6 | 2164 | goto err_out_mwi_3; |
1da177e4 LT |
2165 | } |
2166 | ||
2167 | rc = pci_request_regions(pdev, MODULENAME); | |
b57b7e5a | 2168 | if (rc < 0) { |
2e8a538d | 2169 | if (netif_msg_probe(tp)) |
9b91cf9d | 2170 | dev_err(&pdev->dev, "could not request regions.\n"); |
4ff96fa6 | 2171 | goto err_out_mwi_3; |
1da177e4 LT |
2172 | } |
2173 | ||
2174 | tp->cp_cmd = PCIMulRW | RxChkSum; | |
2175 | ||
2176 | if ((sizeof(dma_addr_t) > 4) && | |
6a35528a | 2177 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
1da177e4 LT |
2178 | tp->cp_cmd |= PCIDAC; |
2179 | dev->features |= NETIF_F_HIGHDMA; | |
2180 | } else { | |
284901a9 | 2181 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 2182 | if (rc < 0) { |
4ff96fa6 | 2183 | if (netif_msg_probe(tp)) { |
9b91cf9d | 2184 | dev_err(&pdev->dev, |
4ff96fa6 FR |
2185 | "DMA configuration failed.\n"); |
2186 | } | |
2187 | goto err_out_free_res_4; | |
1da177e4 LT |
2188 | } |
2189 | } | |
2190 | ||
1da177e4 | 2191 | /* ioremap MMIO region */ |
bcf0bf90 | 2192 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
4ff96fa6 | 2193 | if (!ioaddr) { |
b57b7e5a | 2194 | if (netif_msg_probe(tp)) |
9b91cf9d | 2195 | dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
1da177e4 | 2196 | rc = -EIO; |
4ff96fa6 | 2197 | goto err_out_free_res_4; |
1da177e4 LT |
2198 | } |
2199 | ||
9c14ceaf FR |
2200 | tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
2201 | if (!tp->pcie_cap && netif_msg_probe(tp)) | |
2202 | dev_info(&pdev->dev, "no PCI Express capability\n"); | |
2203 | ||
d78ad8cb | 2204 | RTL_W16(IntrMask, 0x0000); |
1da177e4 LT |
2205 | |
2206 | /* Soft reset the chip. */ | |
2207 | RTL_W8(ChipCmd, CmdReset); | |
2208 | ||
2209 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 2210 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
2211 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
2212 | break; | |
b518fa8e | 2213 | msleep_interruptible(1); |
1da177e4 LT |
2214 | } |
2215 | ||
d78ad8cb KW |
2216 | RTL_W16(IntrStatus, 0xffff); |
2217 | ||
ca52efd5 | 2218 | pci_set_master(pdev); |
2219 | ||
1da177e4 LT |
2220 | /* Identify chip attached to board */ |
2221 | rtl8169_get_mac_version(tp, ioaddr); | |
1da177e4 | 2222 | |
f21b75e9 JD |
2223 | /* Use appropriate default if unknown */ |
2224 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
2225 | if (netif_msg_probe(tp)) { | |
2226 | dev_notice(&pdev->dev, | |
2227 | "unknown MAC, using family default\n"); | |
2228 | } | |
2229 | tp->mac_version = cfg->default_ver; | |
2230 | } | |
2231 | ||
1da177e4 | 2232 | rtl8169_print_mac_version(tp); |
1da177e4 | 2233 | |
cee60c37 | 2234 | for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
1da177e4 LT |
2235 | if (tp->mac_version == rtl_chip_info[i].mac_version) |
2236 | break; | |
2237 | } | |
cee60c37 | 2238 | if (i == ARRAY_SIZE(rtl_chip_info)) { |
f21b75e9 JD |
2239 | dev_err(&pdev->dev, |
2240 | "driver bug, MAC version not found in rtl_chip_info\n"); | |
2241 | goto err_out_msi_5; | |
1da177e4 LT |
2242 | } |
2243 | tp->chipset = i; | |
2244 | ||
5d06a99f FR |
2245 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
2246 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
2247 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
20037fa4 BP |
2248 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
2249 | tp->features |= RTL_FEATURE_WOL; | |
2250 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) | |
2251 | tp->features |= RTL_FEATURE_WOL; | |
fbac58fc | 2252 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
5d06a99f FR |
2253 | RTL_W8(Cfg9346, Cfg9346_Lock); |
2254 | ||
66ec5d4f FR |
2255 | if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
2256 | (RTL_R8(PHYstatus) & TBI_Enable)) { | |
1da177e4 LT |
2257 | tp->set_speed = rtl8169_set_speed_tbi; |
2258 | tp->get_settings = rtl8169_gset_tbi; | |
2259 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
2260 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
2261 | tp->link_ok = rtl8169_tbi_link_ok; | |
8b4ab28d | 2262 | tp->do_ioctl = rtl_tbi_ioctl; |
1da177e4 | 2263 | |
64e4bfb4 | 2264 | tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
1da177e4 LT |
2265 | } else { |
2266 | tp->set_speed = rtl8169_set_speed_xmii; | |
2267 | tp->get_settings = rtl8169_gset_xmii; | |
2268 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
2269 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
2270 | tp->link_ok = rtl8169_xmii_link_ok; | |
8b4ab28d | 2271 | tp->do_ioctl = rtl_xmii_ioctl; |
1da177e4 LT |
2272 | } |
2273 | ||
df58ef51 FR |
2274 | spin_lock_init(&tp->lock); |
2275 | ||
738e1e69 PV |
2276 | tp->mmio_addr = ioaddr; |
2277 | ||
7bf6bf48 | 2278 | /* Get MAC address */ |
1da177e4 LT |
2279 | for (i = 0; i < MAC_ADDR_LEN; i++) |
2280 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6d6525b7 | 2281 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 2282 | |
1da177e4 | 2283 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
1da177e4 LT |
2284 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
2285 | dev->irq = pdev->irq; | |
2286 | dev->base_addr = (unsigned long) ioaddr; | |
1da177e4 | 2287 | |
bea3348e | 2288 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
1da177e4 LT |
2289 | |
2290 | #ifdef CONFIG_R8169_VLAN | |
2291 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
1da177e4 LT |
2292 | #endif |
2293 | ||
2294 | tp->intr_mask = 0xffff; | |
0e485150 FR |
2295 | tp->align = cfg->align; |
2296 | tp->hw_start = cfg->hw_start; | |
2297 | tp->intr_event = cfg->intr_event; | |
2298 | tp->napi_event = cfg->napi_event; | |
1da177e4 | 2299 | |
2efa53f3 FR |
2300 | init_timer(&tp->timer); |
2301 | tp->timer.data = (unsigned long) dev; | |
2302 | tp->timer.function = rtl8169_phy_timer; | |
2303 | ||
1da177e4 | 2304 | rc = register_netdev(dev); |
4ff96fa6 | 2305 | if (rc < 0) |
fbac58fc | 2306 | goto err_out_msi_5; |
1da177e4 LT |
2307 | |
2308 | pci_set_drvdata(pdev, dev); | |
2309 | ||
b57b7e5a | 2310 | if (netif_msg_probe(tp)) { |
21d57363 | 2311 | u32 xid = RTL_R32(TxConfig) & 0x9cf0f8ff; |
96b9709c | 2312 | |
b57b7e5a SH |
2313 | printk(KERN_INFO "%s: %s at 0x%lx, " |
2314 | "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " | |
96b9709c | 2315 | "XID %08x IRQ %d\n", |
b57b7e5a | 2316 | dev->name, |
bcf0bf90 | 2317 | rtl_chip_info[tp->chipset].name, |
b57b7e5a SH |
2318 | dev->base_addr, |
2319 | dev->dev_addr[0], dev->dev_addr[1], | |
2320 | dev->dev_addr[2], dev->dev_addr[3], | |
96b9709c | 2321 | dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
b57b7e5a | 2322 | } |
1da177e4 | 2323 | |
4ff96fa6 | 2324 | rtl8169_init_phy(dev, tp); |
8b76ab39 | 2325 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
1da177e4 | 2326 | |
4ff96fa6 FR |
2327 | out: |
2328 | return rc; | |
1da177e4 | 2329 | |
fbac58fc FR |
2330 | err_out_msi_5: |
2331 | rtl_disable_msi(pdev, tp); | |
4ff96fa6 FR |
2332 | iounmap(ioaddr); |
2333 | err_out_free_res_4: | |
2334 | pci_release_regions(pdev); | |
2335 | err_out_mwi_3: | |
2336 | pci_clear_mwi(pdev); | |
2337 | err_out_disable_2: | |
2338 | pci_disable_device(pdev); | |
2339 | err_out_free_dev_1: | |
2340 | free_netdev(dev); | |
2341 | goto out; | |
1da177e4 LT |
2342 | } |
2343 | ||
07d3f51f | 2344 | static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
2345 | { |
2346 | struct net_device *dev = pci_get_drvdata(pdev); | |
2347 | struct rtl8169_private *tp = netdev_priv(dev); | |
2348 | ||
eb2a021c FR |
2349 | flush_scheduled_work(); |
2350 | ||
1da177e4 | 2351 | unregister_netdev(dev); |
fbac58fc | 2352 | rtl_disable_msi(pdev, tp); |
1da177e4 LT |
2353 | rtl8169_release_board(pdev, dev, tp->mmio_addr); |
2354 | pci_set_drvdata(pdev, NULL); | |
2355 | } | |
2356 | ||
1da177e4 LT |
2357 | static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
2358 | struct net_device *dev) | |
2359 | { | |
2360 | unsigned int mtu = dev->mtu; | |
2361 | ||
2362 | tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; | |
2363 | } | |
2364 | ||
2365 | static int rtl8169_open(struct net_device *dev) | |
2366 | { | |
2367 | struct rtl8169_private *tp = netdev_priv(dev); | |
2368 | struct pci_dev *pdev = tp->pci_dev; | |
99f252b0 | 2369 | int retval = -ENOMEM; |
1da177e4 | 2370 | |
1da177e4 | 2371 | |
99f252b0 | 2372 | rtl8169_set_rxbufsize(tp, dev); |
1da177e4 LT |
2373 | |
2374 | /* | |
2375 | * Rx and Tx desscriptors needs 256 bytes alignment. | |
2376 | * pci_alloc_consistent provides more. | |
2377 | */ | |
2378 | tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, | |
2379 | &tp->TxPhyAddr); | |
2380 | if (!tp->TxDescArray) | |
99f252b0 | 2381 | goto out; |
1da177e4 LT |
2382 | |
2383 | tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, | |
2384 | &tp->RxPhyAddr); | |
2385 | if (!tp->RxDescArray) | |
99f252b0 | 2386 | goto err_free_tx_0; |
1da177e4 LT |
2387 | |
2388 | retval = rtl8169_init_ring(dev); | |
2389 | if (retval < 0) | |
99f252b0 | 2390 | goto err_free_rx_1; |
1da177e4 | 2391 | |
c4028958 | 2392 | INIT_DELAYED_WORK(&tp->task, NULL); |
1da177e4 | 2393 | |
99f252b0 FR |
2394 | smp_mb(); |
2395 | ||
fbac58fc FR |
2396 | retval = request_irq(dev->irq, rtl8169_interrupt, |
2397 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, | |
99f252b0 FR |
2398 | dev->name, dev); |
2399 | if (retval < 0) | |
2400 | goto err_release_ring_2; | |
2401 | ||
bea3348e | 2402 | napi_enable(&tp->napi); |
bea3348e | 2403 | |
07ce4064 | 2404 | rtl_hw_start(dev); |
1da177e4 LT |
2405 | |
2406 | rtl8169_request_timer(dev); | |
2407 | ||
2408 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
2409 | out: | |
2410 | return retval; | |
2411 | ||
99f252b0 FR |
2412 | err_release_ring_2: |
2413 | rtl8169_rx_clear(tp); | |
2414 | err_free_rx_1: | |
1da177e4 LT |
2415 | pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
2416 | tp->RxPhyAddr); | |
99f252b0 | 2417 | err_free_tx_0: |
1da177e4 LT |
2418 | pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
2419 | tp->TxPhyAddr); | |
1da177e4 LT |
2420 | goto out; |
2421 | } | |
2422 | ||
2423 | static void rtl8169_hw_reset(void __iomem *ioaddr) | |
2424 | { | |
2425 | /* Disable interrupts */ | |
2426 | rtl8169_irq_mask_and_ack(ioaddr); | |
2427 | ||
2428 | /* Reset the chipset */ | |
2429 | RTL_W8(ChipCmd, CmdReset); | |
2430 | ||
2431 | /* PCI commit */ | |
2432 | RTL_R8(ChipCmd); | |
2433 | } | |
2434 | ||
7f796d83 | 2435 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
2436 | { |
2437 | void __iomem *ioaddr = tp->mmio_addr; | |
2438 | u32 cfg = rtl8169_rx_config; | |
2439 | ||
2440 | cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
2441 | RTL_W32(RxConfig, cfg); | |
2442 | ||
2443 | /* Set DMA burst size and Interframe Gap Time */ | |
2444 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
2445 | (InterFrameGap << TxInterFrameGapShift)); | |
2446 | } | |
2447 | ||
07ce4064 | 2448 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
2449 | { |
2450 | struct rtl8169_private *tp = netdev_priv(dev); | |
2451 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 2452 | unsigned int i; |
1da177e4 LT |
2453 | |
2454 | /* Soft reset the chip. */ | |
2455 | RTL_W8(ChipCmd, CmdReset); | |
2456 | ||
2457 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 2458 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
2459 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
2460 | break; | |
b518fa8e | 2461 | msleep_interruptible(1); |
1da177e4 LT |
2462 | } |
2463 | ||
07ce4064 FR |
2464 | tp->hw_start(dev); |
2465 | ||
07ce4064 FR |
2466 | netif_start_queue(dev); |
2467 | } | |
2468 | ||
2469 | ||
7f796d83 FR |
2470 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
2471 | void __iomem *ioaddr) | |
2472 | { | |
2473 | /* | |
2474 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
2475 | * register to be written before TxDescAddrLow to work. | |
2476 | * Switching from MMIO to I/O access fixes the issue as well. | |
2477 | */ | |
2478 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 2479 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 2480 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 2481 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
2482 | } |
2483 | ||
2484 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
2485 | { | |
2486 | u16 cmd; | |
2487 | ||
2488 | cmd = RTL_R16(CPlusCmd); | |
2489 | RTL_W16(CPlusCmd, cmd); | |
2490 | return cmd; | |
2491 | } | |
2492 | ||
fdd7b4c3 | 2493 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
2494 | { |
2495 | /* Low hurts. Let's disable the filtering. */ | |
fdd7b4c3 | 2496 | RTL_W16(RxMaxSize, rx_buf_sz); |
7f796d83 FR |
2497 | } |
2498 | ||
6dccd16b FR |
2499 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
2500 | { | |
2501 | struct { | |
2502 | u32 mac_version; | |
2503 | u32 clk; | |
2504 | u32 val; | |
2505 | } cfg2_info [] = { | |
2506 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
2507 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
2508 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
2509 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
2510 | }, *p = cfg2_info; | |
2511 | unsigned int i; | |
2512 | u32 clk; | |
2513 | ||
2514 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 2515 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
2516 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
2517 | RTL_W32(0x7c, p->val); | |
2518 | break; | |
2519 | } | |
2520 | } | |
2521 | } | |
2522 | ||
07ce4064 FR |
2523 | static void rtl_hw_start_8169(struct net_device *dev) |
2524 | { | |
2525 | struct rtl8169_private *tp = netdev_priv(dev); | |
2526 | void __iomem *ioaddr = tp->mmio_addr; | |
2527 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 2528 | |
9cb427b6 FR |
2529 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
2530 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
2531 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
2532 | } | |
2533 | ||
1da177e4 | 2534 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
9cb427b6 FR |
2535 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
2536 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
2537 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
2538 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
2539 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2540 | ||
1da177e4 LT |
2541 | RTL_W8(EarlyTxThres, EarlyTxThld); |
2542 | ||
fdd7b4c3 | 2543 | rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
1da177e4 | 2544 | |
c946b304 FR |
2545 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
2546 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
2547 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
2548 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
2549 | rtl_set_rx_tx_config_registers(tp); | |
1da177e4 | 2550 | |
7f796d83 | 2551 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 2552 | |
bcf0bf90 FR |
2553 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
2554 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
06fa7358 | 2555 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 2556 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 2557 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
2558 | } |
2559 | ||
bcf0bf90 FR |
2560 | RTL_W16(CPlusCmd, tp->cp_cmd); |
2561 | ||
6dccd16b FR |
2562 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
2563 | ||
1da177e4 LT |
2564 | /* |
2565 | * Undocumented corner. Supposedly: | |
2566 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
2567 | */ | |
2568 | RTL_W16(IntrMitigate, 0x0000); | |
2569 | ||
7f796d83 | 2570 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 2571 | |
c946b304 FR |
2572 | if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
2573 | (tp->mac_version != RTL_GIGA_MAC_VER_02) && | |
2574 | (tp->mac_version != RTL_GIGA_MAC_VER_03) && | |
2575 | (tp->mac_version != RTL_GIGA_MAC_VER_04)) { | |
2576 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2577 | rtl_set_rx_tx_config_registers(tp); | |
2578 | } | |
2579 | ||
1da177e4 | 2580 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
2581 | |
2582 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
2583 | RTL_R8(IntrMask); | |
1da177e4 LT |
2584 | |
2585 | RTL_W32(RxMissed, 0); | |
2586 | ||
07ce4064 | 2587 | rtl_set_rx_mode(dev); |
1da177e4 LT |
2588 | |
2589 | /* no early-rx interrupts */ | |
2590 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
6dccd16b FR |
2591 | |
2592 | /* Enable all known interrupts by setting the interrupt mask. */ | |
0e485150 | 2593 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 2594 | } |
1da177e4 | 2595 | |
9c14ceaf | 2596 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
458a9f61 | 2597 | { |
9c14ceaf FR |
2598 | struct net_device *dev = pci_get_drvdata(pdev); |
2599 | struct rtl8169_private *tp = netdev_priv(dev); | |
2600 | int cap = tp->pcie_cap; | |
2601 | ||
2602 | if (cap) { | |
2603 | u16 ctl; | |
458a9f61 | 2604 | |
9c14ceaf FR |
2605 | pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
2606 | ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; | |
2607 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); | |
2608 | } | |
458a9f61 FR |
2609 | } |
2610 | ||
dacf8154 FR |
2611 | static void rtl_csi_access_enable(void __iomem *ioaddr) |
2612 | { | |
2613 | u32 csi; | |
2614 | ||
2615 | csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; | |
2616 | rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); | |
2617 | } | |
2618 | ||
2619 | struct ephy_info { | |
2620 | unsigned int offset; | |
2621 | u16 mask; | |
2622 | u16 bits; | |
2623 | }; | |
2624 | ||
2625 | static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) | |
2626 | { | |
2627 | u16 w; | |
2628 | ||
2629 | while (len-- > 0) { | |
2630 | w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; | |
2631 | rtl_ephy_write(ioaddr, e->offset, w); | |
2632 | e++; | |
2633 | } | |
2634 | } | |
2635 | ||
b726e493 FR |
2636 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
2637 | { | |
2638 | struct net_device *dev = pci_get_drvdata(pdev); | |
2639 | struct rtl8169_private *tp = netdev_priv(dev); | |
2640 | int cap = tp->pcie_cap; | |
2641 | ||
2642 | if (cap) { | |
2643 | u16 ctl; | |
2644 | ||
2645 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
2646 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
2647 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
2648 | } | |
2649 | } | |
2650 | ||
2651 | #define R8168_CPCMD_QUIRK_MASK (\ | |
2652 | EnableBist | \ | |
2653 | Mac_dbgo_oe | \ | |
2654 | Force_half_dup | \ | |
2655 | Force_rxflow_en | \ | |
2656 | Force_txflow_en | \ | |
2657 | Cxpl_dbg_sel | \ | |
2658 | ASF | \ | |
2659 | PktCntrDisable | \ | |
2660 | Mac_dbgo_sel) | |
2661 | ||
219a1e9d FR |
2662 | static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
2663 | { | |
b726e493 FR |
2664 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
2665 | ||
2666 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2667 | ||
2e68ae44 FR |
2668 | rtl_tx_performance_tweak(pdev, |
2669 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
219a1e9d FR |
2670 | } |
2671 | ||
2672 | static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) | |
2673 | { | |
2674 | rtl_hw_start_8168bb(ioaddr, pdev); | |
b726e493 FR |
2675 | |
2676 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2677 | ||
2678 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
2679 | } |
2680 | ||
2681 | static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |
2682 | { | |
b726e493 FR |
2683 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
2684 | ||
2685 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2686 | ||
219a1e9d | 2687 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
b726e493 FR |
2688 | |
2689 | rtl_disable_clock_request(pdev); | |
2690 | ||
2691 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
2692 | } |
2693 | ||
ef3386f0 | 2694 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
219a1e9d | 2695 | { |
b726e493 FR |
2696 | static struct ephy_info e_info_8168cp[] = { |
2697 | { 0x01, 0, 0x0001 }, | |
2698 | { 0x02, 0x0800, 0x1000 }, | |
2699 | { 0x03, 0, 0x0042 }, | |
2700 | { 0x06, 0x0080, 0x0000 }, | |
2701 | { 0x07, 0, 0x2000 } | |
2702 | }; | |
2703 | ||
2704 | rtl_csi_access_enable(ioaddr); | |
2705 | ||
2706 | rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); | |
2707 | ||
219a1e9d FR |
2708 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2709 | } | |
2710 | ||
ef3386f0 FR |
2711 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
2712 | { | |
2713 | rtl_csi_access_enable(ioaddr); | |
2714 | ||
2715 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2716 | ||
2717 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2718 | ||
2719 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2720 | } | |
2721 | ||
7f3e3d3a FR |
2722 | static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
2723 | { | |
2724 | rtl_csi_access_enable(ioaddr); | |
2725 | ||
2726 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2727 | ||
2728 | /* Magic. */ | |
2729 | RTL_W8(DBG_REG, 0x20); | |
2730 | ||
2731 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2732 | ||
2733 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2734 | ||
2735 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2736 | } | |
2737 | ||
219a1e9d FR |
2738 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
2739 | { | |
b726e493 FR |
2740 | static struct ephy_info e_info_8168c_1[] = { |
2741 | { 0x02, 0x0800, 0x1000 }, | |
2742 | { 0x03, 0, 0x0002 }, | |
2743 | { 0x06, 0x0080, 0x0000 } | |
2744 | }; | |
2745 | ||
2746 | rtl_csi_access_enable(ioaddr); | |
2747 | ||
2748 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
2749 | ||
2750 | rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); | |
2751 | ||
219a1e9d FR |
2752 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2753 | } | |
2754 | ||
2755 | static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
2756 | { | |
b726e493 FR |
2757 | static struct ephy_info e_info_8168c_2[] = { |
2758 | { 0x01, 0, 0x0001 }, | |
2759 | { 0x03, 0x0400, 0x0220 } | |
2760 | }; | |
2761 | ||
2762 | rtl_csi_access_enable(ioaddr); | |
2763 | ||
2764 | rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); | |
2765 | ||
219a1e9d FR |
2766 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2767 | } | |
2768 | ||
197ff761 FR |
2769 | static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
2770 | { | |
2771 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
2772 | } | |
2773 | ||
6fb07058 FR |
2774 | static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
2775 | { | |
2776 | rtl_csi_access_enable(ioaddr); | |
2777 | ||
2778 | __rtl_hw_start_8168cp(ioaddr, pdev); | |
2779 | } | |
2780 | ||
5b538df9 FR |
2781 | static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
2782 | { | |
2783 | rtl_csi_access_enable(ioaddr); | |
2784 | ||
2785 | rtl_disable_clock_request(pdev); | |
2786 | ||
2787 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2788 | ||
2789 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2790 | ||
2791 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2792 | } | |
2793 | ||
07ce4064 FR |
2794 | static void rtl_hw_start_8168(struct net_device *dev) |
2795 | { | |
2dd99530 FR |
2796 | struct rtl8169_private *tp = netdev_priv(dev); |
2797 | void __iomem *ioaddr = tp->mmio_addr; | |
0e485150 | 2798 | struct pci_dev *pdev = tp->pci_dev; |
2dd99530 FR |
2799 | |
2800 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
2801 | ||
2802 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2803 | ||
fdd7b4c3 | 2804 | rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
2dd99530 | 2805 | |
0e485150 | 2806 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
2807 | |
2808 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2809 | ||
0e485150 | 2810 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 2811 | |
0e485150 FR |
2812 | /* Work around for RxFIFO overflow. */ |
2813 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { | |
2814 | tp->intr_event |= RxFIFOOver | PCSTimeout; | |
2815 | tp->intr_event &= ~RxOverflow; | |
2816 | } | |
2817 | ||
2818 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 2819 | |
b8363901 FR |
2820 | rtl_set_rx_mode(dev); |
2821 | ||
2822 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
2823 | (InterFrameGap << TxInterFrameGapShift)); | |
2dd99530 FR |
2824 | |
2825 | RTL_R8(IntrMask); | |
2826 | ||
219a1e9d FR |
2827 | switch (tp->mac_version) { |
2828 | case RTL_GIGA_MAC_VER_11: | |
2829 | rtl_hw_start_8168bb(ioaddr, pdev); | |
2830 | break; | |
2831 | ||
2832 | case RTL_GIGA_MAC_VER_12: | |
2833 | case RTL_GIGA_MAC_VER_17: | |
2834 | rtl_hw_start_8168bef(ioaddr, pdev); | |
2835 | break; | |
2836 | ||
2837 | case RTL_GIGA_MAC_VER_18: | |
ef3386f0 | 2838 | rtl_hw_start_8168cp_1(ioaddr, pdev); |
219a1e9d FR |
2839 | break; |
2840 | ||
2841 | case RTL_GIGA_MAC_VER_19: | |
2842 | rtl_hw_start_8168c_1(ioaddr, pdev); | |
2843 | break; | |
2844 | ||
2845 | case RTL_GIGA_MAC_VER_20: | |
2846 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
2847 | break; | |
2848 | ||
197ff761 FR |
2849 | case RTL_GIGA_MAC_VER_21: |
2850 | rtl_hw_start_8168c_3(ioaddr, pdev); | |
2851 | break; | |
2852 | ||
6fb07058 FR |
2853 | case RTL_GIGA_MAC_VER_22: |
2854 | rtl_hw_start_8168c_4(ioaddr, pdev); | |
2855 | break; | |
2856 | ||
ef3386f0 FR |
2857 | case RTL_GIGA_MAC_VER_23: |
2858 | rtl_hw_start_8168cp_2(ioaddr, pdev); | |
2859 | break; | |
2860 | ||
7f3e3d3a FR |
2861 | case RTL_GIGA_MAC_VER_24: |
2862 | rtl_hw_start_8168cp_3(ioaddr, pdev); | |
2863 | break; | |
2864 | ||
5b538df9 FR |
2865 | case RTL_GIGA_MAC_VER_25: |
2866 | rtl_hw_start_8168d(ioaddr, pdev); | |
2867 | break; | |
2868 | ||
219a1e9d FR |
2869 | default: |
2870 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
2871 | dev->name, tp->mac_version); | |
2872 | break; | |
2873 | } | |
2dd99530 | 2874 | |
0e485150 FR |
2875 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
2876 | ||
b8363901 FR |
2877 | RTL_W8(Cfg9346, Cfg9346_Lock); |
2878 | ||
2dd99530 | 2879 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
6dccd16b | 2880 | |
0e485150 | 2881 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 2882 | } |
1da177e4 | 2883 | |
2857ffb7 FR |
2884 | #define R810X_CPCMD_QUIRK_MASK (\ |
2885 | EnableBist | \ | |
2886 | Mac_dbgo_oe | \ | |
2887 | Force_half_dup | \ | |
5edcc537 | 2888 | Force_rxflow_en | \ |
2857ffb7 FR |
2889 | Force_txflow_en | \ |
2890 | Cxpl_dbg_sel | \ | |
2891 | ASF | \ | |
2892 | PktCntrDisable | \ | |
2893 | PCIDAC | \ | |
2894 | PCIMulRW) | |
2895 | ||
2896 | static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) | |
2897 | { | |
2898 | static struct ephy_info e_info_8102e_1[] = { | |
2899 | { 0x01, 0, 0x6e65 }, | |
2900 | { 0x02, 0, 0x091f }, | |
2901 | { 0x03, 0, 0xc2f9 }, | |
2902 | { 0x06, 0, 0xafb5 }, | |
2903 | { 0x07, 0, 0x0e00 }, | |
2904 | { 0x19, 0, 0xec80 }, | |
2905 | { 0x01, 0, 0x2e65 }, | |
2906 | { 0x01, 0, 0x6e65 } | |
2907 | }; | |
2908 | u8 cfg1; | |
2909 | ||
2910 | rtl_csi_access_enable(ioaddr); | |
2911 | ||
2912 | RTL_W8(DBG_REG, FIX_NAK_1); | |
2913 | ||
2914 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2915 | ||
2916 | RTL_W8(Config1, | |
2917 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
2918 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2919 | ||
2920 | cfg1 = RTL_R8(Config1); | |
2921 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
2922 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
2923 | ||
2924 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); | |
2925 | ||
2926 | rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); | |
2927 | } | |
2928 | ||
2929 | static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
2930 | { | |
2931 | rtl_csi_access_enable(ioaddr); | |
2932 | ||
2933 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2934 | ||
2935 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
2936 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2937 | ||
2938 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); | |
2939 | } | |
2940 | ||
2941 | static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) | |
2942 | { | |
2943 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
2944 | ||
2945 | rtl_ephy_write(ioaddr, 0x03, 0xc2f9); | |
2946 | } | |
2947 | ||
07ce4064 FR |
2948 | static void rtl_hw_start_8101(struct net_device *dev) |
2949 | { | |
cdf1a608 FR |
2950 | struct rtl8169_private *tp = netdev_priv(dev); |
2951 | void __iomem *ioaddr = tp->mmio_addr; | |
2952 | struct pci_dev *pdev = tp->pci_dev; | |
2953 | ||
e3cf0cc0 FR |
2954 | if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
2955 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
9c14ceaf FR |
2956 | int cap = tp->pcie_cap; |
2957 | ||
2958 | if (cap) { | |
2959 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, | |
2960 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
2961 | } | |
cdf1a608 FR |
2962 | } |
2963 | ||
2857ffb7 FR |
2964 | switch (tp->mac_version) { |
2965 | case RTL_GIGA_MAC_VER_07: | |
2966 | rtl_hw_start_8102e_1(ioaddr, pdev); | |
2967 | break; | |
2968 | ||
2969 | case RTL_GIGA_MAC_VER_08: | |
2970 | rtl_hw_start_8102e_3(ioaddr, pdev); | |
2971 | break; | |
2972 | ||
2973 | case RTL_GIGA_MAC_VER_09: | |
2974 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
2975 | break; | |
cdf1a608 FR |
2976 | } |
2977 | ||
2978 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
2979 | ||
2980 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2981 | ||
fdd7b4c3 | 2982 | rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz); |
cdf1a608 FR |
2983 | |
2984 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; | |
2985 | ||
2986 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2987 | ||
2988 | RTL_W16(IntrMitigate, 0x0000); | |
2989 | ||
2990 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2991 | ||
2992 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2993 | rtl_set_rx_tx_config_registers(tp); | |
2994 | ||
2995 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
2996 | ||
2997 | RTL_R8(IntrMask); | |
2998 | ||
cdf1a608 FR |
2999 | rtl_set_rx_mode(dev); |
3000 | ||
0e485150 FR |
3001 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
3002 | ||
cdf1a608 | 3003 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
6dccd16b | 3004 | |
0e485150 | 3005 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
3006 | } |
3007 | ||
3008 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
3009 | { | |
3010 | struct rtl8169_private *tp = netdev_priv(dev); | |
3011 | int ret = 0; | |
3012 | ||
3013 | if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) | |
3014 | return -EINVAL; | |
3015 | ||
3016 | dev->mtu = new_mtu; | |
3017 | ||
3018 | if (!netif_running(dev)) | |
3019 | goto out; | |
3020 | ||
3021 | rtl8169_down(dev); | |
3022 | ||
3023 | rtl8169_set_rxbufsize(tp, dev); | |
3024 | ||
3025 | ret = rtl8169_init_ring(dev); | |
3026 | if (ret < 0) | |
3027 | goto out; | |
3028 | ||
bea3348e | 3029 | napi_enable(&tp->napi); |
1da177e4 | 3030 | |
07ce4064 | 3031 | rtl_hw_start(dev); |
1da177e4 LT |
3032 | |
3033 | rtl8169_request_timer(dev); | |
3034 | ||
3035 | out: | |
3036 | return ret; | |
3037 | } | |
3038 | ||
3039 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
3040 | { | |
95e0918d | 3041 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
3042 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
3043 | } | |
3044 | ||
3045 | static void rtl8169_free_rx_skb(struct rtl8169_private *tp, | |
3046 | struct sk_buff **sk_buff, struct RxDesc *desc) | |
3047 | { | |
3048 | struct pci_dev *pdev = tp->pci_dev; | |
3049 | ||
3050 | pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, | |
3051 | PCI_DMA_FROMDEVICE); | |
3052 | dev_kfree_skb(*sk_buff); | |
3053 | *sk_buff = NULL; | |
3054 | rtl8169_make_unusable_by_asic(desc); | |
3055 | } | |
3056 | ||
3057 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
3058 | { | |
3059 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
3060 | ||
3061 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
3062 | } | |
3063 | ||
3064 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
3065 | u32 rx_buf_sz) | |
3066 | { | |
3067 | desc->addr = cpu_to_le64(mapping); | |
3068 | wmb(); | |
3069 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
3070 | } | |
3071 | ||
15d31758 SH |
3072 | static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
3073 | struct net_device *dev, | |
3074 | struct RxDesc *desc, int rx_buf_sz, | |
3075 | unsigned int align) | |
1da177e4 LT |
3076 | { |
3077 | struct sk_buff *skb; | |
3078 | dma_addr_t mapping; | |
e9f63f30 | 3079 | unsigned int pad; |
1da177e4 | 3080 | |
e9f63f30 FR |
3081 | pad = align ? align : NET_IP_ALIGN; |
3082 | ||
3083 | skb = netdev_alloc_skb(dev, rx_buf_sz + pad); | |
1da177e4 LT |
3084 | if (!skb) |
3085 | goto err_out; | |
3086 | ||
e9f63f30 | 3087 | skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
1da177e4 | 3088 | |
689be439 | 3089 | mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
1da177e4 LT |
3090 | PCI_DMA_FROMDEVICE); |
3091 | ||
3092 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
1da177e4 | 3093 | out: |
15d31758 | 3094 | return skb; |
1da177e4 LT |
3095 | |
3096 | err_out: | |
1da177e4 LT |
3097 | rtl8169_make_unusable_by_asic(desc); |
3098 | goto out; | |
3099 | } | |
3100 | ||
3101 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
3102 | { | |
07d3f51f | 3103 | unsigned int i; |
1da177e4 LT |
3104 | |
3105 | for (i = 0; i < NUM_RX_DESC; i++) { | |
3106 | if (tp->Rx_skbuff[i]) { | |
3107 | rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, | |
3108 | tp->RxDescArray + i); | |
3109 | } | |
3110 | } | |
3111 | } | |
3112 | ||
3113 | static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, | |
3114 | u32 start, u32 end) | |
3115 | { | |
3116 | u32 cur; | |
5b0384f4 | 3117 | |
4ae47c2d | 3118 | for (cur = start; end - cur != 0; cur++) { |
15d31758 SH |
3119 | struct sk_buff *skb; |
3120 | unsigned int i = cur % NUM_RX_DESC; | |
1da177e4 | 3121 | |
4ae47c2d FR |
3122 | WARN_ON((s32)(end - cur) < 0); |
3123 | ||
1da177e4 LT |
3124 | if (tp->Rx_skbuff[i]) |
3125 | continue; | |
bcf0bf90 | 3126 | |
15d31758 SH |
3127 | skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
3128 | tp->RxDescArray + i, | |
3129 | tp->rx_buf_sz, tp->align); | |
3130 | if (!skb) | |
1da177e4 | 3131 | break; |
15d31758 SH |
3132 | |
3133 | tp->Rx_skbuff[i] = skb; | |
1da177e4 LT |
3134 | } |
3135 | return cur - start; | |
3136 | } | |
3137 | ||
3138 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) | |
3139 | { | |
3140 | desc->opts1 |= cpu_to_le32(RingEnd); | |
3141 | } | |
3142 | ||
3143 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) | |
3144 | { | |
3145 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
3146 | } | |
3147 | ||
3148 | static int rtl8169_init_ring(struct net_device *dev) | |
3149 | { | |
3150 | struct rtl8169_private *tp = netdev_priv(dev); | |
3151 | ||
3152 | rtl8169_init_ring_indexes(tp); | |
3153 | ||
3154 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
3155 | memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); | |
3156 | ||
3157 | if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) | |
3158 | goto err_out; | |
3159 | ||
3160 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); | |
3161 | ||
3162 | return 0; | |
3163 | ||
3164 | err_out: | |
3165 | rtl8169_rx_clear(tp); | |
3166 | return -ENOMEM; | |
3167 | } | |
3168 | ||
3169 | static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, | |
3170 | struct TxDesc *desc) | |
3171 | { | |
3172 | unsigned int len = tx_skb->len; | |
3173 | ||
3174 | pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); | |
3175 | desc->opts1 = 0x00; | |
3176 | desc->opts2 = 0x00; | |
3177 | desc->addr = 0x00; | |
3178 | tx_skb->len = 0; | |
3179 | } | |
3180 | ||
3181 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
3182 | { | |
3183 | unsigned int i; | |
3184 | ||
3185 | for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { | |
3186 | unsigned int entry = i % NUM_TX_DESC; | |
3187 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
3188 | unsigned int len = tx_skb->len; | |
3189 | ||
3190 | if (len) { | |
3191 | struct sk_buff *skb = tx_skb->skb; | |
3192 | ||
3193 | rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, | |
3194 | tp->TxDescArray + entry); | |
3195 | if (skb) { | |
3196 | dev_kfree_skb(skb); | |
3197 | tx_skb->skb = NULL; | |
3198 | } | |
cebf8cc7 | 3199 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
3200 | } |
3201 | } | |
3202 | tp->cur_tx = tp->dirty_tx = 0; | |
3203 | } | |
3204 | ||
c4028958 | 3205 | static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
1da177e4 LT |
3206 | { |
3207 | struct rtl8169_private *tp = netdev_priv(dev); | |
3208 | ||
c4028958 | 3209 | PREPARE_DELAYED_WORK(&tp->task, task); |
1da177e4 LT |
3210 | schedule_delayed_work(&tp->task, 4); |
3211 | } | |
3212 | ||
3213 | static void rtl8169_wait_for_quiescence(struct net_device *dev) | |
3214 | { | |
3215 | struct rtl8169_private *tp = netdev_priv(dev); | |
3216 | void __iomem *ioaddr = tp->mmio_addr; | |
3217 | ||
3218 | synchronize_irq(dev->irq); | |
3219 | ||
3220 | /* Wait for any pending NAPI task to complete */ | |
bea3348e | 3221 | napi_disable(&tp->napi); |
1da177e4 LT |
3222 | |
3223 | rtl8169_irq_mask_and_ack(ioaddr); | |
3224 | ||
d1d08d12 DM |
3225 | tp->intr_mask = 0xffff; |
3226 | RTL_W16(IntrMask, tp->intr_event); | |
bea3348e | 3227 | napi_enable(&tp->napi); |
1da177e4 LT |
3228 | } |
3229 | ||
c4028958 | 3230 | static void rtl8169_reinit_task(struct work_struct *work) |
1da177e4 | 3231 | { |
c4028958 DH |
3232 | struct rtl8169_private *tp = |
3233 | container_of(work, struct rtl8169_private, task.work); | |
3234 | struct net_device *dev = tp->dev; | |
1da177e4 LT |
3235 | int ret; |
3236 | ||
eb2a021c FR |
3237 | rtnl_lock(); |
3238 | ||
3239 | if (!netif_running(dev)) | |
3240 | goto out_unlock; | |
3241 | ||
3242 | rtl8169_wait_for_quiescence(dev); | |
3243 | rtl8169_close(dev); | |
1da177e4 LT |
3244 | |
3245 | ret = rtl8169_open(dev); | |
3246 | if (unlikely(ret < 0)) { | |
07d3f51f | 3247 | if (net_ratelimit() && netif_msg_drv(tp)) { |
53edbecd | 3248 | printk(KERN_ERR PFX "%s: reinit failure (status = %d)." |
07d3f51f | 3249 | " Rescheduling.\n", dev->name, ret); |
1da177e4 LT |
3250 | } |
3251 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
3252 | } | |
eb2a021c FR |
3253 | |
3254 | out_unlock: | |
3255 | rtnl_unlock(); | |
1da177e4 LT |
3256 | } |
3257 | ||
c4028958 | 3258 | static void rtl8169_reset_task(struct work_struct *work) |
1da177e4 | 3259 | { |
c4028958 DH |
3260 | struct rtl8169_private *tp = |
3261 | container_of(work, struct rtl8169_private, task.work); | |
3262 | struct net_device *dev = tp->dev; | |
1da177e4 | 3263 | |
eb2a021c FR |
3264 | rtnl_lock(); |
3265 | ||
1da177e4 | 3266 | if (!netif_running(dev)) |
eb2a021c | 3267 | goto out_unlock; |
1da177e4 LT |
3268 | |
3269 | rtl8169_wait_for_quiescence(dev); | |
3270 | ||
bea3348e | 3271 | rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
1da177e4 LT |
3272 | rtl8169_tx_clear(tp); |
3273 | ||
3274 | if (tp->dirty_rx == tp->cur_rx) { | |
3275 | rtl8169_init_ring_indexes(tp); | |
07ce4064 | 3276 | rtl_hw_start(dev); |
1da177e4 | 3277 | netif_wake_queue(dev); |
cebf8cc7 | 3278 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
1da177e4 | 3279 | } else { |
07d3f51f | 3280 | if (net_ratelimit() && netif_msg_intr(tp)) { |
53edbecd | 3281 | printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", |
07d3f51f | 3282 | dev->name); |
1da177e4 LT |
3283 | } |
3284 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
3285 | } | |
eb2a021c FR |
3286 | |
3287 | out_unlock: | |
3288 | rtnl_unlock(); | |
1da177e4 LT |
3289 | } |
3290 | ||
3291 | static void rtl8169_tx_timeout(struct net_device *dev) | |
3292 | { | |
3293 | struct rtl8169_private *tp = netdev_priv(dev); | |
3294 | ||
3295 | rtl8169_hw_reset(tp->mmio_addr); | |
3296 | ||
3297 | /* Let's wait a bit while any (async) irq lands on */ | |
3298 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
3299 | } | |
3300 | ||
3301 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
3302 | u32 opts1) | |
3303 | { | |
3304 | struct skb_shared_info *info = skb_shinfo(skb); | |
3305 | unsigned int cur_frag, entry; | |
a6343afb | 3306 | struct TxDesc * uninitialized_var(txd); |
1da177e4 LT |
3307 | |
3308 | entry = tp->cur_tx; | |
3309 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
3310 | skb_frag_t *frag = info->frags + cur_frag; | |
3311 | dma_addr_t mapping; | |
3312 | u32 status, len; | |
3313 | void *addr; | |
3314 | ||
3315 | entry = (entry + 1) % NUM_TX_DESC; | |
3316 | ||
3317 | txd = tp->TxDescArray + entry; | |
3318 | len = frag->size; | |
3319 | addr = ((void *) page_address(frag->page)) + frag->page_offset; | |
3320 | mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); | |
3321 | ||
3322 | /* anti gcc 2.95.3 bugware (sic) */ | |
3323 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
3324 | ||
3325 | txd->opts1 = cpu_to_le32(status); | |
3326 | txd->addr = cpu_to_le64(mapping); | |
3327 | ||
3328 | tp->tx_skb[entry].len = len; | |
3329 | } | |
3330 | ||
3331 | if (cur_frag) { | |
3332 | tp->tx_skb[entry].skb = skb; | |
3333 | txd->opts1 |= cpu_to_le32(LastFrag); | |
3334 | } | |
3335 | ||
3336 | return cur_frag; | |
3337 | } | |
3338 | ||
3339 | static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) | |
3340 | { | |
3341 | if (dev->features & NETIF_F_TSO) { | |
7967168c | 3342 | u32 mss = skb_shinfo(skb)->gso_size; |
1da177e4 LT |
3343 | |
3344 | if (mss) | |
3345 | return LargeSend | ((mss & MSSMask) << MSSShift); | |
3346 | } | |
84fa7933 | 3347 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 3348 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
3349 | |
3350 | if (ip->protocol == IPPROTO_TCP) | |
3351 | return IPCS | TCPCS; | |
3352 | else if (ip->protocol == IPPROTO_UDP) | |
3353 | return IPCS | UDPCS; | |
3354 | WARN_ON(1); /* we need a WARN() */ | |
3355 | } | |
3356 | return 0; | |
3357 | } | |
3358 | ||
61357325 SH |
3359 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
3360 | struct net_device *dev) | |
1da177e4 LT |
3361 | { |
3362 | struct rtl8169_private *tp = netdev_priv(dev); | |
3363 | unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; | |
3364 | struct TxDesc *txd = tp->TxDescArray + entry; | |
3365 | void __iomem *ioaddr = tp->mmio_addr; | |
3366 | dma_addr_t mapping; | |
3367 | u32 status, len; | |
3368 | u32 opts1; | |
5b0384f4 | 3369 | |
1da177e4 | 3370 | if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
b57b7e5a SH |
3371 | if (netif_msg_drv(tp)) { |
3372 | printk(KERN_ERR | |
3373 | "%s: BUG! Tx Ring full when queue awake!\n", | |
3374 | dev->name); | |
3375 | } | |
1da177e4 LT |
3376 | goto err_stop; |
3377 | } | |
3378 | ||
3379 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3380 | goto err_stop; | |
3381 | ||
3382 | opts1 = DescOwn | rtl8169_tso_csum(skb, dev); | |
3383 | ||
3384 | frags = rtl8169_xmit_frags(tp, skb, opts1); | |
3385 | if (frags) { | |
3386 | len = skb_headlen(skb); | |
3387 | opts1 |= FirstFrag; | |
3388 | } else { | |
3389 | len = skb->len; | |
1da177e4 LT |
3390 | opts1 |= FirstFrag | LastFrag; |
3391 | tp->tx_skb[entry].skb = skb; | |
3392 | } | |
3393 | ||
3394 | mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); | |
3395 | ||
3396 | tp->tx_skb[entry].len = len; | |
3397 | txd->addr = cpu_to_le64(mapping); | |
3398 | txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); | |
3399 | ||
3400 | wmb(); | |
3401 | ||
3402 | /* anti gcc 2.95.3 bugware (sic) */ | |
3403 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
3404 | txd->opts1 = cpu_to_le32(status); | |
3405 | ||
1da177e4 LT |
3406 | tp->cur_tx += frags + 1; |
3407 | ||
3408 | smp_wmb(); | |
3409 | ||
275391a4 | 3410 | RTL_W8(TxPoll, NPQ); /* set polling bit */ |
1da177e4 LT |
3411 | |
3412 | if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { | |
3413 | netif_stop_queue(dev); | |
3414 | smp_rmb(); | |
3415 | if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) | |
3416 | netif_wake_queue(dev); | |
3417 | } | |
3418 | ||
61357325 | 3419 | return NETDEV_TX_OK; |
1da177e4 LT |
3420 | |
3421 | err_stop: | |
3422 | netif_stop_queue(dev); | |
cebf8cc7 | 3423 | dev->stats.tx_dropped++; |
61357325 | 3424 | return NETDEV_TX_BUSY; |
1da177e4 LT |
3425 | } |
3426 | ||
3427 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
3428 | { | |
3429 | struct rtl8169_private *tp = netdev_priv(dev); | |
3430 | struct pci_dev *pdev = tp->pci_dev; | |
3431 | void __iomem *ioaddr = tp->mmio_addr; | |
3432 | u16 pci_status, pci_cmd; | |
3433 | ||
3434 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
3435 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
3436 | ||
b57b7e5a SH |
3437 | if (netif_msg_intr(tp)) { |
3438 | printk(KERN_ERR | |
3439 | "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", | |
3440 | dev->name, pci_cmd, pci_status); | |
3441 | } | |
1da177e4 LT |
3442 | |
3443 | /* | |
3444 | * The recovery sequence below admits a very elaborated explanation: | |
3445 | * - it seems to work; | |
d03902b8 FR |
3446 | * - I did not see what else could be done; |
3447 | * - it makes iop3xx happy. | |
1da177e4 LT |
3448 | * |
3449 | * Feel free to adjust to your needs. | |
3450 | */ | |
a27993f3 | 3451 | if (pdev->broken_parity_status) |
d03902b8 FR |
3452 | pci_cmd &= ~PCI_COMMAND_PARITY; |
3453 | else | |
3454 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
3455 | ||
3456 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
3457 | |
3458 | pci_write_config_word(pdev, PCI_STATUS, | |
3459 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
3460 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
3461 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
3462 | ||
3463 | /* The infamous DAC f*ckup only happens at boot time */ | |
3464 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
b57b7e5a SH |
3465 | if (netif_msg_intr(tp)) |
3466 | printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); | |
1da177e4 LT |
3467 | tp->cp_cmd &= ~PCIDAC; |
3468 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
3469 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
3470 | } |
3471 | ||
3472 | rtl8169_hw_reset(ioaddr); | |
d03902b8 FR |
3473 | |
3474 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
1da177e4 LT |
3475 | } |
3476 | ||
07d3f51f FR |
3477 | static void rtl8169_tx_interrupt(struct net_device *dev, |
3478 | struct rtl8169_private *tp, | |
3479 | void __iomem *ioaddr) | |
1da177e4 LT |
3480 | { |
3481 | unsigned int dirty_tx, tx_left; | |
3482 | ||
1da177e4 LT |
3483 | dirty_tx = tp->dirty_tx; |
3484 | smp_rmb(); | |
3485 | tx_left = tp->cur_tx - dirty_tx; | |
3486 | ||
3487 | while (tx_left > 0) { | |
3488 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
3489 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
3490 | u32 len = tx_skb->len; | |
3491 | u32 status; | |
3492 | ||
3493 | rmb(); | |
3494 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
3495 | if (status & DescOwn) | |
3496 | break; | |
3497 | ||
cebf8cc7 FR |
3498 | dev->stats.tx_bytes += len; |
3499 | dev->stats.tx_packets++; | |
1da177e4 LT |
3500 | |
3501 | rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); | |
3502 | ||
3503 | if (status & LastFrag) { | |
87433bfc | 3504 | dev_kfree_skb(tx_skb->skb); |
1da177e4 LT |
3505 | tx_skb->skb = NULL; |
3506 | } | |
3507 | dirty_tx++; | |
3508 | tx_left--; | |
3509 | } | |
3510 | ||
3511 | if (tp->dirty_tx != dirty_tx) { | |
3512 | tp->dirty_tx = dirty_tx; | |
3513 | smp_wmb(); | |
3514 | if (netif_queue_stopped(dev) && | |
3515 | (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { | |
3516 | netif_wake_queue(dev); | |
3517 | } | |
d78ae2dc FR |
3518 | /* |
3519 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
3520 | * too close. Let's kick an extra TxPoll request when a burst | |
3521 | * of start_xmit activity is detected (if it is not detected, | |
3522 | * it is slow enough). -- FR | |
3523 | */ | |
3524 | smp_rmb(); | |
3525 | if (tp->cur_tx != dirty_tx) | |
3526 | RTL_W8(TxPoll, NPQ); | |
1da177e4 LT |
3527 | } |
3528 | } | |
3529 | ||
126fa4b9 FR |
3530 | static inline int rtl8169_fragmented_frame(u32 status) |
3531 | { | |
3532 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
3533 | } | |
3534 | ||
1da177e4 LT |
3535 | static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
3536 | { | |
3537 | u32 opts1 = le32_to_cpu(desc->opts1); | |
3538 | u32 status = opts1 & RxProtoMask; | |
3539 | ||
3540 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
3541 | ((status == RxProtoUDP) && !(opts1 & UDPFail)) || | |
3542 | ((status == RxProtoIP) && !(opts1 & IPFail))) | |
3543 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3544 | else | |
3545 | skb->ip_summed = CHECKSUM_NONE; | |
3546 | } | |
3547 | ||
07d3f51f FR |
3548 | static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
3549 | struct rtl8169_private *tp, int pkt_size, | |
3550 | dma_addr_t addr) | |
1da177e4 | 3551 | { |
b449655f SH |
3552 | struct sk_buff *skb; |
3553 | bool done = false; | |
1da177e4 | 3554 | |
b449655f SH |
3555 | if (pkt_size >= rx_copybreak) |
3556 | goto out; | |
1da177e4 | 3557 | |
07d3f51f | 3558 | skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
b449655f SH |
3559 | if (!skb) |
3560 | goto out; | |
3561 | ||
07d3f51f FR |
3562 | pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
3563 | PCI_DMA_FROMDEVICE); | |
86402234 | 3564 | skb_reserve(skb, NET_IP_ALIGN); |
b449655f SH |
3565 | skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
3566 | *sk_buff = skb; | |
3567 | done = true; | |
3568 | out: | |
3569 | return done; | |
1da177e4 LT |
3570 | } |
3571 | ||
07d3f51f FR |
3572 | static int rtl8169_rx_interrupt(struct net_device *dev, |
3573 | struct rtl8169_private *tp, | |
bea3348e | 3574 | void __iomem *ioaddr, u32 budget) |
1da177e4 LT |
3575 | { |
3576 | unsigned int cur_rx, rx_left; | |
3577 | unsigned int delta, count; | |
3578 | ||
1da177e4 LT |
3579 | cur_rx = tp->cur_rx; |
3580 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
865c652d | 3581 | rx_left = min(rx_left, budget); |
1da177e4 | 3582 | |
4dcb7d33 | 3583 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 3584 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 3585 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
3586 | u32 status; |
3587 | ||
3588 | rmb(); | |
126fa4b9 | 3589 | status = le32_to_cpu(desc->opts1); |
1da177e4 LT |
3590 | |
3591 | if (status & DescOwn) | |
3592 | break; | |
4dcb7d33 | 3593 | if (unlikely(status & RxRES)) { |
b57b7e5a SH |
3594 | if (netif_msg_rx_err(tp)) { |
3595 | printk(KERN_INFO | |
3596 | "%s: Rx ERROR. status = %08x\n", | |
3597 | dev->name, status); | |
3598 | } | |
cebf8cc7 | 3599 | dev->stats.rx_errors++; |
1da177e4 | 3600 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 3601 | dev->stats.rx_length_errors++; |
1da177e4 | 3602 | if (status & RxCRC) |
cebf8cc7 | 3603 | dev->stats.rx_crc_errors++; |
9dccf611 FR |
3604 | if (status & RxFOVF) { |
3605 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
cebf8cc7 | 3606 | dev->stats.rx_fifo_errors++; |
9dccf611 | 3607 | } |
126fa4b9 | 3608 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
1da177e4 | 3609 | } else { |
1da177e4 | 3610 | struct sk_buff *skb = tp->Rx_skbuff[entry]; |
b449655f | 3611 | dma_addr_t addr = le64_to_cpu(desc->addr); |
1da177e4 | 3612 | int pkt_size = (status & 0x00001FFF) - 4; |
b449655f | 3613 | struct pci_dev *pdev = tp->pci_dev; |
1da177e4 | 3614 | |
126fa4b9 FR |
3615 | /* |
3616 | * The driver does not support incoming fragmented | |
3617 | * frames. They are seen as a symptom of over-mtu | |
3618 | * sized frames. | |
3619 | */ | |
3620 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
3621 | dev->stats.rx_dropped++; |
3622 | dev->stats.rx_length_errors++; | |
126fa4b9 | 3623 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
4dcb7d33 | 3624 | continue; |
126fa4b9 FR |
3625 | } |
3626 | ||
1da177e4 | 3627 | rtl8169_rx_csum(skb, desc); |
bcf0bf90 | 3628 | |
07d3f51f | 3629 | if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { |
b449655f SH |
3630 | pci_dma_sync_single_for_device(pdev, addr, |
3631 | pkt_size, PCI_DMA_FROMDEVICE); | |
3632 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); | |
3633 | } else { | |
a866bbf6 | 3634 | pci_unmap_single(pdev, addr, tp->rx_buf_sz, |
b449655f | 3635 | PCI_DMA_FROMDEVICE); |
1da177e4 LT |
3636 | tp->Rx_skbuff[entry] = NULL; |
3637 | } | |
3638 | ||
1da177e4 LT |
3639 | skb_put(skb, pkt_size); |
3640 | skb->protocol = eth_type_trans(skb, dev); | |
3641 | ||
3642 | if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) | |
865c652d | 3643 | netif_receive_skb(skb); |
1da177e4 | 3644 | |
cebf8cc7 FR |
3645 | dev->stats.rx_bytes += pkt_size; |
3646 | dev->stats.rx_packets++; | |
1da177e4 | 3647 | } |
6dccd16b FR |
3648 | |
3649 | /* Work around for AMD plateform. */ | |
95e0918d | 3650 | if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
6dccd16b FR |
3651 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
3652 | desc->opts2 = 0; | |
3653 | cur_rx++; | |
3654 | } | |
1da177e4 LT |
3655 | } |
3656 | ||
3657 | count = cur_rx - tp->cur_rx; | |
3658 | tp->cur_rx = cur_rx; | |
3659 | ||
3660 | delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); | |
b57b7e5a | 3661 | if (!delta && count && netif_msg_intr(tp)) |
1da177e4 LT |
3662 | printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
3663 | tp->dirty_rx += delta; | |
3664 | ||
3665 | /* | |
3666 | * FIXME: until there is periodic timer to try and refill the ring, | |
3667 | * a temporary shortage may definitely kill the Rx process. | |
3668 | * - disable the asic to try and avoid an overflow and kick it again | |
3669 | * after refill ? | |
3670 | * - how do others driver handle this condition (Uh oh...). | |
3671 | */ | |
b57b7e5a | 3672 | if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
1da177e4 LT |
3673 | printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
3674 | ||
3675 | return count; | |
3676 | } | |
3677 | ||
07d3f51f | 3678 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 3679 | { |
07d3f51f | 3680 | struct net_device *dev = dev_instance; |
1da177e4 | 3681 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 3682 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 3683 | int handled = 0; |
865c652d | 3684 | int status; |
1da177e4 | 3685 | |
f11a377b DD |
3686 | /* loop handling interrupts until we have no new ones or |
3687 | * we hit a invalid/hotplug case. | |
3688 | */ | |
865c652d | 3689 | status = RTL_R16(IntrStatus); |
f11a377b DD |
3690 | while (status && status != 0xffff) { |
3691 | handled = 1; | |
1da177e4 | 3692 | |
f11a377b DD |
3693 | /* Handle all of the error cases first. These will reset |
3694 | * the chip, so just exit the loop. | |
3695 | */ | |
3696 | if (unlikely(!netif_running(dev))) { | |
3697 | rtl8169_asic_down(ioaddr); | |
3698 | break; | |
3699 | } | |
1da177e4 | 3700 | |
f11a377b DD |
3701 | /* Work around for rx fifo overflow */ |
3702 | if (unlikely(status & RxFIFOOver) && | |
3703 | (tp->mac_version == RTL_GIGA_MAC_VER_11)) { | |
3704 | netif_stop_queue(dev); | |
3705 | rtl8169_tx_timeout(dev); | |
3706 | break; | |
3707 | } | |
1da177e4 | 3708 | |
f11a377b DD |
3709 | if (unlikely(status & SYSErr)) { |
3710 | rtl8169_pcierr_interrupt(dev); | |
3711 | break; | |
3712 | } | |
1da177e4 | 3713 | |
f11a377b DD |
3714 | if (status & LinkChg) |
3715 | rtl8169_check_link_status(dev, tp, ioaddr); | |
0e485150 | 3716 | |
f11a377b DD |
3717 | /* We need to see the lastest version of tp->intr_mask to |
3718 | * avoid ignoring an MSI interrupt and having to wait for | |
3719 | * another event which may never come. | |
3720 | */ | |
3721 | smp_rmb(); | |
3722 | if (status & tp->intr_mask & tp->napi_event) { | |
3723 | RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); | |
3724 | tp->intr_mask = ~tp->napi_event; | |
3725 | ||
3726 | if (likely(napi_schedule_prep(&tp->napi))) | |
3727 | __napi_schedule(&tp->napi); | |
3728 | else if (netif_msg_intr(tp)) { | |
3729 | printk(KERN_INFO "%s: interrupt %04x in poll\n", | |
3730 | dev->name, status); | |
3731 | } | |
3732 | } | |
1da177e4 | 3733 | |
f11a377b DD |
3734 | /* We only get a new MSI interrupt when all active irq |
3735 | * sources on the chip have been acknowledged. So, ack | |
3736 | * everything we've seen and check if new sources have become | |
3737 | * active to avoid blocking all interrupts from the chip. | |
3738 | */ | |
3739 | RTL_W16(IntrStatus, | |
3740 | (status & RxFIFOOver) ? (status | RxOverflow) : status); | |
3741 | status = RTL_R16(IntrStatus); | |
865c652d | 3742 | } |
1da177e4 | 3743 | |
1da177e4 LT |
3744 | return IRQ_RETVAL(handled); |
3745 | } | |
3746 | ||
bea3348e | 3747 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 3748 | { |
bea3348e SH |
3749 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
3750 | struct net_device *dev = tp->dev; | |
1da177e4 | 3751 | void __iomem *ioaddr = tp->mmio_addr; |
bea3348e | 3752 | int work_done; |
1da177e4 | 3753 | |
bea3348e | 3754 | work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
1da177e4 LT |
3755 | rtl8169_tx_interrupt(dev, tp, ioaddr); |
3756 | ||
bea3348e | 3757 | if (work_done < budget) { |
288379f0 | 3758 | napi_complete(napi); |
f11a377b DD |
3759 | |
3760 | /* We need for force the visibility of tp->intr_mask | |
3761 | * for other CPUs, as we can loose an MSI interrupt | |
3762 | * and potentially wait for a retransmit timeout if we don't. | |
3763 | * The posted write to IntrMask is safe, as it will | |
3764 | * eventually make it to the chip and we won't loose anything | |
3765 | * until it does. | |
1da177e4 | 3766 | */ |
f11a377b | 3767 | tp->intr_mask = 0xffff; |
1da177e4 | 3768 | smp_wmb(); |
0e485150 | 3769 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
3770 | } |
3771 | ||
bea3348e | 3772 | return work_done; |
1da177e4 | 3773 | } |
1da177e4 | 3774 | |
523a6094 FR |
3775 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
3776 | { | |
3777 | struct rtl8169_private *tp = netdev_priv(dev); | |
3778 | ||
3779 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
3780 | return; | |
3781 | ||
3782 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
3783 | RTL_W32(RxMissed, 0); | |
3784 | } | |
3785 | ||
1da177e4 LT |
3786 | static void rtl8169_down(struct net_device *dev) |
3787 | { | |
3788 | struct rtl8169_private *tp = netdev_priv(dev); | |
3789 | void __iomem *ioaddr = tp->mmio_addr; | |
733b736c | 3790 | unsigned int intrmask; |
1da177e4 LT |
3791 | |
3792 | rtl8169_delete_timer(dev); | |
3793 | ||
3794 | netif_stop_queue(dev); | |
3795 | ||
93dd79e8 | 3796 | napi_disable(&tp->napi); |
93dd79e8 | 3797 | |
1da177e4 LT |
3798 | core_down: |
3799 | spin_lock_irq(&tp->lock); | |
3800 | ||
3801 | rtl8169_asic_down(ioaddr); | |
3802 | ||
523a6094 | 3803 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
3804 | |
3805 | spin_unlock_irq(&tp->lock); | |
3806 | ||
3807 | synchronize_irq(dev->irq); | |
3808 | ||
1da177e4 | 3809 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
fbd568a3 | 3810 | synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
1da177e4 LT |
3811 | |
3812 | /* | |
3813 | * And now for the 50k$ question: are IRQ disabled or not ? | |
3814 | * | |
3815 | * Two paths lead here: | |
3816 | * 1) dev->close | |
3817 | * -> netif_running() is available to sync the current code and the | |
3818 | * IRQ handler. See rtl8169_interrupt for details. | |
3819 | * 2) dev->change_mtu | |
3820 | * -> rtl8169_poll can not be issued again and re-enable the | |
3821 | * interruptions. Let's simply issue the IRQ down sequence again. | |
733b736c AP |
3822 | * |
3823 | * No loop if hotpluged or major error (0xffff). | |
1da177e4 | 3824 | */ |
733b736c AP |
3825 | intrmask = RTL_R16(IntrMask); |
3826 | if (intrmask && (intrmask != 0xffff)) | |
1da177e4 LT |
3827 | goto core_down; |
3828 | ||
3829 | rtl8169_tx_clear(tp); | |
3830 | ||
3831 | rtl8169_rx_clear(tp); | |
3832 | } | |
3833 | ||
3834 | static int rtl8169_close(struct net_device *dev) | |
3835 | { | |
3836 | struct rtl8169_private *tp = netdev_priv(dev); | |
3837 | struct pci_dev *pdev = tp->pci_dev; | |
3838 | ||
355423d0 IV |
3839 | /* update counters before going down */ |
3840 | rtl8169_update_counters(dev); | |
3841 | ||
1da177e4 LT |
3842 | rtl8169_down(dev); |
3843 | ||
3844 | free_irq(dev->irq, dev); | |
3845 | ||
1da177e4 LT |
3846 | pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
3847 | tp->RxPhyAddr); | |
3848 | pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
3849 | tp->TxPhyAddr); | |
3850 | tp->TxDescArray = NULL; | |
3851 | tp->RxDescArray = NULL; | |
3852 | ||
3853 | return 0; | |
3854 | } | |
3855 | ||
07ce4064 | 3856 | static void rtl_set_rx_mode(struct net_device *dev) |
1da177e4 LT |
3857 | { |
3858 | struct rtl8169_private *tp = netdev_priv(dev); | |
3859 | void __iomem *ioaddr = tp->mmio_addr; | |
3860 | unsigned long flags; | |
3861 | u32 mc_filter[2]; /* Multicast hash filter */ | |
07d3f51f | 3862 | int rx_mode; |
1da177e4 LT |
3863 | u32 tmp = 0; |
3864 | ||
3865 | if (dev->flags & IFF_PROMISC) { | |
3866 | /* Unconditionally log net taps. */ | |
b57b7e5a SH |
3867 | if (netif_msg_link(tp)) { |
3868 | printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", | |
3869 | dev->name); | |
3870 | } | |
1da177e4 LT |
3871 | rx_mode = |
3872 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
3873 | AcceptAllPhys; | |
3874 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
3875 | } else if ((dev->mc_count > multicast_filter_limit) | |
3876 | || (dev->flags & IFF_ALLMULTI)) { | |
3877 | /* Too many to filter perfectly -- accept all multicasts. */ | |
3878 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
3879 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
3880 | } else { | |
3881 | struct dev_mc_list *mclist; | |
07d3f51f FR |
3882 | unsigned int i; |
3883 | ||
1da177e4 LT |
3884 | rx_mode = AcceptBroadcast | AcceptMyPhys; |
3885 | mc_filter[1] = mc_filter[0] = 0; | |
3886 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
3887 | i++, mclist = mclist->next) { | |
3888 | int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; | |
3889 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
3890 | rx_mode |= AcceptMulticast; | |
3891 | } | |
3892 | } | |
3893 | ||
3894 | spin_lock_irqsave(&tp->lock, flags); | |
3895 | ||
3896 | tmp = rtl8169_rx_config | rx_mode | | |
3897 | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
3898 | ||
f887cce8 | 3899 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
1087f4f4 FR |
3900 | u32 data = mc_filter[0]; |
3901 | ||
3902 | mc_filter[0] = swab32(mc_filter[1]); | |
3903 | mc_filter[1] = swab32(data); | |
bcf0bf90 FR |
3904 | } |
3905 | ||
1da177e4 LT |
3906 | RTL_W32(MAR0 + 0, mc_filter[0]); |
3907 | RTL_W32(MAR0 + 4, mc_filter[1]); | |
3908 | ||
57a9f236 FR |
3909 | RTL_W32(RxConfig, tmp); |
3910 | ||
1da177e4 LT |
3911 | spin_unlock_irqrestore(&tp->lock, flags); |
3912 | } | |
3913 | ||
3914 | /** | |
3915 | * rtl8169_get_stats - Get rtl8169 read/write statistics | |
3916 | * @dev: The Ethernet Device to get statistics for | |
3917 | * | |
3918 | * Get TX/RX statistics for rtl8169 | |
3919 | */ | |
3920 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) | |
3921 | { | |
3922 | struct rtl8169_private *tp = netdev_priv(dev); | |
3923 | void __iomem *ioaddr = tp->mmio_addr; | |
3924 | unsigned long flags; | |
3925 | ||
3926 | if (netif_running(dev)) { | |
3927 | spin_lock_irqsave(&tp->lock, flags); | |
523a6094 | 3928 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
3929 | spin_unlock_irqrestore(&tp->lock, flags); |
3930 | } | |
5b0384f4 | 3931 | |
cebf8cc7 | 3932 | return &dev->stats; |
1da177e4 LT |
3933 | } |
3934 | ||
861ab440 | 3935 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 3936 | { |
5d06a99f | 3937 | if (!netif_running(dev)) |
861ab440 | 3938 | return; |
5d06a99f FR |
3939 | |
3940 | netif_device_detach(dev); | |
3941 | netif_stop_queue(dev); | |
861ab440 RW |
3942 | } |
3943 | ||
3944 | #ifdef CONFIG_PM | |
3945 | ||
3946 | static int rtl8169_suspend(struct device *device) | |
3947 | { | |
3948 | struct pci_dev *pdev = to_pci_dev(device); | |
3949 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 3950 | |
861ab440 | 3951 | rtl8169_net_suspend(dev); |
1371fa6d | 3952 | |
5d06a99f FR |
3953 | return 0; |
3954 | } | |
3955 | ||
861ab440 | 3956 | static int rtl8169_resume(struct device *device) |
5d06a99f | 3957 | { |
861ab440 | 3958 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f FR |
3959 | struct net_device *dev = pci_get_drvdata(pdev); |
3960 | ||
3961 | if (!netif_running(dev)) | |
3962 | goto out; | |
3963 | ||
3964 | netif_device_attach(dev); | |
3965 | ||
5d06a99f FR |
3966 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
3967 | out: | |
3968 | return 0; | |
3969 | } | |
3970 | ||
861ab440 RW |
3971 | static struct dev_pm_ops rtl8169_pm_ops = { |
3972 | .suspend = rtl8169_suspend, | |
3973 | .resume = rtl8169_resume, | |
3974 | .freeze = rtl8169_suspend, | |
3975 | .thaw = rtl8169_resume, | |
3976 | .poweroff = rtl8169_suspend, | |
3977 | .restore = rtl8169_resume, | |
3978 | }; | |
3979 | ||
3980 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
3981 | ||
3982 | #else /* !CONFIG_PM */ | |
3983 | ||
3984 | #define RTL8169_PM_OPS NULL | |
3985 | ||
3986 | #endif /* !CONFIG_PM */ | |
3987 | ||
1765f95d FR |
3988 | static void rtl_shutdown(struct pci_dev *pdev) |
3989 | { | |
861ab440 | 3990 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 3991 | struct rtl8169_private *tp = netdev_priv(dev); |
3992 | void __iomem *ioaddr = tp->mmio_addr; | |
861ab440 RW |
3993 | |
3994 | rtl8169_net_suspend(dev); | |
1765f95d | 3995 | |
4bb3f522 | 3996 | spin_lock_irq(&tp->lock); |
3997 | ||
3998 | rtl8169_asic_down(ioaddr); | |
3999 | ||
4000 | spin_unlock_irq(&tp->lock); | |
4001 | ||
861ab440 | 4002 | if (system_state == SYSTEM_POWER_OFF) { |
ca52efd5 | 4003 | /* WoL fails with some 8168 when the receiver is disabled. */ |
4004 | if (tp->features & RTL_FEATURE_WOL) { | |
4005 | pci_clear_master(pdev); | |
4006 | ||
4007 | RTL_W8(ChipCmd, CmdRxEnb); | |
4008 | /* PCI commit */ | |
4009 | RTL_R8(ChipCmd); | |
4010 | } | |
4011 | ||
861ab440 RW |
4012 | pci_wake_from_d3(pdev, true); |
4013 | pci_set_power_state(pdev, PCI_D3hot); | |
4014 | } | |
4015 | } | |
5d06a99f | 4016 | |
1da177e4 LT |
4017 | static struct pci_driver rtl8169_pci_driver = { |
4018 | .name = MODULENAME, | |
4019 | .id_table = rtl8169_pci_tbl, | |
4020 | .probe = rtl8169_init_one, | |
4021 | .remove = __devexit_p(rtl8169_remove_one), | |
1765f95d | 4022 | .shutdown = rtl_shutdown, |
861ab440 | 4023 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
4024 | }; |
4025 | ||
07d3f51f | 4026 | static int __init rtl8169_init_module(void) |
1da177e4 | 4027 | { |
29917620 | 4028 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
4029 | } |
4030 | ||
07d3f51f | 4031 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
4032 | { |
4033 | pci_unregister_driver(&rtl8169_pci_driver); | |
4034 | } | |
4035 | ||
4036 | module_init(rtl8169_init_module); | |
4037 | module_exit(rtl8169_cleanup_module); |