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r8169: remove useless struct member
[deliverable/linux.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
ea8dbdd1 84#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 86#define RTL_EEPROM_SIG_ADDR 0x0000
87
1da177e4
LT		 88/* write/read MMIO register */
89#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92#define RTL_R8(reg) readb (ioaddr + (reg))
93#define RTL_R16(reg) readw (ioaddr + (reg))
94#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
95
96enum mac_version {
ba6eb6ee
FR		 97 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
98 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
99 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
100 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
101 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 102 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 103 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
104 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
105 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
106 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 107 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 108 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
109 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
110 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
111 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
112 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
113 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
114 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
115 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 116 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 117 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 118 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 119 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9
FR		 120 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
121 RTL_GIGA_MAC_VER_25 = 0x19 // 8168D
1da177e4
LT		 122};
123
1da177e4
LT		 124#define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
126
3c6bee1d 127static const struct {
1da177e4
LT		 128 const char *name;
129 u8 mac_version;
130 u32 RxConfigMask; /* Clears the bits supported by this chip */
131} rtl_chip_info[] = {
ba6eb6ee
FR		 132 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 138 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 146 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9
FR		 155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E
1da177e4
LT		 157};
158#undef _R
159
bcf0bf90
FR		 160enum cfg_version {
161 RTL_CFG_0 = 0x00,
162 RTL_CFG_1,
163 RTL_CFG_2
164};
165
07ce4064
FR		 166static void rtl_hw_start_8169(struct net_device *);
167static void rtl_hw_start_8168(struct net_device *);
168static void rtl_hw_start_8101(struct net_device *);
169
1da177e4 170static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
176 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 177 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 178 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
179 { PCI_VENDOR_ID_LINKSYS, 0x1032,
180 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 181 { 0x0001, 0x8168,
182 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 183 {0,},
184};
185
186MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
187
188static int rx_copybreak = 200;
189static int use_dac;
b57b7e5a
SH		 190static struct {
191 u32 msg_enable;
192} debug = { -1 };
1da177e4 193
07d3f51f
FR		 194enum rtl_registers {
195 MAC0 = 0, /* Ethernet hardware address. */
773d2021 196 MAC4 = 4,
07d3f51f
FR		 197 MAR0 = 8, /* Multicast filter. */
198 CounterAddrLow = 0x10,
199 CounterAddrHigh = 0x14,
200 TxDescStartAddrLow = 0x20,
201 TxDescStartAddrHigh = 0x24,
202 TxHDescStartAddrLow = 0x28,
203 TxHDescStartAddrHigh = 0x2c,
204 FLASH = 0x30,
205 ERSR = 0x36,
206 ChipCmd = 0x37,
207 TxPoll = 0x38,
208 IntrMask = 0x3c,
209 IntrStatus = 0x3e,
210 TxConfig = 0x40,
211 RxConfig = 0x44,
212 RxMissed = 0x4c,
213 Cfg9346 = 0x50,
214 Config0 = 0x51,
215 Config1 = 0x52,
216 Config2 = 0x53,
217 Config3 = 0x54,
218 Config4 = 0x55,
219 Config5 = 0x56,
220 MultiIntr = 0x5c,
221 PHYAR = 0x60,
07d3f51f
FR		 222 PHYstatus = 0x6c,
223 RxMaxSize = 0xda,
224 CPlusCmd = 0xe0,
225 IntrMitigate = 0xe2,
226 RxDescAddrLow = 0xe4,
227 RxDescAddrHigh = 0xe8,
228 EarlyTxThres = 0xec,
229 FuncEvent = 0xf0,
230 FuncEventMask = 0xf4,
231 FuncPresetState = 0xf8,
232 FuncForceEvent = 0xfc,
1da177e4
LT		 233};
234
f162a5d1
FR		 235enum rtl8110_registers {
236 TBICSR = 0x64,
237 TBI_ANAR = 0x68,
238 TBI_LPAR = 0x6a,
239};
240
241enum rtl8168_8101_registers {
242 CSIDR = 0x64,
243 CSIAR = 0x68,
244#define CSIAR_FLAG 0x80000000
245#define CSIAR_WRITE_CMD 0x80000000
246#define CSIAR_BYTE_ENABLE 0x0f
247#define CSIAR_BYTE_ENABLE_SHIFT 12
248#define CSIAR_ADDR_MASK 0x0fff
249
250 EPHYAR = 0x80,
251#define EPHYAR_FLAG 0x80000000
252#define EPHYAR_WRITE_CMD 0x80000000
253#define EPHYAR_REG_MASK 0x1f
254#define EPHYAR_REG_SHIFT 16
255#define EPHYAR_DATA_MASK 0xffff
256 DBG_REG = 0xd1,
257#define FIX_NAK_1 (1 << 4)
258#define FIX_NAK_2 (1 << 3)
259};
260
07d3f51f 261enum rtl_register_content {
1da177e4 262 /* InterruptStatusBits */
07d3f51f
FR		 263 SYSErr = 0x8000,
264 PCSTimeout = 0x4000,
265 SWInt = 0x0100,
266 TxDescUnavail = 0x0080,
267 RxFIFOOver = 0x0040,
268 LinkChg = 0x0020,
269 RxOverflow = 0x0010,
270 TxErr = 0x0008,
271 TxOK = 0x0004,
272 RxErr = 0x0002,
273 RxOK = 0x0001,
1da177e4
LT		 274
275 /* RxStatusDesc */
9dccf611
FR		 276 RxFOVF = (1 << 23),
277 RxRWT = (1 << 22),
278 RxRES = (1 << 21),
279 RxRUNT = (1 << 20),
280 RxCRC = (1 << 19),
1da177e4
LT		 281
282 /* ChipCmdBits */
07d3f51f
FR		 283 CmdReset = 0x10,
284 CmdRxEnb = 0x08,
285 CmdTxEnb = 0x04,
286 RxBufEmpty = 0x01,
1da177e4 287
275391a4
FR		 288 /* TXPoll register p.5 */
289 HPQ = 0x80, /* Poll cmd on the high prio queue */
290 NPQ = 0x40, /* Poll cmd on the low prio queue */
291 FSWInt = 0x01, /* Forced software interrupt */
292
1da177e4 293 /* Cfg9346Bits */
07d3f51f
FR		 294 Cfg9346_Lock = 0x00,
295 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 296
297 /* rx_mode_bits */
07d3f51f
FR		 298 AcceptErr = 0x20,
299 AcceptRunt = 0x10,
300 AcceptBroadcast = 0x08,
301 AcceptMulticast = 0x04,
302 AcceptMyPhys = 0x02,
303 AcceptAllPhys = 0x01,
1da177e4
LT		 304
305 /* RxConfigBits */
07d3f51f
FR		 306 RxCfgFIFOShift = 13,
307 RxCfgDMAShift = 8,
1da177e4
LT		 308
309 /* TxConfigBits */
310 TxInterFrameGapShift = 24,
311 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
312
5d06a99f 313 /* Config1 register p.24 */
f162a5d1
FR		 314 LEDS1 = (1 << 7),
315 LEDS0 = (1 << 6),
fbac58fc 316 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 317 Speed_down = (1 << 4),
318 MEMMAP = (1 << 3),
319 IOMAP = (1 << 2),
320 VPD = (1 << 1),
5d06a99f
FR		 321 PMEnable = (1 << 0), /* Power Management Enable */
322
6dccd16b
FR		 323 /* Config2 register p. 25 */
324 PCI_Clock_66MHz = 0x01,
325 PCI_Clock_33MHz = 0x00,
326
61a4dcc2
FR		 327 /* Config3 register p.25 */
328 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
329 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 330 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 331
5d06a99f 332 /* Config5 register p.27 */
61a4dcc2
FR		 333 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
334 MWF = (1 << 5), /* Accept Multicast wakeup frame */
335 UWF = (1 << 4), /* Accept Unicast wakeup frame */
336 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 337 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
338
1da177e4
LT		 339 /* TBICSR p.28 */
340 TBIReset = 0x80000000,
341 TBILoopback = 0x40000000,
342 TBINwEnable = 0x20000000,
343 TBINwRestart = 0x10000000,
344 TBILinkOk = 0x02000000,
345 TBINwComplete = 0x01000000,
346
347 /* CPlusCmd p.31 */
f162a5d1
FR		 348 EnableBist = (1 << 15), // 8168 8101
349 Mac_dbgo_oe = (1 << 14), // 8168 8101
350 Normal_mode = (1 << 13), // unused
351 Force_half_dup = (1 << 12), // 8168 8101
352 Force_rxflow_en = (1 << 11), // 8168 8101
353 Force_txflow_en = (1 << 10), // 8168 8101
354 Cxpl_dbg_sel = (1 << 9), // 8168 8101
355 ASF = (1 << 8), // 8168 8101
356 PktCntrDisable = (1 << 7), // 8168 8101
357 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 358 RxVlan = (1 << 6),
359 RxChkSum = (1 << 5),
360 PCIDAC = (1 << 4),
361 PCIMulRW = (1 << 3),
0e485150
FR		 362 INTT_0 = 0x0000, // 8168
363 INTT_1 = 0x0001, // 8168
364 INTT_2 = 0x0002, // 8168
365 INTT_3 = 0x0003, // 8168
1da177e4
LT		 366
367 /* rtl8169_PHYstatus */
07d3f51f
FR		 368 TBI_Enable = 0x80,
369 TxFlowCtrl = 0x40,
370 RxFlowCtrl = 0x20,
371 _1000bpsF = 0x10,
372 _100bps = 0x08,
373 _10bps = 0x04,
374 LinkStatus = 0x02,
375 FullDup = 0x01,
1da177e4 376
1da177e4 377 /* _TBICSRBit */
07d3f51f 378 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 379
380 /* DumpCounterCommand */
07d3f51f 381 CounterDump = 0x8,
1da177e4
LT		 382};
383
07d3f51f 384enum desc_status_bit {
1da177e4
LT		 385 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
386 RingEnd = (1 << 30), /* End of descriptor ring */
387 FirstFrag = (1 << 29), /* First segment of a packet */
388 LastFrag = (1 << 28), /* Final segment of a packet */
389
390 /* Tx private */
391 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
392 MSSShift = 16, /* MSS value position */
393 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
394 IPCS = (1 << 18), /* Calculate IP checksum */
395 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
396 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
397 TxVlanTag = (1 << 17), /* Add VLAN tag */
398
399 /* Rx private */
400 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
401 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
402
403#define RxProtoUDP (PID1)
404#define RxProtoTCP (PID0)
405#define RxProtoIP (PID1 | PID0)
406#define RxProtoMask RxProtoIP
407
408 IPFail = (1 << 16), /* IP checksum failed */
409 UDPFail = (1 << 15), /* UDP/IP checksum failed */
410 TCPFail = (1 << 14), /* TCP/IP checksum failed */
411 RxVlanTag = (1 << 16), /* VLAN tag available */
412};
413
414#define RsvdMask 0x3fffc000
415
416struct TxDesc {
6cccd6e7
REB		 417 __le32 opts1;
418 __le32 opts2;
419 __le64 addr;
1da177e4
LT		 420};
421
422struct RxDesc {
6cccd6e7
REB		 423 __le32 opts1;
424 __le32 opts2;
425 __le64 addr;
1da177e4
LT		 426};
427
428struct ring_info {
429 struct sk_buff *skb;
430 u32 len;
431 u8 __pad[sizeof(void *) - sizeof(u32)];
432};
433
f23e7fda 434enum features {
ccdffb9a
FR		 435 RTL_FEATURE_WOL = (1 << 0),
436 RTL_FEATURE_MSI = (1 << 1),
437 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 438};
439
355423d0
IV		 440struct rtl8169_counters {
441 __le64 tx_packets;
442 __le64 rx_packets;
443 __le64 tx_errors;
444 __le32 rx_errors;
445 __le16 rx_missed;
446 __le16 align_errors;
447 __le32 tx_one_collision;
448 __le32 tx_multi_collision;
449 __le64 rx_unicast;
450 __le64 rx_broadcast;
451 __le32 rx_multicast;
452 __le16 tx_aborted;
453 __le16 tx_underun;
454};
455
1da177e4
LT		 456struct rtl8169_private {
457 void __iomem *mmio_addr; /* memory map physical address */
458 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 459 struct net_device *dev;
bea3348e 460 struct napi_struct napi;
1da177e4 461 spinlock_t lock; /* spin lock flag */
b57b7e5a 462 u32 msg_enable;
1da177e4
LT		 463 int chipset;
464 int mac_version;
1da177e4
LT		 465 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
466 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
467 u32 dirty_rx;
468 u32 dirty_tx;
469 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
470 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
471 dma_addr_t TxPhyAddr;
472 dma_addr_t RxPhyAddr;
473 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
474 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 475 unsigned align;
1da177e4
LT		 476 unsigned rx_buf_sz;
477 struct timer_list timer;
478 u16 cp_cmd;
0e485150
FR		 479 u16 intr_event;
480 u16 napi_event;
1da177e4 481 u16 intr_mask;
1da177e4
LT		 482 int phy_1000_ctrl_reg;
483#ifdef CONFIG_R8169_VLAN
484 struct vlan_group *vlgrp;
485#endif
486 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 487 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 488 void (*phy_reset_enable)(void __iomem *);
07ce4064 489 void (*hw_start)(struct net_device *);
1da177e4
LT		 490 unsigned int (*phy_reset_pending)(void __iomem *);
491 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 492 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 493 int pcie_cap;
c4028958 494 struct delayed_work task;
f23e7fda 495 unsigned features;
ccdffb9a
FR		 496
497 struct mii_if_info mii;
355423d0 498 struct rtl8169_counters counters;
1da177e4
LT		 499};
500
979b6c13 501MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 502MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 503module_param(rx_copybreak, int, 0);
1b7efd58 504MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 505module_param(use_dac, int, 0);
506MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 507module_param_named(debug, debug.msg_enable, int, 0);
508MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 509MODULE_LICENSE("GPL");
510MODULE_VERSION(RTL8169_VERSION);
511
512static int rtl8169_open(struct net_device *dev);
513static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 514static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 515static int rtl8169_init_ring(struct net_device *dev);
07ce4064 516static void rtl_hw_start(struct net_device *dev);
1da177e4 517static int rtl8169_close(struct net_device *dev);
07ce4064 518static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 519static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 520static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 521static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 522 void __iomem *, u32 budget);
4dcb7d33 523static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 524static void rtl8169_down(struct net_device *dev);
99f252b0 525static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 526static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 527
1da177e4 528static const unsigned int rtl8169_rx_config =
5b0384f4 529 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 530
07d3f51f 531static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 532{
533 int i;
534
a6baf3af 535 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 536
2371408c 537 for (i = 20; i > 0; i--) {
07d3f51f
FR		 538 /*
539 * Check if the RTL8169 has completed writing to the specified
540 * MII register.
541 */
5b0384f4 542 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 543 break;
2371408c 544 udelay(25);
1da177e4
LT		 545 }
546}
547
07d3f51f 548static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 549{
550 int i, value = -1;
551
a6baf3af 552 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 553
2371408c 554 for (i = 20; i > 0; i--) {
07d3f51f
FR		 555 /*
556 * Check if the RTL8169 has completed retrieving data from
557 * the specified MII register.
558 */
1da177e4 559 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 560 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 561 break;
562 }
2371408c 563 udelay(25);
1da177e4
LT		 564 }
565 return value;
566}
567
dacf8154
FR		 568static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
569{
570 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
571}
572
ccdffb9a
FR		 573static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
574 int val)
575{
576 struct rtl8169_private *tp = netdev_priv(dev);
577 void __iomem *ioaddr = tp->mmio_addr;
578
579 mdio_write(ioaddr, location, val);
580}
581
582static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
583{
584 struct rtl8169_private *tp = netdev_priv(dev);
585 void __iomem *ioaddr = tp->mmio_addr;
586
587 return mdio_read(ioaddr, location);
588}
589
dacf8154
FR		 590static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
591{
592 unsigned int i;
593
594 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
595 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
596
597 for (i = 0; i < 100; i++) {
598 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
599 break;
600 udelay(10);
601 }
602}
603
604static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
605{
606 u16 value = 0xffff;
607 unsigned int i;
608
609 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
610
611 for (i = 0; i < 100; i++) {
612 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
613 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
614 break;
615 }
616 udelay(10);
617 }
618
619 return value;
620}
621
622static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
623{
624 unsigned int i;
625
626 RTL_W32(CSIDR, value);
627 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
628 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
629
630 for (i = 0; i < 100; i++) {
631 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
632 break;
633 udelay(10);
634 }
635}
636
637static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
638{
639 u32 value = ~0x00;
640 unsigned int i;
641
642 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
643 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
644
645 for (i = 0; i < 100; i++) {
646 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
647 value = RTL_R32(CSIDR);
648 break;
649 }
650 udelay(10);
651 }
652
653 return value;
654}
655
1da177e4
LT		 656static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
657{
658 RTL_W16(IntrMask, 0x0000);
659
660 RTL_W16(IntrStatus, 0xffff);
661}
662
663static void rtl8169_asic_down(void __iomem *ioaddr)
664{
665 RTL_W8(ChipCmd, 0x00);
666 rtl8169_irq_mask_and_ack(ioaddr);
667 RTL_R16(CPlusCmd);
668}
669
670static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
671{
672 return RTL_R32(TBICSR) & TBIReset;
673}
674
675static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
676{
64e4bfb4 677 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 678}
679
680static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
681{
682 return RTL_R32(TBICSR) & TBILinkOk;
683}
684
685static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
686{
687 return RTL_R8(PHYstatus) & LinkStatus;
688}
689
690static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
691{
692 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
693}
694
695static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
696{
697 unsigned int val;
698
9e0db8ef
FR		 699 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
700 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 701}
702
703static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 704 struct rtl8169_private *tp,
705 void __iomem *ioaddr)
1da177e4
LT		 706{
707 unsigned long flags;
708
709 spin_lock_irqsave(&tp->lock, flags);
710 if (tp->link_ok(ioaddr)) {
711 netif_carrier_on(dev);
b57b7e5a
SH		 712 if (netif_msg_ifup(tp))
713 printk(KERN_INFO PFX "%s: link up\n", dev->name);
714 } else {
715 if (netif_msg_ifdown(tp))
716 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 717 netif_carrier_off(dev);
b57b7e5a 718 }
1da177e4
LT		 719 spin_unlock_irqrestore(&tp->lock, flags);
720}
721
61a4dcc2
FR		 722static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
723{
724 struct rtl8169_private *tp = netdev_priv(dev);
725 void __iomem *ioaddr = tp->mmio_addr;
726 u8 options;
727
728 wol->wolopts = 0;
729
730#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
731 wol->supported = WAKE_ANY;
732
733 spin_lock_irq(&tp->lock);
734
735 options = RTL_R8(Config1);
736 if (!(options & PMEnable))
737 goto out_unlock;
738
739 options = RTL_R8(Config3);
740 if (options & LinkUp)
741 wol->wolopts |= WAKE_PHY;
742 if (options & MagicPacket)
743 wol->wolopts |= WAKE_MAGIC;
744
745 options = RTL_R8(Config5);
746 if (options & UWF)
747 wol->wolopts |= WAKE_UCAST;
748 if (options & BWF)
5b0384f4 749 wol->wolopts |= WAKE_BCAST;
61a4dcc2 750 if (options & MWF)
5b0384f4 751 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 752
753out_unlock:
754 spin_unlock_irq(&tp->lock);
755}
756
757static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
758{
759 struct rtl8169_private *tp = netdev_priv(dev);
760 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 761 unsigned int i;
61a4dcc2
FR		 762 static struct {
763 u32 opt;
764 u16 reg;
765 u8 mask;
766 } cfg[] = {
767 { WAKE_ANY, Config1, PMEnable },
768 { WAKE_PHY, Config3, LinkUp },
769 { WAKE_MAGIC, Config3, MagicPacket },
770 { WAKE_UCAST, Config5, UWF },
771 { WAKE_BCAST, Config5, BWF },
772 { WAKE_MCAST, Config5, MWF },
773 { WAKE_ANY, Config5, LanWake }
774 };
775
776 spin_lock_irq(&tp->lock);
777
778 RTL_W8(Cfg9346, Cfg9346_Unlock);
779
780 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
781 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
782 if (wol->wolopts & cfg[i].opt)
783 options |= cfg[i].mask;
784 RTL_W8(cfg[i].reg, options);
785 }
786
787 RTL_W8(Cfg9346, Cfg9346_Lock);
788
f23e7fda
FR		 789 if (wol->wolopts)
790 tp->features |= RTL_FEATURE_WOL;
791 else
792 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 793 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 794
795 spin_unlock_irq(&tp->lock);
796
797 return 0;
798}
799
1da177e4
LT		 800static void rtl8169_get_drvinfo(struct net_device *dev,
801 struct ethtool_drvinfo *info)
802{
803 struct rtl8169_private *tp = netdev_priv(dev);
804
805 strcpy(info->driver, MODULENAME);
806 strcpy(info->version, RTL8169_VERSION);
807 strcpy(info->bus_info, pci_name(tp->pci_dev));
808}
809
810static int rtl8169_get_regs_len(struct net_device *dev)
811{
812 return R8169_REGS_SIZE;
813}
814
815static int rtl8169_set_speed_tbi(struct net_device *dev,
816 u8 autoneg, u16 speed, u8 duplex)
817{
818 struct rtl8169_private *tp = netdev_priv(dev);
819 void __iomem *ioaddr = tp->mmio_addr;
820 int ret = 0;
821 u32 reg;
822
823 reg = RTL_R32(TBICSR);
824 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
825 (duplex == DUPLEX_FULL)) {
826 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
827 } else if (autoneg == AUTONEG_ENABLE)
828 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
829 else {
b57b7e5a
SH		 830 if (netif_msg_link(tp)) {
831 printk(KERN_WARNING "%s: "
832 "incorrect speed setting refused in TBI mode\n",
833 dev->name);
834 }
1da177e4
LT		 835 ret = -EOPNOTSUPP;
836 }
837
838 return ret;
839}
840
841static int rtl8169_set_speed_xmii(struct net_device *dev,
842 u8 autoneg, u16 speed, u8 duplex)
843{
844 struct rtl8169_private *tp = netdev_priv(dev);
845 void __iomem *ioaddr = tp->mmio_addr;
846 int auto_nego, giga_ctrl;
847
64e4bfb4
FR		 848 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
849 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
850 ADVERTISE_100HALF | ADVERTISE_100FULL);
851 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
852 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 853
854 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 855 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
856 ADVERTISE_100HALF | ADVERTISE_100FULL);
857 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 858 } else {
859 if (speed == SPEED_10)
64e4bfb4 860 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 861 else if (speed == SPEED_100)
64e4bfb4 862 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 863 else if (speed == SPEED_1000)
64e4bfb4 864 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 865
866 if (duplex == DUPLEX_HALF)
64e4bfb4 867 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 868
869 if (duplex == DUPLEX_FULL)
64e4bfb4 870 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 871
872 /* This tweak comes straight from Realtek's driver. */
873 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 874 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
875 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 876 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 877 }
878 }
879
2857ffb7
FR		 880 /* The 8100e/8101e/8102e do Fast Ethernet only. */
881 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
882 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
883 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
884 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
885 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
bcf0bf90 886 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 887 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
888 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 889 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 890 netif_msg_link(tp)) {
891 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
892 dev->name);
893 }
64e4bfb4 894 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 895 }
896
623a1593
FR		 897 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
898
a2de6b89
FR		 899 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
900 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
901 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
902 /*
903 * Wake up the PHY.
904 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
905 */
2584fbc3
RS		 906 mdio_write(ioaddr, 0x1f, 0x0000);
907 mdio_write(ioaddr, 0x0e, 0x0000);
908 }
909
1da177e4
LT		 910 tp->phy_1000_ctrl_reg = giga_ctrl;
911
64e4bfb4
FR		 912 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
913 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
914 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 915 return 0;
916}
917
918static int rtl8169_set_speed(struct net_device *dev,
919 u8 autoneg, u16 speed, u8 duplex)
920{
921 struct rtl8169_private *tp = netdev_priv(dev);
922 int ret;
923
924 ret = tp->set_speed(dev, autoneg, speed, duplex);
925
64e4bfb4 926 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 927 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
928
929 return ret;
930}
931
932static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
933{
934 struct rtl8169_private *tp = netdev_priv(dev);
935 unsigned long flags;
936 int ret;
937
938 spin_lock_irqsave(&tp->lock, flags);
939 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
940 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 941
1da177e4
LT		 942 return ret;
943}
944
945static u32 rtl8169_get_rx_csum(struct net_device *dev)
946{
947 struct rtl8169_private *tp = netdev_priv(dev);
948
949 return tp->cp_cmd & RxChkSum;
950}
951
952static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
953{
954 struct rtl8169_private *tp = netdev_priv(dev);
955 void __iomem *ioaddr = tp->mmio_addr;
956 unsigned long flags;
957
958 spin_lock_irqsave(&tp->lock, flags);
959
960 if (data)
961 tp->cp_cmd |= RxChkSum;
962 else
963 tp->cp_cmd &= ~RxChkSum;
964
965 RTL_W16(CPlusCmd, tp->cp_cmd);
966 RTL_R16(CPlusCmd);
967
968 spin_unlock_irqrestore(&tp->lock, flags);
969
970 return 0;
971}
972
973#ifdef CONFIG_R8169_VLAN
974
975static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
976 struct sk_buff *skb)
977{
978 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
979 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
980}
981
982static void rtl8169_vlan_rx_register(struct net_device *dev,
983 struct vlan_group *grp)
984{
985 struct rtl8169_private *tp = netdev_priv(dev);
986 void __iomem *ioaddr = tp->mmio_addr;
987 unsigned long flags;
988
989 spin_lock_irqsave(&tp->lock, flags);
990 tp->vlgrp = grp;
991 if (tp->vlgrp)
992 tp->cp_cmd |= RxVlan;
993 else
994 tp->cp_cmd &= ~RxVlan;
995 RTL_W16(CPlusCmd, tp->cp_cmd);
996 RTL_R16(CPlusCmd);
997 spin_unlock_irqrestore(&tp->lock, flags);
998}
999
1da177e4
LT		 1000static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1001 struct sk_buff *skb)
1002{
1003 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1004 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1005 int ret;
1006
865c652d
FR		 1007 if (vlgrp && (opts2 & RxVlanTag)) {
1008 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 1009 ret = 0;
1010 } else
1011 ret = -1;
1012 desc->opts2 = 0;
1013 return ret;
1014}
1015
1016#else /* !CONFIG_R8169_VLAN */
1017
1018static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1019 struct sk_buff *skb)
1020{
1021 return 0;
1022}
1023
1024static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1025 struct sk_buff *skb)
1026{
1027 return -1;
1028}
1029
1030#endif
1031
ccdffb9a 1032static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1033{
1034 struct rtl8169_private *tp = netdev_priv(dev);
1035 void __iomem *ioaddr = tp->mmio_addr;
1036 u32 status;
1037
1038 cmd->supported =
1039 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1040 cmd->port = PORT_FIBRE;
1041 cmd->transceiver = XCVR_INTERNAL;
1042
1043 status = RTL_R32(TBICSR);
1044 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1045 cmd->autoneg = !!(status & TBINwEnable);
1046
1047 cmd->speed = SPEED_1000;
1048 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1049
1050 return 0;
1da177e4
LT		 1051}
1052
ccdffb9a 1053static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1054{
1055 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1056
1057 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1058}
1059
1060static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1061{
1062 struct rtl8169_private *tp = netdev_priv(dev);
1063 unsigned long flags;
ccdffb9a 1064 int rc;
1da177e4
LT		 1065
1066 spin_lock_irqsave(&tp->lock, flags);
1067
ccdffb9a 1068 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1069
1070 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1071 return rc;
1da177e4
LT		 1072}
1073
1074static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1075 void *p)
1076{
5b0384f4
FR		 1077 struct rtl8169_private *tp = netdev_priv(dev);
1078 unsigned long flags;
1da177e4 1079
5b0384f4
FR		 1080 if (regs->len > R8169_REGS_SIZE)
1081 regs->len = R8169_REGS_SIZE;
1da177e4 1082
5b0384f4
FR		 1083 spin_lock_irqsave(&tp->lock, flags);
1084 memcpy_fromio(p, tp->mmio_addr, regs->len);
1085 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1086}
1087
b57b7e5a
SH		 1088static u32 rtl8169_get_msglevel(struct net_device *dev)
1089{
1090 struct rtl8169_private *tp = netdev_priv(dev);
1091
1092 return tp->msg_enable;
1093}
1094
1095static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1096{
1097 struct rtl8169_private *tp = netdev_priv(dev);
1098
1099 tp->msg_enable = value;
1100}
1101
d4a3a0fc
SH		 1102static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1103 "tx_packets",
1104 "rx_packets",
1105 "tx_errors",
1106 "rx_errors",
1107 "rx_missed",
1108 "align_errors",
1109 "tx_single_collisions",
1110 "tx_multi_collisions",
1111 "unicast",
1112 "broadcast",
1113 "multicast",
1114 "tx_aborted",
1115 "tx_underrun",
1116};
1117
b9f2c044 1118static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1119{
b9f2c044
JG		 1120 switch (sset) {
1121 case ETH_SS_STATS:
1122 return ARRAY_SIZE(rtl8169_gstrings);
1123 default:
1124 return -EOPNOTSUPP;
1125 }
d4a3a0fc
SH		 1126}
1127
355423d0 1128static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1129{
1130 struct rtl8169_private *tp = netdev_priv(dev);
1131 void __iomem *ioaddr = tp->mmio_addr;
1132 struct rtl8169_counters *counters;
1133 dma_addr_t paddr;
1134 u32 cmd;
355423d0 1135 int wait = 1000;
d4a3a0fc 1136
355423d0
IV		 1137 /*
1138 * Some chips are unable to dump tally counters when the receiver
1139 * is disabled.
1140 */
1141 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1142 return;
d4a3a0fc
SH		 1143
1144 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1145 if (!counters)
1146 return;
1147
1148 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1149 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1150 RTL_W32(CounterAddrLow, cmd);
1151 RTL_W32(CounterAddrLow, cmd | CounterDump);
1152
355423d0
IV		 1153 while (wait--) {
1154 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1155 /* copy updated counters */
1156 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1157 break;
355423d0
IV		 1158 }
1159 udelay(10);
d4a3a0fc
SH		 1160 }
1161
1162 RTL_W32(CounterAddrLow, 0);
1163 RTL_W32(CounterAddrHigh, 0);
1164
d4a3a0fc
SH		 1165 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1166}
1167
355423d0
IV		 1168static void rtl8169_get_ethtool_stats(struct net_device *dev,
1169 struct ethtool_stats *stats, u64 *data)
1170{
1171 struct rtl8169_private *tp = netdev_priv(dev);
1172
1173 ASSERT_RTNL();
1174
1175 rtl8169_update_counters(dev);
1176
1177 data[0] = le64_to_cpu(tp->counters.tx_packets);
1178 data[1] = le64_to_cpu(tp->counters.rx_packets);
1179 data[2] = le64_to_cpu(tp->counters.tx_errors);
1180 data[3] = le32_to_cpu(tp->counters.rx_errors);
1181 data[4] = le16_to_cpu(tp->counters.rx_missed);
1182 data[5] = le16_to_cpu(tp->counters.align_errors);
1183 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1184 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1185 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1186 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1187 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1188 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1189 data[12] = le16_to_cpu(tp->counters.tx_underun);
1190}
1191
d4a3a0fc
SH		 1192static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1193{
1194 switch(stringset) {
1195 case ETH_SS_STATS:
1196 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1197 break;
1198 }
1199}
1200
7282d491 1201static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1202 .get_drvinfo = rtl8169_get_drvinfo,
1203 .get_regs_len = rtl8169_get_regs_len,
1204 .get_link = ethtool_op_get_link,
1205 .get_settings = rtl8169_get_settings,
1206 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1207 .get_msglevel = rtl8169_get_msglevel,
1208 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1209 .get_rx_csum = rtl8169_get_rx_csum,
1210 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1211 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1212 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1213 .set_tso = ethtool_op_set_tso,
1214 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1215 .get_wol = rtl8169_get_wol,
1216 .set_wol = rtl8169_set_wol,
d4a3a0fc 1217 .get_strings = rtl8169_get_strings,
b9f2c044 1218 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1219 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1220};
1221
07d3f51f
FR		 1222static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1223 int bitnum, int bitval)
1da177e4
LT		 1224{
1225 int val;
1226
1227 val = mdio_read(ioaddr, reg);
1228 val = (bitval == 1) ?
1229 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1230 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1231}
1232
07d3f51f
FR		 1233static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1234 void __iomem *ioaddr)
1da177e4 1235{
0e485150
FR		 1236 /*
1237 * The driver currently handles the 8168Bf and the 8168Be identically
1238 * but they can be identified more specifically through the test below
1239 * if needed:
1240 *
1241 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1242 *
1243 * Same thing for the 8101Eb and the 8101Ec:
1244 *
1245 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1246 */
1da177e4
LT		 1247 const struct {
1248 u32 mask;
e3cf0cc0 1249 u32 val;
1da177e4
LT		 1250 int mac_version;
1251 } mac_info[] = {
5b538df9
FR		 1252 /* 8168D family. */
1253 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 },
1254
ef808d50 1255 /* 8168C family. */
7f3e3d3a 1256 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1257 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1258 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1259 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1260 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1261 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1262 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1263 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1264 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1265
1266 /* 8168B family. */
1267 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1268 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1269 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1270 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1271
1272 /* 8101 family. */
2857ffb7
FR		 1273 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1274 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1275 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1276 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1277 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1278 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1279 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1280 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1281 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1282 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1283 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1284 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1285 /* FIXME: where did these entries come from ? -- FR */
1286 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1287 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1288
1289 /* 8110 family. */
1290 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1291 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1292 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1293 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1294 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1295 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1296
1297 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1298 }, *p = mac_info;
1299 u32 reg;
1300
e3cf0cc0
FR		 1301 reg = RTL_R32(TxConfig);
1302 while ((reg & p->mask) != p->val)
1da177e4
LT		 1303 p++;
1304 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1305
1306 if (p->mask == 0x00000000) {
1307 struct pci_dev *pdev = tp->pci_dev;
1308
1309 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1310 }
1da177e4
LT		 1311}
1312
1313static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1314{
bcf0bf90 1315 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1316}
1317
867763c1
FR		 1318struct phy_reg {
1319 u16 reg;
1320 u16 val;
1321};
1322
1323static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1324{
1325 while (len-- > 0) {
1326 mdio_write(ioaddr, regs->reg, regs->val);
1327 regs++;
1328 }
1329}
1330
5615d9f1 1331static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1332{
1da177e4
LT		 1333 struct {
1334 u16 regs[5]; /* Beware of bit-sign propagation */
1335 } phy_magic[5] = { {
1336 { 0x0000, //w 4 15 12 0
1337 0x00a1, //w 3 15 0 00a1
1338 0x0008, //w 2 15 0 0008
1339 0x1020, //w 1 15 0 1020
1340 0x1000 } },{ //w 0 15 0 1000
1341 { 0x7000, //w 4 15 12 7
1342 0xff41, //w 3 15 0 ff41
1343 0xde60, //w 2 15 0 de60
1344 0x0140, //w 1 15 0 0140
1345 0x0077 } },{ //w 0 15 0 0077
1346 { 0xa000, //w 4 15 12 a
1347 0xdf01, //w 3 15 0 df01
1348 0xdf20, //w 2 15 0 df20
1349 0xff95, //w 1 15 0 ff95
1350 0xfa00 } },{ //w 0 15 0 fa00
1351 { 0xb000, //w 4 15 12 b
1352 0xff41, //w 3 15 0 ff41
1353 0xde20, //w 2 15 0 de20
1354 0x0140, //w 1 15 0 0140
1355 0x00bb } },{ //w 0 15 0 00bb
1356 { 0xf000, //w 4 15 12 f
1357 0xdf01, //w 3 15 0 df01
1358 0xdf20, //w 2 15 0 df20
1359 0xff95, //w 1 15 0 ff95
1360 0xbf00 } //w 0 15 0 bf00
1361 }
1362 }, *p = phy_magic;
07d3f51f 1363 unsigned int i;
1da177e4 1364
a441d7b6
FR		 1365 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1366 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1367 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1368 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1369
1370 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1371 int val, pos = 4;
1372
1373 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1374 mdio_write(ioaddr, pos, val);
1375 while (--pos >= 0)
1376 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1377 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1378 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1379 }
a441d7b6 1380 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1381}
1382
5615d9f1
FR		 1383static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1384{
a441d7b6
FR		 1385 struct phy_reg phy_reg_init[] = {
1386 { 0x1f, 0x0002 },
1387 { 0x01, 0x90d0 },
1388 { 0x1f, 0x0000 }
1389 };
1390
1391 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1392}
1393
236b8082
FR		 1394static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1395{
1396 struct phy_reg phy_reg_init[] = {
1397 { 0x10, 0xf41b },
1398 { 0x1f, 0x0000 }
1399 };
1400
1401 mdio_write(ioaddr, 0x1f, 0x0001);
1402 mdio_patch(ioaddr, 0x16, 1 << 0);
1403
1404 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1405}
1406
1407static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1408{
1409 struct phy_reg phy_reg_init[] = {
1410 { 0x1f, 0x0001 },
1411 { 0x10, 0xf41b },
1412 { 0x1f, 0x0000 }
1413 };
1414
1415 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1416}
1417
ef3386f0 1418static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1419{
1420 struct phy_reg phy_reg_init[] = {
1421 { 0x1f, 0x0000 },
1422 { 0x1d, 0x0f00 },
1423 { 0x1f, 0x0002 },
1424 { 0x0c, 0x1ec8 },
1425 { 0x1f, 0x0000 }
1426 };
1427
1428 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1429}
1430
ef3386f0
FR		 1431static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1432{
1433 struct phy_reg phy_reg_init[] = {
1434 { 0x1f, 0x0001 },
1435 { 0x1d, 0x3d98 },
1436 { 0x1f, 0x0000 }
1437 };
1438
1439 mdio_write(ioaddr, 0x1f, 0x0000);
1440 mdio_patch(ioaddr, 0x14, 1 << 5);
1441 mdio_patch(ioaddr, 0x0d, 1 << 5);
1442
1443 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1444}
1445
219a1e9d 1446static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
867763c1
FR		 1447{
1448 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1449 { 0x1f, 0x0001 },
1450 { 0x12, 0x2300 },
867763c1
FR		 1451 { 0x1f, 0x0002 },
1452 { 0x00, 0x88d4 },
1453 { 0x01, 0x82b1 },
1454 { 0x03, 0x7002 },
1455 { 0x08, 0x9e30 },
1456 { 0x09, 0x01f0 },
1457 { 0x0a, 0x5500 },
1458 { 0x0c, 0x00c8 },
1459 { 0x1f, 0x0003 },
1460 { 0x12, 0xc096 },
1461 { 0x16, 0x000a },
f50d4275
FR		 1462 { 0x1f, 0x0000 },
1463 { 0x1f, 0x0000 },
1464 { 0x09, 0x2000 },
1465 { 0x09, 0x0000 }
867763c1
FR		 1466 };
1467
1468 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1469
1470 mdio_patch(ioaddr, 0x14, 1 << 5);
1471 mdio_patch(ioaddr, 0x0d, 1 << 5);
1472 mdio_write(ioaddr, 0x1f, 0x0000);
867763c1
FR		 1473}
1474
219a1e9d 1475static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
7da97ec9
FR		 1476{
1477 struct phy_reg phy_reg_init[] = {
f50d4275 1478 { 0x1f, 0x0001 },
7da97ec9 1479 { 0x12, 0x2300 },
f50d4275
FR		 1480 { 0x03, 0x802f },
1481 { 0x02, 0x4f02 },
1482 { 0x01, 0x0409 },
1483 { 0x00, 0xf099 },
1484 { 0x04, 0x9800 },
1485 { 0x04, 0x9000 },
1486 { 0x1d, 0x3d98 },
7da97ec9
FR		 1487 { 0x1f, 0x0002 },
1488 { 0x0c, 0x7eb8 },
f50d4275
FR		 1489 { 0x06, 0x0761 },
1490 { 0x1f, 0x0003 },
1491 { 0x16, 0x0f0a },
7da97ec9
FR		 1492 { 0x1f, 0x0000 }
1493 };
1494
1495 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275
FR		 1496
1497 mdio_patch(ioaddr, 0x16, 1 << 0);
1498 mdio_patch(ioaddr, 0x14, 1 << 5);
1499 mdio_patch(ioaddr, 0x0d, 1 << 5);
1500 mdio_write(ioaddr, 0x1f, 0x0000);
7da97ec9
FR		 1501}
1502
197ff761
FR		 1503static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1504{
1505 struct phy_reg phy_reg_init[] = {
1506 { 0x1f, 0x0001 },
1507 { 0x12, 0x2300 },
1508 { 0x1d, 0x3d98 },
1509 { 0x1f, 0x0002 },
1510 { 0x0c, 0x7eb8 },
1511 { 0x06, 0x5461 },
1512 { 0x1f, 0x0003 },
1513 { 0x16, 0x0f0a },
1514 { 0x1f, 0x0000 }
1515 };
1516
1517 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1518
1519 mdio_patch(ioaddr, 0x16, 1 << 0);
1520 mdio_patch(ioaddr, 0x14, 1 << 5);
1521 mdio_patch(ioaddr, 0x0d, 1 << 5);
1522 mdio_write(ioaddr, 0x1f, 0x0000);
1523}
1524
6fb07058
FR		 1525static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1526{
1527 rtl8168c_3_hw_phy_config(ioaddr);
1528}
1529
5b538df9
FR		 1530static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1531{
1532 struct phy_reg phy_reg_init_0[] = {
1533 { 0x1f, 0x0001 },
1534 { 0x09, 0x2770 },
1535 { 0x08, 0x04d0 },
1536 { 0x0b, 0xad15 },
1537 { 0x0c, 0x5bf0 },
1538 { 0x1c, 0xf101 },
1539 { 0x1f, 0x0003 },
1540 { 0x14, 0x94d7 },
1541 { 0x12, 0xf4d6 },
1542 { 0x09, 0xca0f },
1543 { 0x1f, 0x0002 },
1544 { 0x0b, 0x0b10 },
1545 { 0x0c, 0xd1f7 },
1546 { 0x1f, 0x0002 },
1547 { 0x06, 0x5461 },
1548 { 0x1f, 0x0002 },
1549 { 0x05, 0x6662 },
1550 { 0x1f, 0x0000 },
1551 { 0x14, 0x0060 },
1552 { 0x1f, 0x0000 },
1553 { 0x0d, 0xf8a0 },
1554 { 0x1f, 0x0005 },
1555 { 0x05, 0xffc2 }
1556 };
1557
1558 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1559
1560 if (mdio_read(ioaddr, 0x06) == 0xc400) {
1561 struct phy_reg phy_reg_init_1[] = {
1562 { 0x1f, 0x0005 },
1563 { 0x01, 0x0300 },
1564 { 0x1f, 0x0000 },
1565 { 0x11, 0x401c },
1566 { 0x16, 0x4100 },
1567 { 0x1f, 0x0005 },
1568 { 0x07, 0x0010 },
1569 { 0x05, 0x83dc },
1570 { 0x06, 0x087d },
1571 { 0x05, 0x8300 },
1572 { 0x06, 0x0101 },
1573 { 0x06, 0x05f8 },
1574 { 0x06, 0xf9fa },
1575 { 0x06, 0xfbef },
1576 { 0x06, 0x79e2 },
1577 { 0x06, 0x835f },
1578 { 0x06, 0xe0f8 },
1579 { 0x06, 0x9ae1 },
1580 { 0x06, 0xf89b },
1581 { 0x06, 0xef31 },
1582 { 0x06, 0x3b65 },
1583 { 0x06, 0xaa07 },
1584 { 0x06, 0x81e4 },
1585 { 0x06, 0xf89a },
1586 { 0x06, 0xe5f8 },
1587 { 0x06, 0x9baf },
1588 { 0x06, 0x06ae },
1589 { 0x05, 0x83dc },
1590 { 0x06, 0x8300 },
1591 };
1592
1593 rtl_phy_write(ioaddr, phy_reg_init_1,
1594 ARRAY_SIZE(phy_reg_init_1));
1595 }
1596
1597 mdio_write(ioaddr, 0x1f, 0x0000);
1598}
1599
2857ffb7
FR		 1600static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1601{
1602 struct phy_reg phy_reg_init[] = {
1603 { 0x1f, 0x0003 },
1604 { 0x08, 0x441d },
1605 { 0x01, 0x9100 },
1606 { 0x1f, 0x0000 }
1607 };
1608
1609 mdio_write(ioaddr, 0x1f, 0x0000);
1610 mdio_patch(ioaddr, 0x11, 1 << 12);
1611 mdio_patch(ioaddr, 0x19, 1 << 13);
1612
1613 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1614}
1615
5615d9f1
FR		 1616static void rtl_hw_phy_config(struct net_device *dev)
1617{
1618 struct rtl8169_private *tp = netdev_priv(dev);
1619 void __iomem *ioaddr = tp->mmio_addr;
1620
1621 rtl8169_print_mac_version(tp);
1622
1623 switch (tp->mac_version) {
1624 case RTL_GIGA_MAC_VER_01:
1625 break;
1626 case RTL_GIGA_MAC_VER_02:
1627 case RTL_GIGA_MAC_VER_03:
1628 rtl8169s_hw_phy_config(ioaddr);
1629 break;
1630 case RTL_GIGA_MAC_VER_04:
1631 rtl8169sb_hw_phy_config(ioaddr);
1632 break;
2857ffb7
FR		 1633 case RTL_GIGA_MAC_VER_07:
1634 case RTL_GIGA_MAC_VER_08:
1635 case RTL_GIGA_MAC_VER_09:
1636 rtl8102e_hw_phy_config(ioaddr);
1637 break;
236b8082
FR		 1638 case RTL_GIGA_MAC_VER_11:
1639 rtl8168bb_hw_phy_config(ioaddr);
1640 break;
1641 case RTL_GIGA_MAC_VER_12:
1642 rtl8168bef_hw_phy_config(ioaddr);
1643 break;
1644 case RTL_GIGA_MAC_VER_17:
1645 rtl8168bef_hw_phy_config(ioaddr);
1646 break;
867763c1 1647 case RTL_GIGA_MAC_VER_18:
ef3386f0 1648 rtl8168cp_1_hw_phy_config(ioaddr);
867763c1
FR		 1649 break;
1650 case RTL_GIGA_MAC_VER_19:
219a1e9d 1651 rtl8168c_1_hw_phy_config(ioaddr);
867763c1 1652 break;
7da97ec9 1653 case RTL_GIGA_MAC_VER_20:
219a1e9d 1654 rtl8168c_2_hw_phy_config(ioaddr);
7da97ec9 1655 break;
197ff761
FR		 1656 case RTL_GIGA_MAC_VER_21:
1657 rtl8168c_3_hw_phy_config(ioaddr);
1658 break;
6fb07058
FR		 1659 case RTL_GIGA_MAC_VER_22:
1660 rtl8168c_4_hw_phy_config(ioaddr);
1661 break;
ef3386f0 1662 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 1663 case RTL_GIGA_MAC_VER_24:
ef3386f0
FR		 1664 rtl8168cp_2_hw_phy_config(ioaddr);
1665 break;
5b538df9
FR		 1666 case RTL_GIGA_MAC_VER_25:
1667 rtl8168d_hw_phy_config(ioaddr);
1668 break;
ef3386f0 1669
5615d9f1
FR		 1670 default:
1671 break;
1672 }
1673}
1674
1da177e4
LT		 1675static void rtl8169_phy_timer(unsigned long __opaque)
1676{
1677 struct net_device *dev = (struct net_device *)__opaque;
1678 struct rtl8169_private *tp = netdev_priv(dev);
1679 struct timer_list *timer = &tp->timer;
1680 void __iomem *ioaddr = tp->mmio_addr;
1681 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1682
bcf0bf90 1683 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1684
64e4bfb4 1685 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1686 return;
1687
1688 spin_lock_irq(&tp->lock);
1689
1690 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1691 /*
1da177e4
LT		 1692 * A busy loop could burn quite a few cycles on nowadays CPU.
1693 * Let's delay the execution of the timer for a few ticks.
1694 */
1695 timeout = HZ/10;
1696 goto out_mod_timer;
1697 }
1698
1699 if (tp->link_ok(ioaddr))
1700 goto out_unlock;
1701
b57b7e5a
SH		 1702 if (netif_msg_link(tp))
1703 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1704
1705 tp->phy_reset_enable(ioaddr);
1706
1707out_mod_timer:
1708 mod_timer(timer, jiffies + timeout);
1709out_unlock:
1710 spin_unlock_irq(&tp->lock);
1711}
1712
1713static inline void rtl8169_delete_timer(struct net_device *dev)
1714{
1715 struct rtl8169_private *tp = netdev_priv(dev);
1716 struct timer_list *timer = &tp->timer;
1717
e179bb7b 1718 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1719 return;
1720
1721 del_timer_sync(timer);
1722}
1723
1724static inline void rtl8169_request_timer(struct net_device *dev)
1725{
1726 struct rtl8169_private *tp = netdev_priv(dev);
1727 struct timer_list *timer = &tp->timer;
1728
e179bb7b 1729 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1730 return;
1731
2efa53f3 1732 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1733}
1734
1735#ifdef CONFIG_NET_POLL_CONTROLLER
1736/*
1737 * Polling 'interrupt' - used by things like netconsole to send skbs
1738 * without having to re-enable interrupts. It's not called while
1739 * the interrupt routine is executing.
1740 */
1741static void rtl8169_netpoll(struct net_device *dev)
1742{
1743 struct rtl8169_private *tp = netdev_priv(dev);
1744 struct pci_dev *pdev = tp->pci_dev;
1745
1746 disable_irq(pdev->irq);
7d12e780 1747 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1748 enable_irq(pdev->irq);
1749}
1750#endif
1751
1752static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1753 void __iomem *ioaddr)
1754{
1755 iounmap(ioaddr);
1756 pci_release_regions(pdev);
1757 pci_disable_device(pdev);
1758 free_netdev(dev);
1759}
1760
bf793295
FR		 1761static void rtl8169_phy_reset(struct net_device *dev,
1762 struct rtl8169_private *tp)
1763{
1764 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1765 unsigned int i;
bf793295
FR		 1766
1767 tp->phy_reset_enable(ioaddr);
1768 for (i = 0; i < 100; i++) {
1769 if (!tp->phy_reset_pending(ioaddr))
1770 return;
1771 msleep(1);
1772 }
1773 if (netif_msg_link(tp))
1774 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1775}
1776
4ff96fa6
FR		 1777static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1778{
1779 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1780
5615d9f1 1781 rtl_hw_phy_config(dev);
4ff96fa6 1782
77332894
MS		 1783 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1784 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1785 RTL_W8(0x82, 0x01);
1786 }
4ff96fa6 1787
6dccd16b
FR		 1788 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1789
1790 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1791 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1792
bcf0bf90 1793 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1794 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1795 RTL_W8(0x82, 0x01);
1796 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1797 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1798 }
1799
bf793295
FR		 1800 rtl8169_phy_reset(dev, tp);
1801
901dda2b
FR		 1802 /*
1803 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1804 * only 8101. Don't panic.
1805 */
1806 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1807
1808 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1809 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1810}
1811
773d2021
FR		 1812static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1813{
1814 void __iomem *ioaddr = tp->mmio_addr;
1815 u32 high;
1816 u32 low;
1817
1818 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1819 high = addr[4] | (addr[5] << 8);
1820
1821 spin_lock_irq(&tp->lock);
1822
1823 RTL_W8(Cfg9346, Cfg9346_Unlock);
1824 RTL_W32(MAC0, low);
1825 RTL_W32(MAC4, high);
1826 RTL_W8(Cfg9346, Cfg9346_Lock);
1827
1828 spin_unlock_irq(&tp->lock);
1829}
1830
1831static int rtl_set_mac_address(struct net_device *dev, void *p)
1832{
1833 struct rtl8169_private *tp = netdev_priv(dev);
1834 struct sockaddr *addr = p;
1835
1836 if (!is_valid_ether_addr(addr->sa_data))
1837 return -EADDRNOTAVAIL;
1838
1839 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1840
1841 rtl_rar_set(tp, dev->dev_addr);
1842
1843 return 0;
1844}
1845
5f787a1a
FR		 1846static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1847{
1848 struct rtl8169_private *tp = netdev_priv(dev);
1849 struct mii_ioctl_data *data = if_mii(ifr);
1850
8b4ab28d
FR		 1851 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
1852}
5f787a1a 1853
8b4ab28d
FR		 1854static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1855{
5f787a1a
FR		 1856 switch (cmd) {
1857 case SIOCGMIIPHY:
1858 data->phy_id = 32; /* Internal PHY */
1859 return 0;
1860
1861 case SIOCGMIIREG:
1862 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1863 return 0;
1864
1865 case SIOCSMIIREG:
1866 if (!capable(CAP_NET_ADMIN))
1867 return -EPERM;
1868 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1869 return 0;
1870 }
1871 return -EOPNOTSUPP;
1872}
1873
8b4ab28d
FR		 1874static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
1875{
1876 return -EOPNOTSUPP;
1877}
1878
0e485150
FR		 1879static const struct rtl_cfg_info {
1880 void (*hw_start)(struct net_device *);
1881 unsigned int region;
1882 unsigned int align;
1883 u16 intr_event;
1884 u16 napi_event;
ccdffb9a 1885 unsigned features;
0e485150
FR		 1886} rtl_cfg_infos [] = {
1887 [RTL_CFG_0] = {
1888 .hw_start = rtl_hw_start_8169,
1889 .region = 1,
e9f63f30 1890 .align = 0,
0e485150
FR		 1891 .intr_event = SYSErr | LinkChg | RxOverflow |
1892 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1893 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1894 .features = RTL_FEATURE_GMII
0e485150
FR		 1895 },
1896 [RTL_CFG_1] = {
1897 .hw_start = rtl_hw_start_8168,
1898 .region = 2,
1899 .align = 8,
1900 .intr_event = SYSErr | LinkChg | RxOverflow |
1901 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1902 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1903 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1904 },
1905 [RTL_CFG_2] = {
1906 .hw_start = rtl_hw_start_8101,
1907 .region = 2,
1908 .align = 8,
1909 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1910 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1911 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1912 .features = RTL_FEATURE_MSI
0e485150
FR		 1913 }
1914};
1915
fbac58fc
FR		 1916/* Cfg9346_Unlock assumed. */
1917static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1918 const struct rtl_cfg_info *cfg)
1919{
1920 unsigned msi = 0;
1921 u8 cfg2;
1922
1923 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1924 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1925 if (pci_enable_msi(pdev)) {
1926 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1927 } else {
1928 cfg2 |= MSIEnable;
1929 msi = RTL_FEATURE_MSI;
1930 }
1931 }
1932 RTL_W8(Config2, cfg2);
1933 return msi;
1934}
1935
1936static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1937{
1938 if (tp->features & RTL_FEATURE_MSI) {
1939 pci_disable_msi(pdev);
1940 tp->features &= ~RTL_FEATURE_MSI;
1941 }
1942}
1943
8b4ab28d
FR		 1944static const struct net_device_ops rtl8169_netdev_ops = {
1945 .ndo_open = rtl8169_open,
1946 .ndo_stop = rtl8169_close,
1947 .ndo_get_stats = rtl8169_get_stats,
00829823 1948 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 1949 .ndo_tx_timeout = rtl8169_tx_timeout,
1950 .ndo_validate_addr = eth_validate_addr,
1951 .ndo_change_mtu = rtl8169_change_mtu,
1952 .ndo_set_mac_address = rtl_set_mac_address,
1953 .ndo_do_ioctl = rtl8169_ioctl,
1954 .ndo_set_multicast_list = rtl_set_rx_mode,
1955#ifdef CONFIG_R8169_VLAN
1956 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
1957#endif
1958#ifdef CONFIG_NET_POLL_CONTROLLER
1959 .ndo_poll_controller = rtl8169_netpoll,
1960#endif
1961
1962};
1963
1da177e4 1964static int __devinit
4ff96fa6 1965rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1966{
0e485150
FR		 1967 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1968 const unsigned int region = cfg->region;
1da177e4 1969 struct rtl8169_private *tp;
ccdffb9a 1970 struct mii_if_info *mii;
4ff96fa6
FR		 1971 struct net_device *dev;
1972 void __iomem *ioaddr;
07d3f51f
FR		 1973 unsigned int i;
1974 int rc;
1da177e4 1975
4ff96fa6
FR		 1976 if (netif_msg_drv(&debug)) {
1977 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1978 MODULENAME, RTL8169_VERSION);
1979 }
1da177e4 1980
1da177e4 1981 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1982 if (!dev) {
b57b7e5a 1983 if (netif_msg_drv(&debug))
9b91cf9d 1984 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1985 rc = -ENOMEM;
1986 goto out;
1da177e4
LT		 1987 }
1988
1da177e4 1989 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 1990 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 1991 tp = netdev_priv(dev);
c4028958 1992 tp->dev = dev;
21e197f2 1993 tp->pci_dev = pdev;
b57b7e5a 1994 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1995
ccdffb9a
FR		 1996 mii = &tp->mii;
1997 mii->dev = dev;
1998 mii->mdio_read = rtl_mdio_read;
1999 mii->mdio_write = rtl_mdio_write;
2000 mii->phy_id_mask = 0x1f;
2001 mii->reg_num_mask = 0x1f;
2002 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2003
1da177e4
LT		 2004 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2005 rc = pci_enable_device(pdev);
b57b7e5a 2006 if (rc < 0) {
2e8a538d 2007 if (netif_msg_probe(tp))
9b91cf9d 2008 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 2009 goto err_out_free_dev_1;
1da177e4
LT		 2010 }
2011
2012 rc = pci_set_mwi(pdev);
2013 if (rc < 0)
4ff96fa6 2014 goto err_out_disable_2;
1da177e4 2015
1da177e4 2016 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 2017 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 2018 if (netif_msg_probe(tp)) {
9b91cf9d 2019 dev_err(&pdev->dev,
bcf0bf90
FR		 2020 "region #%d not an MMIO resource, aborting\n",
2021 region);
4ff96fa6 2022 }
1da177e4 2023 rc = -ENODEV;
4ff96fa6 2024 goto err_out_mwi_3;
1da177e4 2025 }
4ff96fa6 2026
1da177e4 2027 /* check for weird/broken PCI region reporting */
bcf0bf90 2028 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 2029 if (netif_msg_probe(tp)) {
9b91cf9d 2030 dev_err(&pdev->dev,
4ff96fa6
FR		 2031 "Invalid PCI region size(s), aborting\n");
2032 }
1da177e4 2033 rc = -ENODEV;
4ff96fa6 2034 goto err_out_mwi_3;
1da177e4
LT		 2035 }
2036
2037 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 2038 if (rc < 0) {
2e8a538d 2039 if (netif_msg_probe(tp))
9b91cf9d 2040 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 2041 goto err_out_mwi_3;
1da177e4
LT		 2042 }
2043
2044 tp->cp_cmd = PCIMulRW | RxChkSum;
2045
2046 if ((sizeof(dma_addr_t) > 4) &&
6a35528a 2047 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 2048 tp->cp_cmd |= PCIDAC;
2049 dev->features |= NETIF_F_HIGHDMA;
2050 } else {
284901a9 2051 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 2052 if (rc < 0) {
4ff96fa6 2053 if (netif_msg_probe(tp)) {
9b91cf9d 2054 dev_err(&pdev->dev,
4ff96fa6
FR		 2055 "DMA configuration failed.\n");
2056 }
2057 goto err_out_free_res_4;
1da177e4
LT		 2058 }
2059 }
2060
2061 pci_set_master(pdev);
2062
2063 /* ioremap MMIO region */
bcf0bf90 2064 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 2065 if (!ioaddr) {
b57b7e5a 2066 if (netif_msg_probe(tp))
9b91cf9d 2067 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 2068 rc = -EIO;
4ff96fa6 2069 goto err_out_free_res_4;
1da177e4
LT		 2070 }
2071
9c14ceaf
FR		 2072 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2073 if (!tp->pcie_cap && netif_msg_probe(tp))
2074 dev_info(&pdev->dev, "no PCI Express capability\n");
2075
d78ad8cb 2076 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 2077
2078 /* Soft reset the chip. */
2079 RTL_W8(ChipCmd, CmdReset);
2080
2081 /* Check that the chip has finished the reset. */
07d3f51f 2082 for (i = 0; i < 100; i++) {
1da177e4
LT		 2083 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2084 break;
b518fa8e 2085 msleep_interruptible(1);
1da177e4
LT		 2086 }
2087
d78ad8cb
KW		 2088 RTL_W16(IntrStatus, 0xffff);
2089
1da177e4
LT		 2090 /* Identify chip attached to board */
2091 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 2092
2093 rtl8169_print_mac_version(tp);
1da177e4 2094
cee60c37 2095 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 2096 if (tp->mac_version == rtl_chip_info[i].mac_version)
2097 break;
2098 }
cee60c37 2099 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 2100 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 2101 if (netif_msg_probe(tp)) {
2e8a538d 2102 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 2103 "unknown chip version, assuming %s\n",
2104 rtl_chip_info[0].name);
b57b7e5a 2105 }
cee60c37 2106 i = 0;
1da177e4
LT		 2107 }
2108 tp->chipset = i;
2109
5d06a99f
FR		 2110 RTL_W8(Cfg9346, Cfg9346_Unlock);
2111 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2112 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 2113 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2114 tp->features |= RTL_FEATURE_WOL;
2115 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2116 tp->features |= RTL_FEATURE_WOL;
fbac58fc 2117 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 2118 RTL_W8(Cfg9346, Cfg9346_Lock);
2119
66ec5d4f
FR		 2120 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2121 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 2122 tp->set_speed = rtl8169_set_speed_tbi;
2123 tp->get_settings = rtl8169_gset_tbi;
2124 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2125 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2126 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 2127 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 2128
64e4bfb4 2129 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 2130 } else {
2131 tp->set_speed = rtl8169_set_speed_xmii;
2132 tp->get_settings = rtl8169_gset_xmii;
2133 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2134 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2135 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 2136 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 2137 }
2138
df58ef51
FR		 2139 spin_lock_init(&tp->lock);
2140
738e1e69
PV		 2141 tp->mmio_addr = ioaddr;
2142
7bf6bf48 2143 /* Get MAC address */
1da177e4
LT		 2144 for (i = 0; i < MAC_ADDR_LEN; i++)
2145 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 2146 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 2147
1da177e4 2148 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 2149 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2150 dev->irq = pdev->irq;
2151 dev->base_addr = (unsigned long) ioaddr;
1da177e4 2152
bea3348e 2153 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 2154
2155#ifdef CONFIG_R8169_VLAN
2156 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4
LT		 2157#endif
2158
2159 tp->intr_mask = 0xffff;
0e485150
FR		 2160 tp->align = cfg->align;
2161 tp->hw_start = cfg->hw_start;
2162 tp->intr_event = cfg->intr_event;
2163 tp->napi_event = cfg->napi_event;
1da177e4 2164
2efa53f3
FR		 2165 init_timer(&tp->timer);
2166 tp->timer.data = (unsigned long) dev;
2167 tp->timer.function = rtl8169_phy_timer;
2168
1da177e4 2169 rc = register_netdev(dev);
4ff96fa6 2170 if (rc < 0)
fbac58fc 2171 goto err_out_msi_5;
1da177e4
LT		 2172
2173 pci_set_drvdata(pdev, dev);
2174
b57b7e5a 2175 if (netif_msg_probe(tp)) {
96b9709c
FR		 2176 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2177
b57b7e5a
SH		 2178 printk(KERN_INFO "%s: %s at 0x%lx, "
2179 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2180 "XID %08x IRQ %d\n",
b57b7e5a 2181 dev->name,
bcf0bf90 2182 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2183 dev->base_addr,
2184 dev->dev_addr[0], dev->dev_addr[1],
2185 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2186 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2187 }
1da177e4 2188
4ff96fa6 2189 rtl8169_init_phy(dev, tp);
8b76ab39 2190 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2191
4ff96fa6
FR		 2192out:
2193 return rc;
1da177e4 2194
fbac58fc
FR		 2195err_out_msi_5:
2196 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2197 iounmap(ioaddr);
2198err_out_free_res_4:
2199 pci_release_regions(pdev);
2200err_out_mwi_3:
2201 pci_clear_mwi(pdev);
2202err_out_disable_2:
2203 pci_disable_device(pdev);
2204err_out_free_dev_1:
2205 free_netdev(dev);
2206 goto out;
1da177e4
LT		 2207}
2208
07d3f51f 2209static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2210{
2211 struct net_device *dev = pci_get_drvdata(pdev);
2212 struct rtl8169_private *tp = netdev_priv(dev);
2213
eb2a021c
FR		 2214 flush_scheduled_work();
2215
1da177e4 2216 unregister_netdev(dev);
fbac58fc 2217 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2218 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2219 pci_set_drvdata(pdev, NULL);
2220}
2221
1da177e4
LT		 2222static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2223 struct net_device *dev)
2224{
2225 unsigned int mtu = dev->mtu;
2226
2227 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2228}
2229
2230static int rtl8169_open(struct net_device *dev)
2231{
2232 struct rtl8169_private *tp = netdev_priv(dev);
2233 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2234 int retval = -ENOMEM;
1da177e4 2235
1da177e4 2236
99f252b0 2237 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2238
2239 /*
2240 * Rx and Tx desscriptors needs 256 bytes alignment.
2241 * pci_alloc_consistent provides more.
2242 */
2243 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2244 &tp->TxPhyAddr);
2245 if (!tp->TxDescArray)
99f252b0 2246 goto out;
1da177e4
LT		 2247
2248 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2249 &tp->RxPhyAddr);
2250 if (!tp->RxDescArray)
99f252b0 2251 goto err_free_tx_0;
1da177e4
LT		 2252
2253 retval = rtl8169_init_ring(dev);
2254 if (retval < 0)
99f252b0 2255 goto err_free_rx_1;
1da177e4 2256
c4028958 2257 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2258
99f252b0
FR		 2259 smp_mb();
2260
fbac58fc
FR		 2261 retval = request_irq(dev->irq, rtl8169_interrupt,
2262 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2263 dev->name, dev);
2264 if (retval < 0)
2265 goto err_release_ring_2;
2266
bea3348e 2267 napi_enable(&tp->napi);
bea3348e 2268
07ce4064 2269 rtl_hw_start(dev);
1da177e4
LT		 2270
2271 rtl8169_request_timer(dev);
2272
2273 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2274out:
2275 return retval;
2276
99f252b0
FR		 2277err_release_ring_2:
2278 rtl8169_rx_clear(tp);
2279err_free_rx_1:
1da177e4
LT		 2280 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2281 tp->RxPhyAddr);
99f252b0 2282err_free_tx_0:
1da177e4
LT		 2283 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2284 tp->TxPhyAddr);
1da177e4
LT		 2285 goto out;
2286}
2287
2288static void rtl8169_hw_reset(void __iomem *ioaddr)
2289{
2290 /* Disable interrupts */
2291 rtl8169_irq_mask_and_ack(ioaddr);
2292
2293 /* Reset the chipset */
2294 RTL_W8(ChipCmd, CmdReset);
2295
2296 /* PCI commit */
2297 RTL_R8(ChipCmd);
2298}
2299
7f796d83 2300static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2301{
2302 void __iomem *ioaddr = tp->mmio_addr;
2303 u32 cfg = rtl8169_rx_config;
2304
2305 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2306 RTL_W32(RxConfig, cfg);
2307
2308 /* Set DMA burst size and Interframe Gap Time */
2309 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2310 (InterFrameGap << TxInterFrameGapShift));
2311}
2312
07ce4064 2313static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2314{
2315 struct rtl8169_private *tp = netdev_priv(dev);
2316 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2317 unsigned int i;
1da177e4
LT		 2318
2319 /* Soft reset the chip. */
2320 RTL_W8(ChipCmd, CmdReset);
2321
2322 /* Check that the chip has finished the reset. */
07d3f51f 2323 for (i = 0; i < 100; i++) {
1da177e4
LT		 2324 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2325 break;
b518fa8e 2326 msleep_interruptible(1);
1da177e4
LT		 2327 }
2328
07ce4064
FR		 2329 tp->hw_start(dev);
2330
07ce4064
FR		 2331 netif_start_queue(dev);
2332}
2333
2334
7f796d83
FR		 2335static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2336 void __iomem *ioaddr)
2337{
2338 /*
2339 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2340 * register to be written before TxDescAddrLow to work.
2341 * Switching from MMIO to I/O access fixes the issue as well.
2342 */
2343 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 2344 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 2345 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 2346 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 2347}
2348
2349static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2350{
2351 u16 cmd;
2352
2353 cmd = RTL_R16(CPlusCmd);
2354 RTL_W16(CPlusCmd, cmd);
2355 return cmd;
2356}
2357
2358static void rtl_set_rx_max_size(void __iomem *ioaddr)
2359{
2360 /* Low hurts. Let's disable the filtering. */
2361 RTL_W16(RxMaxSize, 16383);
2362}
2363
6dccd16b
FR		 2364static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2365{
2366 struct {
2367 u32 mac_version;
2368 u32 clk;
2369 u32 val;
2370 } cfg2_info [] = {
2371 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2372 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2373 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2374 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2375 }, *p = cfg2_info;
2376 unsigned int i;
2377 u32 clk;
2378
2379 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2380 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2381 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2382 RTL_W32(0x7c, p->val);
2383 break;
2384 }
2385 }
2386}
2387
07ce4064
FR		 2388static void rtl_hw_start_8169(struct net_device *dev)
2389{
2390 struct rtl8169_private *tp = netdev_priv(dev);
2391 void __iomem *ioaddr = tp->mmio_addr;
2392 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2393
9cb427b6
FR		 2394 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2395 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2396 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2397 }
2398
1da177e4 2399 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2400 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2401 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2402 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2403 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2404 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2405
1da177e4
LT		 2406 RTL_W8(EarlyTxThres, EarlyTxThld);
2407
7f796d83 2408 rtl_set_rx_max_size(ioaddr);
1da177e4 2409
c946b304
FR		 2410 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2411 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2412 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2413 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2414 rtl_set_rx_tx_config_registers(tp);
1da177e4 2415
7f796d83 2416 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2417
bcf0bf90
FR		 2418 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2419 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2420 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2421 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2422 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2423 }
2424
bcf0bf90
FR		 2425 RTL_W16(CPlusCmd, tp->cp_cmd);
2426
6dccd16b
FR		 2427 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2428
1da177e4
LT		 2429 /*
2430 * Undocumented corner. Supposedly:
2431 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2432 */
2433 RTL_W16(IntrMitigate, 0x0000);
2434
7f796d83 2435 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2436
c946b304
FR		 2437 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2438 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2439 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2440 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2441 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2442 rtl_set_rx_tx_config_registers(tp);
2443 }
2444
1da177e4 2445 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2446
2447 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2448 RTL_R8(IntrMask);
1da177e4
LT		 2449
2450 RTL_W32(RxMissed, 0);
2451
07ce4064 2452 rtl_set_rx_mode(dev);
1da177e4
LT		 2453
2454 /* no early-rx interrupts */
2455 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2456
2457 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2458 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2459}
1da177e4 2460
9c14ceaf 2461static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2462{
9c14ceaf
FR		 2463 struct net_device *dev = pci_get_drvdata(pdev);
2464 struct rtl8169_private *tp = netdev_priv(dev);
2465 int cap = tp->pcie_cap;
2466
2467 if (cap) {
2468 u16 ctl;
458a9f61 2469
9c14ceaf
FR		 2470 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2471 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2472 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2473 }
458a9f61
FR		 2474}
2475
dacf8154
FR		 2476static void rtl_csi_access_enable(void __iomem *ioaddr)
2477{
2478 u32 csi;
2479
2480 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2481 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2482}
2483
2484struct ephy_info {
2485 unsigned int offset;
2486 u16 mask;
2487 u16 bits;
2488};
2489
2490static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2491{
2492 u16 w;
2493
2494 while (len-- > 0) {
2495 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2496 rtl_ephy_write(ioaddr, e->offset, w);
2497 e++;
2498 }
2499}
2500
b726e493
FR		 2501static void rtl_disable_clock_request(struct pci_dev *pdev)
2502{
2503 struct net_device *dev = pci_get_drvdata(pdev);
2504 struct rtl8169_private *tp = netdev_priv(dev);
2505 int cap = tp->pcie_cap;
2506
2507 if (cap) {
2508 u16 ctl;
2509
2510 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2511 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2512 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2513 }
2514}
2515
2516#define R8168_CPCMD_QUIRK_MASK (\
2517 EnableBist | \
2518 Mac_dbgo_oe | \
2519 Force_half_dup | \
2520 Force_rxflow_en | \
2521 Force_txflow_en | \
2522 Cxpl_dbg_sel | \
2523 ASF | \
2524 PktCntrDisable | \
2525 Mac_dbgo_sel)
2526
219a1e9d
FR		 2527static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2528{
b726e493
FR		 2529 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2530
2531 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2532
2e68ae44
FR		 2533 rtl_tx_performance_tweak(pdev,
2534 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 2535}
2536
2537static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2538{
2539 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493
FR		 2540
2541 RTL_W8(EarlyTxThres, EarlyTxThld);
2542
2543 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 2544}
2545
2546static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2547{
b726e493
FR		 2548 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2549
2550 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2551
219a1e9d 2552 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 2553
2554 rtl_disable_clock_request(pdev);
2555
2556 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 2557}
2558
ef3386f0 2559static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 2560{
b726e493
FR		 2561 static struct ephy_info e_info_8168cp[] = {
2562 { 0x01, 0, 0x0001 },
2563 { 0x02, 0x0800, 0x1000 },
2564 { 0x03, 0, 0x0042 },
2565 { 0x06, 0x0080, 0x0000 },
2566 { 0x07, 0, 0x2000 }
2567 };
2568
2569 rtl_csi_access_enable(ioaddr);
2570
2571 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2572
219a1e9d
FR		 2573 __rtl_hw_start_8168cp(ioaddr, pdev);
2574}
2575
ef3386f0
FR		 2576static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2577{
2578 rtl_csi_access_enable(ioaddr);
2579
2580 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2581
2582 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2583
2584 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2585}
2586
7f3e3d3a
FR		 2587static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2588{
2589 rtl_csi_access_enable(ioaddr);
2590
2591 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2592
2593 /* Magic. */
2594 RTL_W8(DBG_REG, 0x20);
2595
2596 RTL_W8(EarlyTxThres, EarlyTxThld);
2597
2598 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2599
2600 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2601}
2602
219a1e9d
FR		 2603static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2604{
b726e493
FR		 2605 static struct ephy_info e_info_8168c_1[] = {
2606 { 0x02, 0x0800, 0x1000 },
2607 { 0x03, 0, 0x0002 },
2608 { 0x06, 0x0080, 0x0000 }
2609 };
2610
2611 rtl_csi_access_enable(ioaddr);
2612
2613 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2614
2615 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2616
219a1e9d
FR		 2617 __rtl_hw_start_8168cp(ioaddr, pdev);
2618}
2619
2620static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2621{
b726e493
FR		 2622 static struct ephy_info e_info_8168c_2[] = {
2623 { 0x01, 0, 0x0001 },
2624 { 0x03, 0x0400, 0x0220 }
2625 };
2626
2627 rtl_csi_access_enable(ioaddr);
2628
2629 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2630
219a1e9d
FR		 2631 __rtl_hw_start_8168cp(ioaddr, pdev);
2632}
2633
197ff761
FR		 2634static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2635{
2636 rtl_hw_start_8168c_2(ioaddr, pdev);
2637}
2638
6fb07058
FR		 2639static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2640{
2641 rtl_csi_access_enable(ioaddr);
2642
2643 __rtl_hw_start_8168cp(ioaddr, pdev);
2644}
2645
5b538df9
FR		 2646static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2647{
2648 rtl_csi_access_enable(ioaddr);
2649
2650 rtl_disable_clock_request(pdev);
2651
2652 RTL_W8(EarlyTxThres, EarlyTxThld);
2653
2654 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2655
2656 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2657}
2658
07ce4064
FR		 2659static void rtl_hw_start_8168(struct net_device *dev)
2660{
2dd99530
FR		 2661 struct rtl8169_private *tp = netdev_priv(dev);
2662 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2663 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2664
2665 RTL_W8(Cfg9346, Cfg9346_Unlock);
2666
2667 RTL_W8(EarlyTxThres, EarlyTxThld);
2668
2669 rtl_set_rx_max_size(ioaddr);
2670
0e485150 2671 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2672
2673 RTL_W16(CPlusCmd, tp->cp_cmd);
2674
0e485150 2675 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2676
0e485150
FR		 2677 /* Work around for RxFIFO overflow. */
2678 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2679 tp->intr_event |= RxFIFOOver | PCSTimeout;
2680 tp->intr_event &= ~RxOverflow;
2681 }
2682
2683 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 2684
b8363901
FR		 2685 rtl_set_rx_mode(dev);
2686
2687 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2688 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 2689
2690 RTL_R8(IntrMask);
2691
219a1e9d
FR		 2692 switch (tp->mac_version) {
2693 case RTL_GIGA_MAC_VER_11:
2694 rtl_hw_start_8168bb(ioaddr, pdev);
2695 break;
2696
2697 case RTL_GIGA_MAC_VER_12:
2698 case RTL_GIGA_MAC_VER_17:
2699 rtl_hw_start_8168bef(ioaddr, pdev);
2700 break;
2701
2702 case RTL_GIGA_MAC_VER_18:
ef3386f0 2703 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 2704 break;
2705
2706 case RTL_GIGA_MAC_VER_19:
2707 rtl_hw_start_8168c_1(ioaddr, pdev);
2708 break;
2709
2710 case RTL_GIGA_MAC_VER_20:
2711 rtl_hw_start_8168c_2(ioaddr, pdev);
2712 break;
2713
197ff761
FR		 2714 case RTL_GIGA_MAC_VER_21:
2715 rtl_hw_start_8168c_3(ioaddr, pdev);
2716 break;
2717
6fb07058
FR		 2718 case RTL_GIGA_MAC_VER_22:
2719 rtl_hw_start_8168c_4(ioaddr, pdev);
2720 break;
2721
ef3386f0
FR		 2722 case RTL_GIGA_MAC_VER_23:
2723 rtl_hw_start_8168cp_2(ioaddr, pdev);
2724 break;
2725
7f3e3d3a
FR		 2726 case RTL_GIGA_MAC_VER_24:
2727 rtl_hw_start_8168cp_3(ioaddr, pdev);
2728 break;
2729
5b538df9
FR		 2730 case RTL_GIGA_MAC_VER_25:
2731 rtl_hw_start_8168d(ioaddr, pdev);
2732 break;
2733
219a1e9d
FR		 2734 default:
2735 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2736 dev->name, tp->mac_version);
2737 break;
2738 }
2dd99530 2739
0e485150
FR		 2740 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2741
b8363901
FR		 2742 RTL_W8(Cfg9346, Cfg9346_Lock);
2743
2dd99530 2744 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2745
0e485150 2746 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2747}
1da177e4 2748
2857ffb7
FR		 2749#define R810X_CPCMD_QUIRK_MASK (\
2750 EnableBist | \
2751 Mac_dbgo_oe | \
2752 Force_half_dup | \
2753 Force_half_dup | \
2754 Force_txflow_en | \
2755 Cxpl_dbg_sel | \
2756 ASF | \
2757 PktCntrDisable | \
2758 PCIDAC | \
2759 PCIMulRW)
2760
2761static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2762{
2763 static struct ephy_info e_info_8102e_1[] = {
2764 { 0x01, 0, 0x6e65 },
2765 { 0x02, 0, 0x091f },
2766 { 0x03, 0, 0xc2f9 },
2767 { 0x06, 0, 0xafb5 },
2768 { 0x07, 0, 0x0e00 },
2769 { 0x19, 0, 0xec80 },
2770 { 0x01, 0, 0x2e65 },
2771 { 0x01, 0, 0x6e65 }
2772 };
2773 u8 cfg1;
2774
2775 rtl_csi_access_enable(ioaddr);
2776
2777 RTL_W8(DBG_REG, FIX_NAK_1);
2778
2779 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2780
2781 RTL_W8(Config1,
2782 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2783 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2784
2785 cfg1 = RTL_R8(Config1);
2786 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2787 RTL_W8(Config1, cfg1 & ~LEDS0);
2788
2789 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2790
2791 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2792}
2793
2794static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2795{
2796 rtl_csi_access_enable(ioaddr);
2797
2798 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2799
2800 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2801 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2802
2803 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2804}
2805
2806static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2807{
2808 rtl_hw_start_8102e_2(ioaddr, pdev);
2809
2810 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2811}
2812
07ce4064
FR		 2813static void rtl_hw_start_8101(struct net_device *dev)
2814{
cdf1a608
FR		 2815 struct rtl8169_private *tp = netdev_priv(dev);
2816 void __iomem *ioaddr = tp->mmio_addr;
2817 struct pci_dev *pdev = tp->pci_dev;
2818
e3cf0cc0
FR		 2819 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2820 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2821 int cap = tp->pcie_cap;
2822
2823 if (cap) {
2824 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2825 PCI_EXP_DEVCTL_NOSNOOP_EN);
2826 }
cdf1a608
FR		 2827 }
2828
2857ffb7
FR		 2829 switch (tp->mac_version) {
2830 case RTL_GIGA_MAC_VER_07:
2831 rtl_hw_start_8102e_1(ioaddr, pdev);
2832 break;
2833
2834 case RTL_GIGA_MAC_VER_08:
2835 rtl_hw_start_8102e_3(ioaddr, pdev);
2836 break;
2837
2838 case RTL_GIGA_MAC_VER_09:
2839 rtl_hw_start_8102e_2(ioaddr, pdev);
2840 break;
cdf1a608
FR		 2841 }
2842
2843 RTL_W8(Cfg9346, Cfg9346_Unlock);
2844
2845 RTL_W8(EarlyTxThres, EarlyTxThld);
2846
2847 rtl_set_rx_max_size(ioaddr);
2848
2849 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2850
2851 RTL_W16(CPlusCmd, tp->cp_cmd);
2852
2853 RTL_W16(IntrMitigate, 0x0000);
2854
2855 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2856
2857 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2858 rtl_set_rx_tx_config_registers(tp);
2859
2860 RTL_W8(Cfg9346, Cfg9346_Lock);
2861
2862 RTL_R8(IntrMask);
2863
cdf1a608
FR		 2864 rtl_set_rx_mode(dev);
2865
0e485150
FR		 2866 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2867
cdf1a608 2868 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2869
0e485150 2870 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2871}
2872
2873static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2874{
2875 struct rtl8169_private *tp = netdev_priv(dev);
2876 int ret = 0;
2877
2878 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2879 return -EINVAL;
2880
2881 dev->mtu = new_mtu;
2882
2883 if (!netif_running(dev))
2884 goto out;
2885
2886 rtl8169_down(dev);
2887
2888 rtl8169_set_rxbufsize(tp, dev);
2889
2890 ret = rtl8169_init_ring(dev);
2891 if (ret < 0)
2892 goto out;
2893
bea3348e 2894 napi_enable(&tp->napi);
1da177e4 2895
07ce4064 2896 rtl_hw_start(dev);
1da177e4
LT		 2897
2898 rtl8169_request_timer(dev);
2899
2900out:
2901 return ret;
2902}
2903
2904static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2905{
95e0918d 2906 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2907 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2908}
2909
2910static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2911 struct sk_buff **sk_buff, struct RxDesc *desc)
2912{
2913 struct pci_dev *pdev = tp->pci_dev;
2914
2915 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2916 PCI_DMA_FROMDEVICE);
2917 dev_kfree_skb(*sk_buff);
2918 *sk_buff = NULL;
2919 rtl8169_make_unusable_by_asic(desc);
2920}
2921
2922static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2923{
2924 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2925
2926 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2927}
2928
2929static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2930 u32 rx_buf_sz)
2931{
2932 desc->addr = cpu_to_le64(mapping);
2933 wmb();
2934 rtl8169_mark_to_asic(desc, rx_buf_sz);
2935}
2936
15d31758
SH		 2937static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2938 struct net_device *dev,
2939 struct RxDesc *desc, int rx_buf_sz,
2940 unsigned int align)
1da177e4
LT		 2941{
2942 struct sk_buff *skb;
2943 dma_addr_t mapping;
e9f63f30 2944 unsigned int pad;
1da177e4 2945
e9f63f30
FR		 2946 pad = align ? align : NET_IP_ALIGN;
2947
2948 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2949 if (!skb)
2950 goto err_out;
2951
e9f63f30 2952 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2953
689be439 2954 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2955 PCI_DMA_FROMDEVICE);
2956
2957 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2958out:
15d31758 2959 return skb;
1da177e4
LT		 2960
2961err_out:
1da177e4
LT		 2962 rtl8169_make_unusable_by_asic(desc);
2963 goto out;
2964}
2965
2966static void rtl8169_rx_clear(struct rtl8169_private *tp)
2967{
07d3f51f 2968 unsigned int i;
1da177e4
LT		 2969
2970 for (i = 0; i < NUM_RX_DESC; i++) {
2971 if (tp->Rx_skbuff[i]) {
2972 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2973 tp->RxDescArray + i);
2974 }
2975 }
2976}
2977
2978static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2979 u32 start, u32 end)
2980{
2981 u32 cur;
5b0384f4 2982
4ae47c2d 2983 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2984 struct sk_buff *skb;
2985 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2986
4ae47c2d
FR		 2987 WARN_ON((s32)(end - cur) < 0);
2988
1da177e4
LT		 2989 if (tp->Rx_skbuff[i])
2990 continue;
bcf0bf90 2991
15d31758
SH		 2992 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2993 tp->RxDescArray + i,
2994 tp->rx_buf_sz, tp->align);
2995 if (!skb)
1da177e4 2996 break;
15d31758
SH		 2997
2998 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2999 }
3000 return cur - start;
3001}
3002
3003static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3004{
3005 desc->opts1 |= cpu_to_le32(RingEnd);
3006}
3007
3008static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3009{
3010 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3011}
3012
3013static int rtl8169_init_ring(struct net_device *dev)
3014{
3015 struct rtl8169_private *tp = netdev_priv(dev);
3016
3017 rtl8169_init_ring_indexes(tp);
3018
3019 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3020 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3021
3022 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3023 goto err_out;
3024
3025 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3026
3027 return 0;
3028
3029err_out:
3030 rtl8169_rx_clear(tp);
3031 return -ENOMEM;
3032}
3033
3034static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3035 struct TxDesc *desc)
3036{
3037 unsigned int len = tx_skb->len;
3038
3039 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3040 desc->opts1 = 0x00;
3041 desc->opts2 = 0x00;
3042 desc->addr = 0x00;
3043 tx_skb->len = 0;
3044}
3045
3046static void rtl8169_tx_clear(struct rtl8169_private *tp)
3047{
3048 unsigned int i;
3049
3050 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3051 unsigned int entry = i % NUM_TX_DESC;
3052 struct ring_info *tx_skb = tp->tx_skb + entry;
3053 unsigned int len = tx_skb->len;
3054
3055 if (len) {
3056 struct sk_buff *skb = tx_skb->skb;
3057
3058 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3059 tp->TxDescArray + entry);
3060 if (skb) {
3061 dev_kfree_skb(skb);
3062 tx_skb->skb = NULL;
3063 }
cebf8cc7 3064 tp->dev->stats.tx_dropped++;
1da177e4
LT		 3065 }
3066 }
3067 tp->cur_tx = tp->dirty_tx = 0;
3068}
3069
c4028958 3070static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 3071{
3072 struct rtl8169_private *tp = netdev_priv(dev);
3073
c4028958 3074 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 3075 schedule_delayed_work(&tp->task, 4);
3076}
3077
3078static void rtl8169_wait_for_quiescence(struct net_device *dev)
3079{
3080 struct rtl8169_private *tp = netdev_priv(dev);
3081 void __iomem *ioaddr = tp->mmio_addr;
3082
3083 synchronize_irq(dev->irq);
3084
3085 /* Wait for any pending NAPI task to complete */
bea3348e 3086 napi_disable(&tp->napi);
1da177e4
LT		 3087
3088 rtl8169_irq_mask_and_ack(ioaddr);
3089
d1d08d12
DM		 3090 tp->intr_mask = 0xffff;
3091 RTL_W16(IntrMask, tp->intr_event);
bea3348e 3092 napi_enable(&tp->napi);
1da177e4
LT		 3093}
3094
c4028958 3095static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 3096{
c4028958
DH		 3097 struct rtl8169_private *tp =
3098 container_of(work, struct rtl8169_private, task.work);
3099 struct net_device *dev = tp->dev;
1da177e4
LT		 3100 int ret;
3101
eb2a021c
FR		 3102 rtnl_lock();
3103
3104 if (!netif_running(dev))
3105 goto out_unlock;
3106
3107 rtl8169_wait_for_quiescence(dev);
3108 rtl8169_close(dev);
1da177e4
LT		 3109
3110 ret = rtl8169_open(dev);
3111 if (unlikely(ret < 0)) {
07d3f51f 3112 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 3113 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 3114 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 3115 }
3116 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3117 }
eb2a021c
FR		 3118
3119out_unlock:
3120 rtnl_unlock();
1da177e4
LT		 3121}
3122
c4028958 3123static void rtl8169_reset_task(struct work_struct *work)
1da177e4 3124{
c4028958
DH		 3125 struct rtl8169_private *tp =
3126 container_of(work, struct rtl8169_private, task.work);
3127 struct net_device *dev = tp->dev;
1da177e4 3128
eb2a021c
FR		 3129 rtnl_lock();
3130
1da177e4 3131 if (!netif_running(dev))
eb2a021c 3132 goto out_unlock;
1da177e4
LT		 3133
3134 rtl8169_wait_for_quiescence(dev);
3135
bea3348e 3136 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 3137 rtl8169_tx_clear(tp);
3138
3139 if (tp->dirty_rx == tp->cur_rx) {
3140 rtl8169_init_ring_indexes(tp);
07ce4064 3141 rtl_hw_start(dev);
1da177e4 3142 netif_wake_queue(dev);
cebf8cc7 3143 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 3144 } else {
07d3f51f 3145 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 3146 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 3147 dev->name);
1da177e4
LT		 3148 }
3149 rtl8169_schedule_work(dev, rtl8169_reset_task);
3150 }
eb2a021c
FR		 3151
3152out_unlock:
3153 rtnl_unlock();
1da177e4
LT		 3154}
3155
3156static void rtl8169_tx_timeout(struct net_device *dev)
3157{
3158 struct rtl8169_private *tp = netdev_priv(dev);
3159
3160 rtl8169_hw_reset(tp->mmio_addr);
3161
3162 /* Let's wait a bit while any (async) irq lands on */
3163 rtl8169_schedule_work(dev, rtl8169_reset_task);
3164}
3165
3166static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3167 u32 opts1)
3168{
3169 struct skb_shared_info *info = skb_shinfo(skb);
3170 unsigned int cur_frag, entry;
a6343afb 3171 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 3172
3173 entry = tp->cur_tx;
3174 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3175 skb_frag_t *frag = info->frags + cur_frag;
3176 dma_addr_t mapping;
3177 u32 status, len;
3178 void *addr;
3179
3180 entry = (entry + 1) % NUM_TX_DESC;
3181
3182 txd = tp->TxDescArray + entry;
3183 len = frag->size;
3184 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3185 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3186
3187 /* anti gcc 2.95.3 bugware (sic) */
3188 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3189
3190 txd->opts1 = cpu_to_le32(status);
3191 txd->addr = cpu_to_le64(mapping);
3192
3193 tp->tx_skb[entry].len = len;
3194 }
3195
3196 if (cur_frag) {
3197 tp->tx_skb[entry].skb = skb;
3198 txd->opts1 |= cpu_to_le32(LastFrag);
3199 }
3200
3201 return cur_frag;
3202}
3203
3204static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3205{
3206 if (dev->features & NETIF_F_TSO) {
7967168c 3207 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 3208
3209 if (mss)
3210 return LargeSend | ((mss & MSSMask) << MSSShift);
3211 }
84fa7933 3212 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 3213 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 3214
3215 if (ip->protocol == IPPROTO_TCP)
3216 return IPCS | TCPCS;
3217 else if (ip->protocol == IPPROTO_UDP)
3218 return IPCS | UDPCS;
3219 WARN_ON(1); /* we need a WARN() */
3220 }
3221 return 0;
3222}
3223
3224static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3225{
3226 struct rtl8169_private *tp = netdev_priv(dev);
3227 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3228 struct TxDesc *txd = tp->TxDescArray + entry;
3229 void __iomem *ioaddr = tp->mmio_addr;
3230 dma_addr_t mapping;
3231 u32 status, len;
3232 u32 opts1;
188f4af0 3233 int ret = NETDEV_TX_OK;
5b0384f4 3234
1da177e4 3235 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 3236 if (netif_msg_drv(tp)) {
3237 printk(KERN_ERR
3238 "%s: BUG! Tx Ring full when queue awake!\n",
3239 dev->name);
3240 }
1da177e4
LT		 3241 goto err_stop;
3242 }
3243
3244 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3245 goto err_stop;
3246
3247 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3248
3249 frags = rtl8169_xmit_frags(tp, skb, opts1);
3250 if (frags) {
3251 len = skb_headlen(skb);
3252 opts1 |= FirstFrag;
3253 } else {
3254 len = skb->len;
1da177e4
LT		 3255 opts1 |= FirstFrag | LastFrag;
3256 tp->tx_skb[entry].skb = skb;
3257 }
3258
3259 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3260
3261 tp->tx_skb[entry].len = len;
3262 txd->addr = cpu_to_le64(mapping);
3263 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3264
3265 wmb();
3266
3267 /* anti gcc 2.95.3 bugware (sic) */
3268 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3269 txd->opts1 = cpu_to_le32(status);
3270
3271 dev->trans_start = jiffies;
3272
3273 tp->cur_tx += frags + 1;
3274
3275 smp_wmb();
3276
275391a4 3277 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 3278
3279 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3280 netif_stop_queue(dev);
3281 smp_rmb();
3282 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3283 netif_wake_queue(dev);
3284 }
3285
3286out:
3287 return ret;
3288
3289err_stop:
3290 netif_stop_queue(dev);
188f4af0 3291 ret = NETDEV_TX_BUSY;
cebf8cc7 3292 dev->stats.tx_dropped++;
1da177e4
LT		 3293 goto out;
3294}
3295
3296static void rtl8169_pcierr_interrupt(struct net_device *dev)
3297{
3298 struct rtl8169_private *tp = netdev_priv(dev);
3299 struct pci_dev *pdev = tp->pci_dev;
3300 void __iomem *ioaddr = tp->mmio_addr;
3301 u16 pci_status, pci_cmd;
3302
3303 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3304 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3305
b57b7e5a
SH		 3306 if (netif_msg_intr(tp)) {
3307 printk(KERN_ERR
3308 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3309 dev->name, pci_cmd, pci_status);
3310 }
1da177e4
LT		 3311
3312 /*
3313 * The recovery sequence below admits a very elaborated explanation:
3314 * - it seems to work;
d03902b8
FR		 3315 * - I did not see what else could be done;
3316 * - it makes iop3xx happy.
1da177e4
LT		 3317 *
3318 * Feel free to adjust to your needs.
3319 */
a27993f3 3320 if (pdev->broken_parity_status)
d03902b8
FR		 3321 pci_cmd &= ~PCI_COMMAND_PARITY;
3322 else
3323 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3324
3325 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 3326
3327 pci_write_config_word(pdev, PCI_STATUS,
3328 pci_status & (PCI_STATUS_DETECTED_PARITY |
3329 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3330 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3331
3332 /* The infamous DAC f*ckup only happens at boot time */
3333 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 3334 if (netif_msg_intr(tp))
3335 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 3336 tp->cp_cmd &= ~PCIDAC;
3337 RTL_W16(CPlusCmd, tp->cp_cmd);
3338 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 3339 }
3340
3341 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 3342
3343 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 3344}
3345
07d3f51f
FR		 3346static void rtl8169_tx_interrupt(struct net_device *dev,
3347 struct rtl8169_private *tp,
3348 void __iomem *ioaddr)
1da177e4
LT		 3349{
3350 unsigned int dirty_tx, tx_left;
3351
1da177e4
LT		 3352 dirty_tx = tp->dirty_tx;
3353 smp_rmb();
3354 tx_left = tp->cur_tx - dirty_tx;
3355
3356 while (tx_left > 0) {
3357 unsigned int entry = dirty_tx % NUM_TX_DESC;
3358 struct ring_info *tx_skb = tp->tx_skb + entry;
3359 u32 len = tx_skb->len;
3360 u32 status;
3361
3362 rmb();
3363 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3364 if (status & DescOwn)
3365 break;
3366
cebf8cc7
FR		 3367 dev->stats.tx_bytes += len;
3368 dev->stats.tx_packets++;
1da177e4
LT		 3369
3370 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3371
3372 if (status & LastFrag) {
3373 dev_kfree_skb_irq(tx_skb->skb);
3374 tx_skb->skb = NULL;
3375 }
3376 dirty_tx++;
3377 tx_left--;
3378 }
3379
3380 if (tp->dirty_tx != dirty_tx) {
3381 tp->dirty_tx = dirty_tx;
3382 smp_wmb();
3383 if (netif_queue_stopped(dev) &&
3384 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3385 netif_wake_queue(dev);
3386 }
d78ae2dc
FR		 3387 /*
3388 * 8168 hack: TxPoll requests are lost when the Tx packets are
3389 * too close. Let's kick an extra TxPoll request when a burst
3390 * of start_xmit activity is detected (if it is not detected,
3391 * it is slow enough). -- FR
3392 */
3393 smp_rmb();
3394 if (tp->cur_tx != dirty_tx)
3395 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3396 }
3397}
3398
126fa4b9
FR		 3399static inline int rtl8169_fragmented_frame(u32 status)
3400{
3401 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3402}
3403
1da177e4
LT		 3404static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3405{
3406 u32 opts1 = le32_to_cpu(desc->opts1);
3407 u32 status = opts1 & RxProtoMask;
3408
3409 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3410 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3411 ((status == RxProtoIP) && !(opts1 & IPFail)))
3412 skb->ip_summed = CHECKSUM_UNNECESSARY;
3413 else
3414 skb->ip_summed = CHECKSUM_NONE;
3415}
3416
07d3f51f
FR		 3417static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3418 struct rtl8169_private *tp, int pkt_size,
3419 dma_addr_t addr)
1da177e4 3420{
b449655f
SH		 3421 struct sk_buff *skb;
3422 bool done = false;
1da177e4 3423
b449655f
SH		 3424 if (pkt_size >= rx_copybreak)
3425 goto out;
1da177e4 3426
07d3f51f 3427 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3428 if (!skb)
3429 goto out;
3430
07d3f51f
FR		 3431 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3432 PCI_DMA_FROMDEVICE);
86402234 3433 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3434 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3435 *sk_buff = skb;
3436 done = true;
3437out:
3438 return done;
1da177e4
LT		 3439}
3440
07d3f51f
FR		 3441static int rtl8169_rx_interrupt(struct net_device *dev,
3442 struct rtl8169_private *tp,
bea3348e 3443 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3444{
3445 unsigned int cur_rx, rx_left;
3446 unsigned int delta, count;
3447
1da177e4
LT		 3448 cur_rx = tp->cur_rx;
3449 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3450 rx_left = min(rx_left, budget);
1da177e4 3451
4dcb7d33 3452 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3453 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3454 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3455 u32 status;
3456
3457 rmb();
126fa4b9 3458 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3459
3460 if (status & DescOwn)
3461 break;
4dcb7d33 3462 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3463 if (netif_msg_rx_err(tp)) {
3464 printk(KERN_INFO
3465 "%s: Rx ERROR. status = %08x\n",
3466 dev->name, status);
3467 }
cebf8cc7 3468 dev->stats.rx_errors++;
1da177e4 3469 if (status & (RxRWT | RxRUNT))
cebf8cc7 3470 dev->stats.rx_length_errors++;
1da177e4 3471 if (status & RxCRC)
cebf8cc7 3472 dev->stats.rx_crc_errors++;
9dccf611
FR		 3473 if (status & RxFOVF) {
3474 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3475 dev->stats.rx_fifo_errors++;
9dccf611 3476 }
126fa4b9 3477 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3478 } else {
1da177e4 3479 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3480 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3481 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3482 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3483
126fa4b9
FR		 3484 /*
3485 * The driver does not support incoming fragmented
3486 * frames. They are seen as a symptom of over-mtu
3487 * sized frames.
3488 */
3489 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3490 dev->stats.rx_dropped++;
3491 dev->stats.rx_length_errors++;
126fa4b9 3492 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3493 continue;
126fa4b9
FR		 3494 }
3495
1da177e4 3496 rtl8169_rx_csum(skb, desc);
bcf0bf90 3497
07d3f51f 3498 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3499 pci_dma_sync_single_for_device(pdev, addr,
3500 pkt_size, PCI_DMA_FROMDEVICE);
3501 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3502 } else {
a866bbf6 3503 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3504 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3505 tp->Rx_skbuff[entry] = NULL;
3506 }
3507
1da177e4
LT		 3508 skb_put(skb, pkt_size);
3509 skb->protocol = eth_type_trans(skb, dev);
3510
3511 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3512 netif_receive_skb(skb);
1da177e4 3513
cebf8cc7
FR		 3514 dev->stats.rx_bytes += pkt_size;
3515 dev->stats.rx_packets++;
1da177e4 3516 }
6dccd16b
FR		 3517
3518 /* Work around for AMD plateform. */
95e0918d 3519 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3520 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3521 desc->opts2 = 0;
3522 cur_rx++;
3523 }
1da177e4
LT		 3524 }
3525
3526 count = cur_rx - tp->cur_rx;
3527 tp->cur_rx = cur_rx;
3528
3529 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3530 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3531 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3532 tp->dirty_rx += delta;
3533
3534 /*
3535 * FIXME: until there is periodic timer to try and refill the ring,
3536 * a temporary shortage may definitely kill the Rx process.
3537 * - disable the asic to try and avoid an overflow and kick it again
3538 * after refill ?
3539 * - how do others driver handle this condition (Uh oh...).
3540 */
b57b7e5a 3541 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3542 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3543
3544 return count;
3545}
3546
07d3f51f 3547static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3548{
07d3f51f 3549 struct net_device *dev = dev_instance;
1da177e4 3550 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3551 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3552 int handled = 0;
865c652d 3553 int status;
1da177e4 3554
865c652d 3555 status = RTL_R16(IntrStatus);
1da177e4 3556
865c652d
FR		 3557 /* hotplug/major error/no more work/shared irq */
3558 if ((status == 0xffff) || !status)
3559 goto out;
1da177e4 3560
865c652d 3561 handled = 1;
1da177e4 3562
865c652d
FR		 3563 if (unlikely(!netif_running(dev))) {
3564 rtl8169_asic_down(ioaddr);
3565 goto out;
3566 }
1da177e4 3567
865c652d
FR		 3568 status &= tp->intr_mask;
3569 RTL_W16(IntrStatus,
3570 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 3571
865c652d
FR		 3572 if (!(status & tp->intr_event))
3573 goto out;
0e485150 3574
865c652d
FR		 3575 /* Work around for rx fifo overflow */
3576 if (unlikely(status & RxFIFOOver) &&
3577 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3578 netif_stop_queue(dev);
3579 rtl8169_tx_timeout(dev);
3580 goto out;
3581 }
1da177e4 3582
865c652d
FR		 3583 if (unlikely(status & SYSErr)) {
3584 rtl8169_pcierr_interrupt(dev);
3585 goto out;
3586 }
1da177e4 3587
865c652d
FR		 3588 if (status & LinkChg)
3589 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 3590
865c652d
FR		 3591 if (status & tp->napi_event) {
3592 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3593 tp->intr_mask = ~tp->napi_event;
313b0305 3594
288379f0
BH		 3595 if (likely(napi_schedule_prep(&tp->napi)))
3596 __napi_schedule(&tp->napi);
865c652d
FR		 3597 else if (netif_msg_intr(tp)) {
3598 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3599 dev->name, status);
b57b7e5a 3600 }
1da177e4
LT		 3601 }
3602out:
3603 return IRQ_RETVAL(handled);
3604}
3605
bea3348e 3606static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3607{
bea3348e
SH		 3608 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3609 struct net_device *dev = tp->dev;
1da177e4 3610 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3611 int work_done;
1da177e4 3612
bea3348e 3613 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3614 rtl8169_tx_interrupt(dev, tp, ioaddr);
3615
bea3348e 3616 if (work_done < budget) {
288379f0 3617 napi_complete(napi);
1da177e4
LT		 3618 tp->intr_mask = 0xffff;
3619 /*
3620 * 20040426: the barrier is not strictly required but the
3621 * behavior of the irq handler could be less predictable
3622 * without it. Btw, the lack of flush for the posted pci
3623 * write is safe - FR
3624 */
3625 smp_wmb();
0e485150 3626 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3627 }
3628
bea3348e 3629 return work_done;
1da177e4 3630}
1da177e4 3631
523a6094
FR		 3632static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3633{
3634 struct rtl8169_private *tp = netdev_priv(dev);
3635
3636 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3637 return;
3638
3639 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3640 RTL_W32(RxMissed, 0);
3641}
3642
1da177e4
LT		 3643static void rtl8169_down(struct net_device *dev)
3644{
3645 struct rtl8169_private *tp = netdev_priv(dev);
3646 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3647 unsigned int intrmask;
1da177e4
LT		 3648
3649 rtl8169_delete_timer(dev);
3650
3651 netif_stop_queue(dev);
3652
93dd79e8 3653 napi_disable(&tp->napi);
93dd79e8 3654
1da177e4
LT		 3655core_down:
3656 spin_lock_irq(&tp->lock);
3657
3658 rtl8169_asic_down(ioaddr);
3659
523a6094 3660 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3661
3662 spin_unlock_irq(&tp->lock);
3663
3664 synchronize_irq(dev->irq);
3665
1da177e4 3666 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3667 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3668
3669 /*
3670 * And now for the 50k$ question: are IRQ disabled or not ?
3671 *
3672 * Two paths lead here:
3673 * 1) dev->close
3674 * -> netif_running() is available to sync the current code and the
3675 * IRQ handler. See rtl8169_interrupt for details.
3676 * 2) dev->change_mtu
3677 * -> rtl8169_poll can not be issued again and re-enable the
3678 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3679 *
3680 * No loop if hotpluged or major error (0xffff).
1da177e4 3681 */
733b736c
AP		 3682 intrmask = RTL_R16(IntrMask);
3683 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3684 goto core_down;
3685
3686 rtl8169_tx_clear(tp);
3687
3688 rtl8169_rx_clear(tp);
3689}
3690
3691static int rtl8169_close(struct net_device *dev)
3692{
3693 struct rtl8169_private *tp = netdev_priv(dev);
3694 struct pci_dev *pdev = tp->pci_dev;
3695
355423d0
IV		 3696 /* update counters before going down */
3697 rtl8169_update_counters(dev);
3698
1da177e4
LT		 3699 rtl8169_down(dev);
3700
3701 free_irq(dev->irq, dev);
3702
1da177e4
LT		 3703 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3704 tp->RxPhyAddr);
3705 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3706 tp->TxPhyAddr);
3707 tp->TxDescArray = NULL;
3708 tp->RxDescArray = NULL;
3709
3710 return 0;
3711}
3712
07ce4064 3713static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3714{
3715 struct rtl8169_private *tp = netdev_priv(dev);
3716 void __iomem *ioaddr = tp->mmio_addr;
3717 unsigned long flags;
3718 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3719 int rx_mode;
1da177e4
LT		 3720 u32 tmp = 0;
3721
3722 if (dev->flags & IFF_PROMISC) {
3723 /* Unconditionally log net taps. */
b57b7e5a
SH		 3724 if (netif_msg_link(tp)) {
3725 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3726 dev->name);
3727 }
1da177e4
LT		 3728 rx_mode =
3729 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3730 AcceptAllPhys;
3731 mc_filter[1] = mc_filter[0] = 0xffffffff;
3732 } else if ((dev->mc_count > multicast_filter_limit)
3733 || (dev->flags & IFF_ALLMULTI)) {
3734 /* Too many to filter perfectly -- accept all multicasts. */
3735 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3736 mc_filter[1] = mc_filter[0] = 0xffffffff;
3737 } else {
3738 struct dev_mc_list *mclist;
07d3f51f
FR		 3739 unsigned int i;
3740
1da177e4
LT		 3741 rx_mode = AcceptBroadcast | AcceptMyPhys;
3742 mc_filter[1] = mc_filter[0] = 0;
3743 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3744 i++, mclist = mclist->next) {
3745 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3746 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3747 rx_mode |= AcceptMulticast;
3748 }
3749 }
3750
3751 spin_lock_irqsave(&tp->lock, flags);
3752
3753 tmp = rtl8169_rx_config | rx_mode |
3754 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3755
f887cce8 3756 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3757 u32 data = mc_filter[0];
3758
3759 mc_filter[0] = swab32(mc_filter[1]);
3760 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3761 }
3762
1da177e4
LT		 3763 RTL_W32(MAR0 + 0, mc_filter[0]);
3764 RTL_W32(MAR0 + 4, mc_filter[1]);
3765
57a9f236
FR		 3766 RTL_W32(RxConfig, tmp);
3767
1da177e4
LT		 3768 spin_unlock_irqrestore(&tp->lock, flags);
3769}
3770
3771/**
3772 * rtl8169_get_stats - Get rtl8169 read/write statistics
3773 * @dev: The Ethernet Device to get statistics for
3774 *
3775 * Get TX/RX statistics for rtl8169
3776 */
3777static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3778{
3779 struct rtl8169_private *tp = netdev_priv(dev);
3780 void __iomem *ioaddr = tp->mmio_addr;
3781 unsigned long flags;
3782
3783 if (netif_running(dev)) {
3784 spin_lock_irqsave(&tp->lock, flags);
523a6094 3785 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3786 spin_unlock_irqrestore(&tp->lock, flags);
3787 }
5b0384f4 3788
cebf8cc7 3789 return &dev->stats;
1da177e4
LT		 3790}
3791
861ab440 3792static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 3793{
5d06a99f
FR		 3794 struct rtl8169_private *tp = netdev_priv(dev);
3795 void __iomem *ioaddr = tp->mmio_addr;
3796
3797 if (!netif_running(dev))
861ab440 3798 return;
5d06a99f
FR		 3799
3800 netif_device_detach(dev);
3801 netif_stop_queue(dev);
3802
3803 spin_lock_irq(&tp->lock);
3804
3805 rtl8169_asic_down(ioaddr);
3806
523a6094 3807 rtl8169_rx_missed(dev, ioaddr);
5d06a99f
FR		 3808
3809 spin_unlock_irq(&tp->lock);
861ab440
RW		 3810}
3811
3812#ifdef CONFIG_PM
3813
3814static int rtl8169_suspend(struct device *device)
3815{
3816 struct pci_dev *pdev = to_pci_dev(device);
3817 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 3818
861ab440 3819 rtl8169_net_suspend(dev);
1371fa6d 3820
5d06a99f
FR		 3821 return 0;
3822}
3823
861ab440 3824static int rtl8169_resume(struct device *device)
5d06a99f 3825{
861ab440 3826 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f
FR		 3827 struct net_device *dev = pci_get_drvdata(pdev);
3828
3829 if (!netif_running(dev))
3830 goto out;
3831
3832 netif_device_attach(dev);
3833
5d06a99f
FR		 3834 rtl8169_schedule_work(dev, rtl8169_reset_task);
3835out:
3836 return 0;
3837}
3838
861ab440
RW		 3839static struct dev_pm_ops rtl8169_pm_ops = {
3840 .suspend = rtl8169_suspend,
3841 .resume = rtl8169_resume,
3842 .freeze = rtl8169_suspend,
3843 .thaw = rtl8169_resume,
3844 .poweroff = rtl8169_suspend,
3845 .restore = rtl8169_resume,
3846};
3847
3848#define RTL8169_PM_OPS (&rtl8169_pm_ops)
3849
3850#else /* !CONFIG_PM */
3851
3852#define RTL8169_PM_OPS NULL
3853
3854#endif /* !CONFIG_PM */
3855
1765f95d
FR		 3856static void rtl_shutdown(struct pci_dev *pdev)
3857{
861ab440
RW		 3858 struct net_device *dev = pci_get_drvdata(pdev);
3859
3860 rtl8169_net_suspend(dev);
1765f95d 3861
861ab440
RW		 3862 if (system_state == SYSTEM_POWER_OFF) {
3863 pci_wake_from_d3(pdev, true);
3864 pci_set_power_state(pdev, PCI_D3hot);
3865 }
3866}
5d06a99f 3867
1da177e4
LT		 3868static struct pci_driver rtl8169_pci_driver = {
3869 .name = MODULENAME,
3870 .id_table = rtl8169_pci_tbl,
3871 .probe = rtl8169_init_one,
3872 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 3873 .shutdown = rtl_shutdown,
861ab440 3874 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 3875};
3876
07d3f51f 3877static int __init rtl8169_init_module(void)
1da177e4 3878{
29917620 3879 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3880}
3881
07d3f51f 3882static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3883{
3884 pci_unregister_driver(&rtl8169_pci_driver);
3885}
3886
3887module_init(rtl8169_init_module);
3888module_exit(rtl8169_cleanup_module);
Linux kernel - Deliverables
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