[deliverable/linux.git] / drivers / net / r8169.c

/*
=========================================================================
 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
 --------------------------------------------------------------------

 History:
 Feb  4 2002	- created initially by ShuChen <shuchen@realtek.com.tw>.
 May 20 2002	- Add link status force-mode and TBI mode support.
	2004	- Massive updates. See kernel SCM system for details.
=========================================================================
VERSION 1.1	<2002/10/4>

	The bit4:0 of MII register 4 is called "selector field", and have to be
	00001b to indicate support of IEEE std 802.3 during NWay process of
	exchanging Link Code Word (FLP).

VERSION 1.2	<2002/11/30>

	- Large style cleanup
	- Use ether_crc in stock kernel (linux/crc32.h)
	- Copy mc_filter setup code from 8139cp
	  (includes an optimization, and avoids set_bit use)

VERSION 1.6LK	<2004/04/14>

	- Merge of Realtek's version 1.6
	- Conversion to DMA API
	- Suspend/resume
	- Endianness
	- Misc Rx/Tx bugs

VERSION 2.2LK	<2005/01/25>

	- RX csum, TX csum/SG, TSO
	- VLAN
	- baby (< 7200) Jumbo frames support
	- Merge of Realtek's version 2.2 (new phy)
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>

#include <asm/system.h>
#include <asm/io.h>
#include <asm/irq.h>

#ifdef CONFIG_R8169_NAPI
#define NAPI_SUFFIX	"-NAPI"
#else
#define NAPI_SUFFIX	""
#endif

#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
#define MODULENAME "r8169"
#define PFX MODULENAME ": "

#ifdef RTL8169_DEBUG
#define assert(expr) \
	if (!(expr)) {					\
		printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
		#expr,__FILE__,__FUNCTION__,__LINE__);		\
	}
#define dprintk(fmt, args...)	do { printk(PFX fmt, ## args); } while (0)
#else
#define assert(expr) do {} while (0)
#define dprintk(fmt, args...)	do {} while (0)
#endif /* RTL8169_DEBUG */

#define R8169_MSG_DEFAULT \
	(NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)

#define TX_BUFFS_AVAIL(tp) \
	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)

#ifdef CONFIG_R8169_NAPI
#define rtl8169_rx_skb			netif_receive_skb
#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_receive_skb
#define rtl8169_rx_quota(count, quota)	min(count, quota)
#else
#define rtl8169_rx_skb			netif_rx
#define rtl8169_rx_hwaccel_skb		vlan_hwaccel_rx
#define rtl8169_rx_quota(count, quota)	count
#endif

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
static const int max_interrupt_work = 20;

/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   The RTL chips use a 64 element hash table based on the Ethernet CRC. */
static const int multicast_filter_limit = 32;

/* MAC address length */
#define MAC_ADDR_LEN	6

#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */
#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
#define EarlyTxThld 	0x3F	/* 0x3F means NO early transmit */
#define RxPacketMaxSize	0x3FE8	/* 16K - 1 - ETH_HLEN - VLAN - CRC... */
#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */
#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */

#define R8169_REGS_SIZE		256
#define R8169_NAPI_WEIGHT	64
#define NUM_TX_DESC	64	/* Number of Tx descriptor registers */
#define NUM_RX_DESC	256	/* Number of Rx descriptor registers */
#define RX_BUF_SIZE	1536	/* Rx Buffer size */
#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))

#define RTL8169_TX_TIMEOUT	(6*HZ)
#define RTL8169_PHY_TIMEOUT	(10*HZ)

/* write/read MMIO register */
#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
#define RTL_R8(reg)		readb (ioaddr + (reg))
#define RTL_R16(reg)		readw (ioaddr + (reg))
#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))

enum mac_version {
	RTL_GIGA_MAC_VER_01 = 0x01, // 8169
	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
	RTL_GIGA_MAC_VER_15 = 0x0f  // 8101
};

enum phy_version {
	RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
	RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
	RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
};

#define _R(NAME,MAC,MASK) \
	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }

static const struct {
	const char *name;
	u8 mac_version;
	u32 RxConfigMask;	/* Clears the bits supported by this chip */
} rtl_chip_info[] = {
	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
};
#undef _R

enum cfg_version {
	RTL_CFG_0 = 0x00,
	RTL_CFG_1,
	RTL_CFG_2
};

static void rtl_hw_start_8169(struct net_device *);
static void rtl_hw_start_8168(struct net_device *);
static void rtl_hw_start_8101(struct net_device *);

static struct pci_device_id rtl8169_pci_tbl[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },
	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
Commit	Line	Data
1da177e4 LT	1	/*
	2	=========================================================================
	3	r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
	4	--------------------------------------------------------------------
	5
	6	History:
	7	Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
	8	May 20 2002 - Add link status force-mode and TBI mode support.
5b0384f4	9	2004 - Massive updates. See kernel SCM system for details.
1da177e4 LT	10	=========================================================================
	11	VERSION 1.1 <2002/10/4>
	12
	13	The bit4:0 of MII register 4 is called "selector field", and have to be
	14	00001b to indicate support of IEEE std 802.3 during NWay process of
5b0384f4	15	exchanging Link Code Word (FLP).
1da177e4 LT	16
	17	VERSION 1.2 <2002/11/30>
	18
	19	- Large style cleanup
	20	- Use ether_crc in stock kernel (linux/crc32.h)
	21	- Copy mc_filter setup code from 8139cp
	22	(includes an optimization, and avoids set_bit use)
	23
	24	VERSION 1.6LK <2004/04/14>
	25
	26	- Merge of Realtek's version 1.6
	27	- Conversion to DMA API
	28	- Suspend/resume
	29	- Endianness
	30	- Misc Rx/Tx bugs
	31
	32	VERSION 2.2LK <2005/01/25>
	33
	34	- RX csum, TX csum/SG, TSO
	35	- VLAN
	36	- baby (< 7200) Jumbo frames support
	37	- Merge of Realtek's version 2.2 (new phy)
	38	*/
	39
	40	#include <linux/module.h>
	41	#include <linux/moduleparam.h>
	42	#include <linux/pci.h>
	43	#include <linux/netdevice.h>
	44	#include <linux/etherdevice.h>
	45	#include <linux/delay.h>
	46	#include <linux/ethtool.h>
	47	#include <linux/mii.h>
	48	#include <linux/if_vlan.h>
	49	#include <linux/crc32.h>
	50	#include <linux/in.h>
	51	#include <linux/ip.h>
	52	#include <linux/tcp.h>
	53	#include <linux/init.h>
	54	#include <linux/dma-mapping.h>
	55
99f252b0	56	#include <asm/system.h>
1da177e4 LT	57	#include <asm/io.h>
	58	#include <asm/irq.h>
	59
f7ccf420 SH	60	#ifdef CONFIG_R8169_NAPI
	61	#define NAPI_SUFFIX "-NAPI"
	62	#else
	63	#define NAPI_SUFFIX ""
	64	#endif
	65
	66	#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4 LT	67	#define MODULENAME "r8169"
	68	#define PFX MODULENAME ": "
	69
	70	#ifdef RTL8169_DEBUG
	71	#define assert(expr) \
5b0384f4 FR	72	if (!(expr)) { \
	73	printk( "Assertion failed! %s,%s,%s,line=%d\n", \
	74	#expr,__FILE__,__FUNCTION__,__LINE__); \
	75	}
1da177e4 LT	76	#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
	77	#else
	78	#define assert(expr) do {} while (0)
	79	#define dprintk(fmt, args...) do {} while (0)
	80	#endif /* RTL8169_DEBUG */
	81
b57b7e5a	82	#define R8169_MSG_DEFAULT \
f0e837d9	83	(NETIF_MSG_DRV \| NETIF_MSG_PROBE \| NETIF_MSG_IFUP \| NETIF_MSG_IFDOWN)
b57b7e5a	84
1da177e4 LT	85	#define TX_BUFFS_AVAIL(tp) \
	86	(tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
	87
	88	#ifdef CONFIG_R8169_NAPI
	89	#define rtl8169_rx_skb netif_receive_skb
0b50f81d	90	#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4 LT	91	#define rtl8169_rx_quota(count, quota) min(count, quota)
	92	#else
	93	#define rtl8169_rx_skb netif_rx
0b50f81d	94	#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4 LT	95	#define rtl8169_rx_quota(count, quota) count
	96	#endif
	97
1da177e4	98	/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309	99	static const int max_interrupt_work = 20;
1da177e4 LT	100
	101	/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
	102	The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309	103	static const int multicast_filter_limit = 32;
1da177e4 LT	104
	105	/* MAC address length */
	106	#define MAC_ADDR_LEN 6
	107
	108	#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
	109	#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
	110	#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
	111	#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
	112	#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
	113	#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
	114	#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
	115
	116	#define R8169_REGS_SIZE 256
	117	#define R8169_NAPI_WEIGHT 64
	118	#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
	119	#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
	120	#define RX_BUF_SIZE 1536 /* Rx Buffer size */
	121	#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
	122	#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
	123
	124	#define RTL8169_TX_TIMEOUT (6*HZ)
	125	#define RTL8169_PHY_TIMEOUT (10*HZ)
	126
	127	/* write/read MMIO register */
	128	#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
	129	#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
	130	#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
	131	#define RTL_R8(reg) readb (ioaddr + (reg))
	132	#define RTL_R16(reg) readw (ioaddr + (reg))
	133	#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
	134
	135	enum mac_version {
ba6eb6ee FR	136	RTL_GIGA_MAC_VER_01 = 0x01, // 8169
	137	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
	138	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
	139	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
	140	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b	141	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 FR	142	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
2dd99530 FR	143	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608 FR	144	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
	145	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
	146	RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4 LT	147	};
	148
	149	enum phy_version {
	150	RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	151	RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	152	RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
	153	RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
	154	RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
	155	RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
	156	};
	157
1da177e4 LT	158	#define _R(NAME,MAC,MASK) \
	159	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
	160
3c6bee1d	161	static const struct {
1da177e4 LT	162	const char *name;
	163	u8 mac_version;
	164	u32 RxConfigMask; /* Clears the bits supported by this chip */
	165	} rtl_chip_info[] = {
ba6eb6ee FR	166	_R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
	167	_R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
	168	_R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
	169	_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
	170	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b	171	_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90 FR	172	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
	173	_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
	174	_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
	175	_R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
	176	_R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4 LT	177	};
	178	#undef _R
	179
bcf0bf90 FR	180	enum cfg_version {
	181	RTL_CFG_0 = 0x00,
	182	RTL_CFG_1,
	183	RTL_CFG_2
	184	};
	185
07ce4064 FR	186	static void rtl_hw_start_8169(struct net_device *);
	187	static void rtl_hw_start_8168(struct net_device *);
	188	static void rtl_hw_start_8101(struct net_device *);
	189
1da177e4	190	static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90	191	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf	192	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551	193	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064	194	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90 FR	195	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
bcf0bf90 FR	196	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },