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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq
[deliverable/linux.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4 27 * The module loadable parameters that are supported by the driver and a brief
a2a20aef 28 * explanation of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
6cef2b8e
JP		 57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
1da177e4
LT		 59#include <linux/module.h>
60#include <linux/types.h>
61#include <linux/errno.h>
62#include <linux/ioport.h>
63#include <linux/pci.h>
1e7f0bd8 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/kernel.h>
66#include <linux/netdevice.h>
67#include <linux/etherdevice.h>
40239396 68#include <linux/mdio.h>
1da177e4
LT		 69#include <linux/skbuff.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/stddef.h>
73#include <linux/ioctl.h>
74#include <linux/timex.h>
1da177e4 75#include <linux/ethtool.h>
1da177e4 76#include <linux/workqueue.h>
be3a6b02 77#include <linux/if_vlan.h>
7d3d0439
RA		 78#include <linux/ip.h>
79#include <linux/tcp.h>
d44570e4
JP		 80#include <linux/uaccess.h>
81#include <linux/io.h>
5a0e3ad6 82#include <linux/slab.h>
7d3d0439 83#include <net/tcp.h>
1da177e4 84
1da177e4 85#include <asm/system.h>
fe931395 86#include <asm/div64.h>
330ce0de 87#include <asm/irq.h>
1da177e4
LT		 88
89/* local include */
90#include "s2io.h"
91#include "s2io-regs.h"
92
29d0a2b0 93#define DRV_VERSION "2.0.26.25"
6c1792f4 94
1da177e4 95/* S2io Driver name & version. */
20346722 96static char s2io_driver_name[] = "Neterion";
6c1792f4 97static char s2io_driver_version[] = DRV_VERSION;
1da177e4 98
d44570e4
JP		 99static int rxd_size[2] = {32, 48};
100static int rxd_count[2] = {127, 85};
da6971d8 101
1ee6dd77 102static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd 103{
104 int ret;
105
106 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 107 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd 108
109 return ret;
110}
111
20346722 112/*
1da177e4
LT		 113 * Cards with following subsystem_id have a link state indication
114 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
115 * macro below identifies these cards given the subsystem_id.
116 */
d44570e4
JP		 117#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
118 (dev_type == XFRAME_I_DEVICE) ? \
119 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
120 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 121
122#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
123 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 124
d44570e4 125static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 126{
127 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
128}
129
1da177e4 130/* Ethtool related variables and Macros. */
6fce365d 131static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 132 "Register test\t(offline)",
133 "Eeprom test\t(offline)",
134 "Link test\t(online)",
135 "RLDRAM test\t(offline)",
136 "BIST Test\t(offline)"
137};
138
6fce365d 139static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 140 {"tmac_frms"},
141 {"tmac_data_octets"},
142 {"tmac_drop_frms"},
143 {"tmac_mcst_frms"},
144 {"tmac_bcst_frms"},
145 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 146 {"tmac_ttl_octets"},
147 {"tmac_ucst_frms"},
148 {"tmac_nucst_frms"},
1da177e4 149 {"tmac_any_err_frms"},
bd1034f0 150 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 151 {"tmac_vld_ip_octets"},
152 {"tmac_vld_ip"},
153 {"tmac_drop_ip"},
154 {"tmac_icmp"},
155 {"tmac_rst_tcp"},
156 {"tmac_tcp"},
157 {"tmac_udp"},
158 {"rmac_vld_frms"},
159 {"rmac_data_octets"},
160 {"rmac_fcs_err_frms"},
161 {"rmac_drop_frms"},
162 {"rmac_vld_mcst_frms"},
163 {"rmac_vld_bcst_frms"},
164 {"rmac_in_rng_len_err_frms"},
bd1034f0 165 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 166 {"rmac_long_frms"},
167 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 168 {"rmac_unsup_ctrl_frms"},
169 {"rmac_ttl_octets"},
170 {"rmac_accepted_ucst_frms"},
171 {"rmac_accepted_nucst_frms"},
1da177e4 172 {"rmac_discarded_frms"},
bd1034f0
AR		 173 {"rmac_drop_events"},
174 {"rmac_ttl_less_fb_octets"},
175 {"rmac_ttl_frms"},
1da177e4
LT		 176 {"rmac_usized_frms"},
177 {"rmac_osized_frms"},
178 {"rmac_frag_frms"},
179 {"rmac_jabber_frms"},
bd1034f0
AR		 180 {"rmac_ttl_64_frms"},
181 {"rmac_ttl_65_127_frms"},
182 {"rmac_ttl_128_255_frms"},
183 {"rmac_ttl_256_511_frms"},
184 {"rmac_ttl_512_1023_frms"},
185 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 186 {"rmac_ip"},
187 {"rmac_ip_octets"},
188 {"rmac_hdr_err_ip"},
189 {"rmac_drop_ip"},
190 {"rmac_icmp"},
191 {"rmac_tcp"},
192 {"rmac_udp"},
193 {"rmac_err_drp_udp"},
bd1034f0
AR		 194 {"rmac_xgmii_err_sym"},
195 {"rmac_frms_q0"},
196 {"rmac_frms_q1"},
197 {"rmac_frms_q2"},
198 {"rmac_frms_q3"},
199 {"rmac_frms_q4"},
200 {"rmac_frms_q5"},
201 {"rmac_frms_q6"},
202 {"rmac_frms_q7"},
203 {"rmac_full_q0"},
204 {"rmac_full_q1"},
205 {"rmac_full_q2"},
206 {"rmac_full_q3"},
207 {"rmac_full_q4"},
208 {"rmac_full_q5"},
209 {"rmac_full_q6"},
210 {"rmac_full_q7"},
1da177e4 211 {"rmac_pause_cnt"},
bd1034f0
AR		 212 {"rmac_xgmii_data_err_cnt"},
213 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 214 {"rmac_accepted_ip"},
215 {"rmac_err_tcp"},
bd1034f0
AR		 216 {"rd_req_cnt"},
217 {"new_rd_req_cnt"},
218 {"new_rd_req_rtry_cnt"},
219 {"rd_rtry_cnt"},
220 {"wr_rtry_rd_ack_cnt"},
221 {"wr_req_cnt"},
222 {"new_wr_req_cnt"},
223 {"new_wr_req_rtry_cnt"},
224 {"wr_rtry_cnt"},
225 {"wr_disc_cnt"},
226 {"rd_rtry_wr_ack_cnt"},
227 {"txp_wr_cnt"},
228 {"txd_rd_cnt"},
229 {"txd_wr_cnt"},
230 {"rxd_rd_cnt"},
231 {"rxd_wr_cnt"},
232 {"txf_rd_cnt"},
fa1f0cb3
SS		 233 {"rxf_wr_cnt"}
234};
235
6fce365d 236static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 237 {"rmac_ttl_1519_4095_frms"},
238 {"rmac_ttl_4096_8191_frms"},
239 {"rmac_ttl_8192_max_frms"},
240 {"rmac_ttl_gt_max_frms"},
241 {"rmac_osized_alt_frms"},
242 {"rmac_jabber_alt_frms"},
243 {"rmac_gt_max_alt_frms"},
244 {"rmac_vlan_frms"},
245 {"rmac_len_discard"},
246 {"rmac_fcs_discard"},
247 {"rmac_pf_discard"},
248 {"rmac_da_discard"},
249 {"rmac_red_discard"},
250 {"rmac_rts_discard"},
251 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 252 {"link_fault_cnt"}
253};
254
6fce365d 255static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac 256 {"\n DRIVER STATISTICS"},
257 {"single_bit_ecc_errs"},
258 {"double_bit_ecc_errs"},
bd1034f0
AR		 259 {"parity_err_cnt"},
260 {"serious_err_cnt"},
261 {"soft_reset_cnt"},
262 {"fifo_full_cnt"},
8116f3cf
SS		 263 {"ring_0_full_cnt"},
264 {"ring_1_full_cnt"},
265 {"ring_2_full_cnt"},
266 {"ring_3_full_cnt"},
267 {"ring_4_full_cnt"},
268 {"ring_5_full_cnt"},
269 {"ring_6_full_cnt"},
270 {"ring_7_full_cnt"},
43b7c451
SH		 271 {"alarm_transceiver_temp_high"},
272 {"alarm_transceiver_temp_low"},
273 {"alarm_laser_bias_current_high"},
274 {"alarm_laser_bias_current_low"},
275 {"alarm_laser_output_power_high"},
276 {"alarm_laser_output_power_low"},
277 {"warn_transceiver_temp_high"},
278 {"warn_transceiver_temp_low"},
279 {"warn_laser_bias_current_high"},
280 {"warn_laser_bias_current_low"},
281 {"warn_laser_output_power_high"},
282 {"warn_laser_output_power_low"},
283 {"lro_aggregated_pkts"},
284 {"lro_flush_both_count"},
285 {"lro_out_of_sequence_pkts"},
286 {"lro_flush_due_to_max_pkts"},
287 {"lro_avg_aggr_pkts"},
288 {"mem_alloc_fail_cnt"},
289 {"pci_map_fail_cnt"},
290 {"watchdog_timer_cnt"},
291 {"mem_allocated"},
292 {"mem_freed"},
293 {"link_up_cnt"},
294 {"link_down_cnt"},
295 {"link_up_time"},
296 {"link_down_time"},
297 {"tx_tcode_buf_abort_cnt"},
298 {"tx_tcode_desc_abort_cnt"},
299 {"tx_tcode_parity_err_cnt"},
300 {"tx_tcode_link_loss_cnt"},
301 {"tx_tcode_list_proc_err_cnt"},
302 {"rx_tcode_parity_err_cnt"},
303 {"rx_tcode_abort_cnt"},
304 {"rx_tcode_parity_abort_cnt"},
305 {"rx_tcode_rda_fail_cnt"},
306 {"rx_tcode_unkn_prot_cnt"},
307 {"rx_tcode_fcs_err_cnt"},
308 {"rx_tcode_buf_size_err_cnt"},
309 {"rx_tcode_rxd_corrupt_cnt"},
310 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 311 {"tda_err_cnt"},
312 {"pfc_err_cnt"},
313 {"pcc_err_cnt"},
314 {"tti_err_cnt"},
315 {"tpa_err_cnt"},
316 {"sm_err_cnt"},
317 {"lso_err_cnt"},
318 {"mac_tmac_err_cnt"},
319 {"mac_rmac_err_cnt"},
320 {"xgxs_txgxs_err_cnt"},
321 {"xgxs_rxgxs_err_cnt"},
322 {"rc_err_cnt"},
323 {"prc_pcix_err_cnt"},
324 {"rpa_err_cnt"},
325 {"rda_err_cnt"},
326 {"rti_err_cnt"},
327 {"mc_err_cnt"}
1da177e4
LT		 328};
329
4c3616cd
AMR		 330#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
331#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
332#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 333
d44570e4
JP		 334#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
335#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 336
d44570e4
JP		 337#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
338#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 339
4c3616cd 340#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 341#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 342
d44570e4
JP		 343#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
344 init_timer(&timer); \
345 timer.function = handle; \
346 timer.data = (unsigned long)arg; \
347 mod_timer(&timer, (jiffies + exp)) \
25fff88e 348
2fd37688
SS		 349/* copy mac addr to def_mac_addr array */
350static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
351{
352 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
353 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
354 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
355 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
356 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
357 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
358}
04025095 359
be3a6b02 360/* Add the vlan */
361static void s2io_vlan_rx_register(struct net_device *dev,
04025095 362 struct vlan_group *grp)
be3a6b02 363{
2fda096d 364 int i;
4cf1653a 365 struct s2io_nic *nic = netdev_priv(dev);
2fda096d 366 unsigned long flags[MAX_TX_FIFOS];
2fda096d 367 struct config_param *config = &nic->config;
ffb5df6c 368 struct mac_info *mac_control = &nic->mac_control;
2fda096d 369
13d866a9
JP		 370 for (i = 0; i < config->tx_fifo_num; i++) {
371 struct fifo_info *fifo = &mac_control->fifos[i];
372
373 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
374 }
be3a6b02 375
be3a6b02 376 nic->vlgrp = grp;
13d866a9
JP		 377
378 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
379 struct fifo_info *fifo = &mac_control->fifos[i];
380
381 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
382 }
be3a6b02 383}
384
cdb5bf02 385/* Unregister the vlan */
04025095 386static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 387{
388 int i;
4cf1653a 389 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02 390 unsigned long flags[MAX_TX_FIFOS];
cdb5bf02 391 struct config_param *config = &nic->config;
ffb5df6c 392 struct mac_info *mac_control = &nic->mac_control;
cdb5bf02 393
13d866a9
JP		 394 for (i = 0; i < config->tx_fifo_num; i++) {
395 struct fifo_info *fifo = &mac_control->fifos[i];
396
397 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
398 }
cdb5bf02
SH		 399
400 if (nic->vlgrp)
401 vlan_group_set_device(nic->vlgrp, vid, NULL);
402
13d866a9
JP		 403 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
404 struct fifo_info *fifo = &mac_control->fifos[i];
405
406 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
407 }
cdb5bf02
SH		 408}
409
20346722 410/*
1da177e4
LT		 411 * Constants to be programmed into the Xena's registers, to configure
412 * the XAUI.
413 */
414
1da177e4 415#define END_SIGN 0x0
f71e1309 416static const u64 herc_act_dtx_cfg[] = {
541ae68f 417 /* Set address */
e960fc5c 418 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 419 /* Write data */
e960fc5c 420 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 421 /* Set address */
422 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
423 /* Write data */
424 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
425 /* Set address */
e960fc5c 426 0x801205150D440000ULL, 0x801205150D4400E0ULL,
427 /* Write data */
428 0x801205150D440004ULL, 0x801205150D4400E4ULL,
429 /* Set address */
541ae68f 430 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
431 /* Write data */
432 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
433 /* Done */
434 END_SIGN
435};
436
f71e1309 437static const u64 xena_dtx_cfg[] = {
c92ca04b 438 /* Set address */
1da177e4 439 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 440 /* Write data */
441 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
442 /* Set address */
443 0x8001051500000000ULL, 0x80010515000000E0ULL,
444 /* Write data */
445 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
446 /* Set address */
1da177e4 447 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 448 /* Write data */
449 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 450 END_SIGN
451};
452
20346722 453/*
1da177e4
LT		 454 * Constants for Fixing the MacAddress problem seen mostly on
455 * Alpha machines.
456 */
f71e1309 457static const u64 fix_mac[] = {
1da177e4
LT		 458 0x0060000000000000ULL, 0x0060600000000000ULL,
459 0x0040600000000000ULL, 0x0000600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0060600000000000ULL,
470 0x0020600000000000ULL, 0x0000600000000000ULL,
471 0x0040600000000000ULL, 0x0060600000000000ULL,
472 END_SIGN
473};
474
b41477f3
AR		 475MODULE_LICENSE("GPL");
476MODULE_VERSION(DRV_VERSION);
477
478
1da177e4 479/* Module Loadable parameters. */
6cfc482b 480S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 481S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 482S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 483S2IO_PARM_INT(rx_ring_mode, 1);
484S2IO_PARM_INT(use_continuous_tx_intrs, 1);
485S2IO_PARM_INT(rmac_pause_time, 0x100);
486S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
487S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
488S2IO_PARM_INT(shared_splits, 0);
489S2IO_PARM_INT(tmac_util_period, 5);
490S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 491S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 492/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
493S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 494/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 495S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 496/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 497S2IO_PARM_INT(intr_type, 2);
7d3d0439 498/* Large receive offload feature */
43b7c451
SH		 499static unsigned int lro_enable;
500module_param_named(lro, lro_enable, uint, 0);
501
7d3d0439
RA		 502/* Max pkts to be aggregated by LRO at one time. If not specified,
503 * aggregation happens until we hit max IP pkt size(64K)
504 */
b41477f3 505S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 506S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 507
508S2IO_PARM_INT(napi, 1);
509S2IO_PARM_INT(ufo, 0);
926930b2 510S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 511
512static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 513{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 514static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 515{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 516static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 517{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 518
519module_param_array(tx_fifo_len, uint, NULL, 0);
520module_param_array(rx_ring_sz, uint, NULL, 0);
521module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 522
20346722 523/*
1da177e4 524 * S2IO device table.
20346722 525 * This table lists all the devices that this driver supports.
1da177e4 526 */
a3aa1884 527static DEFINE_PCI_DEVICE_TABLE(s2io_tbl) = {
1da177e4
LT		 528 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
529 PCI_ANY_ID, PCI_ANY_ID},
530 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
531 PCI_ANY_ID, PCI_ANY_ID},
532 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 533 PCI_ANY_ID, PCI_ANY_ID},
534 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
535 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 536 {0,}
537};
538
539MODULE_DEVICE_TABLE(pci, s2io_tbl);
540
d796fdb7
LV		 541static struct pci_error_handlers s2io_err_handler = {
542 .error_detected = s2io_io_error_detected,
543 .slot_reset = s2io_io_slot_reset,
544 .resume = s2io_io_resume,
545};
546
1da177e4 547static struct pci_driver s2io_driver = {
d44570e4
JP		 548 .name = "S2IO",
549 .id_table = s2io_tbl,
550 .probe = s2io_init_nic,
551 .remove = __devexit_p(s2io_rem_nic),
552 .err_handler = &s2io_err_handler,
1da177e4
LT		 553};
554
555/* A simplifier macro used both by init and free shared_mem Fns(). */
556#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
557
3a3d5756
SH		 558/* netqueue manipulation helper functions */
559static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
560{
fd2ea0a7
DM		 561 if (!sp->config.multiq) {
562 int i;
563
3a3d5756
SH		 564 for (i = 0; i < sp->config.tx_fifo_num; i++)
565 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 566 }
fd2ea0a7 567 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 568}
569
570static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
571{
fd2ea0a7 572 if (!sp->config.multiq)
3a3d5756
SH		 573 sp->mac_control.fifos[fifo_no].queue_state =
574 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 575
576 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 577}
578
579static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
580{
fd2ea0a7
DM		 581 if (!sp->config.multiq) {
582 int i;
583
3a3d5756
SH		 584 for (i = 0; i < sp->config.tx_fifo_num; i++)
585 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 586 }
fd2ea0a7 587 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 588}
589
590static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
591{
fd2ea0a7 592 if (!sp->config.multiq)
3a3d5756
SH		 593 sp->mac_control.fifos[fifo_no].queue_state =
594 FIFO_QUEUE_START;
fd2ea0a7
DM		 595
596 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 597}
598
599static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
600{
fd2ea0a7
DM		 601 if (!sp->config.multiq) {
602 int i;
603
3a3d5756
SH		 604 for (i = 0; i < sp->config.tx_fifo_num; i++)
605 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 606 }
fd2ea0a7 607 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 608}
609
610static inline void s2io_wake_tx_queue(
611 struct fifo_info *fifo, int cnt, u8 multiq)
612{
613
3a3d5756
SH		 614 if (multiq) {
615 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
616 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 617 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 618 if (netif_queue_stopped(fifo->dev)) {
619 fifo->queue_state = FIFO_QUEUE_START;
620 netif_wake_queue(fifo->dev);
621 }
622 }
623}
624
1da177e4
LT		 625/**
626 * init_shared_mem - Allocation and Initialization of Memory
627 * @nic: Device private variable.
20346722 628 * Description: The function allocates all the memory areas shared
629 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 630 * Rx descriptors and the statistics block.
631 */
632
633static int init_shared_mem(struct s2io_nic *nic)
634{
635 u32 size;
636 void *tmp_v_addr, *tmp_v_addr_next;
637 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 638 struct RxD_block *pre_rxd_blk = NULL;
372cc597 639 int i, j, blk_cnt;
1da177e4
LT		 640 int lst_size, lst_per_page;
641 struct net_device *dev = nic->dev;
8ae418cf 642 unsigned long tmp;
1ee6dd77 643 struct buffAdd *ba;
ffb5df6c
JP		 644 struct config_param *config = &nic->config;
645 struct mac_info *mac_control = &nic->mac_control;
491976b2 646 unsigned long long mem_allocated = 0;
1da177e4 647
13d866a9 648 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 649 size = 0;
650 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 651 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
652
653 size += tx_cfg->fifo_len;
1da177e4
LT		 654 }
655 if (size > MAX_AVAILABLE_TXDS) {
9e39f7c5
JP		 656 DBG_PRINT(ERR_DBG,
657 "Too many TxDs requested: %d, max supported: %d\n",
658 size, MAX_AVAILABLE_TXDS);
b41477f3 659 return -EINVAL;
1da177e4
LT		 660 }
661
2fda096d
SR		 662 size = 0;
663 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 664 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
665
666 size = tx_cfg->fifo_len;
2fda096d
SR		 667 /*
668 * Legal values are from 2 to 8192
669 */
670 if (size < 2) {
9e39f7c5
JP		 671 DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
672 "Valid lengths are 2 through 8192\n",
673 i, size);
2fda096d
SR		 674 return -EINVAL;
675 }
676 }
677
1ee6dd77 678 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 679 lst_per_page = PAGE_SIZE / lst_size;
680
681 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 682 struct fifo_info *fifo = &mac_control->fifos[i];
683 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 685 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 686
687 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688 if (!fifo->list_info) {
d44570e4 689 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 690 return -ENOMEM;
691 }
491976b2 692 mem_allocated += list_holder_size;
1da177e4
LT		 693 }
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
696 lst_per_page);
13d866a9
JP		 697 struct fifo_info *fifo = &mac_control->fifos[i];
698 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
699
700 fifo->tx_curr_put_info.offset = 0;
701 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->tx_curr_get_info.offset = 0;
703 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->fifo_no = i;
705 fifo->nic = nic;
706 fifo->max_txds = MAX_SKB_FRAGS + 2;
707 fifo->dev = dev;
20346722 708
1da177e4
LT		 709 for (j = 0; j < page_num; j++) {
710 int k = 0;
711 dma_addr_t tmp_p;
712 void *tmp_v;
713 tmp_v = pci_alloc_consistent(nic->pdev,
714 PAGE_SIZE, &tmp_p);
715 if (!tmp_v) {
9e39f7c5
JP		 716 DBG_PRINT(INFO_DBG,
717 "pci_alloc_consistent failed for TxDL\n");
1da177e4
LT		 718 return -ENOMEM;
719 }
776bd20f 720 /* If we got a zero DMA address(can happen on
721 * certain platforms like PPC), reallocate.
722 * Store virtual address of page we don't want,
723 * to be freed later.
724 */
725 if (!tmp_p) {
726 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 727 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 728 "%s: Zero DMA address for TxDL. "
729 "Virtual address %p\n",
730 dev->name, tmp_v);
776bd20f 731 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 732 PAGE_SIZE, &tmp_p);
776bd20f 733 if (!tmp_v) {
0c61ed5f 734 DBG_PRINT(INFO_DBG,
9e39f7c5 735 "pci_alloc_consistent failed for TxDL\n");
776bd20f 736 return -ENOMEM;
737 }
491976b2 738 mem_allocated += PAGE_SIZE;
776bd20f 739 }
1da177e4
LT		 740 while (k < lst_per_page) {
741 int l = (j * lst_per_page) + k;
13d866a9 742 if (l == tx_cfg->fifo_len)
20346722 743 break;
13d866a9 744 fifo->list_info[l].list_virt_addr =
d44570e4 745 tmp_v + (k * lst_size);
13d866a9 746 fifo->list_info[l].list_phy_addr =
d44570e4 747 tmp_p + (k * lst_size);
1da177e4
LT		 748 k++;
749 }
750 }
751 }
1da177e4 752
2fda096d 753 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 754 struct fifo_info *fifo = &mac_control->fifos[i];
755 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
756
757 size = tx_cfg->fifo_len;
758 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
759 if (!fifo->ufo_in_band_v)
2fda096d
SR		 760 return -ENOMEM;
761 mem_allocated += (size * sizeof(u64));
762 }
fed5eccd 763
1da177e4
LT		 764 /* Allocation and initialization of RXDs in Rings */
765 size = 0;
766 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 767 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
768 struct ring_info *ring = &mac_control->rings[i];
769
770 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
9e39f7c5
JP		 771 DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
772 "multiple of RxDs per Block\n",
773 dev->name, i);
1da177e4
LT		 774 return FAILURE;
775 }
13d866a9
JP		 776 size += rx_cfg->num_rxd;
777 ring->block_count = rx_cfg->num_rxd /
d44570e4 778 (rxd_count[nic->rxd_mode] + 1);
13d866a9 779 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 780 }
da6971d8 781 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 782 size = (size * (sizeof(struct RxD1)));
da6971d8 783 else
1ee6dd77 784 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 785
786 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 787 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
788 struct ring_info *ring = &mac_control->rings[i];
789
790 ring->rx_curr_get_info.block_index = 0;
791 ring->rx_curr_get_info.offset = 0;
792 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
793 ring->rx_curr_put_info.block_index = 0;
794 ring->rx_curr_put_info.offset = 0;
795 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
796 ring->nic = nic;
797 ring->ring_no = i;
798 ring->lro = lro_enable;
799
800 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 801 /* Allocating all the Rx blocks */
802 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 803 struct rx_block_info *rx_blocks;
da6971d8
AR		 804 int l;
805
13d866a9 806 rx_blocks = &ring->rx_blocks[j];
d44570e4 807 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 808 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
809 &tmp_p_addr);
810 if (tmp_v_addr == NULL) {
811 /*
20346722 812 * In case of failure, free_shared_mem()
813 * is called, which should free any
814 * memory that was alloced till the
1da177e4
LT		 815 * failure happened.
816 */
da6971d8 817 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 818 return -ENOMEM;
819 }
491976b2 820 mem_allocated += size;
1da177e4 821 memset(tmp_v_addr, 0, size);
4f870320
JP		 822
823 size = sizeof(struct rxd_info) *
824 rxd_count[nic->rxd_mode];
da6971d8
AR		 825 rx_blocks->block_virt_addr = tmp_v_addr;
826 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 827 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 828 if (!rx_blocks->rxds)
829 return -ENOMEM;
4f870320 830 mem_allocated += size;
d44570e4 831 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 832 rx_blocks->rxds[l].virt_addr =
833 rx_blocks->block_virt_addr +
834 (rxd_size[nic->rxd_mode] * l);
835 rx_blocks->rxds[l].dma_addr =
836 rx_blocks->block_dma_addr +
837 (rxd_size[nic->rxd_mode] * l);
838 }
1da177e4
LT		 839 }
840 /* Interlinking all Rx Blocks */
841 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 842 int next = (j + 1) % blk_cnt;
843 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
844 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
845 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
846 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 847
d44570e4 848 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
1da177e4 849 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 850 (unsigned long)tmp_v_addr_next;
1da177e4 851 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 852 (u64)tmp_p_addr_next;
1da177e4
LT		 853 }
854 }
6d517a27 855 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 856 /*
857 * Allocation of Storages for buffer addresses in 2BUFF mode
858 * and the buffers as well.
859 */
860 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 861 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
862 struct ring_info *ring = &mac_control->rings[i];
863
864 blk_cnt = rx_cfg->num_rxd /
d44570e4 865 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 866 size = sizeof(struct buffAdd *) * blk_cnt;
867 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 868 if (!ring->ba)
1da177e4 869 return -ENOMEM;
4f870320 870 mem_allocated += size;
da6971d8
AR		 871 for (j = 0; j < blk_cnt; j++) {
872 int k = 0;
4f870320
JP		 873
874 size = sizeof(struct buffAdd) *
875 (rxd_count[nic->rxd_mode] + 1);
876 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 877 if (!ring->ba[j])
1da177e4 878 return -ENOMEM;
4f870320 879 mem_allocated += size;
da6971d8 880 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 881 ba = &ring->ba[j][k];
4f870320
JP		 882 size = BUF0_LEN + ALIGN_SIZE;
883 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 884 if (!ba->ba_0_org)
885 return -ENOMEM;
4f870320 886 mem_allocated += size;
da6971d8
AR		 887 tmp = (unsigned long)ba->ba_0_org;
888 tmp += ALIGN_SIZE;
d44570e4
JP		 889 tmp &= ~((unsigned long)ALIGN_SIZE);
890 ba->ba_0 = (void *)tmp;
da6971d8 891
4f870320
JP		 892 size = BUF1_LEN + ALIGN_SIZE;
893 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 894 if (!ba->ba_1_org)
895 return -ENOMEM;
4f870320 896 mem_allocated += size;
d44570e4 897 tmp = (unsigned long)ba->ba_1_org;
da6971d8 898 tmp += ALIGN_SIZE;
d44570e4
JP		 899 tmp &= ~((unsigned long)ALIGN_SIZE);
900 ba->ba_1 = (void *)tmp;
da6971d8
AR		 901 k++;
902 }
1da177e4
LT		 903 }
904 }
905 }
1da177e4
LT		 906
907 /* Allocation and initialization of Statistics block */
1ee6dd77 908 size = sizeof(struct stat_block);
d44570e4
JP		 909 mac_control->stats_mem =
910 pci_alloc_consistent(nic->pdev, size,
911 &mac_control->stats_mem_phy);
1da177e4
LT		 912
913 if (!mac_control->stats_mem) {
20346722 914 /*
915 * In case of failure, free_shared_mem() is called, which
916 * should free any memory that was alloced till the
1da177e4
LT		 917 * failure happened.
918 */
919 return -ENOMEM;
920 }
491976b2 921 mem_allocated += size;
1da177e4
LT		 922 mac_control->stats_mem_sz = size;
923
924 tmp_v_addr = mac_control->stats_mem;
d44570e4 925 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
1da177e4 926 memset(tmp_v_addr, 0, size);
3a22813a
BL		 927 DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
928 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
491976b2 929 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 930 return SUCCESS;
931}
932
20346722 933/**
934 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 935 * @nic: Device private variable.
936 * Description: This function is to free all memory locations allocated by
937 * the init_shared_mem() function and return it to the kernel.
938 */
939
940static void free_shared_mem(struct s2io_nic *nic)
941{
942 int i, j, blk_cnt, size;
943 void *tmp_v_addr;
944 dma_addr_t tmp_p_addr;
1da177e4 945 int lst_size, lst_per_page;
8910b49f 946 struct net_device *dev;
491976b2 947 int page_num = 0;
ffb5df6c
JP		 948 struct config_param *config;
949 struct mac_info *mac_control;
950 struct stat_block *stats;
951 struct swStat *swstats;
1da177e4
LT		 952
953 if (!nic)
954 return;
955
8910b49f
MG		 956 dev = nic->dev;
957
1da177e4 958 config = &nic->config;
ffb5df6c
JP		 959 mac_control = &nic->mac_control;
960 stats = mac_control->stats_info;
961 swstats = &stats->sw_stat;
1da177e4 962
d44570e4 963 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 964 lst_per_page = PAGE_SIZE / lst_size;
965
966 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 967 struct fifo_info *fifo = &mac_control->fifos[i];
968 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
969
970 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 971 for (j = 0; j < page_num; j++) {
972 int mem_blks = (j * lst_per_page);
13d866a9
JP		 973 struct list_info_hold *fli;
974
975 if (!fifo->list_info)
6aa20a22 976 return;
13d866a9
JP		 977
978 fli = &fifo->list_info[mem_blks];
979 if (!fli->list_virt_addr)
1da177e4
LT		 980 break;
981 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 982 fli->list_virt_addr,
983 fli->list_phy_addr);
ffb5df6c 984 swstats->mem_freed += PAGE_SIZE;
1da177e4 985 }
776bd20f 986 /* If we got a zero DMA address during allocation,
987 * free the page now
988 */
989 if (mac_control->zerodma_virt_addr) {
990 pci_free_consistent(nic->pdev, PAGE_SIZE,
991 mac_control->zerodma_virt_addr,
992 (dma_addr_t)0);
6aa20a22 993 DBG_PRINT(INIT_DBG,
9e39f7c5
JP		 994 "%s: Freeing TxDL with zero DMA address. "
995 "Virtual address %p\n",
996 dev->name, mac_control->zerodma_virt_addr);
ffb5df6c 997 swstats->mem_freed += PAGE_SIZE;
776bd20f 998 }
13d866a9 999 kfree(fifo->list_info);
82c2d023 1000 swstats->mem_freed += tx_cfg->fifo_len *
d44570e4 1001 sizeof(struct list_info_hold);
1da177e4
LT		 1002 }
1003
1da177e4 1004 size = SIZE_OF_BLOCK;
1da177e4 1005 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1006 struct ring_info *ring = &mac_control->rings[i];
1007
1008 blk_cnt = ring->block_count;
1da177e4 1009 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1010 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1011 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1012 if (tmp_v_addr == NULL)
1013 break;
1014 pci_free_consistent(nic->pdev, size,
1015 tmp_v_addr, tmp_p_addr);
ffb5df6c 1016 swstats->mem_freed += size;
13d866a9 1017 kfree(ring->rx_blocks[j].rxds);
ffb5df6c
JP		 1018 swstats->mem_freed += sizeof(struct rxd_info) *
1019 rxd_count[nic->rxd_mode];
1da177e4
LT		 1020 }
1021 }
1022
6d517a27 1023 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1024 /* Freeing buffer storage addresses in 2BUFF mode. */
1025 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1026 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1027 struct ring_info *ring = &mac_control->rings[i];
1028
1029 blk_cnt = rx_cfg->num_rxd /
1030 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1031 for (j = 0; j < blk_cnt; j++) {
1032 int k = 0;
13d866a9 1033 if (!ring->ba[j])
da6971d8
AR		 1034 continue;
1035 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1036 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1037 kfree(ba->ba_0_org);
ffb5df6c
JP		 1038 swstats->mem_freed +=
1039 BUF0_LEN + ALIGN_SIZE;
da6971d8 1040 kfree(ba->ba_1_org);
ffb5df6c
JP		 1041 swstats->mem_freed +=
1042 BUF1_LEN + ALIGN_SIZE;
da6971d8
AR		 1043 k++;
1044 }
13d866a9 1045 kfree(ring->ba[j]);
ffb5df6c
JP		 1046 swstats->mem_freed += sizeof(struct buffAdd) *
1047 (rxd_count[nic->rxd_mode] + 1);
1da177e4 1048 }
13d866a9 1049 kfree(ring->ba);
ffb5df6c
JP		 1050 swstats->mem_freed += sizeof(struct buffAdd *) *
1051 blk_cnt;
1da177e4 1052 }
1da177e4 1053 }
1da177e4 1054
2fda096d 1055 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1056 struct fifo_info *fifo = &mac_control->fifos[i];
1057 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1058
1059 if (fifo->ufo_in_band_v) {
ffb5df6c
JP		 1060 swstats->mem_freed += tx_cfg->fifo_len *
1061 sizeof(u64);
13d866a9 1062 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1063 }
1064 }
1065
1da177e4 1066 if (mac_control->stats_mem) {
ffb5df6c 1067 swstats->mem_freed += mac_control->stats_mem_sz;
1da177e4
LT		 1068 pci_free_consistent(nic->pdev,
1069 mac_control->stats_mem_sz,
1070 mac_control->stats_mem,
1071 mac_control->stats_mem_phy);
491976b2 1072 }
1da177e4
LT		 1073}
1074
541ae68f 1075/**
1076 * s2io_verify_pci_mode -
1077 */
1078
1ee6dd77 1079static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1080{
1ee6dd77 1081 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1082 register u64 val64 = 0;
1083 int mode;
1084
1085 val64 = readq(&bar0->pci_mode);
1086 mode = (u8)GET_PCI_MODE(val64);
1087
d44570e4 1088 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f 1089 return -1; /* Unknown PCI mode */
1090 return mode;
1091}
1092
c92ca04b
AR		 1093#define NEC_VENID 0x1033
1094#define NEC_DEVID 0x0125
1095static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1096{
1097 struct pci_dev *tdev = NULL;
26d36b64
AC		 1098 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1099 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1100 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1101 pci_dev_put(tdev);
c92ca04b 1102 return 1;
7ad62dbc 1103 }
c92ca04b
AR		 1104 }
1105 }
1106 return 0;
1107}
541ae68f 1108
7b32a312 1109static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 1110/**
1111 * s2io_print_pci_mode -
1112 */
1ee6dd77 1113static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1114{
1ee6dd77 1115 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1116 register u64 val64 = 0;
1117 int mode;
1118 struct config_param *config = &nic->config;
9e39f7c5 1119 const char *pcimode;
541ae68f 1120
1121 val64 = readq(&bar0->pci_mode);
1122 mode = (u8)GET_PCI_MODE(val64);
1123
d44570e4 1124 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f 1125 return -1; /* Unknown PCI mode */
1126
c92ca04b
AR		 1127 config->bus_speed = bus_speed[mode];
1128
1129 if (s2io_on_nec_bridge(nic->pdev)) {
1130 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1131 nic->dev->name);
c92ca04b
AR		 1132 return mode;
1133 }
1134
d44570e4
JP		 1135 switch (mode) {
1136 case PCI_MODE_PCI_33:
9e39f7c5 1137 pcimode = "33MHz PCI bus";
d44570e4
JP		 1138 break;
1139 case PCI_MODE_PCI_66:
9e39f7c5 1140 pcimode = "66MHz PCI bus";
d44570e4
JP		 1141 break;
1142 case PCI_MODE_PCIX_M1_66:
9e39f7c5 1143 pcimode = "66MHz PCIX(M1) bus";
d44570e4
JP		 1144 break;
1145 case PCI_MODE_PCIX_M1_100:
9e39f7c5 1146 pcimode = "100MHz PCIX(M1) bus";
d44570e4
JP		 1147 break;
1148 case PCI_MODE_PCIX_M1_133:
9e39f7c5 1149 pcimode = "133MHz PCIX(M1) bus";
d44570e4
JP		 1150 break;
1151 case PCI_MODE_PCIX_M2_66:
9e39f7c5 1152 pcimode = "133MHz PCIX(M2) bus";
d44570e4
JP		 1153 break;
1154 case PCI_MODE_PCIX_M2_100:
9e39f7c5 1155 pcimode = "200MHz PCIX(M2) bus";
d44570e4
JP		 1156 break;
1157 case PCI_MODE_PCIX_M2_133:
9e39f7c5 1158 pcimode = "266MHz PCIX(M2) bus";
d44570e4
JP		 1159 break;
1160 default:
9e39f7c5
JP		 1161 pcimode = "unsupported bus!";
1162 mode = -1;
541ae68f 1163 }
1164
9e39f7c5
JP		 1165 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1166 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1167
541ae68f 1168 return mode;
1169}
1170
b7c5678f
RV		 1171/**
1172 * init_tti - Initialization transmit traffic interrupt scheme
1173 * @nic: device private variable
1174 * @link: link status (UP/DOWN) used to enable/disable continuous
1175 * transmit interrupts
1176 * Description: The function configures transmit traffic interrupts
1177 * Return Value: SUCCESS on success and
1178 * '-1' on failure
1179 */
1180
0d66afe7 1181static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1182{
1183 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1184 register u64 val64 = 0;
1185 int i;
ffb5df6c 1186 struct config_param *config = &nic->config;
b7c5678f
RV		 1187
1188 for (i = 0; i < config->tx_fifo_num; i++) {
1189 /*
1190 * TTI Initialization. Default Tx timer gets us about
1191 * 250 interrupts per sec. Continuous interrupts are enabled
1192 * by default.
1193 */
1194 if (nic->device_type == XFRAME_II_DEVICE) {
1195 int count = (nic->config.bus_speed * 125)/2;
1196 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1197 } else
1198 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1199
1200 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1201 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1202 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1203 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1204 if (i == 0)
1205 if (use_continuous_tx_intrs && (link == LINK_UP))
1206 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1207 writeq(val64, &bar0->tti_data1_mem);
1208
ac731ab6
SH		 1209 if (nic->config.intr_type == MSI_X) {
1210 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1211 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1212 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1213 TTI_DATA2_MEM_TX_UFC_D(0x300);
1214 } else {
1215 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1216 TX_DEFAULT_STEERING) &&
1217 (config->tx_fifo_num > 1) &&
1218 (i >= nic->udp_fifo_idx) &&
1219 (i < (nic->udp_fifo_idx +
1220 nic->total_udp_fifos)))
ac731ab6
SH		 1221 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1222 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1223 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1224 TTI_DATA2_MEM_TX_UFC_D(0x120);
1225 else
1226 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1227 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1228 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1229 TTI_DATA2_MEM_TX_UFC_D(0x80);
1230 }
b7c5678f
RV		 1231
1232 writeq(val64, &bar0->tti_data2_mem);
1233
d44570e4
JP		 1234 val64 = TTI_CMD_MEM_WE |
1235 TTI_CMD_MEM_STROBE_NEW_CMD |
1236 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1237 writeq(val64, &bar0->tti_command_mem);
1238
1239 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1240 TTI_CMD_MEM_STROBE_NEW_CMD,
1241 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1242 return FAILURE;
1243 }
1244
1245 return SUCCESS;
1246}
1247
20346722 1248/**
1249 * init_nic - Initialization of hardware
b7c5678f 1250 * @nic: device private variable
20346722 1251 * Description: The function sequentially configures every block
1252 * of the H/W from their reset values.
1253 * Return Value: SUCCESS on success and
1da177e4
LT		 1254 * '-1' on failure (endian settings incorrect).
1255 */
1256
1257static int init_nic(struct s2io_nic *nic)
1258{
1ee6dd77 1259 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1260 struct net_device *dev = nic->dev;
1261 register u64 val64 = 0;
1262 void __iomem *add;
1263 u32 time;
1264 int i, j;
c92ca04b 1265 int dtx_cnt = 0;
1da177e4 1266 unsigned long long mem_share;
20346722 1267 int mem_size;
ffb5df6c
JP		 1268 struct config_param *config = &nic->config;
1269 struct mac_info *mac_control = &nic->mac_control;
1da177e4 1270
5e25b9dd 1271 /* to set the swapper controle on the card */
d44570e4
JP		 1272 if (s2io_set_swapper(nic)) {
1273 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1274 return -EIO;
1da177e4
LT		 1275 }
1276
541ae68f 1277 /*
1278 * Herc requires EOI to be removed from reset before XGXS, so..
1279 */
1280 if (nic->device_type & XFRAME_II_DEVICE) {
1281 val64 = 0xA500000000ULL;
1282 writeq(val64, &bar0->sw_reset);
1283 msleep(500);
1284 val64 = readq(&bar0->sw_reset);
1285 }
1286
1da177e4
LT		 1287 /* Remove XGXS from reset state */
1288 val64 = 0;
1289 writeq(val64, &bar0->sw_reset);
1da177e4 1290 msleep(500);
20346722 1291 val64 = readq(&bar0->sw_reset);
1da177e4 1292
7962024e
SH		 1293 /* Ensure that it's safe to access registers by checking
1294 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1295 */
1296 if (nic->device_type == XFRAME_II_DEVICE) {
1297 for (i = 0; i < 50; i++) {
1298 val64 = readq(&bar0->adapter_status);
1299 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1300 break;
1301 msleep(10);
1302 }
1303 if (i == 50)
1304 return -ENODEV;
1305 }
1306
1da177e4
LT		 1307 /* Enable Receiving broadcasts */
1308 add = &bar0->mac_cfg;
1309 val64 = readq(&bar0->mac_cfg);
1310 val64 |= MAC_RMAC_BCAST_ENABLE;
1311 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1312 writel((u32)val64, add);
1da177e4
LT		 1313 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1314 writel((u32) (val64 >> 32), (add + 4));
1315
1316 /* Read registers in all blocks */
1317 val64 = readq(&bar0->mac_int_mask);
1318 val64 = readq(&bar0->mc_int_mask);
1319 val64 = readq(&bar0->xgxs_int_mask);
1320
1321 /* Set MTU */
1322 val64 = dev->mtu;
1323 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1324
541ae68f 1325 if (nic->device_type & XFRAME_II_DEVICE) {
1326 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1327 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1328 &bar0->dtx_control, UF);
541ae68f 1329 if (dtx_cnt & 0x1)
1330 msleep(1); /* Necessary!! */
1da177e4
LT		 1331 dtx_cnt++;
1332 }
541ae68f 1333 } else {
c92ca04b
AR		 1334 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1335 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1336 &bar0->dtx_control, UF);
1337 val64 = readq(&bar0->dtx_control);
1338 dtx_cnt++;
1da177e4
LT		 1339 }
1340 }
1341
1342 /* Tx DMA Initialization */
1343 val64 = 0;
1344 writeq(val64, &bar0->tx_fifo_partition_0);
1345 writeq(val64, &bar0->tx_fifo_partition_1);
1346 writeq(val64, &bar0->tx_fifo_partition_2);
1347 writeq(val64, &bar0->tx_fifo_partition_3);
1348
1da177e4 1349 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1350 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1351
1352 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1353 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1354
1355 if (i == (config->tx_fifo_num - 1)) {
1356 if (i % 2 == 0)
1357 i++;
1358 }
1359
1360 switch (i) {
1361 case 1:
1362 writeq(val64, &bar0->tx_fifo_partition_0);
1363 val64 = 0;
b7c5678f 1364 j = 0;
1da177e4
LT		 1365 break;
1366 case 3:
1367 writeq(val64, &bar0->tx_fifo_partition_1);
1368 val64 = 0;
b7c5678f 1369 j = 0;
1da177e4
LT		 1370 break;
1371 case 5:
1372 writeq(val64, &bar0->tx_fifo_partition_2);
1373 val64 = 0;
b7c5678f 1374 j = 0;
1da177e4
LT		 1375 break;
1376 case 7:
1377 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1378 val64 = 0;
1379 j = 0;
1380 break;
1381 default:
1382 j++;
1da177e4
LT		 1383 break;
1384 }
1385 }
1386
5e25b9dd 1387 /*
1388 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1389 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1390 */
d44570e4 1391 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd 1392 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1393
1da177e4
LT		 1394 val64 = readq(&bar0->tx_fifo_partition_0);
1395 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1396 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1397
20346722 1398 /*
1399 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1400 * integrity checking.
1401 */
1402 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1403 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1404 TX_PA_CFG_IGNORE_SNAP_OUI |
1405 TX_PA_CFG_IGNORE_LLC_CTRL |
1406 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1407 writeq(val64, &bar0->tx_pa_cfg);
1408
1409 /* Rx DMA intialization. */
1410 val64 = 0;
1411 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1412 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1413
1414 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1415 }
1416 writeq(val64, &bar0->rx_queue_priority);
1417
20346722 1418 /*
1419 * Allocating equal share of memory to all the
1da177e4
LT		 1420 * configured Rings.
1421 */
1422 val64 = 0;
541ae68f 1423 if (nic->device_type & XFRAME_II_DEVICE)
1424 mem_size = 32;
1425 else
1426 mem_size = 64;
1427
1da177e4
LT		 1428 for (i = 0; i < config->rx_ring_num; i++) {
1429 switch (i) {
1430 case 0:
20346722 1431 mem_share = (mem_size / config->rx_ring_num +
1432 mem_size % config->rx_ring_num);
1da177e4
LT		 1433 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1434 continue;
1435 case 1:
20346722 1436 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1437 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1438 continue;
1439 case 2:
20346722 1440 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1441 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1442 continue;
1443 case 3:
20346722 1444 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1445 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1446 continue;
1447 case 4:
20346722 1448 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1449 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1450 continue;
1451 case 5:
20346722 1452 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1453 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1454 continue;
1455 case 6:
20346722 1456 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1457 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1458 continue;
1459 case 7:
20346722 1460 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1461 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1462 continue;
1463 }
1464 }
1465 writeq(val64, &bar0->rx_queue_cfg);
1466
20346722 1467 /*
5e25b9dd 1468 * Filling Tx round robin registers
b7c5678f 1469 * as per the number of FIFOs for equal scheduling priority
1da177e4 1470 */
5e25b9dd 1471 switch (config->tx_fifo_num) {
1472 case 1:
b7c5678f 1473 val64 = 0x0;
5e25b9dd 1474 writeq(val64, &bar0->tx_w_round_robin_0);
1475 writeq(val64, &bar0->tx_w_round_robin_1);
1476 writeq(val64, &bar0->tx_w_round_robin_2);
1477 writeq(val64, &bar0->tx_w_round_robin_3);
1478 writeq(val64, &bar0->tx_w_round_robin_4);
1479 break;
1480 case 2:
b7c5678f 1481 val64 = 0x0001000100010001ULL;
5e25b9dd 1482 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1483 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1485 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1486 val64 = 0x0001000100000000ULL;
5e25b9dd 1487 writeq(val64, &bar0->tx_w_round_robin_4);
1488 break;
1489 case 3:
b7c5678f 1490 val64 = 0x0001020001020001ULL;
5e25b9dd 1491 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1492 val64 = 0x0200010200010200ULL;
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1494 val64 = 0x0102000102000102ULL;
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1496 val64 = 0x0001020001020001ULL;
5e25b9dd 1497 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1498 val64 = 0x0200010200000000ULL;
5e25b9dd 1499 writeq(val64, &bar0->tx_w_round_robin_4);
1500 break;
1501 case 4:
b7c5678f 1502 val64 = 0x0001020300010203ULL;
5e25b9dd 1503 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1504 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1506 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1507 val64 = 0x0001020300000000ULL;
5e25b9dd 1508 writeq(val64, &bar0->tx_w_round_robin_4);
1509 break;
1510 case 5:
b7c5678f 1511 val64 = 0x0001020304000102ULL;
5e25b9dd 1512 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1513 val64 = 0x0304000102030400ULL;
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1515 val64 = 0x0102030400010203ULL;
5e25b9dd 1516 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1517 val64 = 0x0400010203040001ULL;
5e25b9dd 1518 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1519 val64 = 0x0203040000000000ULL;
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_4);
1521 break;
1522 case 6:
b7c5678f 1523 val64 = 0x0001020304050001ULL;
5e25b9dd 1524 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1525 val64 = 0x0203040500010203ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1527 val64 = 0x0405000102030405ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1529 val64 = 0x0001020304050001ULL;
5e25b9dd 1530 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1531 val64 = 0x0203040500000000ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_4);
1533 break;
1534 case 7:
b7c5678f 1535 val64 = 0x0001020304050600ULL;
5e25b9dd 1536 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1537 val64 = 0x0102030405060001ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1539 val64 = 0x0203040506000102ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1541 val64 = 0x0304050600010203ULL;
5e25b9dd 1542 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1543 val64 = 0x0405060000000000ULL;
5e25b9dd 1544 writeq(val64, &bar0->tx_w_round_robin_4);
1545 break;
1546 case 8:
b7c5678f 1547 val64 = 0x0001020304050607ULL;
5e25b9dd 1548 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1549 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1551 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1552 val64 = 0x0001020300000000ULL;
5e25b9dd 1553 writeq(val64, &bar0->tx_w_round_robin_4);
1554 break;
1555 }
1556
b41477f3 1557 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1558 val64 = readq(&bar0->tx_fifo_partition_0);
1559 val64 |= (TX_FIFO_PARTITION_EN);
1560 writeq(val64, &bar0->tx_fifo_partition_0);
1561
5e25b9dd 1562 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1563 * number of Rings and steering based on QoS with
1564 * equal priority.
1565 */
5e25b9dd 1566 switch (config->rx_ring_num) {
1567 case 1:
0425b46a
SH		 1568 val64 = 0x0;
1569 writeq(val64, &bar0->rx_w_round_robin_0);
1570 writeq(val64, &bar0->rx_w_round_robin_1);
1571 writeq(val64, &bar0->rx_w_round_robin_2);
1572 writeq(val64, &bar0->rx_w_round_robin_3);
1573 writeq(val64, &bar0->rx_w_round_robin_4);
1574
5e25b9dd 1575 val64 = 0x8080808080808080ULL;
1576 writeq(val64, &bar0->rts_qos_steering);
1577 break;
1578 case 2:
0425b46a 1579 val64 = 0x0001000100010001ULL;
5e25b9dd 1580 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1581 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1582 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1583 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1584 val64 = 0x0001000100000000ULL;
5e25b9dd 1585 writeq(val64, &bar0->rx_w_round_robin_4);
1586
1587 val64 = 0x8080808040404040ULL;
1588 writeq(val64, &bar0->rts_qos_steering);
1589 break;
1590 case 3:
0425b46a 1591 val64 = 0x0001020001020001ULL;
5e25b9dd 1592 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1593 val64 = 0x0200010200010200ULL;
5e25b9dd 1594 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1595 val64 = 0x0102000102000102ULL;
5e25b9dd 1596 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1597 val64 = 0x0001020001020001ULL;
5e25b9dd 1598 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1599 val64 = 0x0200010200000000ULL;
5e25b9dd 1600 writeq(val64, &bar0->rx_w_round_robin_4);
1601
1602 val64 = 0x8080804040402020ULL;
1603 writeq(val64, &bar0->rts_qos_steering);
1604 break;
1605 case 4:
0425b46a 1606 val64 = 0x0001020300010203ULL;
5e25b9dd 1607 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1608 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1609 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1610 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1611 val64 = 0x0001020300000000ULL;
5e25b9dd 1612 writeq(val64, &bar0->rx_w_round_robin_4);
1613
1614 val64 = 0x8080404020201010ULL;
1615 writeq(val64, &bar0->rts_qos_steering);
1616 break;
1617 case 5:
0425b46a 1618 val64 = 0x0001020304000102ULL;
5e25b9dd 1619 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1620 val64 = 0x0304000102030400ULL;
5e25b9dd 1621 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1622 val64 = 0x0102030400010203ULL;
5e25b9dd 1623 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1624 val64 = 0x0400010203040001ULL;
5e25b9dd 1625 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1626 val64 = 0x0203040000000000ULL;
5e25b9dd 1627 writeq(val64, &bar0->rx_w_round_robin_4);
1628
1629 val64 = 0x8080404020201008ULL;
1630 writeq(val64, &bar0->rts_qos_steering);
1631 break;
1632 case 6:
0425b46a 1633 val64 = 0x0001020304050001ULL;
5e25b9dd 1634 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1635 val64 = 0x0203040500010203ULL;
5e25b9dd 1636 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1637 val64 = 0x0405000102030405ULL;
5e25b9dd 1638 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1639 val64 = 0x0001020304050001ULL;
5e25b9dd 1640 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1641 val64 = 0x0203040500000000ULL;
5e25b9dd 1642 writeq(val64, &bar0->rx_w_round_robin_4);
1643
1644 val64 = 0x8080404020100804ULL;
1645 writeq(val64, &bar0->rts_qos_steering);
1646 break;
1647 case 7:
0425b46a 1648 val64 = 0x0001020304050600ULL;
5e25b9dd 1649 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1650 val64 = 0x0102030405060001ULL;
5e25b9dd 1651 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1652 val64 = 0x0203040506000102ULL;
5e25b9dd 1653 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1654 val64 = 0x0304050600010203ULL;
5e25b9dd 1655 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1656 val64 = 0x0405060000000000ULL;
5e25b9dd 1657 writeq(val64, &bar0->rx_w_round_robin_4);
1658
1659 val64 = 0x8080402010080402ULL;
1660 writeq(val64, &bar0->rts_qos_steering);
1661 break;
1662 case 8:
0425b46a 1663 val64 = 0x0001020304050607ULL;
5e25b9dd 1664 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1665 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1666 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1667 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1668 val64 = 0x0001020300000000ULL;
5e25b9dd 1669 writeq(val64, &bar0->rx_w_round_robin_4);
1670
1671 val64 = 0x8040201008040201ULL;
1672 writeq(val64, &bar0->rts_qos_steering);
1673 break;
1674 }
1da177e4
LT		 1675
1676 /* UDP Fix */
1677 val64 = 0;
20346722 1678 for (i = 0; i < 8; i++)
1da177e4
LT		 1679 writeq(val64, &bar0->rts_frm_len_n[i]);
1680
5e25b9dd 1681 /* Set the default rts frame length for the rings configured */
1682 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1683 for (i = 0 ; i < config->rx_ring_num ; i++)
1684 writeq(val64, &bar0->rts_frm_len_n[i]);
1685
1686 /* Set the frame length for the configured rings
1687 * desired by the user
1688 */
1689 for (i = 0; i < config->rx_ring_num; i++) {
1690 /* If rts_frm_len[i] == 0 then it is assumed that user not
1691 * specified frame length steering.
1692 * If the user provides the frame length then program
1693 * the rts_frm_len register for those values or else
1694 * leave it as it is.
1695 */
1696 if (rts_frm_len[i] != 0) {
1697 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1698 &bar0->rts_frm_len_n[i]);
5e25b9dd 1699 }
1700 }
8a4bdbaa 1701
9fc93a41
SS		 1702 /* Disable differentiated services steering logic */
1703 for (i = 0; i < 64; i++) {
1704 if (rts_ds_steer(nic, i, 0) == FAILURE) {
9e39f7c5
JP		 1705 DBG_PRINT(ERR_DBG,
1706 "%s: rts_ds_steer failed on codepoint %d\n",
1707 dev->name, i);
9f74ffde 1708 return -ENODEV;
9fc93a41
SS		 1709 }
1710 }
1711
20346722 1712 /* Program statistics memory */
1da177e4 1713 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1714
541ae68f 1715 if (nic->device_type == XFRAME_II_DEVICE) {
1716 val64 = STAT_BC(0x320);
1717 writeq(val64, &bar0->stat_byte_cnt);
1718 }
1719
20346722 1720 /*
1da177e4
LT		 1721 * Initializing the sampling rate for the device to calculate the
1722 * bandwidth utilization.
1723 */
1724 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1725 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1726 writeq(val64, &bar0->mac_link_util);
1727
20346722 1728 /*
1729 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1730 * Scheme.
1731 */
1da177e4 1732
b7c5678f
RV		 1733 /* Initialize TTI */
1734 if (SUCCESS != init_tti(nic, nic->last_link_state))
1735 return -ENODEV;
1da177e4 1736
8a4bdbaa
SS		 1737 /* RTI Initialization */
1738 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1739 /*
8a4bdbaa
SS		 1740 * Programmed to generate Apprx 500 Intrs per
1741 * second
1742 */
1743 int count = (nic->config.bus_speed * 125)/4;
1744 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1745 } else
1746 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1747 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1748 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1749 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1750 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1751
1752 writeq(val64, &bar0->rti_data1_mem);
1753
1754 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1755 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1756 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1757 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1758 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1759 else
d44570e4
JP		 1760 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1761 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1762 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1763
8a4bdbaa 1764 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1765 val64 = RTI_CMD_MEM_WE |
1766 RTI_CMD_MEM_STROBE_NEW_CMD |
1767 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1768 writeq(val64, &bar0->rti_command_mem);
1da177e4 1769
8a4bdbaa
SS		 1770 /*
1771 * Once the operation completes, the Strobe bit of the
1772 * command register will be reset. We poll for this
1773 * particular condition. We wait for a maximum of 500ms
1774 * for the operation to complete, if it's not complete
1775 * by then we return error.
1776 */
1777 time = 0;
f957bcf0 1778 while (true) {
8a4bdbaa
SS		 1779 val64 = readq(&bar0->rti_command_mem);
1780 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1781 break;
b6e3f982 1782
8a4bdbaa 1783 if (time > 10) {
9e39f7c5 1784 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
8a4bdbaa 1785 dev->name);
9f74ffde 1786 return -ENODEV;
b6e3f982 1787 }
8a4bdbaa
SS		 1788 time++;
1789 msleep(50);
1da177e4 1790 }
1da177e4
LT		 1791 }
1792
20346722 1793 /*
1794 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1795 * the 8 Queues on Rx side.
1796 */
1797 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1798 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1799
1800 /* Disable RMAC PAD STRIPPING */
509a2671 1801 add = &bar0->mac_cfg;
1da177e4
LT		 1802 val64 = readq(&bar0->mac_cfg);
1803 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1804 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1805 writel((u32) (val64), add);
1806 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807 writel((u32) (val64 >> 32), (add + 4));
1808 val64 = readq(&bar0->mac_cfg);
1809
7d3d0439
RA		 1810 /* Enable FCS stripping by adapter */
1811 add = &bar0->mac_cfg;
1812 val64 = readq(&bar0->mac_cfg);
1813 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1814 if (nic->device_type == XFRAME_II_DEVICE)
1815 writeq(val64, &bar0->mac_cfg);
1816 else {
1817 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1818 writel((u32) (val64), add);
1819 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1820 writel((u32) (val64 >> 32), (add + 4));
1821 }
1822
20346722 1823 /*
1824 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1825 * generated by xena.
1826 */
1827 val64 = readq(&bar0->rmac_pause_cfg);
1828 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1829 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1830 writeq(val64, &bar0->rmac_pause_cfg);
1831
20346722 1832 /*
1da177e4
LT		 1833 * Set the Threshold Limit for Generating the pause frame
1834 * If the amount of data in any Queue exceeds ratio of
1835 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1836 * pause frame is generated
1837 */
1838 val64 = 0;
1839 for (i = 0; i < 4; i++) {
d44570e4
JP		 1840 val64 |= (((u64)0xFF00 |
1841 nic->mac_control.mc_pause_threshold_q0q3)
1842 << (i * 2 * 8));
1da177e4
LT		 1843 }
1844 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1845
1846 val64 = 0;
1847 for (i = 0; i < 4; i++) {
d44570e4
JP		 1848 val64 |= (((u64)0xFF00 |
1849 nic->mac_control.mc_pause_threshold_q4q7)
1850 << (i * 2 * 8));
1da177e4
LT		 1851 }
1852 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1853
20346722 1854 /*
1855 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1856 * exceeded the limit pointed by shared_splits
1857 */
1858 val64 = readq(&bar0->pic_control);
1859 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1860 writeq(val64, &bar0->pic_control);
1861
863c11a9
AR		 1862 if (nic->config.bus_speed == 266) {
1863 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1864 writeq(0x0, &bar0->read_retry_delay);
1865 writeq(0x0, &bar0->write_retry_delay);
1866 }
1867
541ae68f 1868 /*
1869 * Programming the Herc to split every write transaction
1870 * that does not start on an ADB to reduce disconnects.
1871 */
1872 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1873 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1874 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1875 writeq(val64, &bar0->misc_control);
1876 val64 = readq(&bar0->pic_control2);
b7b5a128 1877 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1878 writeq(val64, &bar0->pic_control2);
541ae68f 1879 }
c92ca04b
AR		 1880 if (strstr(nic->product_name, "CX4")) {
1881 val64 = TMAC_AVG_IPG(0x17);
1882 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1883 }
1884
1da177e4
LT		 1885 return SUCCESS;
1886}
a371a07d 1887#define LINK_UP_DOWN_INTERRUPT 1
1888#define MAC_RMAC_ERR_TIMER 2
1889
1ee6dd77 1890static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1891{
1892 if (nic->device_type == XFRAME_II_DEVICE)
1893 return LINK_UP_DOWN_INTERRUPT;
1894 else
1895 return MAC_RMAC_ERR_TIMER;
1896}
8116f3cf 1897
9caab458
SS		 1898/**
1899 * do_s2io_write_bits - update alarm bits in alarm register
1900 * @value: alarm bits
1901 * @flag: interrupt status
1902 * @addr: address value
1903 * Description: update alarm bits in alarm register
1904 * Return Value:
1905 * NONE.
1906 */
1907static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1908{
1909 u64 temp64;
1910
1911 temp64 = readq(addr);
1912
d44570e4
JP		 1913 if (flag == ENABLE_INTRS)
1914 temp64 &= ~((u64)value);
9caab458 1915 else
d44570e4 1916 temp64 |= ((u64)value);
9caab458
SS		 1917 writeq(temp64, addr);
1918}
1da177e4 1919
43b7c451 1920static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1921{
1922 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1923 register u64 gen_int_mask = 0;
01e16faa 1924 u64 interruptible;
9caab458 1925
01e16faa 1926 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1927 if (mask & TX_DMA_INTR) {
9caab458
SS		 1928 gen_int_mask |= TXDMA_INT_M;
1929
1930 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1931 TXDMA_PCC_INT | TXDMA_TTI_INT |
1932 TXDMA_LSO_INT | TXDMA_TPA_INT |
1933 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1934
1935 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1936 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1937 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1938 &bar0->pfc_err_mask);
9caab458
SS		 1939
1940 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1941 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1942 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1943
1944 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1945 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1946 PCC_N_SERR | PCC_6_COF_OV_ERR |
1947 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1948 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1949 PCC_TXB_ECC_SG_ERR,
1950 flag, &bar0->pcc_err_mask);
9caab458
SS		 1951
1952 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1953 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1954
1955 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1956 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1957 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1958 flag, &bar0->lso_err_mask);
9caab458
SS		 1959
1960 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1961 flag, &bar0->tpa_err_mask);
9caab458
SS		 1962
1963 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1964 }
1965
1966 if (mask & TX_MAC_INTR) {
1967 gen_int_mask |= TXMAC_INT_M;
1968 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1969 &bar0->mac_int_mask);
9caab458 1970 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1971 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1972 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1973 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1974 }
1975
1976 if (mask & TX_XGXS_INTR) {
1977 gen_int_mask |= TXXGXS_INT_M;
1978 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1979 &bar0->xgxs_int_mask);
9caab458 1980 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1981 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1982 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1983 }
1984
1985 if (mask & RX_DMA_INTR) {
1986 gen_int_mask |= RXDMA_INT_M;
1987 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1988 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1989 flag, &bar0->rxdma_int_mask);
9caab458 1990 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 1991 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1992 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1993 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 1994 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 1995 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1996 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1997 &bar0->prc_pcix_err_mask);
9caab458 1998 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 1999 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2000 &bar0->rpa_err_mask);
9caab458 2001 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 2002 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2003 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2004 RDA_FRM_ECC_SG_ERR |
2005 RDA_MISC_ERR|RDA_PCIX_ERR,
2006 flag, &bar0->rda_err_mask);
9caab458 2007 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2008 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2009 flag, &bar0->rti_err_mask);
9caab458
SS		 2010 }
2011
2012 if (mask & RX_MAC_INTR) {
2013 gen_int_mask |= RXMAC_INT_M;
2014 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2015 &bar0->mac_int_mask);
2016 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2017 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2018 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2019 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2020 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2021 do_s2io_write_bits(interruptible,
d44570e4 2022 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2023 }
2024
d44570e4 2025 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2026 gen_int_mask |= RXXGXS_INT_M;
2027 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2028 &bar0->xgxs_int_mask);
9caab458 2029 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2030 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2031 }
2032
2033 if (mask & MC_INTR) {
2034 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2035 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2036 flag, &bar0->mc_int_mask);
9caab458 2037 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2038 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2039 &bar0->mc_err_mask);
9caab458
SS		 2040 }
2041 nic->general_int_mask = gen_int_mask;
2042
2043 /* Remove this line when alarm interrupts are enabled */
2044 nic->general_int_mask = 0;
2045}
d44570e4 2046
20346722 2047/**
2048 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2049 * @nic: device private variable,
2050 * @mask: A mask indicating which Intr block must be modified and,
2051 * @flag: A flag indicating whether to enable or disable the Intrs.
2052 * Description: This function will either disable or enable the interrupts
20346722 2053 * depending on the flag argument. The mask argument can be used to
2054 * enable/disable any Intr block.
1da177e4
LT		 2055 * Return Value: NONE.
2056 */
2057
2058static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2059{
1ee6dd77 2060 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2061 register u64 temp64 = 0, intr_mask = 0;
2062
2063 intr_mask = nic->general_int_mask;
1da177e4
LT		 2064
2065 /* Top level interrupt classification */
2066 /* PIC Interrupts */
9caab458 2067 if (mask & TX_PIC_INTR) {
1da177e4 2068 /* Enable PIC Intrs in the general intr mask register */
9caab458 2069 intr_mask |= TXPIC_INT_M;
1da177e4 2070 if (flag == ENABLE_INTRS) {
20346722 2071 /*
a371a07d 2072 * If Hercules adapter enable GPIO otherwise
b41477f3 2073 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 2074 * interrupts for now.
2075 * TODO
1da177e4 2076 */
a371a07d 2077 if (s2io_link_fault_indication(nic) ==
d44570e4 2078 LINK_UP_DOWN_INTERRUPT) {
9caab458 2079 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2080 &bar0->pic_int_mask);
9caab458 2081 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2082 &bar0->gpio_int_mask);
9caab458 2083 } else
a371a07d 2084 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2085 } else if (flag == DISABLE_INTRS) {
20346722 2086 /*
2087 * Disable PIC Intrs in the general
2088 * intr mask register
1da177e4
LT		 2089 */
2090 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2091 }
2092 }
2093
1da177e4
LT		 2094 /* Tx traffic interrupts */
2095 if (mask & TX_TRAFFIC_INTR) {
9caab458 2096 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2097 if (flag == ENABLE_INTRS) {
20346722 2098 /*
1da177e4 2099 * Enable all the Tx side interrupts
20346722 2100 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2101 */
2102 writeq(0x0, &bar0->tx_traffic_mask);
2103 } else if (flag == DISABLE_INTRS) {
20346722 2104 /*
2105 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2106 * register.
2107 */
2108 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2109 }
2110 }
2111
2112 /* Rx traffic interrupts */
2113 if (mask & RX_TRAFFIC_INTR) {
9caab458 2114 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2115 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2116 /* writing 0 Enables all 8 RX interrupt levels */
2117 writeq(0x0, &bar0->rx_traffic_mask);
2118 } else if (flag == DISABLE_INTRS) {
20346722 2119 /*
2120 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2121 * register.
2122 */
2123 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2124 }
2125 }
9caab458
SS		 2126
2127 temp64 = readq(&bar0->general_int_mask);
2128 if (flag == ENABLE_INTRS)
d44570e4 2129 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2130 else
2131 temp64 = DISABLE_ALL_INTRS;
2132 writeq(temp64, &bar0->general_int_mask);
2133
2134 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2135}
2136
19a60522
SS		 2137/**
2138 * verify_pcc_quiescent- Checks for PCC quiescent state
2139 * Return: 1 If PCC is quiescence
2140 * 0 If PCC is not quiescence
2141 */
1ee6dd77 2142static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2143{
19a60522 2144 int ret = 0, herc;
1ee6dd77 2145 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2146 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2147
19a60522 2148 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2149
f957bcf0 2150 if (flag == false) {
44c10138 2151 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2152 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2153 ret = 1;
19a60522
SS		 2154 } else {
2155 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2156 ret = 1;
20346722 2157 }
2158 } else {
44c10138 2159 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2160 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2161 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2162 ret = 1;
5e25b9dd 2163 } else {
2164 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2165 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2166 ret = 1;
20346722 2167 }
2168 }
2169
2170 return ret;
2171}
2172/**
2173 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2174 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2175 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2176 * differs and the calling function passes the input argument flag to
2177 * indicate this.
20346722 2178 * Return: 1 If xena is quiescence
1da177e4
LT		 2179 * 0 If Xena is not quiescence
2180 */
2181
1ee6dd77 2182static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2183{
19a60522 2184 int mode;
1ee6dd77 2185 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2186 u64 val64 = readq(&bar0->adapter_status);
2187 mode = s2io_verify_pci_mode(sp);
1da177e4 2188
19a60522 2189 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
9e39f7c5 2190 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
19a60522
SS		 2191 return 0;
2192 }
2193 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
9e39f7c5 2194 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
19a60522
SS		 2195 return 0;
2196 }
2197 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
9e39f7c5 2198 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
19a60522
SS		 2199 return 0;
2200 }
2201 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
9e39f7c5 2202 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
19a60522
SS		 2203 return 0;
2204 }
2205 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
9e39f7c5 2206 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
19a60522
SS		 2207 return 0;
2208 }
2209 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
9e39f7c5 2210 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
19a60522
SS		 2211 return 0;
2212 }
2213 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
9e39f7c5 2214 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
19a60522
SS		 2215 return 0;
2216 }
2217 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
9e39f7c5 2218 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
19a60522 2219 return 0;
1da177e4
LT		 2220 }
2221
19a60522
SS		 2222 /*
2223 * In PCI 33 mode, the P_PLL is not used, and therefore,
2224 * the the P_PLL_LOCK bit in the adapter_status register will
2225 * not be asserted.
2226 */
2227 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2228 sp->device_type == XFRAME_II_DEVICE &&
2229 mode != PCI_MODE_PCI_33) {
9e39f7c5 2230 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
19a60522
SS		 2231 return 0;
2232 }
2233 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2234 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
9e39f7c5 2235 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
19a60522
SS		 2236 return 0;
2237 }
2238 return 1;
1da177e4
LT		 2239}
2240
2241/**
2242 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2243 * @sp: Pointer to device specifc structure
20346722 2244 * Description :
1da177e4
LT		 2245 * New procedure to clear mac address reading problems on Alpha platforms
2246 *
2247 */
2248
d44570e4 2249static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2250{
1ee6dd77 2251 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2252 u64 val64;
2253 int i = 0;
2254
2255 while (fix_mac[i] != END_SIGN) {
2256 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2257 udelay(10);
1da177e4
LT		 2258 val64 = readq(&bar0->gpio_control);
2259 }
2260}
2261
2262/**
20346722 2263 * start_nic - Turns the device on
1da177e4 2264 * @nic : device private variable.
20346722 2265 * Description:
2266 * This function actually turns the device on. Before this function is
2267 * called,all Registers are configured from their reset states
2268 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2269 * calling this function, the device interrupts are cleared and the NIC is
2270 * literally switched on by writing into the adapter control register.
20346722 2271 * Return Value:
1da177e4
LT		 2272 * SUCCESS on success and -1 on failure.
2273 */
2274
2275static int start_nic(struct s2io_nic *nic)
2276{
1ee6dd77 2277 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2278 struct net_device *dev = nic->dev;
2279 register u64 val64 = 0;
20346722 2280 u16 subid, i;
ffb5df6c
JP		 2281 struct config_param *config = &nic->config;
2282 struct mac_info *mac_control = &nic->mac_control;
1da177e4
LT		 2283
2284 /* PRC Initialization and configuration */
2285 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2286 struct ring_info *ring = &mac_control->rings[i];
2287
d44570e4 2288 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2289 &bar0->prc_rxd0_n[i]);
2290
2291 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2292 if (nic->rxd_mode == RXD_MODE_1)
2293 val64 |= PRC_CTRL_RC_ENABLED;
2294 else
2295 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2296 if (nic->device_type == XFRAME_II_DEVICE)
2297 val64 |= PRC_CTRL_GROUP_READS;
2298 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2299 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2300 writeq(val64, &bar0->prc_ctrl_n[i]);
2301 }
2302
da6971d8
AR		 2303 if (nic->rxd_mode == RXD_MODE_3B) {
2304 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2305 val64 = readq(&bar0->rx_pa_cfg);
2306 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2307 writeq(val64, &bar0->rx_pa_cfg);
2308 }
1da177e4 2309
926930b2
SS		 2310 if (vlan_tag_strip == 0) {
2311 val64 = readq(&bar0->rx_pa_cfg);
2312 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2313 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2314 nic->vlan_strip_flag = 0;
926930b2
SS		 2315 }
2316
20346722 2317 /*
1da177e4
LT		 2318 * Enabling MC-RLDRAM. After enabling the device, we timeout
2319 * for around 100ms, which is approximately the time required
2320 * for the device to be ready for operation.
2321 */
2322 val64 = readq(&bar0->mc_rldram_mrs);
2323 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2324 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2325 val64 = readq(&bar0->mc_rldram_mrs);
2326
20346722 2327 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2328
2329 /* Enabling ECC Protection. */
2330 val64 = readq(&bar0->adapter_control);
2331 val64 &= ~ADAPTER_ECC_EN;
2332 writeq(val64, &bar0->adapter_control);
2333
20346722 2334 /*
2335 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2336 * it.
2337 */
2338 val64 = readq(&bar0->adapter_status);
19a60522 2339 if (!verify_xena_quiescence(nic)) {
9e39f7c5
JP		 2340 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2341 "Adapter status reads: 0x%llx\n",
2342 dev->name, (unsigned long long)val64);
1da177e4
LT		 2343 return FAILURE;
2344 }
2345
20346722 2346 /*
1da177e4 2347 * With some switches, link might be already up at this point.
20346722 2348 * Because of this weird behavior, when we enable laser,
2349 * we may not get link. We need to handle this. We cannot
2350 * figure out which switch is misbehaving. So we are forced to
2351 * make a global change.
1da177e4
LT		 2352 */
2353
2354 /* Enabling Laser. */
2355 val64 = readq(&bar0->adapter_control);
2356 val64 |= ADAPTER_EOI_TX_ON;
2357 writeq(val64, &bar0->adapter_control);
2358
c92ca04b
AR		 2359 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2360 /*
2361 * Dont see link state interrupts initally on some switches,
2362 * so directly scheduling the link state task here.
2363 */
2364 schedule_work(&nic->set_link_task);
2365 }
1da177e4
LT		 2366 /* SXE-002: Initialize link and activity LED */
2367 subid = nic->pdev->subsystem_device;
541ae68f 2368 if (((subid & 0xFF) >= 0x07) &&
2369 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2370 val64 = readq(&bar0->gpio_control);
2371 val64 |= 0x0000800000000000ULL;
2372 writeq(val64, &bar0->gpio_control);
2373 val64 = 0x0411040400000000ULL;
509a2671 2374 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2375 }
2376
1da177e4
LT		 2377 return SUCCESS;
2378}
fed5eccd
AR		 2379/**
2380 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2381 */
d44570e4
JP		 2382static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2383 struct TxD *txdlp, int get_off)
fed5eccd 2384{
1ee6dd77 2385 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2386 struct sk_buff *skb;
1ee6dd77 2387 struct TxD *txds;
fed5eccd
AR		 2388 u16 j, frg_cnt;
2389
2390 txds = txdlp;
2fda096d 2391 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2392 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2393 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2394 txds++;
2395 }
2396
d44570e4 2397 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2398 if (!skb) {
1ee6dd77 2399 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2400 return NULL;
2401 }
d44570e4 2402 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
e743d313 2403 skb_headlen(skb), PCI_DMA_TODEVICE);
fed5eccd
AR		 2404 frg_cnt = skb_shinfo(skb)->nr_frags;
2405 if (frg_cnt) {
2406 txds++;
2407 for (j = 0; j < frg_cnt; j++, txds++) {
2408 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2409 if (!txds->Buffer_Pointer)
2410 break;
d44570e4
JP		 2411 pci_unmap_page(nic->pdev,
2412 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2413 frag->size, PCI_DMA_TODEVICE);
2414 }
2415 }
d44570e4
JP		 2416 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2417 return skb;
fed5eccd 2418}
1da177e4 2419
20346722 2420/**
2421 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2422 * @nic : device private variable.
20346722 2423 * Description:
1da177e4 2424 * Free all queued Tx buffers.
20346722 2425 * Return Value: void
d44570e4 2426 */
1da177e4
LT		 2427
2428static void free_tx_buffers(struct s2io_nic *nic)
2429{
2430 struct net_device *dev = nic->dev;
2431 struct sk_buff *skb;
1ee6dd77 2432 struct TxD *txdp;
1da177e4 2433 int i, j;
fed5eccd 2434 int cnt = 0;
ffb5df6c
JP		 2435 struct config_param *config = &nic->config;
2436 struct mac_info *mac_control = &nic->mac_control;
2437 struct stat_block *stats = mac_control->stats_info;
2438 struct swStat *swstats = &stats->sw_stat;
1da177e4
LT		 2439
2440 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2441 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2442 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2443 unsigned long flags;
13d866a9
JP		 2444
2445 spin_lock_irqsave(&fifo->tx_lock, flags);
2446 for (j = 0; j < tx_cfg->fifo_len; j++) {
2447 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2448 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2449 if (skb) {
ffb5df6c 2450 swstats->mem_freed += skb->truesize;
fed5eccd
AR		 2451 dev_kfree_skb(skb);
2452 cnt++;
1da177e4 2453 }
1da177e4
LT		 2454 }
2455 DBG_PRINT(INTR_DBG,
9e39f7c5 2456 "%s: forcibly freeing %d skbs on FIFO%d\n",
1da177e4 2457 dev->name, cnt, i);
13d866a9
JP		 2458 fifo->tx_curr_get_info.offset = 0;
2459 fifo->tx_curr_put_info.offset = 0;
2460 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2461 }
2462}
2463
20346722 2464/**
2465 * stop_nic - To stop the nic
1da177e4 2466 * @nic ; device private variable.
20346722 2467 * Description:
2468 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2469 * function does. This function is called to stop the device.
2470 * Return Value:
2471 * void.
2472 */
2473
2474static void stop_nic(struct s2io_nic *nic)
2475{
1ee6dd77 2476 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2477 register u64 val64 = 0;
5d3213cc 2478 u16 interruptible;
1da177e4
LT		 2479
2480 /* Disable all interrupts */
9caab458 2481 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2482 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2483 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2484 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2485
5d3213cc
AR		 2486 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2487 val64 = readq(&bar0->adapter_control);
2488 val64 &= ~(ADAPTER_CNTL_EN);
2489 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2490}
2491
20346722 2492/**
2493 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2494 * @ring_info: per ring structure
3f78d885
SH		 2495 * @from_card_up: If this is true, we will map the buffer to get
2496 * the dma address for buf0 and buf1 to give it to the card.
2497 * Else we will sync the already mapped buffer to give it to the card.
20346722 2498 * Description:
1da177e4
LT		 2499 * The function allocates Rx side skbs and puts the physical
2500 * address of these buffers into the RxD buffer pointers, so that the NIC
2501 * can DMA the received frame into these locations.
2502 * The NIC supports 3 receive modes, viz
2503 * 1. single buffer,
2504 * 2. three buffer and
2505 * 3. Five buffer modes.
20346722 2506 * Each mode defines how many fragments the received frame will be split
2507 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2508 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2509 * is split into 3 fragments. As of now only single buffer mode is
2510 * supported.
2511 * Return Value:
2512 * SUCCESS on success or an appropriate -ve value on failure.
2513 */
8d8bb39b 2514static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2515 int from_card_up)
1da177e4 2516{
1da177e4 2517 struct sk_buff *skb;
1ee6dd77 2518 struct RxD_t *rxdp;
0425b46a 2519 int off, size, block_no, block_no1;
1da177e4 2520 u32 alloc_tab = 0;
20346722 2521 u32 alloc_cnt;
20346722 2522 u64 tmp;
1ee6dd77 2523 struct buffAdd *ba;
1ee6dd77 2524 struct RxD_t *first_rxdp = NULL;
363dc367 2525 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2526 int rxd_index = 0;
6d517a27
VP		 2527 struct RxD1 *rxdp1;
2528 struct RxD3 *rxdp3;
ffb5df6c 2529 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2530
0425b46a 2531 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2532
0425b46a 2533 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2534 while (alloc_tab < alloc_cnt) {
0425b46a 2535 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2536
0425b46a
SH		 2537 off = ring->rx_curr_put_info.offset;
2538
2539 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2540
2541 rxd_index = off + 1;
2542 if (block_no)
2543 rxd_index += (block_no * ring->rxd_count);
da6971d8 2544
7d2e3cb7 2545 if ((block_no == block_no1) &&
d44570e4
JP		 2546 (off == ring->rx_curr_get_info.offset) &&
2547 (rxdp->Host_Control)) {
9e39f7c5
JP		 2548 DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2549 ring->dev->name);
1da177e4
LT		 2550 goto end;
2551 }
0425b46a
SH		 2552 if (off && (off == ring->rxd_count)) {
2553 ring->rx_curr_put_info.block_index++;
2554 if (ring->rx_curr_put_info.block_index ==
d44570e4 2555 ring->block_count)
0425b46a
SH		 2556 ring->rx_curr_put_info.block_index = 0;
2557 block_no = ring->rx_curr_put_info.block_index;
2558 off = 0;
2559 ring->rx_curr_put_info.offset = off;
2560 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2561 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2562 ring->dev->name, rxdp);
2563
1da177e4 2564 }
c9fcbf47 2565
da6971d8 2566 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2567 ((ring->rxd_mode == RXD_MODE_3B) &&
2568 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2569 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2570 goto end;
2571 }
da6971d8 2572 /* calculate size of skb based on ring mode */
d44570e4
JP		 2573 size = ring->mtu +
2574 HEADER_ETHERNET_II_802_3_SIZE +
2575 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2576 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2577 size += NET_IP_ALIGN;
da6971d8 2578 else
0425b46a 2579 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2580
da6971d8
AR		 2581 /* allocate skb */
2582 skb = dev_alloc_skb(size);
d44570e4 2583 if (!skb) {
9e39f7c5
JP		 2584 DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2585 ring->dev->name);
303bcb4b 2586 if (first_rxdp) {
2587 wmb();
2588 first_rxdp->Control_1 |= RXD_OWN_XENA;
2589 }
ffb5df6c 2590 swstats->mem_alloc_fail_cnt++;
7d2e3cb7 2591
da6971d8
AR		 2592 return -ENOMEM ;
2593 }
ffb5df6c 2594 swstats->mem_allocated += skb->truesize;
0425b46a
SH		 2595
2596 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2597 /* 1 buffer mode - normal operation mode */
d44570e4 2598 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2599 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2600 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2601 rxdp1->Buffer0_ptr =
2602 pci_map_single(ring->pdev, skb->data,
2603 size - NET_IP_ALIGN,
2604 PCI_DMA_FROMDEVICE);
8d8bb39b 2605 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2606 rxdp1->Buffer0_ptr))
491abf25
VP		 2607 goto pci_map_failed;
2608
8a4bdbaa 2609 rxdp->Control_2 =
491976b2 2610 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2611 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2612 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2613 /*
6d517a27
VP		 2614 * 2 buffer mode -
2615 * 2 buffer mode provides 128
da6971d8 2616 * byte aligned receive buffers.
da6971d8
AR		 2617 */
2618
d44570e4 2619 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2620 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2621 Buffer0_ptr = rxdp3->Buffer0_ptr;
2622 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2623 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2624 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2625 rxdp3->Buffer0_ptr = Buffer0_ptr;
2626 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2627
0425b46a 2628 ba = &ring->ba[block_no][off];
da6971d8 2629 skb_reserve(skb, BUF0_LEN);
d44570e4 2630 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2631 tmp += ALIGN_SIZE;
2632 tmp &= ~ALIGN_SIZE;
2633 skb->data = (void *) (unsigned long)tmp;
27a884dc 2634 skb_reset_tail_pointer(skb);
da6971d8 2635
3f78d885 2636 if (from_card_up) {
6d517a27 2637 rxdp3->Buffer0_ptr =
d44570e4
JP		 2638 pci_map_single(ring->pdev, ba->ba_0,
2639 BUF0_LEN,
2640 PCI_DMA_FROMDEVICE);
2641 if (pci_dma_mapping_error(nic->pdev,
2642 rxdp3->Buffer0_ptr))
3f78d885
SH		 2643 goto pci_map_failed;
2644 } else
0425b46a 2645 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2646 (dma_addr_t)rxdp3->Buffer0_ptr,
2647 BUF0_LEN,
2648 PCI_DMA_FROMDEVICE);
491abf25 2649
da6971d8 2650 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2651 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2652 /* Two buffer mode */
2653
2654 /*
6aa20a22 2655 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2656 * L4 payload
2657 */
d44570e4
JP		 2658 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2659 skb->data,
2660 ring->mtu + 4,
2661 PCI_DMA_FROMDEVICE);
da6971d8 2662
8d8bb39b 2663 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2664 rxdp3->Buffer2_ptr))
491abf25
VP		 2665 goto pci_map_failed;
2666
3f78d885 2667 if (from_card_up) {
0425b46a
SH		 2668 rxdp3->Buffer1_ptr =
2669 pci_map_single(ring->pdev,
d44570e4
JP		 2670 ba->ba_1,
2671 BUF1_LEN,
2672 PCI_DMA_FROMDEVICE);
0425b46a 2673
8d8bb39b 2674 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2675 rxdp3->Buffer1_ptr)) {
2676 pci_unmap_single(ring->pdev,
2677 (dma_addr_t)(unsigned long)
2678 skb->data,
2679 ring->mtu + 4,
2680 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2681 goto pci_map_failed;
2682 }
75c30b13 2683 }
da6971d8
AR		 2684 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2685 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2686 (ring->mtu + 4);
da6971d8 2687 }
b7b5a128 2688 rxdp->Control_2 |= s2BIT(0);
0425b46a 2689 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2690 }
303bcb4b 2691 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2692 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2693 off++;
0425b46a 2694 if (off == (ring->rxd_count + 1))
da6971d8 2695 off = 0;
0425b46a 2696 ring->rx_curr_put_info.offset = off;
20346722 2697
da6971d8 2698 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2699 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2700 if (first_rxdp) {
2701 wmb();
2702 first_rxdp->Control_1 |= RXD_OWN_XENA;
2703 }
2704 first_rxdp = rxdp;
2705 }
0425b46a 2706 ring->rx_bufs_left += 1;
1da177e4
LT		 2707 alloc_tab++;
2708 }
2709
d44570e4 2710end:
303bcb4b 2711 /* Transfer ownership of first descriptor to adapter just before
2712 * exiting. Before that, use memory barrier so that ownership
2713 * and other fields are seen by adapter correctly.
2714 */
2715 if (first_rxdp) {
2716 wmb();
2717 first_rxdp->Control_1 |= RXD_OWN_XENA;
2718 }
2719
1da177e4 2720 return SUCCESS;
d44570e4 2721
491abf25 2722pci_map_failed:
ffb5df6c
JP		 2723 swstats->pci_map_fail_cnt++;
2724 swstats->mem_freed += skb->truesize;
491abf25
VP		 2725 dev_kfree_skb_irq(skb);
2726 return -ENOMEM;
1da177e4
LT		 2727}
2728
da6971d8
AR		 2729static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2730{
2731 struct net_device *dev = sp->dev;
2732 int j;
2733 struct sk_buff *skb;
1ee6dd77 2734 struct RxD_t *rxdp;
1ee6dd77 2735 struct buffAdd *ba;
6d517a27
VP		 2736 struct RxD1 *rxdp1;
2737 struct RxD3 *rxdp3;
ffb5df6c
JP		 2738 struct mac_info *mac_control = &sp->mac_control;
2739 struct stat_block *stats = mac_control->stats_info;
2740 struct swStat *swstats = &stats->sw_stat;
da6971d8 2741
da6971d8
AR		 2742 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2743 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2744 rx_blocks[blk].rxds[j].virt_addr;
2745 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2746 if (!skb)
da6971d8 2747 continue;
da6971d8 2748 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2749 rxdp1 = (struct RxD1 *)rxdp;
2750 pci_unmap_single(sp->pdev,
2751 (dma_addr_t)rxdp1->Buffer0_ptr,
2752 dev->mtu +
2753 HEADER_ETHERNET_II_802_3_SIZE +
2754 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2755 PCI_DMA_FROMDEVICE);
1ee6dd77 2756 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2757 } else if (sp->rxd_mode == RXD_MODE_3B) {
2758 rxdp3 = (struct RxD3 *)rxdp;
2759 ba = &mac_control->rings[ring_no].ba[blk][j];
2760 pci_unmap_single(sp->pdev,
2761 (dma_addr_t)rxdp3->Buffer0_ptr,
2762 BUF0_LEN,
2763 PCI_DMA_FROMDEVICE);
2764 pci_unmap_single(sp->pdev,
2765 (dma_addr_t)rxdp3->Buffer1_ptr,
2766 BUF1_LEN,
2767 PCI_DMA_FROMDEVICE);
2768 pci_unmap_single(sp->pdev,
2769 (dma_addr_t)rxdp3->Buffer2_ptr,
2770 dev->mtu + 4,
2771 PCI_DMA_FROMDEVICE);
1ee6dd77 2772 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2773 }
ffb5df6c 2774 swstats->mem_freed += skb->truesize;
da6971d8 2775 dev_kfree_skb(skb);
0425b46a 2776 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2777 }
2778}
2779
1da177e4 2780/**
20346722 2781 * free_rx_buffers - Frees all Rx buffers
1da177e4 2782 * @sp: device private variable.
20346722 2783 * Description:
1da177e4
LT		 2784 * This function will free all Rx buffers allocated by host.
2785 * Return Value:
2786 * NONE.
2787 */
2788
2789static void free_rx_buffers(struct s2io_nic *sp)
2790{
2791 struct net_device *dev = sp->dev;
da6971d8 2792 int i, blk = 0, buf_cnt = 0;
ffb5df6c
JP		 2793 struct config_param *config = &sp->config;
2794 struct mac_info *mac_control = &sp->mac_control;
1da177e4
LT		 2795
2796 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2797 struct ring_info *ring = &mac_control->rings[i];
2798
da6971d8 2799 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2800 free_rxd_blk(sp, i, blk);
1da177e4 2801
13d866a9
JP		 2802 ring->rx_curr_put_info.block_index = 0;
2803 ring->rx_curr_get_info.block_index = 0;
2804 ring->rx_curr_put_info.offset = 0;
2805 ring->rx_curr_get_info.offset = 0;
2806 ring->rx_bufs_left = 0;
9e39f7c5 2807 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
1da177e4
LT		 2808 dev->name, buf_cnt, i);
2809 }
2810}
2811
8d8bb39b 2812static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2813{
8d8bb39b 2814 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2815 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2816 ring->dev->name);
f61e0a35
SH		 2817 }
2818 return 0;
2819}
2820
1da177e4
LT		 2821/**
2822 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2823 * @napi : pointer to the napi structure.
20346722 2824 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2825 * during one pass through the 'Poll" function.
2826 * Description:
2827 * Comes into picture only if NAPI support has been incorporated. It does
2828 * the same thing that rx_intr_handler does, but not in a interrupt context
2829 * also It will process only a given number of packets.
2830 * Return value:
2831 * 0 on success and 1 if there are No Rx packets to be processed.
2832 */
2833
f61e0a35 2834static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2835{
f61e0a35
SH		 2836 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2837 struct net_device *dev = ring->dev;
f61e0a35 2838 int pkts_processed = 0;
1a79d1c3
AV		 2839 u8 __iomem *addr = NULL;
2840 u8 val8 = 0;
4cf1653a 2841 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2842 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2843 int budget_org = budget;
1da177e4 2844
f61e0a35
SH		 2845 if (unlikely(!is_s2io_card_up(nic)))
2846 return 0;
1da177e4 2847
f61e0a35 2848 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2849 s2io_chk_rx_buffers(nic, ring);
1da177e4 2850
f61e0a35 2851 if (pkts_processed < budget_org) {
288379f0 2852 napi_complete(napi);
f61e0a35 2853 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2854 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2855 addr += 7 - ring->ring_no;
2856 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2857 writeb(val8, addr);
2858 val8 = readb(addr);
1da177e4 2859 }
f61e0a35
SH		 2860 return pkts_processed;
2861}
d44570e4 2862
f61e0a35
SH		 2863static int s2io_poll_inta(struct napi_struct *napi, int budget)
2864{
2865 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2866 int pkts_processed = 0;
2867 int ring_pkts_processed, i;
2868 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2869 int budget_org = budget;
ffb5df6c
JP		 2870 struct config_param *config = &nic->config;
2871 struct mac_info *mac_control = &nic->mac_control;
1da177e4 2872
f61e0a35
SH		 2873 if (unlikely(!is_s2io_card_up(nic)))
2874 return 0;
1da177e4 2875
1da177e4 2876 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2877 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2878 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2879 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2880 pkts_processed += ring_pkts_processed;
2881 budget -= ring_pkts_processed;
2882 if (budget <= 0)
1da177e4 2883 break;
1da177e4 2884 }
f61e0a35 2885 if (pkts_processed < budget_org) {
288379f0 2886 napi_complete(napi);
f61e0a35
SH		 2887 /* Re enable the Rx interrupts for the ring */
2888 writeq(0, &bar0->rx_traffic_mask);
2889 readl(&bar0->rx_traffic_mask);
2890 }
2891 return pkts_processed;
1da177e4 2892}
20346722 2893
b41477f3 2894#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2895/**
b41477f3 2896 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2897 * @dev : pointer to the device structure.
2898 * Description:
b41477f3
AR		 2899 * This function will be called by upper layer to check for events on the
2900 * interface in situations where interrupts are disabled. It is used for
2901 * specific in-kernel networking tasks, such as remote consoles and kernel
2902 * debugging over the network (example netdump in RedHat).
612eff0e 2903 */
612eff0e
BH		 2904static void s2io_netpoll(struct net_device *dev)
2905{
4cf1653a 2906 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2907 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2908 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e 2909 int i;
ffb5df6c
JP		 2910 struct config_param *config = &nic->config;
2911 struct mac_info *mac_control = &nic->mac_control;
612eff0e 2912
d796fdb7
LV		 2913 if (pci_channel_offline(nic->pdev))
2914 return;
2915
612eff0e
BH		 2916 disable_irq(dev->irq);
2917
612eff0e 2918 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2919 writeq(val64, &bar0->tx_traffic_int);
2920
6aa20a22 2921 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2922 * run out of skbs and will fail and eventually netpoll application such
2923 * as netdump will fail.
2924 */
2925 for (i = 0; i < config->tx_fifo_num; i++)
2926 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2927
b41477f3 2928 /* check for received packet and indicate up to network */
13d866a9
JP		 2929 for (i = 0; i < config->rx_ring_num; i++) {
2930 struct ring_info *ring = &mac_control->rings[i];
2931
2932 rx_intr_handler(ring, 0);
2933 }
612eff0e
BH		 2934
2935 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2936 struct ring_info *ring = &mac_control->rings[i];
2937
2938 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
9e39f7c5
JP		 2939 DBG_PRINT(INFO_DBG,
2940 "%s: Out of memory in Rx Netpoll!!\n",
2941 dev->name);
612eff0e
BH		 2942 break;
2943 }
2944 }
612eff0e 2945 enable_irq(dev->irq);
612eff0e
BH		 2946}
2947#endif
2948
20346722 2949/**
1da177e4 2950 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2951 * @ring_info: per ring structure.
2952 * @budget: budget for napi processing.
20346722 2953 * Description:
2954 * If the interrupt is because of a received frame or if the
1da177e4 2955 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2956 * called. It picks out the RxD at which place the last Rx processing had
2957 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2958 * the offset.
2959 * Return Value:
f61e0a35 2960 * No. of napi packets processed.
1da177e4 2961 */
f61e0a35 2962static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2963{
c9fcbf47 2964 int get_block, put_block;
1ee6dd77
RB		 2965 struct rx_curr_get_info get_info, put_info;
2966 struct RxD_t *rxdp;
1da177e4 2967 struct sk_buff *skb;
f61e0a35 2968 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2969 int i;
d44570e4
JP		 2970 struct RxD1 *rxdp1;
2971 struct RxD3 *rxdp3;
7d3d0439 2972
20346722 2973 get_info = ring_data->rx_curr_get_info;
2974 get_block = get_info.block_index;
1ee6dd77 2975 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2976 put_block = put_info.block_index;
da6971d8 2977 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2978
da6971d8 2979 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2980 /*
2981 * If your are next to put index then it's
2982 * FIFO full condition
2983 */
da6971d8
AR		 2984 if ((get_block == put_block) &&
2985 (get_info.offset + 1) == put_info.offset) {
0425b46a 2986 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 2987 ring_data->dev->name);
da6971d8
AR		 2988 break;
2989 }
d44570e4 2990 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722 2991 if (skb == NULL) {
9e39f7c5 2992 DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
0425b46a 2993 ring_data->dev->name);
f61e0a35 2994 return 0;
1da177e4 2995 }
0425b46a 2996 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 2997 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 2998 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 2999 rxdp1->Buffer0_ptr,
3000 ring_data->mtu +
3001 HEADER_ETHERNET_II_802_3_SIZE +
3002 HEADER_802_2_SIZE +
3003 HEADER_SNAP_SIZE,
3004 PCI_DMA_FROMDEVICE);
0425b46a 3005 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 3006 rxdp3 = (struct RxD3 *)rxdp;
3007 pci_dma_sync_single_for_cpu(ring_data->pdev,
3008 (dma_addr_t)rxdp3->Buffer0_ptr,
3009 BUF0_LEN,
3010 PCI_DMA_FROMDEVICE);
3011 pci_unmap_single(ring_data->pdev,
3012 (dma_addr_t)rxdp3->Buffer2_ptr,
3013 ring_data->mtu + 4,
3014 PCI_DMA_FROMDEVICE);
da6971d8 3015 }
863c11a9 3016 prefetch(skb->data);
20346722 3017 rx_osm_handler(ring_data, rxdp);
3018 get_info.offset++;
da6971d8
AR		 3019 ring_data->rx_curr_get_info.offset = get_info.offset;
3020 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3021 rxds[get_info.offset].virt_addr;
0425b46a 3022 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3023 get_info.offset = 0;
da6971d8 3024 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3025 get_block++;
da6971d8
AR		 3026 if (get_block == ring_data->block_count)
3027 get_block = 0;
3028 ring_data->rx_curr_get_info.block_index = get_block;
20346722 3029 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3030 }
1da177e4 3031
f61e0a35
SH		 3032 if (ring_data->nic->config.napi) {
3033 budget--;
3034 napi_pkts++;
3035 if (!budget)
0425b46a
SH		 3036 break;
3037 }
20346722 3038 pkt_cnt++;
1da177e4
LT		 3039 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3040 break;
3041 }
0425b46a 3042 if (ring_data->lro) {
7d3d0439 3043 /* Clear all LRO sessions before exiting */
d44570e4 3044 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3045 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3046 if (lro->in_use) {
0425b46a 3047 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3048 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3049 clear_lro_session(lro);
3050 }
3051 }
3052 }
d44570e4 3053 return napi_pkts;
1da177e4 3054}
20346722 3055
3056/**
1da177e4
LT		 3057 * tx_intr_handler - Transmit interrupt handler
3058 * @nic : device private variable
20346722 3059 * Description:
3060 * If an interrupt was raised to indicate DMA complete of the
3061 * Tx packet, this function is called. It identifies the last TxD
3062 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3063 * DMA'ed into the NICs internal memory.
3064 * Return Value:
3065 * NONE
3066 */
3067
1ee6dd77 3068static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3069{
1ee6dd77 3070 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3071 struct tx_curr_get_info get_info, put_info;
3a3d5756 3072 struct sk_buff *skb = NULL;
1ee6dd77 3073 struct TxD *txdlp;
3a3d5756 3074 int pkt_cnt = 0;
2fda096d 3075 unsigned long flags = 0;
f9046eb3 3076 u8 err_mask;
ffb5df6c
JP		 3077 struct stat_block *stats = nic->mac_control.stats_info;
3078 struct swStat *swstats = &stats->sw_stat;
1da177e4 3079
2fda096d 3080 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3081 return;
2fda096d 3082
20346722 3083 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3084 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
d44570e4
JP		 3085 txdlp = (struct TxD *)
3086 fifo_data->list_info[get_info.offset].list_virt_addr;
20346722 3087 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3088 (get_info.offset != put_info.offset) &&
3089 (txdlp->Host_Control)) {
3090 /* Check for TxD errors */
3091 if (txdlp->Control_1 & TXD_T_CODE) {
3092 unsigned long long err;
3093 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0 3094 if (err & 0x1) {
ffb5df6c 3095 swstats->parity_err_cnt++;
bd1034f0 3096 }
491976b2
SH		 3097
3098 /* update t_code statistics */
f9046eb3 3099 err_mask = err >> 48;
d44570e4
JP		 3100 switch (err_mask) {
3101 case 2:
ffb5df6c 3102 swstats->tx_buf_abort_cnt++;
491976b2
SH		 3103 break;
3104
d44570e4 3105 case 3:
ffb5df6c 3106 swstats->tx_desc_abort_cnt++;
491976b2
SH		 3107 break;
3108
d44570e4 3109 case 7:
ffb5df6c 3110 swstats->tx_parity_err_cnt++;
491976b2
SH		 3111 break;
3112
d44570e4 3113 case 10:
ffb5df6c 3114 swstats->tx_link_loss_cnt++;
491976b2
SH		 3115 break;
3116
d44570e4 3117 case 15:
ffb5df6c 3118 swstats->tx_list_proc_err_cnt++;
491976b2 3119 break;
d44570e4 3120 }
20346722 3121 }
1da177e4 3122
fed5eccd 3123 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3124 if (skb == NULL) {
2fda096d 3125 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
9e39f7c5
JP		 3126 DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3127 __func__);
20346722 3128 return;
3129 }
3a3d5756 3130 pkt_cnt++;
20346722 3131
20346722 3132 /* Updating the statistics block */
ffb5df6c 3133 swstats->mem_freed += skb->truesize;
20346722 3134 dev_kfree_skb_irq(skb);
3135
3136 get_info.offset++;
863c11a9
AR		 3137 if (get_info.offset == get_info.fifo_len + 1)
3138 get_info.offset = 0;
d44570e4
JP		 3139 txdlp = (struct TxD *)
3140 fifo_data->list_info[get_info.offset].list_virt_addr;
3141 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3142 }
3143
3a3d5756 3144 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3145
3146 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3147}
3148
bd1034f0
AR		 3149/**
3150 * s2io_mdio_write - Function to write in to MDIO registers
3151 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3152 * @addr : address value
3153 * @value : data value
3154 * @dev : pointer to net_device structure
3155 * Description:
3156 * This function is used to write values to the MDIO registers
3157 * NONE
3158 */
d44570e4
JP		 3159static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3160 struct net_device *dev)
bd1034f0 3161{
d44570e4 3162 u64 val64;
4cf1653a 3163 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3164 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3165
d44570e4
JP		 3166 /* address transaction */
3167 val64 = MDIO_MMD_INDX_ADDR(addr) |
3168 MDIO_MMD_DEV_ADDR(mmd_type) |
3169 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3170 writeq(val64, &bar0->mdio_control);
3171 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3172 writeq(val64, &bar0->mdio_control);
3173 udelay(100);
3174
d44570e4
JP		 3175 /* Data transaction */
3176 val64 = MDIO_MMD_INDX_ADDR(addr) |
3177 MDIO_MMD_DEV_ADDR(mmd_type) |
3178 MDIO_MMS_PRT_ADDR(0x0) |
3179 MDIO_MDIO_DATA(value) |
3180 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3181 writeq(val64, &bar0->mdio_control);
3182 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3183 writeq(val64, &bar0->mdio_control);
3184 udelay(100);
3185
d44570e4
JP		 3186 val64 = MDIO_MMD_INDX_ADDR(addr) |
3187 MDIO_MMD_DEV_ADDR(mmd_type) |
3188 MDIO_MMS_PRT_ADDR(0x0) |
3189 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3190 writeq(val64, &bar0->mdio_control);
3191 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3192 writeq(val64, &bar0->mdio_control);
3193 udelay(100);
bd1034f0
AR		 3194}
3195
3196/**
3197 * s2io_mdio_read - Function to write in to MDIO registers
3198 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3199 * @addr : address value
3200 * @dev : pointer to net_device structure
3201 * Description:
3202 * This function is used to read values to the MDIO registers
3203 * NONE
3204 */
3205static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3206{
3207 u64 val64 = 0x0;
3208 u64 rval64 = 0x0;
4cf1653a 3209 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3210 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3211
3212 /* address transaction */
d44570e4
JP		 3213 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3214 | MDIO_MMD_DEV_ADDR(mmd_type)
3215 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3216 writeq(val64, &bar0->mdio_control);
3217 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3218 writeq(val64, &bar0->mdio_control);
3219 udelay(100);
3220
3221 /* Data transaction */
d44570e4
JP		 3222 val64 = MDIO_MMD_INDX_ADDR(addr) |
3223 MDIO_MMD_DEV_ADDR(mmd_type) |
3224 MDIO_MMS_PRT_ADDR(0x0) |
3225 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3226 writeq(val64, &bar0->mdio_control);
3227 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3228 writeq(val64, &bar0->mdio_control);
3229 udelay(100);
3230
3231 /* Read the value from regs */
3232 rval64 = readq(&bar0->mdio_control);
3233 rval64 = rval64 & 0xFFFF0000;
3234 rval64 = rval64 >> 16;
3235 return rval64;
3236}
d44570e4 3237
bd1034f0
AR		 3238/**
3239 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
fbfecd37 3240 * @counter : counter value to be updated
bd1034f0
AR		 3241 * @flag : flag to indicate the status
3242 * @type : counter type
3243 * Description:
3244 * This function is to check the status of the xpak counters value
3245 * NONE
3246 */
3247
d44570e4
JP		 3248static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3249 u16 flag, u16 type)
bd1034f0
AR		 3250{
3251 u64 mask = 0x3;
3252 u64 val64;
3253 int i;
d44570e4 3254 for (i = 0; i < index; i++)
bd1034f0
AR		 3255 mask = mask << 0x2;
3256
d44570e4 3257 if (flag > 0) {
bd1034f0
AR		 3258 *counter = *counter + 1;
3259 val64 = *regs_stat & mask;
3260 val64 = val64 >> (index * 0x2);
3261 val64 = val64 + 1;
d44570e4
JP		 3262 if (val64 == 3) {
3263 switch (type) {
bd1034f0 3264 case 1:
9e39f7c5
JP		 3265 DBG_PRINT(ERR_DBG,
3266 "Take Xframe NIC out of service.\n");
3267 DBG_PRINT(ERR_DBG,
3268"Excessive temperatures may result in premature transceiver failure.\n");
d44570e4 3269 break;
bd1034f0 3270 case 2:
9e39f7c5
JP		 3271 DBG_PRINT(ERR_DBG,
3272 "Take Xframe NIC out of service.\n");
3273 DBG_PRINT(ERR_DBG,
3274"Excessive bias currents may indicate imminent laser diode failure.\n");
d44570e4 3275 break;
bd1034f0 3276 case 3:
9e39f7c5
JP		 3277 DBG_PRINT(ERR_DBG,
3278 "Take Xframe NIC out of service.\n");
3279 DBG_PRINT(ERR_DBG,
3280"Excessive laser output power may saturate far-end receiver.\n");
d44570e4 3281 break;
bd1034f0 3282 default:
d44570e4
JP		 3283 DBG_PRINT(ERR_DBG,
3284 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3285 }
3286 val64 = 0x0;
3287 }
3288 val64 = val64 << (index * 0x2);
3289 *regs_stat = (*regs_stat & (~mask)) | (val64);
3290
3291 } else {
3292 *regs_stat = *regs_stat & (~mask);
3293 }
3294}
3295
3296/**
3297 * s2io_updt_xpak_counter - Function to update the xpak counters
3298 * @dev : pointer to net_device struct
3299 * Description:
3300 * This function is to upate the status of the xpak counters value
3301 * NONE
3302 */
3303static void s2io_updt_xpak_counter(struct net_device *dev)
3304{
3305 u16 flag = 0x0;
3306 u16 type = 0x0;
3307 u16 val16 = 0x0;
3308 u64 val64 = 0x0;
3309 u64 addr = 0x0;
3310
4cf1653a 3311 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 3312 struct stat_block *stats = sp->mac_control.stats_info;
3313 struct xpakStat *xstats = &stats->xpak_stat;
bd1034f0
AR		 3314
3315 /* Check the communication with the MDIO slave */
40239396 3316 addr = MDIO_CTRL1;
bd1034f0 3317 val64 = 0x0;
40239396 3318 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3319 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
9e39f7c5
JP		 3320 DBG_PRINT(ERR_DBG,
3321 "ERR: MDIO slave access failed - Returned %llx\n",
3322 (unsigned long long)val64);
bd1034f0
AR		 3323 return;
3324 }
3325
40239396 3326 /* Check for the expected value of control reg 1 */
d44570e4 3327 if (val64 != MDIO_CTRL1_SPEED10G) {
9e39f7c5
JP		 3328 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3329 "Returned: %llx- Expected: 0x%x\n",
40239396 3330 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3331 return;
3332 }
3333
3334 /* Loading the DOM register to MDIO register */
3335 addr = 0xA100;
40239396
BH		 3336 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3337 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3338
3339 /* Reading the Alarm flags */
3340 addr = 0xA070;
3341 val64 = 0x0;
40239396 3342 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3343
3344 flag = CHECKBIT(val64, 0x7);
3345 type = 1;
ffb5df6c
JP		 3346 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3347 &xstats->xpak_regs_stat,
d44570e4 3348 0x0, flag, type);
bd1034f0 3349
d44570e4 3350 if (CHECKBIT(val64, 0x6))
ffb5df6c 3351 xstats->alarm_transceiver_temp_low++;
bd1034f0
AR		 3352
3353 flag = CHECKBIT(val64, 0x3);
3354 type = 2;
ffb5df6c
JP		 3355 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3356 &xstats->xpak_regs_stat,
d44570e4 3357 0x2, flag, type);
bd1034f0 3358
d44570e4 3359 if (CHECKBIT(val64, 0x2))
ffb5df6c 3360 xstats->alarm_laser_bias_current_low++;
bd1034f0
AR		 3361
3362 flag = CHECKBIT(val64, 0x1);
3363 type = 3;
ffb5df6c
JP		 3364 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3365 &xstats->xpak_regs_stat,
d44570e4 3366 0x4, flag, type);
bd1034f0 3367
d44570e4 3368 if (CHECKBIT(val64, 0x0))
ffb5df6c 3369 xstats->alarm_laser_output_power_low++;
bd1034f0
AR		 3370
3371 /* Reading the Warning flags */
3372 addr = 0xA074;
3373 val64 = 0x0;
40239396 3374 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3375
d44570e4 3376 if (CHECKBIT(val64, 0x7))
ffb5df6c 3377 xstats->warn_transceiver_temp_high++;
bd1034f0 3378
d44570e4 3379 if (CHECKBIT(val64, 0x6))
ffb5df6c 3380 xstats->warn_transceiver_temp_low++;
bd1034f0 3381
d44570e4 3382 if (CHECKBIT(val64, 0x3))
ffb5df6c 3383 xstats->warn_laser_bias_current_high++;
bd1034f0 3384
d44570e4 3385 if (CHECKBIT(val64, 0x2))
ffb5df6c 3386 xstats->warn_laser_bias_current_low++;
bd1034f0 3387
d44570e4 3388 if (CHECKBIT(val64, 0x1))
ffb5df6c 3389 xstats->warn_laser_output_power_high++;
bd1034f0 3390
d44570e4 3391 if (CHECKBIT(val64, 0x0))
ffb5df6c 3392 xstats->warn_laser_output_power_low++;
bd1034f0
AR		 3393}
3394
20346722 3395/**
1da177e4 3396 * wait_for_cmd_complete - waits for a command to complete.
20346722 3397 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3398 * s2io_nic structure.
20346722 3399 * Description: Function that waits for a command to Write into RMAC
3400 * ADDR DATA registers to be completed and returns either success or
3401 * error depending on whether the command was complete or not.
1da177e4
LT		 3402 * Return value:
3403 * SUCCESS on success and FAILURE on failure.
3404 */
3405
9fc93a41 3406static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3407 int bit_state)
1da177e4 3408{
9fc93a41 3409 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3410 u64 val64;
3411
9fc93a41
SS		 3412 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3413 return FAILURE;
3414
3415 do {
c92ca04b 3416 val64 = readq(addr);
9fc93a41
SS		 3417 if (bit_state == S2IO_BIT_RESET) {
3418 if (!(val64 & busy_bit)) {
3419 ret = SUCCESS;
3420 break;
3421 }
3422 } else {
2d146eb1 3423 if (val64 & busy_bit) {
9fc93a41
SS		 3424 ret = SUCCESS;
3425 break;
3426 }
1da177e4 3427 }
c92ca04b 3428
d44570e4 3429 if (in_interrupt())
9fc93a41 3430 mdelay(delay);
c92ca04b 3431 else
9fc93a41 3432 msleep(delay);
c92ca04b 3433
9fc93a41
SS		 3434 if (++cnt >= 10)
3435 delay = 50;
3436 } while (cnt < 20);
1da177e4
LT		 3437 return ret;
3438}
19a60522
SS		 3439/*
3440 * check_pci_device_id - Checks if the device id is supported
3441 * @id : device id
3442 * Description: Function to check if the pci device id is supported by driver.
3443 * Return value: Actual device id if supported else PCI_ANY_ID
3444 */
3445static u16 check_pci_device_id(u16 id)
3446{
3447 switch (id) {
3448 case PCI_DEVICE_ID_HERC_WIN:
3449 case PCI_DEVICE_ID_HERC_UNI:
3450 return XFRAME_II_DEVICE;
3451 case PCI_DEVICE_ID_S2IO_UNI:
3452 case PCI_DEVICE_ID_S2IO_WIN:
3453 return XFRAME_I_DEVICE;
3454 default:
3455 return PCI_ANY_ID;
3456 }
3457}
1da177e4 3458
20346722 3459/**
3460 * s2io_reset - Resets the card.
1da177e4
LT		 3461 * @sp : private member of the device structure.
3462 * Description: Function to Reset the card. This function then also
20346722 3463 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3464 * the card reset also resets the configuration space.
3465 * Return value:
3466 * void.
3467 */
3468
d44570e4 3469static void s2io_reset(struct s2io_nic *sp)
1da177e4 3470{
1ee6dd77 3471 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3472 u64 val64;
5e25b9dd 3473 u16 subid, pci_cmd;
19a60522
SS		 3474 int i;
3475 u16 val16;
491976b2
SH		 3476 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3477 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
ffb5df6c
JP		 3478 struct stat_block *stats;
3479 struct swStat *swstats;
491976b2 3480
9e39f7c5 3481 DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3a22813a 3482 __func__, pci_name(sp->pdev));
1da177e4 3483
0b1f7ebe 3484 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3485 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3486
1da177e4
LT		 3487 val64 = SW_RESET_ALL;
3488 writeq(val64, &bar0->sw_reset);
d44570e4 3489 if (strstr(sp->product_name, "CX4"))
c92ca04b 3490 msleep(750);
19a60522
SS		 3491 msleep(250);
3492 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3493
19a60522
SS		 3494 /* Restore the PCI state saved during initialization. */
3495 pci_restore_state(sp->pdev);
b8a623bf 3496 pci_save_state(sp->pdev);
19a60522
SS		 3497 pci_read_config_word(sp->pdev, 0x2, &val16);
3498 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3499 break;
3500 msleep(200);
3501 }
1da177e4 3502
d44570e4
JP		 3503 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3504 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3505
3506 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3507
3508 s2io_init_pci(sp);
1da177e4 3509
20346722 3510 /* Set swapper to enable I/O register access */
3511 s2io_set_swapper(sp);
3512
faa4f796
SH		 3513 /* restore mac_addr entries */
3514 do_s2io_restore_unicast_mc(sp);
3515
cc6e7c44
RA		 3516 /* Restore the MSIX table entries from local variables */
3517 restore_xmsi_data(sp);
3518
5e25b9dd 3519 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3520 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3521 /* Clear "detected parity error" bit */
303bcb4b 3522 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3523
303bcb4b 3524 /* Clearing PCIX Ecc status register */
3525 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3526
303bcb4b 3527 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3528 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3529 }
5e25b9dd 3530
20346722 3531 /* Reset device statistics maintained by OS */
d44570e4 3532 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3533
ffb5df6c
JP		 3534 stats = sp->mac_control.stats_info;
3535 swstats = &stats->sw_stat;
3536
491976b2 3537 /* save link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3538 up_cnt = swstats->link_up_cnt;
3539 down_cnt = swstats->link_down_cnt;
3540 up_time = swstats->link_up_time;
3541 down_time = swstats->link_down_time;
3542 reset_cnt = swstats->soft_reset_cnt;
3543 mem_alloc_cnt = swstats->mem_allocated;
3544 mem_free_cnt = swstats->mem_freed;
3545 watchdog_cnt = swstats->watchdog_timer_cnt;
3546
3547 memset(stats, 0, sizeof(struct stat_block));
3548
491976b2 3549 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3550 swstats->link_up_cnt = up_cnt;
3551 swstats->link_down_cnt = down_cnt;
3552 swstats->link_up_time = up_time;
3553 swstats->link_down_time = down_time;
3554 swstats->soft_reset_cnt = reset_cnt;
3555 swstats->mem_allocated = mem_alloc_cnt;
3556 swstats->mem_freed = mem_free_cnt;
3557 swstats->watchdog_timer_cnt = watchdog_cnt;
20346722 3558
1da177e4
LT		 3559 /* SXE-002: Configure link and activity LED to turn it off */
3560 subid = sp->pdev->subsystem_device;
541ae68f 3561 if (((subid & 0xFF) >= 0x07) &&
3562 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3563 val64 = readq(&bar0->gpio_control);
3564 val64 |= 0x0000800000000000ULL;
3565 writeq(val64, &bar0->gpio_control);
3566 val64 = 0x0411040400000000ULL;
509a2671 3567 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3568 }
3569
541ae68f 3570 /*
3571 * Clear spurious ECC interrupts that would have occured on
3572 * XFRAME II cards after reset.
3573 */
3574 if (sp->device_type == XFRAME_II_DEVICE) {
3575 val64 = readq(&bar0->pcc_err_reg);
3576 writeq(val64, &bar0->pcc_err_reg);
3577 }
3578
f957bcf0 3579 sp->device_enabled_once = false;
1da177e4
LT		 3580}
3581
3582/**
20346722 3583 * s2io_set_swapper - to set the swapper controle on the card
3584 * @sp : private member of the device structure,
1da177e4 3585 * pointer to the s2io_nic structure.
20346722 3586 * Description: Function to set the swapper control on the card
1da177e4
LT		 3587 * correctly depending on the 'endianness' of the system.
3588 * Return value:
3589 * SUCCESS on success and FAILURE on failure.
3590 */
3591
d44570e4 3592static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3593{
3594 struct net_device *dev = sp->dev;
1ee6dd77 3595 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3596 u64 val64, valt, valr;
3597
20346722 3598 /*
1da177e4
LT		 3599 * Set proper endian settings and verify the same by reading
3600 * the PIF Feed-back register.
3601 */
3602
3603 val64 = readq(&bar0->pif_rd_swapper_fb);
3604 if (val64 != 0x0123456789ABCDEFULL) {
3605 int i = 0;
3606 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3607 0x8100008181000081ULL, /* FE=1, SE=0 */
3608 0x4200004242000042ULL, /* FE=0, SE=1 */
3609 0}; /* FE=0, SE=0 */
3610
d44570e4 3611 while (i < 4) {
1da177e4
LT		 3612 writeq(value[i], &bar0->swapper_ctrl);
3613 val64 = readq(&bar0->pif_rd_swapper_fb);
3614 if (val64 == 0x0123456789ABCDEFULL)
3615 break;
3616 i++;
3617 }
3618 if (i == 4) {
9e39f7c5
JP		 3619 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3620 "feedback read %llx\n",
3621 dev->name, (unsigned long long)val64);
1da177e4
LT		 3622 return FAILURE;
3623 }
3624 valr = value[i];
3625 } else {
3626 valr = readq(&bar0->swapper_ctrl);
3627 }
3628
3629 valt = 0x0123456789ABCDEFULL;
3630 writeq(valt, &bar0->xmsi_address);
3631 val64 = readq(&bar0->xmsi_address);
3632
d44570e4 3633 if (val64 != valt) {
1da177e4
LT		 3634 int i = 0;
3635 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3636 0x0081810000818100ULL, /* FE=1, SE=0 */
3637 0x0042420000424200ULL, /* FE=0, SE=1 */
3638 0}; /* FE=0, SE=0 */
3639
d44570e4 3640 while (i < 4) {
1da177e4
LT		 3641 writeq((value[i] | valr), &bar0->swapper_ctrl);
3642 writeq(valt, &bar0->xmsi_address);
3643 val64 = readq(&bar0->xmsi_address);
d44570e4 3644 if (val64 == valt)
1da177e4
LT		 3645 break;
3646 i++;
3647 }
d44570e4 3648 if (i == 4) {
20346722 3649 unsigned long long x = val64;
9e39f7c5
JP		 3650 DBG_PRINT(ERR_DBG,
3651 "Write failed, Xmsi_addr reads:0x%llx\n", x);
1da177e4
LT		 3652 return FAILURE;
3653 }
3654 }
3655 val64 = readq(&bar0->swapper_ctrl);
3656 val64 &= 0xFFFF000000000000ULL;
3657
d44570e4 3658#ifdef __BIG_ENDIAN
20346722 3659 /*
3660 * The device by default set to a big endian format, so a
1da177e4
LT		 3661 * big endian driver need not set anything.
3662 */
3663 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3664 SWAPPER_CTRL_TXP_SE |
3665 SWAPPER_CTRL_TXD_R_FE |
3666 SWAPPER_CTRL_TXD_W_FE |
3667 SWAPPER_CTRL_TXF_R_FE |
3668 SWAPPER_CTRL_RXD_R_FE |
3669 SWAPPER_CTRL_RXD_W_FE |
3670 SWAPPER_CTRL_RXF_W_FE |
3671 SWAPPER_CTRL_XMSI_FE |
3672 SWAPPER_CTRL_STATS_FE |
3673 SWAPPER_CTRL_STATS_SE);
eaae7f72 3674 if (sp->config.intr_type == INTA)
cc6e7c44 3675 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3676 writeq(val64, &bar0->swapper_ctrl);
3677#else
20346722 3678 /*
1da177e4 3679 * Initially we enable all bits to make it accessible by the
20346722 3680 * driver, then we selectively enable only those bits that
1da177e4
LT		 3681 * we want to set.
3682 */
3683 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3684 SWAPPER_CTRL_TXP_SE |
3685 SWAPPER_CTRL_TXD_R_FE |
3686 SWAPPER_CTRL_TXD_R_SE |
3687 SWAPPER_CTRL_TXD_W_FE |
3688 SWAPPER_CTRL_TXD_W_SE |
3689 SWAPPER_CTRL_TXF_R_FE |
3690 SWAPPER_CTRL_RXD_R_FE |
3691 SWAPPER_CTRL_RXD_R_SE |
3692 SWAPPER_CTRL_RXD_W_FE |
3693 SWAPPER_CTRL_RXD_W_SE |
3694 SWAPPER_CTRL_RXF_W_FE |
3695 SWAPPER_CTRL_XMSI_FE |
3696 SWAPPER_CTRL_STATS_FE |
3697 SWAPPER_CTRL_STATS_SE);
eaae7f72 3698 if (sp->config.intr_type == INTA)
cc6e7c44 3699 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3700 writeq(val64, &bar0->swapper_ctrl);
3701#endif
3702 val64 = readq(&bar0->swapper_ctrl);
3703
20346722 3704 /*
3705 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3706 * feedback register.
3707 */
3708 val64 = readq(&bar0->pif_rd_swapper_fb);
3709 if (val64 != 0x0123456789ABCDEFULL) {
3710 /* Endian settings are incorrect, calls for another dekko. */
9e39f7c5
JP		 3711 DBG_PRINT(ERR_DBG,
3712 "%s: Endian settings are wrong, feedback read %llx\n",
3713 dev->name, (unsigned long long)val64);
1da177e4
LT		 3714 return FAILURE;
3715 }
3716
3717 return SUCCESS;
3718}
3719
1ee6dd77 3720static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3721{
1ee6dd77 3722 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3723 u64 val64;
3724 int ret = 0, cnt = 0;
3725
3726 do {
3727 val64 = readq(&bar0->xmsi_access);
b7b5a128 3728 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3729 break;
3730 mdelay(1);
3731 cnt++;
d44570e4 3732 } while (cnt < 5);
cc6e7c44
RA		 3733 if (cnt == 5) {
3734 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3735 ret = 1;
3736 }
3737
3738 return ret;
3739}
3740
1ee6dd77 3741static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3742{
1ee6dd77 3743 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3744 u64 val64;
f61e0a35
SH		 3745 int i, msix_index;
3746
f61e0a35
SH		 3747 if (nic->device_type == XFRAME_I_DEVICE)
3748 return;
cc6e7c44 3749
d44570e4
JP		 3750 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3751 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3752 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3753 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3754 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3755 writeq(val64, &bar0->xmsi_access);
f61e0a35 3756 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3757 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3758 __func__, msix_index);
cc6e7c44
RA		 3759 continue;
3760 }
3761 }
3762}
3763
1ee6dd77 3764static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3765{
1ee6dd77 3766 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3767 u64 val64, addr, data;
f61e0a35
SH		 3768 int i, msix_index;
3769
3770 if (nic->device_type == XFRAME_I_DEVICE)
3771 return;
cc6e7c44
RA		 3772
3773 /* Store and display */
d44570e4
JP		 3774 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3775 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3776 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3777 writeq(val64, &bar0->xmsi_access);
f61e0a35 3778 if (wait_for_msix_trans(nic, msix_index)) {
9e39f7c5
JP		 3779 DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3780 __func__, msix_index);
cc6e7c44
RA		 3781 continue;
3782 }
3783 addr = readq(&bar0->xmsi_address);
3784 data = readq(&bar0->xmsi_data);
3785 if (addr && data) {
3786 nic->msix_info[i].addr = addr;
3787 nic->msix_info[i].data = data;
3788 }
3789 }
3790}
3791
1ee6dd77 3792static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3793{
1ee6dd77 3794 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3795 u64 rx_mat;
cc6e7c44
RA		 3796 u16 msi_control; /* Temp variable */
3797 int ret, i, j, msix_indx = 1;
4f870320 3798 int size;
ffb5df6c
JP		 3799 struct stat_block *stats = nic->mac_control.stats_info;
3800 struct swStat *swstats = &stats->sw_stat;
cc6e7c44 3801
4f870320 3802 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3803 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3804 if (!nic->entries) {
d44570e4
JP		 3805 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3806 __func__);
ffb5df6c 3807 swstats->mem_alloc_fail_cnt++;
cc6e7c44
RA		 3808 return -ENOMEM;
3809 }
ffb5df6c 3810 swstats->mem_allocated += size;
f61e0a35 3811
4f870320 3812 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3813 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3814 if (!nic->s2io_entries) {
8a4bdbaa 3815 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3816 __func__);
ffb5df6c 3817 swstats->mem_alloc_fail_cnt++;
cc6e7c44 3818 kfree(nic->entries);
ffb5df6c 3819 swstats->mem_freed
f61e0a35 3820 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3821 return -ENOMEM;
3822 }
ffb5df6c 3823 swstats->mem_allocated += size;
cc6e7c44 3824
ac731ab6
SH		 3825 nic->entries[0].entry = 0;
3826 nic->s2io_entries[0].entry = 0;
3827 nic->s2io_entries[0].in_use = MSIX_FLG;
3828 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3829 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3830
f61e0a35
SH		 3831 for (i = 1; i < nic->num_entries; i++) {
3832 nic->entries[i].entry = ((i - 1) * 8) + 1;
3833 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3834 nic->s2io_entries[i].arg = NULL;
3835 nic->s2io_entries[i].in_use = 0;
3836 }
3837
8a4bdbaa 3838 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3839 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3840 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3841 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3842 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3843 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3844 msix_indx += 8;
cc6e7c44 3845 }
8a4bdbaa 3846 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3847 readq(&bar0->rx_mat);
cc6e7c44 3848
f61e0a35 3849 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3850 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3851 if (ret) {
9e39f7c5 3852 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
cc6e7c44 3853 kfree(nic->entries);
ffb5df6c
JP		 3854 swstats->mem_freed += nic->num_entries *
3855 sizeof(struct msix_entry);
cc6e7c44 3856 kfree(nic->s2io_entries);
ffb5df6c
JP		 3857 swstats->mem_freed += nic->num_entries *
3858 sizeof(struct s2io_msix_entry);
cc6e7c44
RA		 3859 nic->entries = NULL;
3860 nic->s2io_entries = NULL;
3861 return -ENOMEM;
3862 }
3863
3864 /*
3865 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3866 * in the herc NIC. (Temp change, needs to be removed later)
3867 */
3868 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3869 msi_control |= 0x1; /* Enable MSI */
3870 pci_write_config_word(nic->pdev, 0x42, msi_control);
3871
3872 return 0;
3873}
3874
8abc4d5b 3875/* Handle software interrupt used during MSI(X) test */
33390a70 3876static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3877{
3878 struct s2io_nic *sp = dev_id;
3879
3880 sp->msi_detected = 1;
3881 wake_up(&sp->msi_wait);
3882
3883 return IRQ_HANDLED;
3884}
3885
3886/* Test interrupt path by forcing a a software IRQ */
33390a70 3887static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3888{
3889 struct pci_dev *pdev = sp->pdev;
3890 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3891 int err;
3892 u64 val64, saved64;
3893
3894 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3895 sp->name, sp);
8abc4d5b
SS		 3896 if (err) {
3897 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3898 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3899 return err;
3900 }
3901
d44570e4 3902 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3903 sp->msi_detected = 0;
3904
3905 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3906 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3907 val64 |= SCHED_INT_CTRL_TIMER_EN;
3908 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3909 writeq(val64, &bar0->scheduled_int_ctrl);
3910
3911 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3912
3913 if (!sp->msi_detected) {
3914 /* MSI(X) test failed, go back to INTx mode */
2450022a 3915 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
9e39f7c5
JP		 3916 "using MSI(X) during test\n",
3917 sp->dev->name, pci_name(pdev));
8abc4d5b
SS		 3918
3919 err = -EOPNOTSUPP;
3920 }
3921
3922 free_irq(sp->entries[1].vector, sp);
3923
3924 writeq(saved64, &bar0->scheduled_int_ctrl);
3925
3926 return err;
3927}
18b2b7bd
SH		 3928
3929static void remove_msix_isr(struct s2io_nic *sp)
3930{
3931 int i;
3932 u16 msi_control;
3933
f61e0a35 3934 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3935 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3936 int vector = sp->entries[i].vector;
3937 void *arg = sp->s2io_entries[i].arg;
3938 free_irq(vector, arg);
3939 }
3940 }
3941
3942 kfree(sp->entries);
3943 kfree(sp->s2io_entries);
3944 sp->entries = NULL;
3945 sp->s2io_entries = NULL;
3946
3947 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3948 msi_control &= 0xFFFE; /* Disable MSI */
3949 pci_write_config_word(sp->pdev, 0x42, msi_control);
3950
3951 pci_disable_msix(sp->pdev);
3952}
3953
3954static void remove_inta_isr(struct s2io_nic *sp)
3955{
3956 struct net_device *dev = sp->dev;
3957
3958 free_irq(sp->pdev->irq, dev);
3959}
3960
1da177e4
LT		 3961/* ********************************************************* *
3962 * Functions defined below concern the OS part of the driver *
3963 * ********************************************************* */
3964
20346722 3965/**
1da177e4
LT		 3966 * s2io_open - open entry point of the driver
3967 * @dev : pointer to the device structure.
3968 * Description:
3969 * This function is the open entry point of the driver. It mainly calls a
3970 * function to allocate Rx buffers and inserts them into the buffer
20346722 3971 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3972 * Return value:
3973 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3974 * file on failure.
3975 */
3976
ac1f60db 3977static int s2io_open(struct net_device *dev)
1da177e4 3978{
4cf1653a 3979 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 3980 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3981 int err = 0;
3982
20346722 3983 /*
3984 * Make sure you have link off by default every time
1da177e4
LT		 3985 * Nic is initialized
3986 */
3987 netif_carrier_off(dev);
0b1f7ebe 3988 sp->last_link_state = 0;
1da177e4
LT		 3989
3990 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3991 err = s2io_card_up(sp);
3992 if (err) {
1da177e4
LT		 3993 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3994 dev->name);
e6a8fee2 3995 goto hw_init_failed;
1da177e4
LT		 3996 }
3997
2fd37688 3998 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 3999 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4000 s2io_card_down(sp);
20346722 4001 err = -ENODEV;
e6a8fee2 4002 goto hw_init_failed;
1da177e4 4003 }
3a3d5756 4004 s2io_start_all_tx_queue(sp);
1da177e4 4005 return 0;
20346722 4006
20346722 4007hw_init_failed:
eaae7f72 4008 if (sp->config.intr_type == MSI_X) {
491976b2 4009 if (sp->entries) {
cc6e7c44 4010 kfree(sp->entries);
ffb5df6c
JP		 4011 swstats->mem_freed += sp->num_entries *
4012 sizeof(struct msix_entry);
491976b2
SH		 4013 }
4014 if (sp->s2io_entries) {
cc6e7c44 4015 kfree(sp->s2io_entries);
ffb5df6c
JP		 4016 swstats->mem_freed += sp->num_entries *
4017 sizeof(struct s2io_msix_entry);
491976b2 4018 }
cc6e7c44 4019 }
20346722 4020 return err;
1da177e4
LT		 4021}
4022
4023/**
4024 * s2io_close -close entry point of the driver
4025 * @dev : device pointer.
4026 * Description:
4027 * This is the stop entry point of the driver. It needs to undo exactly
4028 * whatever was done by the open entry point,thus it's usually referred to
4029 * as the close function.Among other things this function mainly stops the
4030 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4031 * Return value:
4032 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4033 * file on failure.
4034 */
4035
ac1f60db 4036static int s2io_close(struct net_device *dev)
1da177e4 4037{
4cf1653a 4038 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4039 struct config_param *config = &sp->config;
4040 u64 tmp64;
4041 int offset;
cc6e7c44 4042
9f74ffde 4043 /* Return if the device is already closed *
d44570e4
JP		 4044 * Can happen when s2io_card_up failed in change_mtu *
4045 */
9f74ffde
SH		 4046 if (!is_s2io_card_up(sp))
4047 return 0;
4048
3a3d5756 4049 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4050 /* delete all populated mac entries */
4051 for (offset = 1; offset < config->max_mc_addr; offset++) {
4052 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4053 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4054 do_s2io_delete_unicast_mc(sp, tmp64);
4055 }
4056
e6a8fee2 4057 s2io_card_down(sp);
cc6e7c44 4058
1da177e4
LT		 4059 return 0;
4060}
4061
4062/**
4063 * s2io_xmit - Tx entry point of te driver
4064 * @skb : the socket buffer containing the Tx data.
4065 * @dev : device pointer.
4066 * Description :
4067 * This function is the Tx entry point of the driver. S2IO NIC supports
4068 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4069 * NOTE: when device cant queue the pkt,just the trans_start variable will
4070 * not be upadted.
4071 * Return value:
4072 * 0 on success & 1 on failure.
4073 */
4074
61357325 4075static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4076{
4cf1653a 4077 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4078 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4079 register u64 val64;
1ee6dd77
RB		 4080 struct TxD *txdp;
4081 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4082 unsigned long flags = 0;
be3a6b02 4083 u16 vlan_tag = 0;
2fda096d 4084 struct fifo_info *fifo = NULL;
6cfc482b 4085 int do_spin_lock = 1;
75c30b13 4086 int offload_type;
6cfc482b 4087 int enable_per_list_interrupt = 0;
ffb5df6c
JP		 4088 struct config_param *config = &sp->config;
4089 struct mac_info *mac_control = &sp->mac_control;
4090 struct stat_block *stats = mac_control->stats_info;
4091 struct swStat *swstats = &stats->sw_stat;
1da177e4 4092
20346722 4093 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4094
4095 if (unlikely(skb->len <= 0)) {
9e39f7c5 4096 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
491976b2 4097 dev_kfree_skb_any(skb);
6ed10654 4098 return NETDEV_TX_OK;
2fda096d 4099 }
491976b2 4100
92b84437 4101 if (!is_s2io_card_up(sp)) {
20346722 4102 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4103 dev->name);
20346722 4104 dev_kfree_skb(skb);
6ed10654 4105 return NETDEV_TX_OK;
1da177e4
LT		 4106 }
4107
4108 queue = 0;
3a3d5756 4109 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4110 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4111 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4112 if (skb->protocol == htons(ETH_P_IP)) {
4113 struct iphdr *ip;
4114 struct tcphdr *th;
4115 ip = ip_hdr(skb);
4116
4117 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4118 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4119 ip->ihl*4);
6cfc482b
SH		 4120
4121 if (ip->protocol == IPPROTO_TCP) {
4122 queue_len = sp->total_tcp_fifos;
4123 queue = (ntohs(th->source) +
d44570e4
JP		 4124 ntohs(th->dest)) &
4125 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4126 if (queue >= queue_len)
4127 queue = queue_len - 1;
4128 } else if (ip->protocol == IPPROTO_UDP) {
4129 queue_len = sp->total_udp_fifos;
4130 queue = (ntohs(th->source) +
d44570e4
JP		 4131 ntohs(th->dest)) &
4132 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4133 if (queue >= queue_len)
4134 queue = queue_len - 1;
4135 queue += sp->udp_fifo_idx;
4136 if (skb->len > 1024)
4137 enable_per_list_interrupt = 1;
4138 do_spin_lock = 0;
4139 }
4140 }
4141 }
4142 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4143 /* get fifo number based on skb->priority value */
4144 queue = config->fifo_mapping
d44570e4 4145 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4146 fifo = &mac_control->fifos[queue];
3a3d5756 4147
6cfc482b
SH		 4148 if (do_spin_lock)
4149 spin_lock_irqsave(&fifo->tx_lock, flags);
4150 else {
4151 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4152 return NETDEV_TX_LOCKED;
4153 }
be3a6b02 4154
3a3d5756
SH		 4155 if (sp->config.multiq) {
4156 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4157 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4158 return NETDEV_TX_BUSY;
4159 }
b19fa1fa 4160 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4161 if (netif_queue_stopped(dev)) {
4162 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4163 return NETDEV_TX_BUSY;
4164 }
4165 }
4166
d44570e4
JP		 4167 put_off = (u16)fifo->tx_curr_put_info.offset;
4168 get_off = (u16)fifo->tx_curr_get_info.offset;
4169 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
20346722 4170
2fda096d 4171 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4172 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4173 if (txdp->Host_Control ||
d44570e4 4174 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4175 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4176 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4177 dev_kfree_skb(skb);
2fda096d 4178 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4179 return NETDEV_TX_OK;
1da177e4 4180 }
0b1f7ebe 4181
75c30b13 4182 offload_type = s2io_offload_type(skb);
75c30b13 4183 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4184 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4185 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4186 }
84fa7933 4187 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4188 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4189 TXD_TX_CKO_TCP_EN |
4190 TXD_TX_CKO_UDP_EN);
1da177e4 4191 }
fed5eccd
AR		 4192 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4193 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4194 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4195 if (enable_per_list_interrupt)
4196 if (put_off & (queue_len >> 5))
4197 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4198 if (vlan_tag) {
be3a6b02 4199 txdp->Control_2 |= TXD_VLAN_ENABLE;
4200 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4201 }
4202
e743d313 4203 frg_len = skb_headlen(skb);
75c30b13 4204 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4205 int ufo_size;
4206
75c30b13 4207 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4208 ufo_size &= ~7;
4209 txdp->Control_1 |= TXD_UFO_EN;
4210 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4211 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4212#ifdef __BIG_ENDIAN
3459feb8 4213 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4214 fifo->ufo_in_band_v[put_off] =
d44570e4 4215 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4216#else
2fda096d 4217 fifo->ufo_in_band_v[put_off] =
d44570e4 4218 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4219#endif
2fda096d 4220 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4221 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4222 fifo->ufo_in_band_v,
4223 sizeof(u64),
4224 PCI_DMA_TODEVICE);
8d8bb39b 4225 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4226 goto pci_map_failed;
fed5eccd 4227 txdp++;
fed5eccd 4228 }
1da177e4 4229
d44570e4
JP		 4230 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4231 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4232 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4233 goto pci_map_failed;
4234
d44570e4 4235 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4236 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4237 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4238 txdp->Control_1 |= TXD_UFO_EN;
4239
4240 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4241 /* For fragmented SKB. */
4242 for (i = 0; i < frg_cnt; i++) {
4243 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 4244 /* A '0' length fragment will be ignored */
4245 if (!frag->size)
4246 continue;
1da177e4 4247 txdp++;
d44570e4
JP		 4248 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4249 frag->page_offset,
4250 frag->size,
4251 PCI_DMA_TODEVICE);
efd51b5c 4252 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4253 if (offload_type == SKB_GSO_UDP)
fed5eccd 4254 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4255 }
4256 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4257
75c30b13 4258 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4259 frg_cnt++; /* as Txd0 was used for inband header */
4260
1da177e4 4261 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4262 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4263 writeq(val64, &tx_fifo->TxDL_Pointer);
4264
4265 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4266 TX_FIFO_LAST_LIST);
75c30b13 4267 if (offload_type)
fed5eccd 4268 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4269
1da177e4
LT		 4270 writeq(val64, &tx_fifo->List_Control);
4271
303bcb4b 4272 mmiowb();
4273
1da177e4 4274 put_off++;
2fda096d 4275 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4276 put_off = 0;
2fda096d 4277 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4278
4279 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4280 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
ffb5df6c 4281 swstats->fifo_full_cnt++;
1da177e4
LT		 4282 DBG_PRINT(TX_DBG,
4283 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4284 put_off, get_off);
3a3d5756 4285 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4286 }
ffb5df6c 4287 swstats->mem_allocated += skb->truesize;
2fda096d 4288 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4289
f6f4bfa3
SH		 4290 if (sp->config.intr_type == MSI_X)
4291 tx_intr_handler(fifo);
4292
6ed10654 4293 return NETDEV_TX_OK;
ffb5df6c 4294
491abf25 4295pci_map_failed:
ffb5df6c 4296 swstats->pci_map_fail_cnt++;
3a3d5756 4297 s2io_stop_tx_queue(sp, fifo->fifo_no);
ffb5df6c 4298 swstats->mem_freed += skb->truesize;
491abf25 4299 dev_kfree_skb(skb);
2fda096d 4300 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4301 return NETDEV_TX_OK;
1da177e4
LT		 4302}
4303
25fff88e 4304static void
4305s2io_alarm_handle(unsigned long data)
4306{
1ee6dd77 4307 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4308 struct net_device *dev = sp->dev;
25fff88e 4309
8116f3cf 4310 s2io_handle_errors(dev);
25fff88e 4311 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4312}
4313
7d12e780 4314static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4315{
1ee6dd77
RB		 4316 struct ring_info *ring = (struct ring_info *)dev_id;
4317 struct s2io_nic *sp = ring->nic;
f61e0a35 4318 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4319
f61e0a35 4320 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4321 return IRQ_HANDLED;
92b84437 4322
f61e0a35 4323 if (sp->config.napi) {
1a79d1c3
AV		 4324 u8 __iomem *addr = NULL;
4325 u8 val8 = 0;
f61e0a35 4326
1a79d1c3 4327 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4328 addr += (7 - ring->ring_no);
4329 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4330 writeb(val8, addr);
4331 val8 = readb(addr);
288379f0 4332 napi_schedule(&ring->napi);
f61e0a35
SH		 4333 } else {
4334 rx_intr_handler(ring, 0);
8d8bb39b 4335 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4336 }
7d3d0439 4337
cc6e7c44
RA		 4338 return IRQ_HANDLED;
4339}
4340
7d12e780 4341static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4342{
ac731ab6
SH		 4343 int i;
4344 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4345 struct s2io_nic *sp = fifos->nic;
4346 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4347 struct config_param *config = &sp->config;
4348 u64 reason;
cc6e7c44 4349
ac731ab6
SH		 4350 if (unlikely(!is_s2io_card_up(sp)))
4351 return IRQ_NONE;
4352
4353 reason = readq(&bar0->general_int_status);
4354 if (unlikely(reason == S2IO_MINUS_ONE))
4355 /* Nothing much can be done. Get out */
92b84437 4356 return IRQ_HANDLED;
92b84437 4357
01e16faa
SH		 4358 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4359 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4360
01e16faa
SH		 4361 if (reason & GEN_INTR_TXPIC)
4362 s2io_txpic_intr_handle(sp);
ac731ab6 4363
01e16faa
SH		 4364 if (reason & GEN_INTR_TXTRAFFIC)
4365 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4366
01e16faa
SH		 4367 for (i = 0; i < config->tx_fifo_num; i++)
4368 tx_intr_handler(&fifos[i]);
ac731ab6 4369
01e16faa
SH		 4370 writeq(sp->general_int_mask, &bar0->general_int_mask);
4371 readl(&bar0->general_int_status);
4372 return IRQ_HANDLED;
4373 }
4374 /* The interrupt was not raised by us */
4375 return IRQ_NONE;
cc6e7c44 4376}
ac731ab6 4377
1ee6dd77 4378static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4379{
1ee6dd77 4380 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d 4381 u64 val64;
4382
4383 val64 = readq(&bar0->pic_int_status);
4384 if (val64 & PIC_INT_GPIO) {
4385 val64 = readq(&bar0->gpio_int_reg);
4386 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4387 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4388 /*
4389 * This is unstable state so clear both up/down
4390 * interrupt and adapter to re-evaluate the link state.
4391 */
d44570e4 4392 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d 4393 val64 |= GPIO_INT_REG_LINK_UP;
4394 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4395 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4396 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4397 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4398 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4399 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4400 val64 = readq(&bar0->adapter_status);
d44570e4 4401 /* Enable Adapter */
19a60522
SS		 4402 val64 = readq(&bar0->adapter_control);
4403 val64 |= ADAPTER_CNTL_EN;
4404 writeq(val64, &bar0->adapter_control);
4405 val64 |= ADAPTER_LED_ON;
4406 writeq(val64, &bar0->adapter_control);
4407 if (!sp->device_enabled_once)
4408 sp->device_enabled_once = 1;
c92ca04b 4409
19a60522
SS		 4410 s2io_link(sp, LINK_UP);
4411 /*
4412 * unmask link down interrupt and mask link-up
4413 * intr
4414 */
4415 val64 = readq(&bar0->gpio_int_mask);
4416 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4417 val64 |= GPIO_INT_MASK_LINK_UP;
4418 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4419
d44570e4 4420 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4421 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4422 s2io_link(sp, LINK_DOWN);
4423 /* Link is down so unmaks link up interrupt */
4424 val64 = readq(&bar0->gpio_int_mask);
4425 val64 &= ~GPIO_INT_MASK_LINK_UP;
4426 val64 |= GPIO_INT_MASK_LINK_DOWN;
4427 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4428
4429 /* turn off LED */
4430 val64 = readq(&bar0->adapter_control);
d44570e4 4431 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4432 writeq(val64, &bar0->adapter_control);
a371a07d 4433 }
4434 }
c92ca04b 4435 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4436}
4437
8116f3cf
SS		 4438/**
4439 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4440 * @value: alarm bits
4441 * @addr: address value
4442 * @cnt: counter variable
4443 * Description: Check for alarm and increment the counter
4444 * Return Value:
4445 * 1 - if alarm bit set
4446 * 0 - if alarm bit is not set
4447 */
d44570e4
JP		 4448static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4449 unsigned long long *cnt)
8116f3cf
SS		 4450{
4451 u64 val64;
4452 val64 = readq(addr);
d44570e4 4453 if (val64 & value) {
8116f3cf
SS		 4454 writeq(val64, addr);
4455 (*cnt)++;
4456 return 1;
4457 }
4458 return 0;
4459
4460}
4461
4462/**
4463 * s2io_handle_errors - Xframe error indication handler
4464 * @nic: device private variable
4465 * Description: Handle alarms such as loss of link, single or
4466 * double ECC errors, critical and serious errors.
4467 * Return Value:
4468 * NONE
4469 */
d44570e4 4470static void s2io_handle_errors(void *dev_id)
8116f3cf 4471{
d44570e4 4472 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4473 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4474 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4475 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4476 int i = 0;
4477
4478 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4479 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4480
92b84437 4481 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4482 return;
4483
4484 if (pci_channel_offline(sp->pdev))
4485 return;
4486
4487 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4488 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4489
4490 /* Handling the XPAK counters update */
d44570e4 4491 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4492 /* waiting for an hour */
4493 stats->xpak_timer_count++;
4494 } else {
4495 s2io_updt_xpak_counter(dev);
4496 /* reset the count to zero */
4497 stats->xpak_timer_count = 0;
4498 }
4499
4500 /* Handling link status change error Intr */
4501 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4502 val64 = readq(&bar0->mac_rmac_err_reg);
4503 writeq(val64, &bar0->mac_rmac_err_reg);
4504 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4505 schedule_work(&sp->set_link_task);
4506 }
4507
4508 /* In case of a serious error, the device will be Reset. */
4509 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4510 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4511 goto reset;
4512
4513 /* Check for data parity error */
4514 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4515 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4516 goto reset;
4517
4518 /* Check for ring full counter */
4519 if (sp->device_type == XFRAME_II_DEVICE) {
4520 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4521 for (i = 0; i < 4; i++) {
4522 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4523 temp64 >>= 64 - ((i+1)*16);
4524 sw_stat->ring_full_cnt[i] += temp64;
4525 }
4526
4527 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4528 for (i = 0; i < 4; i++) {
4529 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4530 temp64 >>= 64 - ((i+1)*16);
d44570e4 4531 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4532 }
4533 }
4534
4535 val64 = readq(&bar0->txdma_int_status);
4536 /*check for pfc_err*/
4537 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4538 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4539 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4540 PFC_PCIX_ERR,
4541 &bar0->pfc_err_reg,
4542 &sw_stat->pfc_err_cnt))
8116f3cf 4543 goto reset;
d44570e4
JP		 4544 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4545 &bar0->pfc_err_reg,
4546 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4547 }
4548
4549 /*check for tda_err*/
4550 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4551 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4552 TDA_SM0_ERR_ALARM |
4553 TDA_SM1_ERR_ALARM,
4554 &bar0->tda_err_reg,
4555 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4556 goto reset;
4557 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4558 &bar0->tda_err_reg,
4559 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4560 }
4561 /*check for pcc_err*/
4562 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4563 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4564 PCC_N_SERR | PCC_6_COF_OV_ERR |
4565 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4566 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4567 PCC_TXB_ECC_DB_ERR,
4568 &bar0->pcc_err_reg,
4569 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4570 goto reset;
4571 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4572 &bar0->pcc_err_reg,
4573 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4574 }
4575
4576 /*check for tti_err*/
4577 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4578 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4579 &bar0->tti_err_reg,
4580 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4581 goto reset;
4582 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4583 &bar0->tti_err_reg,
4584 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4585 }
4586
4587 /*check for lso_err*/
4588 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4589 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4590 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4591 &bar0->lso_err_reg,
4592 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4593 goto reset;
4594 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4595 &bar0->lso_err_reg,
4596 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4597 }
4598
4599 /*check for tpa_err*/
4600 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4601 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4602 &bar0->tpa_err_reg,
4603 &sw_stat->tpa_err_cnt))
8116f3cf 4604 goto reset;
d44570e4
JP		 4605 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4606 &bar0->tpa_err_reg,
4607 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4608 }
4609
4610 /*check for sm_err*/
4611 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4612 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4613 &bar0->sm_err_reg,
4614 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4615 goto reset;
4616 }
4617
4618 val64 = readq(&bar0->mac_int_status);
4619 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4620 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4621 &bar0->mac_tmac_err_reg,
4622 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4623 goto reset;
d44570e4
JP		 4624 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4625 TMAC_DESC_ECC_SG_ERR |
4626 TMAC_DESC_ECC_DB_ERR,
4627 &bar0->mac_tmac_err_reg,
4628 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4629 }
4630
4631 val64 = readq(&bar0->xgxs_int_status);
4632 if (val64 & XGXS_INT_STATUS_TXGXS) {
4633 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4634 &bar0->xgxs_txgxs_err_reg,
4635 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4636 goto reset;
4637 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4638 &bar0->xgxs_txgxs_err_reg,
4639 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4640 }
4641
4642 val64 = readq(&bar0->rxdma_int_status);
4643 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4644 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4645 RC_FTC_ECC_DB_ERR |
4646 RC_PRCn_SM_ERR_ALARM |
4647 RC_FTC_SM_ERR_ALARM,
4648 &bar0->rc_err_reg,
4649 &sw_stat->rc_err_cnt))
8116f3cf 4650 goto reset;
d44570e4
JP		 4651 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4652 RC_FTC_ECC_SG_ERR |
4653 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4654 &sw_stat->rc_err_cnt);
4655 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4656 PRC_PCI_AB_WR_Rn |
4657 PRC_PCI_AB_F_WR_Rn,
4658 &bar0->prc_pcix_err_reg,
4659 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4660 goto reset;
d44570e4
JP		 4661 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4662 PRC_PCI_DP_WR_Rn |
4663 PRC_PCI_DP_F_WR_Rn,
4664 &bar0->prc_pcix_err_reg,
4665 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4666 }
4667
4668 if (val64 & RXDMA_INT_RPA_INT_M) {
4669 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4670 &bar0->rpa_err_reg,
4671 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4672 goto reset;
4673 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4674 &bar0->rpa_err_reg,
4675 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4676 }
4677
4678 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4679 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4680 RDA_FRM_ECC_DB_N_AERR |
4681 RDA_SM1_ERR_ALARM |
4682 RDA_SM0_ERR_ALARM |
4683 RDA_RXD_ECC_DB_SERR,
4684 &bar0->rda_err_reg,
4685 &sw_stat->rda_err_cnt))
8116f3cf 4686 goto reset;
d44570e4
JP		 4687 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4688 RDA_FRM_ECC_SG_ERR |
4689 RDA_MISC_ERR |
4690 RDA_PCIX_ERR,
4691 &bar0->rda_err_reg,
4692 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4693 }
4694
4695 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4696 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4697 &bar0->rti_err_reg,
4698 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4699 goto reset;
4700 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4701 &bar0->rti_err_reg,
4702 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4703 }
4704
4705 val64 = readq(&bar0->mac_int_status);
4706 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4707 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4708 &bar0->mac_rmac_err_reg,
4709 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4710 goto reset;
d44570e4
JP		 4711 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4712 RMAC_SINGLE_ECC_ERR |
4713 RMAC_DOUBLE_ECC_ERR,
4714 &bar0->mac_rmac_err_reg,
4715 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4716 }
4717
4718 val64 = readq(&bar0->xgxs_int_status);
4719 if (val64 & XGXS_INT_STATUS_RXGXS) {
4720 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4721 &bar0->xgxs_rxgxs_err_reg,
4722 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4723 goto reset;
4724 }
4725
4726 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4727 if (val64 & MC_INT_STATUS_MC_INT) {
4728 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4729 &bar0->mc_err_reg,
4730 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4731 goto reset;
4732
4733 /* Handling Ecc errors */
4734 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4735 writeq(val64, &bar0->mc_err_reg);
4736 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4737 sw_stat->double_ecc_errs++;
4738 if (sp->device_type != XFRAME_II_DEVICE) {
4739 /*
4740 * Reset XframeI only if critical error
4741 */
4742 if (val64 &
d44570e4
JP		 4743 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4744 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4745 goto reset;
4746 }
8116f3cf
SS		 4747 } else
4748 sw_stat->single_ecc_errs++;
4749 }
4750 }
4751 return;
4752
4753reset:
3a3d5756 4754 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4755 schedule_work(&sp->rst_timer_task);
4756 sw_stat->soft_reset_cnt++;
8116f3cf
SS		 4757}
4758
1da177e4
LT		 4759/**
4760 * s2io_isr - ISR handler of the device .
4761 * @irq: the irq of the device.
4762 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4763 * Description: This function is the ISR handler of the device. It
4764 * identifies the reason for the interrupt and calls the relevant
4765 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4766 * recv buffers, if their numbers are below the panic value which is
4767 * presently set to 25% of the original number of rcv buffers allocated.
4768 * Return value:
20346722 4769 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4770 * IRQ_NONE: will be returned if interrupt is not from our device
4771 */
7d12e780 4772static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4773{
d44570e4 4774 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4775 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4776 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4777 int i;
19a60522 4778 u64 reason = 0;
1ee6dd77 4779 struct mac_info *mac_control;
1da177e4
LT		 4780 struct config_param *config;
4781
d796fdb7
LV		 4782 /* Pretend we handled any irq's from a disconnected card */
4783 if (pci_channel_offline(sp->pdev))
4784 return IRQ_NONE;
4785
596c5c97 4786 if (!is_s2io_card_up(sp))
92b84437 4787 return IRQ_NONE;
92b84437 4788
1da177e4 4789 config = &sp->config;
ffb5df6c 4790 mac_control = &sp->mac_control;
1da177e4 4791
20346722 4792 /*
1da177e4
LT		 4793 * Identify the cause for interrupt and call the appropriate
4794 * interrupt handler. Causes for the interrupt could be;
4795 * 1. Rx of packet.
4796 * 2. Tx complete.
4797 * 3. Link down.
1da177e4
LT		 4798 */
4799 reason = readq(&bar0->general_int_status);
4800
d44570e4
JP		 4801 if (unlikely(reason == S2IO_MINUS_ONE))
4802 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4803
d44570e4
JP		 4804 if (reason &
4805 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4806 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4807
4808 if (config->napi) {
4809 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4810 napi_schedule(&sp->napi);
f61e0a35
SH		 4811 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4812 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4813 readl(&bar0->rx_traffic_int);
db874e65 4814 }
596c5c97
SS		 4815 } else {
4816 /*
4817 * rx_traffic_int reg is an R1 register, writing all 1's
4818 * will ensure that the actual interrupt causing bit
4819 * get's cleared and hence a read can be avoided.
4820 */
4821 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4822 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4823
13d866a9
JP		 4824 for (i = 0; i < config->rx_ring_num; i++) {
4825 struct ring_info *ring = &mac_control->rings[i];
4826
4827 rx_intr_handler(ring, 0);
4828 }
db874e65 4829 }
596c5c97 4830
db874e65 4831 /*
596c5c97 4832 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4833 * will ensure that the actual interrupt causing bit get's
4834 * cleared and hence a read can be avoided.
4835 */
596c5c97
SS		 4836 if (reason & GEN_INTR_TXTRAFFIC)
4837 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4838
596c5c97
SS		 4839 for (i = 0; i < config->tx_fifo_num; i++)
4840 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4841
596c5c97
SS		 4842 if (reason & GEN_INTR_TXPIC)
4843 s2io_txpic_intr_handle(sp);
fe113638 4844
596c5c97
SS		 4845 /*
4846 * Reallocate the buffers from the interrupt handler itself.
4847 */
4848 if (!config->napi) {
13d866a9
JP		 4849 for (i = 0; i < config->rx_ring_num; i++) {
4850 struct ring_info *ring = &mac_control->rings[i];
4851
4852 s2io_chk_rx_buffers(sp, ring);
4853 }
596c5c97
SS		 4854 }
4855 writeq(sp->general_int_mask, &bar0->general_int_mask);
4856 readl(&bar0->general_int_status);
20346722 4857
596c5c97 4858 return IRQ_HANDLED;
db874e65 4859
d44570e4 4860 } else if (!reason) {
596c5c97
SS		 4861 /* The interrupt was not raised by us */
4862 return IRQ_NONE;
4863 }
db874e65 4864
1da177e4
LT		 4865 return IRQ_HANDLED;
4866}
4867
7ba013ac 4868/**
4869 * s2io_updt_stats -
4870 */
1ee6dd77 4871static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4872{
1ee6dd77 4873 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac 4874 u64 val64;
4875 int cnt = 0;
4876
92b84437 4877 if (is_s2io_card_up(sp)) {
7ba013ac 4878 /* Apprx 30us on a 133 MHz bus */
4879 val64 = SET_UPDT_CLICKS(10) |
4880 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4881 writeq(val64, &bar0->stat_cfg);
4882 do {
4883 udelay(100);
4884 val64 = readq(&bar0->stat_cfg);
b7b5a128 4885 if (!(val64 & s2BIT(0)))
7ba013ac 4886 break;
4887 cnt++;
4888 if (cnt == 5)
4889 break; /* Updt failed */
d44570e4 4890 } while (1);
8a4bdbaa 4891 }
7ba013ac 4892}
4893
1da177e4 4894/**
20346722 4895 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4896 * @dev : pointer to the device structure.
4897 * Description:
20346722 4898 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4899 * structure and returns a pointer to the same.
4900 * Return value:
4901 * pointer to the updated net_device_stats structure.
4902 */
ac1f60db 4903static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4904{
4cf1653a 4905 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 4906 struct mac_info *mac_control = &sp->mac_control;
4907 struct stat_block *stats = mac_control->stats_info;
4a490432 4908 u64 delta;
1da177e4 4909
7ba013ac 4910 /* Configure Stats for immediate updt */
4911 s2io_updt_stats(sp);
4912
4a490432
JM		 4913 /* A device reset will cause the on-adapter statistics to be zero'ed.
4914 * This can be done while running by changing the MTU. To prevent the
4915 * system from having the stats zero'ed, the driver keeps a copy of the
4916 * last update to the system (which is also zero'ed on reset). This
4917 * enables the driver to accurately know the delta between the last
4918 * update and the current update.
4919 */
4920 delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4921 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4922 sp->stats.rx_packets += delta;
4923 dev->stats.rx_packets += delta;
4924
4925 delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4926 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4927 sp->stats.tx_packets += delta;
4928 dev->stats.tx_packets += delta;
4929
4930 delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4931 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4932 sp->stats.rx_bytes += delta;
4933 dev->stats.rx_bytes += delta;
4934
4935 delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4936 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4937 sp->stats.tx_bytes += delta;
4938 dev->stats.tx_bytes += delta;
4939
4940 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4941 sp->stats.rx_errors += delta;
4942 dev->stats.rx_errors += delta;
4943
4944 delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4945 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4946 sp->stats.tx_errors += delta;
4947 dev->stats.tx_errors += delta;
4948
4949 delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4950 sp->stats.rx_dropped += delta;
4951 dev->stats.rx_dropped += delta;
4952
4953 delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4954 sp->stats.tx_dropped += delta;
4955 dev->stats.tx_dropped += delta;
4956
4957 /* The adapter MAC interprets pause frames as multicast packets, but
4958 * does not pass them up. This erroneously increases the multicast
4959 * packet count and needs to be deducted when the multicast frame count
4960 * is queried.
4961 */
4962 delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4963 le32_to_cpu(stats->rmac_vld_mcst_frms);
4964 delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4965 delta -= sp->stats.multicast;
4966 sp->stats.multicast += delta;
4967 dev->stats.multicast += delta;
1da177e4 4968
4a490432
JM		 4969 delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4970 le32_to_cpu(stats->rmac_usized_frms)) +
4971 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4972 sp->stats.rx_length_errors += delta;
4973 dev->stats.rx_length_errors += delta;
13d866a9 4974
4a490432
JM		 4975 delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4976 sp->stats.rx_crc_errors += delta;
4977 dev->stats.rx_crc_errors += delta;
0425b46a 4978
d44570e4 4979 return &dev->stats;
1da177e4
LT		 4980}
4981
4982/**
4983 * s2io_set_multicast - entry point for multicast address enable/disable.
4984 * @dev : pointer to the device structure
4985 * Description:
20346722 4986 * This function is a driver entry point which gets called by the kernel
4987 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4988 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4989 * determine, if multicast address must be enabled or if promiscuous mode
4990 * is to be disabled etc.
4991 * Return value:
4992 * void.
4993 */
4994
4995static void s2io_set_multicast(struct net_device *dev)
4996{
4997 int i, j, prev_cnt;
22bedad3 4998 struct netdev_hw_addr *ha;
4cf1653a 4999 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5000 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5001 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 5002 0xfeffffffffffULL;
faa4f796 5003 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 5004 void __iomem *add;
faa4f796 5005 struct config_param *config = &sp->config;
1da177e4
LT		 5006
5007 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
5008 /* Enable all Multicast addresses */
5009 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
5010 &bar0->rmac_addr_data0_mem);
5011 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
5012 &bar0->rmac_addr_data1_mem);
5013 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5014 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5015 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 5016 writeq(val64, &bar0->rmac_addr_cmd_mem);
5017 /* Wait till command completes */
c92ca04b 5018 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5019 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5020 S2IO_BIT_RESET);
1da177e4
LT		 5021
5022 sp->m_cast_flg = 1;
faa4f796 5023 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 5024 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
5025 /* Disable all Multicast addresses */
5026 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5027 &bar0->rmac_addr_data0_mem);
5e25b9dd 5028 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
5029 &bar0->rmac_addr_data1_mem);
1da177e4 5030 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5031 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5032 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5033 writeq(val64, &bar0->rmac_addr_cmd_mem);
5034 /* Wait till command completes */
c92ca04b 5035 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5036 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5037 S2IO_BIT_RESET);
1da177e4
LT		 5038
5039 sp->m_cast_flg = 0;
5040 sp->all_multi_pos = 0;
5041 }
5042
5043 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5044 /* Put the NIC into promiscuous mode */
5045 add = &bar0->mac_cfg;
5046 val64 = readq(&bar0->mac_cfg);
5047 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5048
5049 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5050 writel((u32)val64, add);
1da177e4
LT		 5051 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5052 writel((u32) (val64 >> 32), (add + 4));
5053
926930b2
SS		 5054 if (vlan_tag_strip != 1) {
5055 val64 = readq(&bar0->rx_pa_cfg);
5056 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5057 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5058 sp->vlan_strip_flag = 0;
926930b2
SS		 5059 }
5060
1da177e4
LT		 5061 val64 = readq(&bar0->mac_cfg);
5062 sp->promisc_flg = 1;
776bd20f 5063 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5064 dev->name);
5065 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5066 /* Remove the NIC from promiscuous mode */
5067 add = &bar0->mac_cfg;
5068 val64 = readq(&bar0->mac_cfg);
5069 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5070
5071 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5072 writel((u32)val64, add);
1da177e4
LT		 5073 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5074 writel((u32) (val64 >> 32), (add + 4));
5075
926930b2
SS		 5076 if (vlan_tag_strip != 0) {
5077 val64 = readq(&bar0->rx_pa_cfg);
5078 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5079 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5080 sp->vlan_strip_flag = 1;
926930b2
SS		 5081 }
5082
1da177e4
LT		 5083 val64 = readq(&bar0->mac_cfg);
5084 sp->promisc_flg = 0;
9e39f7c5 5085 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
1da177e4
LT		 5086 }
5087
5088 /* Update individual M_CAST address list */
4cd24eaf
JP		 5089 if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5090 if (netdev_mc_count(dev) >
faa4f796 5091 (config->max_mc_addr - config->max_mac_addr)) {
9e39f7c5
JP		 5092 DBG_PRINT(ERR_DBG,
5093 "%s: No more Rx filters can be added - "
5094 "please enable ALL_MULTI instead\n",
1da177e4 5095 dev->name);
1da177e4
LT		 5096 return;
5097 }
5098
5099 prev_cnt = sp->mc_addr_count;
4cd24eaf 5100 sp->mc_addr_count = netdev_mc_count(dev);
1da177e4
LT		 5101
5102 /* Clear out the previous list of Mc in the H/W. */
5103 for (i = 0; i < prev_cnt; i++) {
5104 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5105 &bar0->rmac_addr_data0_mem);
5106 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5107 &bar0->rmac_addr_data1_mem);
1da177e4 5108 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5109 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5110 RMAC_ADDR_CMD_MEM_OFFSET
5111 (config->mc_start_offset + i);
1da177e4
LT		 5112 writeq(val64, &bar0->rmac_addr_cmd_mem);
5113
5114 /* Wait for command completes */
c92ca04b 5115 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5116 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5117 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5118 DBG_PRINT(ERR_DBG,
5119 "%s: Adding Multicasts failed\n",
5120 dev->name);
1da177e4
LT		 5121 return;
5122 }
5123 }
5124
5125 /* Create the new Rx filter list and update the same in H/W. */
5508590c 5126 i = 0;
22bedad3
JP		 5127 netdev_for_each_mc_addr(ha, dev) {
5128 memcpy(sp->usr_addrs[i].addr, ha->addr,
1da177e4 5129 ETH_ALEN);
a7a80d5a 5130 mac_addr = 0;
1da177e4 5131 for (j = 0; j < ETH_ALEN; j++) {
22bedad3 5132 mac_addr |= ha->addr[j];
1da177e4
LT		 5133 mac_addr <<= 8;
5134 }
5135 mac_addr >>= 8;
5136 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5137 &bar0->rmac_addr_data0_mem);
5138 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5139 &bar0->rmac_addr_data1_mem);
1da177e4 5140 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5141 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5142 RMAC_ADDR_CMD_MEM_OFFSET
5143 (i + config->mc_start_offset);
1da177e4
LT		 5144 writeq(val64, &bar0->rmac_addr_cmd_mem);
5145
5146 /* Wait for command completes */
c92ca04b 5147 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5148 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5149 S2IO_BIT_RESET)) {
9e39f7c5
JP		 5150 DBG_PRINT(ERR_DBG,
5151 "%s: Adding Multicasts failed\n",
5152 dev->name);
1da177e4
LT		 5153 return;
5154 }
5508590c 5155 i++;
1da177e4
LT		 5156 }
5157 }
5158}
5159
faa4f796
SH		 5160/* read from CAM unicast & multicast addresses and store it in
5161 * def_mac_addr structure
5162 */
dac499f9 5163static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5164{
5165 int offset;
5166 u64 mac_addr = 0x0;
5167 struct config_param *config = &sp->config;
5168
5169 /* store unicast & multicast mac addresses */
5170 for (offset = 0; offset < config->max_mc_addr; offset++) {
5171 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5172 /* if read fails disable the entry */
5173 if (mac_addr == FAILURE)
5174 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5175 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5176 }
5177}
5178
5179/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5180static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5181{
5182 int offset;
5183 struct config_param *config = &sp->config;
5184 /* restore unicast mac address */
5185 for (offset = 0; offset < config->max_mac_addr; offset++)
5186 do_s2io_prog_unicast(sp->dev,
d44570e4 5187 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5188
5189 /* restore multicast mac address */
5190 for (offset = config->mc_start_offset;
d44570e4 5191 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5192 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5193}
5194
5195/* add a multicast MAC address to CAM */
5196static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5197{
5198 int i;
5199 u64 mac_addr = 0;
5200 struct config_param *config = &sp->config;
5201
5202 for (i = 0; i < ETH_ALEN; i++) {
5203 mac_addr <<= 8;
5204 mac_addr |= addr[i];
5205 }
5206 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5207 return SUCCESS;
5208
5209 /* check if the multicast mac already preset in CAM */
5210 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5211 u64 tmp64;
5212 tmp64 = do_s2io_read_unicast_mc(sp, i);
5213 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5214 break;
5215
5216 if (tmp64 == mac_addr)
5217 return SUCCESS;
5218 }
5219 if (i == config->max_mc_addr) {
5220 DBG_PRINT(ERR_DBG,
d44570e4 5221 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5222 return FAILURE;
5223 }
5224 /* Update the internal structure with this new mac address */
5225 do_s2io_copy_mac_addr(sp, i, mac_addr);
5226
d44570e4 5227 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5228}
5229
5230/* add MAC address to CAM */
5231static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5232{
5233 u64 val64;
5234 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5235
5236 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5237 &bar0->rmac_addr_data0_mem);
2fd37688 5238
d44570e4 5239 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5240 RMAC_ADDR_CMD_MEM_OFFSET(off);
5241 writeq(val64, &bar0->rmac_addr_cmd_mem);
5242
5243 /* Wait till command completes */
5244 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5245 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5246 S2IO_BIT_RESET)) {
faa4f796 5247 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5248 return FAILURE;
5249 }
5250 return SUCCESS;
5251}
faa4f796
SH		 5252/* deletes a specified unicast/multicast mac entry from CAM */
5253static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5254{
5255 int offset;
5256 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5257 struct config_param *config = &sp->config;
5258
5259 for (offset = 1;
d44570e4 5260 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5261 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5262 if (tmp64 == addr) {
5263 /* disable the entry by writing 0xffffffffffffULL */
5264 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5265 return FAILURE;
5266 /* store the new mac list from CAM */
5267 do_s2io_store_unicast_mc(sp);
5268 return SUCCESS;
5269 }
5270 }
5271 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5272 (unsigned long long)addr);
faa4f796
SH		 5273 return FAILURE;
5274}
5275
5276/* read mac entries from CAM */
5277static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5278{
5279 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5280 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5281
5282 /* read mac addr */
d44570e4 5283 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5284 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5285 writeq(val64, &bar0->rmac_addr_cmd_mem);
5286
5287 /* Wait till command completes */
5288 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5289 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5290 S2IO_BIT_RESET)) {
faa4f796
SH		 5291 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5292 return FAILURE;
5293 }
5294 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5295
5296 return tmp64 >> 16;
faa4f796 5297}
2fd37688
SS		 5298
5299/**
5300 * s2io_set_mac_addr driver entry point
5301 */
faa4f796 5302
2fd37688
SS		 5303static int s2io_set_mac_addr(struct net_device *dev, void *p)
5304{
5305 struct sockaddr *addr = p;
5306
5307 if (!is_valid_ether_addr(addr->sa_data))
5308 return -EINVAL;
5309
5310 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5311
5312 /* store the MAC address in CAM */
d44570e4 5313 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5314}
1da177e4 5315/**
2fd37688 5316 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5317 * @dev : pointer to the device structure.
5318 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5319 * Description : This procedure will program the Xframe to receive
1da177e4 5320 * frames with new Mac Address
20346722 5321 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5322 * as defined in errno.h file on failure.
5323 */
faa4f796 5324
2fd37688 5325static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5326{
4cf1653a 5327 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5328 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5329 int i;
faa4f796
SH		 5330 u64 tmp64;
5331 struct config_param *config = &sp->config;
1da177e4 5332
20346722 5333 /*
d44570e4
JP		 5334 * Set the new MAC address as the new unicast filter and reflect this
5335 * change on the device address registered with the OS. It will be
5336 * at offset 0.
5337 */
1da177e4
LT		 5338 for (i = 0; i < ETH_ALEN; i++) {
5339 mac_addr <<= 8;
5340 mac_addr |= addr[i];
2fd37688
SS		 5341 perm_addr <<= 8;
5342 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5343 }
5344
2fd37688
SS		 5345 /* check if the dev_addr is different than perm_addr */
5346 if (mac_addr == perm_addr)
d8d70caf
SS		 5347 return SUCCESS;
5348
faa4f796
SH		 5349 /* check if the mac already preset in CAM */
5350 for (i = 1; i < config->max_mac_addr; i++) {
5351 tmp64 = do_s2io_read_unicast_mc(sp, i);
5352 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5353 break;
5354
5355 if (tmp64 == mac_addr) {
5356 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5357 "MAC addr:0x%llx already present in CAM\n",
5358 (unsigned long long)mac_addr);
faa4f796
SH		 5359 return SUCCESS;
5360 }
5361 }
5362 if (i == config->max_mac_addr) {
5363 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5364 return FAILURE;
5365 }
d8d70caf 5366 /* Update the internal structure with this new mac address */
faa4f796 5367 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5368
5369 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5370}
5371
5372/**
20346722 5373 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5374 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5375 * @info: pointer to the structure with parameters given by ethtool to set
5376 * link information.
5377 * Description:
20346722 5378 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5379 * the NIC.
5380 * Return value:
5381 * 0 on success.
d44570e4 5382 */
1da177e4
LT		 5383
5384static int s2io_ethtool_sset(struct net_device *dev,
5385 struct ethtool_cmd *info)
5386{
4cf1653a 5387 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5388 if ((info->autoneg == AUTONEG_ENABLE) ||
d44570e4
JP		 5389 (info->speed != SPEED_10000) ||
5390 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5391 return -EINVAL;
5392 else {
5393 s2io_close(sp->dev);
5394 s2io_open(sp->dev);
5395 }
5396
5397 return 0;
5398}
5399
5400/**
20346722 5401 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5402 * @sp : private member of the device structure, pointer to the
5403 * s2io_nic structure.
5404 * @info : pointer to the structure with parameters given by ethtool
5405 * to return link information.
5406 * Description:
5407 * Returns link specific information like speed, duplex etc.. to ethtool.
5408 * Return value :
5409 * return 0 on success.
5410 */
5411
5412static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5413{
4cf1653a 5414 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5415 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5416 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5417 info->port = PORT_FIBRE;
1a7eb72b
SS		 5418
5419 /* info->transceiver */
5420 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5421
5422 if (netif_carrier_ok(sp->dev)) {
5423 info->speed = 10000;
5424 info->duplex = DUPLEX_FULL;
5425 } else {
5426 info->speed = -1;
5427 info->duplex = -1;
5428 }
5429
5430 info->autoneg = AUTONEG_DISABLE;
5431 return 0;
5432}
5433
5434/**
20346722 5435 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5436 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5437 * s2io_nic structure.
5438 * @info : pointer to the structure with parameters given by ethtool to
5439 * return driver information.
5440 * Description:
5441 * Returns driver specefic information like name, version etc.. to ethtool.
5442 * Return value:
5443 * void
5444 */
5445
5446static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5447 struct ethtool_drvinfo *info)
5448{
4cf1653a 5449 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5450
dbc2309d
JL		 5451 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5452 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5453 strncpy(info->fw_version, "", sizeof(info->fw_version));
5454 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5455 info->regdump_len = XENA_REG_SPACE;
5456 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5457}
5458
5459/**
5460 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5461 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5462 * s2io_nic structure.
20346722 5463 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5464 * dumping the registers.
5465 * @reg_space: The input argumnet into which all the registers are dumped.
5466 * Description:
5467 * Dumps the entire register space of xFrame NIC into the user given
5468 * buffer area.
5469 * Return value :
5470 * void .
d44570e4 5471 */
1da177e4
LT		 5472
5473static void s2io_ethtool_gregs(struct net_device *dev,
5474 struct ethtool_regs *regs, void *space)
5475{
5476 int i;
5477 u64 reg;
d44570e4 5478 u8 *reg_space = (u8 *)space;
4cf1653a 5479 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5480
5481 regs->len = XENA_REG_SPACE;
5482 regs->version = sp->pdev->subsystem_device;
5483
5484 for (i = 0; i < regs->len; i += 8) {
5485 reg = readq(sp->bar0 + i);
5486 memcpy((reg_space + i), &reg, 8);
5487 }
5488}
5489
5490/**
5491 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5492 * @data : address of the private member of the device structure, which
1da177e4 5493 * is a pointer to the s2io_nic structure, provided as an u32.
20346722 5494 * Description: This is actually the timer function that alternates the
5495 * adapter LED bit of the adapter control bit to set/reset every time on
5496 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4 5497 * once every second.
d44570e4 5498 */
1da177e4
LT		 5499static void s2io_phy_id(unsigned long data)
5500{
d44570e4 5501 struct s2io_nic *sp = (struct s2io_nic *)data;
1ee6dd77 5502 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5503 u64 val64 = 0;
5504 u16 subid;
5505
5506 subid = sp->pdev->subsystem_device;
541ae68f 5507 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5508 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5509 val64 = readq(&bar0->gpio_control);
5510 val64 ^= GPIO_CTRL_GPIO_0;
5511 writeq(val64, &bar0->gpio_control);
5512 } else {
5513 val64 = readq(&bar0->adapter_control);
5514 val64 ^= ADAPTER_LED_ON;
5515 writeq(val64, &bar0->adapter_control);
5516 }
5517
5518 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5519}
5520
5521/**
5522 * s2io_ethtool_idnic - To physically identify the nic on the system.
5523 * @sp : private member of the device structure, which is a pointer to the
5524 * s2io_nic structure.
20346722 5525 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5526 * ethtool.
5527 * Description: Used to physically identify the NIC on the system.
20346722 5528 * The Link LED will blink for a time specified by the user for
1da177e4 5529 * identification.
20346722 5530 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5531 * identification is possible only if it's link is up.
5532 * Return value:
5533 * int , returns 0 on success
5534 */
5535
5536static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5537{
5538 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5539 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5540 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5541 u16 subid;
5542
5543 subid = sp->pdev->subsystem_device;
5544 last_gpio_ctrl_val = readq(&bar0->gpio_control);
d44570e4 5545 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5546 val64 = readq(&bar0->adapter_control);
5547 if (!(val64 & ADAPTER_CNTL_EN)) {
6cef2b8e 5548 pr_err("Adapter Link down, cannot blink LED\n");
1da177e4
LT		 5549 return -EFAULT;
5550 }
5551 }
5552 if (sp->id_timer.function == NULL) {
5553 init_timer(&sp->id_timer);
5554 sp->id_timer.function = s2io_phy_id;
d44570e4 5555 sp->id_timer.data = (unsigned long)sp;
1da177e4
LT		 5556 }
5557 mod_timer(&sp->id_timer, jiffies);
5558 if (data)
20346722 5559 msleep_interruptible(data * HZ);
1da177e4 5560 else
20346722 5561 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5562 del_timer_sync(&sp->id_timer);
5563
541ae68f 5564 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5565 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5566 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5567 }
5568
5569 return 0;
5570}
5571
0cec35eb 5572static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5573 struct ethtool_ringparam *ering)
0cec35eb 5574{
4cf1653a 5575 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5576 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb
SH		 5577
5578 if (sp->rxd_mode == RXD_MODE_1)
5579 ering->rx_max_pending = MAX_RX_DESC_1;
5580 else if (sp->rxd_mode == RXD_MODE_3B)
5581 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5582
5583 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5584 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5585 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5586
9e39f7c5 5587 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
0cec35eb
SH		 5588 ering->tx_pending = tx_desc_count;
5589 rx_desc_count = 0;
8a4bdbaa 5590 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5591 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5592
0cec35eb
SH		 5593 ering->rx_pending = rx_desc_count;
5594
5595 ering->rx_mini_max_pending = 0;
5596 ering->rx_mini_pending = 0;
d44570e4 5597 if (sp->rxd_mode == RXD_MODE_1)
0cec35eb
SH		 5598 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5599 else if (sp->rxd_mode == RXD_MODE_3B)
5600 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5601 ering->rx_jumbo_pending = rx_desc_count;
5602}
5603
1da177e4
LT		 5604/**
5605 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 5606 * @sp : private member of the device structure, which is a pointer to the
5607 * s2io_nic structure.
1da177e4
LT		 5608 * @ep : pointer to the structure with pause parameters given by ethtool.
5609 * Description:
5610 * Returns the Pause frame generation and reception capability of the NIC.
5611 * Return value:
5612 * void
5613 */
5614static void s2io_ethtool_getpause_data(struct net_device *dev,
5615 struct ethtool_pauseparam *ep)
5616{
5617 u64 val64;
4cf1653a 5618 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5619 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5620
5621 val64 = readq(&bar0->rmac_pause_cfg);
5622 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5623 ep->tx_pause = true;
1da177e4 5624 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5625 ep->rx_pause = true;
5626 ep->autoneg = false;
1da177e4
LT		 5627}
5628
5629/**
5630 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5631 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5632 * s2io_nic structure.
5633 * @ep : pointer to the structure with pause parameters given by ethtool.
5634 * Description:
5635 * It can be used to set or reset Pause frame generation or reception
5636 * support of the NIC.
5637 * Return value:
5638 * int, returns 0 on Success
5639 */
5640
5641static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5642 struct ethtool_pauseparam *ep)
1da177e4
LT		 5643{
5644 u64 val64;
4cf1653a 5645 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5646 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5647
5648 val64 = readq(&bar0->rmac_pause_cfg);
5649 if (ep->tx_pause)
5650 val64 |= RMAC_PAUSE_GEN_ENABLE;
5651 else
5652 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5653 if (ep->rx_pause)
5654 val64 |= RMAC_PAUSE_RX_ENABLE;
5655 else
5656 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5657 writeq(val64, &bar0->rmac_pause_cfg);
5658 return 0;
5659}
5660
5661/**
5662 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5663 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5664 * s2io_nic structure.
5665 * @off : offset at which the data must be written
5666 * @data : Its an output parameter where the data read at the given
20346722 5667 * offset is stored.
1da177e4 5668 * Description:
20346722 5669 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5670 * read data.
5671 * NOTE: Will allow to read only part of the EEPROM visible through the
5672 * I2C bus.
5673 * Return value:
5674 * -1 on failure and 0 on success.
5675 */
5676
5677#define S2IO_DEV_ID 5
d44570e4 5678static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5679{
5680 int ret = -1;
5681 u32 exit_cnt = 0;
5682 u64 val64;
1ee6dd77 5683 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5684
ad4ebed0 5685 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5686 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5687 I2C_CONTROL_ADDR(off) |
5688 I2C_CONTROL_BYTE_CNT(0x3) |
5689 I2C_CONTROL_READ |
5690 I2C_CONTROL_CNTL_START;
ad4ebed0 5691 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5692
ad4ebed0 5693 while (exit_cnt < 5) {
5694 val64 = readq(&bar0->i2c_control);
5695 if (I2C_CONTROL_CNTL_END(val64)) {
5696 *data = I2C_CONTROL_GET_DATA(val64);
5697 ret = 0;
5698 break;
5699 }
5700 msleep(50);
5701 exit_cnt++;
1da177e4 5702 }
1da177e4
LT		 5703 }
5704
ad4ebed0 5705 if (sp->device_type == XFRAME_II_DEVICE) {
5706 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5707 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5708 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5709 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5710 val64 |= SPI_CONTROL_REQ;
5711 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5712 while (exit_cnt < 5) {
5713 val64 = readq(&bar0->spi_control);
5714 if (val64 & SPI_CONTROL_NACK) {
5715 ret = 1;
5716 break;
5717 } else if (val64 & SPI_CONTROL_DONE) {
5718 *data = readq(&bar0->spi_data);
5719 *data &= 0xffffff;
5720 ret = 0;
5721 break;
5722 }
5723 msleep(50);
5724 exit_cnt++;
5725 }
5726 }
1da177e4
LT		 5727 return ret;
5728}
5729
5730/**
5731 * write_eeprom - actually writes the relevant part of the data value.
5732 * @sp : private member of the device structure, which is a pointer to the
5733 * s2io_nic structure.
5734 * @off : offset at which the data must be written
5735 * @data : The data that is to be written
20346722 5736 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5737 * the Eeprom. (max of 3)
5738 * Description:
5739 * Actually writes the relevant part of the data value into the Eeprom
5740 * through the I2C bus.
5741 * Return value:
5742 * 0 on success, -1 on failure.
5743 */
5744
d44570e4 5745static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5746{
5747 int exit_cnt = 0, ret = -1;
5748 u64 val64;
1ee6dd77 5749 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5750
ad4ebed0 5751 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5752 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5753 I2C_CONTROL_ADDR(off) |
5754 I2C_CONTROL_BYTE_CNT(cnt) |
5755 I2C_CONTROL_SET_DATA((u32)data) |
5756 I2C_CONTROL_CNTL_START;
ad4ebed0 5757 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5758
5759 while (exit_cnt < 5) {
5760 val64 = readq(&bar0->i2c_control);
5761 if (I2C_CONTROL_CNTL_END(val64)) {
5762 if (!(val64 & I2C_CONTROL_NACK))
5763 ret = 0;
5764 break;
5765 }
5766 msleep(50);
5767 exit_cnt++;
5768 }
5769 }
1da177e4 5770
ad4ebed0 5771 if (sp->device_type == XFRAME_II_DEVICE) {
5772 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5773 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5774
5775 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5776 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5777 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5778 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5779 val64 |= SPI_CONTROL_REQ;
5780 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5781 while (exit_cnt < 5) {
5782 val64 = readq(&bar0->spi_control);
5783 if (val64 & SPI_CONTROL_NACK) {
5784 ret = 1;
5785 break;
5786 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5787 ret = 0;
ad4ebed0 5788 break;
5789 }
5790 msleep(50);
5791 exit_cnt++;
1da177e4 5792 }
1da177e4 5793 }
1da177e4
LT		 5794 return ret;
5795}
1ee6dd77 5796static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5797{
b41477f3
AR		 5798 u8 *vpd_data;
5799 u8 data;
d44570e4 5800 int i = 0, cnt, fail = 0;
9dc737a7 5801 int vpd_addr = 0x80;
ffb5df6c 5802 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
9dc737a7
AR		 5803
5804 if (nic->device_type == XFRAME_II_DEVICE) {
5805 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5806 vpd_addr = 0x80;
d44570e4 5807 } else {
9dc737a7
AR		 5808 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5809 vpd_addr = 0x50;
5810 }
19a60522 5811 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5812
b41477f3 5813 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945 5814 if (!vpd_data) {
ffb5df6c 5815 swstats->mem_alloc_fail_cnt++;
b41477f3 5816 return;
c53d4945 5817 }
ffb5df6c 5818 swstats->mem_allocated += 256;
b41477f3 5819
d44570e4 5820 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5821 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5822 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5823 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5824 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5825 msleep(2);
5826 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5827 if (data == 0x80)
5828 break;
5829 }
5830 if (cnt >= 5) {
5831 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5832 fail = 1;
5833 break;
5834 }
5835 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5836 (u32 *)&vpd_data[i]);
5837 }
19a60522 5838
d44570e4 5839 if (!fail) {
19a60522
SS		 5840 /* read serial number of adapter */
5841 for (cnt = 0; cnt < 256; cnt++) {
d44570e4
JP		 5842 if ((vpd_data[cnt] == 'S') &&
5843 (vpd_data[cnt+1] == 'N') &&
5844 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
19a60522
SS		 5845 memset(nic->serial_num, 0, VPD_STRING_LEN);
5846 memcpy(nic->serial_num, &vpd_data[cnt + 3],
d44570e4 5847 vpd_data[cnt+2]);
19a60522
SS		 5848 break;
5849 }
5850 }
5851 }
5852
876e956f 5853 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN))
9dc737a7 5854 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
b41477f3 5855 kfree(vpd_data);
ffb5df6c 5856 swstats->mem_freed += 256;
9dc737a7
AR		 5857}
5858
1da177e4
LT		 5859/**
5860 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5861 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5862 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5863 * containing all relevant information.
5864 * @data_buf : user defined value to be written into Eeprom.
5865 * Description: Reads the values stored in the Eeprom at given offset
5866 * for a given length. Stores these values int the input argument data
5867 * buffer 'data_buf' and returns these to the caller (ethtool.)
5868 * Return value:
5869 * int 0 on success
5870 */
5871
5872static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5873 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5874{
ad4ebed0 5875 u32 i, valid;
5876 u64 data;
4cf1653a 5877 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5878
5879 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5880
5881 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5882 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5883
5884 for (i = 0; i < eeprom->len; i += 4) {
5885 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5886 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5887 return -EFAULT;
5888 }
5889 valid = INV(data);
5890 memcpy((data_buf + i), &valid, 4);
5891 }
5892 return 0;
5893}
5894
5895/**
5896 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5897 * @sp : private member of the device structure, which is a pointer to the
5898 * s2io_nic structure.
20346722 5899 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5900 * containing all relevant information.
5901 * @data_buf ; user defined value to be written into Eeprom.
5902 * Description:
5903 * Tries to write the user provided value in the Eeprom, at the offset
5904 * given by the user.
5905 * Return value:
5906 * 0 on success, -EFAULT on failure.
5907 */
5908
5909static int s2io_ethtool_seeprom(struct net_device *dev,
5910 struct ethtool_eeprom *eeprom,
d44570e4 5911 u8 *data_buf)
1da177e4
LT		 5912{
5913 int len = eeprom->len, cnt = 0;
ad4ebed0 5914 u64 valid = 0, data;
4cf1653a 5915 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5916
5917 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5918 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5919 "ETHTOOL_WRITE_EEPROM Err: "
5920 "Magic value is wrong, it is 0x%x should be 0x%x\n",
5921 (sp->pdev->vendor | (sp->pdev->device << 16)),
5922 eeprom->magic);
1da177e4
LT		 5923 return -EFAULT;
5924 }
5925
5926 while (len) {
d44570e4
JP		 5927 data = (u32)data_buf[cnt] & 0x000000FF;
5928 if (data)
5929 valid = (u32)(data << 24);
5930 else
1da177e4
LT		 5931 valid = data;
5932
5933 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5934 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 5935 "ETHTOOL_WRITE_EEPROM Err: "
5936 "Cannot write into the specified offset\n");
1da177e4
LT		 5937 return -EFAULT;
5938 }
5939 cnt++;
5940 len--;
5941 }
5942
5943 return 0;
5944}
5945
5946/**
20346722 5947 * s2io_register_test - reads and writes into all clock domains.
5948 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5949 * s2io_nic structure.
5950 * @data : variable that returns the result of each of the test conducted b
5951 * by the driver.
5952 * Description:
5953 * Read and write into all clock domains. The NIC has 3 clock domains,
5954 * see that registers in all the three regions are accessible.
5955 * Return value:
5956 * 0 on success.
5957 */
5958
d44570e4 5959static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5960{
1ee6dd77 5961 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5962 u64 val64 = 0, exp_val;
1da177e4
LT		 5963 int fail = 0;
5964
20346722 5965 val64 = readq(&bar0->pif_rd_swapper_fb);
5966 if (val64 != 0x123456789abcdefULL) {
1da177e4 5967 fail = 1;
9e39f7c5 5968 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
1da177e4
LT		 5969 }
5970
5971 val64 = readq(&bar0->rmac_pause_cfg);
5972 if (val64 != 0xc000ffff00000000ULL) {
5973 fail = 1;
9e39f7c5 5974 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
1da177e4
LT		 5975 }
5976
5977 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5978 if (sp->device_type == XFRAME_II_DEVICE)
5979 exp_val = 0x0404040404040404ULL;
5980 else
5981 exp_val = 0x0808080808080808ULL;
5982 if (val64 != exp_val) {
1da177e4 5983 fail = 1;
9e39f7c5 5984 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
1da177e4
LT		 5985 }
5986
5987 val64 = readq(&bar0->xgxs_efifo_cfg);
5988 if (val64 != 0x000000001923141EULL) {
5989 fail = 1;
9e39f7c5 5990 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
1da177e4
LT		 5991 }
5992
5993 val64 = 0x5A5A5A5A5A5A5A5AULL;
5994 writeq(val64, &bar0->xmsi_data);
5995 val64 = readq(&bar0->xmsi_data);
5996 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5997 fail = 1;
9e39f7c5 5998 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
1da177e4
LT		 5999 }
6000
6001 val64 = 0xA5A5A5A5A5A5A5A5ULL;
6002 writeq(val64, &bar0->xmsi_data);
6003 val64 = readq(&bar0->xmsi_data);
6004 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
6005 fail = 1;
9e39f7c5 6006 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
1da177e4
LT		 6007 }
6008
6009 *data = fail;
ad4ebed0 6010 return fail;
1da177e4
LT		 6011}
6012
6013/**
20346722 6014 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 6015 * @sp : private member of the device structure, which is a pointer to the
6016 * s2io_nic structure.
6017 * @data:variable that returns the result of each of the test conducted by
6018 * the driver.
6019 * Description:
20346722 6020 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 6021 * register.
6022 * Return value:
6023 * 0 on success.
6024 */
6025
d44570e4 6026static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6027{
6028 int fail = 0;
ad4ebed0 6029 u64 ret_data, org_4F0, org_7F0;
6030 u8 saved_4F0 = 0, saved_7F0 = 0;
6031 struct net_device *dev = sp->dev;
1da177e4
LT		 6032
6033 /* Test Write Error at offset 0 */
ad4ebed0 6034 /* Note that SPI interface allows write access to all areas
6035 * of EEPROM. Hence doing all negative testing only for Xframe I.
6036 */
6037 if (sp->device_type == XFRAME_I_DEVICE)
6038 if (!write_eeprom(sp, 0, 0, 3))
6039 fail = 1;
6040
6041 /* Save current values at offsets 0x4F0 and 0x7F0 */
6042 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6043 saved_4F0 = 1;
6044 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6045 saved_7F0 = 1;
1da177e4
LT		 6046
6047 /* Test Write at offset 4f0 */
ad4ebed0 6048 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6049 fail = 1;
6050 if (read_eeprom(sp, 0x4F0, &ret_data))
6051 fail = 1;
6052
ad4ebed0 6053 if (ret_data != 0x012345) {
26b7625c 6054 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6055 "Data written %llx Data read %llx\n",
6056 dev->name, (unsigned long long)0x12345,
6057 (unsigned long long)ret_data);
1da177e4 6058 fail = 1;
ad4ebed0 6059 }
1da177e4
LT		 6060
6061 /* Reset the EEPROM data go FFFF */
ad4ebed0 6062 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6063
6064 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6065 if (sp->device_type == XFRAME_I_DEVICE)
6066 if (!write_eeprom(sp, 0x07C, 0, 3))
6067 fail = 1;
1da177e4 6068
ad4ebed0 6069 /* Test Write Request at offset 0x7f0 */
6070 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6071 fail = 1;
ad4ebed0 6072 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6073 fail = 1;
6074
ad4ebed0 6075 if (ret_data != 0x012345) {
26b7625c 6076 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6077 "Data written %llx Data read %llx\n",
6078 dev->name, (unsigned long long)0x12345,
6079 (unsigned long long)ret_data);
1da177e4 6080 fail = 1;
ad4ebed0 6081 }
1da177e4
LT		 6082
6083 /* Reset the EEPROM data go FFFF */
ad4ebed0 6084 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6085
ad4ebed0 6086 if (sp->device_type == XFRAME_I_DEVICE) {
6087 /* Test Write Error at offset 0x80 */
6088 if (!write_eeprom(sp, 0x080, 0, 3))
6089 fail = 1;
1da177e4 6090
ad4ebed0 6091 /* Test Write Error at offset 0xfc */
6092 if (!write_eeprom(sp, 0x0FC, 0, 3))
6093 fail = 1;
1da177e4 6094
ad4ebed0 6095 /* Test Write Error at offset 0x100 */
6096 if (!write_eeprom(sp, 0x100, 0, 3))
6097 fail = 1;
1da177e4 6098
ad4ebed0 6099 /* Test Write Error at offset 4ec */
6100 if (!write_eeprom(sp, 0x4EC, 0, 3))
6101 fail = 1;
6102 }
6103
6104 /* Restore values at offsets 0x4F0 and 0x7F0 */
6105 if (saved_4F0)
6106 write_eeprom(sp, 0x4F0, org_4F0, 3);
6107 if (saved_7F0)
6108 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6109
6110 *data = fail;
ad4ebed0 6111 return fail;
1da177e4
LT		 6112}
6113
6114/**
6115 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6116 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6117 * s2io_nic structure.
20346722 6118 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6119 * the driver.
6120 * Description:
6121 * This invokes the MemBist test of the card. We give around
6122 * 2 secs time for the Test to complete. If it's still not complete
20346722 6123 * within this peiod, we consider that the test failed.
1da177e4
LT		 6124 * Return value:
6125 * 0 on success and -1 on failure.
6126 */
6127
d44570e4 6128static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6129{
6130 u8 bist = 0;
6131 int cnt = 0, ret = -1;
6132
6133 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6134 bist |= PCI_BIST_START;
6135 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6136
6137 while (cnt < 20) {
6138 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6139 if (!(bist & PCI_BIST_START)) {
6140 *data = (bist & PCI_BIST_CODE_MASK);
6141 ret = 0;
6142 break;
6143 }
6144 msleep(100);
6145 cnt++;
6146 }
6147
6148 return ret;
6149}
6150
6151/**
20346722 6152 * s2io-link_test - verifies the link state of the nic
6153 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6154 * s2io_nic structure.
6155 * @data: variable that returns the result of each of the test conducted by
6156 * the driver.
6157 * Description:
20346722 6158 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6159 * argument 'data' appropriately.
6160 * Return value:
6161 * 0 on success.
6162 */
6163
d44570e4 6164static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6165{
1ee6dd77 6166 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6167 u64 val64;
6168
6169 val64 = readq(&bar0->adapter_status);
d44570e4 6170 if (!(LINK_IS_UP(val64)))
1da177e4 6171 *data = 1;
c92ca04b
AR		 6172 else
6173 *data = 0;
1da177e4 6174
b41477f3 6175 return *data;
1da177e4
LT		 6176}
6177
6178/**
20346722 6179 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6180 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6181 * s2io_nic structure.
20346722 6182 * @data - variable that returns the result of each of the test
1da177e4
LT		 6183 * conducted by the driver.
6184 * Description:
20346722 6185 * This is one of the offline test that tests the read and write
1da177e4
LT		 6186 * access to the RldRam chip on the NIC.
6187 * Return value:
6188 * 0 on success.
6189 */
6190
d44570e4 6191static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6192{
1ee6dd77 6193 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6194 u64 val64;
ad4ebed0 6195 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6196
6197 val64 = readq(&bar0->adapter_control);
6198 val64 &= ~ADAPTER_ECC_EN;
6199 writeq(val64, &bar0->adapter_control);
6200
6201 val64 = readq(&bar0->mc_rldram_test_ctrl);
6202 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6203 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6204
6205 val64 = readq(&bar0->mc_rldram_mrs);
6206 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6207 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6208
6209 val64 |= MC_RLDRAM_MRS_ENABLE;
6210 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6211
6212 while (iteration < 2) {
6213 val64 = 0x55555555aaaa0000ULL;
d44570e4 6214 if (iteration == 1)
1da177e4 6215 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6216 writeq(val64, &bar0->mc_rldram_test_d0);
6217
6218 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6219 if (iteration == 1)
1da177e4 6220 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6221 writeq(val64, &bar0->mc_rldram_test_d1);
6222
6223 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6224 if (iteration == 1)
1da177e4 6225 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6226 writeq(val64, &bar0->mc_rldram_test_d2);
6227
ad4ebed0 6228 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6229 writeq(val64, &bar0->mc_rldram_test_add);
6230
d44570e4
JP		 6231 val64 = MC_RLDRAM_TEST_MODE |
6232 MC_RLDRAM_TEST_WRITE |
6233 MC_RLDRAM_TEST_GO;
ad4ebed0 6234 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6235
6236 for (cnt = 0; cnt < 5; cnt++) {
6237 val64 = readq(&bar0->mc_rldram_test_ctrl);
6238 if (val64 & MC_RLDRAM_TEST_DONE)
6239 break;
6240 msleep(200);
6241 }
6242
6243 if (cnt == 5)
6244 break;
6245
ad4ebed0 6246 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6247 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6248
6249 for (cnt = 0; cnt < 5; cnt++) {
6250 val64 = readq(&bar0->mc_rldram_test_ctrl);
6251 if (val64 & MC_RLDRAM_TEST_DONE)
6252 break;
6253 msleep(500);
6254 }
6255
6256 if (cnt == 5)
6257 break;
6258
6259 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6260 if (!(val64 & MC_RLDRAM_TEST_PASS))
6261 test_fail = 1;
1da177e4
LT		 6262
6263 iteration++;
6264 }
6265
ad4ebed0 6266 *data = test_fail;
1da177e4 6267
ad4ebed0 6268 /* Bring the adapter out of test mode */
6269 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6270
6271 return test_fail;
1da177e4
LT		 6272}
6273
6274/**
6275 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6276 * @sp : private member of the device structure, which is a pointer to the
6277 * s2io_nic structure.
6278 * @ethtest : pointer to a ethtool command specific structure that will be
6279 * returned to the user.
20346722 6280 * @data : variable that returns the result of each of the test
1da177e4
LT		 6281 * conducted by the driver.
6282 * Description:
6283 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6284 * the health of the card.
6285 * Return value:
6286 * void
6287 */
6288
6289static void s2io_ethtool_test(struct net_device *dev,
6290 struct ethtool_test *ethtest,
d44570e4 6291 uint64_t *data)
1da177e4 6292{
4cf1653a 6293 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6294 int orig_state = netif_running(sp->dev);
6295
6296 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6297 /* Offline Tests. */
20346722 6298 if (orig_state)
1da177e4 6299 s2io_close(sp->dev);
1da177e4
LT		 6300
6301 if (s2io_register_test(sp, &data[0]))
6302 ethtest->flags |= ETH_TEST_FL_FAILED;
6303
6304 s2io_reset(sp);
1da177e4
LT		 6305
6306 if (s2io_rldram_test(sp, &data[3]))
6307 ethtest->flags |= ETH_TEST_FL_FAILED;
6308
6309 s2io_reset(sp);
1da177e4
LT		 6310
6311 if (s2io_eeprom_test(sp, &data[1]))
6312 ethtest->flags |= ETH_TEST_FL_FAILED;
6313
6314 if (s2io_bist_test(sp, &data[4]))
6315 ethtest->flags |= ETH_TEST_FL_FAILED;
6316
6317 if (orig_state)
6318 s2io_open(sp->dev);
6319
6320 data[2] = 0;
6321 } else {
6322 /* Online Tests. */
6323 if (!orig_state) {
d44570e4 6324 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6325 dev->name);
6326 data[0] = -1;
6327 data[1] = -1;
6328 data[2] = -1;
6329 data[3] = -1;
6330 data[4] = -1;
6331 }
6332
6333 if (s2io_link_test(sp, &data[2]))
6334 ethtest->flags |= ETH_TEST_FL_FAILED;
6335
6336 data[0] = 0;
6337 data[1] = 0;
6338 data[3] = 0;
6339 data[4] = 0;
6340 }
6341}
6342
6343static void s2io_get_ethtool_stats(struct net_device *dev,
6344 struct ethtool_stats *estats,
d44570e4 6345 u64 *tmp_stats)
1da177e4 6346{
8116f3cf 6347 int i = 0, k;
4cf1653a 6348 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 6349 struct stat_block *stats = sp->mac_control.stats_info;
6350 struct swStat *swstats = &stats->sw_stat;
6351 struct xpakStat *xstats = &stats->xpak_stat;
1da177e4 6352
7ba013ac 6353 s2io_updt_stats(sp);
541ae68f 6354 tmp_stats[i++] =
ffb5df6c
JP		 6355 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6356 le32_to_cpu(stats->tmac_frms);
541ae68f 6357 tmp_stats[i++] =
ffb5df6c
JP		 6358 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6359 le32_to_cpu(stats->tmac_data_octets);
6360 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
541ae68f 6361 tmp_stats[i++] =
ffb5df6c
JP		 6362 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6363 le32_to_cpu(stats->tmac_mcst_frms);
541ae68f 6364 tmp_stats[i++] =
ffb5df6c
JP		 6365 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6366 le32_to_cpu(stats->tmac_bcst_frms);
6367 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
bd1034f0 6368 tmp_stats[i++] =
ffb5df6c
JP		 6369 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6370 le32_to_cpu(stats->tmac_ttl_octets);
bd1034f0 6371 tmp_stats[i++] =
ffb5df6c
JP		 6372 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6373 le32_to_cpu(stats->tmac_ucst_frms);
d44570e4 6374 tmp_stats[i++] =
ffb5df6c
JP		 6375 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6376 le32_to_cpu(stats->tmac_nucst_frms);
541ae68f 6377 tmp_stats[i++] =
ffb5df6c
JP		 6378 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6379 le32_to_cpu(stats->tmac_any_err_frms);
6380 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6381 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
541ae68f 6382 tmp_stats[i++] =
ffb5df6c
JP		 6383 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6384 le32_to_cpu(stats->tmac_vld_ip);
541ae68f 6385 tmp_stats[i++] =
ffb5df6c
JP		 6386 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6387 le32_to_cpu(stats->tmac_drop_ip);
541ae68f 6388 tmp_stats[i++] =
ffb5df6c
JP		 6389 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6390 le32_to_cpu(stats->tmac_icmp);
541ae68f 6391 tmp_stats[i++] =
ffb5df6c
JP		 6392 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6393 le32_to_cpu(stats->tmac_rst_tcp);
6394 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6395 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6396 le32_to_cpu(stats->tmac_udp);
541ae68f 6397 tmp_stats[i++] =
ffb5df6c
JP		 6398 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6399 le32_to_cpu(stats->rmac_vld_frms);
541ae68f 6400 tmp_stats[i++] =
ffb5df6c
JP		 6401 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6402 le32_to_cpu(stats->rmac_data_octets);
6403 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6404 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
541ae68f 6405 tmp_stats[i++] =
ffb5df6c
JP		 6406 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6407 le32_to_cpu(stats->rmac_vld_mcst_frms);
541ae68f 6408 tmp_stats[i++] =
ffb5df6c
JP		 6409 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6410 le32_to_cpu(stats->rmac_vld_bcst_frms);
6411 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6412 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6413 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
d44570e4 6416 tmp_stats[i++] =
ffb5df6c
JP		 6417 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6418 le32_to_cpu(stats->rmac_ttl_octets);
bd1034f0 6419 tmp_stats[i++] =
ffb5df6c
JP		 6420 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6421 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
d44570e4 6422 tmp_stats[i++] =
ffb5df6c
JP		 6423 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6424 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
541ae68f 6425 tmp_stats[i++] =
ffb5df6c
JP		 6426 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6427 le32_to_cpu(stats->rmac_discarded_frms);
d44570e4 6428 tmp_stats[i++] =
ffb5df6c
JP		 6429 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6430 << 32 | le32_to_cpu(stats->rmac_drop_events);
6431 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6432 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
541ae68f 6433 tmp_stats[i++] =
ffb5df6c
JP		 6434 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6435 le32_to_cpu(stats->rmac_usized_frms);
541ae68f 6436 tmp_stats[i++] =
ffb5df6c
JP		 6437 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6438 le32_to_cpu(stats->rmac_osized_frms);
541ae68f 6439 tmp_stats[i++] =
ffb5df6c
JP		 6440 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6441 le32_to_cpu(stats->rmac_frag_frms);
541ae68f 6442 tmp_stats[i++] =
ffb5df6c
JP		 6443 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6444 le32_to_cpu(stats->rmac_jabber_frms);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6446 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6447 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6448 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6449 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6450 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
bd1034f0 6451 tmp_stats[i++] =
ffb5df6c
JP		 6452 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6453 le32_to_cpu(stats->rmac_ip);
6454 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6455 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
bd1034f0 6456 tmp_stats[i++] =
ffb5df6c
JP		 6457 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6458 le32_to_cpu(stats->rmac_drop_ip);
bd1034f0 6459 tmp_stats[i++] =
ffb5df6c
JP		 6460 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6461 le32_to_cpu(stats->rmac_icmp);
6462 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
bd1034f0 6463 tmp_stats[i++] =
ffb5df6c
JP		 6464 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6465 le32_to_cpu(stats->rmac_udp);
541ae68f 6466 tmp_stats[i++] =
ffb5df6c
JP		 6467 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6468 le32_to_cpu(stats->rmac_err_drp_udp);
6469 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6470 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6471 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6472 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6473 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6474 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6475 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6476 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6477 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6478 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6479 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6480 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6481 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6482 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6483 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6484 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6485 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
541ae68f 6486 tmp_stats[i++] =
ffb5df6c
JP		 6487 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6488 le32_to_cpu(stats->rmac_pause_cnt);
6489 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6490 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
541ae68f 6491 tmp_stats[i++] =
ffb5df6c
JP		 6492 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6493 le32_to_cpu(stats->rmac_accepted_ip);
6494 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6495 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6496 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6497 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6498 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6499 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6500 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6501 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6502 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6503 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6504 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6505 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6506 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6507 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6508 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6509 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6510 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6511 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6512 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
fa1f0cb3
SS		 6513
6514 /* Enhanced statistics exist only for Hercules */
d44570e4 6515 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6516 tmp_stats[i++] =
ffb5df6c 6517 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
fa1f0cb3 6518 tmp_stats[i++] =
ffb5df6c 6519 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
fa1f0cb3 6520 tmp_stats[i++] =
ffb5df6c
JP		 6521 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6522 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6523 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6524 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6525 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6526 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6527 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6528 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6529 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6530 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6531 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6532 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6533 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6534 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
fa1f0cb3
SS		 6535 }
6536
7ba013ac 6537 tmp_stats[i++] = 0;
ffb5df6c
JP		 6538 tmp_stats[i++] = swstats->single_ecc_errs;
6539 tmp_stats[i++] = swstats->double_ecc_errs;
6540 tmp_stats[i++] = swstats->parity_err_cnt;
6541 tmp_stats[i++] = swstats->serious_err_cnt;
6542 tmp_stats[i++] = swstats->soft_reset_cnt;
6543 tmp_stats[i++] = swstats->fifo_full_cnt;
8116f3cf 6544 for (k = 0; k < MAX_RX_RINGS; k++)
ffb5df6c
JP		 6545 tmp_stats[i++] = swstats->ring_full_cnt[k];
6546 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6547 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6548 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6549 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6550 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6551 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6552 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6553 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6554 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6555 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6556 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6557 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6558 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6559 tmp_stats[i++] = swstats->sending_both;
6560 tmp_stats[i++] = swstats->outof_sequence_pkts;
6561 tmp_stats[i++] = swstats->flush_max_pkts;
6562 if (swstats->num_aggregations) {
6563 u64 tmp = swstats->sum_avg_pkts_aggregated;
bd1034f0 6564 int count = 0;
6aa20a22 6565 /*
bd1034f0
AR		 6566 * Since 64-bit divide does not work on all platforms,
6567 * do repeated subtraction.
6568 */
ffb5df6c
JP		 6569 while (tmp >= swstats->num_aggregations) {
6570 tmp -= swstats->num_aggregations;
bd1034f0
AR		 6571 count++;
6572 }
6573 tmp_stats[i++] = count;
d44570e4 6574 } else
bd1034f0 6575 tmp_stats[i++] = 0;
ffb5df6c
JP		 6576 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6577 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6578 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6579 tmp_stats[i++] = swstats->mem_allocated;
6580 tmp_stats[i++] = swstats->mem_freed;
6581 tmp_stats[i++] = swstats->link_up_cnt;
6582 tmp_stats[i++] = swstats->link_down_cnt;
6583 tmp_stats[i++] = swstats->link_up_time;
6584 tmp_stats[i++] = swstats->link_down_time;
6585
6586 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6587 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6588 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6589 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6590 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6591
6592 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6593 tmp_stats[i++] = swstats->rx_abort_cnt;
6594 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6595 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6596 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6597 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6598 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6599 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6600 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6601 tmp_stats[i++] = swstats->tda_err_cnt;
6602 tmp_stats[i++] = swstats->pfc_err_cnt;
6603 tmp_stats[i++] = swstats->pcc_err_cnt;
6604 tmp_stats[i++] = swstats->tti_err_cnt;
6605 tmp_stats[i++] = swstats->tpa_err_cnt;
6606 tmp_stats[i++] = swstats->sm_err_cnt;
6607 tmp_stats[i++] = swstats->lso_err_cnt;
6608 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6609 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6610 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6611 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6612 tmp_stats[i++] = swstats->rc_err_cnt;
6613 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6614 tmp_stats[i++] = swstats->rpa_err_cnt;
6615 tmp_stats[i++] = swstats->rda_err_cnt;
6616 tmp_stats[i++] = swstats->rti_err_cnt;
6617 tmp_stats[i++] = swstats->mc_err_cnt;
1da177e4
LT		 6618}
6619
ac1f60db 6620static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6621{
d44570e4 6622 return XENA_REG_SPACE;
1da177e4
LT		 6623}
6624
6625
d44570e4 6626static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
1da177e4 6627{
4cf1653a 6628 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 6629
d44570e4 6630 return sp->rx_csum;
1da177e4 6631}
ac1f60db
AB		 6632
6633static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6634{
4cf1653a 6635 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6636
6637 if (data)
6638 sp->rx_csum = 1;
6639 else
6640 sp->rx_csum = 0;
6641
6642 return 0;
6643}
ac1f60db
AB		 6644
6645static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6646{
d44570e4 6647 return XENA_EEPROM_SPACE;
1da177e4
LT		 6648}
6649
b9f2c044 6650static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6651{
4cf1653a 6652 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6653
6654 switch (sset) {
6655 case ETH_SS_TEST:
6656 return S2IO_TEST_LEN;
6657 case ETH_SS_STATS:
d44570e4 6658 switch (sp->device_type) {
b9f2c044
JG		 6659 case XFRAME_I_DEVICE:
6660 return XFRAME_I_STAT_LEN;
6661 case XFRAME_II_DEVICE:
6662 return XFRAME_II_STAT_LEN;
6663 default:
6664 return 0;
6665 }
6666 default:
6667 return -EOPNOTSUPP;
6668 }
1da177e4 6669}
ac1f60db
AB		 6670
6671static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6672 u32 stringset, u8 *data)
1da177e4 6673{
fa1f0cb3 6674 int stat_size = 0;
4cf1653a 6675 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6676
1da177e4
LT		 6677 switch (stringset) {
6678 case ETH_SS_TEST:
6679 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6680 break;
6681 case ETH_SS_STATS:
fa1f0cb3 6682 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6683 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6684 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6685 memcpy(data + stat_size,
d44570e4
JP		 6686 &ethtool_enhanced_stats_keys,
6687 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6688 stat_size += sizeof(ethtool_enhanced_stats_keys);
6689 }
6690
6691 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6692 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6693 }
6694}
1da177e4 6695
ac1f60db 6696static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6697{
6698 if (data)
6699 dev->features |= NETIF_F_IP_CSUM;
6700 else
6701 dev->features &= ~NETIF_F_IP_CSUM;
6702
6703 return 0;
6704}
6705
75c30b13
AR		 6706static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6707{
6708 return (dev->features & NETIF_F_TSO) != 0;
6709}
6710static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6711{
6712 if (data)
6713 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6714 else
6715 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6716
6717 return 0;
6718}
1da177e4 6719
7282d491 6720static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6721 .get_settings = s2io_ethtool_gset,
6722 .set_settings = s2io_ethtool_sset,
6723 .get_drvinfo = s2io_ethtool_gdrvinfo,
6724 .get_regs_len = s2io_ethtool_get_regs_len,
6725 .get_regs = s2io_ethtool_gregs,
6726 .get_link = ethtool_op_get_link,
6727 .get_eeprom_len = s2io_get_eeprom_len,
6728 .get_eeprom = s2io_ethtool_geeprom,
6729 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6730 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6731 .get_pauseparam = s2io_ethtool_getpause_data,
6732 .set_pauseparam = s2io_ethtool_setpause_data,
6733 .get_rx_csum = s2io_ethtool_get_rx_csum,
6734 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6735 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6736 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6737 .get_tso = s2io_ethtool_op_get_tso,
6738 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6739 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6740 .self_test = s2io_ethtool_test,
6741 .get_strings = s2io_ethtool_get_strings,
6742 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6743 .get_ethtool_stats = s2io_get_ethtool_stats,
6744 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6745};
6746
6747/**
20346722 6748 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6749 * @dev : Device pointer.
6750 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6751 * a proprietary structure used to pass information to the driver.
6752 * @cmd : This is used to distinguish between the different commands that
6753 * can be passed to the IOCTL functions.
6754 * Description:
20346722 6755 * Currently there are no special functionality supported in IOCTL, hence
6756 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6757 */
6758
ac1f60db 6759static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6760{
6761 return -EOPNOTSUPP;
6762}
6763
6764/**
6765 * s2io_change_mtu - entry point to change MTU size for the device.
6766 * @dev : device pointer.
6767 * @new_mtu : the new MTU size for the device.
6768 * Description: A driver entry point to change MTU size for the device.
6769 * Before changing the MTU the device must be stopped.
6770 * Return value:
6771 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6772 * file on failure.
6773 */
6774
ac1f60db 6775static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6776{
4cf1653a 6777 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6778 int ret = 0;
1da177e4
LT		 6779
6780 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6781 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6782 return -EPERM;
6783 }
6784
1da177e4 6785 dev->mtu = new_mtu;
d8892c6e 6786 if (netif_running(dev)) {
3a3d5756 6787 s2io_stop_all_tx_queue(sp);
e6a8fee2 6788 s2io_card_down(sp);
9f74ffde
SH		 6789 ret = s2io_card_up(sp);
6790 if (ret) {
d8892c6e 6791 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6792 __func__);
9f74ffde 6793 return ret;
d8892c6e 6794 }
3a3d5756 6795 s2io_wake_all_tx_queue(sp);
d8892c6e 6796 } else { /* Device is down */
1ee6dd77 6797 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e 6798 u64 val64 = new_mtu;
6799
6800 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6801 }
1da177e4 6802
9f74ffde 6803 return ret;
1da177e4
LT		 6804}
6805
1da177e4
LT		 6806/**
6807 * s2io_set_link - Set the LInk status
6808 * @data: long pointer to device private structue
6809 * Description: Sets the link status for the adapter
6810 */
6811
c4028958 6812static void s2io_set_link(struct work_struct *work)
1da177e4 6813{
d44570e4
JP		 6814 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6815 set_link_task);
1da177e4 6816 struct net_device *dev = nic->dev;
1ee6dd77 6817 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6818 register u64 val64;
6819 u16 subid;
6820
22747d6b
FR		 6821 rtnl_lock();
6822
6823 if (!netif_running(dev))
6824 goto out_unlock;
6825
92b84437 6826 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6827 /* The card is being reset, no point doing anything */
22747d6b 6828 goto out_unlock;
1da177e4
LT		 6829 }
6830
6831 subid = nic->pdev->subsystem_device;
a371a07d 6832 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6833 /*
6834 * Allow a small delay for the NICs self initiated
6835 * cleanup to complete.
6836 */
6837 msleep(100);
6838 }
1da177e4
LT		 6839
6840 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6841 if (LINK_IS_UP(val64)) {
6842 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6843 if (verify_xena_quiescence(nic)) {
6844 val64 = readq(&bar0->adapter_control);
6845 val64 |= ADAPTER_CNTL_EN;
1da177e4 6846 writeq(val64, &bar0->adapter_control);
19a60522 6847 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6848 nic->device_type, subid)) {
19a60522
SS		 6849 val64 = readq(&bar0->gpio_control);
6850 val64 |= GPIO_CTRL_GPIO_0;
6851 writeq(val64, &bar0->gpio_control);
6852 val64 = readq(&bar0->gpio_control);
6853 } else {
6854 val64 |= ADAPTER_LED_ON;
6855 writeq(val64, &bar0->adapter_control);
a371a07d 6856 }
f957bcf0 6857 nic->device_enabled_once = true;
19a60522 6858 } else {
9e39f7c5
JP		 6859 DBG_PRINT(ERR_DBG,
6860 "%s: Error: device is not Quiescent\n",
6861 dev->name);
3a3d5756 6862 s2io_stop_all_tx_queue(nic);
1da177e4 6863 }
19a60522 6864 }
92c48799
SS		 6865 val64 = readq(&bar0->adapter_control);
6866 val64 |= ADAPTER_LED_ON;
6867 writeq(val64, &bar0->adapter_control);
6868 s2io_link(nic, LINK_UP);
19a60522
SS		 6869 } else {
6870 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6871 subid)) {
6872 val64 = readq(&bar0->gpio_control);
6873 val64 &= ~GPIO_CTRL_GPIO_0;
6874 writeq(val64, &bar0->gpio_control);
6875 val64 = readq(&bar0->gpio_control);
1da177e4 6876 }
92c48799
SS		 6877 /* turn off LED */
6878 val64 = readq(&bar0->adapter_control);
d44570e4 6879 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6880 writeq(val64, &bar0->adapter_control);
19a60522 6881 s2io_link(nic, LINK_DOWN);
1da177e4 6882 }
92b84437 6883 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6884
6885out_unlock:
d8d70caf 6886 rtnl_unlock();
1da177e4
LT		 6887}
6888
1ee6dd77 6889static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6890 struct buffAdd *ba,
6891 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6892 u64 *temp2, int size)
5d3213cc
AR		 6893{
6894 struct net_device *dev = sp->dev;
491abf25 6895 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6896
6897 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6898 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6899 /* allocate skb */
6900 if (*skb) {
6901 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6902 /*
6903 * As Rx frame are not going to be processed,
6904 * using same mapped address for the Rxd
6905 * buffer pointer
6906 */
6d517a27 6907 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6908 } else {
6909 *skb = dev_alloc_skb(size);
6910 if (!(*skb)) {
9e39f7c5
JP		 6911 DBG_PRINT(INFO_DBG,
6912 "%s: Out of memory to allocate %s\n",
6913 dev->name, "1 buf mode SKBs");
ffb5df6c 6914 stats->mem_alloc_fail_cnt++;
5d3213cc
AR		 6915 return -ENOMEM ;
6916 }
ffb5df6c 6917 stats->mem_allocated += (*skb)->truesize;
5d3213cc
AR		 6918 /* storing the mapped addr in a temp variable
6919 * such it will be used for next rxd whose
6920 * Host Control is NULL
6921 */
6d517a27 6922 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6923 pci_map_single(sp->pdev, (*skb)->data,
6924 size - NET_IP_ALIGN,
6925 PCI_DMA_FROMDEVICE);
8d8bb39b 6926 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6927 goto memalloc_failed;
5d3213cc
AR		 6928 rxdp->Host_Control = (unsigned long) (*skb);
6929 }
6930 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6931 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6932 /* Two buffer Mode */
6933 if (*skb) {
6d517a27
VP		 6934 rxdp3->Buffer2_ptr = *temp2;
6935 rxdp3->Buffer0_ptr = *temp0;
6936 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6937 } else {
6938 *skb = dev_alloc_skb(size);
2ceaac75 6939 if (!(*skb)) {
9e39f7c5
JP		 6940 DBG_PRINT(INFO_DBG,
6941 "%s: Out of memory to allocate %s\n",
6942 dev->name,
6943 "2 buf mode SKBs");
ffb5df6c 6944 stats->mem_alloc_fail_cnt++;
2ceaac75
DR		 6945 return -ENOMEM;
6946 }
ffb5df6c 6947 stats->mem_allocated += (*skb)->truesize;
6d517a27 6948 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6949 pci_map_single(sp->pdev, (*skb)->data,
6950 dev->mtu + 4,
6951 PCI_DMA_FROMDEVICE);
8d8bb39b 6952 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6953 goto memalloc_failed;
6d517a27 6954 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6955 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6956 PCI_DMA_FROMDEVICE);
8d8bb39b 6957 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6958 rxdp3->Buffer0_ptr)) {
6959 pci_unmap_single(sp->pdev,
6960 (dma_addr_t)rxdp3->Buffer2_ptr,
6961 dev->mtu + 4,
6962 PCI_DMA_FROMDEVICE);
491abf25
VP		 6963 goto memalloc_failed;
6964 }
5d3213cc
AR		 6965 rxdp->Host_Control = (unsigned long) (*skb);
6966
6967 /* Buffer-1 will be dummy buffer not used */
6d517a27 6968 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6969 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 6970 PCI_DMA_FROMDEVICE);
8d8bb39b 6971 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6972 rxdp3->Buffer1_ptr)) {
6973 pci_unmap_single(sp->pdev,
6974 (dma_addr_t)rxdp3->Buffer0_ptr,
6975 BUF0_LEN, PCI_DMA_FROMDEVICE);
6976 pci_unmap_single(sp->pdev,
6977 (dma_addr_t)rxdp3->Buffer2_ptr,
6978 dev->mtu + 4,
6979 PCI_DMA_FROMDEVICE);
491abf25
VP		 6980 goto memalloc_failed;
6981 }
5d3213cc
AR		 6982 }
6983 }
6984 return 0;
d44570e4
JP		 6985
6986memalloc_failed:
6987 stats->pci_map_fail_cnt++;
6988 stats->mem_freed += (*skb)->truesize;
6989 dev_kfree_skb(*skb);
6990 return -ENOMEM;
5d3213cc 6991}
491abf25 6992
1ee6dd77
RB		 6993static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6994 int size)
5d3213cc
AR		 6995{
6996 struct net_device *dev = sp->dev;
6997 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 6998 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 6999 } else if (sp->rxd_mode == RXD_MODE_3B) {
7000 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
7001 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 7002 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 7003 }
7004}
7005
1ee6dd77 7006static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 7007{
7008 int i, j, k, blk_cnt = 0, size;
5d3213cc 7009 struct config_param *config = &sp->config;
ffb5df6c 7010 struct mac_info *mac_control = &sp->mac_control;
5d3213cc 7011 struct net_device *dev = sp->dev;
1ee6dd77 7012 struct RxD_t *rxdp = NULL;
5d3213cc 7013 struct sk_buff *skb = NULL;
1ee6dd77 7014 struct buffAdd *ba = NULL;
5d3213cc
AR		 7015 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
7016
7017 /* Calculate the size based on ring mode */
7018 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
7019 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
7020 if (sp->rxd_mode == RXD_MODE_1)
7021 size += NET_IP_ALIGN;
7022 else if (sp->rxd_mode == RXD_MODE_3B)
7023 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 7024
7025 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7026 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7027 struct ring_info *ring = &mac_control->rings[i];
7028
d44570e4 7029 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 7030
7031 for (j = 0; j < blk_cnt; j++) {
7032 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7033 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7034 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7035 ba = &ring->ba[j][k];
d44570e4
JP		 7036 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7037 (u64 *)&temp0_64,
7038 (u64 *)&temp1_64,
7039 (u64 *)&temp2_64,
7040 size) == -ENOMEM) {
ac1f90d6
SS		 7041 return 0;
7042 }
5d3213cc
AR		 7043
7044 set_rxd_buffer_size(sp, rxdp, size);
7045 wmb();
7046 /* flip the Ownership bit to Hardware */
7047 rxdp->Control_1 |= RXD_OWN_XENA;
7048 }
7049 }
7050 }
7051 return 0;
7052
7053}
7054
d44570e4 7055static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7056{
e6a8fee2 7057 int ret = 0;
c92ca04b 7058 struct net_device *dev = sp->dev;
e6a8fee2 7059 int err = 0;
1da177e4 7060
eaae7f72 7061 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7062 ret = s2io_enable_msi_x(sp);
7063 if (ret) {
7064 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7065 sp->config.intr_type = INTA;
20346722 7066 }
1da177e4 7067
d44570e4
JP		 7068 /*
7069 * Store the values of the MSIX table in
7070 * the struct s2io_nic structure
7071 */
e6a8fee2 7072 store_xmsi_data(sp);
c92ca04b 7073
e6a8fee2 7074 /* After proper initialization of H/W, register ISR */
eaae7f72 7075 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7076 int i, msix_rx_cnt = 0;
7077
f61e0a35
SH		 7078 for (i = 0; i < sp->num_entries; i++) {
7079 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7080 if (sp->s2io_entries[i].type ==
d44570e4 7081 MSIX_RING_TYPE) {
ac731ab6
SH		 7082 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7083 dev->name, i);
7084 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7085 s2io_msix_ring_handle,
7086 0,
7087 sp->desc[i],
7088 sp->s2io_entries[i].arg);
ac731ab6 7089 } else if (sp->s2io_entries[i].type ==
d44570e4 7090 MSIX_ALARM_TYPE) {
ac731ab6 7091 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7092 dev->name, i);
ac731ab6 7093 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7094 s2io_msix_fifo_handle,
7095 0,
7096 sp->desc[i],
7097 sp->s2io_entries[i].arg);
ac731ab6 7098
fb6a825b 7099 }
ac731ab6
SH		 7100 /* if either data or addr is zero print it. */
7101 if (!(sp->msix_info[i].addr &&
d44570e4 7102 sp->msix_info[i].data)) {
ac731ab6 7103 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7104 "%s @Addr:0x%llx Data:0x%llx\n",
7105 sp->desc[i],
7106 (unsigned long long)
7107 sp->msix_info[i].addr,
7108 (unsigned long long)
7109 ntohl(sp->msix_info[i].data));
ac731ab6 7110 } else
fb6a825b 7111 msix_rx_cnt++;
ac731ab6
SH		 7112 if (err) {
7113 remove_msix_isr(sp);
7114
7115 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7116 "%s:MSI-X-%d registration "
7117 "failed\n", dev->name, i);
ac731ab6
SH		 7118
7119 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7120 "%s: Defaulting to INTA\n",
7121 dev->name);
ac731ab6
SH		 7122 sp->config.intr_type = INTA;
7123 break;
fb6a825b 7124 }
ac731ab6
SH		 7125 sp->s2io_entries[i].in_use =
7126 MSIX_REGISTERED_SUCCESS;
c92ca04b 7127 }
e6a8fee2 7128 }
18b2b7bd 7129 if (!err) {
6cef2b8e 7130 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
9e39f7c5
JP		 7131 DBG_PRINT(INFO_DBG,
7132 "MSI-X-TX entries enabled through alarm vector\n");
18b2b7bd 7133 }
e6a8fee2 7134 }
eaae7f72 7135 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7136 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7137 sp->name, dev);
e6a8fee2
AR		 7138 if (err) {
7139 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7140 dev->name);
7141 return -1;
7142 }
7143 }
7144 return 0;
7145}
d44570e4
JP		 7146
7147static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7148{
18b2b7bd
SH		 7149 if (sp->config.intr_type == MSI_X)
7150 remove_msix_isr(sp);
7151 else
7152 remove_inta_isr(sp);
e6a8fee2
AR		 7153}
7154
d44570e4 7155static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7156{
7157 int cnt = 0;
1ee6dd77 7158 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7159 register u64 val64 = 0;
5f490c96
SH		 7160 struct config_param *config;
7161 config = &sp->config;
e6a8fee2 7162
9f74ffde
SH		 7163 if (!is_s2io_card_up(sp))
7164 return;
7165
e6a8fee2
AR		 7166 del_timer_sync(&sp->alarm_timer);
7167 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7168 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7169 msleep(50);
92b84437 7170 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7171
5f490c96 7172 /* Disable napi */
f61e0a35
SH		 7173 if (sp->config.napi) {
7174 int off = 0;
7175 if (config->intr_type == MSI_X) {
7176 for (; off < sp->config.rx_ring_num; off++)
7177 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7178 }
f61e0a35
SH		 7179 else
7180 napi_disable(&sp->napi);
7181 }
5f490c96 7182
e6a8fee2 7183 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7184 if (do_io)
7185 stop_nic(sp);
e6a8fee2
AR		 7186
7187 s2io_rem_isr(sp);
1da177e4 7188
01e16faa
SH		 7189 /* stop the tx queue, indicate link down */
7190 s2io_link(sp, LINK_DOWN);
7191
1da177e4 7192 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7193 while (do_io) {
5d3213cc
AR		 7194 /* As per the HW requirement we need to replenish the
7195 * receive buffer to avoid the ring bump. Since there is
7196 * no intention of processing the Rx frame at this pointwe are
7197 * just settting the ownership bit of rxd in Each Rx
7198 * ring to HW and set the appropriate buffer size
7199 * based on the ring mode
7200 */
7201 rxd_owner_bit_reset(sp);
7202
1da177e4 7203 val64 = readq(&bar0->adapter_status);
19a60522 7204 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7205 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7206 break;
1da177e4
LT		 7207 }
7208
7209 msleep(50);
7210 cnt++;
7211 if (cnt == 10) {
9e39f7c5
JP		 7212 DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7213 "adapter status reads 0x%llx\n",
d44570e4 7214 (unsigned long long)val64);
1da177e4
LT		 7215 break;
7216 }
d796fdb7
LV		 7217 }
7218 if (do_io)
7219 s2io_reset(sp);
1da177e4 7220
7ba013ac 7221 /* Free all Tx buffers */
1da177e4 7222 free_tx_buffers(sp);
7ba013ac 7223
7224 /* Free all Rx buffers */
1da177e4
LT		 7225 free_rx_buffers(sp);
7226
92b84437 7227 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7228}
7229
d44570e4 7230static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7231{
7232 do_s2io_card_down(sp, 1);
7233}
7234
d44570e4 7235static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7236{
cc6e7c44 7237 int i, ret = 0;
1da177e4 7238 struct config_param *config;
ffb5df6c 7239 struct mac_info *mac_control;
d44570e4 7240 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7241 u16 interruptible;
1da177e4
LT		 7242
7243 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7244 ret = init_nic(sp);
7245 if (ret != 0) {
1da177e4
LT		 7246 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7247 dev->name);
9f74ffde
SH		 7248 if (ret != -EIO)
7249 s2io_reset(sp);
7250 return ret;
1da177e4
LT		 7251 }
7252
20346722 7253 /*
7254 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7255 * Rx ring and initializing buffers into 30 Rx blocks
7256 */
1da177e4 7257 config = &sp->config;
ffb5df6c 7258 mac_control = &sp->mac_control;
1da177e4
LT		 7259
7260 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7261 struct ring_info *ring = &mac_control->rings[i];
7262
7263 ring->mtu = dev->mtu;
7264 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7265 if (ret) {
1da177e4
LT		 7266 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7267 dev->name);
7268 s2io_reset(sp);
7269 free_rx_buffers(sp);
7270 return -ENOMEM;
7271 }
7272 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7273 ring->rx_bufs_left);
1da177e4 7274 }
5f490c96
SH		 7275
7276 /* Initialise napi */
f61e0a35 7277 if (config->napi) {
f61e0a35
SH		 7278 if (config->intr_type == MSI_X) {
7279 for (i = 0; i < sp->config.rx_ring_num; i++)
7280 napi_enable(&sp->mac_control.rings[i].napi);
7281 } else {
7282 napi_enable(&sp->napi);
7283 }
7284 }
5f490c96 7285
19a60522
SS		 7286 /* Maintain the state prior to the open */
7287 if (sp->promisc_flg)
7288 sp->promisc_flg = 0;
7289 if (sp->m_cast_flg) {
7290 sp->m_cast_flg = 0;
d44570e4 7291 sp->all_multi_pos = 0;
19a60522 7292 }
1da177e4
LT		 7293
7294 /* Setting its receive mode */
7295 s2io_set_multicast(dev);
7296
7d3d0439 7297 if (sp->lro) {
b41477f3 7298 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7299 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7300 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7301 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7302 sp->lro_max_aggr_per_sess = lro_max_pkts;
7303 }
7304
1da177e4
LT		 7305 /* Enable Rx Traffic and interrupts on the NIC */
7306 if (start_nic(sp)) {
7307 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7308 s2io_reset(sp);
e6a8fee2
AR		 7309 free_rx_buffers(sp);
7310 return -ENODEV;
7311 }
7312
7313 /* Add interrupt service routine */
7314 if (s2io_add_isr(sp) != 0) {
eaae7f72 7315 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7316 s2io_rem_isr(sp);
7317 s2io_reset(sp);
1da177e4
LT		 7318 free_rx_buffers(sp);
7319 return -ENODEV;
7320 }
7321
25fff88e 7322 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7323
01e16faa
SH		 7324 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7325
e6a8fee2 7326 /* Enable select interrupts */
9caab458 7327 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7328 if (sp->config.intr_type != INTA) {
7329 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7330 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7331 } else {
e6a8fee2 7332 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7333 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7334 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7335 }
7336
1da177e4
LT		 7337 return 0;
7338}
7339
20346722 7340/**
1da177e4
LT		 7341 * s2io_restart_nic - Resets the NIC.
7342 * @data : long pointer to the device private structure
7343 * Description:
7344 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7345 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7346 * the run time of the watch dog routine which is run holding a
7347 * spin lock.
7348 */
7349
c4028958 7350static void s2io_restart_nic(struct work_struct *work)
1da177e4 7351{
1ee6dd77 7352 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7353 struct net_device *dev = sp->dev;
1da177e4 7354
22747d6b
FR		 7355 rtnl_lock();
7356
7357 if (!netif_running(dev))
7358 goto out_unlock;
7359
e6a8fee2 7360 s2io_card_down(sp);
1da177e4 7361 if (s2io_card_up(sp)) {
d44570e4 7362 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7363 }
3a3d5756 7364 s2io_wake_all_tx_queue(sp);
d44570e4 7365 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7366out_unlock:
7367 rtnl_unlock();
1da177e4
LT		 7368}
7369
20346722 7370/**
7371 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7372 * @dev : Pointer to net device structure
7373 * Description:
7374 * This function is triggered if the Tx Queue is stopped
7375 * for a pre-defined amount of time when the Interface is still up.
7376 * If the Interface is jammed in such a situation, the hardware is
7377 * reset (by s2io_close) and restarted again (by s2io_open) to
7378 * overcome any problem that might have been caused in the hardware.
7379 * Return value:
7380 * void
7381 */
7382
7383static void s2io_tx_watchdog(struct net_device *dev)
7384{
4cf1653a 7385 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 7386 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7387
7388 if (netif_carrier_ok(dev)) {
ffb5df6c 7389 swstats->watchdog_timer_cnt++;
1da177e4 7390 schedule_work(&sp->rst_timer_task);
ffb5df6c 7391 swstats->soft_reset_cnt++;
1da177e4
LT		 7392 }
7393}
7394
7395/**
7396 * rx_osm_handler - To perform some OS related operations on SKB.
7397 * @sp: private member of the device structure,pointer to s2io_nic structure.
7398 * @skb : the socket buffer pointer.
7399 * @len : length of the packet
7400 * @cksum : FCS checksum of the frame.
7401 * @ring_no : the ring from which this RxD was extracted.
20346722 7402 * Description:
b41477f3 7403 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7404 * some OS related operations on the SKB before passing it to the upper
7405 * layers. It mainly checks if the checksum is OK, if so adds it to the
7406 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7407 * to the upper layer. If the checksum is wrong, it increments the Rx
7408 * packet error count, frees the SKB and returns error.
7409 * Return value:
7410 * SUCCESS on success and -1 on failure.
7411 */
1ee6dd77 7412static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7413{
1ee6dd77 7414 struct s2io_nic *sp = ring_data->nic;
d44570e4 7415 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7416 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7417 ((unsigned long)rxdp->Host_Control);
20346722 7418 int ring_no = ring_data->ring_no;
1da177e4 7419 u16 l3_csum, l4_csum;
863c11a9 7420 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7421 struct lro *uninitialized_var(lro);
f9046eb3 7422 u8 err_mask;
ffb5df6c 7423 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
da6971d8 7424
20346722 7425 skb->dev = dev;
c92ca04b 7426
863c11a9 7427 if (err) {
bd1034f0 7428 /* Check for parity error */
d44570e4 7429 if (err & 0x1)
ffb5df6c 7430 swstats->parity_err_cnt++;
d44570e4 7431
f9046eb3 7432 err_mask = err >> 48;
d44570e4
JP		 7433 switch (err_mask) {
7434 case 1:
ffb5df6c 7435 swstats->rx_parity_err_cnt++;
491976b2
SH		 7436 break;
7437
d44570e4 7438 case 2:
ffb5df6c 7439 swstats->rx_abort_cnt++;
491976b2
SH		 7440 break;
7441
d44570e4 7442 case 3:
ffb5df6c 7443 swstats->rx_parity_abort_cnt++;
491976b2
SH		 7444 break;
7445
d44570e4 7446 case 4:
ffb5df6c 7447 swstats->rx_rda_fail_cnt++;
491976b2
SH		 7448 break;
7449
d44570e4 7450 case 5:
ffb5df6c 7451 swstats->rx_unkn_prot_cnt++;
491976b2
SH		 7452 break;
7453
d44570e4 7454 case 6:
ffb5df6c 7455 swstats->rx_fcs_err_cnt++;
491976b2 7456 break;
bd1034f0 7457
d44570e4 7458 case 7:
ffb5df6c 7459 swstats->rx_buf_size_err_cnt++;
491976b2
SH		 7460 break;
7461
d44570e4 7462 case 8:
ffb5df6c 7463 swstats->rx_rxd_corrupt_cnt++;
491976b2
SH		 7464 break;
7465
d44570e4 7466 case 15:
ffb5df6c 7467 swstats->rx_unkn_err_cnt++;
491976b2
SH		 7468 break;
7469 }
863c11a9 7470 /*
d44570e4
JP		 7471 * Drop the packet if bad transfer code. Exception being
7472 * 0x5, which could be due to unsupported IPv6 extension header.
7473 * In this case, we let stack handle the packet.
7474 * Note that in this case, since checksum will be incorrect,
7475 * stack will validate the same.
7476 */
f9046eb3
OH		 7477 if (err_mask != 0x5) {
7478 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7479 dev->name, err_mask);
dc56e634 7480 dev->stats.rx_crc_errors++;
ffb5df6c 7481 swstats->mem_freed
491976b2 7482 += skb->truesize;
863c11a9 7483 dev_kfree_skb(skb);
0425b46a 7484 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7485 rxdp->Host_Control = 0;
7486 return 0;
7487 }
20346722 7488 }
1da177e4 7489
20346722 7490 rxdp->Host_Control = 0;
da6971d8
AR		 7491 if (sp->rxd_mode == RXD_MODE_1) {
7492 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7493
da6971d8 7494 skb_put(skb, len);
6d517a27 7495 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7496 int get_block = ring_data->rx_curr_get_info.block_index;
7497 int get_off = ring_data->rx_curr_get_info.offset;
7498 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7499 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7500 unsigned char *buff = skb_push(skb, buf0_len);
7501
1ee6dd77 7502 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8 7503 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7504 skb_put(skb, buf2_len);
da6971d8 7505 }
20346722 7506
d44570e4
JP		 7507 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7508 ((!ring_data->lro) ||
7509 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722 7510 (sp->rx_csum)) {
7511 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7512 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7513 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7514 /*
1da177e4
LT		 7515 * NIC verifies if the Checksum of the received
7516 * frame is Ok or not and accordingly returns
7517 * a flag in the RxD.
7518 */
7519 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7520 if (ring_data->lro) {
7d3d0439
RA		 7521 u32 tcp_len;
7522 u8 *tcp;
7523 int ret = 0;
7524
0425b46a 7525 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7526 skb->data, &tcp,
7527 &tcp_len, &lro,
7528 rxdp, sp);
7d3d0439 7529 switch (ret) {
d44570e4
JP		 7530 case 3: /* Begin anew */
7531 lro->parent = skb;
7532 goto aggregate;
7533 case 1: /* Aggregate */
7534 lro_append_pkt(sp, lro, skb, tcp_len);
7535 goto aggregate;
7536 case 4: /* Flush session */
7537 lro_append_pkt(sp, lro, skb, tcp_len);
7538 queue_rx_frame(lro->parent,
7539 lro->vlan_tag);
7540 clear_lro_session(lro);
ffb5df6c 7541 swstats->flush_max_pkts++;
d44570e4
JP		 7542 goto aggregate;
7543 case 2: /* Flush both */
7544 lro->parent->data_len = lro->frags_len;
ffb5df6c 7545 swstats->sending_both++;
d44570e4
JP		 7546 queue_rx_frame(lro->parent,
7547 lro->vlan_tag);
7548 clear_lro_session(lro);
7549 goto send_up;
7550 case 0: /* sessions exceeded */
7551 case -1: /* non-TCP or not L2 aggregatable */
7552 case 5: /*
7553 * First pkt in session not
7554 * L3/L4 aggregatable
7555 */
7556 break;
7557 default:
7558 DBG_PRINT(ERR_DBG,
7559 "%s: Samadhana!!\n",
7560 __func__);
7561 BUG();
7d3d0439
RA		 7562 }
7563 }
1da177e4 7564 } else {
20346722 7565 /*
7566 * Packet with erroneous checksum, let the
1da177e4
LT		 7567 * upper layers deal with it.
7568 */
7569 skb->ip_summed = CHECKSUM_NONE;
7570 }
cdb5bf02 7571 } else
1da177e4 7572 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7573
ffb5df6c 7574 swstats->mem_freed += skb->truesize;
7d3d0439 7575send_up:
0c8dfc83 7576 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7577 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7578aggregate:
0425b46a 7579 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7580 return SUCCESS;
7581}
7582
7583/**
7584 * s2io_link - stops/starts the Tx queue.
7585 * @sp : private member of the device structure, which is a pointer to the
7586 * s2io_nic structure.
7587 * @link : inidicates whether link is UP/DOWN.
7588 * Description:
7589 * This function stops/starts the Tx queue depending on whether the link
20346722 7590 * status of the NIC is is down or up. This is called by the Alarm
7591 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7592 * Return value:
7593 * void.
7594 */
7595
d44570e4 7596static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7597{
d44570e4 7598 struct net_device *dev = (struct net_device *)sp->dev;
ffb5df6c 7599 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7600
7601 if (link != sp->last_link_state) {
b7c5678f 7602 init_tti(sp, link);
1da177e4
LT		 7603 if (link == LINK_DOWN) {
7604 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7605 s2io_stop_all_tx_queue(sp);
1da177e4 7606 netif_carrier_off(dev);
ffb5df6c
JP		 7607 if (swstats->link_up_cnt)
7608 swstats->link_up_time =
7609 jiffies - sp->start_time;
7610 swstats->link_down_cnt++;
1da177e4
LT		 7611 } else {
7612 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
ffb5df6c
JP		 7613 if (swstats->link_down_cnt)
7614 swstats->link_down_time =
d44570e4 7615 jiffies - sp->start_time;
ffb5df6c 7616 swstats->link_up_cnt++;
1da177e4 7617 netif_carrier_on(dev);
3a3d5756 7618 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7619 }
7620 }
7621 sp->last_link_state = link;
491976b2 7622 sp->start_time = jiffies;
1da177e4
LT		 7623}
7624
20346722 7625/**
7626 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7627 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7628 * s2io_nic structure.
7629 * Description:
7630 * This function initializes a few of the PCI and PCI-X configuration registers
7631 * with recommended values.
7632 * Return value:
7633 * void
7634 */
7635
d44570e4 7636static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7637{
20346722 7638 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7639
7640 /* Enable Data Parity Error Recovery in PCI-X command register. */
7641 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7642 &(pcix_cmd));
1da177e4 7643 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7644 (pcix_cmd | 1));
1da177e4 7645 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7646 &(pcix_cmd));
1da177e4
LT		 7647
7648 /* Set the PErr Response bit in PCI command register. */
7649 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7650 pci_write_config_word(sp->pdev, PCI_COMMAND,
7651 (pci_cmd | PCI_COMMAND_PARITY));
7652 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7653}
7654
3a3d5756 7655static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7656 u8 *dev_multiq)
9dc737a7 7657{
d44570e4 7658 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
9e39f7c5 7659 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
d44570e4 7660 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7661
7662 if (tx_fifo_num < 1)
7663 tx_fifo_num = 1;
7664 else
7665 tx_fifo_num = MAX_TX_FIFOS;
7666
9e39f7c5 7667 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
9dc737a7 7668 }
2fda096d 7669
6cfc482b 7670 if (multiq)
3a3d5756 7671 *dev_multiq = multiq;
6cfc482b
SH		 7672
7673 if (tx_steering_type && (1 == tx_fifo_num)) {
7674 if (tx_steering_type != TX_DEFAULT_STEERING)
7675 DBG_PRINT(ERR_DBG,
9e39f7c5 7676 "Tx steering is not supported with "
d44570e4 7677 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7678 tx_steering_type = NO_STEERING;
7679 }
7680
7681 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7682 (tx_steering_type > TX_DEFAULT_STEERING)) {
7683 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7684 "Requested transmit steering not supported\n");
7685 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
6cfc482b 7686 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7687 }
7688
0425b46a 7689 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4 7690 DBG_PRINT(ERR_DBG,
9e39f7c5
JP		 7691 "Requested number of rx rings not supported\n");
7692 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
d44570e4 7693 MAX_RX_RINGS);
0425b46a 7694 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7695 }
0425b46a 7696
eccb8628 7697 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9e39f7c5 7698 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
9dc737a7
AR		 7699 "Defaulting to INTA\n");
7700 *dev_intr_type = INTA;
7701 }
596c5c97 7702
9dc737a7 7703 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7704 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7705 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
9e39f7c5 7706 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
d44570e4 7707 "Defaulting to INTA\n");
9dc737a7
AR		 7708 *dev_intr_type = INTA;
7709 }
fb6a825b 7710
6d517a27 7711 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9e39f7c5
JP		 7712 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7713 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
6d517a27 7714 rx_ring_mode = 1;
9dc737a7
AR		 7715 }
7716 return SUCCESS;
7717}
7718
9fc93a41
SS		 7719/**
7720 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7721 * or Traffic class respectively.
b7c5678f 7722 * @nic: device private variable
9fc93a41
SS		 7723 * Description: The function configures the receive steering to
7724 * desired receive ring.
7725 * Return Value: SUCCESS on success and
7726 * '-1' on failure (endian settings incorrect).
7727 */
7728static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7729{
7730 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7731 register u64 val64 = 0;
7732
7733 if (ds_codepoint > 63)
7734 return FAILURE;
7735
7736 val64 = RTS_DS_MEM_DATA(ring);
7737 writeq(val64, &bar0->rts_ds_mem_data);
7738
7739 val64 = RTS_DS_MEM_CTRL_WE |
7740 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7741 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7742
7743 writeq(val64, &bar0->rts_ds_mem_ctrl);
7744
7745 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7746 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7747 S2IO_BIT_RESET);
9fc93a41
SS		 7748}
7749
04025095
SH		 7750static const struct net_device_ops s2io_netdev_ops = {
7751 .ndo_open = s2io_open,
7752 .ndo_stop = s2io_close,
7753 .ndo_get_stats = s2io_get_stats,
7754 .ndo_start_xmit = s2io_xmit,
7755 .ndo_validate_addr = eth_validate_addr,
7756 .ndo_set_multicast_list = s2io_set_multicast,
7757 .ndo_do_ioctl = s2io_ioctl,
7758 .ndo_set_mac_address = s2io_set_mac_addr,
7759 .ndo_change_mtu = s2io_change_mtu,
7760 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7761 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7762 .ndo_tx_timeout = s2io_tx_watchdog,
7763#ifdef CONFIG_NET_POLL_CONTROLLER
7764 .ndo_poll_controller = s2io_netpoll,
7765#endif
7766};
7767
1da177e4 7768/**
20346722 7769 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7770 * @pdev : structure containing the PCI related information of the device.
7771 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7772 * Description:
7773 * The function initializes an adapter identified by the pci_dec structure.
20346722 7774 * All OS related initialization including memory and device structure and
7775 * initlaization of the device private variable is done. Also the swapper
7776 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7777 * registers of the device.
7778 * Return value:
7779 * returns 0 on success and negative on failure.
7780 */
7781
7782static int __devinit
7783s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7784{
1ee6dd77 7785 struct s2io_nic *sp;
1da177e4 7786 struct net_device *dev;
1da177e4 7787 int i, j, ret;
f957bcf0 7788 int dma_flag = false;
1da177e4
LT		 7789 u32 mac_up, mac_down;
7790 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7791 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7792 u16 subid;
1da177e4 7793 struct config_param *config;
ffb5df6c 7794 struct mac_info *mac_control;
541ae68f 7795 int mode;
cc6e7c44 7796 u8 dev_intr_type = intr_type;
3a3d5756 7797 u8 dev_multiq = 0;
1da177e4 7798
3a3d5756
SH		 7799 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7800 if (ret)
9dc737a7 7801 return ret;
1da177e4 7802
d44570e4
JP		 7803 ret = pci_enable_device(pdev);
7804 if (ret) {
1da177e4 7805 DBG_PRINT(ERR_DBG,
9e39f7c5 7806 "%s: pci_enable_device failed\n", __func__);
1da177e4
LT		 7807 return ret;
7808 }
7809
6a35528a 7810 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
9e39f7c5 7811 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
f957bcf0 7812 dma_flag = true;
d44570e4 7813 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7814 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7815 "Unable to obtain 64bit DMA "
7816 "for consistent allocations\n");
1da177e4
LT		 7817 pci_disable_device(pdev);
7818 return -ENOMEM;
7819 }
284901a9 7820 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
9e39f7c5 7821 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
1da177e4
LT		 7822 } else {
7823 pci_disable_device(pdev);
7824 return -ENOMEM;
7825 }
d44570e4
JP		 7826 ret = pci_request_regions(pdev, s2io_driver_name);
7827 if (ret) {
9e39f7c5 7828 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
d44570e4 7829 __func__, ret);
eccb8628
VP		 7830 pci_disable_device(pdev);
7831 return -ENODEV;
1da177e4 7832 }
3a3d5756 7833 if (dev_multiq)
6cfc482b 7834 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7835 else
b19fa1fa 7836 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7837 if (dev == NULL) {
7838 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7839 pci_disable_device(pdev);
7840 pci_release_regions(pdev);
7841 return -ENODEV;
7842 }
7843
7844 pci_set_master(pdev);
7845 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7846 SET_NETDEV_DEV(dev, &pdev->dev);
7847
7848 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7849 sp = netdev_priv(dev);
1ee6dd77 7850 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7851 sp->dev = dev;
7852 sp->pdev = pdev;
1da177e4 7853 sp->high_dma_flag = dma_flag;
f957bcf0 7854 sp->device_enabled_once = false;
da6971d8
AR		 7855 if (rx_ring_mode == 1)
7856 sp->rxd_mode = RXD_MODE_1;
7857 if (rx_ring_mode == 2)
7858 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7859
eaae7f72 7860 sp->config.intr_type = dev_intr_type;
1da177e4 7861
541ae68f 7862 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7863 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f 7864 sp->device_type = XFRAME_II_DEVICE;
7865 else
7866 sp->device_type = XFRAME_I_DEVICE;
7867
43b7c451 7868 sp->lro = lro_enable;
6aa20a22 7869
1da177e4
LT		 7870 /* Initialize some PCI/PCI-X fields of the NIC. */
7871 s2io_init_pci(sp);
7872
20346722 7873 /*
1da177e4 7874 * Setting the device configuration parameters.
20346722 7875 * Most of these parameters can be specified by the user during
7876 * module insertion as they are module loadable parameters. If
7877 * these parameters are not not specified during load time, they
1da177e4
LT		 7878 * are initialized with default values.
7879 */
1da177e4 7880 config = &sp->config;
ffb5df6c 7881 mac_control = &sp->mac_control;
1da177e4 7882
596c5c97 7883 config->napi = napi;
6cfc482b 7884 config->tx_steering_type = tx_steering_type;
596c5c97 7885
1da177e4 7886 /* Tx side parameters. */
6cfc482b
SH		 7887 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7888 config->tx_fifo_num = MAX_TX_FIFOS;
7889 else
7890 config->tx_fifo_num = tx_fifo_num;
7891
7892 /* Initialize the fifos used for tx steering */
7893 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7894 if (config->tx_fifo_num == 1)
7895 sp->total_tcp_fifos = 1;
7896 else
7897 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7898 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7899 sp->total_udp_fifos = 1;
7900 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7901 } else {
7902 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7903 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7904 sp->udp_fifo_idx = sp->total_tcp_fifos;
7905 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7906 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7907 }
7908
3a3d5756 7909 config->multiq = dev_multiq;
6cfc482b 7910 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7911 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7912
7913 tx_cfg->fifo_len = tx_fifo_len[i];
7914 tx_cfg->fifo_priority = i;
1da177e4
LT		 7915 }
7916
20346722 7917 /* mapping the QoS priority to the configured fifos */
7918 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7919 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7920
6cfc482b
SH		 7921 /* map the hashing selector table to the configured fifos */
7922 for (i = 0; i < config->tx_fifo_num; i++)
7923 sp->fifo_selector[i] = fifo_selector[i];
7924
7925
1da177e4
LT		 7926 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7927 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7928 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7929
7930 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7931 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7932 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7933 break;
7934 }
7935 }
fed5eccd
AR		 7936 /* + 2 because one Txd for skb->data and one Txd for UFO */
7937 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7938
7939 /* Rx side parameters. */
1da177e4 7940 config->rx_ring_num = rx_ring_num;
0425b46a 7941 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7942 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7943 struct ring_info *ring = &mac_control->rings[i];
7944
7945 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7946 rx_cfg->ring_priority = i;
7947 ring->rx_bufs_left = 0;
7948 ring->rxd_mode = sp->rxd_mode;
7949 ring->rxd_count = rxd_count[sp->rxd_mode];
7950 ring->pdev = sp->pdev;
7951 ring->dev = sp->dev;
1da177e4
LT		 7952 }
7953
7954 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7955 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7956
7957 rx_cfg->ring_org = RING_ORG_BUFF1;
7958 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7959 }
7960
7961 /* Setting Mac Control parameters */
7962 mac_control->rmac_pause_time = rmac_pause_time;
7963 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7964 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7965
7966
1da177e4
LT		 7967 /* initialize the shared memory used by the NIC and the host */
7968 if (init_shared_mem(sp)) {
d44570e4 7969 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 7970 ret = -ENOMEM;
7971 goto mem_alloc_failed;
7972 }
7973
275f165f 7974 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7975 if (!sp->bar0) {
19a60522 7976 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7977 dev->name);
7978 ret = -ENOMEM;
7979 goto bar0_remap_failed;
7980 }
7981
275f165f 7982 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7983 if (!sp->bar1) {
19a60522 7984 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7985 dev->name);
7986 ret = -ENOMEM;
7987 goto bar1_remap_failed;
7988 }
7989
7990 dev->irq = pdev->irq;
d44570e4 7991 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 7992
7993 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7994 for (j = 0; j < MAX_TX_FIFOS; j++) {
d44570e4
JP		 7995 mac_control->tx_FIFO_start[j] =
7996 (struct TxFIFO_element __iomem *)
7997 (sp->bar1 + (j * 0x00020000));
1da177e4
LT		 7998 }
7999
8000 /* Driver entry points */
04025095 8001 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 8002 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 8003 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
612eff0e 8004
1da177e4 8005 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 8006 if (sp->high_dma_flag == true)
1da177e4 8007 dev->features |= NETIF_F_HIGHDMA;
1da177e4 8008 dev->features |= NETIF_F_TSO;
f83ef8c0 8009 dev->features |= NETIF_F_TSO6;
db874e65 8010 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 8011 dev->features |= NETIF_F_UFO;
8012 dev->features |= NETIF_F_HW_CSUM;
8013 }
1da177e4 8014 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 8015 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
8016 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 8017
e960fc5c 8018 pci_save_state(sp->pdev);
1da177e4
LT		 8019
8020 /* Setting swapper control on the NIC, for proper reset operation */
8021 if (s2io_set_swapper(sp)) {
9e39f7c5 8022 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
1da177e4
LT		 8023 dev->name);
8024 ret = -EAGAIN;
8025 goto set_swap_failed;
8026 }
8027
541ae68f 8028 /* Verify if the Herc works on the slot its placed into */
8029 if (sp->device_type & XFRAME_II_DEVICE) {
8030 mode = s2io_verify_pci_mode(sp);
8031 if (mode < 0) {
9e39f7c5
JP		 8032 DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
8033 __func__);
541ae68f 8034 ret = -EBADSLT;
8035 goto set_swap_failed;
8036 }
8037 }
8038
f61e0a35
SH		 8039 if (sp->config.intr_type == MSI_X) {
8040 sp->num_entries = config->rx_ring_num + 1;
8041 ret = s2io_enable_msi_x(sp);
8042
8043 if (!ret) {
8044 ret = s2io_test_msi(sp);
8045 /* rollback MSI-X, will re-enable during add_isr() */
8046 remove_msix_isr(sp);
8047 }
8048 if (ret) {
8049
8050 DBG_PRINT(ERR_DBG,
9e39f7c5 8051 "MSI-X requested but failed to enable\n");
f61e0a35
SH		 8052 sp->config.intr_type = INTA;
8053 }
8054 }
8055
8056 if (config->intr_type == MSI_X) {
13d866a9
JP		 8057 for (i = 0; i < config->rx_ring_num ; i++) {
8058 struct ring_info *ring = &mac_control->rings[i];
8059
8060 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8061 }
f61e0a35
SH		 8062 } else {
8063 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8064 }
8065
541ae68f 8066 /* Not needed for Herc */
8067 if (sp->device_type & XFRAME_I_DEVICE) {
8068 /*
8069 * Fix for all "FFs" MAC address problems observed on
8070 * Alpha platforms
8071 */
8072 fix_mac_address(sp);
8073 s2io_reset(sp);
8074 }
1da177e4
LT		 8075
8076 /*
1da177e4
LT		 8077 * MAC address initialization.
8078 * For now only one mac address will be read and used.
8079 */
8080 bar0 = sp->bar0;
8081 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8082 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8083 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8084 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8085 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8086 S2IO_BIT_RESET);
1da177e4 8087 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8088 mac_down = (u32)tmp64;
1da177e4
LT		 8089 mac_up = (u32) (tmp64 >> 32);
8090
1da177e4
LT		 8091 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8092 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8093 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8094 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8095 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8096 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8097
1da177e4
LT		 8098 /* Set the factory defined MAC address initially */
8099 dev->addr_len = ETH_ALEN;
8100 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8101 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8102
faa4f796
SH		 8103 /* initialize number of multicast & unicast MAC entries variables */
8104 if (sp->device_type == XFRAME_I_DEVICE) {
8105 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8106 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8107 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8108 } else if (sp->device_type == XFRAME_II_DEVICE) {
8109 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8110 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8111 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8112 }
8113
8114 /* store mac addresses from CAM to s2io_nic structure */
8115 do_s2io_store_unicast_mc(sp);
8116
f61e0a35
SH		 8117 /* Configure MSIX vector for number of rings configured plus one */
8118 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8119 (config->intr_type == MSI_X))
f61e0a35
SH		 8120 sp->num_entries = config->rx_ring_num + 1;
8121
d44570e4 8122 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8123 store_xmsi_data(sp);
b41477f3
AR		 8124 /* reset Nic and bring it to known state */
8125 s2io_reset(sp);
8126
1da177e4 8127 /*
99993af6 8128 * Initialize link state flags
541ae68f 8129 * and the card state parameter
1da177e4 8130 */
92b84437 8131 sp->state = 0;
1da177e4 8132
1da177e4 8133 /* Initialize spinlocks */
13d866a9
JP		 8134 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8135 struct fifo_info *fifo = &mac_control->fifos[i];
8136
8137 spin_lock_init(&fifo->tx_lock);
8138 }
db874e65 8139
20346722 8140 /*
8141 * SXE-002: Configure link and activity LED to init state
8142 * on driver load.
1da177e4
LT		 8143 */
8144 subid = sp->pdev->subsystem_device;
8145 if ((subid & 0xFF) >= 0x07) {
8146 val64 = readq(&bar0->gpio_control);
8147 val64 |= 0x0000800000000000ULL;
8148 writeq(val64, &bar0->gpio_control);
8149 val64 = 0x0411040400000000ULL;
d44570e4 8150 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8151 val64 = readq(&bar0->gpio_control);
8152 }
8153
8154 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8155
8156 if (register_netdev(dev)) {
8157 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8158 ret = -ENODEV;
8159 goto register_failed;
8160 }
9dc737a7 8161 s2io_vpd_read(sp);
0c61ed5f 8162 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
d44570e4 8163 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8164 sp->product_name, pdev->revision);
b41477f3
AR		 8165 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8166 s2io_driver_version);
9e39f7c5
JP		 8167 DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8168 DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
9dc737a7 8169 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8170 mode = s2io_print_pci_mode(sp);
541ae68f 8171 if (mode < 0) {
541ae68f 8172 ret = -EBADSLT;
9dc737a7 8173 unregister_netdev(dev);
541ae68f 8174 goto set_swap_failed;
8175 }
541ae68f 8176 }
d44570e4
JP		 8177 switch (sp->rxd_mode) {
8178 case RXD_MODE_1:
8179 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8180 dev->name);
8181 break;
8182 case RXD_MODE_3B:
8183 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8184 dev->name);
8185 break;
9dc737a7 8186 }
db874e65 8187
f61e0a35
SH		 8188 switch (sp->config.napi) {
8189 case 0:
8190 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8191 break;
8192 case 1:
db874e65 8193 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8194 break;
8195 }
3a3d5756
SH		 8196
8197 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8198 sp->config.tx_fifo_num);
3a3d5756 8199
0425b46a
SH		 8200 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8201 sp->config.rx_ring_num);
8202
d44570e4
JP		 8203 switch (sp->config.intr_type) {
8204 case INTA:
8205 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8206 break;
8207 case MSI_X:
8208 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8209 break;
9dc737a7 8210 }
3a3d5756 8211 if (sp->config.multiq) {
13d866a9
JP		 8212 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8213 struct fifo_info *fifo = &mac_control->fifos[i];
8214
8215 fifo->multiq = config->multiq;
8216 }
3a3d5756 8217 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8218 dev->name);
3a3d5756
SH		 8219 } else
8220 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8221 dev->name);
3a3d5756 8222
6cfc482b
SH		 8223 switch (sp->config.tx_steering_type) {
8224 case NO_STEERING:
d44570e4
JP		 8225 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8226 dev->name);
8227 break;
6cfc482b 8228 case TX_PRIORITY_STEERING:
d44570e4
JP		 8229 DBG_PRINT(ERR_DBG,
8230 "%s: Priority steering enabled for transmit\n",
8231 dev->name);
6cfc482b
SH		 8232 break;
8233 case TX_DEFAULT_STEERING:
d44570e4
JP		 8234 DBG_PRINT(ERR_DBG,
8235 "%s: Default steering enabled for transmit\n",
8236 dev->name);
6cfc482b
SH		 8237 }
8238
7d3d0439
RA		 8239 if (sp->lro)
8240 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8241 dev->name);
db874e65 8242 if (ufo)
d44570e4
JP		 8243 DBG_PRINT(ERR_DBG,
8244 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8245 dev->name);
7ba013ac 8246 /* Initialize device name */
9dc737a7 8247 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8248
cd0fce03
BL		 8249 if (vlan_tag_strip)
8250 sp->vlan_strip_flag = 1;
8251 else
8252 sp->vlan_strip_flag = 0;
8253
20346722 8254 /*
8255 * Make Link state as off at this point, when the Link change
8256 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8257 * the right state.
8258 */
8259 netif_carrier_off(dev);
1da177e4
LT		 8260
8261 return 0;
8262
d44570e4
JP		 8263register_failed:
8264set_swap_failed:
1da177e4 8265 iounmap(sp->bar1);
d44570e4 8266bar1_remap_failed:
1da177e4 8267 iounmap(sp->bar0);
d44570e4
JP		 8268bar0_remap_failed:
8269mem_alloc_failed:
1da177e4
LT		 8270 free_shared_mem(sp);
8271 pci_disable_device(pdev);
eccb8628 8272 pci_release_regions(pdev);
1da177e4
LT		 8273 pci_set_drvdata(pdev, NULL);
8274 free_netdev(dev);
8275
8276 return ret;
8277}
8278
8279/**
20346722 8280 * s2io_rem_nic - Free the PCI device
1da177e4 8281 * @pdev: structure containing the PCI related information of the device.
20346722 8282 * Description: This function is called by the Pci subsystem to release a
1da177e4 8283 * PCI device and free up all resource held up by the device. This could
20346722 8284 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8285 * from memory.
8286 */
8287
8288static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8289{
8290 struct net_device *dev =
d44570e4 8291 (struct net_device *)pci_get_drvdata(pdev);
1ee6dd77 8292 struct s2io_nic *sp;
1da177e4
LT		 8293
8294 if (dev == NULL) {
8295 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8296 return;
8297 }
8298
22747d6b
FR		 8299 flush_scheduled_work();
8300
4cf1653a 8301 sp = netdev_priv(dev);
1da177e4
LT		 8302 unregister_netdev(dev);
8303
8304 free_shared_mem(sp);
8305 iounmap(sp->bar0);
8306 iounmap(sp->bar1);
eccb8628 8307 pci_release_regions(pdev);
1da177e4 8308 pci_set_drvdata(pdev, NULL);
1da177e4 8309 free_netdev(dev);
19a60522 8310 pci_disable_device(pdev);
1da177e4
LT		 8311}
8312
8313/**
8314 * s2io_starter - Entry point for the driver
8315 * Description: This function is the entry point for the driver. It verifies
8316 * the module loadable parameters and initializes PCI configuration space.
8317 */
8318
43b7c451 8319static int __init s2io_starter(void)
1da177e4 8320{
29917620 8321 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8322}
8323
8324/**
20346722 8325 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8326 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8327 */
8328
372cc597 8329static __exit void s2io_closer(void)
1da177e4
LT		 8330{
8331 pci_unregister_driver(&s2io_driver);
8332 DBG_PRINT(INIT_DBG, "cleanup done\n");
8333}
8334
8335module_init(s2io_starter);
8336module_exit(s2io_closer);
7d3d0439 8337
6aa20a22 8338static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8339 struct tcphdr **tcp, struct RxD_t *rxdp,
8340 struct s2io_nic *sp)
7d3d0439
RA		 8341{
8342 int ip_off;
8343 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8344
8345 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8346 DBG_PRINT(INIT_DBG,
8347 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8348 __func__);
7d3d0439
RA		 8349 return -1;
8350 }
8351
cdb5bf02 8352 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8353 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8354 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8355 /*
8356 * If vlan stripping is disabled and the frame is VLAN tagged,
8357 * shift the offset by the VLAN header size bytes.
8358 */
cd0fce03 8359 if ((!sp->vlan_strip_flag) &&
d44570e4 8360 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8361 ip_off += HEADER_VLAN_SIZE;
8362 } else {
7d3d0439 8363 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8364 return -1;
7d3d0439
RA		 8365 }
8366
8367 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8368 ip_len = (u8)((*ip)->ihl);
8369 ip_len <<= 2;
8370 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8371
8372 return 0;
8373}
8374
1ee6dd77 8375static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8376 struct tcphdr *tcp)
8377{
d44570e4
JP		 8378 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8379 if ((lro->iph->saddr != ip->saddr) ||
8380 (lro->iph->daddr != ip->daddr) ||
8381 (lro->tcph->source != tcp->source) ||
8382 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8383 return -1;
8384 return 0;
8385}
8386
8387static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8388{
d44570e4 8389 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8390}
8391
1ee6dd77 8392static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8393 struct iphdr *ip, struct tcphdr *tcp,
8394 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8395{
d44570e4 8396 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8397 lro->l2h = l2h;
8398 lro->iph = ip;
8399 lro->tcph = tcp;
8400 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8401 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8402 lro->sg_num = 1;
8403 lro->total_len = ntohs(ip->tot_len);
8404 lro->frags_len = 0;
cdb5bf02 8405 lro->vlan_tag = vlan_tag;
6aa20a22 8406 /*
d44570e4
JP		 8407 * Check if we saw TCP timestamp.
8408 * Other consistency checks have already been done.
8409 */
7d3d0439 8410 if (tcp->doff == 8) {
c8855953
SR		 8411 __be32 *ptr;
8412 ptr = (__be32 *)(tcp+1);
7d3d0439 8413 lro->saw_ts = 1;
c8855953 8414 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8415 lro->cur_tsecr = *(ptr+2);
8416 }
8417 lro->in_use = 1;
8418}
8419
1ee6dd77 8420static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8421{
8422 struct iphdr *ip = lro->iph;
8423 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8424 __sum16 nchk;
ffb5df6c
JP		 8425 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8426
d44570e4 8427 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8428
8429 /* Update L3 header */
8430 ip->tot_len = htons(lro->total_len);
8431 ip->check = 0;
8432 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8433 ip->check = nchk;
8434
8435 /* Update L4 header */
8436 tcp->ack_seq = lro->tcp_ack;
8437 tcp->window = lro->window;
8438
8439 /* Update tsecr field if this session has timestamps enabled */
8440 if (lro->saw_ts) {
c8855953 8441 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8442 *(ptr+2) = lro->cur_tsecr;
8443 }
8444
8445 /* Update counters required for calculation of
8446 * average no. of packets aggregated.
8447 */
ffb5df6c
JP		 8448 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8449 swstats->num_aggregations++;
7d3d0439
RA		 8450}
8451
1ee6dd77 8452static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8453 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8454{
d44570e4 8455 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8456 lro->total_len += l4_pyld;
8457 lro->frags_len += l4_pyld;
8458 lro->tcp_next_seq += l4_pyld;
8459 lro->sg_num++;
8460
8461 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8462 lro->tcp_ack = tcp->ack_seq;
8463 lro->window = tcp->window;
6aa20a22 8464
7d3d0439 8465 if (lro->saw_ts) {
c8855953 8466 __be32 *ptr;
7d3d0439 8467 /* Update tsecr and tsval from this packet */
c8855953
SR		 8468 ptr = (__be32 *)(tcp+1);
8469 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8470 lro->cur_tsecr = *(ptr + 2);
8471 }
8472}
8473
1ee6dd77 8474static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8475 struct tcphdr *tcp, u32 tcp_pyld_len)
8476{
7d3d0439
RA		 8477 u8 *ptr;
8478
d44570e4 8479 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8480
7d3d0439
RA		 8481 if (!tcp_pyld_len) {
8482 /* Runt frame or a pure ack */
8483 return -1;
8484 }
8485
8486 if (ip->ihl != 5) /* IP has options */
8487 return -1;
8488
75c30b13
AR		 8489 /* If we see CE codepoint in IP header, packet is not mergeable */
8490 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8491 return -1;
8492
8493 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8494 if (tcp->urg || tcp->psh || tcp->rst ||
8495 tcp->syn || tcp->fin ||
8496 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8497 /*
8498 * Currently recognize only the ack control word and
8499 * any other control field being set would result in
8500 * flushing the LRO session
8501 */
8502 return -1;
8503 }
8504
6aa20a22 8505 /*
7d3d0439
RA		 8506 * Allow only one TCP timestamp option. Don't aggregate if
8507 * any other options are detected.
8508 */
8509 if (tcp->doff != 5 && tcp->doff != 8)
8510 return -1;
8511
8512 if (tcp->doff == 8) {
6aa20a22 8513 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8514 while (*ptr == TCPOPT_NOP)
8515 ptr++;
8516 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8517 return -1;
8518
8519 /* Ensure timestamp value increases monotonically */
8520 if (l_lro)
c8855953 8521 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8522 return -1;
8523
8524 /* timestamp echo reply should be non-zero */
c8855953 8525 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8526 return -1;
8527 }
8528
8529 return 0;
8530}
8531
d44570e4
JP		 8532static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8533 u8 **tcp, u32 *tcp_len, struct lro **lro,
8534 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8535{
8536 struct iphdr *ip;
8537 struct tcphdr *tcph;
8538 int ret = 0, i;
cdb5bf02 8539 u16 vlan_tag = 0;
ffb5df6c 8540 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439 8541
d44570e4
JP		 8542 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8543 rxdp, sp);
8544 if (ret)
7d3d0439 8545 return ret;
7d3d0439 8546
d44570e4
JP		 8547 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8548
cdb5bf02 8549 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8550 tcph = (struct tcphdr *)*tcp;
8551 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8552 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8553 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8554 if (l_lro->in_use) {
8555 if (check_for_socket_match(l_lro, ip, tcph))
8556 continue;
8557 /* Sock pair matched */
8558 *lro = l_lro;
8559
8560 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
9e39f7c5
JP		 8561 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8562 "expected 0x%x, actual 0x%x\n",
8563 __func__,
7d3d0439
RA		 8564 (*lro)->tcp_next_seq,
8565 ntohl(tcph->seq));
8566
ffb5df6c 8567 swstats->outof_sequence_pkts++;
7d3d0439
RA		 8568 ret = 2;
8569 break;
8570 }
8571
d44570e4
JP		 8572 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8573 *tcp_len))
7d3d0439
RA		 8574 ret = 1; /* Aggregate */
8575 else
8576 ret = 2; /* Flush both */
8577 break;
8578 }
8579 }
8580
8581 if (ret == 0) {
8582 /* Before searching for available LRO objects,
8583 * check if the pkt is L3/L4 aggregatable. If not
8584 * don't create new LRO session. Just send this
8585 * packet up.
8586 */
d44570e4 8587 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8588 return 5;
7d3d0439 8589
d44570e4 8590 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8591 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8592 if (!(l_lro->in_use)) {
8593 *lro = l_lro;
8594 ret = 3; /* Begin anew */
8595 break;
8596 }
8597 }
8598 }
8599
8600 if (ret == 0) { /* sessions exceeded */
9e39f7c5 8601 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
b39d66a8 8602 __func__);
7d3d0439
RA		 8603 *lro = NULL;
8604 return ret;
8605 }
8606
8607 switch (ret) {
d44570e4
JP		 8608 case 3:
8609 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8610 vlan_tag);
8611 break;
8612 case 2:
8613 update_L3L4_header(sp, *lro);
8614 break;
8615 case 1:
8616 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8617 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8618 update_L3L4_header(sp, *lro);
d44570e4
JP		 8619 ret = 4; /* Flush the LRO */
8620 }
8621 break;
8622 default:
9e39f7c5 8623 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
d44570e4 8624 break;
7d3d0439
RA		 8625 }
8626
8627 return ret;
8628}
8629
1ee6dd77 8630static void clear_lro_session(struct lro *lro)
7d3d0439 8631{
1ee6dd77 8632 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8633
8634 memset(lro, 0, lro_struct_size);
8635}
8636
cdb5bf02 8637static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8638{
8639 struct net_device *dev = skb->dev;
4cf1653a 8640 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8641
8642 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8643 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8644 /* Queueing the vlan frame to the upper layer */
8645 if (sp->config.napi)
8646 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8647 else
8648 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8649 } else {
8650 if (sp->config.napi)
8651 netif_receive_skb(skb);
8652 else
8653 netif_rx(skb);
8654 }
7d3d0439
RA		 8655}
8656
1ee6dd77 8657static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8658 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8659{
75c30b13 8660 struct sk_buff *first = lro->parent;
ffb5df6c 8661 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439
RA		 8662
8663 first->len += tcp_len;
8664 first->data_len = lro->frags_len;
8665 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8666 if (skb_shinfo(first)->frag_list)
8667 lro->last_frag->next = skb;
7d3d0439
RA		 8668 else
8669 skb_shinfo(first)->frag_list = skb;
372cc597 8670 first->truesize += skb->truesize;
75c30b13 8671 lro->last_frag = skb;
ffb5df6c 8672 swstats->clubbed_frms_cnt++;
7d3d0439 8673}
d796fdb7
LV		 8674
8675/**
8676 * s2io_io_error_detected - called when PCI error is detected
8677 * @pdev: Pointer to PCI device
8453d43f 8678 * @state: The current pci connection state
d796fdb7
LV		 8679 *
8680 * This function is called after a PCI bus error affecting
8681 * this device has been detected.
8682 */
8683static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8684 pci_channel_state_t state)
d796fdb7
LV		 8685{
8686 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8687 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8688
8689 netif_device_detach(netdev);
8690
1e3c8bd6
DN		 8691 if (state == pci_channel_io_perm_failure)
8692 return PCI_ERS_RESULT_DISCONNECT;
8693
d796fdb7
LV		 8694 if (netif_running(netdev)) {
8695 /* Bring down the card, while avoiding PCI I/O */
8696 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8697 }
8698 pci_disable_device(pdev);
8699
8700 return PCI_ERS_RESULT_NEED_RESET;
8701}
8702
8703/**
8704 * s2io_io_slot_reset - called after the pci bus has been reset.
8705 * @pdev: Pointer to PCI device
8706 *
8707 * Restart the card from scratch, as if from a cold-boot.
8708 * At this point, the card has exprienced a hard reset,
8709 * followed by fixups by BIOS, and has its config space
8710 * set up identically to what it was at cold boot.
8711 */
8712static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8713{
8714 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8715 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8716
8717 if (pci_enable_device(pdev)) {
6cef2b8e 8718 pr_err("Cannot re-enable PCI device after reset.\n");
d796fdb7
LV		 8719 return PCI_ERS_RESULT_DISCONNECT;
8720 }
8721
8722 pci_set_master(pdev);
8723 s2io_reset(sp);
8724
8725 return PCI_ERS_RESULT_RECOVERED;
8726}
8727
8728/**
8729 * s2io_io_resume - called when traffic can start flowing again.
8730 * @pdev: Pointer to PCI device
8731 *
8732 * This callback is called when the error recovery driver tells
8733 * us that its OK to resume normal operation.
8734 */
8735static void s2io_io_resume(struct pci_dev *pdev)
8736{
8737 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8738 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8739
8740 if (netif_running(netdev)) {
8741 if (s2io_card_up(sp)) {
6cef2b8e 8742 pr_err("Can't bring device back up after reset.\n");
d796fdb7
LV		 8743 return;
8744 }
8745
8746 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8747 s2io_card_down(sp);
6cef2b8e 8748 pr_err("Can't restore mac addr after reset.\n");
d796fdb7
LV		 8749 return;
8750 }
8751 }
8752
8753 netif_device_attach(netdev);
fd2ea0a7 8754 netif_tx_wake_all_queues(netdev);
d796fdb7 8755}
Linux kernel - Deliverables
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