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s2io.c: Convert skipped nic->config.tx_cfg[i]. to tx_cfg->
[deliverable/linux.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
d44570e4 4 *
1da177e4
LT		 5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4 27 * The module loadable parameters that are supported by the driver and a brief
a2a20aef 28 * explanation of all the variables.
9dc737a7 29 *
20346722 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
3a3d5756
SH		 53 * multiq: This parameter used to enable/disable MULTIQUEUE support.
54 * Possible values '1' for enable and '0' for disable. Default is '0'
1da177e4
LT		 55 ************************************************************************/
56
6cef2b8e
JP		 57#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58
1da177e4
LT		 59#include <linux/module.h>
60#include <linux/types.h>
61#include <linux/errno.h>
62#include <linux/ioport.h>
63#include <linux/pci.h>
1e7f0bd8 64#include <linux/dma-mapping.h>
1da177e4
LT		 65#include <linux/kernel.h>
66#include <linux/netdevice.h>
67#include <linux/etherdevice.h>
40239396 68#include <linux/mdio.h>
1da177e4
LT		 69#include <linux/skbuff.h>
70#include <linux/init.h>
71#include <linux/delay.h>
72#include <linux/stddef.h>
73#include <linux/ioctl.h>
74#include <linux/timex.h>
1da177e4 75#include <linux/ethtool.h>
1da177e4 76#include <linux/workqueue.h>
be3a6b02 77#include <linux/if_vlan.h>
7d3d0439
RA		 78#include <linux/ip.h>
79#include <linux/tcp.h>
d44570e4
JP		 80#include <linux/uaccess.h>
81#include <linux/io.h>
7d3d0439 82#include <net/tcp.h>
1da177e4 83
1da177e4 84#include <asm/system.h>
fe931395 85#include <asm/div64.h>
330ce0de 86#include <asm/irq.h>
1da177e4
LT		 87
88/* local include */
89#include "s2io.h"
90#include "s2io-regs.h"
91
29d0a2b0 92#define DRV_VERSION "2.0.26.25"
6c1792f4 93
1da177e4 94/* S2io Driver name & version. */
20346722 95static char s2io_driver_name[] = "Neterion";
6c1792f4 96static char s2io_driver_version[] = DRV_VERSION;
1da177e4 97
d44570e4
JP		 98static int rxd_size[2] = {32, 48};
99static int rxd_count[2] = {127, 85};
da6971d8 100
1ee6dd77 101static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd 102{
103 int ret;
104
105 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
d44570e4 106 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
5e25b9dd 107
108 return ret;
109}
110
20346722 111/*
1da177e4
LT		 112 * Cards with following subsystem_id have a link state indication
113 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
114 * macro below identifies these cards given the subsystem_id.
115 */
d44570e4
JP		 116#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
117 (dev_type == XFRAME_I_DEVICE) ? \
118 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
119 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 120
121#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
122 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
1da177e4 123
d44570e4 124static inline int is_s2io_card_up(const struct s2io_nic *sp)
92b84437
SS		 125{
126 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
127}
128
1da177e4 129/* Ethtool related variables and Macros. */
6fce365d 130static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
1da177e4
LT		 131 "Register test\t(offline)",
132 "Eeprom test\t(offline)",
133 "Link test\t(online)",
134 "RLDRAM test\t(offline)",
135 "BIST Test\t(offline)"
136};
137
6fce365d 138static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 139 {"tmac_frms"},
140 {"tmac_data_octets"},
141 {"tmac_drop_frms"},
142 {"tmac_mcst_frms"},
143 {"tmac_bcst_frms"},
144 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 145 {"tmac_ttl_octets"},
146 {"tmac_ucst_frms"},
147 {"tmac_nucst_frms"},
1da177e4 148 {"tmac_any_err_frms"},
bd1034f0 149 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 150 {"tmac_vld_ip_octets"},
151 {"tmac_vld_ip"},
152 {"tmac_drop_ip"},
153 {"tmac_icmp"},
154 {"tmac_rst_tcp"},
155 {"tmac_tcp"},
156 {"tmac_udp"},
157 {"rmac_vld_frms"},
158 {"rmac_data_octets"},
159 {"rmac_fcs_err_frms"},
160 {"rmac_drop_frms"},
161 {"rmac_vld_mcst_frms"},
162 {"rmac_vld_bcst_frms"},
163 {"rmac_in_rng_len_err_frms"},
bd1034f0 164 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 165 {"rmac_long_frms"},
166 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 167 {"rmac_unsup_ctrl_frms"},
168 {"rmac_ttl_octets"},
169 {"rmac_accepted_ucst_frms"},
170 {"rmac_accepted_nucst_frms"},
1da177e4 171 {"rmac_discarded_frms"},
bd1034f0
AR		 172 {"rmac_drop_events"},
173 {"rmac_ttl_less_fb_octets"},
174 {"rmac_ttl_frms"},
1da177e4
LT		 175 {"rmac_usized_frms"},
176 {"rmac_osized_frms"},
177 {"rmac_frag_frms"},
178 {"rmac_jabber_frms"},
bd1034f0
AR		 179 {"rmac_ttl_64_frms"},
180 {"rmac_ttl_65_127_frms"},
181 {"rmac_ttl_128_255_frms"},
182 {"rmac_ttl_256_511_frms"},
183 {"rmac_ttl_512_1023_frms"},
184 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 185 {"rmac_ip"},
186 {"rmac_ip_octets"},
187 {"rmac_hdr_err_ip"},
188 {"rmac_drop_ip"},
189 {"rmac_icmp"},
190 {"rmac_tcp"},
191 {"rmac_udp"},
192 {"rmac_err_drp_udp"},
bd1034f0
AR		 193 {"rmac_xgmii_err_sym"},
194 {"rmac_frms_q0"},
195 {"rmac_frms_q1"},
196 {"rmac_frms_q2"},
197 {"rmac_frms_q3"},
198 {"rmac_frms_q4"},
199 {"rmac_frms_q5"},
200 {"rmac_frms_q6"},
201 {"rmac_frms_q7"},
202 {"rmac_full_q0"},
203 {"rmac_full_q1"},
204 {"rmac_full_q2"},
205 {"rmac_full_q3"},
206 {"rmac_full_q4"},
207 {"rmac_full_q5"},
208 {"rmac_full_q6"},
209 {"rmac_full_q7"},
1da177e4 210 {"rmac_pause_cnt"},
bd1034f0
AR		 211 {"rmac_xgmii_data_err_cnt"},
212 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 213 {"rmac_accepted_ip"},
214 {"rmac_err_tcp"},
bd1034f0
AR		 215 {"rd_req_cnt"},
216 {"new_rd_req_cnt"},
217 {"new_rd_req_rtry_cnt"},
218 {"rd_rtry_cnt"},
219 {"wr_rtry_rd_ack_cnt"},
220 {"wr_req_cnt"},
221 {"new_wr_req_cnt"},
222 {"new_wr_req_rtry_cnt"},
223 {"wr_rtry_cnt"},
224 {"wr_disc_cnt"},
225 {"rd_rtry_wr_ack_cnt"},
226 {"txp_wr_cnt"},
227 {"txd_rd_cnt"},
228 {"txd_wr_cnt"},
229 {"rxd_rd_cnt"},
230 {"rxd_wr_cnt"},
231 {"txf_rd_cnt"},
fa1f0cb3
SS		 232 {"rxf_wr_cnt"}
233};
234
6fce365d 235static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 236 {"rmac_ttl_1519_4095_frms"},
237 {"rmac_ttl_4096_8191_frms"},
238 {"rmac_ttl_8192_max_frms"},
239 {"rmac_ttl_gt_max_frms"},
240 {"rmac_osized_alt_frms"},
241 {"rmac_jabber_alt_frms"},
242 {"rmac_gt_max_alt_frms"},
243 {"rmac_vlan_frms"},
244 {"rmac_len_discard"},
245 {"rmac_fcs_discard"},
246 {"rmac_pf_discard"},
247 {"rmac_da_discard"},
248 {"rmac_red_discard"},
249 {"rmac_rts_discard"},
250 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 251 {"link_fault_cnt"}
252};
253
6fce365d 254static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac 255 {"\n DRIVER STATISTICS"},
256 {"single_bit_ecc_errs"},
257 {"double_bit_ecc_errs"},
bd1034f0
AR		 258 {"parity_err_cnt"},
259 {"serious_err_cnt"},
260 {"soft_reset_cnt"},
261 {"fifo_full_cnt"},
8116f3cf
SS		 262 {"ring_0_full_cnt"},
263 {"ring_1_full_cnt"},
264 {"ring_2_full_cnt"},
265 {"ring_3_full_cnt"},
266 {"ring_4_full_cnt"},
267 {"ring_5_full_cnt"},
268 {"ring_6_full_cnt"},
269 {"ring_7_full_cnt"},
43b7c451
SH		 270 {"alarm_transceiver_temp_high"},
271 {"alarm_transceiver_temp_low"},
272 {"alarm_laser_bias_current_high"},
273 {"alarm_laser_bias_current_low"},
274 {"alarm_laser_output_power_high"},
275 {"alarm_laser_output_power_low"},
276 {"warn_transceiver_temp_high"},
277 {"warn_transceiver_temp_low"},
278 {"warn_laser_bias_current_high"},
279 {"warn_laser_bias_current_low"},
280 {"warn_laser_output_power_high"},
281 {"warn_laser_output_power_low"},
282 {"lro_aggregated_pkts"},
283 {"lro_flush_both_count"},
284 {"lro_out_of_sequence_pkts"},
285 {"lro_flush_due_to_max_pkts"},
286 {"lro_avg_aggr_pkts"},
287 {"mem_alloc_fail_cnt"},
288 {"pci_map_fail_cnt"},
289 {"watchdog_timer_cnt"},
290 {"mem_allocated"},
291 {"mem_freed"},
292 {"link_up_cnt"},
293 {"link_down_cnt"},
294 {"link_up_time"},
295 {"link_down_time"},
296 {"tx_tcode_buf_abort_cnt"},
297 {"tx_tcode_desc_abort_cnt"},
298 {"tx_tcode_parity_err_cnt"},
299 {"tx_tcode_link_loss_cnt"},
300 {"tx_tcode_list_proc_err_cnt"},
301 {"rx_tcode_parity_err_cnt"},
302 {"rx_tcode_abort_cnt"},
303 {"rx_tcode_parity_abort_cnt"},
304 {"rx_tcode_rda_fail_cnt"},
305 {"rx_tcode_unkn_prot_cnt"},
306 {"rx_tcode_fcs_err_cnt"},
307 {"rx_tcode_buf_size_err_cnt"},
308 {"rx_tcode_rxd_corrupt_cnt"},
309 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 310 {"tda_err_cnt"},
311 {"pfc_err_cnt"},
312 {"pcc_err_cnt"},
313 {"tti_err_cnt"},
314 {"tpa_err_cnt"},
315 {"sm_err_cnt"},
316 {"lso_err_cnt"},
317 {"mac_tmac_err_cnt"},
318 {"mac_rmac_err_cnt"},
319 {"xgxs_txgxs_err_cnt"},
320 {"xgxs_rxgxs_err_cnt"},
321 {"rc_err_cnt"},
322 {"prc_pcix_err_cnt"},
323 {"rpa_err_cnt"},
324 {"rda_err_cnt"},
325 {"rti_err_cnt"},
326 {"mc_err_cnt"}
1da177e4
LT		 327};
328
4c3616cd
AMR		 329#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
330#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
331#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3 332
d44570e4
JP		 333#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
334#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
fa1f0cb3 335
d44570e4
JP		 336#define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
337#define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
1da177e4 338
4c3616cd 339#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
d44570e4 340#define S2IO_STRINGS_LEN (S2IO_TEST_LEN * ETH_GSTRING_LEN)
1da177e4 341
d44570e4
JP		 342#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
343 init_timer(&timer); \
344 timer.function = handle; \
345 timer.data = (unsigned long)arg; \
346 mod_timer(&timer, (jiffies + exp)) \
25fff88e 347
2fd37688
SS		 348/* copy mac addr to def_mac_addr array */
349static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
350{
351 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
352 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
353 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
354 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
355 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
356 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
357}
04025095 358
be3a6b02 359/* Add the vlan */
360static void s2io_vlan_rx_register(struct net_device *dev,
04025095 361 struct vlan_group *grp)
be3a6b02 362{
2fda096d 363 int i;
4cf1653a 364 struct s2io_nic *nic = netdev_priv(dev);
2fda096d 365 unsigned long flags[MAX_TX_FIFOS];
2fda096d 366 struct config_param *config = &nic->config;
ffb5df6c 367 struct mac_info *mac_control = &nic->mac_control;
2fda096d 368
13d866a9
JP		 369 for (i = 0; i < config->tx_fifo_num; i++) {
370 struct fifo_info *fifo = &mac_control->fifos[i];
371
372 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
373 }
be3a6b02 374
be3a6b02 375 nic->vlgrp = grp;
13d866a9
JP		 376
377 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
378 struct fifo_info *fifo = &mac_control->fifos[i];
379
380 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
381 }
be3a6b02 382}
383
cdb5bf02 384/* Unregister the vlan */
04025095 385static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
cdb5bf02
SH		 386{
387 int i;
4cf1653a 388 struct s2io_nic *nic = netdev_priv(dev);
cdb5bf02 389 unsigned long flags[MAX_TX_FIFOS];
cdb5bf02 390 struct config_param *config = &nic->config;
ffb5df6c 391 struct mac_info *mac_control = &nic->mac_control;
cdb5bf02 392
13d866a9
JP		 393 for (i = 0; i < config->tx_fifo_num; i++) {
394 struct fifo_info *fifo = &mac_control->fifos[i];
395
396 spin_lock_irqsave(&fifo->tx_lock, flags[i]);
397 }
cdb5bf02
SH		 398
399 if (nic->vlgrp)
400 vlan_group_set_device(nic->vlgrp, vid, NULL);
401
13d866a9
JP		 402 for (i = config->tx_fifo_num - 1; i >= 0; i--) {
403 struct fifo_info *fifo = &mac_control->fifos[i];
404
405 spin_unlock_irqrestore(&fifo->tx_lock, flags[i]);
406 }
cdb5bf02
SH		 407}
408
20346722 409/*
1da177e4
LT		 410 * Constants to be programmed into the Xena's registers, to configure
411 * the XAUI.
412 */
413
1da177e4 414#define END_SIGN 0x0
f71e1309 415static const u64 herc_act_dtx_cfg[] = {
541ae68f 416 /* Set address */
e960fc5c 417 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 418 /* Write data */
e960fc5c 419 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f 420 /* Set address */
421 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
422 /* Write data */
423 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
424 /* Set address */
e960fc5c 425 0x801205150D440000ULL, 0x801205150D4400E0ULL,
426 /* Write data */
427 0x801205150D440004ULL, 0x801205150D4400E4ULL,
428 /* Set address */
541ae68f 429 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
430 /* Write data */
431 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
432 /* Done */
433 END_SIGN
434};
435
f71e1309 436static const u64 xena_dtx_cfg[] = {
c92ca04b 437 /* Set address */
1da177e4 438 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 439 /* Write data */
440 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
441 /* Set address */
442 0x8001051500000000ULL, 0x80010515000000E0ULL,
443 /* Write data */
444 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
445 /* Set address */
1da177e4 446 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 447 /* Write data */
448 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 449 END_SIGN
450};
451
20346722 452/*
1da177e4
LT		 453 * Constants for Fixing the MacAddress problem seen mostly on
454 * Alpha machines.
455 */
f71e1309 456static const u64 fix_mac[] = {
1da177e4
LT		 457 0x0060000000000000ULL, 0x0060600000000000ULL,
458 0x0040600000000000ULL, 0x0000600000000000ULL,
459 0x0020600000000000ULL, 0x0060600000000000ULL,
460 0x0020600000000000ULL, 0x0060600000000000ULL,
461 0x0020600000000000ULL, 0x0060600000000000ULL,
462 0x0020600000000000ULL, 0x0060600000000000ULL,
463 0x0020600000000000ULL, 0x0060600000000000ULL,
464 0x0020600000000000ULL, 0x0060600000000000ULL,
465 0x0020600000000000ULL, 0x0060600000000000ULL,
466 0x0020600000000000ULL, 0x0060600000000000ULL,
467 0x0020600000000000ULL, 0x0060600000000000ULL,
468 0x0020600000000000ULL, 0x0060600000000000ULL,
469 0x0020600000000000ULL, 0x0000600000000000ULL,
470 0x0040600000000000ULL, 0x0060600000000000ULL,
471 END_SIGN
472};
473
b41477f3
AR		 474MODULE_LICENSE("GPL");
475MODULE_VERSION(DRV_VERSION);
476
477
1da177e4 478/* Module Loadable parameters. */
6cfc482b 479S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
b41477f3 480S2IO_PARM_INT(rx_ring_num, 1);
3a3d5756 481S2IO_PARM_INT(multiq, 0);
b41477f3
AR		 482S2IO_PARM_INT(rx_ring_mode, 1);
483S2IO_PARM_INT(use_continuous_tx_intrs, 1);
484S2IO_PARM_INT(rmac_pause_time, 0x100);
485S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
486S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
487S2IO_PARM_INT(shared_splits, 0);
488S2IO_PARM_INT(tmac_util_period, 5);
489S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 490S2IO_PARM_INT(l3l4hdr_size, 128);
6cfc482b
SH		 491/* 0 is no steering, 1 is Priority steering, 2 is Default steering */
492S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
303bcb4b 493/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 494S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 495/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 496S2IO_PARM_INT(intr_type, 2);
7d3d0439 497/* Large receive offload feature */
43b7c451
SH		 498static unsigned int lro_enable;
499module_param_named(lro, lro_enable, uint, 0);
500
7d3d0439
RA		 501/* Max pkts to be aggregated by LRO at one time. If not specified,
502 * aggregation happens until we hit max IP pkt size(64K)
503 */
b41477f3 504S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 505S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 506
507S2IO_PARM_INT(napi, 1);
508S2IO_PARM_INT(ufo, 0);
926930b2 509S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 510
511static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
d44570e4 512{DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
b41477f3 513static unsigned int rx_ring_sz[MAX_RX_RINGS] =
d44570e4 514{[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
b41477f3 515static unsigned int rts_frm_len[MAX_RX_RINGS] =
d44570e4 516{[0 ...(MAX_RX_RINGS - 1)] = 0 };
b41477f3
AR		 517
518module_param_array(tx_fifo_len, uint, NULL, 0);
519module_param_array(rx_ring_sz, uint, NULL, 0);
520module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 521
20346722 522/*
1da177e4 523 * S2IO device table.
20346722 524 * This table lists all the devices that this driver supports.
1da177e4
LT		 525 */
526static struct pci_device_id s2io_tbl[] __devinitdata = {
527 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
528 PCI_ANY_ID, PCI_ANY_ID},
529 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
530 PCI_ANY_ID, PCI_ANY_ID},
531 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
d44570e4
JP		 532 PCI_ANY_ID, PCI_ANY_ID},
533 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
534 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 535 {0,}
536};
537
538MODULE_DEVICE_TABLE(pci, s2io_tbl);
539
d796fdb7
LV		 540static struct pci_error_handlers s2io_err_handler = {
541 .error_detected = s2io_io_error_detected,
542 .slot_reset = s2io_io_slot_reset,
543 .resume = s2io_io_resume,
544};
545
1da177e4 546static struct pci_driver s2io_driver = {
d44570e4
JP		 547 .name = "S2IO",
548 .id_table = s2io_tbl,
549 .probe = s2io_init_nic,
550 .remove = __devexit_p(s2io_rem_nic),
551 .err_handler = &s2io_err_handler,
1da177e4
LT		 552};
553
554/* A simplifier macro used both by init and free shared_mem Fns(). */
555#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
556
3a3d5756
SH		 557/* netqueue manipulation helper functions */
558static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
559{
fd2ea0a7
DM		 560 if (!sp->config.multiq) {
561 int i;
562
3a3d5756
SH		 563 for (i = 0; i < sp->config.tx_fifo_num; i++)
564 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
3a3d5756 565 }
fd2ea0a7 566 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 567}
568
569static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
570{
fd2ea0a7 571 if (!sp->config.multiq)
3a3d5756
SH		 572 sp->mac_control.fifos[fifo_no].queue_state =
573 FIFO_QUEUE_STOP;
fd2ea0a7
DM		 574
575 netif_tx_stop_all_queues(sp->dev);
3a3d5756
SH		 576}
577
578static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
579{
fd2ea0a7
DM		 580 if (!sp->config.multiq) {
581 int i;
582
3a3d5756
SH		 583 for (i = 0; i < sp->config.tx_fifo_num; i++)
584 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 585 }
fd2ea0a7 586 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 587}
588
589static inline void s2io_start_tx_queue(struct s2io_nic *sp, int fifo_no)
590{
fd2ea0a7 591 if (!sp->config.multiq)
3a3d5756
SH		 592 sp->mac_control.fifos[fifo_no].queue_state =
593 FIFO_QUEUE_START;
fd2ea0a7
DM		 594
595 netif_tx_start_all_queues(sp->dev);
3a3d5756
SH		 596}
597
598static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
599{
fd2ea0a7
DM		 600 if (!sp->config.multiq) {
601 int i;
602
3a3d5756
SH		 603 for (i = 0; i < sp->config.tx_fifo_num; i++)
604 sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
3a3d5756 605 }
fd2ea0a7 606 netif_tx_wake_all_queues(sp->dev);
3a3d5756
SH		 607}
608
609static inline void s2io_wake_tx_queue(
610 struct fifo_info *fifo, int cnt, u8 multiq)
611{
612
3a3d5756
SH		 613 if (multiq) {
614 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
615 netif_wake_subqueue(fifo->dev, fifo->fifo_no);
b19fa1fa 616 } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 617 if (netif_queue_stopped(fifo->dev)) {
618 fifo->queue_state = FIFO_QUEUE_START;
619 netif_wake_queue(fifo->dev);
620 }
621 }
622}
623
1da177e4
LT		 624/**
625 * init_shared_mem - Allocation and Initialization of Memory
626 * @nic: Device private variable.
20346722 627 * Description: The function allocates all the memory areas shared
628 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 629 * Rx descriptors and the statistics block.
630 */
631
632static int init_shared_mem(struct s2io_nic *nic)
633{
634 u32 size;
635 void *tmp_v_addr, *tmp_v_addr_next;
636 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 637 struct RxD_block *pre_rxd_blk = NULL;
372cc597 638 int i, j, blk_cnt;
1da177e4
LT		 639 int lst_size, lst_per_page;
640 struct net_device *dev = nic->dev;
8ae418cf 641 unsigned long tmp;
1ee6dd77 642 struct buffAdd *ba;
ffb5df6c
JP		 643 struct config_param *config = &nic->config;
644 struct mac_info *mac_control = &nic->mac_control;
491976b2 645 unsigned long long mem_allocated = 0;
1da177e4 646
13d866a9 647 /* Allocation and initialization of TXDLs in FIFOs */
1da177e4
LT		 648 size = 0;
649 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 650 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
651
652 size += tx_cfg->fifo_len;
1da177e4
LT		 653 }
654 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 655 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
d44570e4
JP		 656 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n",
657 size);
b41477f3 658 return -EINVAL;
1da177e4
LT		 659 }
660
2fda096d
SR		 661 size = 0;
662 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 663 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
664
665 size = tx_cfg->fifo_len;
2fda096d
SR		 666 /*
667 * Legal values are from 2 to 8192
668 */
669 if (size < 2) {
670 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
671 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
672 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
d44570e4 673 "are 2 to 8192\n");
2fda096d
SR		 674 return -EINVAL;
675 }
676 }
677
1ee6dd77 678 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 679 lst_per_page = PAGE_SIZE / lst_size;
680
681 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 682 struct fifo_info *fifo = &mac_control->fifos[i];
683 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 int fifo_len = tx_cfg->fifo_len;
1ee6dd77 685 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
13d866a9
JP		 686
687 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
688 if (!fifo->list_info) {
d44570e4 689 DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
1da177e4
LT		 690 return -ENOMEM;
691 }
491976b2 692 mem_allocated += list_holder_size;
1da177e4
LT		 693 }
694 for (i = 0; i < config->tx_fifo_num; i++) {
695 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
696 lst_per_page);
13d866a9
JP		 697 struct fifo_info *fifo = &mac_control->fifos[i];
698 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
699
700 fifo->tx_curr_put_info.offset = 0;
701 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
702 fifo->tx_curr_get_info.offset = 0;
703 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
704 fifo->fifo_no = i;
705 fifo->nic = nic;
706 fifo->max_txds = MAX_SKB_FRAGS + 2;
707 fifo->dev = dev;
20346722 708
1da177e4
LT		 709 for (j = 0; j < page_num; j++) {
710 int k = 0;
711 dma_addr_t tmp_p;
712 void *tmp_v;
713 tmp_v = pci_alloc_consistent(nic->pdev,
714 PAGE_SIZE, &tmp_p);
715 if (!tmp_v) {
d44570e4 716 DBG_PRINT(INFO_DBG, "pci_alloc_consistent ");
0c61ed5f 717 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 718 return -ENOMEM;
719 }
776bd20f 720 /* If we got a zero DMA address(can happen on
721 * certain platforms like PPC), reallocate.
722 * Store virtual address of page we don't want,
723 * to be freed later.
724 */
725 if (!tmp_p) {
726 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 727 DBG_PRINT(INIT_DBG,
d44570e4
JP		 728 "%s: Zero DMA address for TxDL. ",
729 dev->name);
6aa20a22 730 DBG_PRINT(INIT_DBG,
d44570e4 731 "Virtual address %p\n", tmp_v);
776bd20f 732 tmp_v = pci_alloc_consistent(nic->pdev,
d44570e4 733 PAGE_SIZE, &tmp_p);
776bd20f 734 if (!tmp_v) {
0c61ed5f 735 DBG_PRINT(INFO_DBG,
d44570e4
JP		 736 "pci_alloc_consistent ");
737 DBG_PRINT(INFO_DBG,
738 "failed for TxDL\n");
776bd20f 739 return -ENOMEM;
740 }
491976b2 741 mem_allocated += PAGE_SIZE;
776bd20f 742 }
1da177e4
LT		 743 while (k < lst_per_page) {
744 int l = (j * lst_per_page) + k;
13d866a9 745 if (l == tx_cfg->fifo_len)
20346722 746 break;
13d866a9 747 fifo->list_info[l].list_virt_addr =
d44570e4 748 tmp_v + (k * lst_size);
13d866a9 749 fifo->list_info[l].list_phy_addr =
d44570e4 750 tmp_p + (k * lst_size);
1da177e4
LT		 751 k++;
752 }
753 }
754 }
1da177e4 755
2fda096d 756 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 757 struct fifo_info *fifo = &mac_control->fifos[i];
758 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
759
760 size = tx_cfg->fifo_len;
761 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
762 if (!fifo->ufo_in_band_v)
2fda096d
SR		 763 return -ENOMEM;
764 mem_allocated += (size * sizeof(u64));
765 }
fed5eccd 766
1da177e4
LT		 767 /* Allocation and initialization of RXDs in Rings */
768 size = 0;
769 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 770 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
771 struct ring_info *ring = &mac_control->rings[i];
772
773 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
1da177e4 774 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
13d866a9 775 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ", i);
1da177e4
LT		 776 DBG_PRINT(ERR_DBG, "RxDs per Block");
777 return FAILURE;
778 }
13d866a9
JP		 779 size += rx_cfg->num_rxd;
780 ring->block_count = rx_cfg->num_rxd /
d44570e4 781 (rxd_count[nic->rxd_mode] + 1);
13d866a9 782 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
1da177e4 783 }
da6971d8 784 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 785 size = (size * (sizeof(struct RxD1)));
da6971d8 786 else
1ee6dd77 787 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 788
789 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 790 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
791 struct ring_info *ring = &mac_control->rings[i];
792
793 ring->rx_curr_get_info.block_index = 0;
794 ring->rx_curr_get_info.offset = 0;
795 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
796 ring->rx_curr_put_info.block_index = 0;
797 ring->rx_curr_put_info.offset = 0;
798 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
799 ring->nic = nic;
800 ring->ring_no = i;
801 ring->lro = lro_enable;
802
803 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 804 /* Allocating all the Rx blocks */
805 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 806 struct rx_block_info *rx_blocks;
da6971d8
AR		 807 int l;
808
13d866a9 809 rx_blocks = &ring->rx_blocks[j];
d44570e4 810 size = SIZE_OF_BLOCK; /* size is always page size */
1da177e4
LT		 811 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
812 &tmp_p_addr);
813 if (tmp_v_addr == NULL) {
814 /*
20346722 815 * In case of failure, free_shared_mem()
816 * is called, which should free any
817 * memory that was alloced till the
1da177e4
LT		 818 * failure happened.
819 */
da6971d8 820 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 821 return -ENOMEM;
822 }
491976b2 823 mem_allocated += size;
1da177e4 824 memset(tmp_v_addr, 0, size);
4f870320
JP		 825
826 size = sizeof(struct rxd_info) *
827 rxd_count[nic->rxd_mode];
da6971d8
AR		 828 rx_blocks->block_virt_addr = tmp_v_addr;
829 rx_blocks->block_dma_addr = tmp_p_addr;
4f870320 830 rx_blocks->rxds = kmalloc(size, GFP_KERNEL);
372cc597
SS		 831 if (!rx_blocks->rxds)
832 return -ENOMEM;
4f870320 833 mem_allocated += size;
d44570e4 834 for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
da6971d8
AR		 835 rx_blocks->rxds[l].virt_addr =
836 rx_blocks->block_virt_addr +
837 (rxd_size[nic->rxd_mode] * l);
838 rx_blocks->rxds[l].dma_addr =
839 rx_blocks->block_dma_addr +
840 (rxd_size[nic->rxd_mode] * l);
841 }
1da177e4
LT		 842 }
843 /* Interlinking all Rx Blocks */
844 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 845 int next = (j + 1) % blk_cnt;
846 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
847 tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
848 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
849 tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
1da177e4 850
d44570e4 851 pre_rxd_blk = (struct RxD_block *)tmp_v_addr;
1da177e4 852 pre_rxd_blk->reserved_2_pNext_RxD_block =
d44570e4 853 (unsigned long)tmp_v_addr_next;
1da177e4 854 pre_rxd_blk->pNext_RxD_Blk_physical =
d44570e4 855 (u64)tmp_p_addr_next;
1da177e4
LT		 856 }
857 }
6d517a27 858 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 859 /*
860 * Allocation of Storages for buffer addresses in 2BUFF mode
861 * and the buffers as well.
862 */
863 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 864 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
865 struct ring_info *ring = &mac_control->rings[i];
866
867 blk_cnt = rx_cfg->num_rxd /
d44570e4 868 (rxd_count[nic->rxd_mode] + 1);
4f870320
JP		 869 size = sizeof(struct buffAdd *) * blk_cnt;
870 ring->ba = kmalloc(size, GFP_KERNEL);
13d866a9 871 if (!ring->ba)
1da177e4 872 return -ENOMEM;
4f870320 873 mem_allocated += size;
da6971d8
AR		 874 for (j = 0; j < blk_cnt; j++) {
875 int k = 0;
4f870320
JP		 876
877 size = sizeof(struct buffAdd) *
878 (rxd_count[nic->rxd_mode] + 1);
879 ring->ba[j] = kmalloc(size, GFP_KERNEL);
13d866a9 880 if (!ring->ba[j])
1da177e4 881 return -ENOMEM;
4f870320 882 mem_allocated += size;
da6971d8 883 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 884 ba = &ring->ba[j][k];
4f870320
JP		 885 size = BUF0_LEN + ALIGN_SIZE;
886 ba->ba_0_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 887 if (!ba->ba_0_org)
888 return -ENOMEM;
4f870320 889 mem_allocated += size;
da6971d8
AR		 890 tmp = (unsigned long)ba->ba_0_org;
891 tmp += ALIGN_SIZE;
d44570e4
JP		 892 tmp &= ~((unsigned long)ALIGN_SIZE);
893 ba->ba_0 = (void *)tmp;
da6971d8 894
4f870320
JP		 895 size = BUF1_LEN + ALIGN_SIZE;
896 ba->ba_1_org = kmalloc(size, GFP_KERNEL);
da6971d8
AR		 897 if (!ba->ba_1_org)
898 return -ENOMEM;
4f870320 899 mem_allocated += size;
d44570e4 900 tmp = (unsigned long)ba->ba_1_org;
da6971d8 901 tmp += ALIGN_SIZE;
d44570e4
JP		 902 tmp &= ~((unsigned long)ALIGN_SIZE);
903 ba->ba_1 = (void *)tmp;
da6971d8
AR		 904 k++;
905 }
1da177e4
LT		 906 }
907 }
908 }
1da177e4
LT		 909
910 /* Allocation and initialization of Statistics block */
1ee6dd77 911 size = sizeof(struct stat_block);
d44570e4
JP		 912 mac_control->stats_mem =
913 pci_alloc_consistent(nic->pdev, size,
914 &mac_control->stats_mem_phy);
1da177e4
LT		 915
916 if (!mac_control->stats_mem) {
20346722 917 /*
918 * In case of failure, free_shared_mem() is called, which
919 * should free any memory that was alloced till the
1da177e4
LT		 920 * failure happened.
921 */
922 return -ENOMEM;
923 }
491976b2 924 mem_allocated += size;
1da177e4
LT		 925 mac_control->stats_mem_sz = size;
926
927 tmp_v_addr = mac_control->stats_mem;
d44570e4 928 mac_control->stats_info = (struct stat_block *)tmp_v_addr;
1da177e4 929 memset(tmp_v_addr, 0, size);
1da177e4 930 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
d44570e4 931 (unsigned long long)tmp_p_addr);
491976b2 932 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 933 return SUCCESS;
934}
935
20346722 936/**
937 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 938 * @nic: Device private variable.
939 * Description: This function is to free all memory locations allocated by
940 * the init_shared_mem() function and return it to the kernel.
941 */
942
943static void free_shared_mem(struct s2io_nic *nic)
944{
945 int i, j, blk_cnt, size;
946 void *tmp_v_addr;
947 dma_addr_t tmp_p_addr;
1da177e4 948 int lst_size, lst_per_page;
8910b49f 949 struct net_device *dev;
491976b2 950 int page_num = 0;
ffb5df6c
JP		 951 struct config_param *config;
952 struct mac_info *mac_control;
953 struct stat_block *stats;
954 struct swStat *swstats;
1da177e4
LT		 955
956 if (!nic)
957 return;
958
8910b49f
MG		 959 dev = nic->dev;
960
1da177e4 961 config = &nic->config;
ffb5df6c
JP		 962 mac_control = &nic->mac_control;
963 stats = mac_control->stats_info;
964 swstats = &stats->sw_stat;
1da177e4 965
d44570e4 966 lst_size = sizeof(struct TxD) * config->max_txds;
1da177e4
LT		 967 lst_per_page = PAGE_SIZE / lst_size;
968
969 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 970 struct fifo_info *fifo = &mac_control->fifos[i];
971 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
972
973 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
1da177e4
LT		 974 for (j = 0; j < page_num; j++) {
975 int mem_blks = (j * lst_per_page);
13d866a9
JP		 976 struct list_info_hold *fli;
977
978 if (!fifo->list_info)
6aa20a22 979 return;
13d866a9
JP		 980
981 fli = &fifo->list_info[mem_blks];
982 if (!fli->list_virt_addr)
1da177e4
LT		 983 break;
984 pci_free_consistent(nic->pdev, PAGE_SIZE,
13d866a9
JP		 985 fli->list_virt_addr,
986 fli->list_phy_addr);
ffb5df6c 987 swstats->mem_freed += PAGE_SIZE;
1da177e4 988 }
776bd20f 989 /* If we got a zero DMA address during allocation,
990 * free the page now
991 */
992 if (mac_control->zerodma_virt_addr) {
993 pci_free_consistent(nic->pdev, PAGE_SIZE,
994 mac_control->zerodma_virt_addr,
995 (dma_addr_t)0);
6aa20a22 996 DBG_PRINT(INIT_DBG,
d44570e4
JP		 997 "%s: Freeing TxDL with zero DMA addr. ",
998 dev->name);
6b4d617d 999 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
d44570e4 1000 mac_control->zerodma_virt_addr);
ffb5df6c 1001 swstats->mem_freed += PAGE_SIZE;
776bd20f 1002 }
13d866a9 1003 kfree(fifo->list_info);
82c2d023 1004 swstats->mem_freed += tx_cfg->fifo_len *
d44570e4 1005 sizeof(struct list_info_hold);
1da177e4
LT		 1006 }
1007
1da177e4 1008 size = SIZE_OF_BLOCK;
1da177e4 1009 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1010 struct ring_info *ring = &mac_control->rings[i];
1011
1012 blk_cnt = ring->block_count;
1da177e4 1013 for (j = 0; j < blk_cnt; j++) {
13d866a9
JP		 1014 tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
1015 tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
1da177e4
LT		 1016 if (tmp_v_addr == NULL)
1017 break;
1018 pci_free_consistent(nic->pdev, size,
1019 tmp_v_addr, tmp_p_addr);
ffb5df6c 1020 swstats->mem_freed += size;
13d866a9 1021 kfree(ring->rx_blocks[j].rxds);
ffb5df6c
JP		 1022 swstats->mem_freed += sizeof(struct rxd_info) *
1023 rxd_count[nic->rxd_mode];
1da177e4
LT		 1024 }
1025 }
1026
6d517a27 1027 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 1028 /* Freeing buffer storage addresses in 2BUFF mode. */
1029 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1030 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1031 struct ring_info *ring = &mac_control->rings[i];
1032
1033 blk_cnt = rx_cfg->num_rxd /
1034 (rxd_count[nic->rxd_mode] + 1);
da6971d8
AR		 1035 for (j = 0; j < blk_cnt; j++) {
1036 int k = 0;
13d866a9 1037 if (!ring->ba[j])
da6971d8
AR		 1038 continue;
1039 while (k != rxd_count[nic->rxd_mode]) {
13d866a9 1040 struct buffAdd *ba = &ring->ba[j][k];
da6971d8 1041 kfree(ba->ba_0_org);
ffb5df6c
JP		 1042 swstats->mem_freed +=
1043 BUF0_LEN + ALIGN_SIZE;
da6971d8 1044 kfree(ba->ba_1_org);
ffb5df6c
JP		 1045 swstats->mem_freed +=
1046 BUF1_LEN + ALIGN_SIZE;
da6971d8
AR		 1047 k++;
1048 }
13d866a9 1049 kfree(ring->ba[j]);
ffb5df6c
JP		 1050 swstats->mem_freed += sizeof(struct buffAdd) *
1051 (rxd_count[nic->rxd_mode] + 1);
1da177e4 1052 }
13d866a9 1053 kfree(ring->ba);
ffb5df6c
JP		 1054 swstats->mem_freed += sizeof(struct buffAdd *) *
1055 blk_cnt;
1da177e4 1056 }
1da177e4 1057 }
1da177e4 1058
2fda096d 1059 for (i = 0; i < nic->config.tx_fifo_num; i++) {
13d866a9
JP		 1060 struct fifo_info *fifo = &mac_control->fifos[i];
1061 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1062
1063 if (fifo->ufo_in_band_v) {
ffb5df6c
JP		 1064 swstats->mem_freed += tx_cfg->fifo_len *
1065 sizeof(u64);
13d866a9 1066 kfree(fifo->ufo_in_band_v);
2fda096d
SR		 1067 }
1068 }
1069
1da177e4 1070 if (mac_control->stats_mem) {
ffb5df6c 1071 swstats->mem_freed += mac_control->stats_mem_sz;
1da177e4
LT		 1072 pci_free_consistent(nic->pdev,
1073 mac_control->stats_mem_sz,
1074 mac_control->stats_mem,
1075 mac_control->stats_mem_phy);
491976b2 1076 }
1da177e4
LT		 1077}
1078
541ae68f 1079/**
1080 * s2io_verify_pci_mode -
1081 */
1082
1ee6dd77 1083static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 1084{
1ee6dd77 1085 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1086 register u64 val64 = 0;
1087 int mode;
1088
1089 val64 = readq(&bar0->pci_mode);
1090 mode = (u8)GET_PCI_MODE(val64);
1091
d44570e4 1092 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f 1093 return -1; /* Unknown PCI mode */
1094 return mode;
1095}
1096
c92ca04b
AR		 1097#define NEC_VENID 0x1033
1098#define NEC_DEVID 0x0125
1099static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1100{
1101 struct pci_dev *tdev = NULL;
26d36b64
AC		 1102 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1103 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
7ad62dbc 1104 if (tdev->bus == s2io_pdev->bus->parent) {
26d36b64 1105 pci_dev_put(tdev);
c92ca04b 1106 return 1;
7ad62dbc 1107 }
c92ca04b
AR		 1108 }
1109 }
1110 return 0;
1111}
541ae68f 1112
7b32a312 1113static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f 1114/**
1115 * s2io_print_pci_mode -
1116 */
1ee6dd77 1117static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1118{
1ee6dd77 1119 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f 1120 register u64 val64 = 0;
1121 int mode;
1122 struct config_param *config = &nic->config;
1123
1124 val64 = readq(&bar0->pci_mode);
1125 mode = (u8)GET_PCI_MODE(val64);
1126
d44570e4 1127 if (val64 & PCI_MODE_UNKNOWN_MODE)
541ae68f 1128 return -1; /* Unknown PCI mode */
1129
c92ca04b
AR		 1130 config->bus_speed = bus_speed[mode];
1131
1132 if (s2io_on_nec_bridge(nic->pdev)) {
1133 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
d44570e4 1134 nic->dev->name);
c92ca04b
AR		 1135 return mode;
1136 }
1137
d44570e4
JP		 1138 DBG_PRINT(ERR_DBG, "%s: Device is on %d bit ",
1139 nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64);
541ae68f 1140
d44570e4
JP		 1141 switch (mode) {
1142 case PCI_MODE_PCI_33:
1143 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
1144 break;
1145 case PCI_MODE_PCI_66:
1146 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
1147 break;
1148 case PCI_MODE_PCIX_M1_66:
1149 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
1150 break;
1151 case PCI_MODE_PCIX_M1_100:
1152 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
1153 break;
1154 case PCI_MODE_PCIX_M1_133:
1155 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
1156 break;
1157 case PCI_MODE_PCIX_M2_66:
1158 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
1159 break;
1160 case PCI_MODE_PCIX_M2_100:
1161 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
1162 break;
1163 case PCI_MODE_PCIX_M2_133:
1164 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
1165 break;
1166 default:
1167 return -1; /* Unsupported bus speed */
541ae68f 1168 }
1169
1170 return mode;
1171}
1172
b7c5678f
RV		 1173/**
1174 * init_tti - Initialization transmit traffic interrupt scheme
1175 * @nic: device private variable
1176 * @link: link status (UP/DOWN) used to enable/disable continuous
1177 * transmit interrupts
1178 * Description: The function configures transmit traffic interrupts
1179 * Return Value: SUCCESS on success and
1180 * '-1' on failure
1181 */
1182
0d66afe7 1183static int init_tti(struct s2io_nic *nic, int link)
b7c5678f
RV		 1184{
1185 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1186 register u64 val64 = 0;
1187 int i;
ffb5df6c 1188 struct config_param *config = &nic->config;
b7c5678f
RV		 1189
1190 for (i = 0; i < config->tx_fifo_num; i++) {
1191 /*
1192 * TTI Initialization. Default Tx timer gets us about
1193 * 250 interrupts per sec. Continuous interrupts are enabled
1194 * by default.
1195 */
1196 if (nic->device_type == XFRAME_II_DEVICE) {
1197 int count = (nic->config.bus_speed * 125)/2;
1198 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1199 } else
1200 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1201
1202 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
d44570e4
JP		 1203 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1204 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1205 TTI_DATA1_MEM_TX_TIMER_AC_EN;
ac731ab6
SH		 1206 if (i == 0)
1207 if (use_continuous_tx_intrs && (link == LINK_UP))
1208 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
b7c5678f
RV		 1209 writeq(val64, &bar0->tti_data1_mem);
1210
ac731ab6
SH		 1211 if (nic->config.intr_type == MSI_X) {
1212 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1213 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1214 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1215 TTI_DATA2_MEM_TX_UFC_D(0x300);
1216 } else {
1217 if ((nic->config.tx_steering_type ==
d44570e4
JP		 1218 TX_DEFAULT_STEERING) &&
1219 (config->tx_fifo_num > 1) &&
1220 (i >= nic->udp_fifo_idx) &&
1221 (i < (nic->udp_fifo_idx +
1222 nic->total_udp_fifos)))
ac731ab6
SH		 1223 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1224 TTI_DATA2_MEM_TX_UFC_B(0x80) |
1225 TTI_DATA2_MEM_TX_UFC_C(0x100) |
1226 TTI_DATA2_MEM_TX_UFC_D(0x120);
1227 else
1228 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1229 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1230 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1231 TTI_DATA2_MEM_TX_UFC_D(0x80);
1232 }
b7c5678f
RV		 1233
1234 writeq(val64, &bar0->tti_data2_mem);
1235
d44570e4
JP		 1236 val64 = TTI_CMD_MEM_WE |
1237 TTI_CMD_MEM_STROBE_NEW_CMD |
1238 TTI_CMD_MEM_OFFSET(i);
b7c5678f
RV		 1239 writeq(val64, &bar0->tti_command_mem);
1240
1241 if (wait_for_cmd_complete(&bar0->tti_command_mem,
d44570e4
JP		 1242 TTI_CMD_MEM_STROBE_NEW_CMD,
1243 S2IO_BIT_RESET) != SUCCESS)
b7c5678f
RV		 1244 return FAILURE;
1245 }
1246
1247 return SUCCESS;
1248}
1249
20346722 1250/**
1251 * init_nic - Initialization of hardware
b7c5678f 1252 * @nic: device private variable
20346722 1253 * Description: The function sequentially configures every block
1254 * of the H/W from their reset values.
1255 * Return Value: SUCCESS on success and
1da177e4
LT		 1256 * '-1' on failure (endian settings incorrect).
1257 */
1258
1259static int init_nic(struct s2io_nic *nic)
1260{
1ee6dd77 1261 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1262 struct net_device *dev = nic->dev;
1263 register u64 val64 = 0;
1264 void __iomem *add;
1265 u32 time;
1266 int i, j;
c92ca04b 1267 int dtx_cnt = 0;
1da177e4 1268 unsigned long long mem_share;
20346722 1269 int mem_size;
ffb5df6c
JP		 1270 struct config_param *config = &nic->config;
1271 struct mac_info *mac_control = &nic->mac_control;
1da177e4 1272
5e25b9dd 1273 /* to set the swapper controle on the card */
d44570e4
JP		 1274 if (s2io_set_swapper(nic)) {
1275 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
9f74ffde 1276 return -EIO;
1da177e4
LT		 1277 }
1278
541ae68f 1279 /*
1280 * Herc requires EOI to be removed from reset before XGXS, so..
1281 */
1282 if (nic->device_type & XFRAME_II_DEVICE) {
1283 val64 = 0xA500000000ULL;
1284 writeq(val64, &bar0->sw_reset);
1285 msleep(500);
1286 val64 = readq(&bar0->sw_reset);
1287 }
1288
1da177e4
LT		 1289 /* Remove XGXS from reset state */
1290 val64 = 0;
1291 writeq(val64, &bar0->sw_reset);
1da177e4 1292 msleep(500);
20346722 1293 val64 = readq(&bar0->sw_reset);
1da177e4 1294
7962024e
SH		 1295 /* Ensure that it's safe to access registers by checking
1296 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1297 */
1298 if (nic->device_type == XFRAME_II_DEVICE) {
1299 for (i = 0; i < 50; i++) {
1300 val64 = readq(&bar0->adapter_status);
1301 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1302 break;
1303 msleep(10);
1304 }
1305 if (i == 50)
1306 return -ENODEV;
1307 }
1308
1da177e4
LT		 1309 /* Enable Receiving broadcasts */
1310 add = &bar0->mac_cfg;
1311 val64 = readq(&bar0->mac_cfg);
1312 val64 |= MAC_RMAC_BCAST_ENABLE;
1313 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 1314 writel((u32)val64, add);
1da177e4
LT		 1315 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1316 writel((u32) (val64 >> 32), (add + 4));
1317
1318 /* Read registers in all blocks */
1319 val64 = readq(&bar0->mac_int_mask);
1320 val64 = readq(&bar0->mc_int_mask);
1321 val64 = readq(&bar0->xgxs_int_mask);
1322
1323 /* Set MTU */
1324 val64 = dev->mtu;
1325 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1326
541ae68f 1327 if (nic->device_type & XFRAME_II_DEVICE) {
1328 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1329 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1330 &bar0->dtx_control, UF);
541ae68f 1331 if (dtx_cnt & 0x1)
1332 msleep(1); /* Necessary!! */
1da177e4
LT		 1333 dtx_cnt++;
1334 }
541ae68f 1335 } else {
c92ca04b
AR		 1336 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1337 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1338 &bar0->dtx_control, UF);
1339 val64 = readq(&bar0->dtx_control);
1340 dtx_cnt++;
1da177e4
LT		 1341 }
1342 }
1343
1344 /* Tx DMA Initialization */
1345 val64 = 0;
1346 writeq(val64, &bar0->tx_fifo_partition_0);
1347 writeq(val64, &bar0->tx_fifo_partition_1);
1348 writeq(val64, &bar0->tx_fifo_partition_2);
1349 writeq(val64, &bar0->tx_fifo_partition_3);
1350
1da177e4 1351 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 1352 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1353
1354 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1355 vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1da177e4
LT		 1356
1357 if (i == (config->tx_fifo_num - 1)) {
1358 if (i % 2 == 0)
1359 i++;
1360 }
1361
1362 switch (i) {
1363 case 1:
1364 writeq(val64, &bar0->tx_fifo_partition_0);
1365 val64 = 0;
b7c5678f 1366 j = 0;
1da177e4
LT		 1367 break;
1368 case 3:
1369 writeq(val64, &bar0->tx_fifo_partition_1);
1370 val64 = 0;
b7c5678f 1371 j = 0;
1da177e4
LT		 1372 break;
1373 case 5:
1374 writeq(val64, &bar0->tx_fifo_partition_2);
1375 val64 = 0;
b7c5678f 1376 j = 0;
1da177e4
LT		 1377 break;
1378 case 7:
1379 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1380 val64 = 0;
1381 j = 0;
1382 break;
1383 default:
1384 j++;
1da177e4
LT		 1385 break;
1386 }
1387 }
1388
5e25b9dd 1389 /*
1390 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1391 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1392 */
d44570e4 1393 if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
5e25b9dd 1394 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1395
1da177e4
LT		 1396 val64 = readq(&bar0->tx_fifo_partition_0);
1397 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
d44570e4 1398 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1da177e4 1399
20346722 1400 /*
1401 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1402 * integrity checking.
1403 */
1404 val64 = readq(&bar0->tx_pa_cfg);
d44570e4
JP		 1405 val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1406 TX_PA_CFG_IGNORE_SNAP_OUI |
1407 TX_PA_CFG_IGNORE_LLC_CTRL |
1408 TX_PA_CFG_IGNORE_L2_ERR;
1da177e4
LT		 1409 writeq(val64, &bar0->tx_pa_cfg);
1410
1411 /* Rx DMA intialization. */
1412 val64 = 0;
1413 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 1414 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1415
1416 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1da177e4
LT		 1417 }
1418 writeq(val64, &bar0->rx_queue_priority);
1419
20346722 1420 /*
1421 * Allocating equal share of memory to all the
1da177e4
LT		 1422 * configured Rings.
1423 */
1424 val64 = 0;
541ae68f 1425 if (nic->device_type & XFRAME_II_DEVICE)
1426 mem_size = 32;
1427 else
1428 mem_size = 64;
1429
1da177e4
LT		 1430 for (i = 0; i < config->rx_ring_num; i++) {
1431 switch (i) {
1432 case 0:
20346722 1433 mem_share = (mem_size / config->rx_ring_num +
1434 mem_size % config->rx_ring_num);
1da177e4
LT		 1435 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1436 continue;
1437 case 1:
20346722 1438 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1439 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1440 continue;
1441 case 2:
20346722 1442 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1443 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1444 continue;
1445 case 3:
20346722 1446 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1447 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1448 continue;
1449 case 4:
20346722 1450 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1451 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1452 continue;
1453 case 5:
20346722 1454 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1455 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1456 continue;
1457 case 6:
20346722 1458 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1459 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1460 continue;
1461 case 7:
20346722 1462 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1463 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1464 continue;
1465 }
1466 }
1467 writeq(val64, &bar0->rx_queue_cfg);
1468
20346722 1469 /*
5e25b9dd 1470 * Filling Tx round robin registers
b7c5678f 1471 * as per the number of FIFOs for equal scheduling priority
1da177e4 1472 */
5e25b9dd 1473 switch (config->tx_fifo_num) {
1474 case 1:
b7c5678f 1475 val64 = 0x0;
5e25b9dd 1476 writeq(val64, &bar0->tx_w_round_robin_0);
1477 writeq(val64, &bar0->tx_w_round_robin_1);
1478 writeq(val64, &bar0->tx_w_round_robin_2);
1479 writeq(val64, &bar0->tx_w_round_robin_3);
1480 writeq(val64, &bar0->tx_w_round_robin_4);
1481 break;
1482 case 2:
b7c5678f 1483 val64 = 0x0001000100010001ULL;
5e25b9dd 1484 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1485 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1486 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1487 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1488 val64 = 0x0001000100000000ULL;
5e25b9dd 1489 writeq(val64, &bar0->tx_w_round_robin_4);
1490 break;
1491 case 3:
b7c5678f 1492 val64 = 0x0001020001020001ULL;
5e25b9dd 1493 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1494 val64 = 0x0200010200010200ULL;
5e25b9dd 1495 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1496 val64 = 0x0102000102000102ULL;
5e25b9dd 1497 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1498 val64 = 0x0001020001020001ULL;
5e25b9dd 1499 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1500 val64 = 0x0200010200000000ULL;
5e25b9dd 1501 writeq(val64, &bar0->tx_w_round_robin_4);
1502 break;
1503 case 4:
b7c5678f 1504 val64 = 0x0001020300010203ULL;
5e25b9dd 1505 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1506 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1507 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1508 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1509 val64 = 0x0001020300000000ULL;
5e25b9dd 1510 writeq(val64, &bar0->tx_w_round_robin_4);
1511 break;
1512 case 5:
b7c5678f 1513 val64 = 0x0001020304000102ULL;
5e25b9dd 1514 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1515 val64 = 0x0304000102030400ULL;
5e25b9dd 1516 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1517 val64 = 0x0102030400010203ULL;
5e25b9dd 1518 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1519 val64 = 0x0400010203040001ULL;
5e25b9dd 1520 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1521 val64 = 0x0203040000000000ULL;
5e25b9dd 1522 writeq(val64, &bar0->tx_w_round_robin_4);
1523 break;
1524 case 6:
b7c5678f 1525 val64 = 0x0001020304050001ULL;
5e25b9dd 1526 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1527 val64 = 0x0203040500010203ULL;
5e25b9dd 1528 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1529 val64 = 0x0405000102030405ULL;
5e25b9dd 1530 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1531 val64 = 0x0001020304050001ULL;
5e25b9dd 1532 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1533 val64 = 0x0203040500000000ULL;
5e25b9dd 1534 writeq(val64, &bar0->tx_w_round_robin_4);
1535 break;
1536 case 7:
b7c5678f 1537 val64 = 0x0001020304050600ULL;
5e25b9dd 1538 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1539 val64 = 0x0102030405060001ULL;
5e25b9dd 1540 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1541 val64 = 0x0203040506000102ULL;
5e25b9dd 1542 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1543 val64 = 0x0304050600010203ULL;
5e25b9dd 1544 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1545 val64 = 0x0405060000000000ULL;
5e25b9dd 1546 writeq(val64, &bar0->tx_w_round_robin_4);
1547 break;
1548 case 8:
b7c5678f 1549 val64 = 0x0001020304050607ULL;
5e25b9dd 1550 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1551 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1552 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1553 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1554 val64 = 0x0001020300000000ULL;
5e25b9dd 1555 writeq(val64, &bar0->tx_w_round_robin_4);
1556 break;
1557 }
1558
b41477f3 1559 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1560 val64 = readq(&bar0->tx_fifo_partition_0);
1561 val64 |= (TX_FIFO_PARTITION_EN);
1562 writeq(val64, &bar0->tx_fifo_partition_0);
1563
5e25b9dd 1564 /* Filling the Rx round robin registers as per the
0425b46a
SH		 1565 * number of Rings and steering based on QoS with
1566 * equal priority.
1567 */
5e25b9dd 1568 switch (config->rx_ring_num) {
1569 case 1:
0425b46a
SH		 1570 val64 = 0x0;
1571 writeq(val64, &bar0->rx_w_round_robin_0);
1572 writeq(val64, &bar0->rx_w_round_robin_1);
1573 writeq(val64, &bar0->rx_w_round_robin_2);
1574 writeq(val64, &bar0->rx_w_round_robin_3);
1575 writeq(val64, &bar0->rx_w_round_robin_4);
1576
5e25b9dd 1577 val64 = 0x8080808080808080ULL;
1578 writeq(val64, &bar0->rts_qos_steering);
1579 break;
1580 case 2:
0425b46a 1581 val64 = 0x0001000100010001ULL;
5e25b9dd 1582 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1583 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1584 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1585 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1586 val64 = 0x0001000100000000ULL;
5e25b9dd 1587 writeq(val64, &bar0->rx_w_round_robin_4);
1588
1589 val64 = 0x8080808040404040ULL;
1590 writeq(val64, &bar0->rts_qos_steering);
1591 break;
1592 case 3:
0425b46a 1593 val64 = 0x0001020001020001ULL;
5e25b9dd 1594 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1595 val64 = 0x0200010200010200ULL;
5e25b9dd 1596 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1597 val64 = 0x0102000102000102ULL;
5e25b9dd 1598 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1599 val64 = 0x0001020001020001ULL;
5e25b9dd 1600 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1601 val64 = 0x0200010200000000ULL;
5e25b9dd 1602 writeq(val64, &bar0->rx_w_round_robin_4);
1603
1604 val64 = 0x8080804040402020ULL;
1605 writeq(val64, &bar0->rts_qos_steering);
1606 break;
1607 case 4:
0425b46a 1608 val64 = 0x0001020300010203ULL;
5e25b9dd 1609 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1610 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1611 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1612 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1613 val64 = 0x0001020300000000ULL;
5e25b9dd 1614 writeq(val64, &bar0->rx_w_round_robin_4);
1615
1616 val64 = 0x8080404020201010ULL;
1617 writeq(val64, &bar0->rts_qos_steering);
1618 break;
1619 case 5:
0425b46a 1620 val64 = 0x0001020304000102ULL;
5e25b9dd 1621 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1622 val64 = 0x0304000102030400ULL;
5e25b9dd 1623 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1624 val64 = 0x0102030400010203ULL;
5e25b9dd 1625 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1626 val64 = 0x0400010203040001ULL;
5e25b9dd 1627 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1628 val64 = 0x0203040000000000ULL;
5e25b9dd 1629 writeq(val64, &bar0->rx_w_round_robin_4);
1630
1631 val64 = 0x8080404020201008ULL;
1632 writeq(val64, &bar0->rts_qos_steering);
1633 break;
1634 case 6:
0425b46a 1635 val64 = 0x0001020304050001ULL;
5e25b9dd 1636 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1637 val64 = 0x0203040500010203ULL;
5e25b9dd 1638 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1639 val64 = 0x0405000102030405ULL;
5e25b9dd 1640 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1641 val64 = 0x0001020304050001ULL;
5e25b9dd 1642 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1643 val64 = 0x0203040500000000ULL;
5e25b9dd 1644 writeq(val64, &bar0->rx_w_round_robin_4);
1645
1646 val64 = 0x8080404020100804ULL;
1647 writeq(val64, &bar0->rts_qos_steering);
1648 break;
1649 case 7:
0425b46a 1650 val64 = 0x0001020304050600ULL;
5e25b9dd 1651 writeq(val64, &bar0->rx_w_round_robin_0);
0425b46a 1652 val64 = 0x0102030405060001ULL;
5e25b9dd 1653 writeq(val64, &bar0->rx_w_round_robin_1);
0425b46a 1654 val64 = 0x0203040506000102ULL;
5e25b9dd 1655 writeq(val64, &bar0->rx_w_round_robin_2);
0425b46a 1656 val64 = 0x0304050600010203ULL;
5e25b9dd 1657 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1658 val64 = 0x0405060000000000ULL;
5e25b9dd 1659 writeq(val64, &bar0->rx_w_round_robin_4);
1660
1661 val64 = 0x8080402010080402ULL;
1662 writeq(val64, &bar0->rts_qos_steering);
1663 break;
1664 case 8:
0425b46a 1665 val64 = 0x0001020304050607ULL;
5e25b9dd 1666 writeq(val64, &bar0->rx_w_round_robin_0);
5e25b9dd 1667 writeq(val64, &bar0->rx_w_round_robin_1);
5e25b9dd 1668 writeq(val64, &bar0->rx_w_round_robin_2);
5e25b9dd 1669 writeq(val64, &bar0->rx_w_round_robin_3);
0425b46a 1670 val64 = 0x0001020300000000ULL;
5e25b9dd 1671 writeq(val64, &bar0->rx_w_round_robin_4);
1672
1673 val64 = 0x8040201008040201ULL;
1674 writeq(val64, &bar0->rts_qos_steering);
1675 break;
1676 }
1da177e4
LT		 1677
1678 /* UDP Fix */
1679 val64 = 0;
20346722 1680 for (i = 0; i < 8; i++)
1da177e4
LT		 1681 writeq(val64, &bar0->rts_frm_len_n[i]);
1682
5e25b9dd 1683 /* Set the default rts frame length for the rings configured */
1684 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1685 for (i = 0 ; i < config->rx_ring_num ; i++)
1686 writeq(val64, &bar0->rts_frm_len_n[i]);
1687
1688 /* Set the frame length for the configured rings
1689 * desired by the user
1690 */
1691 for (i = 0; i < config->rx_ring_num; i++) {
1692 /* If rts_frm_len[i] == 0 then it is assumed that user not
1693 * specified frame length steering.
1694 * If the user provides the frame length then program
1695 * the rts_frm_len register for those values or else
1696 * leave it as it is.
1697 */
1698 if (rts_frm_len[i] != 0) {
1699 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
d44570e4 1700 &bar0->rts_frm_len_n[i]);
5e25b9dd 1701 }
1702 }
8a4bdbaa 1703
9fc93a41
SS		 1704 /* Disable differentiated services steering logic */
1705 for (i = 0; i < 64; i++) {
1706 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1707 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
d44570e4 1708 dev->name);
9fc93a41 1709 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1710 return -ENODEV;
9fc93a41
SS		 1711 }
1712 }
1713
20346722 1714 /* Program statistics memory */
1da177e4 1715 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1716
541ae68f 1717 if (nic->device_type == XFRAME_II_DEVICE) {
1718 val64 = STAT_BC(0x320);
1719 writeq(val64, &bar0->stat_byte_cnt);
1720 }
1721
20346722 1722 /*
1da177e4
LT		 1723 * Initializing the sampling rate for the device to calculate the
1724 * bandwidth utilization.
1725 */
1726 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
d44570e4 1727 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1da177e4
LT		 1728 writeq(val64, &bar0->mac_link_util);
1729
20346722 1730 /*
1731 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1732 * Scheme.
1733 */
1da177e4 1734
b7c5678f
RV		 1735 /* Initialize TTI */
1736 if (SUCCESS != init_tti(nic, nic->last_link_state))
1737 return -ENODEV;
1da177e4 1738
8a4bdbaa
SS		 1739 /* RTI Initialization */
1740 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1741 /*
8a4bdbaa
SS		 1742 * Programmed to generate Apprx 500 Intrs per
1743 * second
1744 */
1745 int count = (nic->config.bus_speed * 125)/4;
1746 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1747 } else
1748 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1749 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
d44570e4
JP		 1750 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1751 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1752 RTI_DATA1_MEM_RX_TIMER_AC_EN;
8a4bdbaa
SS		 1753
1754 writeq(val64, &bar0->rti_data1_mem);
1755
1756 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1757 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1758 if (nic->config.intr_type == MSI_X)
d44570e4
JP		 1759 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1760 RTI_DATA2_MEM_RX_UFC_D(0x40));
8a4bdbaa 1761 else
d44570e4
JP		 1762 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1763 RTI_DATA2_MEM_RX_UFC_D(0x80));
8a4bdbaa 1764 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1765
8a4bdbaa 1766 for (i = 0; i < config->rx_ring_num; i++) {
d44570e4
JP		 1767 val64 = RTI_CMD_MEM_WE |
1768 RTI_CMD_MEM_STROBE_NEW_CMD |
1769 RTI_CMD_MEM_OFFSET(i);
8a4bdbaa 1770 writeq(val64, &bar0->rti_command_mem);
1da177e4 1771
8a4bdbaa
SS		 1772 /*
1773 * Once the operation completes, the Strobe bit of the
1774 * command register will be reset. We poll for this
1775 * particular condition. We wait for a maximum of 500ms
1776 * for the operation to complete, if it's not complete
1777 * by then we return error.
1778 */
1779 time = 0;
f957bcf0 1780 while (true) {
8a4bdbaa
SS		 1781 val64 = readq(&bar0->rti_command_mem);
1782 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1783 break;
b6e3f982 1784
8a4bdbaa
SS		 1785 if (time > 10) {
1786 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1787 dev->name);
9f74ffde 1788 return -ENODEV;
b6e3f982 1789 }
8a4bdbaa
SS		 1790 time++;
1791 msleep(50);
1da177e4 1792 }
1da177e4
LT		 1793 }
1794
20346722 1795 /*
1796 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1797 * the 8 Queues on Rx side.
1798 */
1799 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1800 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1801
1802 /* Disable RMAC PAD STRIPPING */
509a2671 1803 add = &bar0->mac_cfg;
1da177e4
LT		 1804 val64 = readq(&bar0->mac_cfg);
1805 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1806 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1807 writel((u32) (val64), add);
1808 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1809 writel((u32) (val64 >> 32), (add + 4));
1810 val64 = readq(&bar0->mac_cfg);
1811
7d3d0439
RA		 1812 /* Enable FCS stripping by adapter */
1813 add = &bar0->mac_cfg;
1814 val64 = readq(&bar0->mac_cfg);
1815 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1816 if (nic->device_type == XFRAME_II_DEVICE)
1817 writeq(val64, &bar0->mac_cfg);
1818 else {
1819 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1820 writel((u32) (val64), add);
1821 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1822 writel((u32) (val64 >> 32), (add + 4));
1823 }
1824
20346722 1825 /*
1826 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1827 * generated by xena.
1828 */
1829 val64 = readq(&bar0->rmac_pause_cfg);
1830 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1831 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1832 writeq(val64, &bar0->rmac_pause_cfg);
1833
20346722 1834 /*
1da177e4
LT		 1835 * Set the Threshold Limit for Generating the pause frame
1836 * If the amount of data in any Queue exceeds ratio of
1837 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1838 * pause frame is generated
1839 */
1840 val64 = 0;
1841 for (i = 0; i < 4; i++) {
d44570e4
JP		 1842 val64 |= (((u64)0xFF00 |
1843 nic->mac_control.mc_pause_threshold_q0q3)
1844 << (i * 2 * 8));
1da177e4
LT		 1845 }
1846 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1847
1848 val64 = 0;
1849 for (i = 0; i < 4; i++) {
d44570e4
JP		 1850 val64 |= (((u64)0xFF00 |
1851 nic->mac_control.mc_pause_threshold_q4q7)
1852 << (i * 2 * 8));
1da177e4
LT		 1853 }
1854 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1855
20346722 1856 /*
1857 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1858 * exceeded the limit pointed by shared_splits
1859 */
1860 val64 = readq(&bar0->pic_control);
1861 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1862 writeq(val64, &bar0->pic_control);
1863
863c11a9
AR		 1864 if (nic->config.bus_speed == 266) {
1865 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1866 writeq(0x0, &bar0->read_retry_delay);
1867 writeq(0x0, &bar0->write_retry_delay);
1868 }
1869
541ae68f 1870 /*
1871 * Programming the Herc to split every write transaction
1872 * that does not start on an ADB to reduce disconnects.
1873 */
1874 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1875 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1876 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1877 writeq(val64, &bar0->misc_control);
1878 val64 = readq(&bar0->pic_control2);
b7b5a128 1879 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1880 writeq(val64, &bar0->pic_control2);
541ae68f 1881 }
c92ca04b
AR		 1882 if (strstr(nic->product_name, "CX4")) {
1883 val64 = TMAC_AVG_IPG(0x17);
1884 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d 1885 }
1886
1da177e4
LT		 1887 return SUCCESS;
1888}
a371a07d 1889#define LINK_UP_DOWN_INTERRUPT 1
1890#define MAC_RMAC_ERR_TIMER 2
1891
1ee6dd77 1892static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1893{
1894 if (nic->device_type == XFRAME_II_DEVICE)
1895 return LINK_UP_DOWN_INTERRUPT;
1896 else
1897 return MAC_RMAC_ERR_TIMER;
1898}
8116f3cf 1899
9caab458
SS		 1900/**
1901 * do_s2io_write_bits - update alarm bits in alarm register
1902 * @value: alarm bits
1903 * @flag: interrupt status
1904 * @addr: address value
1905 * Description: update alarm bits in alarm register
1906 * Return Value:
1907 * NONE.
1908 */
1909static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1910{
1911 u64 temp64;
1912
1913 temp64 = readq(addr);
1914
d44570e4
JP		 1915 if (flag == ENABLE_INTRS)
1916 temp64 &= ~((u64)value);
9caab458 1917 else
d44570e4 1918 temp64 |= ((u64)value);
9caab458
SS		 1919 writeq(temp64, addr);
1920}
1da177e4 1921
43b7c451 1922static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1923{
1924 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1925 register u64 gen_int_mask = 0;
01e16faa 1926 u64 interruptible;
9caab458 1927
01e16faa 1928 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
9caab458 1929 if (mask & TX_DMA_INTR) {
9caab458
SS		 1930 gen_int_mask |= TXDMA_INT_M;
1931
1932 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
d44570e4
JP		 1933 TXDMA_PCC_INT | TXDMA_TTI_INT |
1934 TXDMA_LSO_INT | TXDMA_TPA_INT |
1935 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
9caab458
SS		 1936
1937 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
d44570e4
JP		 1938 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1939 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1940 &bar0->pfc_err_mask);
9caab458
SS		 1941
1942 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
d44570e4
JP		 1943 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1944 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
9caab458
SS		 1945
1946 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
d44570e4
JP		 1947 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1948 PCC_N_SERR | PCC_6_COF_OV_ERR |
1949 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1950 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1951 PCC_TXB_ECC_SG_ERR,
1952 flag, &bar0->pcc_err_mask);
9caab458
SS		 1953
1954 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
d44570e4 1955 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
9caab458
SS		 1956
1957 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
d44570e4
JP		 1958 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1959 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1960 flag, &bar0->lso_err_mask);
9caab458
SS		 1961
1962 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
d44570e4 1963 flag, &bar0->tpa_err_mask);
9caab458
SS		 1964
1965 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
9caab458
SS		 1966 }
1967
1968 if (mask & TX_MAC_INTR) {
1969 gen_int_mask |= TXMAC_INT_M;
1970 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
d44570e4 1971 &bar0->mac_int_mask);
9caab458 1972 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
d44570e4
JP		 1973 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1974 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1975 flag, &bar0->mac_tmac_err_mask);
9caab458
SS		 1976 }
1977
1978 if (mask & TX_XGXS_INTR) {
1979 gen_int_mask |= TXXGXS_INT_M;
1980 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
d44570e4 1981 &bar0->xgxs_int_mask);
9caab458 1982 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
d44570e4
JP		 1983 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1984 flag, &bar0->xgxs_txgxs_err_mask);
9caab458
SS		 1985 }
1986
1987 if (mask & RX_DMA_INTR) {
1988 gen_int_mask |= RXDMA_INT_M;
1989 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
d44570e4
JP		 1990 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1991 flag, &bar0->rxdma_int_mask);
9caab458 1992 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
d44570e4
JP		 1993 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1994 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1995 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
9caab458 1996 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
d44570e4
JP		 1997 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1998 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1999 &bar0->prc_pcix_err_mask);
9caab458 2000 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
d44570e4
JP		 2001 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
2002 &bar0->rpa_err_mask);
9caab458 2003 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
d44570e4
JP		 2004 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
2005 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
2006 RDA_FRM_ECC_SG_ERR |
2007 RDA_MISC_ERR|RDA_PCIX_ERR,
2008 flag, &bar0->rda_err_mask);
9caab458 2009 do_s2io_write_bits(RTI_SM_ERR_ALARM |
d44570e4
JP		 2010 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
2011 flag, &bar0->rti_err_mask);
9caab458
SS		 2012 }
2013
2014 if (mask & RX_MAC_INTR) {
2015 gen_int_mask |= RXMAC_INT_M;
2016 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
d44570e4
JP		 2017 &bar0->mac_int_mask);
2018 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
2019 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
2020 RMAC_DOUBLE_ECC_ERR);
01e16faa
SH		 2021 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
2022 interruptible |= RMAC_LINK_STATE_CHANGE_INT;
2023 do_s2io_write_bits(interruptible,
d44570e4 2024 flag, &bar0->mac_rmac_err_mask);
9caab458
SS		 2025 }
2026
d44570e4 2027 if (mask & RX_XGXS_INTR) {
9caab458
SS		 2028 gen_int_mask |= RXXGXS_INT_M;
2029 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
d44570e4 2030 &bar0->xgxs_int_mask);
9caab458 2031 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
d44570e4 2032 &bar0->xgxs_rxgxs_err_mask);
9caab458
SS		 2033 }
2034
2035 if (mask & MC_INTR) {
2036 gen_int_mask |= MC_INT_M;
d44570e4
JP		 2037 do_s2io_write_bits(MC_INT_MASK_MC_INT,
2038 flag, &bar0->mc_int_mask);
9caab458 2039 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
d44570e4
JP		 2040 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
2041 &bar0->mc_err_mask);
9caab458
SS		 2042 }
2043 nic->general_int_mask = gen_int_mask;
2044
2045 /* Remove this line when alarm interrupts are enabled */
2046 nic->general_int_mask = 0;
2047}
d44570e4 2048
20346722 2049/**
2050 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 2051 * @nic: device private variable,
2052 * @mask: A mask indicating which Intr block must be modified and,
2053 * @flag: A flag indicating whether to enable or disable the Intrs.
2054 * Description: This function will either disable or enable the interrupts
20346722 2055 * depending on the flag argument. The mask argument can be used to
2056 * enable/disable any Intr block.
1da177e4
LT		 2057 * Return Value: NONE.
2058 */
2059
2060static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
2061{
1ee6dd77 2062 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 2063 register u64 temp64 = 0, intr_mask = 0;
2064
2065 intr_mask = nic->general_int_mask;
1da177e4
LT		 2066
2067 /* Top level interrupt classification */
2068 /* PIC Interrupts */
9caab458 2069 if (mask & TX_PIC_INTR) {
1da177e4 2070 /* Enable PIC Intrs in the general intr mask register */
9caab458 2071 intr_mask |= TXPIC_INT_M;
1da177e4 2072 if (flag == ENABLE_INTRS) {
20346722 2073 /*
a371a07d 2074 * If Hercules adapter enable GPIO otherwise
b41477f3 2075 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722 2076 * interrupts for now.
2077 * TODO
1da177e4 2078 */
a371a07d 2079 if (s2io_link_fault_indication(nic) ==
d44570e4 2080 LINK_UP_DOWN_INTERRUPT) {
9caab458 2081 do_s2io_write_bits(PIC_INT_GPIO, flag,
d44570e4 2082 &bar0->pic_int_mask);
9caab458 2083 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
d44570e4 2084 &bar0->gpio_int_mask);
9caab458 2085 } else
a371a07d 2086 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 2087 } else if (flag == DISABLE_INTRS) {
20346722 2088 /*
2089 * Disable PIC Intrs in the general
2090 * intr mask register
1da177e4
LT		 2091 */
2092 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 2093 }
2094 }
2095
1da177e4
LT		 2096 /* Tx traffic interrupts */
2097 if (mask & TX_TRAFFIC_INTR) {
9caab458 2098 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 2099 if (flag == ENABLE_INTRS) {
20346722 2100 /*
1da177e4 2101 * Enable all the Tx side interrupts
20346722 2102 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 2103 */
2104 writeq(0x0, &bar0->tx_traffic_mask);
2105 } else if (flag == DISABLE_INTRS) {
20346722 2106 /*
2107 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 2108 * register.
2109 */
2110 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2111 }
2112 }
2113
2114 /* Rx traffic interrupts */
2115 if (mask & RX_TRAFFIC_INTR) {
9caab458 2116 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2117 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2118 /* writing 0 Enables all 8 RX interrupt levels */
2119 writeq(0x0, &bar0->rx_traffic_mask);
2120 } else if (flag == DISABLE_INTRS) {
20346722 2121 /*
2122 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2123 * register.
2124 */
2125 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2126 }
2127 }
9caab458
SS		 2128
2129 temp64 = readq(&bar0->general_int_mask);
2130 if (flag == ENABLE_INTRS)
d44570e4 2131 temp64 &= ~((u64)intr_mask);
9caab458
SS		 2132 else
2133 temp64 = DISABLE_ALL_INTRS;
2134 writeq(temp64, &bar0->general_int_mask);
2135
2136 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2137}
2138
19a60522
SS		 2139/**
2140 * verify_pcc_quiescent- Checks for PCC quiescent state
2141 * Return: 1 If PCC is quiescence
2142 * 0 If PCC is not quiescence
2143 */
1ee6dd77 2144static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2145{
19a60522 2146 int ret = 0, herc;
1ee6dd77 2147 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2148 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2149
19a60522 2150 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722 2151
f957bcf0 2152 if (flag == false) {
44c10138 2153 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2154 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2155 ret = 1;
19a60522
SS		 2156 } else {
2157 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2158 ret = 1;
20346722 2159 }
2160 } else {
44c10138 2161 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2162 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2163 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2164 ret = 1;
5e25b9dd 2165 } else {
2166 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2167 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2168 ret = 1;
20346722 2169 }
2170 }
2171
2172 return ret;
2173}
2174/**
2175 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2176 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2177 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2178 * differs and the calling function passes the input argument flag to
2179 * indicate this.
20346722 2180 * Return: 1 If xena is quiescence
1da177e4
LT		 2181 * 0 If Xena is not quiescence
2182 */
2183
1ee6dd77 2184static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2185{
19a60522 2186 int mode;
1ee6dd77 2187 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2188 u64 val64 = readq(&bar0->adapter_status);
2189 mode = s2io_verify_pci_mode(sp);
1da177e4 2190
19a60522
SS		 2191 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2192 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2193 return 0;
2194 }
2195 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
d44570e4 2196 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
19a60522
SS		 2197 return 0;
2198 }
2199 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2200 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2201 return 0;
2202 }
2203 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2204 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2205 return 0;
2206 }
2207 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2208 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2209 return 0;
2210 }
2211 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2212 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2213 return 0;
2214 }
2215 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2216 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2217 return 0;
2218 }
2219 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2220 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2221 return 0;
1da177e4
LT		 2222 }
2223
19a60522
SS		 2224 /*
2225 * In PCI 33 mode, the P_PLL is not used, and therefore,
2226 * the the P_PLL_LOCK bit in the adapter_status register will
2227 * not be asserted.
2228 */
2229 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
d44570e4
JP		 2230 sp->device_type == XFRAME_II_DEVICE &&
2231 mode != PCI_MODE_PCI_33) {
19a60522
SS		 2232 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2233 return 0;
2234 }
2235 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
d44570e4 2236 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
19a60522
SS		 2237 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2238 return 0;
2239 }
2240 return 1;
1da177e4
LT		 2241}
2242
2243/**
2244 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2245 * @sp: Pointer to device specifc structure
20346722 2246 * Description :
1da177e4
LT		 2247 * New procedure to clear mac address reading problems on Alpha platforms
2248 *
2249 */
2250
d44570e4 2251static void fix_mac_address(struct s2io_nic *sp)
1da177e4 2252{
1ee6dd77 2253 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2254 u64 val64;
2255 int i = 0;
2256
2257 while (fix_mac[i] != END_SIGN) {
2258 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2259 udelay(10);
1da177e4
LT		 2260 val64 = readq(&bar0->gpio_control);
2261 }
2262}
2263
2264/**
20346722 2265 * start_nic - Turns the device on
1da177e4 2266 * @nic : device private variable.
20346722 2267 * Description:
2268 * This function actually turns the device on. Before this function is
2269 * called,all Registers are configured from their reset states
2270 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2271 * calling this function, the device interrupts are cleared and the NIC is
2272 * literally switched on by writing into the adapter control register.
20346722 2273 * Return Value:
1da177e4
LT		 2274 * SUCCESS on success and -1 on failure.
2275 */
2276
2277static int start_nic(struct s2io_nic *nic)
2278{
1ee6dd77 2279 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2280 struct net_device *dev = nic->dev;
2281 register u64 val64 = 0;
20346722 2282 u16 subid, i;
ffb5df6c
JP		 2283 struct config_param *config = &nic->config;
2284 struct mac_info *mac_control = &nic->mac_control;
1da177e4
LT		 2285
2286 /* PRC Initialization and configuration */
2287 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2288 struct ring_info *ring = &mac_control->rings[i];
2289
d44570e4 2290 writeq((u64)ring->rx_blocks[0].block_dma_addr,
1da177e4
LT		 2291 &bar0->prc_rxd0_n[i]);
2292
2293 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2294 if (nic->rxd_mode == RXD_MODE_1)
2295 val64 |= PRC_CTRL_RC_ENABLED;
2296 else
2297 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2298 if (nic->device_type == XFRAME_II_DEVICE)
2299 val64 |= PRC_CTRL_GROUP_READS;
2300 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2301 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2302 writeq(val64, &bar0->prc_ctrl_n[i]);
2303 }
2304
da6971d8
AR		 2305 if (nic->rxd_mode == RXD_MODE_3B) {
2306 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2307 val64 = readq(&bar0->rx_pa_cfg);
2308 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2309 writeq(val64, &bar0->rx_pa_cfg);
2310 }
1da177e4 2311
926930b2
SS		 2312 if (vlan_tag_strip == 0) {
2313 val64 = readq(&bar0->rx_pa_cfg);
2314 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2315 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 2316 nic->vlan_strip_flag = 0;
926930b2
SS		 2317 }
2318
20346722 2319 /*
1da177e4
LT		 2320 * Enabling MC-RLDRAM. After enabling the device, we timeout
2321 * for around 100ms, which is approximately the time required
2322 * for the device to be ready for operation.
2323 */
2324 val64 = readq(&bar0->mc_rldram_mrs);
2325 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2326 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2327 val64 = readq(&bar0->mc_rldram_mrs);
2328
20346722 2329 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2330
2331 /* Enabling ECC Protection. */
2332 val64 = readq(&bar0->adapter_control);
2333 val64 &= ~ADAPTER_ECC_EN;
2334 writeq(val64, &bar0->adapter_control);
2335
20346722 2336 /*
2337 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2338 * it.
2339 */
2340 val64 = readq(&bar0->adapter_status);
19a60522 2341 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2342 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2343 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
d44570e4 2344 (unsigned long long)val64);
1da177e4
LT		 2345 return FAILURE;
2346 }
2347
20346722 2348 /*
1da177e4 2349 * With some switches, link might be already up at this point.
20346722 2350 * Because of this weird behavior, when we enable laser,
2351 * we may not get link. We need to handle this. We cannot
2352 * figure out which switch is misbehaving. So we are forced to
2353 * make a global change.
1da177e4
LT		 2354 */
2355
2356 /* Enabling Laser. */
2357 val64 = readq(&bar0->adapter_control);
2358 val64 |= ADAPTER_EOI_TX_ON;
2359 writeq(val64, &bar0->adapter_control);
2360
c92ca04b
AR		 2361 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2362 /*
2363 * Dont see link state interrupts initally on some switches,
2364 * so directly scheduling the link state task here.
2365 */
2366 schedule_work(&nic->set_link_task);
2367 }
1da177e4
LT		 2368 /* SXE-002: Initialize link and activity LED */
2369 subid = nic->pdev->subsystem_device;
541ae68f 2370 if (((subid & 0xFF) >= 0x07) &&
2371 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2372 val64 = readq(&bar0->gpio_control);
2373 val64 |= 0x0000800000000000ULL;
2374 writeq(val64, &bar0->gpio_control);
2375 val64 = 0x0411040400000000ULL;
509a2671 2376 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2377 }
2378
1da177e4
LT		 2379 return SUCCESS;
2380}
fed5eccd
AR		 2381/**
2382 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2383 */
d44570e4
JP		 2384static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2385 struct TxD *txdlp, int get_off)
fed5eccd 2386{
1ee6dd77 2387 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2388 struct sk_buff *skb;
1ee6dd77 2389 struct TxD *txds;
fed5eccd
AR		 2390 u16 j, frg_cnt;
2391
2392 txds = txdlp;
2fda096d 2393 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
d44570e4
JP		 2394 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2395 sizeof(u64), PCI_DMA_TODEVICE);
fed5eccd
AR		 2396 txds++;
2397 }
2398
d44570e4 2399 skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
fed5eccd 2400 if (!skb) {
1ee6dd77 2401 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2402 return NULL;
2403 }
d44570e4
JP		 2404 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2405 skb->len - skb->data_len, PCI_DMA_TODEVICE);
fed5eccd
AR		 2406 frg_cnt = skb_shinfo(skb)->nr_frags;
2407 if (frg_cnt) {
2408 txds++;
2409 for (j = 0; j < frg_cnt; j++, txds++) {
2410 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2411 if (!txds->Buffer_Pointer)
2412 break;
d44570e4
JP		 2413 pci_unmap_page(nic->pdev,
2414 (dma_addr_t)txds->Buffer_Pointer,
fed5eccd
AR		 2415 frag->size, PCI_DMA_TODEVICE);
2416 }
2417 }
d44570e4
JP		 2418 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2419 return skb;
fed5eccd 2420}
1da177e4 2421
20346722 2422/**
2423 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2424 * @nic : device private variable.
20346722 2425 * Description:
1da177e4 2426 * Free all queued Tx buffers.
20346722 2427 * Return Value: void
d44570e4 2428 */
1da177e4
LT		 2429
2430static void free_tx_buffers(struct s2io_nic *nic)
2431{
2432 struct net_device *dev = nic->dev;
2433 struct sk_buff *skb;
1ee6dd77 2434 struct TxD *txdp;
1da177e4 2435 int i, j;
fed5eccd 2436 int cnt = 0;
ffb5df6c
JP		 2437 struct config_param *config = &nic->config;
2438 struct mac_info *mac_control = &nic->mac_control;
2439 struct stat_block *stats = mac_control->stats_info;
2440 struct swStat *swstats = &stats->sw_stat;
1da177e4
LT		 2441
2442 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 2443 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2444 struct fifo_info *fifo = &mac_control->fifos[i];
2fda096d 2445 unsigned long flags;
13d866a9
JP		 2446
2447 spin_lock_irqsave(&fifo->tx_lock, flags);
2448 for (j = 0; j < tx_cfg->fifo_len; j++) {
2449 txdp = (struct TxD *)fifo->list_info[j].list_virt_addr;
fed5eccd
AR		 2450 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2451 if (skb) {
ffb5df6c 2452 swstats->mem_freed += skb->truesize;
fed5eccd
AR		 2453 dev_kfree_skb(skb);
2454 cnt++;
1da177e4 2455 }
1da177e4
LT		 2456 }
2457 DBG_PRINT(INTR_DBG,
2458 "%s:forcibly freeing %d skbs on FIFO%d\n",
2459 dev->name, cnt, i);
13d866a9
JP		 2460 fifo->tx_curr_get_info.offset = 0;
2461 fifo->tx_curr_put_info.offset = 0;
2462 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 2463 }
2464}
2465
20346722 2466/**
2467 * stop_nic - To stop the nic
1da177e4 2468 * @nic ; device private variable.
20346722 2469 * Description:
2470 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2471 * function does. This function is called to stop the device.
2472 * Return Value:
2473 * void.
2474 */
2475
2476static void stop_nic(struct s2io_nic *nic)
2477{
1ee6dd77 2478 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2479 register u64 val64 = 0;
5d3213cc 2480 u16 interruptible;
1da177e4
LT		 2481
2482 /* Disable all interrupts */
9caab458 2483 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2484 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2485 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2486 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2487
5d3213cc
AR		 2488 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2489 val64 = readq(&bar0->adapter_control);
2490 val64 &= ~(ADAPTER_CNTL_EN);
2491 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2492}
2493
20346722 2494/**
2495 * fill_rx_buffers - Allocates the Rx side skbs
0425b46a 2496 * @ring_info: per ring structure
3f78d885
SH		 2497 * @from_card_up: If this is true, we will map the buffer to get
2498 * the dma address for buf0 and buf1 to give it to the card.
2499 * Else we will sync the already mapped buffer to give it to the card.
20346722 2500 * Description:
1da177e4
LT		 2501 * The function allocates Rx side skbs and puts the physical
2502 * address of these buffers into the RxD buffer pointers, so that the NIC
2503 * can DMA the received frame into these locations.
2504 * The NIC supports 3 receive modes, viz
2505 * 1. single buffer,
2506 * 2. three buffer and
2507 * 3. Five buffer modes.
20346722 2508 * Each mode defines how many fragments the received frame will be split
2509 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2510 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2511 * is split into 3 fragments. As of now only single buffer mode is
2512 * supported.
2513 * Return Value:
2514 * SUCCESS on success or an appropriate -ve value on failure.
2515 */
8d8bb39b 2516static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
d44570e4 2517 int from_card_up)
1da177e4 2518{
1da177e4 2519 struct sk_buff *skb;
1ee6dd77 2520 struct RxD_t *rxdp;
0425b46a 2521 int off, size, block_no, block_no1;
1da177e4 2522 u32 alloc_tab = 0;
20346722 2523 u32 alloc_cnt;
20346722 2524 u64 tmp;
1ee6dd77 2525 struct buffAdd *ba;
1ee6dd77 2526 struct RxD_t *first_rxdp = NULL;
363dc367 2527 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
0425b46a 2528 int rxd_index = 0;
6d517a27
VP		 2529 struct RxD1 *rxdp1;
2530 struct RxD3 *rxdp3;
ffb5df6c 2531 struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
1da177e4 2532
0425b46a 2533 alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
1da177e4 2534
0425b46a 2535 block_no1 = ring->rx_curr_get_info.block_index;
1da177e4 2536 while (alloc_tab < alloc_cnt) {
0425b46a 2537 block_no = ring->rx_curr_put_info.block_index;
1da177e4 2538
0425b46a
SH		 2539 off = ring->rx_curr_put_info.offset;
2540
2541 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2542
2543 rxd_index = off + 1;
2544 if (block_no)
2545 rxd_index += (block_no * ring->rxd_count);
da6971d8 2546
7d2e3cb7 2547 if ((block_no == block_no1) &&
d44570e4
JP		 2548 (off == ring->rx_curr_get_info.offset) &&
2549 (rxdp->Host_Control)) {
2550 DBG_PRINT(INTR_DBG, "%s: Get and Put", ring->dev->name);
1da177e4
LT		 2551 DBG_PRINT(INTR_DBG, " info equated\n");
2552 goto end;
2553 }
0425b46a
SH		 2554 if (off && (off == ring->rxd_count)) {
2555 ring->rx_curr_put_info.block_index++;
2556 if (ring->rx_curr_put_info.block_index ==
d44570e4 2557 ring->block_count)
0425b46a
SH		 2558 ring->rx_curr_put_info.block_index = 0;
2559 block_no = ring->rx_curr_put_info.block_index;
2560 off = 0;
2561 ring->rx_curr_put_info.offset = off;
2562 rxdp = ring->rx_blocks[block_no].block_virt_addr;
1da177e4 2563 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
0425b46a
SH		 2564 ring->dev->name, rxdp);
2565
1da177e4 2566 }
c9fcbf47 2567
da6971d8 2568 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
d44570e4
JP		 2569 ((ring->rxd_mode == RXD_MODE_3B) &&
2570 (rxdp->Control_2 & s2BIT(0)))) {
0425b46a 2571 ring->rx_curr_put_info.offset = off;
1da177e4
LT		 2572 goto end;
2573 }
da6971d8 2574 /* calculate size of skb based on ring mode */
d44570e4
JP		 2575 size = ring->mtu +
2576 HEADER_ETHERNET_II_802_3_SIZE +
2577 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
0425b46a 2578 if (ring->rxd_mode == RXD_MODE_1)
da6971d8 2579 size += NET_IP_ALIGN;
da6971d8 2580 else
0425b46a 2581 size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2582
da6971d8
AR		 2583 /* allocate skb */
2584 skb = dev_alloc_skb(size);
d44570e4 2585 if (!skb) {
0425b46a 2586 DBG_PRINT(INFO_DBG, "%s: Out of ", ring->dev->name);
0c61ed5f 2587 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b 2588 if (first_rxdp) {
2589 wmb();
2590 first_rxdp->Control_1 |= RXD_OWN_XENA;
2591 }
ffb5df6c 2592 swstats->mem_alloc_fail_cnt++;
7d2e3cb7 2593
da6971d8
AR		 2594 return -ENOMEM ;
2595 }
ffb5df6c 2596 swstats->mem_allocated += skb->truesize;
0425b46a
SH		 2597
2598 if (ring->rxd_mode == RXD_MODE_1) {
da6971d8 2599 /* 1 buffer mode - normal operation mode */
d44570e4 2600 rxdp1 = (struct RxD1 *)rxdp;
1ee6dd77 2601 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2602 skb_reserve(skb, NET_IP_ALIGN);
d44570e4
JP		 2603 rxdp1->Buffer0_ptr =
2604 pci_map_single(ring->pdev, skb->data,
2605 size - NET_IP_ALIGN,
2606 PCI_DMA_FROMDEVICE);
8d8bb39b 2607 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2608 rxdp1->Buffer0_ptr))
491abf25
VP		 2609 goto pci_map_failed;
2610
8a4bdbaa 2611 rxdp->Control_2 =
491976b2 2612 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
d44570e4 2613 rxdp->Host_Control = (unsigned long)skb;
0425b46a 2614 } else if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8 2615 /*
6d517a27
VP		 2616 * 2 buffer mode -
2617 * 2 buffer mode provides 128
da6971d8 2618 * byte aligned receive buffers.
da6971d8
AR		 2619 */
2620
d44570e4 2621 rxdp3 = (struct RxD3 *)rxdp;
491976b2 2622 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2623 Buffer0_ptr = rxdp3->Buffer0_ptr;
2624 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2625 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2626 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2627 rxdp3->Buffer0_ptr = Buffer0_ptr;
2628 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2629
0425b46a 2630 ba = &ring->ba[block_no][off];
da6971d8 2631 skb_reserve(skb, BUF0_LEN);
d44570e4 2632 tmp = (u64)(unsigned long)skb->data;
da6971d8
AR		 2633 tmp += ALIGN_SIZE;
2634 tmp &= ~ALIGN_SIZE;
2635 skb->data = (void *) (unsigned long)tmp;
27a884dc 2636 skb_reset_tail_pointer(skb);
da6971d8 2637
3f78d885 2638 if (from_card_up) {
6d517a27 2639 rxdp3->Buffer0_ptr =
d44570e4
JP		 2640 pci_map_single(ring->pdev, ba->ba_0,
2641 BUF0_LEN,
2642 PCI_DMA_FROMDEVICE);
2643 if (pci_dma_mapping_error(nic->pdev,
2644 rxdp3->Buffer0_ptr))
3f78d885
SH		 2645 goto pci_map_failed;
2646 } else
0425b46a 2647 pci_dma_sync_single_for_device(ring->pdev,
d44570e4
JP		 2648 (dma_addr_t)rxdp3->Buffer0_ptr,
2649 BUF0_LEN,
2650 PCI_DMA_FROMDEVICE);
491abf25 2651
da6971d8 2652 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
0425b46a 2653 if (ring->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 2654 /* Two buffer mode */
2655
2656 /*
6aa20a22 2657 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2658 * L4 payload
2659 */
d44570e4
JP		 2660 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2661 skb->data,
2662 ring->mtu + 4,
2663 PCI_DMA_FROMDEVICE);
da6971d8 2664
8d8bb39b 2665 if (pci_dma_mapping_error(nic->pdev,
d44570e4 2666 rxdp3->Buffer2_ptr))
491abf25
VP		 2667 goto pci_map_failed;
2668
3f78d885 2669 if (from_card_up) {
0425b46a
SH		 2670 rxdp3->Buffer1_ptr =
2671 pci_map_single(ring->pdev,
d44570e4
JP		 2672 ba->ba_1,
2673 BUF1_LEN,
2674 PCI_DMA_FROMDEVICE);
0425b46a 2675
8d8bb39b 2676 if (pci_dma_mapping_error(nic->pdev,
d44570e4
JP		 2677 rxdp3->Buffer1_ptr)) {
2678 pci_unmap_single(ring->pdev,
2679 (dma_addr_t)(unsigned long)
2680 skb->data,
2681 ring->mtu + 4,
2682 PCI_DMA_FROMDEVICE);
3f78d885
SH		 2683 goto pci_map_failed;
2684 }
75c30b13 2685 }
da6971d8
AR		 2686 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2687 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
d44570e4 2688 (ring->mtu + 4);
da6971d8 2689 }
b7b5a128 2690 rxdp->Control_2 |= s2BIT(0);
0425b46a 2691 rxdp->Host_Control = (unsigned long) (skb);
1da177e4 2692 }
303bcb4b 2693 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2694 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2695 off++;
0425b46a 2696 if (off == (ring->rxd_count + 1))
da6971d8 2697 off = 0;
0425b46a 2698 ring->rx_curr_put_info.offset = off;
20346722 2699
da6971d8 2700 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b 2701 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2702 if (first_rxdp) {
2703 wmb();
2704 first_rxdp->Control_1 |= RXD_OWN_XENA;
2705 }
2706 first_rxdp = rxdp;
2707 }
0425b46a 2708 ring->rx_bufs_left += 1;
1da177e4
LT		 2709 alloc_tab++;
2710 }
2711
d44570e4 2712end:
303bcb4b 2713 /* Transfer ownership of first descriptor to adapter just before
2714 * exiting. Before that, use memory barrier so that ownership
2715 * and other fields are seen by adapter correctly.
2716 */
2717 if (first_rxdp) {
2718 wmb();
2719 first_rxdp->Control_1 |= RXD_OWN_XENA;
2720 }
2721
1da177e4 2722 return SUCCESS;
d44570e4 2723
491abf25 2724pci_map_failed:
ffb5df6c
JP		 2725 swstats->pci_map_fail_cnt++;
2726 swstats->mem_freed += skb->truesize;
491abf25
VP		 2727 dev_kfree_skb_irq(skb);
2728 return -ENOMEM;
1da177e4
LT		 2729}
2730
da6971d8
AR		 2731static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2732{
2733 struct net_device *dev = sp->dev;
2734 int j;
2735 struct sk_buff *skb;
1ee6dd77 2736 struct RxD_t *rxdp;
1ee6dd77 2737 struct buffAdd *ba;
6d517a27
VP		 2738 struct RxD1 *rxdp1;
2739 struct RxD3 *rxdp3;
ffb5df6c
JP		 2740 struct mac_info *mac_control = &sp->mac_control;
2741 struct stat_block *stats = mac_control->stats_info;
2742 struct swStat *swstats = &stats->sw_stat;
da6971d8 2743
da6971d8
AR		 2744 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2745 rxdp = mac_control->rings[ring_no].
d44570e4
JP		 2746 rx_blocks[blk].rxds[j].virt_addr;
2747 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2748 if (!skb)
da6971d8 2749 continue;
da6971d8 2750 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4
JP		 2751 rxdp1 = (struct RxD1 *)rxdp;
2752 pci_unmap_single(sp->pdev,
2753 (dma_addr_t)rxdp1->Buffer0_ptr,
2754 dev->mtu +
2755 HEADER_ETHERNET_II_802_3_SIZE +
2756 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2757 PCI_DMA_FROMDEVICE);
1ee6dd77 2758 memset(rxdp, 0, sizeof(struct RxD1));
d44570e4
JP		 2759 } else if (sp->rxd_mode == RXD_MODE_3B) {
2760 rxdp3 = (struct RxD3 *)rxdp;
2761 ba = &mac_control->rings[ring_no].ba[blk][j];
2762 pci_unmap_single(sp->pdev,
2763 (dma_addr_t)rxdp3->Buffer0_ptr,
2764 BUF0_LEN,
2765 PCI_DMA_FROMDEVICE);
2766 pci_unmap_single(sp->pdev,
2767 (dma_addr_t)rxdp3->Buffer1_ptr,
2768 BUF1_LEN,
2769 PCI_DMA_FROMDEVICE);
2770 pci_unmap_single(sp->pdev,
2771 (dma_addr_t)rxdp3->Buffer2_ptr,
2772 dev->mtu + 4,
2773 PCI_DMA_FROMDEVICE);
1ee6dd77 2774 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2775 }
ffb5df6c 2776 swstats->mem_freed += skb->truesize;
da6971d8 2777 dev_kfree_skb(skb);
0425b46a 2778 mac_control->rings[ring_no].rx_bufs_left -= 1;
da6971d8
AR		 2779 }
2780}
2781
1da177e4 2782/**
20346722 2783 * free_rx_buffers - Frees all Rx buffers
1da177e4 2784 * @sp: device private variable.
20346722 2785 * Description:
1da177e4
LT		 2786 * This function will free all Rx buffers allocated by host.
2787 * Return Value:
2788 * NONE.
2789 */
2790
2791static void free_rx_buffers(struct s2io_nic *sp)
2792{
2793 struct net_device *dev = sp->dev;
da6971d8 2794 int i, blk = 0, buf_cnt = 0;
ffb5df6c
JP		 2795 struct config_param *config = &sp->config;
2796 struct mac_info *mac_control = &sp->mac_control;
1da177e4
LT		 2797
2798 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2799 struct ring_info *ring = &mac_control->rings[i];
2800
da6971d8 2801 for (blk = 0; blk < rx_ring_sz[i]; blk++)
d44570e4 2802 free_rxd_blk(sp, i, blk);
1da177e4 2803
13d866a9
JP		 2804 ring->rx_curr_put_info.block_index = 0;
2805 ring->rx_curr_get_info.block_index = 0;
2806 ring->rx_curr_put_info.offset = 0;
2807 ring->rx_curr_get_info.offset = 0;
2808 ring->rx_bufs_left = 0;
1da177e4
LT		 2809 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2810 dev->name, buf_cnt, i);
2811 }
2812}
2813
8d8bb39b 2814static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
f61e0a35 2815{
8d8bb39b 2816 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
f61e0a35
SH		 2817 DBG_PRINT(INFO_DBG, "%s:Out of memory", ring->dev->name);
2818 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
2819 }
2820 return 0;
2821}
2822
1da177e4
LT		 2823/**
2824 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2825 * @napi : pointer to the napi structure.
20346722 2826 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2827 * during one pass through the 'Poll" function.
2828 * Description:
2829 * Comes into picture only if NAPI support has been incorporated. It does
2830 * the same thing that rx_intr_handler does, but not in a interrupt context
2831 * also It will process only a given number of packets.
2832 * Return value:
2833 * 0 on success and 1 if there are No Rx packets to be processed.
2834 */
2835
f61e0a35 2836static int s2io_poll_msix(struct napi_struct *napi, int budget)
1da177e4 2837{
f61e0a35
SH		 2838 struct ring_info *ring = container_of(napi, struct ring_info, napi);
2839 struct net_device *dev = ring->dev;
f61e0a35 2840 int pkts_processed = 0;
1a79d1c3
AV		 2841 u8 __iomem *addr = NULL;
2842 u8 val8 = 0;
4cf1653a 2843 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2844 struct XENA_dev_config __iomem *bar0 = nic->bar0;
f61e0a35 2845 int budget_org = budget;
1da177e4 2846
f61e0a35
SH		 2847 if (unlikely(!is_s2io_card_up(nic)))
2848 return 0;
1da177e4 2849
f61e0a35 2850 pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2851 s2io_chk_rx_buffers(nic, ring);
1da177e4 2852
f61e0a35 2853 if (pkts_processed < budget_org) {
288379f0 2854 napi_complete(napi);
f61e0a35 2855 /*Re Enable MSI-Rx Vector*/
1a79d1c3 2856 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 2857 addr += 7 - ring->ring_no;
2858 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2859 writeb(val8, addr);
2860 val8 = readb(addr);
1da177e4 2861 }
f61e0a35
SH		 2862 return pkts_processed;
2863}
d44570e4 2864
f61e0a35
SH		 2865static int s2io_poll_inta(struct napi_struct *napi, int budget)
2866{
2867 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
f61e0a35
SH		 2868 int pkts_processed = 0;
2869 int ring_pkts_processed, i;
2870 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2871 int budget_org = budget;
ffb5df6c
JP		 2872 struct config_param *config = &nic->config;
2873 struct mac_info *mac_control = &nic->mac_control;
1da177e4 2874
f61e0a35
SH		 2875 if (unlikely(!is_s2io_card_up(nic)))
2876 return 0;
1da177e4 2877
1da177e4 2878 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9 2879 struct ring_info *ring = &mac_control->rings[i];
f61e0a35 2880 ring_pkts_processed = rx_intr_handler(ring, budget);
8d8bb39b 2881 s2io_chk_rx_buffers(nic, ring);
f61e0a35
SH		 2882 pkts_processed += ring_pkts_processed;
2883 budget -= ring_pkts_processed;
2884 if (budget <= 0)
1da177e4 2885 break;
1da177e4 2886 }
f61e0a35 2887 if (pkts_processed < budget_org) {
288379f0 2888 napi_complete(napi);
f61e0a35
SH		 2889 /* Re enable the Rx interrupts for the ring */
2890 writeq(0, &bar0->rx_traffic_mask);
2891 readl(&bar0->rx_traffic_mask);
2892 }
2893 return pkts_processed;
1da177e4 2894}
20346722 2895
b41477f3 2896#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2897/**
b41477f3 2898 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2899 * @dev : pointer to the device structure.
2900 * Description:
b41477f3
AR		 2901 * This function will be called by upper layer to check for events on the
2902 * interface in situations where interrupts are disabled. It is used for
2903 * specific in-kernel networking tasks, such as remote consoles and kernel
2904 * debugging over the network (example netdump in RedHat).
612eff0e 2905 */
612eff0e
BH		 2906static void s2io_netpoll(struct net_device *dev)
2907{
4cf1653a 2908 struct s2io_nic *nic = netdev_priv(dev);
1ee6dd77 2909 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2910 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e 2911 int i;
ffb5df6c
JP		 2912 struct config_param *config = &nic->config;
2913 struct mac_info *mac_control = &nic->mac_control;
612eff0e 2914
d796fdb7
LV		 2915 if (pci_channel_offline(nic->pdev))
2916 return;
2917
612eff0e
BH		 2918 disable_irq(dev->irq);
2919
612eff0e 2920 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2921 writeq(val64, &bar0->tx_traffic_int);
2922
6aa20a22 2923 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2924 * run out of skbs and will fail and eventually netpoll application such
2925 * as netdump will fail.
2926 */
2927 for (i = 0; i < config->tx_fifo_num; i++)
2928 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2929
b41477f3 2930 /* check for received packet and indicate up to network */
13d866a9
JP		 2931 for (i = 0; i < config->rx_ring_num; i++) {
2932 struct ring_info *ring = &mac_control->rings[i];
2933
2934 rx_intr_handler(ring, 0);
2935 }
612eff0e
BH		 2936
2937 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 2938 struct ring_info *ring = &mac_control->rings[i];
2939
2940 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
0c61ed5f
RV		 2941 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2942 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2943 break;
2944 }
2945 }
612eff0e
BH		 2946 enable_irq(dev->irq);
2947 return;
2948}
2949#endif
2950
20346722 2951/**
1da177e4 2952 * rx_intr_handler - Rx interrupt handler
f61e0a35
SH		 2953 * @ring_info: per ring structure.
2954 * @budget: budget for napi processing.
20346722 2955 * Description:
2956 * If the interrupt is because of a received frame or if the
1da177e4 2957 * receive ring contains fresh as yet un-processed frames,this function is
20346722 2958 * called. It picks out the RxD at which place the last Rx processing had
2959 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2960 * the offset.
2961 * Return Value:
f61e0a35 2962 * No. of napi packets processed.
1da177e4 2963 */
f61e0a35 2964static int rx_intr_handler(struct ring_info *ring_data, int budget)
1da177e4 2965{
c9fcbf47 2966 int get_block, put_block;
1ee6dd77
RB		 2967 struct rx_curr_get_info get_info, put_info;
2968 struct RxD_t *rxdp;
1da177e4 2969 struct sk_buff *skb;
f61e0a35 2970 int pkt_cnt = 0, napi_pkts = 0;
7d3d0439 2971 int i;
d44570e4
JP		 2972 struct RxD1 *rxdp1;
2973 struct RxD3 *rxdp3;
7d3d0439 2974
20346722 2975 get_info = ring_data->rx_curr_get_info;
2976 get_block = get_info.block_index;
1ee6dd77 2977 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2978 put_block = put_info.block_index;
da6971d8 2979 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65 2980
da6971d8 2981 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2982 /*
2983 * If your are next to put index then it's
2984 * FIFO full condition
2985 */
da6971d8
AR		 2986 if ((get_block == put_block) &&
2987 (get_info.offset + 1) == put_info.offset) {
0425b46a 2988 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
d44570e4 2989 ring_data->dev->name);
da6971d8
AR		 2990 break;
2991 }
d44570e4 2992 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
20346722 2993 if (skb == NULL) {
2994 DBG_PRINT(ERR_DBG, "%s: The skb is ",
0425b46a 2995 ring_data->dev->name);
20346722 2996 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
f61e0a35 2997 return 0;
1da177e4 2998 }
0425b46a 2999 if (ring_data->rxd_mode == RXD_MODE_1) {
d44570e4 3000 rxdp1 = (struct RxD1 *)rxdp;
0425b46a 3001 pci_unmap_single(ring_data->pdev, (dma_addr_t)
d44570e4
JP		 3002 rxdp1->Buffer0_ptr,
3003 ring_data->mtu +
3004 HEADER_ETHERNET_II_802_3_SIZE +
3005 HEADER_802_2_SIZE +
3006 HEADER_SNAP_SIZE,
3007 PCI_DMA_FROMDEVICE);
0425b46a 3008 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
d44570e4
JP		 3009 rxdp3 = (struct RxD3 *)rxdp;
3010 pci_dma_sync_single_for_cpu(ring_data->pdev,
3011 (dma_addr_t)rxdp3->Buffer0_ptr,
3012 BUF0_LEN,
3013 PCI_DMA_FROMDEVICE);
3014 pci_unmap_single(ring_data->pdev,
3015 (dma_addr_t)rxdp3->Buffer2_ptr,
3016 ring_data->mtu + 4,
3017 PCI_DMA_FROMDEVICE);
da6971d8 3018 }
863c11a9 3019 prefetch(skb->data);
20346722 3020 rx_osm_handler(ring_data, rxdp);
3021 get_info.offset++;
da6971d8
AR		 3022 ring_data->rx_curr_get_info.offset = get_info.offset;
3023 rxdp = ring_data->rx_blocks[get_block].
d44570e4 3024 rxds[get_info.offset].virt_addr;
0425b46a 3025 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
20346722 3026 get_info.offset = 0;
da6971d8 3027 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 3028 get_block++;
da6971d8
AR		 3029 if (get_block == ring_data->block_count)
3030 get_block = 0;
3031 ring_data->rx_curr_get_info.block_index = get_block;
20346722 3032 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
3033 }
1da177e4 3034
f61e0a35
SH		 3035 if (ring_data->nic->config.napi) {
3036 budget--;
3037 napi_pkts++;
3038 if (!budget)
0425b46a
SH		 3039 break;
3040 }
20346722 3041 pkt_cnt++;
1da177e4
LT		 3042 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
3043 break;
3044 }
0425b46a 3045 if (ring_data->lro) {
7d3d0439 3046 /* Clear all LRO sessions before exiting */
d44570e4 3047 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 3048 struct lro *lro = &ring_data->lro0_n[i];
7d3d0439 3049 if (lro->in_use) {
0425b46a 3050 update_L3L4_header(ring_data->nic, lro);
cdb5bf02 3051 queue_rx_frame(lro->parent, lro->vlan_tag);
7d3d0439
RA		 3052 clear_lro_session(lro);
3053 }
3054 }
3055 }
d44570e4 3056 return napi_pkts;
1da177e4 3057}
20346722 3058
3059/**
1da177e4
LT		 3060 * tx_intr_handler - Transmit interrupt handler
3061 * @nic : device private variable
20346722 3062 * Description:
3063 * If an interrupt was raised to indicate DMA complete of the
3064 * Tx packet, this function is called. It identifies the last TxD
3065 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 3066 * DMA'ed into the NICs internal memory.
3067 * Return Value:
3068 * NONE
3069 */
3070
1ee6dd77 3071static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 3072{
1ee6dd77 3073 struct s2io_nic *nic = fifo_data->nic;
1ee6dd77 3074 struct tx_curr_get_info get_info, put_info;
3a3d5756 3075 struct sk_buff *skb = NULL;
1ee6dd77 3076 struct TxD *txdlp;
3a3d5756 3077 int pkt_cnt = 0;
2fda096d 3078 unsigned long flags = 0;
f9046eb3 3079 u8 err_mask;
ffb5df6c
JP		 3080 struct stat_block *stats = nic->mac_control.stats_info;
3081 struct swStat *swstats = &stats->sw_stat;
1da177e4 3082
2fda096d 3083 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
d44570e4 3084 return;
2fda096d 3085
20346722 3086 get_info = fifo_data->tx_curr_get_info;
1ee6dd77 3087 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
d44570e4
JP		 3088 txdlp = (struct TxD *)
3089 fifo_data->list_info[get_info.offset].list_virt_addr;
20346722 3090 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3091 (get_info.offset != put_info.offset) &&
3092 (txdlp->Host_Control)) {
3093 /* Check for TxD errors */
3094 if (txdlp->Control_1 & TXD_T_CODE) {
3095 unsigned long long err;
3096 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0 3097 if (err & 0x1) {
ffb5df6c 3098 swstats->parity_err_cnt++;
bd1034f0 3099 }
491976b2
SH		 3100
3101 /* update t_code statistics */
f9046eb3 3102 err_mask = err >> 48;
d44570e4
JP		 3103 switch (err_mask) {
3104 case 2:
ffb5df6c 3105 swstats->tx_buf_abort_cnt++;
491976b2
SH		 3106 break;
3107
d44570e4 3108 case 3:
ffb5df6c 3109 swstats->tx_desc_abort_cnt++;
491976b2
SH		 3110 break;
3111
d44570e4 3112 case 7:
ffb5df6c 3113 swstats->tx_parity_err_cnt++;
491976b2
SH		 3114 break;
3115
d44570e4 3116 case 10:
ffb5df6c 3117 swstats->tx_link_loss_cnt++;
491976b2
SH		 3118 break;
3119
d44570e4 3120 case 15:
ffb5df6c 3121 swstats->tx_list_proc_err_cnt++;
491976b2 3122 break;
d44570e4 3123 }
20346722 3124 }
1da177e4 3125
fed5eccd 3126 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3127 if (skb == NULL) {
2fda096d 3128 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
d44570e4 3129 DBG_PRINT(ERR_DBG, "%s: Null skb ", __func__);
20346722 3130 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3131 return;
3132 }
3a3d5756 3133 pkt_cnt++;
20346722 3134
20346722 3135 /* Updating the statistics block */
dc56e634 3136 nic->dev->stats.tx_bytes += skb->len;
ffb5df6c 3137 swstats->mem_freed += skb->truesize;
20346722 3138 dev_kfree_skb_irq(skb);
3139
3140 get_info.offset++;
863c11a9
AR		 3141 if (get_info.offset == get_info.fifo_len + 1)
3142 get_info.offset = 0;
d44570e4
JP		 3143 txdlp = (struct TxD *)
3144 fifo_data->list_info[get_info.offset].list_virt_addr;
3145 fifo_data->tx_curr_get_info.offset = get_info.offset;
1da177e4
LT		 3146 }
3147
3a3d5756 3148 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
2fda096d
SR		 3149
3150 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3151}
3152
bd1034f0
AR		 3153/**
3154 * s2io_mdio_write - Function to write in to MDIO registers
3155 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3156 * @addr : address value
3157 * @value : data value
3158 * @dev : pointer to net_device structure
3159 * Description:
3160 * This function is used to write values to the MDIO registers
3161 * NONE
3162 */
d44570e4
JP		 3163static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3164 struct net_device *dev)
bd1034f0 3165{
d44570e4 3166 u64 val64;
4cf1653a 3167 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3168 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0 3169
d44570e4
JP		 3170 /* address transaction */
3171 val64 = MDIO_MMD_INDX_ADDR(addr) |
3172 MDIO_MMD_DEV_ADDR(mmd_type) |
3173 MDIO_MMS_PRT_ADDR(0x0);
bd1034f0
AR		 3174 writeq(val64, &bar0->mdio_control);
3175 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3176 writeq(val64, &bar0->mdio_control);
3177 udelay(100);
3178
d44570e4
JP		 3179 /* Data transaction */
3180 val64 = MDIO_MMD_INDX_ADDR(addr) |
3181 MDIO_MMD_DEV_ADDR(mmd_type) |
3182 MDIO_MMS_PRT_ADDR(0x0) |
3183 MDIO_MDIO_DATA(value) |
3184 MDIO_OP(MDIO_OP_WRITE_TRANS);
bd1034f0
AR		 3185 writeq(val64, &bar0->mdio_control);
3186 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3187 writeq(val64, &bar0->mdio_control);
3188 udelay(100);
3189
d44570e4
JP		 3190 val64 = MDIO_MMD_INDX_ADDR(addr) |
3191 MDIO_MMD_DEV_ADDR(mmd_type) |
3192 MDIO_MMS_PRT_ADDR(0x0) |
3193 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3194 writeq(val64, &bar0->mdio_control);
3195 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3196 writeq(val64, &bar0->mdio_control);
3197 udelay(100);
bd1034f0
AR		 3198}
3199
3200/**
3201 * s2io_mdio_read - Function to write in to MDIO registers
3202 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3203 * @addr : address value
3204 * @dev : pointer to net_device structure
3205 * Description:
3206 * This function is used to read values to the MDIO registers
3207 * NONE
3208 */
3209static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3210{
3211 u64 val64 = 0x0;
3212 u64 rval64 = 0x0;
4cf1653a 3213 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 3214 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3215
3216 /* address transaction */
d44570e4
JP		 3217 val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3218 | MDIO_MMD_DEV_ADDR(mmd_type)
3219 | MDIO_MMS_PRT_ADDR(0x0));
bd1034f0
AR		 3220 writeq(val64, &bar0->mdio_control);
3221 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3222 writeq(val64, &bar0->mdio_control);
3223 udelay(100);
3224
3225 /* Data transaction */
d44570e4
JP		 3226 val64 = MDIO_MMD_INDX_ADDR(addr) |
3227 MDIO_MMD_DEV_ADDR(mmd_type) |
3228 MDIO_MMS_PRT_ADDR(0x0) |
3229 MDIO_OP(MDIO_OP_READ_TRANS);
bd1034f0
AR		 3230 writeq(val64, &bar0->mdio_control);
3231 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3232 writeq(val64, &bar0->mdio_control);
3233 udelay(100);
3234
3235 /* Read the value from regs */
3236 rval64 = readq(&bar0->mdio_control);
3237 rval64 = rval64 & 0xFFFF0000;
3238 rval64 = rval64 >> 16;
3239 return rval64;
3240}
d44570e4 3241
bd1034f0
AR		 3242/**
3243 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3244 * @counter : couter value to be updated
3245 * @flag : flag to indicate the status
3246 * @type : counter type
3247 * Description:
3248 * This function is to check the status of the xpak counters value
3249 * NONE
3250 */
3251
d44570e4
JP		 3252static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3253 u16 flag, u16 type)
bd1034f0
AR		 3254{
3255 u64 mask = 0x3;
3256 u64 val64;
3257 int i;
d44570e4 3258 for (i = 0; i < index; i++)
bd1034f0
AR		 3259 mask = mask << 0x2;
3260
d44570e4 3261 if (flag > 0) {
bd1034f0
AR		 3262 *counter = *counter + 1;
3263 val64 = *regs_stat & mask;
3264 val64 = val64 >> (index * 0x2);
3265 val64 = val64 + 1;
d44570e4
JP		 3266 if (val64 == 3) {
3267 switch (type) {
bd1034f0
AR		 3268 case 1:
3269 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3270 "service. Excessive temperatures may "
3271 "result in premature transceiver "
3272 "failure \n");
d44570e4 3273 break;
bd1034f0
AR		 3274 case 2:
3275 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3276 "service Excessive bias currents may "
3277 "indicate imminent laser diode "
3278 "failure \n");
d44570e4 3279 break;
bd1034f0
AR		 3280 case 3:
3281 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3282 "service Excessive laser output "
3283 "power may saturate far-end "
3284 "receiver\n");
d44570e4 3285 break;
bd1034f0 3286 default:
d44570e4
JP		 3287 DBG_PRINT(ERR_DBG,
3288 "Incorrect XPAK Alarm type\n");
bd1034f0
AR		 3289 }
3290 val64 = 0x0;
3291 }
3292 val64 = val64 << (index * 0x2);
3293 *regs_stat = (*regs_stat & (~mask)) | (val64);
3294
3295 } else {
3296 *regs_stat = *regs_stat & (~mask);
3297 }
3298}
3299
3300/**
3301 * s2io_updt_xpak_counter - Function to update the xpak counters
3302 * @dev : pointer to net_device struct
3303 * Description:
3304 * This function is to upate the status of the xpak counters value
3305 * NONE
3306 */
3307static void s2io_updt_xpak_counter(struct net_device *dev)
3308{
3309 u16 flag = 0x0;
3310 u16 type = 0x0;
3311 u16 val16 = 0x0;
3312 u64 val64 = 0x0;
3313 u64 addr = 0x0;
3314
4cf1653a 3315 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 3316 struct stat_block *stats = sp->mac_control.stats_info;
3317 struct xpakStat *xstats = &stats->xpak_stat;
bd1034f0
AR		 3318
3319 /* Check the communication with the MDIO slave */
40239396 3320 addr = MDIO_CTRL1;
bd1034f0 3321 val64 = 0x0;
40239396 3322 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
d44570e4 3323 if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
bd1034f0
AR		 3324 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3325 "Returned %llx\n", (unsigned long long)val64);
3326 return;
3327 }
3328
40239396 3329 /* Check for the expected value of control reg 1 */
d44570e4 3330 if (val64 != MDIO_CTRL1_SPEED10G) {
bd1034f0 3331 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
40239396
BH		 3332 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x%x\n",
3333 (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
bd1034f0
AR		 3334 return;
3335 }
3336
3337 /* Loading the DOM register to MDIO register */
3338 addr = 0xA100;
40239396
BH		 3339 s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3340 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3341
3342 /* Reading the Alarm flags */
3343 addr = 0xA070;
3344 val64 = 0x0;
40239396 3345 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0
AR		 3346
3347 flag = CHECKBIT(val64, 0x7);
3348 type = 1;
ffb5df6c
JP		 3349 s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3350 &xstats->xpak_regs_stat,
d44570e4 3351 0x0, flag, type);
bd1034f0 3352
d44570e4 3353 if (CHECKBIT(val64, 0x6))
ffb5df6c 3354 xstats->alarm_transceiver_temp_low++;
bd1034f0
AR		 3355
3356 flag = CHECKBIT(val64, 0x3);
3357 type = 2;
ffb5df6c
JP		 3358 s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3359 &xstats->xpak_regs_stat,
d44570e4 3360 0x2, flag, type);
bd1034f0 3361
d44570e4 3362 if (CHECKBIT(val64, 0x2))
ffb5df6c 3363 xstats->alarm_laser_bias_current_low++;
bd1034f0
AR		 3364
3365 flag = CHECKBIT(val64, 0x1);
3366 type = 3;
ffb5df6c
JP		 3367 s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3368 &xstats->xpak_regs_stat,
d44570e4 3369 0x4, flag, type);
bd1034f0 3370
d44570e4 3371 if (CHECKBIT(val64, 0x0))
ffb5df6c 3372 xstats->alarm_laser_output_power_low++;
bd1034f0
AR		 3373
3374 /* Reading the Warning flags */
3375 addr = 0xA074;
3376 val64 = 0x0;
40239396 3377 val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
bd1034f0 3378
d44570e4 3379 if (CHECKBIT(val64, 0x7))
ffb5df6c 3380 xstats->warn_transceiver_temp_high++;
bd1034f0 3381
d44570e4 3382 if (CHECKBIT(val64, 0x6))
ffb5df6c 3383 xstats->warn_transceiver_temp_low++;
bd1034f0 3384
d44570e4 3385 if (CHECKBIT(val64, 0x3))
ffb5df6c 3386 xstats->warn_laser_bias_current_high++;
bd1034f0 3387
d44570e4 3388 if (CHECKBIT(val64, 0x2))
ffb5df6c 3389 xstats->warn_laser_bias_current_low++;
bd1034f0 3390
d44570e4 3391 if (CHECKBIT(val64, 0x1))
ffb5df6c 3392 xstats->warn_laser_output_power_high++;
bd1034f0 3393
d44570e4 3394 if (CHECKBIT(val64, 0x0))
ffb5df6c 3395 xstats->warn_laser_output_power_low++;
bd1034f0
AR		 3396}
3397
20346722 3398/**
1da177e4 3399 * wait_for_cmd_complete - waits for a command to complete.
20346722 3400 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3401 * s2io_nic structure.
20346722 3402 * Description: Function that waits for a command to Write into RMAC
3403 * ADDR DATA registers to be completed and returns either success or
3404 * error depending on whether the command was complete or not.
1da177e4
LT		 3405 * Return value:
3406 * SUCCESS on success and FAILURE on failure.
3407 */
3408
9fc93a41 3409static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
d44570e4 3410 int bit_state)
1da177e4 3411{
9fc93a41 3412 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3413 u64 val64;
3414
9fc93a41
SS		 3415 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3416 return FAILURE;
3417
3418 do {
c92ca04b 3419 val64 = readq(addr);
9fc93a41
SS		 3420 if (bit_state == S2IO_BIT_RESET) {
3421 if (!(val64 & busy_bit)) {
3422 ret = SUCCESS;
3423 break;
3424 }
3425 } else {
3426 if (!(val64 & busy_bit)) {
3427 ret = SUCCESS;
3428 break;
3429 }
1da177e4 3430 }
c92ca04b 3431
d44570e4 3432 if (in_interrupt())
9fc93a41 3433 mdelay(delay);
c92ca04b 3434 else
9fc93a41 3435 msleep(delay);
c92ca04b 3436
9fc93a41
SS		 3437 if (++cnt >= 10)
3438 delay = 50;
3439 } while (cnt < 20);
1da177e4
LT		 3440 return ret;
3441}
19a60522
SS		 3442/*
3443 * check_pci_device_id - Checks if the device id is supported
3444 * @id : device id
3445 * Description: Function to check if the pci device id is supported by driver.
3446 * Return value: Actual device id if supported else PCI_ANY_ID
3447 */
3448static u16 check_pci_device_id(u16 id)
3449{
3450 switch (id) {
3451 case PCI_DEVICE_ID_HERC_WIN:
3452 case PCI_DEVICE_ID_HERC_UNI:
3453 return XFRAME_II_DEVICE;
3454 case PCI_DEVICE_ID_S2IO_UNI:
3455 case PCI_DEVICE_ID_S2IO_WIN:
3456 return XFRAME_I_DEVICE;
3457 default:
3458 return PCI_ANY_ID;
3459 }
3460}
1da177e4 3461
20346722 3462/**
3463 * s2io_reset - Resets the card.
1da177e4
LT		 3464 * @sp : private member of the device structure.
3465 * Description: Function to Reset the card. This function then also
20346722 3466 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3467 * the card reset also resets the configuration space.
3468 * Return value:
3469 * void.
3470 */
3471
d44570e4 3472static void s2io_reset(struct s2io_nic *sp)
1da177e4 3473{
1ee6dd77 3474 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3475 u64 val64;
5e25b9dd 3476 u16 subid, pci_cmd;
19a60522
SS		 3477 int i;
3478 u16 val16;
491976b2
SH		 3479 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3480 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
ffb5df6c
JP		 3481 struct stat_block *stats;
3482 struct swStat *swstats;
491976b2 3483
d44570e4
JP		 3484 DBG_PRINT(INIT_DBG, "%s - Resetting XFrame card %s\n",
3485 __func__, sp->dev->name);
1da177e4 3486
0b1f7ebe 3487 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3488 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3489
1da177e4
LT		 3490 val64 = SW_RESET_ALL;
3491 writeq(val64, &bar0->sw_reset);
d44570e4 3492 if (strstr(sp->product_name, "CX4"))
c92ca04b 3493 msleep(750);
19a60522
SS		 3494 msleep(250);
3495 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3496
19a60522
SS		 3497 /* Restore the PCI state saved during initialization. */
3498 pci_restore_state(sp->pdev);
3499 pci_read_config_word(sp->pdev, 0x2, &val16);
3500 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3501 break;
3502 msleep(200);
3503 }
1da177e4 3504
d44570e4
JP		 3505 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3506 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
19a60522
SS		 3507
3508 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3509
3510 s2io_init_pci(sp);
1da177e4 3511
20346722 3512 /* Set swapper to enable I/O register access */
3513 s2io_set_swapper(sp);
3514
faa4f796
SH		 3515 /* restore mac_addr entries */
3516 do_s2io_restore_unicast_mc(sp);
3517
cc6e7c44
RA		 3518 /* Restore the MSIX table entries from local variables */
3519 restore_xmsi_data(sp);
3520
5e25b9dd 3521 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3522 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3523 /* Clear "detected parity error" bit */
303bcb4b 3524 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3525
303bcb4b 3526 /* Clearing PCIX Ecc status register */
3527 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3528
303bcb4b 3529 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3530 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3531 }
5e25b9dd 3532
20346722 3533 /* Reset device statistics maintained by OS */
d44570e4 3534 memset(&sp->stats, 0, sizeof(struct net_device_stats));
8a4bdbaa 3535
ffb5df6c
JP		 3536 stats = sp->mac_control.stats_info;
3537 swstats = &stats->sw_stat;
3538
491976b2 3539 /* save link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3540 up_cnt = swstats->link_up_cnt;
3541 down_cnt = swstats->link_down_cnt;
3542 up_time = swstats->link_up_time;
3543 down_time = swstats->link_down_time;
3544 reset_cnt = swstats->soft_reset_cnt;
3545 mem_alloc_cnt = swstats->mem_allocated;
3546 mem_free_cnt = swstats->mem_freed;
3547 watchdog_cnt = swstats->watchdog_timer_cnt;
3548
3549 memset(stats, 0, sizeof(struct stat_block));
3550
491976b2 3551 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
ffb5df6c
JP		 3552 swstats->link_up_cnt = up_cnt;
3553 swstats->link_down_cnt = down_cnt;
3554 swstats->link_up_time = up_time;
3555 swstats->link_down_time = down_time;
3556 swstats->soft_reset_cnt = reset_cnt;
3557 swstats->mem_allocated = mem_alloc_cnt;
3558 swstats->mem_freed = mem_free_cnt;
3559 swstats->watchdog_timer_cnt = watchdog_cnt;
20346722 3560
1da177e4
LT		 3561 /* SXE-002: Configure link and activity LED to turn it off */
3562 subid = sp->pdev->subsystem_device;
541ae68f 3563 if (((subid & 0xFF) >= 0x07) &&
3564 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3565 val64 = readq(&bar0->gpio_control);
3566 val64 |= 0x0000800000000000ULL;
3567 writeq(val64, &bar0->gpio_control);
3568 val64 = 0x0411040400000000ULL;
509a2671 3569 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3570 }
3571
541ae68f 3572 /*
3573 * Clear spurious ECC interrupts that would have occured on
3574 * XFRAME II cards after reset.
3575 */
3576 if (sp->device_type == XFRAME_II_DEVICE) {
3577 val64 = readq(&bar0->pcc_err_reg);
3578 writeq(val64, &bar0->pcc_err_reg);
3579 }
3580
f957bcf0 3581 sp->device_enabled_once = false;
1da177e4
LT		 3582}
3583
3584/**
20346722 3585 * s2io_set_swapper - to set the swapper controle on the card
3586 * @sp : private member of the device structure,
1da177e4 3587 * pointer to the s2io_nic structure.
20346722 3588 * Description: Function to set the swapper control on the card
1da177e4
LT		 3589 * correctly depending on the 'endianness' of the system.
3590 * Return value:
3591 * SUCCESS on success and FAILURE on failure.
3592 */
3593
d44570e4 3594static int s2io_set_swapper(struct s2io_nic *sp)
1da177e4
LT		 3595{
3596 struct net_device *dev = sp->dev;
1ee6dd77 3597 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3598 u64 val64, valt, valr;
3599
20346722 3600 /*
1da177e4
LT		 3601 * Set proper endian settings and verify the same by reading
3602 * the PIF Feed-back register.
3603 */
3604
3605 val64 = readq(&bar0->pif_rd_swapper_fb);
3606 if (val64 != 0x0123456789ABCDEFULL) {
3607 int i = 0;
3608 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3609 0x8100008181000081ULL, /* FE=1, SE=0 */
3610 0x4200004242000042ULL, /* FE=0, SE=1 */
3611 0}; /* FE=0, SE=0 */
3612
d44570e4 3613 while (i < 4) {
1da177e4
LT		 3614 writeq(value[i], &bar0->swapper_ctrl);
3615 val64 = readq(&bar0->pif_rd_swapper_fb);
3616 if (val64 == 0x0123456789ABCDEFULL)
3617 break;
3618 i++;
3619 }
3620 if (i == 4) {
3621 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
d44570e4 3622 dev->name);
1da177e4 3623 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
d44570e4 3624 (unsigned long long)val64);
1da177e4
LT		 3625 return FAILURE;
3626 }
3627 valr = value[i];
3628 } else {
3629 valr = readq(&bar0->swapper_ctrl);
3630 }
3631
3632 valt = 0x0123456789ABCDEFULL;
3633 writeq(valt, &bar0->xmsi_address);
3634 val64 = readq(&bar0->xmsi_address);
3635
d44570e4 3636 if (val64 != valt) {
1da177e4
LT		 3637 int i = 0;
3638 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3639 0x0081810000818100ULL, /* FE=1, SE=0 */
3640 0x0042420000424200ULL, /* FE=0, SE=1 */
3641 0}; /* FE=0, SE=0 */
3642
d44570e4 3643 while (i < 4) {
1da177e4
LT		 3644 writeq((value[i] | valr), &bar0->swapper_ctrl);
3645 writeq(valt, &bar0->xmsi_address);
3646 val64 = readq(&bar0->xmsi_address);
d44570e4 3647 if (val64 == valt)
1da177e4
LT		 3648 break;
3649 i++;
3650 }
d44570e4 3651 if (i == 4) {
20346722 3652 unsigned long long x = val64;
1da177e4 3653 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3654 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3655 return FAILURE;
3656 }
3657 }
3658 val64 = readq(&bar0->swapper_ctrl);
3659 val64 &= 0xFFFF000000000000ULL;
3660
d44570e4 3661#ifdef __BIG_ENDIAN
20346722 3662 /*
3663 * The device by default set to a big endian format, so a
1da177e4
LT		 3664 * big endian driver need not set anything.
3665 */
3666 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3667 SWAPPER_CTRL_TXP_SE |
3668 SWAPPER_CTRL_TXD_R_FE |
3669 SWAPPER_CTRL_TXD_W_FE |
3670 SWAPPER_CTRL_TXF_R_FE |
3671 SWAPPER_CTRL_RXD_R_FE |
3672 SWAPPER_CTRL_RXD_W_FE |
3673 SWAPPER_CTRL_RXF_W_FE |
3674 SWAPPER_CTRL_XMSI_FE |
3675 SWAPPER_CTRL_STATS_FE |
3676 SWAPPER_CTRL_STATS_SE);
eaae7f72 3677 if (sp->config.intr_type == INTA)
cc6e7c44 3678 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3679 writeq(val64, &bar0->swapper_ctrl);
3680#else
20346722 3681 /*
1da177e4 3682 * Initially we enable all bits to make it accessible by the
20346722 3683 * driver, then we selectively enable only those bits that
1da177e4
LT		 3684 * we want to set.
3685 */
3686 val64 |= (SWAPPER_CTRL_TXP_FE |
d44570e4
JP		 3687 SWAPPER_CTRL_TXP_SE |
3688 SWAPPER_CTRL_TXD_R_FE |
3689 SWAPPER_CTRL_TXD_R_SE |
3690 SWAPPER_CTRL_TXD_W_FE |
3691 SWAPPER_CTRL_TXD_W_SE |
3692 SWAPPER_CTRL_TXF_R_FE |
3693 SWAPPER_CTRL_RXD_R_FE |
3694 SWAPPER_CTRL_RXD_R_SE |
3695 SWAPPER_CTRL_RXD_W_FE |
3696 SWAPPER_CTRL_RXD_W_SE |
3697 SWAPPER_CTRL_RXF_W_FE |
3698 SWAPPER_CTRL_XMSI_FE |
3699 SWAPPER_CTRL_STATS_FE |
3700 SWAPPER_CTRL_STATS_SE);
eaae7f72 3701 if (sp->config.intr_type == INTA)
cc6e7c44 3702 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3703 writeq(val64, &bar0->swapper_ctrl);
3704#endif
3705 val64 = readq(&bar0->swapper_ctrl);
3706
20346722 3707 /*
3708 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3709 * feedback register.
3710 */
3711 val64 = readq(&bar0->pif_rd_swapper_fb);
3712 if (val64 != 0x0123456789ABCDEFULL) {
3713 /* Endian settings are incorrect, calls for another dekko. */
3714 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3715 dev->name);
3716 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
d44570e4 3717 (unsigned long long)val64);
1da177e4
LT		 3718 return FAILURE;
3719 }
3720
3721 return SUCCESS;
3722}
3723
1ee6dd77 3724static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3725{
1ee6dd77 3726 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3727 u64 val64;
3728 int ret = 0, cnt = 0;
3729
3730 do {
3731 val64 = readq(&bar0->xmsi_access);
b7b5a128 3732 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3733 break;
3734 mdelay(1);
3735 cnt++;
d44570e4 3736 } while (cnt < 5);
cc6e7c44
RA		 3737 if (cnt == 5) {
3738 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3739 ret = 1;
3740 }
3741
3742 return ret;
3743}
3744
1ee6dd77 3745static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3746{
1ee6dd77 3747 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3748 u64 val64;
f61e0a35
SH		 3749 int i, msix_index;
3750
f61e0a35
SH		 3751 if (nic->device_type == XFRAME_I_DEVICE)
3752 return;
cc6e7c44 3753
d44570e4
JP		 3754 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3755 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
cc6e7c44
RA		 3756 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3757 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
f61e0a35 3758 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3759 writeq(val64, &bar0->xmsi_access);
f61e0a35 3760 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3761 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3762 continue;
3763 }
3764 }
3765}
3766
1ee6dd77 3767static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3768{
1ee6dd77 3769 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44 3770 u64 val64, addr, data;
f61e0a35
SH		 3771 int i, msix_index;
3772
3773 if (nic->device_type == XFRAME_I_DEVICE)
3774 return;
cc6e7c44
RA		 3775
3776 /* Store and display */
d44570e4
JP		 3777 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3778 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
f61e0a35 3779 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
cc6e7c44 3780 writeq(val64, &bar0->xmsi_access);
f61e0a35 3781 if (wait_for_msix_trans(nic, msix_index)) {
b39d66a8 3782 DBG_PRINT(ERR_DBG, "failed in %s\n", __func__);
cc6e7c44
RA		 3783 continue;
3784 }
3785 addr = readq(&bar0->xmsi_address);
3786 data = readq(&bar0->xmsi_data);
3787 if (addr && data) {
3788 nic->msix_info[i].addr = addr;
3789 nic->msix_info[i].data = data;
3790 }
3791 }
3792}
3793
1ee6dd77 3794static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3795{
1ee6dd77 3796 struct XENA_dev_config __iomem *bar0 = nic->bar0;
ac731ab6 3797 u64 rx_mat;
cc6e7c44
RA		 3798 u16 msi_control; /* Temp variable */
3799 int ret, i, j, msix_indx = 1;
4f870320 3800 int size;
ffb5df6c
JP		 3801 struct stat_block *stats = nic->mac_control.stats_info;
3802 struct swStat *swstats = &stats->sw_stat;
cc6e7c44 3803
4f870320 3804 size = nic->num_entries * sizeof(struct msix_entry);
44364a03 3805 nic->entries = kzalloc(size, GFP_KERNEL);
bd684e43 3806 if (!nic->entries) {
d44570e4
JP		 3807 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3808 __func__);
ffb5df6c 3809 swstats->mem_alloc_fail_cnt++;
cc6e7c44
RA		 3810 return -ENOMEM;
3811 }
ffb5df6c 3812 swstats->mem_allocated += size;
f61e0a35 3813
4f870320 3814 size = nic->num_entries * sizeof(struct s2io_msix_entry);
44364a03 3815 nic->s2io_entries = kzalloc(size, GFP_KERNEL);
bd684e43 3816 if (!nic->s2io_entries) {
8a4bdbaa 3817 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
d44570e4 3818 __func__);
ffb5df6c 3819 swstats->mem_alloc_fail_cnt++;
cc6e7c44 3820 kfree(nic->entries);
ffb5df6c 3821 swstats->mem_freed
f61e0a35 3822 += (nic->num_entries * sizeof(struct msix_entry));
cc6e7c44
RA		 3823 return -ENOMEM;
3824 }
ffb5df6c 3825 swstats->mem_allocated += size;
cc6e7c44 3826
ac731ab6
SH		 3827 nic->entries[0].entry = 0;
3828 nic->s2io_entries[0].entry = 0;
3829 nic->s2io_entries[0].in_use = MSIX_FLG;
3830 nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3831 nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3832
f61e0a35
SH		 3833 for (i = 1; i < nic->num_entries; i++) {
3834 nic->entries[i].entry = ((i - 1) * 8) + 1;
3835 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
cc6e7c44
RA		 3836 nic->s2io_entries[i].arg = NULL;
3837 nic->s2io_entries[i].in_use = 0;
3838 }
3839
8a4bdbaa 3840 rx_mat = readq(&bar0->rx_mat);
f61e0a35 3841 for (j = 0; j < nic->config.rx_ring_num; j++) {
8a4bdbaa 3842 rx_mat |= RX_MAT_SET(j, msix_indx);
f61e0a35
SH		 3843 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3844 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3845 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3846 msix_indx += 8;
cc6e7c44 3847 }
8a4bdbaa 3848 writeq(rx_mat, &bar0->rx_mat);
f61e0a35 3849 readq(&bar0->rx_mat);
cc6e7c44 3850
f61e0a35 3851 ret = pci_enable_msix(nic->pdev, nic->entries, nic->num_entries);
c92ca04b 3852 /* We fail init if error or we get less vectors than min required */
cc6e7c44 3853 if (ret) {
073a2436 3854 DBG_PRINT(ERR_DBG, "s2io: Enabling MSI-X failed\n");
cc6e7c44 3855 kfree(nic->entries);
ffb5df6c
JP		 3856 swstats->mem_freed += nic->num_entries *
3857 sizeof(struct msix_entry);
cc6e7c44 3858 kfree(nic->s2io_entries);
ffb5df6c
JP		 3859 swstats->mem_freed += nic->num_entries *
3860 sizeof(struct s2io_msix_entry);
cc6e7c44
RA		 3861 nic->entries = NULL;
3862 nic->s2io_entries = NULL;
3863 return -ENOMEM;
3864 }
3865
3866 /*
3867 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3868 * in the herc NIC. (Temp change, needs to be removed later)
3869 */
3870 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3871 msi_control |= 0x1; /* Enable MSI */
3872 pci_write_config_word(nic->pdev, 0x42, msi_control);
3873
3874 return 0;
3875}
3876
8abc4d5b 3877/* Handle software interrupt used during MSI(X) test */
33390a70 3878static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3879{
3880 struct s2io_nic *sp = dev_id;
3881
3882 sp->msi_detected = 1;
3883 wake_up(&sp->msi_wait);
3884
3885 return IRQ_HANDLED;
3886}
3887
3888/* Test interrupt path by forcing a a software IRQ */
33390a70 3889static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3890{
3891 struct pci_dev *pdev = sp->pdev;
3892 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3893 int err;
3894 u64 val64, saved64;
3895
3896 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
d44570e4 3897 sp->name, sp);
8abc4d5b
SS		 3898 if (err) {
3899 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
d44570e4 3900 sp->dev->name, pci_name(pdev), pdev->irq);
8abc4d5b
SS		 3901 return err;
3902 }
3903
d44570e4 3904 init_waitqueue_head(&sp->msi_wait);
8abc4d5b
SS		 3905 sp->msi_detected = 0;
3906
3907 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3908 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3909 val64 |= SCHED_INT_CTRL_TIMER_EN;
3910 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3911 writeq(val64, &bar0->scheduled_int_ctrl);
3912
3913 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3914
3915 if (!sp->msi_detected) {
3916 /* MSI(X) test failed, go back to INTx mode */
2450022a 3917 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
d44570e4
JP		 3918 "using MSI(X) during test\n", sp->dev->name,
3919 pci_name(pdev));
8abc4d5b
SS		 3920
3921 err = -EOPNOTSUPP;
3922 }
3923
3924 free_irq(sp->entries[1].vector, sp);
3925
3926 writeq(saved64, &bar0->scheduled_int_ctrl);
3927
3928 return err;
3929}
18b2b7bd
SH		 3930
3931static void remove_msix_isr(struct s2io_nic *sp)
3932{
3933 int i;
3934 u16 msi_control;
3935
f61e0a35 3936 for (i = 0; i < sp->num_entries; i++) {
d44570e4 3937 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
18b2b7bd
SH		 3938 int vector = sp->entries[i].vector;
3939 void *arg = sp->s2io_entries[i].arg;
3940 free_irq(vector, arg);
3941 }
3942 }
3943
3944 kfree(sp->entries);
3945 kfree(sp->s2io_entries);
3946 sp->entries = NULL;
3947 sp->s2io_entries = NULL;
3948
3949 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3950 msi_control &= 0xFFFE; /* Disable MSI */
3951 pci_write_config_word(sp->pdev, 0x42, msi_control);
3952
3953 pci_disable_msix(sp->pdev);
3954}
3955
3956static void remove_inta_isr(struct s2io_nic *sp)
3957{
3958 struct net_device *dev = sp->dev;
3959
3960 free_irq(sp->pdev->irq, dev);
3961}
3962
1da177e4
LT		 3963/* ********************************************************* *
3964 * Functions defined below concern the OS part of the driver *
3965 * ********************************************************* */
3966
20346722 3967/**
1da177e4
LT		 3968 * s2io_open - open entry point of the driver
3969 * @dev : pointer to the device structure.
3970 * Description:
3971 * This function is the open entry point of the driver. It mainly calls a
3972 * function to allocate Rx buffers and inserts them into the buffer
20346722 3973 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3974 * Return value:
3975 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3976 * file on failure.
3977 */
3978
ac1f60db 3979static int s2io_open(struct net_device *dev)
1da177e4 3980{
4cf1653a 3981 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 3982 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3983 int err = 0;
3984
20346722 3985 /*
3986 * Make sure you have link off by default every time
1da177e4
LT		 3987 * Nic is initialized
3988 */
3989 netif_carrier_off(dev);
0b1f7ebe 3990 sp->last_link_state = 0;
1da177e4
LT		 3991
3992 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3993 err = s2io_card_up(sp);
3994 if (err) {
1da177e4
LT		 3995 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3996 dev->name);
e6a8fee2 3997 goto hw_init_failed;
1da177e4
LT		 3998 }
3999
2fd37688 4000 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 4001 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 4002 s2io_card_down(sp);
20346722 4003 err = -ENODEV;
e6a8fee2 4004 goto hw_init_failed;
1da177e4 4005 }
3a3d5756 4006 s2io_start_all_tx_queue(sp);
1da177e4 4007 return 0;
20346722 4008
20346722 4009hw_init_failed:
eaae7f72 4010 if (sp->config.intr_type == MSI_X) {
491976b2 4011 if (sp->entries) {
cc6e7c44 4012 kfree(sp->entries);
ffb5df6c
JP		 4013 swstats->mem_freed += sp->num_entries *
4014 sizeof(struct msix_entry);
491976b2
SH		 4015 }
4016 if (sp->s2io_entries) {
cc6e7c44 4017 kfree(sp->s2io_entries);
ffb5df6c
JP		 4018 swstats->mem_freed += sp->num_entries *
4019 sizeof(struct s2io_msix_entry);
491976b2 4020 }
cc6e7c44 4021 }
20346722 4022 return err;
1da177e4
LT		 4023}
4024
4025/**
4026 * s2io_close -close entry point of the driver
4027 * @dev : device pointer.
4028 * Description:
4029 * This is the stop entry point of the driver. It needs to undo exactly
4030 * whatever was done by the open entry point,thus it's usually referred to
4031 * as the close function.Among other things this function mainly stops the
4032 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
4033 * Return value:
4034 * 0 on success and an appropriate (-)ve integer as defined in errno.h
4035 * file on failure.
4036 */
4037
ac1f60db 4038static int s2io_close(struct net_device *dev)
1da177e4 4039{
4cf1653a 4040 struct s2io_nic *sp = netdev_priv(dev);
faa4f796
SH		 4041 struct config_param *config = &sp->config;
4042 u64 tmp64;
4043 int offset;
cc6e7c44 4044
9f74ffde 4045 /* Return if the device is already closed *
d44570e4
JP		 4046 * Can happen when s2io_card_up failed in change_mtu *
4047 */
9f74ffde
SH		 4048 if (!is_s2io_card_up(sp))
4049 return 0;
4050
3a3d5756 4051 s2io_stop_all_tx_queue(sp);
faa4f796
SH		 4052 /* delete all populated mac entries */
4053 for (offset = 1; offset < config->max_mc_addr; offset++) {
4054 tmp64 = do_s2io_read_unicast_mc(sp, offset);
4055 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
4056 do_s2io_delete_unicast_mc(sp, tmp64);
4057 }
4058
e6a8fee2 4059 s2io_card_down(sp);
cc6e7c44 4060
1da177e4
LT		 4061 return 0;
4062}
4063
4064/**
4065 * s2io_xmit - Tx entry point of te driver
4066 * @skb : the socket buffer containing the Tx data.
4067 * @dev : device pointer.
4068 * Description :
4069 * This function is the Tx entry point of the driver. S2IO NIC supports
4070 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4071 * NOTE: when device cant queue the pkt,just the trans_start variable will
4072 * not be upadted.
4073 * Return value:
4074 * 0 on success & 1 on failure.
4075 */
4076
ac1f60db 4077static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4078{
4cf1653a 4079 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 4080 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4081 register u64 val64;
1ee6dd77
RB		 4082 struct TxD *txdp;
4083 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4084 unsigned long flags = 0;
be3a6b02 4085 u16 vlan_tag = 0;
2fda096d 4086 struct fifo_info *fifo = NULL;
6cfc482b 4087 int do_spin_lock = 1;
75c30b13 4088 int offload_type;
6cfc482b 4089 int enable_per_list_interrupt = 0;
ffb5df6c
JP		 4090 struct config_param *config = &sp->config;
4091 struct mac_info *mac_control = &sp->mac_control;
4092 struct stat_block *stats = mac_control->stats_info;
4093 struct swStat *swstats = &stats->sw_stat;
1da177e4 4094
20346722 4095 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4096
4097 if (unlikely(skb->len <= 0)) {
4098 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4099 dev_kfree_skb_any(skb);
6ed10654 4100 return NETDEV_TX_OK;
2fda096d 4101 }
491976b2 4102
92b84437 4103 if (!is_s2io_card_up(sp)) {
20346722 4104 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4105 dev->name);
20346722 4106 dev_kfree_skb(skb);
6ed10654 4107 return NETDEV_TX_OK;
1da177e4
LT		 4108 }
4109
4110 queue = 0;
3a3d5756 4111 if (sp->vlgrp && vlan_tx_tag_present(skb))
be3a6b02 4112 vlan_tag = vlan_tx_tag_get(skb);
6cfc482b
SH		 4113 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4114 if (skb->protocol == htons(ETH_P_IP)) {
4115 struct iphdr *ip;
4116 struct tcphdr *th;
4117 ip = ip_hdr(skb);
4118
4119 if ((ip->frag_off & htons(IP_OFFSET|IP_MF)) == 0) {
4120 th = (struct tcphdr *)(((unsigned char *)ip) +
d44570e4 4121 ip->ihl*4);
6cfc482b
SH		 4122
4123 if (ip->protocol == IPPROTO_TCP) {
4124 queue_len = sp->total_tcp_fifos;
4125 queue = (ntohs(th->source) +
d44570e4
JP		 4126 ntohs(th->dest)) &
4127 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4128 if (queue >= queue_len)
4129 queue = queue_len - 1;
4130 } else if (ip->protocol == IPPROTO_UDP) {
4131 queue_len = sp->total_udp_fifos;
4132 queue = (ntohs(th->source) +
d44570e4
JP		 4133 ntohs(th->dest)) &
4134 sp->fifo_selector[queue_len - 1];
6cfc482b
SH		 4135 if (queue >= queue_len)
4136 queue = queue_len - 1;
4137 queue += sp->udp_fifo_idx;
4138 if (skb->len > 1024)
4139 enable_per_list_interrupt = 1;
4140 do_spin_lock = 0;
4141 }
4142 }
4143 }
4144 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4145 /* get fifo number based on skb->priority value */
4146 queue = config->fifo_mapping
d44570e4 4147 [skb->priority & (MAX_TX_FIFOS - 1)];
6cfc482b 4148 fifo = &mac_control->fifos[queue];
3a3d5756 4149
6cfc482b
SH		 4150 if (do_spin_lock)
4151 spin_lock_irqsave(&fifo->tx_lock, flags);
4152 else {
4153 if (unlikely(!spin_trylock_irqsave(&fifo->tx_lock, flags)))
4154 return NETDEV_TX_LOCKED;
4155 }
be3a6b02 4156
3a3d5756
SH		 4157 if (sp->config.multiq) {
4158 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4159 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4160 return NETDEV_TX_BUSY;
4161 }
b19fa1fa 4162 } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
3a3d5756
SH		 4163 if (netif_queue_stopped(dev)) {
4164 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4165 return NETDEV_TX_BUSY;
4166 }
4167 }
4168
d44570e4
JP		 4169 put_off = (u16)fifo->tx_curr_put_info.offset;
4170 get_off = (u16)fifo->tx_curr_get_info.offset;
4171 txdp = (struct TxD *)fifo->list_info[put_off].list_virt_addr;
20346722 4172
2fda096d 4173 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4174 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4175 if (txdp->Host_Control ||
d44570e4 4176 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4177 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3a3d5756 4178 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4179 dev_kfree_skb(skb);
2fda096d 4180 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4181 return NETDEV_TX_OK;
1da177e4 4182 }
0b1f7ebe 4183
75c30b13 4184 offload_type = s2io_offload_type(skb);
75c30b13 4185 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4186 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4187 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4188 }
84fa7933 4189 if (skb->ip_summed == CHECKSUM_PARTIAL) {
d44570e4
JP		 4190 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4191 TXD_TX_CKO_TCP_EN |
4192 TXD_TX_CKO_UDP_EN);
1da177e4 4193 }
fed5eccd
AR		 4194 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4195 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4196 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
6cfc482b
SH		 4197 if (enable_per_list_interrupt)
4198 if (put_off & (queue_len >> 5))
4199 txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
3a3d5756 4200 if (vlan_tag) {
be3a6b02 4201 txdp->Control_2 |= TXD_VLAN_ENABLE;
4202 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4203 }
4204
fed5eccd 4205 frg_len = skb->len - skb->data_len;
75c30b13 4206 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4207 int ufo_size;
4208
75c30b13 4209 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4210 ufo_size &= ~7;
4211 txdp->Control_1 |= TXD_UFO_EN;
4212 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4213 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4214#ifdef __BIG_ENDIAN
3459feb8 4215 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
2fda096d 4216 fifo->ufo_in_band_v[put_off] =
d44570e4 4217 (__force u64)skb_shinfo(skb)->ip6_frag_id;
fed5eccd 4218#else
2fda096d 4219 fifo->ufo_in_band_v[put_off] =
d44570e4 4220 (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
fed5eccd 4221#endif
2fda096d 4222 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4223 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
d44570e4
JP		 4224 fifo->ufo_in_band_v,
4225 sizeof(u64),
4226 PCI_DMA_TODEVICE);
8d8bb39b 4227 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25 4228 goto pci_map_failed;
fed5eccd 4229 txdp++;
fed5eccd 4230 }
1da177e4 4231
d44570e4
JP		 4232 txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4233 frg_len, PCI_DMA_TODEVICE);
8d8bb39b 4234 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
491abf25
VP		 4235 goto pci_map_failed;
4236
d44570e4 4237 txdp->Host_Control = (unsigned long)skb;
fed5eccd 4238 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4239 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4240 txdp->Control_1 |= TXD_UFO_EN;
4241
4242 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4243 /* For fragmented SKB. */
4244 for (i = 0; i < frg_cnt; i++) {
4245 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe 4246 /* A '0' length fragment will be ignored */
4247 if (!frag->size)
4248 continue;
1da177e4 4249 txdp++;
d44570e4
JP		 4250 txdp->Buffer_Pointer = (u64)pci_map_page(sp->pdev, frag->page,
4251 frag->page_offset,
4252 frag->size,
4253 PCI_DMA_TODEVICE);
efd51b5c 4254 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4255 if (offload_type == SKB_GSO_UDP)
fed5eccd 4256 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4257 }
4258 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4259
75c30b13 4260 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4261 frg_cnt++; /* as Txd0 was used for inband header */
4262
1da177e4 4263 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4264 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4265 writeq(val64, &tx_fifo->TxDL_Pointer);
4266
4267 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4268 TX_FIFO_LAST_LIST);
75c30b13 4269 if (offload_type)
fed5eccd 4270 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4271
1da177e4
LT		 4272 writeq(val64, &tx_fifo->List_Control);
4273
303bcb4b 4274 mmiowb();
4275
1da177e4 4276 put_off++;
2fda096d 4277 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4278 put_off = 0;
2fda096d 4279 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4280
4281 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4282 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
ffb5df6c 4283 swstats->fifo_full_cnt++;
1da177e4
LT		 4284 DBG_PRINT(TX_DBG,
4285 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4286 put_off, get_off);
3a3d5756 4287 s2io_stop_tx_queue(sp, fifo->fifo_no);
1da177e4 4288 }
ffb5df6c 4289 swstats->mem_allocated += skb->truesize;
2fda096d 4290 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4291
f6f4bfa3
SH		 4292 if (sp->config.intr_type == MSI_X)
4293 tx_intr_handler(fifo);
4294
6ed10654 4295 return NETDEV_TX_OK;
ffb5df6c 4296
491abf25 4297pci_map_failed:
ffb5df6c 4298 swstats->pci_map_fail_cnt++;
3a3d5756 4299 s2io_stop_tx_queue(sp, fifo->fifo_no);
ffb5df6c 4300 swstats->mem_freed += skb->truesize;
491abf25 4301 dev_kfree_skb(skb);
2fda096d 4302 spin_unlock_irqrestore(&fifo->tx_lock, flags);
6ed10654 4303 return NETDEV_TX_OK;
1da177e4
LT		 4304}
4305
25fff88e 4306static void
4307s2io_alarm_handle(unsigned long data)
4308{
1ee6dd77 4309 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4310 struct net_device *dev = sp->dev;
25fff88e 4311
8116f3cf 4312 s2io_handle_errors(dev);
25fff88e 4313 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4314}
4315
7d12e780 4316static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4317{
1ee6dd77
RB		 4318 struct ring_info *ring = (struct ring_info *)dev_id;
4319 struct s2io_nic *sp = ring->nic;
f61e0a35 4320 struct XENA_dev_config __iomem *bar0 = sp->bar0;
cc6e7c44 4321
f61e0a35 4322 if (unlikely(!is_s2io_card_up(sp)))
92b84437 4323 return IRQ_HANDLED;
92b84437 4324
f61e0a35 4325 if (sp->config.napi) {
1a79d1c3
AV		 4326 u8 __iomem *addr = NULL;
4327 u8 val8 = 0;
f61e0a35 4328
1a79d1c3 4329 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
f61e0a35
SH		 4330 addr += (7 - ring->ring_no);
4331 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4332 writeb(val8, addr);
4333 val8 = readb(addr);
288379f0 4334 napi_schedule(&ring->napi);
f61e0a35
SH		 4335 } else {
4336 rx_intr_handler(ring, 0);
8d8bb39b 4337 s2io_chk_rx_buffers(sp, ring);
f61e0a35 4338 }
7d3d0439 4339
cc6e7c44
RA		 4340 return IRQ_HANDLED;
4341}
4342
7d12e780 4343static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4344{
ac731ab6
SH		 4345 int i;
4346 struct fifo_info *fifos = (struct fifo_info *)dev_id;
4347 struct s2io_nic *sp = fifos->nic;
4348 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4349 struct config_param *config = &sp->config;
4350 u64 reason;
cc6e7c44 4351
ac731ab6
SH		 4352 if (unlikely(!is_s2io_card_up(sp)))
4353 return IRQ_NONE;
4354
4355 reason = readq(&bar0->general_int_status);
4356 if (unlikely(reason == S2IO_MINUS_ONE))
4357 /* Nothing much can be done. Get out */
92b84437 4358 return IRQ_HANDLED;
92b84437 4359
01e16faa
SH		 4360 if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4361 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
ac731ab6 4362
01e16faa
SH		 4363 if (reason & GEN_INTR_TXPIC)
4364 s2io_txpic_intr_handle(sp);
ac731ab6 4365
01e16faa
SH		 4366 if (reason & GEN_INTR_TXTRAFFIC)
4367 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
ac731ab6 4368
01e16faa
SH		 4369 for (i = 0; i < config->tx_fifo_num; i++)
4370 tx_intr_handler(&fifos[i]);
ac731ab6 4371
01e16faa
SH		 4372 writeq(sp->general_int_mask, &bar0->general_int_mask);
4373 readl(&bar0->general_int_status);
4374 return IRQ_HANDLED;
4375 }
4376 /* The interrupt was not raised by us */
4377 return IRQ_NONE;
cc6e7c44 4378}
ac731ab6 4379
1ee6dd77 4380static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4381{
1ee6dd77 4382 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d 4383 u64 val64;
4384
4385 val64 = readq(&bar0->pic_int_status);
4386 if (val64 & PIC_INT_GPIO) {
4387 val64 = readq(&bar0->gpio_int_reg);
4388 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4389 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4390 /*
4391 * This is unstable state so clear both up/down
4392 * interrupt and adapter to re-evaluate the link state.
4393 */
d44570e4 4394 val64 |= GPIO_INT_REG_LINK_DOWN;
a371a07d 4395 val64 |= GPIO_INT_REG_LINK_UP;
4396 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4397 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4398 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4399 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4400 writeq(val64, &bar0->gpio_int_mask);
d44570e4 4401 } else if (val64 & GPIO_INT_REG_LINK_UP) {
c92ca04b 4402 val64 = readq(&bar0->adapter_status);
d44570e4 4403 /* Enable Adapter */
19a60522
SS		 4404 val64 = readq(&bar0->adapter_control);
4405 val64 |= ADAPTER_CNTL_EN;
4406 writeq(val64, &bar0->adapter_control);
4407 val64 |= ADAPTER_LED_ON;
4408 writeq(val64, &bar0->adapter_control);
4409 if (!sp->device_enabled_once)
4410 sp->device_enabled_once = 1;
c92ca04b 4411
19a60522
SS		 4412 s2io_link(sp, LINK_UP);
4413 /*
4414 * unmask link down interrupt and mask link-up
4415 * intr
4416 */
4417 val64 = readq(&bar0->gpio_int_mask);
4418 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4419 val64 |= GPIO_INT_MASK_LINK_UP;
4420 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4421
d44570e4 4422 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
c92ca04b 4423 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4424 s2io_link(sp, LINK_DOWN);
4425 /* Link is down so unmaks link up interrupt */
4426 val64 = readq(&bar0->gpio_int_mask);
4427 val64 &= ~GPIO_INT_MASK_LINK_UP;
4428 val64 |= GPIO_INT_MASK_LINK_DOWN;
4429 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4430
4431 /* turn off LED */
4432 val64 = readq(&bar0->adapter_control);
d44570e4 4433 val64 = val64 & (~ADAPTER_LED_ON);
ac1f90d6 4434 writeq(val64, &bar0->adapter_control);
a371a07d 4435 }
4436 }
c92ca04b 4437 val64 = readq(&bar0->gpio_int_mask);
a371a07d 4438}
4439
8116f3cf
SS		 4440/**
4441 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4442 * @value: alarm bits
4443 * @addr: address value
4444 * @cnt: counter variable
4445 * Description: Check for alarm and increment the counter
4446 * Return Value:
4447 * 1 - if alarm bit set
4448 * 0 - if alarm bit is not set
4449 */
d44570e4
JP		 4450static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4451 unsigned long long *cnt)
8116f3cf
SS		 4452{
4453 u64 val64;
4454 val64 = readq(addr);
d44570e4 4455 if (val64 & value) {
8116f3cf
SS		 4456 writeq(val64, addr);
4457 (*cnt)++;
4458 return 1;
4459 }
4460 return 0;
4461
4462}
4463
4464/**
4465 * s2io_handle_errors - Xframe error indication handler
4466 * @nic: device private variable
4467 * Description: Handle alarms such as loss of link, single or
4468 * double ECC errors, critical and serious errors.
4469 * Return Value:
4470 * NONE
4471 */
d44570e4 4472static void s2io_handle_errors(void *dev_id)
8116f3cf 4473{
d44570e4 4474 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4475 struct s2io_nic *sp = netdev_priv(dev);
8116f3cf 4476 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d44570e4 4477 u64 temp64 = 0, val64 = 0;
8116f3cf
SS		 4478 int i = 0;
4479
4480 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4481 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4482
92b84437 4483 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4484 return;
4485
4486 if (pci_channel_offline(sp->pdev))
4487 return;
4488
4489 memset(&sw_stat->ring_full_cnt, 0,
d44570e4 4490 sizeof(sw_stat->ring_full_cnt));
8116f3cf
SS		 4491
4492 /* Handling the XPAK counters update */
d44570e4 4493 if (stats->xpak_timer_count < 72000) {
8116f3cf
SS		 4494 /* waiting for an hour */
4495 stats->xpak_timer_count++;
4496 } else {
4497 s2io_updt_xpak_counter(dev);
4498 /* reset the count to zero */
4499 stats->xpak_timer_count = 0;
4500 }
4501
4502 /* Handling link status change error Intr */
4503 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4504 val64 = readq(&bar0->mac_rmac_err_reg);
4505 writeq(val64, &bar0->mac_rmac_err_reg);
4506 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4507 schedule_work(&sp->set_link_task);
4508 }
4509
4510 /* In case of a serious error, the device will be Reset. */
4511 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
d44570e4 4512 &sw_stat->serious_err_cnt))
8116f3cf
SS		 4513 goto reset;
4514
4515 /* Check for data parity error */
4516 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
d44570e4 4517 &sw_stat->parity_err_cnt))
8116f3cf
SS		 4518 goto reset;
4519
4520 /* Check for ring full counter */
4521 if (sp->device_type == XFRAME_II_DEVICE) {
4522 val64 = readq(&bar0->ring_bump_counter1);
d44570e4
JP		 4523 for (i = 0; i < 4; i++) {
4524 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf
SS		 4525 temp64 >>= 64 - ((i+1)*16);
4526 sw_stat->ring_full_cnt[i] += temp64;
4527 }
4528
4529 val64 = readq(&bar0->ring_bump_counter2);
d44570e4
JP		 4530 for (i = 0; i < 4; i++) {
4531 temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
8116f3cf 4532 temp64 >>= 64 - ((i+1)*16);
d44570e4 4533 sw_stat->ring_full_cnt[i+4] += temp64;
8116f3cf
SS		 4534 }
4535 }
4536
4537 val64 = readq(&bar0->txdma_int_status);
4538 /*check for pfc_err*/
4539 if (val64 & TXDMA_PFC_INT) {
d44570e4
JP		 4540 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4541 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4542 PFC_PCIX_ERR,
4543 &bar0->pfc_err_reg,
4544 &sw_stat->pfc_err_cnt))
8116f3cf 4545 goto reset;
d44570e4
JP		 4546 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4547 &bar0->pfc_err_reg,
4548 &sw_stat->pfc_err_cnt);
8116f3cf
SS		 4549 }
4550
4551 /*check for tda_err*/
4552 if (val64 & TXDMA_TDA_INT) {
d44570e4
JP		 4553 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4554 TDA_SM0_ERR_ALARM |
4555 TDA_SM1_ERR_ALARM,
4556 &bar0->tda_err_reg,
4557 &sw_stat->tda_err_cnt))
8116f3cf
SS		 4558 goto reset;
4559 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
d44570e4
JP		 4560 &bar0->tda_err_reg,
4561 &sw_stat->tda_err_cnt);
8116f3cf
SS		 4562 }
4563 /*check for pcc_err*/
4564 if (val64 & TXDMA_PCC_INT) {
d44570e4
JP		 4565 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4566 PCC_N_SERR | PCC_6_COF_OV_ERR |
4567 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4568 PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4569 PCC_TXB_ECC_DB_ERR,
4570 &bar0->pcc_err_reg,
4571 &sw_stat->pcc_err_cnt))
8116f3cf
SS		 4572 goto reset;
4573 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
d44570e4
JP		 4574 &bar0->pcc_err_reg,
4575 &sw_stat->pcc_err_cnt);
8116f3cf
SS		 4576 }
4577
4578 /*check for tti_err*/
4579 if (val64 & TXDMA_TTI_INT) {
d44570e4
JP		 4580 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4581 &bar0->tti_err_reg,
4582 &sw_stat->tti_err_cnt))
8116f3cf
SS		 4583 goto reset;
4584 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
d44570e4
JP		 4585 &bar0->tti_err_reg,
4586 &sw_stat->tti_err_cnt);
8116f3cf
SS		 4587 }
4588
4589 /*check for lso_err*/
4590 if (val64 & TXDMA_LSO_INT) {
d44570e4
JP		 4591 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4592 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4593 &bar0->lso_err_reg,
4594 &sw_stat->lso_err_cnt))
8116f3cf
SS		 4595 goto reset;
4596 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
d44570e4
JP		 4597 &bar0->lso_err_reg,
4598 &sw_stat->lso_err_cnt);
8116f3cf
SS		 4599 }
4600
4601 /*check for tpa_err*/
4602 if (val64 & TXDMA_TPA_INT) {
d44570e4
JP		 4603 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4604 &bar0->tpa_err_reg,
4605 &sw_stat->tpa_err_cnt))
8116f3cf 4606 goto reset;
d44570e4
JP		 4607 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4608 &bar0->tpa_err_reg,
4609 &sw_stat->tpa_err_cnt);
8116f3cf
SS		 4610 }
4611
4612 /*check for sm_err*/
4613 if (val64 & TXDMA_SM_INT) {
d44570e4
JP		 4614 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4615 &bar0->sm_err_reg,
4616 &sw_stat->sm_err_cnt))
8116f3cf
SS		 4617 goto reset;
4618 }
4619
4620 val64 = readq(&bar0->mac_int_status);
4621 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4622 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
d44570e4
JP		 4623 &bar0->mac_tmac_err_reg,
4624 &sw_stat->mac_tmac_err_cnt))
8116f3cf 4625 goto reset;
d44570e4
JP		 4626 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4627 TMAC_DESC_ECC_SG_ERR |
4628 TMAC_DESC_ECC_DB_ERR,
4629 &bar0->mac_tmac_err_reg,
4630 &sw_stat->mac_tmac_err_cnt);
8116f3cf
SS		 4631 }
4632
4633 val64 = readq(&bar0->xgxs_int_status);
4634 if (val64 & XGXS_INT_STATUS_TXGXS) {
4635 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
d44570e4
JP		 4636 &bar0->xgxs_txgxs_err_reg,
4637 &sw_stat->xgxs_txgxs_err_cnt))
8116f3cf
SS		 4638 goto reset;
4639 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
d44570e4
JP		 4640 &bar0->xgxs_txgxs_err_reg,
4641 &sw_stat->xgxs_txgxs_err_cnt);
8116f3cf
SS		 4642 }
4643
4644 val64 = readq(&bar0->rxdma_int_status);
4645 if (val64 & RXDMA_INT_RC_INT_M) {
d44570e4
JP		 4646 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4647 RC_FTC_ECC_DB_ERR |
4648 RC_PRCn_SM_ERR_ALARM |
4649 RC_FTC_SM_ERR_ALARM,
4650 &bar0->rc_err_reg,
4651 &sw_stat->rc_err_cnt))
8116f3cf 4652 goto reset;
d44570e4
JP		 4653 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4654 RC_FTC_ECC_SG_ERR |
4655 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4656 &sw_stat->rc_err_cnt);
4657 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4658 PRC_PCI_AB_WR_Rn |
4659 PRC_PCI_AB_F_WR_Rn,
4660 &bar0->prc_pcix_err_reg,
4661 &sw_stat->prc_pcix_err_cnt))
8116f3cf 4662 goto reset;
d44570e4
JP		 4663 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4664 PRC_PCI_DP_WR_Rn |
4665 PRC_PCI_DP_F_WR_Rn,
4666 &bar0->prc_pcix_err_reg,
4667 &sw_stat->prc_pcix_err_cnt);
8116f3cf
SS		 4668 }
4669
4670 if (val64 & RXDMA_INT_RPA_INT_M) {
4671 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
d44570e4
JP		 4672 &bar0->rpa_err_reg,
4673 &sw_stat->rpa_err_cnt))
8116f3cf
SS		 4674 goto reset;
4675 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
d44570e4
JP		 4676 &bar0->rpa_err_reg,
4677 &sw_stat->rpa_err_cnt);
8116f3cf
SS		 4678 }
4679
4680 if (val64 & RXDMA_INT_RDA_INT_M) {
d44570e4
JP		 4681 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4682 RDA_FRM_ECC_DB_N_AERR |
4683 RDA_SM1_ERR_ALARM |
4684 RDA_SM0_ERR_ALARM |
4685 RDA_RXD_ECC_DB_SERR,
4686 &bar0->rda_err_reg,
4687 &sw_stat->rda_err_cnt))
8116f3cf 4688 goto reset;
d44570e4
JP		 4689 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4690 RDA_FRM_ECC_SG_ERR |
4691 RDA_MISC_ERR |
4692 RDA_PCIX_ERR,
4693 &bar0->rda_err_reg,
4694 &sw_stat->rda_err_cnt);
8116f3cf
SS		 4695 }
4696
4697 if (val64 & RXDMA_INT_RTI_INT_M) {
d44570e4
JP		 4698 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4699 &bar0->rti_err_reg,
4700 &sw_stat->rti_err_cnt))
8116f3cf
SS		 4701 goto reset;
4702 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
d44570e4
JP		 4703 &bar0->rti_err_reg,
4704 &sw_stat->rti_err_cnt);
8116f3cf
SS		 4705 }
4706
4707 val64 = readq(&bar0->mac_int_status);
4708 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4709 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
d44570e4
JP		 4710 &bar0->mac_rmac_err_reg,
4711 &sw_stat->mac_rmac_err_cnt))
8116f3cf 4712 goto reset;
d44570e4
JP		 4713 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4714 RMAC_SINGLE_ECC_ERR |
4715 RMAC_DOUBLE_ECC_ERR,
4716 &bar0->mac_rmac_err_reg,
4717 &sw_stat->mac_rmac_err_cnt);
8116f3cf
SS		 4718 }
4719
4720 val64 = readq(&bar0->xgxs_int_status);
4721 if (val64 & XGXS_INT_STATUS_RXGXS) {
4722 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
d44570e4
JP		 4723 &bar0->xgxs_rxgxs_err_reg,
4724 &sw_stat->xgxs_rxgxs_err_cnt))
8116f3cf
SS		 4725 goto reset;
4726 }
4727
4728 val64 = readq(&bar0->mc_int_status);
d44570e4
JP		 4729 if (val64 & MC_INT_STATUS_MC_INT) {
4730 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4731 &bar0->mc_err_reg,
4732 &sw_stat->mc_err_cnt))
8116f3cf
SS		 4733 goto reset;
4734
4735 /* Handling Ecc errors */
4736 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4737 writeq(val64, &bar0->mc_err_reg);
4738 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4739 sw_stat->double_ecc_errs++;
4740 if (sp->device_type != XFRAME_II_DEVICE) {
4741 /*
4742 * Reset XframeI only if critical error
4743 */
4744 if (val64 &
d44570e4
JP		 4745 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4746 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4747 goto reset;
4748 }
8116f3cf
SS		 4749 } else
4750 sw_stat->single_ecc_errs++;
4751 }
4752 }
4753 return;
4754
4755reset:
3a3d5756 4756 s2io_stop_all_tx_queue(sp);
8116f3cf
SS		 4757 schedule_work(&sp->rst_timer_task);
4758 sw_stat->soft_reset_cnt++;
4759 return;
4760}
4761
1da177e4
LT		 4762/**
4763 * s2io_isr - ISR handler of the device .
4764 * @irq: the irq of the device.
4765 * @dev_id: a void pointer to the dev structure of the NIC.
20346722 4766 * Description: This function is the ISR handler of the device. It
4767 * identifies the reason for the interrupt and calls the relevant
4768 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4769 * recv buffers, if their numbers are below the panic value which is
4770 * presently set to 25% of the original number of rcv buffers allocated.
4771 * Return value:
20346722 4772 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4773 * IRQ_NONE: will be returned if interrupt is not from our device
4774 */
7d12e780 4775static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4 4776{
d44570e4 4777 struct net_device *dev = (struct net_device *)dev_id;
4cf1653a 4778 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4779 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4780 int i;
19a60522 4781 u64 reason = 0;
1ee6dd77 4782 struct mac_info *mac_control;
1da177e4
LT		 4783 struct config_param *config;
4784
d796fdb7
LV		 4785 /* Pretend we handled any irq's from a disconnected card */
4786 if (pci_channel_offline(sp->pdev))
4787 return IRQ_NONE;
4788
596c5c97 4789 if (!is_s2io_card_up(sp))
92b84437 4790 return IRQ_NONE;
92b84437 4791
1da177e4 4792 config = &sp->config;
ffb5df6c 4793 mac_control = &sp->mac_control;
1da177e4 4794
20346722 4795 /*
1da177e4
LT		 4796 * Identify the cause for interrupt and call the appropriate
4797 * interrupt handler. Causes for the interrupt could be;
4798 * 1. Rx of packet.
4799 * 2. Tx complete.
4800 * 3. Link down.
1da177e4
LT		 4801 */
4802 reason = readq(&bar0->general_int_status);
4803
d44570e4
JP		 4804 if (unlikely(reason == S2IO_MINUS_ONE))
4805 return IRQ_HANDLED; /* Nothing much can be done. Get out */
5d3213cc 4806
d44570e4
JP		 4807 if (reason &
4808 (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
596c5c97
SS		 4809 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4810
4811 if (config->napi) {
4812 if (reason & GEN_INTR_RXTRAFFIC) {
288379f0 4813 napi_schedule(&sp->napi);
f61e0a35
SH		 4814 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4815 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4816 readl(&bar0->rx_traffic_int);
db874e65 4817 }
596c5c97
SS		 4818 } else {
4819 /*
4820 * rx_traffic_int reg is an R1 register, writing all 1's
4821 * will ensure that the actual interrupt causing bit
4822 * get's cleared and hence a read can be avoided.
4823 */
4824 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4825 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97 4826
13d866a9
JP		 4827 for (i = 0; i < config->rx_ring_num; i++) {
4828 struct ring_info *ring = &mac_control->rings[i];
4829
4830 rx_intr_handler(ring, 0);
4831 }
db874e65 4832 }
596c5c97 4833
db874e65 4834 /*
596c5c97 4835 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4836 * will ensure that the actual interrupt causing bit get's
4837 * cleared and hence a read can be avoided.
4838 */
596c5c97
SS		 4839 if (reason & GEN_INTR_TXTRAFFIC)
4840 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4841
596c5c97
SS		 4842 for (i = 0; i < config->tx_fifo_num; i++)
4843 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4844
596c5c97
SS		 4845 if (reason & GEN_INTR_TXPIC)
4846 s2io_txpic_intr_handle(sp);
fe113638 4847
596c5c97
SS		 4848 /*
4849 * Reallocate the buffers from the interrupt handler itself.
4850 */
4851 if (!config->napi) {
13d866a9
JP		 4852 for (i = 0; i < config->rx_ring_num; i++) {
4853 struct ring_info *ring = &mac_control->rings[i];
4854
4855 s2io_chk_rx_buffers(sp, ring);
4856 }
596c5c97
SS		 4857 }
4858 writeq(sp->general_int_mask, &bar0->general_int_mask);
4859 readl(&bar0->general_int_status);
20346722 4860
596c5c97 4861 return IRQ_HANDLED;
db874e65 4862
d44570e4 4863 } else if (!reason) {
596c5c97
SS		 4864 /* The interrupt was not raised by us */
4865 return IRQ_NONE;
4866 }
db874e65 4867
1da177e4
LT		 4868 return IRQ_HANDLED;
4869}
4870
7ba013ac 4871/**
4872 * s2io_updt_stats -
4873 */
1ee6dd77 4874static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4875{
1ee6dd77 4876 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac 4877 u64 val64;
4878 int cnt = 0;
4879
92b84437 4880 if (is_s2io_card_up(sp)) {
7ba013ac 4881 /* Apprx 30us on a 133 MHz bus */
4882 val64 = SET_UPDT_CLICKS(10) |
4883 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4884 writeq(val64, &bar0->stat_cfg);
4885 do {
4886 udelay(100);
4887 val64 = readq(&bar0->stat_cfg);
b7b5a128 4888 if (!(val64 & s2BIT(0)))
7ba013ac 4889 break;
4890 cnt++;
4891 if (cnt == 5)
4892 break; /* Updt failed */
d44570e4 4893 } while (1);
8a4bdbaa 4894 }
7ba013ac 4895}
4896
1da177e4 4897/**
20346722 4898 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4899 * @dev : pointer to the device structure.
4900 * Description:
20346722 4901 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4902 * structure and returns a pointer to the same.
4903 * Return value:
4904 * pointer to the updated net_device_stats structure.
4905 */
4906
ac1f60db 4907static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4908{
4cf1653a 4909 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 4910 struct config_param *config = &sp->config;
4911 struct mac_info *mac_control = &sp->mac_control;
4912 struct stat_block *stats = mac_control->stats_info;
0425b46a 4913 int i;
1da177e4 4914
7ba013ac 4915 /* Configure Stats for immediate updt */
4916 s2io_updt_stats(sp);
4917
dc56e634
BL		 4918 /* Using sp->stats as a staging area, because reset (due to mtu
4919 change, for example) will clear some hardware counters */
ffb5df6c 4920 dev->stats.tx_packets += le32_to_cpu(stats->tmac_frms) -
dc56e634 4921 sp->stats.tx_packets;
ffb5df6c
JP		 4922 sp->stats.tx_packets = le32_to_cpu(stats->tmac_frms);
4923
4924 dev->stats.tx_errors += le32_to_cpu(stats->tmac_any_err_frms) -
dc56e634 4925 sp->stats.tx_errors;
ffb5df6c
JP		 4926 sp->stats.tx_errors = le32_to_cpu(stats->tmac_any_err_frms);
4927
4928 dev->stats.rx_errors += le64_to_cpu(stats->rmac_drop_frms) -
dc56e634 4929 sp->stats.rx_errors;
ffb5df6c
JP		 4930 sp->stats.rx_errors = le64_to_cpu(stats->rmac_drop_frms);
4931
4932 dev->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms) -
dc56e634 4933 sp->stats.multicast;
ffb5df6c
JP		 4934 sp->stats.multicast = le32_to_cpu(stats->rmac_vld_mcst_frms);
4935
4936 dev->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms) -
dc56e634 4937 sp->stats.rx_length_errors;
ffb5df6c 4938 sp->stats.rx_length_errors = le64_to_cpu(stats->rmac_long_frms);
1da177e4 4939
0425b46a 4940 /* collect per-ring rx_packets and rx_bytes */
dc56e634 4941 dev->stats.rx_packets = dev->stats.rx_bytes = 0;
0425b46a 4942 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 4943 struct ring_info *ring = &mac_control->rings[i];
4944
4945 dev->stats.rx_packets += ring->rx_packets;
4946 dev->stats.rx_bytes += ring->rx_bytes;
0425b46a
SH		 4947 }
4948
d44570e4 4949 return &dev->stats;
1da177e4
LT		 4950}
4951
4952/**
4953 * s2io_set_multicast - entry point for multicast address enable/disable.
4954 * @dev : pointer to the device structure
4955 * Description:
20346722 4956 * This function is a driver entry point which gets called by the kernel
4957 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4958 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4959 * determine, if multicast address must be enabled or if promiscuous mode
4960 * is to be disabled etc.
4961 * Return value:
4962 * void.
4963 */
4964
4965static void s2io_set_multicast(struct net_device *dev)
4966{
4967 int i, j, prev_cnt;
4968 struct dev_mc_list *mclist;
4cf1653a 4969 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 4970 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4971 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
d44570e4 4972 0xfeffffffffffULL;
faa4f796 4973 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4974 void __iomem *add;
faa4f796 4975 struct config_param *config = &sp->config;
1da177e4
LT		 4976
4977 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4978 /* Enable all Multicast addresses */
4979 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4980 &bar0->rmac_addr_data0_mem);
4981 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4982 &bar0->rmac_addr_data1_mem);
4983 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 4984 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4985 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4986 writeq(val64, &bar0->rmac_addr_cmd_mem);
4987 /* Wait till command completes */
c92ca04b 4988 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 4989 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4990 S2IO_BIT_RESET);
1da177e4
LT		 4991
4992 sp->m_cast_flg = 1;
faa4f796 4993 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4994 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4995 /* Disable all Multicast addresses */
4996 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4997 &bar0->rmac_addr_data0_mem);
5e25b9dd 4998 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4999 &bar0->rmac_addr_data1_mem);
1da177e4 5000 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5001 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5002 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
1da177e4
LT		 5003 writeq(val64, &bar0->rmac_addr_cmd_mem);
5004 /* Wait till command completes */
c92ca04b 5005 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5006 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5007 S2IO_BIT_RESET);
1da177e4
LT		 5008
5009 sp->m_cast_flg = 0;
5010 sp->all_multi_pos = 0;
5011 }
5012
5013 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
5014 /* Put the NIC into promiscuous mode */
5015 add = &bar0->mac_cfg;
5016 val64 = readq(&bar0->mac_cfg);
5017 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
5018
5019 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5020 writel((u32)val64, add);
1da177e4
LT		 5021 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5022 writel((u32) (val64 >> 32), (add + 4));
5023
926930b2
SS		 5024 if (vlan_tag_strip != 1) {
5025 val64 = readq(&bar0->rx_pa_cfg);
5026 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
5027 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5028 sp->vlan_strip_flag = 0;
926930b2
SS		 5029 }
5030
1da177e4
LT		 5031 val64 = readq(&bar0->mac_cfg);
5032 sp->promisc_flg = 1;
776bd20f 5033 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 5034 dev->name);
5035 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
5036 /* Remove the NIC from promiscuous mode */
5037 add = &bar0->mac_cfg;
5038 val64 = readq(&bar0->mac_cfg);
5039 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5040
5041 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
d44570e4 5042 writel((u32)val64, add);
1da177e4
LT		 5043 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5044 writel((u32) (val64 >> 32), (add + 4));
5045
926930b2
SS		 5046 if (vlan_tag_strip != 0) {
5047 val64 = readq(&bar0->rx_pa_cfg);
5048 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5049 writeq(val64, &bar0->rx_pa_cfg);
cd0fce03 5050 sp->vlan_strip_flag = 1;
926930b2
SS		 5051 }
5052
1da177e4
LT		 5053 val64 = readq(&bar0->mac_cfg);
5054 sp->promisc_flg = 0;
776bd20f 5055 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 5056 dev->name);
5057 }
5058
5059 /* Update individual M_CAST address list */
5060 if ((!sp->m_cast_flg) && dev->mc_count) {
5061 if (dev->mc_count >
faa4f796 5062 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 5063 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
5064 dev->name);
5065 DBG_PRINT(ERR_DBG, "can be added, please enable ");
5066 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
5067 return;
5068 }
5069
5070 prev_cnt = sp->mc_addr_count;
5071 sp->mc_addr_count = dev->mc_count;
5072
5073 /* Clear out the previous list of Mc in the H/W. */
5074 for (i = 0; i < prev_cnt; i++) {
5075 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5076 &bar0->rmac_addr_data0_mem);
5077 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5078 &bar0->rmac_addr_data1_mem);
1da177e4 5079 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5080 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5081 RMAC_ADDR_CMD_MEM_OFFSET
5082 (config->mc_start_offset + i);
1da177e4
LT		 5083 writeq(val64, &bar0->rmac_addr_cmd_mem);
5084
5085 /* Wait for command completes */
c92ca04b 5086 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5087 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5088 S2IO_BIT_RESET)) {
5089 DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name);
1da177e4
LT		 5090 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5091 return;
5092 }
5093 }
5094
5095 /* Create the new Rx filter list and update the same in H/W. */
5096 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
5097 i++, mclist = mclist->next) {
5098 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
5099 ETH_ALEN);
a7a80d5a 5100 mac_addr = 0;
1da177e4
LT		 5101 for (j = 0; j < ETH_ALEN; j++) {
5102 mac_addr |= mclist->dmi_addr[j];
5103 mac_addr <<= 8;
5104 }
5105 mac_addr >>= 8;
5106 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5107 &bar0->rmac_addr_data0_mem);
5108 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
d44570e4 5109 &bar0->rmac_addr_data1_mem);
1da177e4 5110 val64 = RMAC_ADDR_CMD_MEM_WE |
d44570e4
JP		 5111 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5112 RMAC_ADDR_CMD_MEM_OFFSET
5113 (i + config->mc_start_offset);
1da177e4
LT		 5114 writeq(val64, &bar0->rmac_addr_cmd_mem);
5115
5116 /* Wait for command completes */
c92ca04b 5117 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5118 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5119 S2IO_BIT_RESET)) {
5120 DBG_PRINT(ERR_DBG, "%s: Adding ", dev->name);
1da177e4
LT		 5121 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
5122 return;
5123 }
5124 }
5125 }
5126}
5127
faa4f796
SH		 5128/* read from CAM unicast & multicast addresses and store it in
5129 * def_mac_addr structure
5130 */
dac499f9 5131static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
faa4f796
SH		 5132{
5133 int offset;
5134 u64 mac_addr = 0x0;
5135 struct config_param *config = &sp->config;
5136
5137 /* store unicast & multicast mac addresses */
5138 for (offset = 0; offset < config->max_mc_addr; offset++) {
5139 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5140 /* if read fails disable the entry */
5141 if (mac_addr == FAILURE)
5142 mac_addr = S2IO_DISABLE_MAC_ENTRY;
5143 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5144 }
5145}
5146
5147/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5148static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5149{
5150 int offset;
5151 struct config_param *config = &sp->config;
5152 /* restore unicast mac address */
5153 for (offset = 0; offset < config->max_mac_addr; offset++)
5154 do_s2io_prog_unicast(sp->dev,
d44570e4 5155 sp->def_mac_addr[offset].mac_addr);
faa4f796
SH		 5156
5157 /* restore multicast mac address */
5158 for (offset = config->mc_start_offset;
d44570e4 5159 offset < config->max_mc_addr; offset++)
faa4f796
SH		 5160 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5161}
5162
5163/* add a multicast MAC address to CAM */
5164static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5165{
5166 int i;
5167 u64 mac_addr = 0;
5168 struct config_param *config = &sp->config;
5169
5170 for (i = 0; i < ETH_ALEN; i++) {
5171 mac_addr <<= 8;
5172 mac_addr |= addr[i];
5173 }
5174 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5175 return SUCCESS;
5176
5177 /* check if the multicast mac already preset in CAM */
5178 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5179 u64 tmp64;
5180 tmp64 = do_s2io_read_unicast_mc(sp, i);
5181 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5182 break;
5183
5184 if (tmp64 == mac_addr)
5185 return SUCCESS;
5186 }
5187 if (i == config->max_mc_addr) {
5188 DBG_PRINT(ERR_DBG,
d44570e4 5189 "CAM full no space left for multicast MAC\n");
faa4f796
SH		 5190 return FAILURE;
5191 }
5192 /* Update the internal structure with this new mac address */
5193 do_s2io_copy_mac_addr(sp, i, mac_addr);
5194
d44570e4 5195 return do_s2io_add_mac(sp, mac_addr, i);
faa4f796
SH		 5196}
5197
5198/* add MAC address to CAM */
5199static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5200{
5201 u64 val64;
5202 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5203
5204 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
d44570e4 5205 &bar0->rmac_addr_data0_mem);
2fd37688 5206
d44570e4 5207 val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
2fd37688
SS		 5208 RMAC_ADDR_CMD_MEM_OFFSET(off);
5209 writeq(val64, &bar0->rmac_addr_cmd_mem);
5210
5211 /* Wait till command completes */
5212 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5213 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5214 S2IO_BIT_RESET)) {
faa4f796 5215 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5216 return FAILURE;
5217 }
5218 return SUCCESS;
5219}
faa4f796
SH		 5220/* deletes a specified unicast/multicast mac entry from CAM */
5221static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5222{
5223 int offset;
5224 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5225 struct config_param *config = &sp->config;
5226
5227 for (offset = 1;
d44570e4 5228 offset < config->max_mc_addr; offset++) {
faa4f796
SH		 5229 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5230 if (tmp64 == addr) {
5231 /* disable the entry by writing 0xffffffffffffULL */
5232 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5233 return FAILURE;
5234 /* store the new mac list from CAM */
5235 do_s2io_store_unicast_mc(sp);
5236 return SUCCESS;
5237 }
5238 }
5239 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
d44570e4 5240 (unsigned long long)addr);
faa4f796
SH		 5241 return FAILURE;
5242}
5243
5244/* read mac entries from CAM */
5245static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5246{
5247 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5248 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5249
5250 /* read mac addr */
d44570e4 5251 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796
SH		 5252 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5253 writeq(val64, &bar0->rmac_addr_cmd_mem);
5254
5255 /* Wait till command completes */
5256 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 5257 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5258 S2IO_BIT_RESET)) {
faa4f796
SH		 5259 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5260 return FAILURE;
5261 }
5262 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4
JP		 5263
5264 return tmp64 >> 16;
faa4f796 5265}
2fd37688
SS		 5266
5267/**
5268 * s2io_set_mac_addr driver entry point
5269 */
faa4f796 5270
2fd37688
SS		 5271static int s2io_set_mac_addr(struct net_device *dev, void *p)
5272{
5273 struct sockaddr *addr = p;
5274
5275 if (!is_valid_ether_addr(addr->sa_data))
5276 return -EINVAL;
5277
5278 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5279
5280 /* store the MAC address in CAM */
d44570e4 5281 return do_s2io_prog_unicast(dev, dev->dev_addr);
2fd37688 5282}
1da177e4 5283/**
2fd37688 5284 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5285 * @dev : pointer to the device structure.
5286 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5287 * Description : This procedure will program the Xframe to receive
1da177e4 5288 * frames with new Mac Address
20346722 5289 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5290 * as defined in errno.h file on failure.
5291 */
faa4f796 5292
2fd37688 5293static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5294{
4cf1653a 5295 struct s2io_nic *sp = netdev_priv(dev);
2fd37688 5296 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5297 int i;
faa4f796
SH		 5298 u64 tmp64;
5299 struct config_param *config = &sp->config;
1da177e4 5300
20346722 5301 /*
d44570e4
JP		 5302 * Set the new MAC address as the new unicast filter and reflect this
5303 * change on the device address registered with the OS. It will be
5304 * at offset 0.
5305 */
1da177e4
LT		 5306 for (i = 0; i < ETH_ALEN; i++) {
5307 mac_addr <<= 8;
5308 mac_addr |= addr[i];
2fd37688
SS		 5309 perm_addr <<= 8;
5310 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5311 }
5312
2fd37688
SS		 5313 /* check if the dev_addr is different than perm_addr */
5314 if (mac_addr == perm_addr)
d8d70caf
SS		 5315 return SUCCESS;
5316
faa4f796
SH		 5317 /* check if the mac already preset in CAM */
5318 for (i = 1; i < config->max_mac_addr; i++) {
5319 tmp64 = do_s2io_read_unicast_mc(sp, i);
5320 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5321 break;
5322
5323 if (tmp64 == mac_addr) {
5324 DBG_PRINT(INFO_DBG,
d44570e4
JP		 5325 "MAC addr:0x%llx already present in CAM\n",
5326 (unsigned long long)mac_addr);
faa4f796
SH		 5327 return SUCCESS;
5328 }
5329 }
5330 if (i == config->max_mac_addr) {
5331 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5332 return FAILURE;
5333 }
d8d70caf 5334 /* Update the internal structure with this new mac address */
faa4f796 5335 do_s2io_copy_mac_addr(sp, i, mac_addr);
d44570e4
JP		 5336
5337 return do_s2io_add_mac(sp, mac_addr, i);
1da177e4
LT		 5338}
5339
5340/**
20346722 5341 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5342 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5343 * @info: pointer to the structure with parameters given by ethtool to set
5344 * link information.
5345 * Description:
20346722 5346 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5347 * the NIC.
5348 * Return value:
5349 * 0 on success.
d44570e4 5350 */
1da177e4
LT		 5351
5352static int s2io_ethtool_sset(struct net_device *dev,
5353 struct ethtool_cmd *info)
5354{
4cf1653a 5355 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5356 if ((info->autoneg == AUTONEG_ENABLE) ||
d44570e4
JP		 5357 (info->speed != SPEED_10000) ||
5358 (info->duplex != DUPLEX_FULL))
1da177e4
LT		 5359 return -EINVAL;
5360 else {
5361 s2io_close(sp->dev);
5362 s2io_open(sp->dev);
5363 }
5364
5365 return 0;
5366}
5367
5368/**
20346722 5369 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5370 * @sp : private member of the device structure, pointer to the
5371 * s2io_nic structure.
5372 * @info : pointer to the structure with parameters given by ethtool
5373 * to return link information.
5374 * Description:
5375 * Returns link specific information like speed, duplex etc.. to ethtool.
5376 * Return value :
5377 * return 0 on success.
5378 */
5379
5380static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5381{
4cf1653a 5382 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5383 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5384 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5385 info->port = PORT_FIBRE;
1a7eb72b
SS		 5386
5387 /* info->transceiver */
5388 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5389
5390 if (netif_carrier_ok(sp->dev)) {
5391 info->speed = 10000;
5392 info->duplex = DUPLEX_FULL;
5393 } else {
5394 info->speed = -1;
5395 info->duplex = -1;
5396 }
5397
5398 info->autoneg = AUTONEG_DISABLE;
5399 return 0;
5400}
5401
5402/**
20346722 5403 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5404 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5405 * s2io_nic structure.
5406 * @info : pointer to the structure with parameters given by ethtool to
5407 * return driver information.
5408 * Description:
5409 * Returns driver specefic information like name, version etc.. to ethtool.
5410 * Return value:
5411 * void
5412 */
5413
5414static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5415 struct ethtool_drvinfo *info)
5416{
4cf1653a 5417 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 5418
dbc2309d
JL		 5419 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5420 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5421 strncpy(info->fw_version, "", sizeof(info->fw_version));
5422 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5423 info->regdump_len = XENA_REG_SPACE;
5424 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5425}
5426
5427/**
5428 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5429 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5430 * s2io_nic structure.
20346722 5431 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5432 * dumping the registers.
5433 * @reg_space: The input argumnet into which all the registers are dumped.
5434 * Description:
5435 * Dumps the entire register space of xFrame NIC into the user given
5436 * buffer area.
5437 * Return value :
5438 * void .
d44570e4 5439 */
1da177e4
LT		 5440
5441static void s2io_ethtool_gregs(struct net_device *dev,
5442 struct ethtool_regs *regs, void *space)
5443{
5444 int i;
5445 u64 reg;
d44570e4 5446 u8 *reg_space = (u8 *)space;
4cf1653a 5447 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5448
5449 regs->len = XENA_REG_SPACE;
5450 regs->version = sp->pdev->subsystem_device;
5451
5452 for (i = 0; i < regs->len; i += 8) {
5453 reg = readq(sp->bar0 + i);
5454 memcpy((reg_space + i), &reg, 8);
5455 }
5456}
5457
5458/**
5459 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5460 * @data : address of the private member of the device structure, which
1da177e4 5461 * is a pointer to the s2io_nic structure, provided as an u32.
20346722 5462 * Description: This is actually the timer function that alternates the
5463 * adapter LED bit of the adapter control bit to set/reset every time on
5464 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4 5465 * once every second.
d44570e4 5466 */
1da177e4
LT		 5467static void s2io_phy_id(unsigned long data)
5468{
d44570e4 5469 struct s2io_nic *sp = (struct s2io_nic *)data;
1ee6dd77 5470 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5471 u64 val64 = 0;
5472 u16 subid;
5473
5474 subid = sp->pdev->subsystem_device;
541ae68f 5475 if ((sp->device_type == XFRAME_II_DEVICE) ||
d44570e4 5476 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5477 val64 = readq(&bar0->gpio_control);
5478 val64 ^= GPIO_CTRL_GPIO_0;
5479 writeq(val64, &bar0->gpio_control);
5480 } else {
5481 val64 = readq(&bar0->adapter_control);
5482 val64 ^= ADAPTER_LED_ON;
5483 writeq(val64, &bar0->adapter_control);
5484 }
5485
5486 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5487}
5488
5489/**
5490 * s2io_ethtool_idnic - To physically identify the nic on the system.
5491 * @sp : private member of the device structure, which is a pointer to the
5492 * s2io_nic structure.
20346722 5493 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5494 * ethtool.
5495 * Description: Used to physically identify the NIC on the system.
20346722 5496 * The Link LED will blink for a time specified by the user for
1da177e4 5497 * identification.
20346722 5498 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5499 * identification is possible only if it's link is up.
5500 * Return value:
5501 * int , returns 0 on success
5502 */
5503
5504static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5505{
5506 u64 val64 = 0, last_gpio_ctrl_val;
4cf1653a 5507 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5508 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5509 u16 subid;
5510
5511 subid = sp->pdev->subsystem_device;
5512 last_gpio_ctrl_val = readq(&bar0->gpio_control);
d44570e4 5513 if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5514 val64 = readq(&bar0->adapter_control);
5515 if (!(val64 & ADAPTER_CNTL_EN)) {
6cef2b8e 5516 pr_err("Adapter Link down, cannot blink LED\n");
1da177e4
LT		 5517 return -EFAULT;
5518 }
5519 }
5520 if (sp->id_timer.function == NULL) {
5521 init_timer(&sp->id_timer);
5522 sp->id_timer.function = s2io_phy_id;
d44570e4 5523 sp->id_timer.data = (unsigned long)sp;
1da177e4
LT		 5524 }
5525 mod_timer(&sp->id_timer, jiffies);
5526 if (data)
20346722 5527 msleep_interruptible(data * HZ);
1da177e4 5528 else
20346722 5529 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5530 del_timer_sync(&sp->id_timer);
5531
541ae68f 5532 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5533 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5534 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5535 }
5536
5537 return 0;
5538}
5539
0cec35eb 5540static void s2io_ethtool_gringparam(struct net_device *dev,
d44570e4 5541 struct ethtool_ringparam *ering)
0cec35eb 5542{
4cf1653a 5543 struct s2io_nic *sp = netdev_priv(dev);
d44570e4 5544 int i, tx_desc_count = 0, rx_desc_count = 0;
0cec35eb
SH		 5545
5546 if (sp->rxd_mode == RXD_MODE_1)
5547 ering->rx_max_pending = MAX_RX_DESC_1;
5548 else if (sp->rxd_mode == RXD_MODE_3B)
5549 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5550
5551 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5552 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5553 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5554
d44570e4 5555 DBG_PRINT(INFO_DBG, "\nmax txds : %d\n", sp->config.max_txds);
0cec35eb
SH		 5556 ering->tx_pending = tx_desc_count;
5557 rx_desc_count = 0;
8a4bdbaa 5558 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5559 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5560
0cec35eb
SH		 5561 ering->rx_pending = rx_desc_count;
5562
5563 ering->rx_mini_max_pending = 0;
5564 ering->rx_mini_pending = 0;
d44570e4 5565 if (sp->rxd_mode == RXD_MODE_1)
0cec35eb
SH		 5566 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5567 else if (sp->rxd_mode == RXD_MODE_3B)
5568 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5569 ering->rx_jumbo_pending = rx_desc_count;
5570}
5571
1da177e4
LT		 5572/**
5573 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722 5574 * @sp : private member of the device structure, which is a pointer to the
5575 * s2io_nic structure.
1da177e4
LT		 5576 * @ep : pointer to the structure with pause parameters given by ethtool.
5577 * Description:
5578 * Returns the Pause frame generation and reception capability of the NIC.
5579 * Return value:
5580 * void
5581 */
5582static void s2io_ethtool_getpause_data(struct net_device *dev,
5583 struct ethtool_pauseparam *ep)
5584{
5585 u64 val64;
4cf1653a 5586 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5587 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5588
5589 val64 = readq(&bar0->rmac_pause_cfg);
5590 if (val64 & RMAC_PAUSE_GEN_ENABLE)
f957bcf0 5591 ep->tx_pause = true;
1da177e4 5592 if (val64 & RMAC_PAUSE_RX_ENABLE)
f957bcf0
TK		 5593 ep->rx_pause = true;
5594 ep->autoneg = false;
1da177e4
LT		 5595}
5596
5597/**
5598 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5599 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5600 * s2io_nic structure.
5601 * @ep : pointer to the structure with pause parameters given by ethtool.
5602 * Description:
5603 * It can be used to set or reset Pause frame generation or reception
5604 * support of the NIC.
5605 * Return value:
5606 * int, returns 0 on Success
5607 */
5608
5609static int s2io_ethtool_setpause_data(struct net_device *dev,
d44570e4 5610 struct ethtool_pauseparam *ep)
1da177e4
LT		 5611{
5612 u64 val64;
4cf1653a 5613 struct s2io_nic *sp = netdev_priv(dev);
1ee6dd77 5614 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5615
5616 val64 = readq(&bar0->rmac_pause_cfg);
5617 if (ep->tx_pause)
5618 val64 |= RMAC_PAUSE_GEN_ENABLE;
5619 else
5620 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5621 if (ep->rx_pause)
5622 val64 |= RMAC_PAUSE_RX_ENABLE;
5623 else
5624 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5625 writeq(val64, &bar0->rmac_pause_cfg);
5626 return 0;
5627}
5628
5629/**
5630 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5631 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5632 * s2io_nic structure.
5633 * @off : offset at which the data must be written
5634 * @data : Its an output parameter where the data read at the given
20346722 5635 * offset is stored.
1da177e4 5636 * Description:
20346722 5637 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5638 * read data.
5639 * NOTE: Will allow to read only part of the EEPROM visible through the
5640 * I2C bus.
5641 * Return value:
5642 * -1 on failure and 0 on success.
5643 */
5644
5645#define S2IO_DEV_ID 5
d44570e4 5646static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
1da177e4
LT		 5647{
5648 int ret = -1;
5649 u32 exit_cnt = 0;
5650 u64 val64;
1ee6dd77 5651 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5652
ad4ebed0 5653 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5654 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5655 I2C_CONTROL_ADDR(off) |
5656 I2C_CONTROL_BYTE_CNT(0x3) |
5657 I2C_CONTROL_READ |
5658 I2C_CONTROL_CNTL_START;
ad4ebed0 5659 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5660
ad4ebed0 5661 while (exit_cnt < 5) {
5662 val64 = readq(&bar0->i2c_control);
5663 if (I2C_CONTROL_CNTL_END(val64)) {
5664 *data = I2C_CONTROL_GET_DATA(val64);
5665 ret = 0;
5666 break;
5667 }
5668 msleep(50);
5669 exit_cnt++;
1da177e4 5670 }
1da177e4
LT		 5671 }
5672
ad4ebed0 5673 if (sp->device_type == XFRAME_II_DEVICE) {
5674 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5675 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5676 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5677 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5678 val64 |= SPI_CONTROL_REQ;
5679 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5680 while (exit_cnt < 5) {
5681 val64 = readq(&bar0->spi_control);
5682 if (val64 & SPI_CONTROL_NACK) {
5683 ret = 1;
5684 break;
5685 } else if (val64 & SPI_CONTROL_DONE) {
5686 *data = readq(&bar0->spi_data);
5687 *data &= 0xffffff;
5688 ret = 0;
5689 break;
5690 }
5691 msleep(50);
5692 exit_cnt++;
5693 }
5694 }
1da177e4
LT		 5695 return ret;
5696}
5697
5698/**
5699 * write_eeprom - actually writes the relevant part of the data value.
5700 * @sp : private member of the device structure, which is a pointer to the
5701 * s2io_nic structure.
5702 * @off : offset at which the data must be written
5703 * @data : The data that is to be written
20346722 5704 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5705 * the Eeprom. (max of 3)
5706 * Description:
5707 * Actually writes the relevant part of the data value into the Eeprom
5708 * through the I2C bus.
5709 * Return value:
5710 * 0 on success, -1 on failure.
5711 */
5712
d44570e4 5713static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
1da177e4
LT		 5714{
5715 int exit_cnt = 0, ret = -1;
5716 u64 val64;
1ee6dd77 5717 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5718
ad4ebed0 5719 if (sp->device_type == XFRAME_I_DEVICE) {
d44570e4
JP		 5720 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5721 I2C_CONTROL_ADDR(off) |
5722 I2C_CONTROL_BYTE_CNT(cnt) |
5723 I2C_CONTROL_SET_DATA((u32)data) |
5724 I2C_CONTROL_CNTL_START;
ad4ebed0 5725 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5726
5727 while (exit_cnt < 5) {
5728 val64 = readq(&bar0->i2c_control);
5729 if (I2C_CONTROL_CNTL_END(val64)) {
5730 if (!(val64 & I2C_CONTROL_NACK))
5731 ret = 0;
5732 break;
5733 }
5734 msleep(50);
5735 exit_cnt++;
5736 }
5737 }
1da177e4 5738
ad4ebed0 5739 if (sp->device_type == XFRAME_II_DEVICE) {
5740 int write_cnt = (cnt == 8) ? 0 : cnt;
d44570e4 5741 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
ad4ebed0 5742
5743 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5744 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5745 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5746 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5747 val64 |= SPI_CONTROL_REQ;
5748 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5749 while (exit_cnt < 5) {
5750 val64 = readq(&bar0->spi_control);
5751 if (val64 & SPI_CONTROL_NACK) {
5752 ret = 1;
5753 break;
5754 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5755 ret = 0;
ad4ebed0 5756 break;
5757 }
5758 msleep(50);
5759 exit_cnt++;
1da177e4 5760 }
1da177e4 5761 }
1da177e4
LT		 5762 return ret;
5763}
1ee6dd77 5764static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5765{
b41477f3
AR		 5766 u8 *vpd_data;
5767 u8 data;
d44570e4 5768 int i = 0, cnt, fail = 0;
9dc737a7 5769 int vpd_addr = 0x80;
ffb5df6c 5770 struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
9dc737a7
AR		 5771
5772 if (nic->device_type == XFRAME_II_DEVICE) {
5773 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5774 vpd_addr = 0x80;
d44570e4 5775 } else {
9dc737a7
AR		 5776 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5777 vpd_addr = 0x50;
5778 }
19a60522 5779 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5780
b41477f3 5781 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945 5782 if (!vpd_data) {
ffb5df6c 5783 swstats->mem_alloc_fail_cnt++;
b41477f3 5784 return;
c53d4945 5785 }
ffb5df6c 5786 swstats->mem_allocated += 256;
b41477f3 5787
d44570e4 5788 for (i = 0; i < 256; i += 4) {
9dc737a7
AR		 5789 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5790 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5791 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
d44570e4 5792 for (cnt = 0; cnt < 5; cnt++) {
9dc737a7
AR		 5793 msleep(2);
5794 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5795 if (data == 0x80)
5796 break;
5797 }
5798 if (cnt >= 5) {
5799 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5800 fail = 1;
5801 break;
5802 }
5803 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5804 (u32 *)&vpd_data[i]);
5805 }
19a60522 5806
d44570e4 5807 if (!fail) {
19a60522
SS		 5808 /* read serial number of adapter */
5809 for (cnt = 0; cnt < 256; cnt++) {
d44570e4
JP		 5810 if ((vpd_data[cnt] == 'S') &&
5811 (vpd_data[cnt+1] == 'N') &&
5812 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
19a60522
SS		 5813 memset(nic->serial_num, 0, VPD_STRING_LEN);
5814 memcpy(nic->serial_num, &vpd_data[cnt + 3],
d44570e4 5815 vpd_data[cnt+2]);
19a60522
SS		 5816 break;
5817 }
5818 }
5819 }
5820
5821 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5822 memset(nic->product_name, 0, vpd_data[1]);
5823 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5824 }
b41477f3 5825 kfree(vpd_data);
ffb5df6c 5826 swstats->mem_freed += 256;
9dc737a7
AR		 5827}
5828
1da177e4
LT		 5829/**
5830 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5831 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5832 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5833 * containing all relevant information.
5834 * @data_buf : user defined value to be written into Eeprom.
5835 * Description: Reads the values stored in the Eeprom at given offset
5836 * for a given length. Stores these values int the input argument data
5837 * buffer 'data_buf' and returns these to the caller (ethtool.)
5838 * Return value:
5839 * int 0 on success
5840 */
5841
5842static int s2io_ethtool_geeprom(struct net_device *dev,
d44570e4 5843 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5844{
ad4ebed0 5845 u32 i, valid;
5846 u64 data;
4cf1653a 5847 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5848
5849 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5850
5851 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5852 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5853
5854 for (i = 0; i < eeprom->len; i += 4) {
5855 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5856 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5857 return -EFAULT;
5858 }
5859 valid = INV(data);
5860 memcpy((data_buf + i), &valid, 4);
5861 }
5862 return 0;
5863}
5864
5865/**
5866 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5867 * @sp : private member of the device structure, which is a pointer to the
5868 * s2io_nic structure.
20346722 5869 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5870 * containing all relevant information.
5871 * @data_buf ; user defined value to be written into Eeprom.
5872 * Description:
5873 * Tries to write the user provided value in the Eeprom, at the offset
5874 * given by the user.
5875 * Return value:
5876 * 0 on success, -EFAULT on failure.
5877 */
5878
5879static int s2io_ethtool_seeprom(struct net_device *dev,
5880 struct ethtool_eeprom *eeprom,
d44570e4 5881 u8 *data_buf)
1da177e4
LT		 5882{
5883 int len = eeprom->len, cnt = 0;
ad4ebed0 5884 u64 valid = 0, data;
4cf1653a 5885 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 5886
5887 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5888 DBG_PRINT(ERR_DBG,
5889 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
d44570e4 5890 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n", eeprom->magic);
1da177e4
LT		 5891 return -EFAULT;
5892 }
5893
5894 while (len) {
d44570e4
JP		 5895 data = (u32)data_buf[cnt] & 0x000000FF;
5896 if (data)
5897 valid = (u32)(data << 24);
5898 else
1da177e4
LT		 5899 valid = data;
5900
5901 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5902 DBG_PRINT(ERR_DBG,
5903 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5904 DBG_PRINT(ERR_DBG,
5905 "write into the specified offset\n");
5906 return -EFAULT;
5907 }
5908 cnt++;
5909 len--;
5910 }
5911
5912 return 0;
5913}
5914
5915/**
20346722 5916 * s2io_register_test - reads and writes into all clock domains.
5917 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5918 * s2io_nic structure.
5919 * @data : variable that returns the result of each of the test conducted b
5920 * by the driver.
5921 * Description:
5922 * Read and write into all clock domains. The NIC has 3 clock domains,
5923 * see that registers in all the three regions are accessible.
5924 * Return value:
5925 * 0 on success.
5926 */
5927
d44570e4 5928static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 5929{
1ee6dd77 5930 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5931 u64 val64 = 0, exp_val;
1da177e4
LT		 5932 int fail = 0;
5933
20346722 5934 val64 = readq(&bar0->pif_rd_swapper_fb);
5935 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5936 fail = 1;
5937 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5938 }
5939
5940 val64 = readq(&bar0->rmac_pause_cfg);
5941 if (val64 != 0xc000ffff00000000ULL) {
5942 fail = 1;
5943 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5944 }
5945
5946 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5947 if (sp->device_type == XFRAME_II_DEVICE)
5948 exp_val = 0x0404040404040404ULL;
5949 else
5950 exp_val = 0x0808080808080808ULL;
5951 if (val64 != exp_val) {
1da177e4
LT		 5952 fail = 1;
5953 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5954 }
5955
5956 val64 = readq(&bar0->xgxs_efifo_cfg);
5957 if (val64 != 0x000000001923141EULL) {
5958 fail = 1;
5959 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5960 }
5961
5962 val64 = 0x5A5A5A5A5A5A5A5AULL;
5963 writeq(val64, &bar0->xmsi_data);
5964 val64 = readq(&bar0->xmsi_data);
5965 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5966 fail = 1;
5967 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5968 }
5969
5970 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5971 writeq(val64, &bar0->xmsi_data);
5972 val64 = readq(&bar0->xmsi_data);
5973 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5974 fail = 1;
5975 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5976 }
5977
5978 *data = fail;
ad4ebed0 5979 return fail;
1da177e4
LT		 5980}
5981
5982/**
20346722 5983 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5984 * @sp : private member of the device structure, which is a pointer to the
5985 * s2io_nic structure.
5986 * @data:variable that returns the result of each of the test conducted by
5987 * the driver.
5988 * Description:
20346722 5989 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5990 * register.
5991 * Return value:
5992 * 0 on success.
5993 */
5994
d44570e4 5995static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 5996{
5997 int fail = 0;
ad4ebed0 5998 u64 ret_data, org_4F0, org_7F0;
5999 u8 saved_4F0 = 0, saved_7F0 = 0;
6000 struct net_device *dev = sp->dev;
1da177e4
LT		 6001
6002 /* Test Write Error at offset 0 */
ad4ebed0 6003 /* Note that SPI interface allows write access to all areas
6004 * of EEPROM. Hence doing all negative testing only for Xframe I.
6005 */
6006 if (sp->device_type == XFRAME_I_DEVICE)
6007 if (!write_eeprom(sp, 0, 0, 3))
6008 fail = 1;
6009
6010 /* Save current values at offsets 0x4F0 and 0x7F0 */
6011 if (!read_eeprom(sp, 0x4F0, &org_4F0))
6012 saved_4F0 = 1;
6013 if (!read_eeprom(sp, 0x7F0, &org_7F0))
6014 saved_7F0 = 1;
1da177e4
LT		 6015
6016 /* Test Write at offset 4f0 */
ad4ebed0 6017 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 6018 fail = 1;
6019 if (read_eeprom(sp, 0x4F0, &ret_data))
6020 fail = 1;
6021
ad4ebed0 6022 if (ret_data != 0x012345) {
26b7625c 6023 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
d44570e4
JP		 6024 "Data written %llx Data read %llx\n",
6025 dev->name, (unsigned long long)0x12345,
6026 (unsigned long long)ret_data);
1da177e4 6027 fail = 1;
ad4ebed0 6028 }
1da177e4
LT		 6029
6030 /* Reset the EEPROM data go FFFF */
ad4ebed0 6031 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 6032
6033 /* Test Write Request Error at offset 0x7c */
ad4ebed0 6034 if (sp->device_type == XFRAME_I_DEVICE)
6035 if (!write_eeprom(sp, 0x07C, 0, 3))
6036 fail = 1;
1da177e4 6037
ad4ebed0 6038 /* Test Write Request at offset 0x7f0 */
6039 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 6040 fail = 1;
ad4ebed0 6041 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 6042 fail = 1;
6043
ad4ebed0 6044 if (ret_data != 0x012345) {
26b7625c 6045 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
d44570e4
JP		 6046 "Data written %llx Data read %llx\n",
6047 dev->name, (unsigned long long)0x12345,
6048 (unsigned long long)ret_data);
1da177e4 6049 fail = 1;
ad4ebed0 6050 }
1da177e4
LT		 6051
6052 /* Reset the EEPROM data go FFFF */
ad4ebed0 6053 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 6054
ad4ebed0 6055 if (sp->device_type == XFRAME_I_DEVICE) {
6056 /* Test Write Error at offset 0x80 */
6057 if (!write_eeprom(sp, 0x080, 0, 3))
6058 fail = 1;
1da177e4 6059
ad4ebed0 6060 /* Test Write Error at offset 0xfc */
6061 if (!write_eeprom(sp, 0x0FC, 0, 3))
6062 fail = 1;
1da177e4 6063
ad4ebed0 6064 /* Test Write Error at offset 0x100 */
6065 if (!write_eeprom(sp, 0x100, 0, 3))
6066 fail = 1;
1da177e4 6067
ad4ebed0 6068 /* Test Write Error at offset 4ec */
6069 if (!write_eeprom(sp, 0x4EC, 0, 3))
6070 fail = 1;
6071 }
6072
6073 /* Restore values at offsets 0x4F0 and 0x7F0 */
6074 if (saved_4F0)
6075 write_eeprom(sp, 0x4F0, org_4F0, 3);
6076 if (saved_7F0)
6077 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 6078
6079 *data = fail;
ad4ebed0 6080 return fail;
1da177e4
LT		 6081}
6082
6083/**
6084 * s2io_bist_test - invokes the MemBist test of the card .
20346722 6085 * @sp : private member of the device structure, which is a pointer to the
1da177e4 6086 * s2io_nic structure.
20346722 6087 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 6088 * the driver.
6089 * Description:
6090 * This invokes the MemBist test of the card. We give around
6091 * 2 secs time for the Test to complete. If it's still not complete
20346722 6092 * within this peiod, we consider that the test failed.
1da177e4
LT		 6093 * Return value:
6094 * 0 on success and -1 on failure.
6095 */
6096
d44570e4 6097static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
1da177e4
LT		 6098{
6099 u8 bist = 0;
6100 int cnt = 0, ret = -1;
6101
6102 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6103 bist |= PCI_BIST_START;
6104 pci_write_config_word(sp->pdev, PCI_BIST, bist);
6105
6106 while (cnt < 20) {
6107 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6108 if (!(bist & PCI_BIST_START)) {
6109 *data = (bist & PCI_BIST_CODE_MASK);
6110 ret = 0;
6111 break;
6112 }
6113 msleep(100);
6114 cnt++;
6115 }
6116
6117 return ret;
6118}
6119
6120/**
20346722 6121 * s2io-link_test - verifies the link state of the nic
6122 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 6123 * s2io_nic structure.
6124 * @data: variable that returns the result of each of the test conducted by
6125 * the driver.
6126 * Description:
20346722 6127 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 6128 * argument 'data' appropriately.
6129 * Return value:
6130 * 0 on success.
6131 */
6132
d44570e4 6133static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6134{
1ee6dd77 6135 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 6136 u64 val64;
6137
6138 val64 = readq(&bar0->adapter_status);
d44570e4 6139 if (!(LINK_IS_UP(val64)))
1da177e4 6140 *data = 1;
c92ca04b
AR		 6141 else
6142 *data = 0;
1da177e4 6143
b41477f3 6144 return *data;
1da177e4
LT		 6145}
6146
6147/**
20346722 6148 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6149 * @sp - private member of the device structure, which is a pointer to the
1da177e4 6150 * s2io_nic structure.
20346722 6151 * @data - variable that returns the result of each of the test
1da177e4
LT		 6152 * conducted by the driver.
6153 * Description:
20346722 6154 * This is one of the offline test that tests the read and write
1da177e4
LT		 6155 * access to the RldRam chip on the NIC.
6156 * Return value:
6157 * 0 on success.
6158 */
6159
d44570e4 6160static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
1da177e4 6161{
1ee6dd77 6162 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 6163 u64 val64;
ad4ebed0 6164 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 6165
6166 val64 = readq(&bar0->adapter_control);
6167 val64 &= ~ADAPTER_ECC_EN;
6168 writeq(val64, &bar0->adapter_control);
6169
6170 val64 = readq(&bar0->mc_rldram_test_ctrl);
6171 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 6172 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6173
6174 val64 = readq(&bar0->mc_rldram_mrs);
6175 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6176 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6177
6178 val64 |= MC_RLDRAM_MRS_ENABLE;
6179 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6180
6181 while (iteration < 2) {
6182 val64 = 0x55555555aaaa0000ULL;
d44570e4 6183 if (iteration == 1)
1da177e4 6184 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6185 writeq(val64, &bar0->mc_rldram_test_d0);
6186
6187 val64 = 0xaaaa5a5555550000ULL;
d44570e4 6188 if (iteration == 1)
1da177e4 6189 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6190 writeq(val64, &bar0->mc_rldram_test_d1);
6191
6192 val64 = 0x55aaaaaaaa5a0000ULL;
d44570e4 6193 if (iteration == 1)
1da177e4 6194 val64 ^= 0xFFFFFFFFFFFF0000ULL;
1da177e4
LT		 6195 writeq(val64, &bar0->mc_rldram_test_d2);
6196
ad4ebed0 6197 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6198 writeq(val64, &bar0->mc_rldram_test_add);
6199
d44570e4
JP		 6200 val64 = MC_RLDRAM_TEST_MODE |
6201 MC_RLDRAM_TEST_WRITE |
6202 MC_RLDRAM_TEST_GO;
ad4ebed0 6203 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6204
6205 for (cnt = 0; cnt < 5; cnt++) {
6206 val64 = readq(&bar0->mc_rldram_test_ctrl);
6207 if (val64 & MC_RLDRAM_TEST_DONE)
6208 break;
6209 msleep(200);
6210 }
6211
6212 if (cnt == 5)
6213 break;
6214
ad4ebed0 6215 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6216 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6217
6218 for (cnt = 0; cnt < 5; cnt++) {
6219 val64 = readq(&bar0->mc_rldram_test_ctrl);
6220 if (val64 & MC_RLDRAM_TEST_DONE)
6221 break;
6222 msleep(500);
6223 }
6224
6225 if (cnt == 5)
6226 break;
6227
6228 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6229 if (!(val64 & MC_RLDRAM_TEST_PASS))
6230 test_fail = 1;
1da177e4
LT		 6231
6232 iteration++;
6233 }
6234
ad4ebed0 6235 *data = test_fail;
1da177e4 6236
ad4ebed0 6237 /* Bring the adapter out of test mode */
6238 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6239
6240 return test_fail;
1da177e4
LT		 6241}
6242
6243/**
6244 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6245 * @sp : private member of the device structure, which is a pointer to the
6246 * s2io_nic structure.
6247 * @ethtest : pointer to a ethtool command specific structure that will be
6248 * returned to the user.
20346722 6249 * @data : variable that returns the result of each of the test
1da177e4
LT		 6250 * conducted by the driver.
6251 * Description:
6252 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6253 * the health of the card.
6254 * Return value:
6255 * void
6256 */
6257
6258static void s2io_ethtool_test(struct net_device *dev,
6259 struct ethtool_test *ethtest,
d44570e4 6260 uint64_t *data)
1da177e4 6261{
4cf1653a 6262 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6263 int orig_state = netif_running(sp->dev);
6264
6265 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6266 /* Offline Tests. */
20346722 6267 if (orig_state)
1da177e4 6268 s2io_close(sp->dev);
1da177e4
LT		 6269
6270 if (s2io_register_test(sp, &data[0]))
6271 ethtest->flags |= ETH_TEST_FL_FAILED;
6272
6273 s2io_reset(sp);
1da177e4
LT		 6274
6275 if (s2io_rldram_test(sp, &data[3]))
6276 ethtest->flags |= ETH_TEST_FL_FAILED;
6277
6278 s2io_reset(sp);
1da177e4
LT		 6279
6280 if (s2io_eeprom_test(sp, &data[1]))
6281 ethtest->flags |= ETH_TEST_FL_FAILED;
6282
6283 if (s2io_bist_test(sp, &data[4]))
6284 ethtest->flags |= ETH_TEST_FL_FAILED;
6285
6286 if (orig_state)
6287 s2io_open(sp->dev);
6288
6289 data[2] = 0;
6290 } else {
6291 /* Online Tests. */
6292 if (!orig_state) {
d44570e4 6293 DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
1da177e4
LT		 6294 dev->name);
6295 data[0] = -1;
6296 data[1] = -1;
6297 data[2] = -1;
6298 data[3] = -1;
6299 data[4] = -1;
6300 }
6301
6302 if (s2io_link_test(sp, &data[2]))
6303 ethtest->flags |= ETH_TEST_FL_FAILED;
6304
6305 data[0] = 0;
6306 data[1] = 0;
6307 data[3] = 0;
6308 data[4] = 0;
6309 }
6310}
6311
6312static void s2io_get_ethtool_stats(struct net_device *dev,
6313 struct ethtool_stats *estats,
d44570e4 6314 u64 *tmp_stats)
1da177e4 6315{
8116f3cf 6316 int i = 0, k;
4cf1653a 6317 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c
JP		 6318 struct stat_block *stats = sp->mac_control.stats_info;
6319 struct swStat *swstats = &stats->sw_stat;
6320 struct xpakStat *xstats = &stats->xpak_stat;
1da177e4 6321
7ba013ac 6322 s2io_updt_stats(sp);
541ae68f 6323 tmp_stats[i++] =
ffb5df6c
JP		 6324 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32 |
6325 le32_to_cpu(stats->tmac_frms);
541ae68f 6326 tmp_stats[i++] =
ffb5df6c
JP		 6327 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6328 le32_to_cpu(stats->tmac_data_octets);
6329 tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
541ae68f 6330 tmp_stats[i++] =
ffb5df6c
JP		 6331 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6332 le32_to_cpu(stats->tmac_mcst_frms);
541ae68f 6333 tmp_stats[i++] =
ffb5df6c
JP		 6334 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6335 le32_to_cpu(stats->tmac_bcst_frms);
6336 tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
bd1034f0 6337 tmp_stats[i++] =
ffb5df6c
JP		 6338 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6339 le32_to_cpu(stats->tmac_ttl_octets);
bd1034f0 6340 tmp_stats[i++] =
ffb5df6c
JP		 6341 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6342 le32_to_cpu(stats->tmac_ucst_frms);
d44570e4 6343 tmp_stats[i++] =
ffb5df6c
JP		 6344 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6345 le32_to_cpu(stats->tmac_nucst_frms);
541ae68f 6346 tmp_stats[i++] =
ffb5df6c
JP		 6347 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6348 le32_to_cpu(stats->tmac_any_err_frms);
6349 tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6350 tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
541ae68f 6351 tmp_stats[i++] =
ffb5df6c
JP		 6352 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6353 le32_to_cpu(stats->tmac_vld_ip);
541ae68f 6354 tmp_stats[i++] =
ffb5df6c
JP		 6355 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6356 le32_to_cpu(stats->tmac_drop_ip);
541ae68f 6357 tmp_stats[i++] =
ffb5df6c
JP		 6358 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6359 le32_to_cpu(stats->tmac_icmp);
541ae68f 6360 tmp_stats[i++] =
ffb5df6c
JP		 6361 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6362 le32_to_cpu(stats->tmac_rst_tcp);
6363 tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6364 tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6365 le32_to_cpu(stats->tmac_udp);
541ae68f 6366 tmp_stats[i++] =
ffb5df6c
JP		 6367 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6368 le32_to_cpu(stats->rmac_vld_frms);
541ae68f 6369 tmp_stats[i++] =
ffb5df6c
JP		 6370 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6371 le32_to_cpu(stats->rmac_data_octets);
6372 tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6373 tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
541ae68f 6374 tmp_stats[i++] =
ffb5df6c
JP		 6375 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6376 le32_to_cpu(stats->rmac_vld_mcst_frms);
541ae68f 6377 tmp_stats[i++] =
ffb5df6c
JP		 6378 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6379 le32_to_cpu(stats->rmac_vld_bcst_frms);
6380 tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6381 tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6382 tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6383 tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6384 tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
d44570e4 6385 tmp_stats[i++] =
ffb5df6c
JP		 6386 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6387 le32_to_cpu(stats->rmac_ttl_octets);
bd1034f0 6388 tmp_stats[i++] =
ffb5df6c
JP		 6389 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6390 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
d44570e4 6391 tmp_stats[i++] =
ffb5df6c
JP		 6392 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6393 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
541ae68f 6394 tmp_stats[i++] =
ffb5df6c
JP		 6395 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6396 le32_to_cpu(stats->rmac_discarded_frms);
d44570e4 6397 tmp_stats[i++] =
ffb5df6c
JP		 6398 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6399 << 32 | le32_to_cpu(stats->rmac_drop_events);
6400 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6401 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
541ae68f 6402 tmp_stats[i++] =
ffb5df6c
JP		 6403 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6404 le32_to_cpu(stats->rmac_usized_frms);
541ae68f 6405 tmp_stats[i++] =
ffb5df6c
JP		 6406 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6407 le32_to_cpu(stats->rmac_osized_frms);
541ae68f 6408 tmp_stats[i++] =
ffb5df6c
JP		 6409 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6410 le32_to_cpu(stats->rmac_frag_frms);
541ae68f 6411 tmp_stats[i++] =
ffb5df6c
JP		 6412 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6413 le32_to_cpu(stats->rmac_jabber_frms);
6414 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6415 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6416 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6417 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6418 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6419 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
bd1034f0 6420 tmp_stats[i++] =
ffb5df6c
JP		 6421 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6422 le32_to_cpu(stats->rmac_ip);
6423 tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6424 tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
bd1034f0 6425 tmp_stats[i++] =
ffb5df6c
JP		 6426 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6427 le32_to_cpu(stats->rmac_drop_ip);
bd1034f0 6428 tmp_stats[i++] =
ffb5df6c
JP		 6429 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6430 le32_to_cpu(stats->rmac_icmp);
6431 tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
bd1034f0 6432 tmp_stats[i++] =
ffb5df6c
JP		 6433 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6434 le32_to_cpu(stats->rmac_udp);
541ae68f 6435 tmp_stats[i++] =
ffb5df6c
JP		 6436 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6437 le32_to_cpu(stats->rmac_err_drp_udp);
6438 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6439 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6440 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6441 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6442 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6443 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6444 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6445 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6446 tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6447 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6448 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6449 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6450 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6451 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6452 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6453 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6454 tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
541ae68f 6455 tmp_stats[i++] =
ffb5df6c
JP		 6456 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6457 le32_to_cpu(stats->rmac_pause_cnt);
6458 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6459 tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
541ae68f 6460 tmp_stats[i++] =
ffb5df6c
JP		 6461 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6462 le32_to_cpu(stats->rmac_accepted_ip);
6463 tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6464 tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6465 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6466 tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6467 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6468 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6469 tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6470 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6471 tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6472 tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6473 tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6474 tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6475 tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6476 tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6477 tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6478 tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6479 tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6480 tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6481 tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
fa1f0cb3
SS		 6482
6483 /* Enhanced statistics exist only for Hercules */
d44570e4 6484 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6485 tmp_stats[i++] =
ffb5df6c 6486 le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
fa1f0cb3 6487 tmp_stats[i++] =
ffb5df6c 6488 le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
fa1f0cb3 6489 tmp_stats[i++] =
ffb5df6c
JP		 6490 le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6491 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6492 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6493 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6494 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6495 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6496 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6497 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6498 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6499 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6500 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6501 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6502 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6503 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
fa1f0cb3
SS		 6504 }
6505
7ba013ac 6506 tmp_stats[i++] = 0;
ffb5df6c
JP		 6507 tmp_stats[i++] = swstats->single_ecc_errs;
6508 tmp_stats[i++] = swstats->double_ecc_errs;
6509 tmp_stats[i++] = swstats->parity_err_cnt;
6510 tmp_stats[i++] = swstats->serious_err_cnt;
6511 tmp_stats[i++] = swstats->soft_reset_cnt;
6512 tmp_stats[i++] = swstats->fifo_full_cnt;
8116f3cf 6513 for (k = 0; k < MAX_RX_RINGS; k++)
ffb5df6c
JP		 6514 tmp_stats[i++] = swstats->ring_full_cnt[k];
6515 tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6516 tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6517 tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6518 tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6519 tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6520 tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6521 tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6522 tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6523 tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6524 tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6525 tmp_stats[i++] = xstats->warn_laser_output_power_high;
6526 tmp_stats[i++] = xstats->warn_laser_output_power_low;
6527 tmp_stats[i++] = swstats->clubbed_frms_cnt;
6528 tmp_stats[i++] = swstats->sending_both;
6529 tmp_stats[i++] = swstats->outof_sequence_pkts;
6530 tmp_stats[i++] = swstats->flush_max_pkts;
6531 if (swstats->num_aggregations) {
6532 u64 tmp = swstats->sum_avg_pkts_aggregated;
bd1034f0 6533 int count = 0;
6aa20a22 6534 /*
bd1034f0
AR		 6535 * Since 64-bit divide does not work on all platforms,
6536 * do repeated subtraction.
6537 */
ffb5df6c
JP		 6538 while (tmp >= swstats->num_aggregations) {
6539 tmp -= swstats->num_aggregations;
bd1034f0
AR		 6540 count++;
6541 }
6542 tmp_stats[i++] = count;
d44570e4 6543 } else
bd1034f0 6544 tmp_stats[i++] = 0;
ffb5df6c
JP		 6545 tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6546 tmp_stats[i++] = swstats->pci_map_fail_cnt;
6547 tmp_stats[i++] = swstats->watchdog_timer_cnt;
6548 tmp_stats[i++] = swstats->mem_allocated;
6549 tmp_stats[i++] = swstats->mem_freed;
6550 tmp_stats[i++] = swstats->link_up_cnt;
6551 tmp_stats[i++] = swstats->link_down_cnt;
6552 tmp_stats[i++] = swstats->link_up_time;
6553 tmp_stats[i++] = swstats->link_down_time;
6554
6555 tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6556 tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6557 tmp_stats[i++] = swstats->tx_parity_err_cnt;
6558 tmp_stats[i++] = swstats->tx_link_loss_cnt;
6559 tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6560
6561 tmp_stats[i++] = swstats->rx_parity_err_cnt;
6562 tmp_stats[i++] = swstats->rx_abort_cnt;
6563 tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6564 tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6565 tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6566 tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6567 tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6568 tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6569 tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6570 tmp_stats[i++] = swstats->tda_err_cnt;
6571 tmp_stats[i++] = swstats->pfc_err_cnt;
6572 tmp_stats[i++] = swstats->pcc_err_cnt;
6573 tmp_stats[i++] = swstats->tti_err_cnt;
6574 tmp_stats[i++] = swstats->tpa_err_cnt;
6575 tmp_stats[i++] = swstats->sm_err_cnt;
6576 tmp_stats[i++] = swstats->lso_err_cnt;
6577 tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6578 tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6579 tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6580 tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6581 tmp_stats[i++] = swstats->rc_err_cnt;
6582 tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6583 tmp_stats[i++] = swstats->rpa_err_cnt;
6584 tmp_stats[i++] = swstats->rda_err_cnt;
6585 tmp_stats[i++] = swstats->rti_err_cnt;
6586 tmp_stats[i++] = swstats->mc_err_cnt;
1da177e4
LT		 6587}
6588
ac1f60db 6589static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4 6590{
d44570e4 6591 return XENA_REG_SPACE;
1da177e4
LT		 6592}
6593
6594
d44570e4 6595static u32 s2io_ethtool_get_rx_csum(struct net_device *dev)
1da177e4 6596{
4cf1653a 6597 struct s2io_nic *sp = netdev_priv(dev);
1da177e4 6598
d44570e4 6599 return sp->rx_csum;
1da177e4 6600}
ac1f60db
AB		 6601
6602static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6603{
4cf1653a 6604 struct s2io_nic *sp = netdev_priv(dev);
1da177e4
LT		 6605
6606 if (data)
6607 sp->rx_csum = 1;
6608 else
6609 sp->rx_csum = 0;
6610
6611 return 0;
6612}
ac1f60db
AB		 6613
6614static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4 6615{
d44570e4 6616 return XENA_EEPROM_SPACE;
1da177e4
LT		 6617}
6618
b9f2c044 6619static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6620{
4cf1653a 6621 struct s2io_nic *sp = netdev_priv(dev);
b9f2c044
JG		 6622
6623 switch (sset) {
6624 case ETH_SS_TEST:
6625 return S2IO_TEST_LEN;
6626 case ETH_SS_STATS:
d44570e4 6627 switch (sp->device_type) {
b9f2c044
JG		 6628 case XFRAME_I_DEVICE:
6629 return XFRAME_I_STAT_LEN;
6630 case XFRAME_II_DEVICE:
6631 return XFRAME_II_STAT_LEN;
6632 default:
6633 return 0;
6634 }
6635 default:
6636 return -EOPNOTSUPP;
6637 }
1da177e4 6638}
ac1f60db
AB		 6639
6640static void s2io_ethtool_get_strings(struct net_device *dev,
d44570e4 6641 u32 stringset, u8 *data)
1da177e4 6642{
fa1f0cb3 6643 int stat_size = 0;
4cf1653a 6644 struct s2io_nic *sp = netdev_priv(dev);
fa1f0cb3 6645
1da177e4
LT		 6646 switch (stringset) {
6647 case ETH_SS_TEST:
6648 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6649 break;
6650 case ETH_SS_STATS:
fa1f0cb3 6651 stat_size = sizeof(ethtool_xena_stats_keys);
d44570e4
JP		 6652 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6653 if (sp->device_type == XFRAME_II_DEVICE) {
fa1f0cb3 6654 memcpy(data + stat_size,
d44570e4
JP		 6655 &ethtool_enhanced_stats_keys,
6656 sizeof(ethtool_enhanced_stats_keys));
fa1f0cb3
SS		 6657 stat_size += sizeof(ethtool_enhanced_stats_keys);
6658 }
6659
6660 memcpy(data + stat_size, &ethtool_driver_stats_keys,
d44570e4 6661 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6662 }
6663}
1da177e4 6664
ac1f60db 6665static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6666{
6667 if (data)
6668 dev->features |= NETIF_F_IP_CSUM;
6669 else
6670 dev->features &= ~NETIF_F_IP_CSUM;
6671
6672 return 0;
6673}
6674
75c30b13
AR		 6675static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6676{
6677 return (dev->features & NETIF_F_TSO) != 0;
6678}
6679static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6680{
6681 if (data)
6682 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6683 else
6684 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6685
6686 return 0;
6687}
1da177e4 6688
7282d491 6689static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6690 .get_settings = s2io_ethtool_gset,
6691 .set_settings = s2io_ethtool_sset,
6692 .get_drvinfo = s2io_ethtool_gdrvinfo,
6693 .get_regs_len = s2io_ethtool_get_regs_len,
6694 .get_regs = s2io_ethtool_gregs,
6695 .get_link = ethtool_op_get_link,
6696 .get_eeprom_len = s2io_get_eeprom_len,
6697 .get_eeprom = s2io_ethtool_geeprom,
6698 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6699 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6700 .get_pauseparam = s2io_ethtool_getpause_data,
6701 .set_pauseparam = s2io_ethtool_setpause_data,
6702 .get_rx_csum = s2io_ethtool_get_rx_csum,
6703 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6704 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6705 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6706 .get_tso = s2io_ethtool_op_get_tso,
6707 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6708 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6709 .self_test = s2io_ethtool_test,
6710 .get_strings = s2io_ethtool_get_strings,
6711 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6712 .get_ethtool_stats = s2io_get_ethtool_stats,
6713 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6714};
6715
6716/**
20346722 6717 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6718 * @dev : Device pointer.
6719 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6720 * a proprietary structure used to pass information to the driver.
6721 * @cmd : This is used to distinguish between the different commands that
6722 * can be passed to the IOCTL functions.
6723 * Description:
20346722 6724 * Currently there are no special functionality supported in IOCTL, hence
6725 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6726 */
6727
ac1f60db 6728static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6729{
6730 return -EOPNOTSUPP;
6731}
6732
6733/**
6734 * s2io_change_mtu - entry point to change MTU size for the device.
6735 * @dev : device pointer.
6736 * @new_mtu : the new MTU size for the device.
6737 * Description: A driver entry point to change MTU size for the device.
6738 * Before changing the MTU the device must be stopped.
6739 * Return value:
6740 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6741 * file on failure.
6742 */
6743
ac1f60db 6744static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6745{
4cf1653a 6746 struct s2io_nic *sp = netdev_priv(dev);
9f74ffde 6747 int ret = 0;
1da177e4
LT		 6748
6749 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
d44570e4 6750 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
1da177e4
LT		 6751 return -EPERM;
6752 }
6753
1da177e4 6754 dev->mtu = new_mtu;
d8892c6e 6755 if (netif_running(dev)) {
3a3d5756 6756 s2io_stop_all_tx_queue(sp);
e6a8fee2 6757 s2io_card_down(sp);
9f74ffde
SH		 6758 ret = s2io_card_up(sp);
6759 if (ret) {
d8892c6e 6760 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
b39d66a8 6761 __func__);
9f74ffde 6762 return ret;
d8892c6e 6763 }
3a3d5756 6764 s2io_wake_all_tx_queue(sp);
d8892c6e 6765 } else { /* Device is down */
1ee6dd77 6766 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e 6767 u64 val64 = new_mtu;
6768
6769 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6770 }
1da177e4 6771
9f74ffde 6772 return ret;
1da177e4
LT		 6773}
6774
1da177e4
LT		 6775/**
6776 * s2io_set_link - Set the LInk status
6777 * @data: long pointer to device private structue
6778 * Description: Sets the link status for the adapter
6779 */
6780
c4028958 6781static void s2io_set_link(struct work_struct *work)
1da177e4 6782{
d44570e4
JP		 6783 struct s2io_nic *nic = container_of(work, struct s2io_nic,
6784 set_link_task);
1da177e4 6785 struct net_device *dev = nic->dev;
1ee6dd77 6786 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6787 register u64 val64;
6788 u16 subid;
6789
22747d6b
FR		 6790 rtnl_lock();
6791
6792 if (!netif_running(dev))
6793 goto out_unlock;
6794
92b84437 6795 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6796 /* The card is being reset, no point doing anything */
22747d6b 6797 goto out_unlock;
1da177e4
LT		 6798 }
6799
6800 subid = nic->pdev->subsystem_device;
a371a07d 6801 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6802 /*
6803 * Allow a small delay for the NICs self initiated
6804 * cleanup to complete.
6805 */
6806 msleep(100);
6807 }
1da177e4
LT		 6808
6809 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6810 if (LINK_IS_UP(val64)) {
6811 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6812 if (verify_xena_quiescence(nic)) {
6813 val64 = readq(&bar0->adapter_control);
6814 val64 |= ADAPTER_CNTL_EN;
1da177e4 6815 writeq(val64, &bar0->adapter_control);
19a60522 6816 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
d44570e4 6817 nic->device_type, subid)) {
19a60522
SS		 6818 val64 = readq(&bar0->gpio_control);
6819 val64 |= GPIO_CTRL_GPIO_0;
6820 writeq(val64, &bar0->gpio_control);
6821 val64 = readq(&bar0->gpio_control);
6822 } else {
6823 val64 |= ADAPTER_LED_ON;
6824 writeq(val64, &bar0->adapter_control);
a371a07d 6825 }
f957bcf0 6826 nic->device_enabled_once = true;
19a60522
SS		 6827 } else {
6828 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6829 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
3a3d5756 6830 s2io_stop_all_tx_queue(nic);
1da177e4 6831 }
19a60522 6832 }
92c48799
SS		 6833 val64 = readq(&bar0->adapter_control);
6834 val64 |= ADAPTER_LED_ON;
6835 writeq(val64, &bar0->adapter_control);
6836 s2io_link(nic, LINK_UP);
19a60522
SS		 6837 } else {
6838 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6839 subid)) {
6840 val64 = readq(&bar0->gpio_control);
6841 val64 &= ~GPIO_CTRL_GPIO_0;
6842 writeq(val64, &bar0->gpio_control);
6843 val64 = readq(&bar0->gpio_control);
1da177e4 6844 }
92c48799
SS		 6845 /* turn off LED */
6846 val64 = readq(&bar0->adapter_control);
d44570e4 6847 val64 = val64 & (~ADAPTER_LED_ON);
92c48799 6848 writeq(val64, &bar0->adapter_control);
19a60522 6849 s2io_link(nic, LINK_DOWN);
1da177e4 6850 }
92b84437 6851 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6852
6853out_unlock:
d8d70caf 6854 rtnl_unlock();
1da177e4
LT		 6855}
6856
1ee6dd77 6857static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
d44570e4
JP		 6858 struct buffAdd *ba,
6859 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6860 u64 *temp2, int size)
5d3213cc
AR		 6861{
6862 struct net_device *dev = sp->dev;
491abf25 6863 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6864
6865 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6866 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6867 /* allocate skb */
6868 if (*skb) {
6869 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6870 /*
6871 * As Rx frame are not going to be processed,
6872 * using same mapped address for the Rxd
6873 * buffer pointer
6874 */
6d517a27 6875 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6876 } else {
6877 *skb = dev_alloc_skb(size);
6878 if (!(*skb)) {
0c61ed5f 6879 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6880 DBG_PRINT(INFO_DBG, "memory to allocate ");
6881 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
ffb5df6c 6882 stats->mem_alloc_fail_cnt++;
5d3213cc
AR		 6883 return -ENOMEM ;
6884 }
ffb5df6c 6885 stats->mem_allocated += (*skb)->truesize;
5d3213cc
AR		 6886 /* storing the mapped addr in a temp variable
6887 * such it will be used for next rxd whose
6888 * Host Control is NULL
6889 */
6d517a27 6890 rxdp1->Buffer0_ptr = *temp0 =
d44570e4
JP		 6891 pci_map_single(sp->pdev, (*skb)->data,
6892 size - NET_IP_ALIGN,
6893 PCI_DMA_FROMDEVICE);
8d8bb39b 6894 if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
491abf25 6895 goto memalloc_failed;
5d3213cc
AR		 6896 rxdp->Host_Control = (unsigned long) (*skb);
6897 }
6898 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6899 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6900 /* Two buffer Mode */
6901 if (*skb) {
6d517a27
VP		 6902 rxdp3->Buffer2_ptr = *temp2;
6903 rxdp3->Buffer0_ptr = *temp0;
6904 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6905 } else {
6906 *skb = dev_alloc_skb(size);
2ceaac75 6907 if (!(*skb)) {
c53d4945
SH		 6908 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6909 DBG_PRINT(INFO_DBG, "memory to allocate ");
6910 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
ffb5df6c 6911 stats->mem_alloc_fail_cnt++;
2ceaac75
DR		 6912 return -ENOMEM;
6913 }
ffb5df6c 6914 stats->mem_allocated += (*skb)->truesize;
6d517a27 6915 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6916 pci_map_single(sp->pdev, (*skb)->data,
6917 dev->mtu + 4,
6918 PCI_DMA_FROMDEVICE);
8d8bb39b 6919 if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
491abf25 6920 goto memalloc_failed;
6d517a27 6921 rxdp3->Buffer0_ptr = *temp0 =
d44570e4
JP		 6922 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6923 PCI_DMA_FROMDEVICE);
8d8bb39b 6924 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6925 rxdp3->Buffer0_ptr)) {
6926 pci_unmap_single(sp->pdev,
6927 (dma_addr_t)rxdp3->Buffer2_ptr,
6928 dev->mtu + 4,
6929 PCI_DMA_FROMDEVICE);
491abf25
VP		 6930 goto memalloc_failed;
6931 }
5d3213cc
AR		 6932 rxdp->Host_Control = (unsigned long) (*skb);
6933
6934 /* Buffer-1 will be dummy buffer not used */
6d517a27 6935 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6936 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
d44570e4 6937 PCI_DMA_FROMDEVICE);
8d8bb39b 6938 if (pci_dma_mapping_error(sp->pdev,
d44570e4
JP		 6939 rxdp3->Buffer1_ptr)) {
6940 pci_unmap_single(sp->pdev,
6941 (dma_addr_t)rxdp3->Buffer0_ptr,
6942 BUF0_LEN, PCI_DMA_FROMDEVICE);
6943 pci_unmap_single(sp->pdev,
6944 (dma_addr_t)rxdp3->Buffer2_ptr,
6945 dev->mtu + 4,
6946 PCI_DMA_FROMDEVICE);
491abf25
VP		 6947 goto memalloc_failed;
6948 }
5d3213cc
AR		 6949 }
6950 }
6951 return 0;
d44570e4
JP		 6952
6953memalloc_failed:
6954 stats->pci_map_fail_cnt++;
6955 stats->mem_freed += (*skb)->truesize;
6956 dev_kfree_skb(*skb);
6957 return -ENOMEM;
5d3213cc 6958}
491abf25 6959
1ee6dd77
RB		 6960static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6961 int size)
5d3213cc
AR		 6962{
6963 struct net_device *dev = sp->dev;
6964 if (sp->rxd_mode == RXD_MODE_1) {
d44570e4 6965 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
5d3213cc
AR		 6966 } else if (sp->rxd_mode == RXD_MODE_3B) {
6967 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6968 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
d44570e4 6969 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
5d3213cc
AR		 6970 }
6971}
6972
1ee6dd77 6973static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6974{
6975 int i, j, k, blk_cnt = 0, size;
5d3213cc 6976 struct config_param *config = &sp->config;
ffb5df6c 6977 struct mac_info *mac_control = &sp->mac_control;
5d3213cc 6978 struct net_device *dev = sp->dev;
1ee6dd77 6979 struct RxD_t *rxdp = NULL;
5d3213cc 6980 struct sk_buff *skb = NULL;
1ee6dd77 6981 struct buffAdd *ba = NULL;
5d3213cc
AR		 6982 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6983
6984 /* Calculate the size based on ring mode */
6985 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6986 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6987 if (sp->rxd_mode == RXD_MODE_1)
6988 size += NET_IP_ALIGN;
6989 else if (sp->rxd_mode == RXD_MODE_3B)
6990 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6991
6992 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 6993 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6994 struct ring_info *ring = &mac_control->rings[i];
6995
d44570e4 6996 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
5d3213cc
AR		 6997
6998 for (j = 0; j < blk_cnt; j++) {
6999 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
d44570e4
JP		 7000 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
7001 if (sp->rxd_mode == RXD_MODE_3B)
13d866a9 7002 ba = &ring->ba[j][k];
d44570e4
JP		 7003 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
7004 (u64 *)&temp0_64,
7005 (u64 *)&temp1_64,
7006 (u64 *)&temp2_64,
7007 size) == -ENOMEM) {
ac1f90d6
SS		 7008 return 0;
7009 }
5d3213cc
AR		 7010
7011 set_rxd_buffer_size(sp, rxdp, size);
7012 wmb();
7013 /* flip the Ownership bit to Hardware */
7014 rxdp->Control_1 |= RXD_OWN_XENA;
7015 }
7016 }
7017 }
7018 return 0;
7019
7020}
7021
d44570e4 7022static int s2io_add_isr(struct s2io_nic *sp)
1da177e4 7023{
e6a8fee2 7024 int ret = 0;
c92ca04b 7025 struct net_device *dev = sp->dev;
e6a8fee2 7026 int err = 0;
1da177e4 7027
eaae7f72 7028 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7029 ret = s2io_enable_msi_x(sp);
7030 if (ret) {
7031 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 7032 sp->config.intr_type = INTA;
20346722 7033 }
1da177e4 7034
d44570e4
JP		 7035 /*
7036 * Store the values of the MSIX table in
7037 * the struct s2io_nic structure
7038 */
e6a8fee2 7039 store_xmsi_data(sp);
c92ca04b 7040
e6a8fee2 7041 /* After proper initialization of H/W, register ISR */
eaae7f72 7042 if (sp->config.intr_type == MSI_X) {
ac731ab6
SH		 7043 int i, msix_rx_cnt = 0;
7044
f61e0a35
SH		 7045 for (i = 0; i < sp->num_entries; i++) {
7046 if (sp->s2io_entries[i].in_use == MSIX_FLG) {
7047 if (sp->s2io_entries[i].type ==
d44570e4 7048 MSIX_RING_TYPE) {
ac731ab6
SH		 7049 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
7050 dev->name, i);
7051 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7052 s2io_msix_ring_handle,
7053 0,
7054 sp->desc[i],
7055 sp->s2io_entries[i].arg);
ac731ab6 7056 } else if (sp->s2io_entries[i].type ==
d44570e4 7057 MSIX_ALARM_TYPE) {
ac731ab6 7058 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
d44570e4 7059 dev->name, i);
ac731ab6 7060 err = request_irq(sp->entries[i].vector,
d44570e4
JP		 7061 s2io_msix_fifo_handle,
7062 0,
7063 sp->desc[i],
7064 sp->s2io_entries[i].arg);
ac731ab6 7065
fb6a825b 7066 }
ac731ab6
SH		 7067 /* if either data or addr is zero print it. */
7068 if (!(sp->msix_info[i].addr &&
d44570e4 7069 sp->msix_info[i].data)) {
ac731ab6 7070 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7071 "%s @Addr:0x%llx Data:0x%llx\n",
7072 sp->desc[i],
7073 (unsigned long long)
7074 sp->msix_info[i].addr,
7075 (unsigned long long)
7076 ntohl(sp->msix_info[i].data));
ac731ab6 7077 } else
fb6a825b 7078 msix_rx_cnt++;
ac731ab6
SH		 7079 if (err) {
7080 remove_msix_isr(sp);
7081
7082 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7083 "%s:MSI-X-%d registration "
7084 "failed\n", dev->name, i);
ac731ab6
SH		 7085
7086 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7087 "%s: Defaulting to INTA\n",
7088 dev->name);
ac731ab6
SH		 7089 sp->config.intr_type = INTA;
7090 break;
fb6a825b 7091 }
ac731ab6
SH		 7092 sp->s2io_entries[i].in_use =
7093 MSIX_REGISTERED_SUCCESS;
c92ca04b 7094 }
e6a8fee2 7095 }
18b2b7bd 7096 if (!err) {
6cef2b8e 7097 pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
ac731ab6 7098 DBG_PRINT(INFO_DBG, "MSI-X-TX entries enabled"
d44570e4 7099 " through alarm vector\n");
18b2b7bd 7100 }
e6a8fee2 7101 }
eaae7f72 7102 if (sp->config.intr_type == INTA) {
d44570e4
JP		 7103 err = request_irq((int)sp->pdev->irq, s2io_isr, IRQF_SHARED,
7104 sp->name, dev);
e6a8fee2
AR		 7105 if (err) {
7106 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7107 dev->name);
7108 return -1;
7109 }
7110 }
7111 return 0;
7112}
d44570e4
JP		 7113
7114static void s2io_rem_isr(struct s2io_nic *sp)
e6a8fee2 7115{
18b2b7bd
SH		 7116 if (sp->config.intr_type == MSI_X)
7117 remove_msix_isr(sp);
7118 else
7119 remove_inta_isr(sp);
e6a8fee2
AR		 7120}
7121
d44570e4 7122static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
e6a8fee2
AR		 7123{
7124 int cnt = 0;
1ee6dd77 7125 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2 7126 register u64 val64 = 0;
5f490c96
SH		 7127 struct config_param *config;
7128 config = &sp->config;
e6a8fee2 7129
9f74ffde
SH		 7130 if (!is_s2io_card_up(sp))
7131 return;
7132
e6a8fee2
AR		 7133 del_timer_sync(&sp->alarm_timer);
7134 /* If s2io_set_link task is executing, wait till it completes. */
d44570e4 7135 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
e6a8fee2 7136 msleep(50);
92b84437 7137 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7138
5f490c96 7139 /* Disable napi */
f61e0a35
SH		 7140 if (sp->config.napi) {
7141 int off = 0;
7142 if (config->intr_type == MSI_X) {
7143 for (; off < sp->config.rx_ring_num; off++)
7144 napi_disable(&sp->mac_control.rings[off].napi);
d44570e4 7145 }
f61e0a35
SH		 7146 else
7147 napi_disable(&sp->napi);
7148 }
5f490c96 7149
e6a8fee2 7150 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7151 if (do_io)
7152 stop_nic(sp);
e6a8fee2
AR		 7153
7154 s2io_rem_isr(sp);
1da177e4 7155
01e16faa
SH		 7156 /* stop the tx queue, indicate link down */
7157 s2io_link(sp, LINK_DOWN);
7158
1da177e4 7159 /* Check if the device is Quiescent and then Reset the NIC */
d44570e4 7160 while (do_io) {
5d3213cc
AR		 7161 /* As per the HW requirement we need to replenish the
7162 * receive buffer to avoid the ring bump. Since there is
7163 * no intention of processing the Rx frame at this pointwe are
7164 * just settting the ownership bit of rxd in Each Rx
7165 * ring to HW and set the appropriate buffer size
7166 * based on the ring mode
7167 */
7168 rxd_owner_bit_reset(sp);
7169
1da177e4 7170 val64 = readq(&bar0->adapter_status);
19a60522 7171 if (verify_xena_quiescence(sp)) {
d44570e4
JP		 7172 if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7173 break;
1da177e4
LT		 7174 }
7175
7176 msleep(50);
7177 cnt++;
7178 if (cnt == 10) {
d44570e4 7179 DBG_PRINT(ERR_DBG, "s2io_close:Device not Quiescent ");
1da177e4 7180 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
d44570e4 7181 (unsigned long long)val64);
1da177e4
LT		 7182 break;
7183 }
d796fdb7
LV		 7184 }
7185 if (do_io)
7186 s2io_reset(sp);
1da177e4 7187
7ba013ac 7188 /* Free all Tx buffers */
1da177e4 7189 free_tx_buffers(sp);
7ba013ac 7190
7191 /* Free all Rx buffers */
1da177e4
LT		 7192 free_rx_buffers(sp);
7193
92b84437 7194 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7195}
7196
d44570e4 7197static void s2io_card_down(struct s2io_nic *sp)
d796fdb7
LV		 7198{
7199 do_s2io_card_down(sp, 1);
7200}
7201
d44570e4 7202static int s2io_card_up(struct s2io_nic *sp)
1da177e4 7203{
cc6e7c44 7204 int i, ret = 0;
1da177e4 7205 struct config_param *config;
ffb5df6c 7206 struct mac_info *mac_control;
d44570e4 7207 struct net_device *dev = (struct net_device *)sp->dev;
e6a8fee2 7208 u16 interruptible;
1da177e4
LT		 7209
7210 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7211 ret = init_nic(sp);
7212 if (ret != 0) {
1da177e4
LT		 7213 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7214 dev->name);
9f74ffde
SH		 7215 if (ret != -EIO)
7216 s2io_reset(sp);
7217 return ret;
1da177e4
LT		 7218 }
7219
20346722 7220 /*
7221 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7222 * Rx ring and initializing buffers into 30 Rx blocks
7223 */
1da177e4 7224 config = &sp->config;
ffb5df6c 7225 mac_control = &sp->mac_control;
1da177e4
LT		 7226
7227 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7228 struct ring_info *ring = &mac_control->rings[i];
7229
7230 ring->mtu = dev->mtu;
7231 ret = fill_rx_buffers(sp, ring, 1);
0425b46a 7232 if (ret) {
1da177e4
LT		 7233 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7234 dev->name);
7235 s2io_reset(sp);
7236 free_rx_buffers(sp);
7237 return -ENOMEM;
7238 }
7239 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
13d866a9 7240 ring->rx_bufs_left);
1da177e4 7241 }
5f490c96
SH		 7242
7243 /* Initialise napi */
f61e0a35 7244 if (config->napi) {
f61e0a35
SH		 7245 if (config->intr_type == MSI_X) {
7246 for (i = 0; i < sp->config.rx_ring_num; i++)
7247 napi_enable(&sp->mac_control.rings[i].napi);
7248 } else {
7249 napi_enable(&sp->napi);
7250 }
7251 }
5f490c96 7252
19a60522
SS		 7253 /* Maintain the state prior to the open */
7254 if (sp->promisc_flg)
7255 sp->promisc_flg = 0;
7256 if (sp->m_cast_flg) {
7257 sp->m_cast_flg = 0;
d44570e4 7258 sp->all_multi_pos = 0;
19a60522 7259 }
1da177e4
LT		 7260
7261 /* Setting its receive mode */
7262 s2io_set_multicast(dev);
7263
7d3d0439 7264 if (sp->lro) {
b41477f3 7265 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439 7266 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
d44570e4 7267 /* Check if we can use (if specified) user provided value */
7d3d0439
RA		 7268 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7269 sp->lro_max_aggr_per_sess = lro_max_pkts;
7270 }
7271
1da177e4
LT		 7272 /* Enable Rx Traffic and interrupts on the NIC */
7273 if (start_nic(sp)) {
7274 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7275 s2io_reset(sp);
e6a8fee2
AR		 7276 free_rx_buffers(sp);
7277 return -ENODEV;
7278 }
7279
7280 /* Add interrupt service routine */
7281 if (s2io_add_isr(sp) != 0) {
eaae7f72 7282 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7283 s2io_rem_isr(sp);
7284 s2io_reset(sp);
1da177e4
LT		 7285 free_rx_buffers(sp);
7286 return -ENODEV;
7287 }
7288
25fff88e 7289 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7290
01e16faa
SH		 7291 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7292
e6a8fee2 7293 /* Enable select interrupts */
9caab458 7294 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
01e16faa
SH		 7295 if (sp->config.intr_type != INTA) {
7296 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7297 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7298 } else {
e6a8fee2 7299 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7300 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7301 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7302 }
7303
1da177e4
LT		 7304 return 0;
7305}
7306
20346722 7307/**
1da177e4
LT		 7308 * s2io_restart_nic - Resets the NIC.
7309 * @data : long pointer to the device private structure
7310 * Description:
7311 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7312 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7313 * the run time of the watch dog routine which is run holding a
7314 * spin lock.
7315 */
7316
c4028958 7317static void s2io_restart_nic(struct work_struct *work)
1da177e4 7318{
1ee6dd77 7319 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7320 struct net_device *dev = sp->dev;
1da177e4 7321
22747d6b
FR		 7322 rtnl_lock();
7323
7324 if (!netif_running(dev))
7325 goto out_unlock;
7326
e6a8fee2 7327 s2io_card_down(sp);
1da177e4 7328 if (s2io_card_up(sp)) {
d44570e4 7329 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
1da177e4 7330 }
3a3d5756 7331 s2io_wake_all_tx_queue(sp);
d44570e4 7332 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
22747d6b
FR		 7333out_unlock:
7334 rtnl_unlock();
1da177e4
LT		 7335}
7336
20346722 7337/**
7338 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7339 * @dev : Pointer to net device structure
7340 * Description:
7341 * This function is triggered if the Tx Queue is stopped
7342 * for a pre-defined amount of time when the Interface is still up.
7343 * If the Interface is jammed in such a situation, the hardware is
7344 * reset (by s2io_close) and restarted again (by s2io_open) to
7345 * overcome any problem that might have been caused in the hardware.
7346 * Return value:
7347 * void
7348 */
7349
7350static void s2io_tx_watchdog(struct net_device *dev)
7351{
4cf1653a 7352 struct s2io_nic *sp = netdev_priv(dev);
ffb5df6c 7353 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7354
7355 if (netif_carrier_ok(dev)) {
ffb5df6c 7356 swstats->watchdog_timer_cnt++;
1da177e4 7357 schedule_work(&sp->rst_timer_task);
ffb5df6c 7358 swstats->soft_reset_cnt++;
1da177e4
LT		 7359 }
7360}
7361
7362/**
7363 * rx_osm_handler - To perform some OS related operations on SKB.
7364 * @sp: private member of the device structure,pointer to s2io_nic structure.
7365 * @skb : the socket buffer pointer.
7366 * @len : length of the packet
7367 * @cksum : FCS checksum of the frame.
7368 * @ring_no : the ring from which this RxD was extracted.
20346722 7369 * Description:
b41477f3 7370 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7371 * some OS related operations on the SKB before passing it to the upper
7372 * layers. It mainly checks if the checksum is OK, if so adds it to the
7373 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7374 * to the upper layer. If the checksum is wrong, it increments the Rx
7375 * packet error count, frees the SKB and returns error.
7376 * Return value:
7377 * SUCCESS on success and -1 on failure.
7378 */
1ee6dd77 7379static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7380{
1ee6dd77 7381 struct s2io_nic *sp = ring_data->nic;
d44570e4 7382 struct net_device *dev = (struct net_device *)ring_data->dev;
20346722 7383 struct sk_buff *skb = (struct sk_buff *)
d44570e4 7384 ((unsigned long)rxdp->Host_Control);
20346722 7385 int ring_no = ring_data->ring_no;
1da177e4 7386 u16 l3_csum, l4_csum;
863c11a9 7387 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
2e6a684b 7388 struct lro *uninitialized_var(lro);
f9046eb3 7389 u8 err_mask;
ffb5df6c 7390 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
da6971d8 7391
20346722 7392 skb->dev = dev;
c92ca04b 7393
863c11a9 7394 if (err) {
bd1034f0 7395 /* Check for parity error */
d44570e4 7396 if (err & 0x1)
ffb5df6c 7397 swstats->parity_err_cnt++;
d44570e4 7398
f9046eb3 7399 err_mask = err >> 48;
d44570e4
JP		 7400 switch (err_mask) {
7401 case 1:
ffb5df6c 7402 swstats->rx_parity_err_cnt++;
491976b2
SH		 7403 break;
7404
d44570e4 7405 case 2:
ffb5df6c 7406 swstats->rx_abort_cnt++;
491976b2
SH		 7407 break;
7408
d44570e4 7409 case 3:
ffb5df6c 7410 swstats->rx_parity_abort_cnt++;
491976b2
SH		 7411 break;
7412
d44570e4 7413 case 4:
ffb5df6c 7414 swstats->rx_rda_fail_cnt++;
491976b2
SH		 7415 break;
7416
d44570e4 7417 case 5:
ffb5df6c 7418 swstats->rx_unkn_prot_cnt++;
491976b2
SH		 7419 break;
7420
d44570e4 7421 case 6:
ffb5df6c 7422 swstats->rx_fcs_err_cnt++;
491976b2 7423 break;
bd1034f0 7424
d44570e4 7425 case 7:
ffb5df6c 7426 swstats->rx_buf_size_err_cnt++;
491976b2
SH		 7427 break;
7428
d44570e4 7429 case 8:
ffb5df6c 7430 swstats->rx_rxd_corrupt_cnt++;
491976b2
SH		 7431 break;
7432
d44570e4 7433 case 15:
ffb5df6c 7434 swstats->rx_unkn_err_cnt++;
491976b2
SH		 7435 break;
7436 }
863c11a9 7437 /*
d44570e4
JP		 7438 * Drop the packet if bad transfer code. Exception being
7439 * 0x5, which could be due to unsupported IPv6 extension header.
7440 * In this case, we let stack handle the packet.
7441 * Note that in this case, since checksum will be incorrect,
7442 * stack will validate the same.
7443 */
f9046eb3
OH		 7444 if (err_mask != 0x5) {
7445 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
d44570e4 7446 dev->name, err_mask);
dc56e634 7447 dev->stats.rx_crc_errors++;
ffb5df6c 7448 swstats->mem_freed
491976b2 7449 += skb->truesize;
863c11a9 7450 dev_kfree_skb(skb);
0425b46a 7451 ring_data->rx_bufs_left -= 1;
863c11a9
AR		 7452 rxdp->Host_Control = 0;
7453 return 0;
7454 }
20346722 7455 }
1da177e4 7456
20346722 7457 /* Updating statistics */
0425b46a 7458 ring_data->rx_packets++;
20346722 7459 rxdp->Host_Control = 0;
da6971d8
AR		 7460 if (sp->rxd_mode == RXD_MODE_1) {
7461 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7462
0425b46a 7463 ring_data->rx_bytes += len;
da6971d8
AR		 7464 skb_put(skb, len);
7465
6d517a27 7466 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7467 int get_block = ring_data->rx_curr_get_info.block_index;
7468 int get_off = ring_data->rx_curr_get_info.offset;
7469 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7470 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7471 unsigned char *buff = skb_push(skb, buf0_len);
7472
1ee6dd77 7473 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
0425b46a 7474 ring_data->rx_bytes += buf0_len + buf2_len;
da6971d8 7475 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7476 skb_put(skb, buf2_len);
da6971d8 7477 }
20346722 7478
d44570e4
JP		 7479 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7480 ((!ring_data->lro) ||
7481 (ring_data->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722 7482 (sp->rx_csum)) {
7483 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7484 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7485 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7486 /*
1da177e4
LT		 7487 * NIC verifies if the Checksum of the received
7488 * frame is Ok or not and accordingly returns
7489 * a flag in the RxD.
7490 */
7491 skb->ip_summed = CHECKSUM_UNNECESSARY;
0425b46a 7492 if (ring_data->lro) {
7d3d0439
RA		 7493 u32 tcp_len;
7494 u8 *tcp;
7495 int ret = 0;
7496
0425b46a 7497 ret = s2io_club_tcp_session(ring_data,
d44570e4
JP		 7498 skb->data, &tcp,
7499 &tcp_len, &lro,
7500 rxdp, sp);
7d3d0439 7501 switch (ret) {
d44570e4
JP		 7502 case 3: /* Begin anew */
7503 lro->parent = skb;
7504 goto aggregate;
7505 case 1: /* Aggregate */
7506 lro_append_pkt(sp, lro, skb, tcp_len);
7507 goto aggregate;
7508 case 4: /* Flush session */
7509 lro_append_pkt(sp, lro, skb, tcp_len);
7510 queue_rx_frame(lro->parent,
7511 lro->vlan_tag);
7512 clear_lro_session(lro);
ffb5df6c 7513 swstats->flush_max_pkts++;
d44570e4
JP		 7514 goto aggregate;
7515 case 2: /* Flush both */
7516 lro->parent->data_len = lro->frags_len;
ffb5df6c 7517 swstats->sending_both++;
d44570e4
JP		 7518 queue_rx_frame(lro->parent,
7519 lro->vlan_tag);
7520 clear_lro_session(lro);
7521 goto send_up;
7522 case 0: /* sessions exceeded */
7523 case -1: /* non-TCP or not L2 aggregatable */
7524 case 5: /*
7525 * First pkt in session not
7526 * L3/L4 aggregatable
7527 */
7528 break;
7529 default:
7530 DBG_PRINT(ERR_DBG,
7531 "%s: Samadhana!!\n",
7532 __func__);
7533 BUG();
7d3d0439
RA		 7534 }
7535 }
1da177e4 7536 } else {
20346722 7537 /*
7538 * Packet with erroneous checksum, let the
1da177e4
LT		 7539 * upper layers deal with it.
7540 */
7541 skb->ip_summed = CHECKSUM_NONE;
7542 }
cdb5bf02 7543 } else
1da177e4 7544 skb->ip_summed = CHECKSUM_NONE;
cdb5bf02 7545
ffb5df6c 7546 swstats->mem_freed += skb->truesize;
7d3d0439 7547send_up:
0c8dfc83 7548 skb_record_rx_queue(skb, ring_no);
cdb5bf02 7549 queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7550aggregate:
0425b46a 7551 sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
1da177e4
LT		 7552 return SUCCESS;
7553}
7554
7555/**
7556 * s2io_link - stops/starts the Tx queue.
7557 * @sp : private member of the device structure, which is a pointer to the
7558 * s2io_nic structure.
7559 * @link : inidicates whether link is UP/DOWN.
7560 * Description:
7561 * This function stops/starts the Tx queue depending on whether the link
20346722 7562 * status of the NIC is is down or up. This is called by the Alarm
7563 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7564 * Return value:
7565 * void.
7566 */
7567
d44570e4 7568static void s2io_link(struct s2io_nic *sp, int link)
1da177e4 7569{
d44570e4 7570 struct net_device *dev = (struct net_device *)sp->dev;
ffb5df6c 7571 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 7572
7573 if (link != sp->last_link_state) {
b7c5678f 7574 init_tti(sp, link);
1da177e4
LT		 7575 if (link == LINK_DOWN) {
7576 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
3a3d5756 7577 s2io_stop_all_tx_queue(sp);
1da177e4 7578 netif_carrier_off(dev);
ffb5df6c
JP		 7579 if (swstats->link_up_cnt)
7580 swstats->link_up_time =
7581 jiffies - sp->start_time;
7582 swstats->link_down_cnt++;
1da177e4
LT		 7583 } else {
7584 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
ffb5df6c
JP		 7585 if (swstats->link_down_cnt)
7586 swstats->link_down_time =
d44570e4 7587 jiffies - sp->start_time;
ffb5df6c 7588 swstats->link_up_cnt++;
1da177e4 7589 netif_carrier_on(dev);
3a3d5756 7590 s2io_wake_all_tx_queue(sp);
1da177e4
LT		 7591 }
7592 }
7593 sp->last_link_state = link;
491976b2 7594 sp->start_time = jiffies;
1da177e4
LT		 7595}
7596
20346722 7597/**
7598 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7599 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7600 * s2io_nic structure.
7601 * Description:
7602 * This function initializes a few of the PCI and PCI-X configuration registers
7603 * with recommended values.
7604 * Return value:
7605 * void
7606 */
7607
d44570e4 7608static void s2io_init_pci(struct s2io_nic *sp)
1da177e4 7609{
20346722 7610 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7611
7612 /* Enable Data Parity Error Recovery in PCI-X command register. */
7613 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7614 &(pcix_cmd));
1da177e4 7615 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7616 (pcix_cmd | 1));
1da177e4 7617 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7618 &(pcix_cmd));
1da177e4
LT		 7619
7620 /* Set the PErr Response bit in PCI command register. */
7621 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7622 pci_write_config_word(sp->pdev, PCI_COMMAND,
7623 (pci_cmd | PCI_COMMAND_PARITY));
7624 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7625}
7626
3a3d5756 7627static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
d44570e4 7628 u8 *dev_multiq)
9dc737a7 7629{
d44570e4 7630 if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
2fda096d 7631 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
d44570e4 7632 "(%d) not supported\n", tx_fifo_num);
6cfc482b
SH		 7633
7634 if (tx_fifo_num < 1)
7635 tx_fifo_num = 1;
7636 else
7637 tx_fifo_num = MAX_TX_FIFOS;
7638
2fda096d
SR		 7639 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7640 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7641 }
2fda096d 7642
6cfc482b 7643 if (multiq)
3a3d5756 7644 *dev_multiq = multiq;
6cfc482b
SH		 7645
7646 if (tx_steering_type && (1 == tx_fifo_num)) {
7647 if (tx_steering_type != TX_DEFAULT_STEERING)
7648 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7649 "s2io: Tx steering is not supported with "
7650 "one fifo. Disabling Tx steering.\n");
6cfc482b
SH		 7651 tx_steering_type = NO_STEERING;
7652 }
7653
7654 if ((tx_steering_type < NO_STEERING) ||
d44570e4
JP		 7655 (tx_steering_type > TX_DEFAULT_STEERING)) {
7656 DBG_PRINT(ERR_DBG,
7657 "s2io: Requested transmit steering not supported\n");
6cfc482b
SH		 7658 DBG_PRINT(ERR_DBG, "s2io: Disabling transmit steering\n");
7659 tx_steering_type = NO_STEERING;
3a3d5756
SH		 7660 }
7661
0425b46a 7662 if (rx_ring_num > MAX_RX_RINGS) {
d44570e4
JP		 7663 DBG_PRINT(ERR_DBG,
7664 "s2io: Requested number of rx rings not supported\n");
0425b46a 7665 DBG_PRINT(ERR_DBG, "s2io: Default to %d rx rings\n",
d44570e4 7666 MAX_RX_RINGS);
0425b46a 7667 rx_ring_num = MAX_RX_RINGS;
9dc737a7 7668 }
0425b46a 7669
eccb8628 7670 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7671 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7672 "Defaulting to INTA\n");
7673 *dev_intr_type = INTA;
7674 }
596c5c97 7675
9dc737a7 7676 if ((*dev_intr_type == MSI_X) &&
d44570e4
JP		 7677 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7678 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7679 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
d44570e4 7680 "Defaulting to INTA\n");
9dc737a7
AR		 7681 *dev_intr_type = INTA;
7682 }
fb6a825b 7683
6d517a27 7684 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7685 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7686 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7687 rx_ring_mode = 1;
9dc737a7
AR		 7688 }
7689 return SUCCESS;
7690}
7691
9fc93a41
SS		 7692/**
7693 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7694 * or Traffic class respectively.
b7c5678f 7695 * @nic: device private variable
9fc93a41
SS		 7696 * Description: The function configures the receive steering to
7697 * desired receive ring.
7698 * Return Value: SUCCESS on success and
7699 * '-1' on failure (endian settings incorrect).
7700 */
7701static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7702{
7703 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7704 register u64 val64 = 0;
7705
7706 if (ds_codepoint > 63)
7707 return FAILURE;
7708
7709 val64 = RTS_DS_MEM_DATA(ring);
7710 writeq(val64, &bar0->rts_ds_mem_data);
7711
7712 val64 = RTS_DS_MEM_CTRL_WE |
7713 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7714 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7715
7716 writeq(val64, &bar0->rts_ds_mem_ctrl);
7717
7718 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
d44570e4
JP		 7719 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7720 S2IO_BIT_RESET);
9fc93a41
SS		 7721}
7722
04025095
SH		 7723static const struct net_device_ops s2io_netdev_ops = {
7724 .ndo_open = s2io_open,
7725 .ndo_stop = s2io_close,
7726 .ndo_get_stats = s2io_get_stats,
7727 .ndo_start_xmit = s2io_xmit,
7728 .ndo_validate_addr = eth_validate_addr,
7729 .ndo_set_multicast_list = s2io_set_multicast,
7730 .ndo_do_ioctl = s2io_ioctl,
7731 .ndo_set_mac_address = s2io_set_mac_addr,
7732 .ndo_change_mtu = s2io_change_mtu,
7733 .ndo_vlan_rx_register = s2io_vlan_rx_register,
7734 .ndo_vlan_rx_kill_vid = s2io_vlan_rx_kill_vid,
7735 .ndo_tx_timeout = s2io_tx_watchdog,
7736#ifdef CONFIG_NET_POLL_CONTROLLER
7737 .ndo_poll_controller = s2io_netpoll,
7738#endif
7739};
7740
1da177e4 7741/**
20346722 7742 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7743 * @pdev : structure containing the PCI related information of the device.
7744 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7745 * Description:
7746 * The function initializes an adapter identified by the pci_dec structure.
20346722 7747 * All OS related initialization including memory and device structure and
7748 * initlaization of the device private variable is done. Also the swapper
7749 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7750 * registers of the device.
7751 * Return value:
7752 * returns 0 on success and negative on failure.
7753 */
7754
7755static int __devinit
7756s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7757{
1ee6dd77 7758 struct s2io_nic *sp;
1da177e4 7759 struct net_device *dev;
1da177e4 7760 int i, j, ret;
f957bcf0 7761 int dma_flag = false;
1da177e4
LT		 7762 u32 mac_up, mac_down;
7763 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7764 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7765 u16 subid;
1da177e4 7766 struct config_param *config;
ffb5df6c 7767 struct mac_info *mac_control;
541ae68f 7768 int mode;
cc6e7c44 7769 u8 dev_intr_type = intr_type;
3a3d5756 7770 u8 dev_multiq = 0;
1da177e4 7771
3a3d5756
SH		 7772 ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7773 if (ret)
9dc737a7 7774 return ret;
1da177e4 7775
d44570e4
JP		 7776 ret = pci_enable_device(pdev);
7777 if (ret) {
1da177e4
LT		 7778 DBG_PRINT(ERR_DBG,
7779 "s2io_init_nic: pci_enable_device failed\n");
7780 return ret;
7781 }
7782
6a35528a 7783 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7784 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
f957bcf0 7785 dma_flag = true;
d44570e4 7786 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4 7787 DBG_PRINT(ERR_DBG,
d44570e4
JP		 7788 "Unable to obtain 64bit DMA "
7789 "for consistent allocations\n");
1da177e4
LT		 7790 pci_disable_device(pdev);
7791 return -ENOMEM;
7792 }
284901a9 7793 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 7794 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7795 } else {
7796 pci_disable_device(pdev);
7797 return -ENOMEM;
7798 }
d44570e4
JP		 7799 ret = pci_request_regions(pdev, s2io_driver_name);
7800 if (ret) {
7801 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n",
7802 __func__, ret);
eccb8628
VP		 7803 pci_disable_device(pdev);
7804 return -ENODEV;
1da177e4 7805 }
3a3d5756 7806 if (dev_multiq)
6cfc482b 7807 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
3a3d5756 7808 else
b19fa1fa 7809 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7810 if (dev == NULL) {
7811 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7812 pci_disable_device(pdev);
7813 pci_release_regions(pdev);
7814 return -ENODEV;
7815 }
7816
7817 pci_set_master(pdev);
7818 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7819 SET_NETDEV_DEV(dev, &pdev->dev);
7820
7821 /* Private member variable initialized to s2io NIC structure */
4cf1653a 7822 sp = netdev_priv(dev);
1ee6dd77 7823 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7824 sp->dev = dev;
7825 sp->pdev = pdev;
1da177e4 7826 sp->high_dma_flag = dma_flag;
f957bcf0 7827 sp->device_enabled_once = false;
da6971d8
AR		 7828 if (rx_ring_mode == 1)
7829 sp->rxd_mode = RXD_MODE_1;
7830 if (rx_ring_mode == 2)
7831 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7832
eaae7f72 7833 sp->config.intr_type = dev_intr_type;
1da177e4 7834
541ae68f 7835 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
d44570e4 7836 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
541ae68f 7837 sp->device_type = XFRAME_II_DEVICE;
7838 else
7839 sp->device_type = XFRAME_I_DEVICE;
7840
43b7c451 7841 sp->lro = lro_enable;
6aa20a22 7842
1da177e4
LT		 7843 /* Initialize some PCI/PCI-X fields of the NIC. */
7844 s2io_init_pci(sp);
7845
20346722 7846 /*
1da177e4 7847 * Setting the device configuration parameters.
20346722 7848 * Most of these parameters can be specified by the user during
7849 * module insertion as they are module loadable parameters. If
7850 * these parameters are not not specified during load time, they
1da177e4
LT		 7851 * are initialized with default values.
7852 */
1da177e4 7853 config = &sp->config;
ffb5df6c 7854 mac_control = &sp->mac_control;
1da177e4 7855
596c5c97 7856 config->napi = napi;
6cfc482b 7857 config->tx_steering_type = tx_steering_type;
596c5c97 7858
1da177e4 7859 /* Tx side parameters. */
6cfc482b
SH		 7860 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7861 config->tx_fifo_num = MAX_TX_FIFOS;
7862 else
7863 config->tx_fifo_num = tx_fifo_num;
7864
7865 /* Initialize the fifos used for tx steering */
7866 if (config->tx_fifo_num < 5) {
d44570e4
JP		 7867 if (config->tx_fifo_num == 1)
7868 sp->total_tcp_fifos = 1;
7869 else
7870 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7871 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7872 sp->total_udp_fifos = 1;
7873 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
6cfc482b
SH		 7874 } else {
7875 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
d44570e4 7876 FIFO_OTHER_MAX_NUM);
6cfc482b
SH		 7877 sp->udp_fifo_idx = sp->total_tcp_fifos;
7878 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7879 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7880 }
7881
3a3d5756 7882 config->multiq = dev_multiq;
6cfc482b 7883 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7884 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7885
7886 tx_cfg->fifo_len = tx_fifo_len[i];
7887 tx_cfg->fifo_priority = i;
1da177e4
LT		 7888 }
7889
20346722 7890 /* mapping the QoS priority to the configured fifos */
7891 for (i = 0; i < MAX_TX_FIFOS; i++)
3a3d5756 7892 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
20346722 7893
6cfc482b
SH		 7894 /* map the hashing selector table to the configured fifos */
7895 for (i = 0; i < config->tx_fifo_num; i++)
7896 sp->fifo_selector[i] = fifo_selector[i];
7897
7898
1da177e4
LT		 7899 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7900 for (i = 0; i < config->tx_fifo_num; i++) {
13d866a9
JP		 7901 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7902
7903 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7904 if (tx_cfg->fifo_len < 65) {
1da177e4
LT		 7905 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7906 break;
7907 }
7908 }
fed5eccd
AR		 7909 /* + 2 because one Txd for skb->data and one Txd for UFO */
7910 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7911
7912 /* Rx side parameters. */
1da177e4 7913 config->rx_ring_num = rx_ring_num;
0425b46a 7914 for (i = 0; i < config->rx_ring_num; i++) {
13d866a9
JP		 7915 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7916 struct ring_info *ring = &mac_control->rings[i];
7917
7918 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7919 rx_cfg->ring_priority = i;
7920 ring->rx_bufs_left = 0;
7921 ring->rxd_mode = sp->rxd_mode;
7922 ring->rxd_count = rxd_count[sp->rxd_mode];
7923 ring->pdev = sp->pdev;
7924 ring->dev = sp->dev;
1da177e4
LT		 7925 }
7926
7927 for (i = 0; i < rx_ring_num; i++) {
13d866a9
JP		 7928 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7929
7930 rx_cfg->ring_org = RING_ORG_BUFF1;
7931 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
1da177e4
LT		 7932 }
7933
7934 /* Setting Mac Control parameters */
7935 mac_control->rmac_pause_time = rmac_pause_time;
7936 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7937 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7938
7939
1da177e4
LT		 7940 /* initialize the shared memory used by the NIC and the host */
7941 if (init_shared_mem(sp)) {
d44570e4 7942 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
1da177e4
LT		 7943 ret = -ENOMEM;
7944 goto mem_alloc_failed;
7945 }
7946
275f165f 7947 sp->bar0 = pci_ioremap_bar(pdev, 0);
1da177e4 7948 if (!sp->bar0) {
19a60522 7949 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7950 dev->name);
7951 ret = -ENOMEM;
7952 goto bar0_remap_failed;
7953 }
7954
275f165f 7955 sp->bar1 = pci_ioremap_bar(pdev, 2);
1da177e4 7956 if (!sp->bar1) {
19a60522 7957 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7958 dev->name);
7959 ret = -ENOMEM;
7960 goto bar1_remap_failed;
7961 }
7962
7963 dev->irq = pdev->irq;
d44570e4 7964 dev->base_addr = (unsigned long)sp->bar0;
1da177e4
LT		 7965
7966 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7967 for (j = 0; j < MAX_TX_FIFOS; j++) {
d44570e4
JP		 7968 mac_control->tx_FIFO_start[j] =
7969 (struct TxFIFO_element __iomem *)
7970 (sp->bar1 + (j * 0x00020000));
1da177e4
LT		 7971 }
7972
7973 /* Driver entry points */
04025095 7974 dev->netdev_ops = &s2io_netdev_ops;
1da177e4 7975 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02 7976 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
612eff0e 7977
1da177e4 7978 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f957bcf0 7979 if (sp->high_dma_flag == true)
1da177e4 7980 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7981 dev->features |= NETIF_F_TSO;
f83ef8c0 7982 dev->features |= NETIF_F_TSO6;
db874e65 7983 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7984 dev->features |= NETIF_F_UFO;
7985 dev->features |= NETIF_F_HW_CSUM;
7986 }
1da177e4 7987 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7988 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7989 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7990
e960fc5c 7991 pci_save_state(sp->pdev);
1da177e4
LT		 7992
7993 /* Setting swapper control on the NIC, for proper reset operation */
7994 if (s2io_set_swapper(sp)) {
7995 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7996 dev->name);
7997 ret = -EAGAIN;
7998 goto set_swap_failed;
7999 }
8000
541ae68f 8001 /* Verify if the Herc works on the slot its placed into */
8002 if (sp->device_type & XFRAME_II_DEVICE) {
8003 mode = s2io_verify_pci_mode(sp);
8004 if (mode < 0) {
b39d66a8 8005 DBG_PRINT(ERR_DBG, "%s: ", __func__);
541ae68f 8006 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
8007 ret = -EBADSLT;
8008 goto set_swap_failed;
8009 }
8010 }
8011
f61e0a35
SH		 8012 if (sp->config.intr_type == MSI_X) {
8013 sp->num_entries = config->rx_ring_num + 1;
8014 ret = s2io_enable_msi_x(sp);
8015
8016 if (!ret) {
8017 ret = s2io_test_msi(sp);
8018 /* rollback MSI-X, will re-enable during add_isr() */
8019 remove_msix_isr(sp);
8020 }
8021 if (ret) {
8022
8023 DBG_PRINT(ERR_DBG,
d44570e4 8024 "s2io: MSI-X requested but failed to enable\n");
f61e0a35
SH		 8025 sp->config.intr_type = INTA;
8026 }
8027 }
8028
8029 if (config->intr_type == MSI_X) {
13d866a9
JP		 8030 for (i = 0; i < config->rx_ring_num ; i++) {
8031 struct ring_info *ring = &mac_control->rings[i];
8032
8033 netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
8034 }
f61e0a35
SH		 8035 } else {
8036 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
8037 }
8038
541ae68f 8039 /* Not needed for Herc */
8040 if (sp->device_type & XFRAME_I_DEVICE) {
8041 /*
8042 * Fix for all "FFs" MAC address problems observed on
8043 * Alpha platforms
8044 */
8045 fix_mac_address(sp);
8046 s2io_reset(sp);
8047 }
1da177e4
LT		 8048
8049 /*
1da177e4
LT		 8050 * MAC address initialization.
8051 * For now only one mac address will be read and used.
8052 */
8053 bar0 = sp->bar0;
8054 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
d44570e4 8055 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 8056 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 8057 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
d44570e4
JP		 8058 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
8059 S2IO_BIT_RESET);
1da177e4 8060 tmp64 = readq(&bar0->rmac_addr_data0_mem);
d44570e4 8061 mac_down = (u32)tmp64;
1da177e4
LT		 8062 mac_up = (u32) (tmp64 >> 32);
8063
1da177e4
LT		 8064 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8065 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8066 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8067 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8068 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8069 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8070
1da177e4
LT		 8071 /* Set the factory defined MAC address initially */
8072 dev->addr_len = ETH_ALEN;
8073 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 8074 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 8075
faa4f796
SH		 8076 /* initialize number of multicast & unicast MAC entries variables */
8077 if (sp->device_type == XFRAME_I_DEVICE) {
8078 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8079 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8080 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8081 } else if (sp->device_type == XFRAME_II_DEVICE) {
8082 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8083 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8084 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8085 }
8086
8087 /* store mac addresses from CAM to s2io_nic structure */
8088 do_s2io_store_unicast_mc(sp);
8089
f61e0a35
SH		 8090 /* Configure MSIX vector for number of rings configured plus one */
8091 if ((sp->device_type == XFRAME_II_DEVICE) &&
d44570e4 8092 (config->intr_type == MSI_X))
f61e0a35
SH		 8093 sp->num_entries = config->rx_ring_num + 1;
8094
d44570e4 8095 /* Store the values of the MSIX table in the s2io_nic structure */
c77dd43e 8096 store_xmsi_data(sp);
b41477f3
AR		 8097 /* reset Nic and bring it to known state */
8098 s2io_reset(sp);
8099
1da177e4 8100 /*
99993af6 8101 * Initialize link state flags
541ae68f 8102 * and the card state parameter
1da177e4 8103 */
92b84437 8104 sp->state = 0;
1da177e4 8105
1da177e4 8106 /* Initialize spinlocks */
13d866a9
JP		 8107 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8108 struct fifo_info *fifo = &mac_control->fifos[i];
8109
8110 spin_lock_init(&fifo->tx_lock);
8111 }
db874e65 8112
20346722 8113 /*
8114 * SXE-002: Configure link and activity LED to init state
8115 * on driver load.
1da177e4
LT		 8116 */
8117 subid = sp->pdev->subsystem_device;
8118 if ((subid & 0xFF) >= 0x07) {
8119 val64 = readq(&bar0->gpio_control);
8120 val64 |= 0x0000800000000000ULL;
8121 writeq(val64, &bar0->gpio_control);
8122 val64 = 0x0411040400000000ULL;
d44570e4 8123 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 8124 val64 = readq(&bar0->gpio_control);
8125 }
8126
8127 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
8128
8129 if (register_netdev(dev)) {
8130 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8131 ret = -ENODEV;
8132 goto register_failed;
8133 }
9dc737a7 8134 s2io_vpd_read(sp);
0c61ed5f 8135 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
d44570e4 8136 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
44c10138 8137 sp->product_name, pdev->revision);
b41477f3
AR		 8138 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8139 s2io_driver_version);
e174961c 8140 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %pM\n", dev->name, dev->dev_addr);
19a60522 8141 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 8142 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 8143 mode = s2io_print_pci_mode(sp);
541ae68f 8144 if (mode < 0) {
9dc737a7 8145 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 8146 ret = -EBADSLT;
9dc737a7 8147 unregister_netdev(dev);
541ae68f 8148 goto set_swap_failed;
8149 }
541ae68f 8150 }
d44570e4
JP		 8151 switch (sp->rxd_mode) {
8152 case RXD_MODE_1:
8153 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8154 dev->name);
8155 break;
8156 case RXD_MODE_3B:
8157 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8158 dev->name);
8159 break;
9dc737a7 8160 }
db874e65 8161
f61e0a35
SH		 8162 switch (sp->config.napi) {
8163 case 0:
8164 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8165 break;
8166 case 1:
db874e65 8167 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
f61e0a35
SH		 8168 break;
8169 }
3a3d5756
SH		 8170
8171 DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
d44570e4 8172 sp->config.tx_fifo_num);
3a3d5756 8173
0425b46a
SH		 8174 DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8175 sp->config.rx_ring_num);
8176
d44570e4
JP		 8177 switch (sp->config.intr_type) {
8178 case INTA:
8179 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8180 break;
8181 case MSI_X:
8182 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8183 break;
9dc737a7 8184 }
3a3d5756 8185 if (sp->config.multiq) {
13d866a9
JP		 8186 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8187 struct fifo_info *fifo = &mac_control->fifos[i];
8188
8189 fifo->multiq = config->multiq;
8190 }
3a3d5756 8191 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
d44570e4 8192 dev->name);
3a3d5756
SH		 8193 } else
8194 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
d44570e4 8195 dev->name);
3a3d5756 8196
6cfc482b
SH		 8197 switch (sp->config.tx_steering_type) {
8198 case NO_STEERING:
d44570e4
JP		 8199 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8200 dev->name);
8201 break;
6cfc482b 8202 case TX_PRIORITY_STEERING:
d44570e4
JP		 8203 DBG_PRINT(ERR_DBG,
8204 "%s: Priority steering enabled for transmit\n",
8205 dev->name);
6cfc482b
SH		 8206 break;
8207 case TX_DEFAULT_STEERING:
d44570e4
JP		 8208 DBG_PRINT(ERR_DBG,
8209 "%s: Default steering enabled for transmit\n",
8210 dev->name);
6cfc482b
SH		 8211 }
8212
7d3d0439
RA		 8213 if (sp->lro)
8214 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 8215 dev->name);
db874e65 8216 if (ufo)
d44570e4
JP		 8217 DBG_PRINT(ERR_DBG,
8218 "%s: UDP Fragmentation Offload(UFO) enabled\n",
8219 dev->name);
7ba013ac 8220 /* Initialize device name */
9dc737a7 8221 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 8222
cd0fce03
BL		 8223 if (vlan_tag_strip)
8224 sp->vlan_strip_flag = 1;
8225 else
8226 sp->vlan_strip_flag = 0;
8227
20346722 8228 /*
8229 * Make Link state as off at this point, when the Link change
8230 * interrupt comes the state will be automatically changed to
1da177e4
LT		 8231 * the right state.
8232 */
8233 netif_carrier_off(dev);
1da177e4
LT		 8234
8235 return 0;
8236
d44570e4
JP		 8237register_failed:
8238set_swap_failed:
1da177e4 8239 iounmap(sp->bar1);
d44570e4 8240bar1_remap_failed:
1da177e4 8241 iounmap(sp->bar0);
d44570e4
JP		 8242bar0_remap_failed:
8243mem_alloc_failed:
1da177e4
LT		 8244 free_shared_mem(sp);
8245 pci_disable_device(pdev);
eccb8628 8246 pci_release_regions(pdev);
1da177e4
LT		 8247 pci_set_drvdata(pdev, NULL);
8248 free_netdev(dev);
8249
8250 return ret;
8251}
8252
8253/**
20346722 8254 * s2io_rem_nic - Free the PCI device
1da177e4 8255 * @pdev: structure containing the PCI related information of the device.
20346722 8256 * Description: This function is called by the Pci subsystem to release a
1da177e4 8257 * PCI device and free up all resource held up by the device. This could
20346722 8258 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8259 * from memory.
8260 */
8261
8262static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8263{
8264 struct net_device *dev =
d44570e4 8265 (struct net_device *)pci_get_drvdata(pdev);
1ee6dd77 8266 struct s2io_nic *sp;
1da177e4
LT		 8267
8268 if (dev == NULL) {
8269 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8270 return;
8271 }
8272
22747d6b
FR		 8273 flush_scheduled_work();
8274
4cf1653a 8275 sp = netdev_priv(dev);
1da177e4
LT		 8276 unregister_netdev(dev);
8277
8278 free_shared_mem(sp);
8279 iounmap(sp->bar0);
8280 iounmap(sp->bar1);
eccb8628 8281 pci_release_regions(pdev);
1da177e4 8282 pci_set_drvdata(pdev, NULL);
1da177e4 8283 free_netdev(dev);
19a60522 8284 pci_disable_device(pdev);
1da177e4
LT		 8285}
8286
8287/**
8288 * s2io_starter - Entry point for the driver
8289 * Description: This function is the entry point for the driver. It verifies
8290 * the module loadable parameters and initializes PCI configuration space.
8291 */
8292
43b7c451 8293static int __init s2io_starter(void)
1da177e4 8294{
29917620 8295 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8296}
8297
8298/**
20346722 8299 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8300 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8301 */
8302
372cc597 8303static __exit void s2io_closer(void)
1da177e4
LT		 8304{
8305 pci_unregister_driver(&s2io_driver);
8306 DBG_PRINT(INIT_DBG, "cleanup done\n");
8307}
8308
8309module_init(s2io_starter);
8310module_exit(s2io_closer);
7d3d0439 8311
6aa20a22 8312static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
d44570e4
JP		 8313 struct tcphdr **tcp, struct RxD_t *rxdp,
8314 struct s2io_nic *sp)
7d3d0439
RA		 8315{
8316 int ip_off;
8317 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8318
8319 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
d44570e4
JP		 8320 DBG_PRINT(INIT_DBG,
8321 "%s: Non-TCP frames not supported for LRO\n",
b39d66a8 8322 __func__);
7d3d0439
RA		 8323 return -1;
8324 }
8325
cdb5bf02 8326 /* Checking for DIX type or DIX type with VLAN */
d44570e4 8327 if ((l2_type == 0) || (l2_type == 4)) {
cdb5bf02
SH		 8328 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8329 /*
8330 * If vlan stripping is disabled and the frame is VLAN tagged,
8331 * shift the offset by the VLAN header size bytes.
8332 */
cd0fce03 8333 if ((!sp->vlan_strip_flag) &&
d44570e4 8334 (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
cdb5bf02
SH		 8335 ip_off += HEADER_VLAN_SIZE;
8336 } else {
7d3d0439 8337 /* LLC, SNAP etc are considered non-mergeable */
cdb5bf02 8338 return -1;
7d3d0439
RA		 8339 }
8340
8341 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8342 ip_len = (u8)((*ip)->ihl);
8343 ip_len <<= 2;
8344 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8345
8346 return 0;
8347}
8348
1ee6dd77 8349static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8350 struct tcphdr *tcp)
8351{
d44570e4
JP		 8352 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8353 if ((lro->iph->saddr != ip->saddr) ||
8354 (lro->iph->daddr != ip->daddr) ||
8355 (lro->tcph->source != tcp->source) ||
8356 (lro->tcph->dest != tcp->dest))
7d3d0439
RA		 8357 return -1;
8358 return 0;
8359}
8360
8361static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8362{
d44570e4 8363 return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
7d3d0439
RA		 8364}
8365
1ee6dd77 8366static void initiate_new_session(struct lro *lro, u8 *l2h,
d44570e4
JP		 8367 struct iphdr *ip, struct tcphdr *tcp,
8368 u32 tcp_pyld_len, u16 vlan_tag)
7d3d0439 8369{
d44570e4 8370 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8371 lro->l2h = l2h;
8372 lro->iph = ip;
8373 lro->tcph = tcp;
8374 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8375 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8376 lro->sg_num = 1;
8377 lro->total_len = ntohs(ip->tot_len);
8378 lro->frags_len = 0;
cdb5bf02 8379 lro->vlan_tag = vlan_tag;
6aa20a22 8380 /*
d44570e4
JP		 8381 * Check if we saw TCP timestamp.
8382 * Other consistency checks have already been done.
8383 */
7d3d0439 8384 if (tcp->doff == 8) {
c8855953
SR		 8385 __be32 *ptr;
8386 ptr = (__be32 *)(tcp+1);
7d3d0439 8387 lro->saw_ts = 1;
c8855953 8388 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8389 lro->cur_tsecr = *(ptr+2);
8390 }
8391 lro->in_use = 1;
8392}
8393
1ee6dd77 8394static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8395{
8396 struct iphdr *ip = lro->iph;
8397 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8398 __sum16 nchk;
ffb5df6c
JP		 8399 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8400
d44570e4 8401 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8402
8403 /* Update L3 header */
8404 ip->tot_len = htons(lro->total_len);
8405 ip->check = 0;
8406 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8407 ip->check = nchk;
8408
8409 /* Update L4 header */
8410 tcp->ack_seq = lro->tcp_ack;
8411 tcp->window = lro->window;
8412
8413 /* Update tsecr field if this session has timestamps enabled */
8414 if (lro->saw_ts) {
c8855953 8415 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8416 *(ptr+2) = lro->cur_tsecr;
8417 }
8418
8419 /* Update counters required for calculation of
8420 * average no. of packets aggregated.
8421 */
ffb5df6c
JP		 8422 swstats->sum_avg_pkts_aggregated += lro->sg_num;
8423 swstats->num_aggregations++;
7d3d0439
RA		 8424}
8425
1ee6dd77 8426static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
d44570e4 8427 struct tcphdr *tcp, u32 l4_pyld)
7d3d0439 8428{
d44570e4 8429 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
7d3d0439
RA		 8430 lro->total_len += l4_pyld;
8431 lro->frags_len += l4_pyld;
8432 lro->tcp_next_seq += l4_pyld;
8433 lro->sg_num++;
8434
8435 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8436 lro->tcp_ack = tcp->ack_seq;
8437 lro->window = tcp->window;
6aa20a22 8438
7d3d0439 8439 if (lro->saw_ts) {
c8855953 8440 __be32 *ptr;
7d3d0439 8441 /* Update tsecr and tsval from this packet */
c8855953
SR		 8442 ptr = (__be32 *)(tcp+1);
8443 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8444 lro->cur_tsecr = *(ptr + 2);
8445 }
8446}
8447
1ee6dd77 8448static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8449 struct tcphdr *tcp, u32 tcp_pyld_len)
8450{
7d3d0439
RA		 8451 u8 *ptr;
8452
d44570e4 8453 DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
79dc1901 8454
7d3d0439
RA		 8455 if (!tcp_pyld_len) {
8456 /* Runt frame or a pure ack */
8457 return -1;
8458 }
8459
8460 if (ip->ihl != 5) /* IP has options */
8461 return -1;
8462
75c30b13
AR		 8463 /* If we see CE codepoint in IP header, packet is not mergeable */
8464 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8465 return -1;
8466
8467 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
d44570e4
JP		 8468 if (tcp->urg || tcp->psh || tcp->rst ||
8469 tcp->syn || tcp->fin ||
8470 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8471 /*
8472 * Currently recognize only the ack control word and
8473 * any other control field being set would result in
8474 * flushing the LRO session
8475 */
8476 return -1;
8477 }
8478
6aa20a22 8479 /*
7d3d0439
RA		 8480 * Allow only one TCP timestamp option. Don't aggregate if
8481 * any other options are detected.
8482 */
8483 if (tcp->doff != 5 && tcp->doff != 8)
8484 return -1;
8485
8486 if (tcp->doff == 8) {
6aa20a22 8487 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8488 while (*ptr == TCPOPT_NOP)
8489 ptr++;
8490 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8491 return -1;
8492
8493 /* Ensure timestamp value increases monotonically */
8494 if (l_lro)
c8855953 8495 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8496 return -1;
8497
8498 /* timestamp echo reply should be non-zero */
c8855953 8499 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8500 return -1;
8501 }
8502
8503 return 0;
8504}
8505
d44570e4
JP		 8506static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8507 u8 **tcp, u32 *tcp_len, struct lro **lro,
8508 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8509{
8510 struct iphdr *ip;
8511 struct tcphdr *tcph;
8512 int ret = 0, i;
cdb5bf02 8513 u16 vlan_tag = 0;
ffb5df6c 8514 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439 8515
d44570e4
JP		 8516 ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8517 rxdp, sp);
8518 if (ret)
7d3d0439 8519 return ret;
7d3d0439 8520
d44570e4
JP		 8521 DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8522
cdb5bf02 8523 vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
7d3d0439
RA		 8524 tcph = (struct tcphdr *)*tcp;
8525 *tcp_len = get_l4_pyld_length(ip, tcph);
d44570e4 8526 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8527 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8528 if (l_lro->in_use) {
8529 if (check_for_socket_match(l_lro, ip, tcph))
8530 continue;
8531 /* Sock pair matched */
8532 *lro = l_lro;
8533
8534 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8535 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
b39d66a8 8536 "0x%x, actual 0x%x\n", __func__,
7d3d0439
RA		 8537 (*lro)->tcp_next_seq,
8538 ntohl(tcph->seq));
8539
ffb5df6c 8540 swstats->outof_sequence_pkts++;
7d3d0439
RA		 8541 ret = 2;
8542 break;
8543 }
8544
d44570e4
JP		 8545 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8546 *tcp_len))
7d3d0439
RA		 8547 ret = 1; /* Aggregate */
8548 else
8549 ret = 2; /* Flush both */
8550 break;
8551 }
8552 }
8553
8554 if (ret == 0) {
8555 /* Before searching for available LRO objects,
8556 * check if the pkt is L3/L4 aggregatable. If not
8557 * don't create new LRO session. Just send this
8558 * packet up.
8559 */
d44570e4 8560 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
7d3d0439 8561 return 5;
7d3d0439 8562
d44570e4 8563 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
0425b46a 8564 struct lro *l_lro = &ring_data->lro0_n[i];
7d3d0439
RA		 8565 if (!(l_lro->in_use)) {
8566 *lro = l_lro;
8567 ret = 3; /* Begin anew */
8568 break;
8569 }
8570 }
8571 }
8572
8573 if (ret == 0) { /* sessions exceeded */
d44570e4 8574 DBG_PRINT(INFO_DBG, "%s:All LRO sessions already in use\n",
b39d66a8 8575 __func__);
7d3d0439
RA		 8576 *lro = NULL;
8577 return ret;
8578 }
8579
8580 switch (ret) {
d44570e4
JP		 8581 case 3:
8582 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8583 vlan_tag);
8584 break;
8585 case 2:
8586 update_L3L4_header(sp, *lro);
8587 break;
8588 case 1:
8589 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8590 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7d3d0439 8591 update_L3L4_header(sp, *lro);
d44570e4
JP		 8592 ret = 4; /* Flush the LRO */
8593 }
8594 break;
8595 default:
8596 DBG_PRINT(ERR_DBG, "%s:Dont know, can't say!!\n", __func__);
8597 break;
7d3d0439
RA		 8598 }
8599
8600 return ret;
8601}
8602
1ee6dd77 8603static void clear_lro_session(struct lro *lro)
7d3d0439 8604{
1ee6dd77 8605 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8606
8607 memset(lro, 0, lro_struct_size);
8608}
8609
cdb5bf02 8610static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
7d3d0439
RA		 8611{
8612 struct net_device *dev = skb->dev;
4cf1653a 8613 struct s2io_nic *sp = netdev_priv(dev);
7d3d0439
RA		 8614
8615 skb->protocol = eth_type_trans(skb, dev);
d44570e4 8616 if (sp->vlgrp && vlan_tag && (sp->vlan_strip_flag)) {
cdb5bf02
SH		 8617 /* Queueing the vlan frame to the upper layer */
8618 if (sp->config.napi)
8619 vlan_hwaccel_receive_skb(skb, sp->vlgrp, vlan_tag);
8620 else
8621 vlan_hwaccel_rx(skb, sp->vlgrp, vlan_tag);
8622 } else {
8623 if (sp->config.napi)
8624 netif_receive_skb(skb);
8625 else
8626 netif_rx(skb);
8627 }
7d3d0439
RA		 8628}
8629
1ee6dd77 8630static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
d44570e4 8631 struct sk_buff *skb, u32 tcp_len)
7d3d0439 8632{
75c30b13 8633 struct sk_buff *first = lro->parent;
ffb5df6c 8634 struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7d3d0439
RA		 8635
8636 first->len += tcp_len;
8637 first->data_len = lro->frags_len;
8638 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8639 if (skb_shinfo(first)->frag_list)
8640 lro->last_frag->next = skb;
7d3d0439
RA		 8641 else
8642 skb_shinfo(first)->frag_list = skb;
372cc597 8643 first->truesize += skb->truesize;
75c30b13 8644 lro->last_frag = skb;
ffb5df6c 8645 swstats->clubbed_frms_cnt++;
7d3d0439
RA		 8646 return;
8647}
d796fdb7
LV		 8648
8649/**
8650 * s2io_io_error_detected - called when PCI error is detected
8651 * @pdev: Pointer to PCI device
8453d43f 8652 * @state: The current pci connection state
d796fdb7
LV		 8653 *
8654 * This function is called after a PCI bus error affecting
8655 * this device has been detected.
8656 */
8657static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
d44570e4 8658 pci_channel_state_t state)
d796fdb7
LV		 8659{
8660 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8661 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8662
8663 netif_device_detach(netdev);
8664
1e3c8bd6
DN		 8665 if (state == pci_channel_io_perm_failure)
8666 return PCI_ERS_RESULT_DISCONNECT;
8667
d796fdb7
LV		 8668 if (netif_running(netdev)) {
8669 /* Bring down the card, while avoiding PCI I/O */
8670 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8671 }
8672 pci_disable_device(pdev);
8673
8674 return PCI_ERS_RESULT_NEED_RESET;
8675}
8676
8677/**
8678 * s2io_io_slot_reset - called after the pci bus has been reset.
8679 * @pdev: Pointer to PCI device
8680 *
8681 * Restart the card from scratch, as if from a cold-boot.
8682 * At this point, the card has exprienced a hard reset,
8683 * followed by fixups by BIOS, and has its config space
8684 * set up identically to what it was at cold boot.
8685 */
8686static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8687{
8688 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8689 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8690
8691 if (pci_enable_device(pdev)) {
6cef2b8e 8692 pr_err("Cannot re-enable PCI device after reset.\n");
d796fdb7
LV		 8693 return PCI_ERS_RESULT_DISCONNECT;
8694 }
8695
8696 pci_set_master(pdev);
8697 s2io_reset(sp);
8698
8699 return PCI_ERS_RESULT_RECOVERED;
8700}
8701
8702/**
8703 * s2io_io_resume - called when traffic can start flowing again.
8704 * @pdev: Pointer to PCI device
8705 *
8706 * This callback is called when the error recovery driver tells
8707 * us that its OK to resume normal operation.
8708 */
8709static void s2io_io_resume(struct pci_dev *pdev)
8710{
8711 struct net_device *netdev = pci_get_drvdata(pdev);
4cf1653a 8712 struct s2io_nic *sp = netdev_priv(netdev);
d796fdb7
LV		 8713
8714 if (netif_running(netdev)) {
8715 if (s2io_card_up(sp)) {
6cef2b8e 8716 pr_err("Can't bring device back up after reset.\n");
d796fdb7
LV		 8717 return;
8718 }
8719
8720 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8721 s2io_card_down(sp);
6cef2b8e 8722 pr_err("Can't restore mac addr after reset.\n");
d796fdb7
LV		 8723 return;
8724 }
8725 }
8726
8727 netif_device_attach(netdev);
fd2ea0a7 8728 netif_tx_wake_all_queues(netdev);
d796fdb7 8729}
Linux kernel - Deliverables
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