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1da177e4 | 1 | /************************************************************************ |
776bd20f | 2 | * s2io.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC |
0c61ed5f | 3 | * Copyright(c) 2002-2007 Neterion Inc. |
1da177e4 LT |
4 | |
5 | * This software may be used and distributed according to the terms of | |
6 | * the GNU General Public License (GPL), incorporated herein by reference. | |
7 | * Drivers based on or derived from this code fall under the GPL and must | |
8 | * retain the authorship, copyright and license notice. This file is not | |
9 | * a complete program and may only be used when the entire operating | |
10 | * system is licensed under the GPL. | |
11 | * See the file COPYING in this distribution for more information. | |
12 | ************************************************************************/ | |
13 | #ifndef _S2IO_H | |
14 | #define _S2IO_H | |
15 | ||
16 | #define TBD 0 | |
b7b5a128 | 17 | #define s2BIT(loc) (0x8000000000000000ULL >> (loc)) |
1da177e4 LT |
18 | #define vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) |
19 | #define INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff) | |
20 | ||
21 | #ifndef BOOL | |
22 | #define BOOL int | |
23 | #endif | |
24 | ||
25 | #ifndef TRUE | |
26 | #define TRUE 1 | |
27 | #define FALSE 0 | |
28 | #endif | |
29 | ||
30 | #undef SUCCESS | |
31 | #define SUCCESS 0 | |
32 | #define FAILURE -1 | |
19a60522 | 33 | #define S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL |
faa4f796 | 34 | #define S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL |
19a60522 | 35 | #define S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 |
9fc93a41 SS |
36 | #define S2IO_BIT_RESET 1 |
37 | #define S2IO_BIT_SET 2 | |
bd1034f0 AR |
38 | #define CHECKBIT(value, nbit) (value & (1 << nbit)) |
39 | ||
20346722 | 40 | /* Maximum time to flicker LED when asked to identify NIC using ethtool */ |
41 | #define MAX_FLICKER_TIME 60000 /* 60 Secs */ | |
42 | ||
1da177e4 | 43 | /* Maximum outstanding splits to be configured into xena. */ |
1ee6dd77 | 44 | enum { |
1da177e4 LT |
45 | XENA_ONE_SPLIT_TRANSACTION = 0, |
46 | XENA_TWO_SPLIT_TRANSACTION = 1, | |
47 | XENA_THREE_SPLIT_TRANSACTION = 2, | |
48 | XENA_FOUR_SPLIT_TRANSACTION = 3, | |
49 | XENA_EIGHT_SPLIT_TRANSACTION = 4, | |
50 | XENA_TWELVE_SPLIT_TRANSACTION = 5, | |
51 | XENA_SIXTEEN_SPLIT_TRANSACTION = 6, | |
52 | XENA_THIRTYTWO_SPLIT_TRANSACTION = 7 | |
1ee6dd77 | 53 | }; |
1da177e4 LT |
54 | #define XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) |
55 | ||
56 | /* OS concerned variables and constants */ | |
20346722 | 57 | #define WATCH_DOG_TIMEOUT 15*HZ |
58 | #define EFILL 0x1234 | |
59 | #define ALIGN_SIZE 127 | |
60 | #define PCIX_COMMAND_REGISTER 0x62 | |
1da177e4 LT |
61 | |
62 | /* | |
63 | * Debug related variables. | |
64 | */ | |
65 | /* different debug levels. */ | |
66 | #define ERR_DBG 0 | |
67 | #define INIT_DBG 1 | |
68 | #define INFO_DBG 2 | |
69 | #define TX_DBG 3 | |
70 | #define INTR_DBG 4 | |
71 | ||
72 | /* Global variable that defines the present debug level of the driver. */ | |
26df54bf | 73 | static int debug_level = ERR_DBG; |
1da177e4 LT |
74 | |
75 | /* DEBUG message print. */ | |
76 | #define DBG_PRINT(dbg_level, args...) if(!(debug_level<dbg_level)) printk(args) | |
77 | ||
491abf25 VP |
78 | #ifndef DMA_ERROR_CODE |
79 | #define DMA_ERROR_CODE (~(dma_addr_t)0x0) | |
80 | #endif | |
81 | ||
1da177e4 LT |
82 | /* Protocol assist features of the NIC */ |
83 | #define L3_CKSUM_OK 0xFFFF | |
84 | #define L4_CKSUM_OK 0xFFFF | |
85 | #define S2IO_JUMBO_SIZE 9600 | |
86 | ||
20346722 | 87 | /* Driver statistics maintained by driver */ |
1ee6dd77 | 88 | struct swStat { |
20346722 | 89 | unsigned long long single_ecc_errs; |
90 | unsigned long long double_ecc_errs; | |
bd1034f0 AR |
91 | unsigned long long parity_err_cnt; |
92 | unsigned long long serious_err_cnt; | |
93 | unsigned long long soft_reset_cnt; | |
94 | unsigned long long fifo_full_cnt; | |
8116f3cf | 95 | unsigned long long ring_full_cnt[8]; |
7d3d0439 RA |
96 | /* LRO statistics */ |
97 | unsigned long long clubbed_frms_cnt; | |
98 | unsigned long long sending_both; | |
99 | unsigned long long outof_sequence_pkts; | |
100 | unsigned long long flush_max_pkts; | |
101 | unsigned long long sum_avg_pkts_aggregated; | |
102 | unsigned long long num_aggregations; | |
c53d4945 SH |
103 | /* Other statistics */ |
104 | unsigned long long mem_alloc_fail_cnt; | |
491abf25 | 105 | unsigned long long pci_map_fail_cnt; |
c53d4945 | 106 | unsigned long long watchdog_timer_cnt; |
491976b2 SH |
107 | unsigned long long mem_allocated; |
108 | unsigned long long mem_freed; | |
109 | unsigned long long link_up_cnt; | |
110 | unsigned long long link_down_cnt; | |
111 | unsigned long long link_up_time; | |
112 | unsigned long long link_down_time; | |
113 | ||
114 | /* Transfer Code statistics */ | |
115 | unsigned long long tx_buf_abort_cnt; | |
116 | unsigned long long tx_desc_abort_cnt; | |
117 | unsigned long long tx_parity_err_cnt; | |
118 | unsigned long long tx_link_loss_cnt; | |
119 | unsigned long long tx_list_proc_err_cnt; | |
120 | ||
121 | unsigned long long rx_parity_err_cnt; | |
122 | unsigned long long rx_abort_cnt; | |
123 | unsigned long long rx_parity_abort_cnt; | |
124 | unsigned long long rx_rda_fail_cnt; | |
125 | unsigned long long rx_unkn_prot_cnt; | |
126 | unsigned long long rx_fcs_err_cnt; | |
127 | unsigned long long rx_buf_size_err_cnt; | |
128 | unsigned long long rx_rxd_corrupt_cnt; | |
129 | unsigned long long rx_unkn_err_cnt; | |
8116f3cf SS |
130 | |
131 | /* Error/alarm statistics*/ | |
132 | unsigned long long tda_err_cnt; | |
133 | unsigned long long pfc_err_cnt; | |
134 | unsigned long long pcc_err_cnt; | |
135 | unsigned long long tti_err_cnt; | |
136 | unsigned long long lso_err_cnt; | |
137 | unsigned long long tpa_err_cnt; | |
138 | unsigned long long sm_err_cnt; | |
139 | unsigned long long mac_tmac_err_cnt; | |
140 | unsigned long long mac_rmac_err_cnt; | |
141 | unsigned long long xgxs_txgxs_err_cnt; | |
142 | unsigned long long xgxs_rxgxs_err_cnt; | |
143 | unsigned long long rc_err_cnt; | |
144 | unsigned long long prc_pcix_err_cnt; | |
145 | unsigned long long rpa_err_cnt; | |
146 | unsigned long long rda_err_cnt; | |
147 | unsigned long long rti_err_cnt; | |
148 | unsigned long long mc_err_cnt; | |
149 | ||
1ee6dd77 | 150 | }; |
20346722 | 151 | |
bd1034f0 | 152 | /* Xpak releated alarm and warnings */ |
1ee6dd77 | 153 | struct xpakStat { |
bd1034f0 AR |
154 | u64 alarm_transceiver_temp_high; |
155 | u64 alarm_transceiver_temp_low; | |
156 | u64 alarm_laser_bias_current_high; | |
157 | u64 alarm_laser_bias_current_low; | |
158 | u64 alarm_laser_output_power_high; | |
159 | u64 alarm_laser_output_power_low; | |
160 | u64 warn_transceiver_temp_high; | |
161 | u64 warn_transceiver_temp_low; | |
162 | u64 warn_laser_bias_current_high; | |
163 | u64 warn_laser_bias_current_low; | |
164 | u64 warn_laser_output_power_high; | |
165 | u64 warn_laser_output_power_low; | |
166 | u64 xpak_regs_stat; | |
167 | u32 xpak_timer_count; | |
1ee6dd77 | 168 | }; |
bd1034f0 AR |
169 | |
170 | ||
1da177e4 | 171 | /* The statistics block of Xena */ |
1ee6dd77 | 172 | struct stat_block { |
1da177e4 | 173 | /* Tx MAC statistics counters. */ |
107c3a73 AV |
174 | __le32 tmac_data_octets; |
175 | __le32 tmac_frms; | |
176 | __le64 tmac_drop_frms; | |
177 | __le32 tmac_bcst_frms; | |
178 | __le32 tmac_mcst_frms; | |
179 | __le64 tmac_pause_ctrl_frms; | |
180 | __le32 tmac_ucst_frms; | |
181 | __le32 tmac_ttl_octets; | |
182 | __le32 tmac_any_err_frms; | |
183 | __le32 tmac_nucst_frms; | |
184 | __le64 tmac_ttl_less_fb_octets; | |
185 | __le64 tmac_vld_ip_octets; | |
186 | __le32 tmac_drop_ip; | |
187 | __le32 tmac_vld_ip; | |
188 | __le32 tmac_rst_tcp; | |
189 | __le32 tmac_icmp; | |
190 | __le64 tmac_tcp; | |
191 | __le32 reserved_0; | |
192 | __le32 tmac_udp; | |
1da177e4 LT |
193 | |
194 | /* Rx MAC Statistics counters. */ | |
107c3a73 AV |
195 | __le32 rmac_data_octets; |
196 | __le32 rmac_vld_frms; | |
197 | __le64 rmac_fcs_err_frms; | |
198 | __le64 rmac_drop_frms; | |
199 | __le32 rmac_vld_bcst_frms; | |
200 | __le32 rmac_vld_mcst_frms; | |
201 | __le32 rmac_out_rng_len_err_frms; | |
202 | __le32 rmac_in_rng_len_err_frms; | |
203 | __le64 rmac_long_frms; | |
204 | __le64 rmac_pause_ctrl_frms; | |
205 | __le64 rmac_unsup_ctrl_frms; | |
206 | __le32 rmac_accepted_ucst_frms; | |
207 | __le32 rmac_ttl_octets; | |
208 | __le32 rmac_discarded_frms; | |
209 | __le32 rmac_accepted_nucst_frms; | |
210 | __le32 reserved_1; | |
211 | __le32 rmac_drop_events; | |
212 | __le64 rmac_ttl_less_fb_octets; | |
213 | __le64 rmac_ttl_frms; | |
214 | __le64 reserved_2; | |
215 | __le32 rmac_usized_frms; | |
216 | __le32 reserved_3; | |
217 | __le32 rmac_frag_frms; | |
218 | __le32 rmac_osized_frms; | |
219 | __le32 reserved_4; | |
220 | __le32 rmac_jabber_frms; | |
221 | __le64 rmac_ttl_64_frms; | |
222 | __le64 rmac_ttl_65_127_frms; | |
223 | __le64 reserved_5; | |
224 | __le64 rmac_ttl_128_255_frms; | |
225 | __le64 rmac_ttl_256_511_frms; | |
226 | __le64 reserved_6; | |
227 | __le64 rmac_ttl_512_1023_frms; | |
228 | __le64 rmac_ttl_1024_1518_frms; | |
229 | __le32 rmac_ip; | |
230 | __le32 reserved_7; | |
231 | __le64 rmac_ip_octets; | |
232 | __le32 rmac_drop_ip; | |
233 | __le32 rmac_hdr_err_ip; | |
234 | __le32 reserved_8; | |
235 | __le32 rmac_icmp; | |
236 | __le64 rmac_tcp; | |
237 | __le32 rmac_err_drp_udp; | |
238 | __le32 rmac_udp; | |
239 | __le64 rmac_xgmii_err_sym; | |
240 | __le64 rmac_frms_q0; | |
241 | __le64 rmac_frms_q1; | |
242 | __le64 rmac_frms_q2; | |
243 | __le64 rmac_frms_q3; | |
244 | __le64 rmac_frms_q4; | |
245 | __le64 rmac_frms_q5; | |
246 | __le64 rmac_frms_q6; | |
247 | __le64 rmac_frms_q7; | |
248 | __le16 rmac_full_q3; | |
249 | __le16 rmac_full_q2; | |
250 | __le16 rmac_full_q1; | |
251 | __le16 rmac_full_q0; | |
252 | __le16 rmac_full_q7; | |
253 | __le16 rmac_full_q6; | |
254 | __le16 rmac_full_q5; | |
255 | __le16 rmac_full_q4; | |
256 | __le32 reserved_9; | |
257 | __le32 rmac_pause_cnt; | |
258 | __le64 rmac_xgmii_data_err_cnt; | |
259 | __le64 rmac_xgmii_ctrl_err_cnt; | |
260 | __le32 rmac_err_tcp; | |
261 | __le32 rmac_accepted_ip; | |
1da177e4 LT |
262 | |
263 | /* PCI/PCI-X Read transaction statistics. */ | |
107c3a73 AV |
264 | __le32 new_rd_req_cnt; |
265 | __le32 rd_req_cnt; | |
266 | __le32 rd_rtry_cnt; | |
267 | __le32 new_rd_req_rtry_cnt; | |
1da177e4 LT |
268 | |
269 | /* PCI/PCI-X Write/Read transaction statistics. */ | |
107c3a73 AV |
270 | __le32 wr_req_cnt; |
271 | __le32 wr_rtry_rd_ack_cnt; | |
272 | __le32 new_wr_req_rtry_cnt; | |
273 | __le32 new_wr_req_cnt; | |
274 | __le32 wr_disc_cnt; | |
275 | __le32 wr_rtry_cnt; | |
1da177e4 LT |
276 | |
277 | /* PCI/PCI-X Write / DMA Transaction statistics. */ | |
107c3a73 AV |
278 | __le32 txp_wr_cnt; |
279 | __le32 rd_rtry_wr_ack_cnt; | |
280 | __le32 txd_wr_cnt; | |
281 | __le32 txd_rd_cnt; | |
282 | __le32 rxd_wr_cnt; | |
283 | __le32 rxd_rd_cnt; | |
284 | __le32 rxf_wr_cnt; | |
285 | __le32 txf_rd_cnt; | |
7ba013ac | 286 | |
541ae68f | 287 | /* Tx MAC statistics overflow counters. */ |
107c3a73 AV |
288 | __le32 tmac_data_octets_oflow; |
289 | __le32 tmac_frms_oflow; | |
290 | __le32 tmac_bcst_frms_oflow; | |
291 | __le32 tmac_mcst_frms_oflow; | |
292 | __le32 tmac_ucst_frms_oflow; | |
293 | __le32 tmac_ttl_octets_oflow; | |
294 | __le32 tmac_any_err_frms_oflow; | |
295 | __le32 tmac_nucst_frms_oflow; | |
296 | __le64 tmac_vlan_frms; | |
297 | __le32 tmac_drop_ip_oflow; | |
298 | __le32 tmac_vld_ip_oflow; | |
299 | __le32 tmac_rst_tcp_oflow; | |
300 | __le32 tmac_icmp_oflow; | |
301 | __le32 tpa_unknown_protocol; | |
302 | __le32 tmac_udp_oflow; | |
303 | __le32 reserved_10; | |
304 | __le32 tpa_parse_failure; | |
541ae68f | 305 | |
306 | /* Rx MAC Statistics overflow counters. */ | |
107c3a73 AV |
307 | __le32 rmac_data_octets_oflow; |
308 | __le32 rmac_vld_frms_oflow; | |
309 | __le32 rmac_vld_bcst_frms_oflow; | |
310 | __le32 rmac_vld_mcst_frms_oflow; | |
311 | __le32 rmac_accepted_ucst_frms_oflow; | |
312 | __le32 rmac_ttl_octets_oflow; | |
313 | __le32 rmac_discarded_frms_oflow; | |
314 | __le32 rmac_accepted_nucst_frms_oflow; | |
315 | __le32 rmac_usized_frms_oflow; | |
316 | __le32 rmac_drop_events_oflow; | |
317 | __le32 rmac_frag_frms_oflow; | |
318 | __le32 rmac_osized_frms_oflow; | |
319 | __le32 rmac_ip_oflow; | |
320 | __le32 rmac_jabber_frms_oflow; | |
321 | __le32 rmac_icmp_oflow; | |
322 | __le32 rmac_drop_ip_oflow; | |
323 | __le32 rmac_err_drp_udp_oflow; | |
324 | __le32 rmac_udp_oflow; | |
325 | __le32 reserved_11; | |
326 | __le32 rmac_pause_cnt_oflow; | |
327 | __le64 rmac_ttl_1519_4095_frms; | |
328 | __le64 rmac_ttl_4096_8191_frms; | |
329 | __le64 rmac_ttl_8192_max_frms; | |
330 | __le64 rmac_ttl_gt_max_frms; | |
331 | __le64 rmac_osized_alt_frms; | |
332 | __le64 rmac_jabber_alt_frms; | |
333 | __le64 rmac_gt_max_alt_frms; | |
334 | __le64 rmac_vlan_frms; | |
335 | __le32 rmac_len_discard; | |
336 | __le32 rmac_fcs_discard; | |
337 | __le32 rmac_pf_discard; | |
338 | __le32 rmac_da_discard; | |
339 | __le32 rmac_red_discard; | |
340 | __le32 rmac_rts_discard; | |
341 | __le32 reserved_12; | |
342 | __le32 rmac_ingm_full_discard; | |
343 | __le32 reserved_13; | |
344 | __le32 rmac_accepted_ip_oflow; | |
345 | __le32 reserved_14; | |
346 | __le32 link_fault_cnt; | |
bd1034f0 | 347 | u8 buffer[20]; |
1ee6dd77 RB |
348 | struct swStat sw_stat; |
349 | struct xpakStat xpak_stat; | |
350 | }; | |
1da177e4 | 351 | |
926930b2 SS |
352 | /* Default value for 'vlan_strip_tag' configuration parameter */ |
353 | #define NO_STRIP_IN_PROMISC 2 | |
354 | ||
20346722 | 355 | /* |
356 | * Structures representing different init time configuration | |
1da177e4 LT |
357 | * parameters of the NIC. |
358 | */ | |
359 | ||
20346722 | 360 | #define MAX_TX_FIFOS 8 |
361 | #define MAX_RX_RINGS 8 | |
362 | ||
6cfc482b SH |
363 | #define FIFO_DEFAULT_NUM 5 |
364 | #define FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */ | |
365 | #define FIFO_OTHER_MAX_NUM 1 | |
366 | ||
2fda096d | 367 | |
0cec35eb SH |
368 | #define MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 127 ) |
369 | #define MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 ) | |
370 | #define MAX_RX_DESC_3 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 85 ) | |
371 | #define MAX_TX_DESC (MAX_AVAILABLE_TXDS) | |
372 | ||
20346722 | 373 | /* FIFO mappings for all possible number of fifos configured */ |
26df54bf | 374 | static int fifo_map[][MAX_TX_FIFOS] = { |
20346722 | 375 | {0, 0, 0, 0, 0, 0, 0, 0}, |
376 | {0, 0, 0, 0, 1, 1, 1, 1}, | |
377 | {0, 0, 0, 1, 1, 1, 2, 2}, | |
378 | {0, 0, 1, 1, 2, 2, 3, 3}, | |
379 | {0, 0, 1, 1, 2, 2, 3, 4}, | |
380 | {0, 0, 1, 1, 2, 3, 4, 5}, | |
381 | {0, 0, 1, 2, 3, 4, 5, 6}, | |
382 | {0, 1, 2, 3, 4, 5, 6, 7}, | |
383 | }; | |
384 | ||
6cfc482b SH |
385 | static u16 fifo_selector[MAX_TX_FIFOS] = {0, 1, 3, 3, 7, 7, 7, 7}; |
386 | ||
1da177e4 | 387 | /* Maintains Per FIFO related information. */ |
1ee6dd77 | 388 | struct tx_fifo_config { |
1da177e4 LT |
389 | #define MAX_AVAILABLE_TXDS 8192 |
390 | u32 fifo_len; /* specifies len of FIFO upto 8192, ie no of TxDLs */ | |
391 | /* Priority definition */ | |
392 | #define TX_FIFO_PRI_0 0 /*Highest */ | |
393 | #define TX_FIFO_PRI_1 1 | |
394 | #define TX_FIFO_PRI_2 2 | |
395 | #define TX_FIFO_PRI_3 3 | |
396 | #define TX_FIFO_PRI_4 4 | |
397 | #define TX_FIFO_PRI_5 5 | |
398 | #define TX_FIFO_PRI_6 6 | |
399 | #define TX_FIFO_PRI_7 7 /*lowest */ | |
400 | u8 fifo_priority; /* specifies pointer level for FIFO */ | |
401 | /* user should not set twos fifos with same pri */ | |
402 | u8 f_no_snoop; | |
403 | #define NO_SNOOP_TXD 0x01 | |
404 | #define NO_SNOOP_TXD_BUFFER 0x02 | |
1ee6dd77 | 405 | }; |
1da177e4 LT |
406 | |
407 | ||
408 | /* Maintains per Ring related information */ | |
1ee6dd77 | 409 | struct rx_ring_config { |
1da177e4 LT |
410 | u32 num_rxd; /*No of RxDs per Rx Ring */ |
411 | #define RX_RING_PRI_0 0 /* highest */ | |
412 | #define RX_RING_PRI_1 1 | |
413 | #define RX_RING_PRI_2 2 | |
414 | #define RX_RING_PRI_3 3 | |
415 | #define RX_RING_PRI_4 4 | |
416 | #define RX_RING_PRI_5 5 | |
417 | #define RX_RING_PRI_6 6 | |
418 | #define RX_RING_PRI_7 7 /* lowest */ | |
419 | ||
420 | u8 ring_priority; /*Specifies service priority of ring */ | |
421 | /* OSM should not set any two rings with same priority */ | |
422 | u8 ring_org; /*Organization of ring */ | |
423 | #define RING_ORG_BUFF1 0x01 | |
424 | #define RX_RING_ORG_BUFF3 0x03 | |
425 | #define RX_RING_ORG_BUFF5 0x05 | |
426 | ||
427 | u8 f_no_snoop; | |
428 | #define NO_SNOOP_RXD 0x01 | |
429 | #define NO_SNOOP_RXD_BUFFER 0x02 | |
1ee6dd77 | 430 | }; |
1da177e4 | 431 | |
20346722 | 432 | /* This structure provides contains values of the tunable parameters |
433 | * of the H/W | |
1da177e4 LT |
434 | */ |
435 | struct config_param { | |
436 | /* Tx Side */ | |
437 | u32 tx_fifo_num; /*Number of Tx FIFOs */ | |
1da177e4 | 438 | |
6cfc482b SH |
439 | /* 0-No steering, 1-Priority steering, 2-Default fifo map */ |
440 | #define NO_STEERING 0 | |
441 | #define TX_PRIORITY_STEERING 0x1 | |
442 | #define TX_DEFAULT_STEERING 0x2 | |
443 | u8 tx_steering_type; | |
444 | ||
20346722 | 445 | u8 fifo_mapping[MAX_TX_FIFOS]; |
1ee6dd77 | 446 | struct tx_fifo_config tx_cfg[MAX_TX_FIFOS]; /*Per-Tx FIFO config */ |
1da177e4 LT |
447 | u32 max_txds; /*Max no. of Tx buffer descriptor per TxDL */ |
448 | u64 tx_intr_type; | |
8abc4d5b SS |
449 | #define INTA 0 |
450 | #define MSI_X 2 | |
451 | u8 intr_type; | |
c77dd43e | 452 | u8 napi; |
8abc4d5b | 453 | |
1da177e4 LT |
454 | /* Specifies if Tx Intr is UTILZ or PER_LIST type. */ |
455 | ||
456 | /* Rx Side */ | |
457 | u32 rx_ring_num; /*Number of receive rings */ | |
1da177e4 LT |
458 | #define MAX_RX_BLOCKS_PER_RING 150 |
459 | ||
1ee6dd77 | 460 | struct rx_ring_config rx_cfg[MAX_RX_RINGS]; /*Per-Rx Ring config */ |
1da177e4 LT |
461 | |
462 | #define HEADER_ETHERNET_II_802_3_SIZE 14 | |
463 | #define HEADER_802_2_SIZE 3 | |
464 | #define HEADER_SNAP_SIZE 5 | |
465 | #define HEADER_VLAN_SIZE 4 | |
466 | ||
467 | #define MIN_MTU 46 | |
468 | #define MAX_PYLD 1500 | |
469 | #define MAX_MTU (MAX_PYLD+18) | |
470 | #define MAX_MTU_VLAN (MAX_PYLD+22) | |
471 | #define MAX_PYLD_JUMBO 9600 | |
472 | #define MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18) | |
473 | #define MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22) | |
20346722 | 474 | u16 bus_speed; |
faa4f796 SH |
475 | int max_mc_addr; /* xena=64 herc=256 */ |
476 | int max_mac_addr; /* xena=16 herc=64 */ | |
477 | int mc_start_offset; /* xena=16 herc=64 */ | |
3a3d5756 | 478 | u8 multiq; |
1da177e4 LT |
479 | }; |
480 | ||
481 | /* Structure representing MAC Addrs */ | |
1ee6dd77 | 482 | struct mac_addr { |
1da177e4 | 483 | u8 mac_addr[ETH_ALEN]; |
1ee6dd77 | 484 | }; |
1da177e4 LT |
485 | |
486 | /* Structure that represent every FIFO element in the BAR1 | |
20346722 | 487 | * Address location. |
1da177e4 | 488 | */ |
1ee6dd77 | 489 | struct TxFIFO_element { |
1da177e4 LT |
490 | u64 TxDL_Pointer; |
491 | ||
492 | u64 List_Control; | |
493 | #define TX_FIFO_LAST_TXD_NUM( val) vBIT(val,0,8) | |
b7b5a128 JS |
494 | #define TX_FIFO_FIRST_LIST s2BIT(14) |
495 | #define TX_FIFO_LAST_LIST s2BIT(15) | |
1da177e4 | 496 | #define TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) |
b7b5a128 JS |
497 | #define TX_FIFO_SPECIAL_FUNC s2BIT(23) |
498 | #define TX_FIFO_DS_NO_SNOOP s2BIT(31) | |
499 | #define TX_FIFO_BUFF_NO_SNOOP s2BIT(30) | |
1ee6dd77 | 500 | }; |
1da177e4 LT |
501 | |
502 | /* Tx descriptor structure */ | |
1ee6dd77 | 503 | struct TxD { |
1da177e4 LT |
504 | u64 Control_1; |
505 | /* bit mask */ | |
b7b5a128 JS |
506 | #define TXD_LIST_OWN_XENA s2BIT(7) |
507 | #define TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15)) | |
1da177e4 LT |
508 | #define TXD_T_CODE_OK(val) (|(val & TXD_T_CODE)) |
509 | #define GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12) | |
b7b5a128 JS |
510 | #define TXD_GATHER_CODE (s2BIT(22) | s2BIT(23)) |
511 | #define TXD_GATHER_CODE_FIRST s2BIT(22) | |
512 | #define TXD_GATHER_CODE_LAST s2BIT(23) | |
513 | #define TXD_TCP_LSO_EN s2BIT(30) | |
514 | #define TXD_UDP_COF_EN s2BIT(31) | |
515 | #define TXD_UFO_EN s2BIT(31) | s2BIT(30) | |
1da177e4 | 516 | #define TXD_TCP_LSO_MSS(val) vBIT(val,34,14) |
fed5eccd | 517 | #define TXD_UFO_MSS(val) vBIT(val,34,14) |
1da177e4 LT |
518 | #define TXD_BUFFER0_SIZE(val) vBIT(val,48,16) |
519 | ||
520 | u64 Control_2; | |
b7b5a128 JS |
521 | #define TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7)) |
522 | #define TXD_TX_CKO_IPV4_EN s2BIT(5) | |
523 | #define TXD_TX_CKO_TCP_EN s2BIT(6) | |
524 | #define TXD_TX_CKO_UDP_EN s2BIT(7) | |
525 | #define TXD_VLAN_ENABLE s2BIT(15) | |
1da177e4 LT |
526 | #define TXD_VLAN_TAG(val) vBIT(val,16,16) |
527 | #define TXD_INT_NUMBER(val) vBIT(val,34,6) | |
b7b5a128 JS |
528 | #define TXD_INT_TYPE_PER_LIST s2BIT(47) |
529 | #define TXD_INT_TYPE_UTILZ s2BIT(46) | |
1da177e4 LT |
530 | #define TXD_SET_MARKER vBIT(0x6,0,4) |
531 | ||
532 | u64 Buffer_Pointer; | |
533 | u64 Host_Control; /* reserved for host */ | |
1ee6dd77 | 534 | }; |
1da177e4 LT |
535 | |
536 | /* Structure to hold the phy and virt addr of every TxDL. */ | |
1ee6dd77 | 537 | struct list_info_hold { |
1da177e4 LT |
538 | dma_addr_t list_phy_addr; |
539 | void *list_virt_addr; | |
1ee6dd77 | 540 | }; |
1da177e4 | 541 | |
da6971d8 | 542 | /* Rx descriptor structure for 1 buffer mode */ |
1ee6dd77 | 543 | struct RxD_t { |
1da177e4 LT |
544 | u64 Host_Control; /* reserved for host */ |
545 | u64 Control_1; | |
b7b5a128 JS |
546 | #define RXD_OWN_XENA s2BIT(7) |
547 | #define RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15)) | |
1da177e4 | 548 | #define RXD_FRAME_PROTO vBIT(0xFFFF,24,8) |
cdb5bf02 | 549 | #define RXD_FRAME_VLAN_TAG s2BIT(24) |
b7b5a128 JS |
550 | #define RXD_FRAME_PROTO_IPV4 s2BIT(27) |
551 | #define RXD_FRAME_PROTO_IPV6 s2BIT(28) | |
552 | #define RXD_FRAME_IP_FRAG s2BIT(29) | |
553 | #define RXD_FRAME_PROTO_TCP s2BIT(30) | |
554 | #define RXD_FRAME_PROTO_UDP s2BIT(31) | |
1da177e4 LT |
555 | #define TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) |
556 | #define RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF) | |
557 | #define RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) | |
558 | ||
559 | u64 Control_2; | |
5e25b9dd | 560 | #define THE_RXD_MARK 0x3 |
561 | #define SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2) | |
562 | #define GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62) | |
563 | ||
1da177e4 LT |
564 | #define MASK_VLAN_TAG vBIT(0xFFFF,48,16) |
565 | #define SET_VLAN_TAG(val) vBIT(val,48,16) | |
566 | #define SET_NUM_TAG(val) vBIT(val,16,32) | |
567 | ||
da6971d8 | 568 | |
1ee6dd77 | 569 | }; |
da6971d8 | 570 | /* Rx descriptor structure for 1 buffer mode */ |
1ee6dd77 RB |
571 | struct RxD1 { |
572 | struct RxD_t h; | |
da6971d8 AR |
573 | |
574 | #define MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14) | |
575 | #define SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) | |
576 | #define RXD_GET_BUFFER0_SIZE_1(_Control_2) \ | |
577 | (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48) | |
578 | u64 Buffer0_ptr; | |
1ee6dd77 | 579 | }; |
da6971d8 AR |
580 | /* Rx descriptor structure for 3 or 2 buffer mode */ |
581 | ||
1ee6dd77 RB |
582 | struct RxD3 { |
583 | struct RxD_t h; | |
da6971d8 AR |
584 | |
585 | #define MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14) | |
586 | #define MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16) | |
587 | #define MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16) | |
588 | #define SET_BUFFER0_SIZE_3(val) vBIT(val,8,8) | |
589 | #define SET_BUFFER1_SIZE_3(val) vBIT(val,16,16) | |
590 | #define SET_BUFFER2_SIZE_3(val) vBIT(val,32,16) | |
591 | #define RXD_GET_BUFFER0_SIZE_3(Control_2) \ | |
592 | (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48) | |
593 | #define RXD_GET_BUFFER1_SIZE_3(Control_2) \ | |
594 | (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32) | |
595 | #define RXD_GET_BUFFER2_SIZE_3(Control_2) \ | |
596 | (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16) | |
1da177e4 LT |
597 | #define BUF0_LEN 40 |
598 | #define BUF1_LEN 1 | |
1da177e4 LT |
599 | |
600 | u64 Buffer0_ptr; | |
1da177e4 LT |
601 | u64 Buffer1_ptr; |
602 | u64 Buffer2_ptr; | |
1ee6dd77 | 603 | }; |
da6971d8 | 604 | |
1da177e4 | 605 | |
20346722 | 606 | /* Structure that represents the Rx descriptor block which contains |
1da177e4 LT |
607 | * 128 Rx descriptors. |
608 | */ | |
1ee6dd77 | 609 | struct RxD_block { |
da6971d8 | 610 | #define MAX_RXDS_PER_BLOCK_1 127 |
1ee6dd77 | 611 | struct RxD1 rxd[MAX_RXDS_PER_BLOCK_1]; |
1da177e4 LT |
612 | |
613 | u64 reserved_0; | |
614 | #define END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL | |
20346722 | 615 | u64 reserved_1; /* 0xFEFFFFFFFFFFFFFF to mark last |
1da177e4 LT |
616 | * Rxd in this blk */ |
617 | u64 reserved_2_pNext_RxD_block; /* Logical ptr to next */ | |
618 | u64 pNext_RxD_Blk_physical; /* Buff0_ptr.In a 32 bit arch | |
20346722 | 619 | * the upper 32 bits should |
1da177e4 | 620 | * be 0 */ |
1ee6dd77 | 621 | }; |
1da177e4 | 622 | |
1da177e4 LT |
623 | #define SIZE_OF_BLOCK 4096 |
624 | ||
19a60522 | 625 | #define RXD_MODE_1 0 /* One Buffer mode */ |
6d517a27 | 626 | #define RXD_MODE_3B 1 /* Two Buffer mode */ |
da6971d8 | 627 | |
20346722 | 628 | /* Structure to hold virtual addresses of Buf0 and Buf1 in |
1da177e4 | 629 | * 2buf mode. */ |
1ee6dd77 | 630 | struct buffAdd { |
1da177e4 LT |
631 | void *ba_0_org; |
632 | void *ba_1_org; | |
633 | void *ba_0; | |
634 | void *ba_1; | |
1ee6dd77 | 635 | }; |
1da177e4 LT |
636 | |
637 | /* Structure which stores all the MAC control parameters */ | |
638 | ||
20346722 | 639 | /* This structure stores the offset of the RxD in the ring |
640 | * from which the Rx Interrupt processor can start picking | |
1da177e4 LT |
641 | * up the RxDs for processing. |
642 | */ | |
1ee6dd77 | 643 | struct rx_curr_get_info { |
1da177e4 LT |
644 | u32 block_index; |
645 | u32 offset; | |
646 | u32 ring_len; | |
1ee6dd77 | 647 | }; |
1da177e4 | 648 | |
1ee6dd77 RB |
649 | struct rx_curr_put_info { |
650 | u32 block_index; | |
651 | u32 offset; | |
652 | u32 ring_len; | |
653 | }; | |
1da177e4 LT |
654 | |
655 | /* This structure stores the offset of the TxDl in the FIFO | |
20346722 | 656 | * from which the Tx Interrupt processor can start picking |
1da177e4 LT |
657 | * up the TxDLs for send complete interrupt processing. |
658 | */ | |
1ee6dd77 | 659 | struct tx_curr_get_info { |
1da177e4 LT |
660 | u32 offset; |
661 | u32 fifo_len; | |
1ee6dd77 | 662 | }; |
1da177e4 | 663 | |
1ee6dd77 RB |
664 | struct tx_curr_put_info { |
665 | u32 offset; | |
666 | u32 fifo_len; | |
667 | }; | |
da6971d8 | 668 | |
1ee6dd77 | 669 | struct rxd_info { |
da6971d8 AR |
670 | void *virt_addr; |
671 | dma_addr_t dma_addr; | |
1ee6dd77 | 672 | }; |
da6971d8 | 673 | |
20346722 | 674 | /* Structure that holds the Phy and virt addresses of the Blocks */ |
1ee6dd77 | 675 | struct rx_block_info { |
da6971d8 | 676 | void *block_virt_addr; |
20346722 | 677 | dma_addr_t block_dma_addr; |
1ee6dd77 RB |
678 | struct rxd_info *rxds; |
679 | }; | |
20346722 | 680 | |
0425b46a SH |
681 | /* Data structure to represent a LRO session */ |
682 | struct lro { | |
683 | struct sk_buff *parent; | |
684 | struct sk_buff *last_frag; | |
685 | u8 *l2h; | |
686 | struct iphdr *iph; | |
687 | struct tcphdr *tcph; | |
688 | u32 tcp_next_seq; | |
689 | __be32 tcp_ack; | |
690 | int total_len; | |
691 | int frags_len; | |
692 | int sg_num; | |
693 | int in_use; | |
694 | __be16 window; | |
695 | u16 vlan_tag; | |
696 | u32 cur_tsval; | |
697 | __be32 cur_tsecr; | |
698 | u8 saw_ts; | |
699 | } ____cacheline_aligned; | |
700 | ||
20346722 | 701 | /* Ring specific structure */ |
1ee6dd77 | 702 | struct ring_info { |
20346722 | 703 | /* The ring number */ |
704 | int ring_no; | |
705 | ||
0425b46a SH |
706 | /* per-ring buffer counter */ |
707 | u32 rx_bufs_left; | |
708 | ||
709 | #define MAX_LRO_SESSIONS 32 | |
710 | struct lro lro0_n[MAX_LRO_SESSIONS]; | |
711 | u8 lro; | |
712 | ||
713 | /* copy of sp->rxd_mode flag */ | |
714 | int rxd_mode; | |
715 | ||
716 | /* Number of rxds per block for the rxd_mode */ | |
717 | int rxd_count; | |
718 | ||
719 | /* copy of sp pointer */ | |
720 | struct s2io_nic *nic; | |
721 | ||
722 | /* copy of sp->dev pointer */ | |
723 | struct net_device *dev; | |
724 | ||
725 | /* copy of sp->pdev pointer */ | |
726 | struct pci_dev *pdev; | |
727 | ||
20346722 | 728 | /* |
729 | * Place holders for the virtual and physical addresses of | |
730 | * all the Rx Blocks | |
731 | */ | |
1ee6dd77 | 732 | struct rx_block_info rx_blocks[MAX_RX_BLOCKS_PER_RING]; |
20346722 | 733 | int block_count; |
734 | int pkt_cnt; | |
735 | ||
736 | /* | |
737 | * Put pointer info which indictes which RxD has to be replenished | |
1da177e4 LT |
738 | * with a new buffer. |
739 | */ | |
1ee6dd77 | 740 | struct rx_curr_put_info rx_curr_put_info; |
1da177e4 | 741 | |
20346722 | 742 | /* |
743 | * Get pointer info which indictes which is the last RxD that was | |
1da177e4 LT |
744 | * processed by the driver. |
745 | */ | |
1ee6dd77 | 746 | struct rx_curr_get_info rx_curr_get_info; |
1da177e4 | 747 | |
0425b46a SH |
748 | /* interface MTU value */ |
749 | unsigned mtu; | |
750 | ||
20346722 | 751 | /* Buffer Address store. */ |
1ee6dd77 | 752 | struct buffAdd **ba; |
0425b46a SH |
753 | |
754 | /* per-Ring statistics */ | |
755 | unsigned long rx_packets; | |
756 | unsigned long rx_bytes; | |
757 | } ____cacheline_aligned; | |
1da177e4 | 758 | |
20346722 | 759 | /* Fifo specific structure */ |
1ee6dd77 | 760 | struct fifo_info { |
20346722 | 761 | /* FIFO number */ |
762 | int fifo_no; | |
763 | ||
764 | /* Maximum TxDs per TxDL */ | |
765 | int max_txds; | |
766 | ||
767 | /* Place holder of all the TX List's Phy and Virt addresses. */ | |
1ee6dd77 | 768 | struct list_info_hold *list_info; |
20346722 | 769 | |
770 | /* | |
771 | * Current offset within the tx FIFO where driver would write | |
772 | * new Tx frame | |
773 | */ | |
1ee6dd77 | 774 | struct tx_curr_put_info tx_curr_put_info; |
20346722 | 775 | |
776 | /* | |
777 | * Current offset within tx FIFO from where the driver would start freeing | |
778 | * the buffers | |
779 | */ | |
1ee6dd77 | 780 | struct tx_curr_get_info tx_curr_get_info; |
3a3d5756 SH |
781 | #define FIFO_QUEUE_START 0 |
782 | #define FIFO_QUEUE_STOP 1 | |
783 | int queue_state; | |
784 | ||
785 | /* copy of sp->dev pointer */ | |
786 | struct net_device *dev; | |
787 | ||
788 | /* copy of multiq status */ | |
789 | u8 multiq; | |
20346722 | 790 | |
2fda096d SR |
791 | /* Per fifo lock */ |
792 | spinlock_t tx_lock; | |
793 | ||
794 | /* Per fifo UFO in band structure */ | |
795 | u64 *ufo_in_band_v; | |
796 | ||
1ee6dd77 | 797 | struct s2io_nic *nic; |
2fda096d | 798 | } ____cacheline_aligned; |
20346722 | 799 | |
47bdd718 | 800 | /* Information related to the Tx and Rx FIFOs and Rings of Xena |
20346722 | 801 | * is maintained in this structure. |
802 | */ | |
1ee6dd77 | 803 | struct mac_info { |
1da177e4 LT |
804 | /* tx side stuff */ |
805 | /* logical pointer of start of each Tx FIFO */ | |
1ee6dd77 | 806 | struct TxFIFO_element __iomem *tx_FIFO_start[MAX_TX_FIFOS]; |
1da177e4 | 807 | |
20346722 | 808 | /* Fifo specific structure */ |
1ee6dd77 | 809 | struct fifo_info fifos[MAX_TX_FIFOS]; |
20346722 | 810 | |
776bd20f | 811 | /* Save virtual address of TxD page with zero DMA addr(if any) */ |
812 | void *zerodma_virt_addr; | |
813 | ||
20346722 | 814 | /* rx side stuff */ |
815 | /* Ring specific structure */ | |
1ee6dd77 | 816 | struct ring_info rings[MAX_RX_RINGS]; |
20346722 | 817 | |
818 | u16 rmac_pause_time; | |
819 | u16 mc_pause_threshold_q0q3; | |
820 | u16 mc_pause_threshold_q4q7; | |
1da177e4 LT |
821 | |
822 | void *stats_mem; /* orignal pointer to allocated mem */ | |
823 | dma_addr_t stats_mem_phy; /* Physical address of the stat block */ | |
824 | u32 stats_mem_sz; | |
1ee6dd77 RB |
825 | struct stat_block *stats_info; /* Logical address of the stat block */ |
826 | }; | |
1da177e4 LT |
827 | |
828 | /* structure representing the user defined MAC addresses */ | |
1ee6dd77 | 829 | struct usr_addr { |
1da177e4 LT |
830 | char addr[ETH_ALEN]; |
831 | int usage_cnt; | |
1ee6dd77 | 832 | }; |
1da177e4 | 833 | |
1da177e4 | 834 | /* Default Tunable parameters of the NIC. */ |
9dc737a7 AR |
835 | #define DEFAULT_FIFO_0_LEN 4096 |
836 | #define DEFAULT_FIFO_1_7_LEN 512 | |
c92ca04b AR |
837 | #define SMALL_BLK_CNT 30 |
838 | #define LARGE_BLK_CNT 100 | |
1da177e4 | 839 | |
cc6e7c44 RA |
840 | /* |
841 | * Structure to keep track of the MSI-X vectors and the corresponding | |
842 | * argument registered against each vector | |
843 | */ | |
844 | #define MAX_REQUESTED_MSI_X 17 | |
845 | struct s2io_msix_entry | |
846 | { | |
847 | u16 vector; | |
848 | u16 entry; | |
849 | void *arg; | |
850 | ||
851 | u8 type; | |
ac731ab6 SH |
852 | #define MSIX_ALARM_TYPE 1 |
853 | #define MSIX_RING_TYPE 2 | |
cc6e7c44 RA |
854 | |
855 | u8 in_use; | |
856 | #define MSIX_REGISTERED_SUCCESS 0xAA | |
857 | }; | |
858 | ||
859 | struct msix_info_st { | |
860 | u64 addr; | |
861 | u64 data; | |
862 | }; | |
863 | ||
92b84437 SS |
864 | /* These flags represent the devices temporary state */ |
865 | enum s2io_device_state_t | |
866 | { | |
867 | __S2IO_STATE_LINK_TASK=0, | |
868 | __S2IO_STATE_CARD_UP | |
869 | }; | |
870 | ||
1da177e4 | 871 | /* Structure representing one instance of the NIC */ |
20346722 | 872 | struct s2io_nic { |
da6971d8 | 873 | int rxd_mode; |
20346722 | 874 | /* |
875 | * Count of packets to be processed in a given iteration, it will be indicated | |
876 | * by the quota field of the device structure when NAPI is enabled. | |
877 | */ | |
878 | int pkts_to_process; | |
20346722 | 879 | struct net_device *dev; |
bea3348e | 880 | struct napi_struct napi; |
1ee6dd77 | 881 | struct mac_info mac_control; |
20346722 | 882 | struct config_param config; |
883 | struct pci_dev *pdev; | |
884 | void __iomem *bar0; | |
885 | void __iomem *bar1; | |
1da177e4 LT |
886 | #define MAX_MAC_SUPPORTED 16 |
887 | #define MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED | |
888 | ||
faa4f796 | 889 | struct mac_addr def_mac_addr[256]; |
1da177e4 LT |
890 | |
891 | struct net_device_stats stats; | |
1da177e4 | 892 | int high_dma_flag; |
1da177e4 LT |
893 | int device_enabled_once; |
894 | ||
c92ca04b | 895 | char name[60]; |
1da177e4 | 896 | |
25fff88e | 897 | /* Timer that handles I/O errors/exceptions */ |
898 | struct timer_list alarm_timer; | |
899 | ||
20346722 | 900 | /* Space to back up the PCI config space */ |
901 | u32 config_space[256 / sizeof(u32)]; | |
902 | ||
1da177e4 LT |
903 | #define PROMISC 1 |
904 | #define ALL_MULTI 2 | |
905 | ||
906 | #define MAX_ADDRS_SUPPORTED 64 | |
907 | u16 usr_addr_count; | |
908 | u16 mc_addr_count; | |
faa4f796 | 909 | struct usr_addr usr_addrs[256]; |
1da177e4 LT |
910 | |
911 | u16 m_cast_flg; | |
912 | u16 all_multi_pos; | |
913 | u16 promisc_flg; | |
914 | ||
1da177e4 LT |
915 | /* Id timer, used to blink NIC to physically identify NIC. */ |
916 | struct timer_list id_timer; | |
917 | ||
918 | /* Restart timer, used to restart NIC if the device is stuck and | |
20346722 | 919 | * a schedule task that will set the correct Link state once the |
1da177e4 LT |
920 | * NIC's PHY has stabilized after a state change. |
921 | */ | |
1da177e4 LT |
922 | struct work_struct rst_timer_task; |
923 | struct work_struct set_link_task; | |
1da177e4 | 924 | |
20346722 | 925 | /* Flag that can be used to turn on or turn off the Rx checksum |
1da177e4 LT |
926 | * offload feature. |
927 | */ | |
928 | int rx_csum; | |
929 | ||
6cfc482b SH |
930 | /* Below variables are used for fifo selection to transmit a packet */ |
931 | u16 fifo_selector[MAX_TX_FIFOS]; | |
932 | ||
933 | /* Total fifos for tcp packets */ | |
934 | u8 total_tcp_fifos; | |
935 | ||
936 | /* | |
937 | * Beginning index of udp for udp packets | |
938 | * Value will be equal to | |
939 | * (tx_fifo_num - FIFO_UDP_MAX_NUM - FIFO_OTHER_MAX_NUM) | |
940 | */ | |
941 | u8 udp_fifo_idx; | |
942 | ||
943 | u8 total_udp_fifos; | |
944 | ||
945 | /* | |
946 | * Beginning index of fifo for all other packets | |
947 | * Value will be equal to (tx_fifo_num - FIFO_OTHER_MAX_NUM) | |
948 | */ | |
949 | u8 other_fifo_idx; | |
950 | ||
20346722 | 951 | /* after blink, the adapter must be restored with original |
1da177e4 LT |
952 | * values. |
953 | */ | |
954 | u64 adapt_ctrl_org; | |
955 | ||
956 | /* Last known link state. */ | |
957 | u16 last_link_state; | |
958 | #define LINK_DOWN 1 | |
959 | #define LINK_UP 2 | |
960 | ||
1da177e4 | 961 | int task_flag; |
491976b2 | 962 | unsigned long long start_time; |
be3a6b02 | 963 | struct vlan_group *vlgrp; |
cc6e7c44 RA |
964 | #define MSIX_FLG 0xA5 |
965 | struct msix_entry *entries; | |
8abc4d5b SS |
966 | int msi_detected; |
967 | wait_queue_head_t msi_wait; | |
cc6e7c44 | 968 | struct s2io_msix_entry *s2io_entries; |
e6a8fee2 | 969 | char desc[MAX_REQUESTED_MSI_X][25]; |
cc6e7c44 | 970 | |
c92ca04b AR |
971 | int avail_msix_vectors; /* No. of MSI-X vectors granted by system */ |
972 | ||
cc6e7c44 RA |
973 | struct msix_info_st msix_info[0x3f]; |
974 | ||
541ae68f | 975 | #define XFRAME_I_DEVICE 1 |
976 | #define XFRAME_II_DEVICE 2 | |
977 | u8 device_type; | |
be3a6b02 | 978 | |
7d3d0439 RA |
979 | unsigned long clubbed_frms_cnt; |
980 | unsigned long sending_both; | |
981 | u8 lro; | |
982 | u16 lro_max_aggr_per_sess; | |
92b84437 | 983 | volatile unsigned long state; |
9caab458 | 984 | u64 general_int_mask; |
ac731ab6 | 985 | |
19a60522 SS |
986 | #define VPD_STRING_LEN 80 |
987 | u8 product_name[VPD_STRING_LEN]; | |
988 | u8 serial_num[VPD_STRING_LEN]; | |
20346722 | 989 | }; |
1da177e4 LT |
990 | |
991 | #define RESET_ERROR 1; | |
992 | #define CMD_ERROR 2; | |
993 | ||
994 | /* OS related system calls */ | |
995 | #ifndef readq | |
996 | static inline u64 readq(void __iomem *addr) | |
997 | { | |
20346722 | 998 | u64 ret = 0; |
999 | ret = readl(addr + 4); | |
7ef24b69 AM |
1000 | ret <<= 32; |
1001 | ret |= readl(addr); | |
1da177e4 LT |
1002 | |
1003 | return ret; | |
1004 | } | |
1005 | #endif | |
1006 | ||
1007 | #ifndef writeq | |
1008 | static inline void writeq(u64 val, void __iomem *addr) | |
1009 | { | |
1010 | writel((u32) (val), addr); | |
1011 | writel((u32) (val >> 32), (addr + 4)); | |
1012 | } | |
c92ca04b | 1013 | #endif |
1da177e4 | 1014 | |
6aa20a22 JG |
1015 | /* |
1016 | * Some registers have to be written in a particular order to | |
1017 | * expect correct hardware operation. The macro SPECIAL_REG_WRITE | |
1018 | * is used to perform such ordered writes. Defines UF (Upper First) | |
c92ca04b | 1019 | * and LF (Lower First) will be used to specify the required write order. |
1da177e4 LT |
1020 | */ |
1021 | #define UF 1 | |
1022 | #define LF 2 | |
1023 | static inline void SPECIAL_REG_WRITE(u64 val, void __iomem *addr, int order) | |
1024 | { | |
c92ca04b AR |
1025 | u32 ret; |
1026 | ||
1da177e4 LT |
1027 | if (order == LF) { |
1028 | writel((u32) (val), addr); | |
c92ca04b | 1029 | ret = readl(addr); |
1da177e4 | 1030 | writel((u32) (val >> 32), (addr + 4)); |
c92ca04b | 1031 | ret = readl(addr + 4); |
1da177e4 LT |
1032 | } else { |
1033 | writel((u32) (val >> 32), (addr + 4)); | |
c92ca04b | 1034 | ret = readl(addr + 4); |
1da177e4 | 1035 | writel((u32) (val), addr); |
c92ca04b | 1036 | ret = readl(addr); |
1da177e4 LT |
1037 | } |
1038 | } | |
1da177e4 LT |
1039 | |
1040 | /* Interrupt related values of Xena */ | |
1041 | ||
1042 | #define ENABLE_INTRS 1 | |
1043 | #define DISABLE_INTRS 2 | |
1044 | ||
1045 | /* Highest level interrupt blocks */ | |
1046 | #define TX_PIC_INTR (0x0001<<0) | |
1047 | #define TX_DMA_INTR (0x0001<<1) | |
1048 | #define TX_MAC_INTR (0x0001<<2) | |
1049 | #define TX_XGXS_INTR (0x0001<<3) | |
1050 | #define TX_TRAFFIC_INTR (0x0001<<4) | |
1051 | #define RX_PIC_INTR (0x0001<<5) | |
1052 | #define RX_DMA_INTR (0x0001<<6) | |
1053 | #define RX_MAC_INTR (0x0001<<7) | |
1054 | #define RX_XGXS_INTR (0x0001<<8) | |
1055 | #define RX_TRAFFIC_INTR (0x0001<<9) | |
1056 | #define MC_INTR (0x0001<<10) | |
1057 | #define ENA_ALL_INTRS ( TX_PIC_INTR | \ | |
1058 | TX_DMA_INTR | \ | |
1059 | TX_MAC_INTR | \ | |
1060 | TX_XGXS_INTR | \ | |
1061 | TX_TRAFFIC_INTR | \ | |
1062 | RX_PIC_INTR | \ | |
1063 | RX_DMA_INTR | \ | |
1064 | RX_MAC_INTR | \ | |
1065 | RX_XGXS_INTR | \ | |
1066 | RX_TRAFFIC_INTR | \ | |
1067 | MC_INTR ) | |
1068 | ||
1069 | /* Interrupt masks for the general interrupt mask register */ | |
1070 | #define DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL | |
1071 | ||
b7b5a128 JS |
1072 | #define TXPIC_INT_M s2BIT(0) |
1073 | #define TXDMA_INT_M s2BIT(1) | |
1074 | #define TXMAC_INT_M s2BIT(2) | |
1075 | #define TXXGXS_INT_M s2BIT(3) | |
1076 | #define TXTRAFFIC_INT_M s2BIT(8) | |
1077 | #define PIC_RX_INT_M s2BIT(32) | |
1078 | #define RXDMA_INT_M s2BIT(33) | |
1079 | #define RXMAC_INT_M s2BIT(34) | |
1080 | #define MC_INT_M s2BIT(35) | |
1081 | #define RXXGXS_INT_M s2BIT(36) | |
1082 | #define RXTRAFFIC_INT_M s2BIT(40) | |
1da177e4 LT |
1083 | |
1084 | /* PIC level Interrupts TODO*/ | |
1085 | ||
1086 | /* DMA level Inressupts */ | |
b7b5a128 JS |
1087 | #define TXDMA_PFC_INT_M s2BIT(0) |
1088 | #define TXDMA_PCC_INT_M s2BIT(2) | |
1da177e4 LT |
1089 | |
1090 | /* PFC block interrupts */ | |
b7b5a128 | 1091 | #define PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */ |
1da177e4 LT |
1092 | |
1093 | /* PCC block interrupts. */ | |
1094 | #define PCC_FB_ECC_ERR vBIT(0xff, 16, 8) /* Interrupt to indicate | |
1095 | PCC_FB_ECC Error. */ | |
1096 | ||
20346722 | 1097 | #define RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG) |
1da177e4 LT |
1098 | /* |
1099 | * Prototype declaration. | |
1100 | */ | |
1101 | static int __devinit s2io_init_nic(struct pci_dev *pdev, | |
1102 | const struct pci_device_id *pre); | |
1103 | static void __devexit s2io_rem_nic(struct pci_dev *pdev); | |
1104 | static int init_shared_mem(struct s2io_nic *sp); | |
1105 | static void free_shared_mem(struct s2io_nic *sp); | |
1106 | static int init_nic(struct s2io_nic *nic); | |
1ee6dd77 RB |
1107 | static void rx_intr_handler(struct ring_info *ring_data); |
1108 | static void tx_intr_handler(struct fifo_info *fifo_data); | |
8116f3cf | 1109 | static void s2io_handle_errors(void * dev_id); |
1da177e4 LT |
1110 | |
1111 | static int s2io_starter(void); | |
19a60522 | 1112 | static void s2io_closer(void); |
1da177e4 | 1113 | static void s2io_tx_watchdog(struct net_device *dev); |
1da177e4 | 1114 | static void s2io_set_multicast(struct net_device *dev); |
1ee6dd77 RB |
1115 | static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp); |
1116 | static void s2io_link(struct s2io_nic * sp, int link); | |
1117 | static void s2io_reset(struct s2io_nic * sp); | |
bea3348e | 1118 | static int s2io_poll(struct napi_struct *napi, int budget); |
1ee6dd77 | 1119 | static void s2io_init_pci(struct s2io_nic * sp); |
2fd37688 | 1120 | static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr); |
25fff88e | 1121 | static void s2io_alarm_handle(unsigned long data); |
cc6e7c44 | 1122 | static irqreturn_t |
7d12e780 | 1123 | s2io_msix_ring_handle(int irq, void *dev_id); |
cc6e7c44 | 1124 | static irqreturn_t |
7d12e780 DH |
1125 | s2io_msix_fifo_handle(int irq, void *dev_id); |
1126 | static irqreturn_t s2io_isr(int irq, void *dev_id); | |
1ee6dd77 | 1127 | static int verify_xena_quiescence(struct s2io_nic *sp); |
7282d491 | 1128 | static const struct ethtool_ops netdev_ethtool_ops; |
c4028958 | 1129 | static void s2io_set_link(struct work_struct *work); |
1ee6dd77 RB |
1130 | static int s2io_set_swapper(struct s2io_nic * sp); |
1131 | static void s2io_card_down(struct s2io_nic *nic); | |
1132 | static int s2io_card_up(struct s2io_nic *nic); | |
9fc93a41 SS |
1133 | static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit, |
1134 | int bit_state); | |
1ee6dd77 RB |
1135 | static int s2io_add_isr(struct s2io_nic * sp); |
1136 | static void s2io_rem_isr(struct s2io_nic * sp); | |
19a60522 | 1137 | |
1ee6dd77 | 1138 | static void restore_xmsi_data(struct s2io_nic *nic); |
faa4f796 SH |
1139 | static void do_s2io_store_unicast_mc(struct s2io_nic *sp); |
1140 | static void do_s2io_restore_unicast_mc(struct s2io_nic *sp); | |
1141 | static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset); | |
1142 | static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr); | |
1143 | static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int offset); | |
1144 | static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr); | |
7d3d0439 | 1145 | |
0425b46a SH |
1146 | static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer, |
1147 | u8 **tcp, u32 *tcp_len, struct lro **lro, struct RxD_t *rxdp, | |
1148 | struct s2io_nic *sp); | |
1ee6dd77 | 1149 | static void clear_lro_session(struct lro *lro); |
cdb5bf02 | 1150 | static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag); |
1ee6dd77 RB |
1151 | static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro); |
1152 | static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro, | |
1153 | struct sk_buff *skb, u32 tcp_len); | |
9fc93a41 | 1154 | static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring); |
b41477f3 | 1155 | |
d796fdb7 LV |
1156 | static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev, |
1157 | pci_channel_state_t state); | |
1158 | static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev); | |
1159 | static void s2io_io_resume(struct pci_dev *pdev); | |
1160 | ||
75c30b13 AR |
1161 | #define s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size |
1162 | #define s2io_udp_mss(skb) skb_shinfo(skb)->gso_size | |
1163 | #define s2io_offload_type(skb) skb_shinfo(skb)->gso_type | |
1164 | ||
b41477f3 AR |
1165 | #define S2IO_PARM_INT(X, def_val) \ |
1166 | static unsigned int X = def_val;\ | |
1167 | module_param(X , uint, 0); | |
1168 | ||
1da177e4 | 1169 | #endif /* _S2IO_H */ |