Commit | Line | Data |
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1da177e4 | 1 | /* |
f90fdc3c | 2 | * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation |
f5279ffd | 3 | * Copyright (c) 2006, 2007 Maciej W. Rozycki |
1da177e4 LT |
4 | * |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
74b0247f | 14 | * |
1da177e4 LT |
15 | * You should have received a copy of the GNU General Public License |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
18 | * | |
19 | * | |
20 | * This driver is designed for the Broadcom SiByte SOC built-in | |
21 | * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. | |
f5279ffd MR |
22 | * |
23 | * Updated to the driver model and the PHY abstraction layer | |
24 | * by Maciej W. Rozycki. | |
1da177e4 | 25 | */ |
f5279ffd MR |
26 | |
27 | #include <linux/bug.h> | |
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/kernel.h> | |
30 | #include <linux/string.h> | |
31 | #include <linux/timer.h> | |
32 | #include <linux/errno.h> | |
33 | #include <linux/ioport.h> | |
34 | #include <linux/slab.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/init.h> | |
1da177e4 | 40 | #include <linux/bitops.h> |
f5279ffd MR |
41 | #include <linux/err.h> |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/mii.h> | |
44 | #include <linux/phy.h> | |
45 | #include <linux/platform_device.h> | |
46 | ||
1da177e4 | 47 | #include <asm/cache.h> |
f5279ffd MR |
48 | #include <asm/io.h> |
49 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
1da177e4 LT |
50 | |
51 | /* This is only here until the firmware is ready. In that case, | |
52 | the firmware leaves the ethernet address in the register for us. */ | |
53 | #ifdef CONFIG_SIBYTE_STANDALONE | |
54 | #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00" | |
55 | #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01" | |
56 | #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02" | |
f90fdc3c | 57 | #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03" |
1da177e4 LT |
58 | #endif |
59 | ||
60 | ||
61 | /* These identify the driver base version and may not be removed. */ | |
62 | #if 0 | |
f5279ffd | 63 | static char version1[] __initdata = |
1da177e4 LT |
64 | "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n"; |
65 | #endif | |
66 | ||
67 | ||
68 | /* Operational parameters that usually are not changed. */ | |
69 | ||
70 | #define CONFIG_SBMAC_COALESCE | |
71 | ||
1da177e4 LT |
72 | /* Time in jiffies before concluding the transmitter is hung. */ |
73 | #define TX_TIMEOUT (2*HZ) | |
74 | ||
75 | ||
76 | MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)"); | |
77 | MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver"); | |
78 | ||
79 | /* A few user-configurable values which may be modified when a driver | |
80 | module is loaded. */ | |
81 | ||
82 | /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
83 | static int debug = 1; | |
84 | module_param(debug, int, S_IRUGO); | |
85 | MODULE_PARM_DESC(debug, "Debug messages"); | |
86 | ||
1da177e4 | 87 | #ifdef CONFIG_SBMAC_COALESCE |
693aa947 MM |
88 | static int int_pktcnt_tx = 255; |
89 | module_param(int_pktcnt_tx, int, S_IRUGO); | |
90 | MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count"); | |
1da177e4 | 91 | |
693aa947 MM |
92 | static int int_timeout_tx = 255; |
93 | module_param(int_timeout_tx, int, S_IRUGO); | |
94 | MODULE_PARM_DESC(int_timeout_tx, "TX timeout value"); | |
95 | ||
96 | static int int_pktcnt_rx = 64; | |
97 | module_param(int_pktcnt_rx, int, S_IRUGO); | |
98 | MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count"); | |
99 | ||
100 | static int int_timeout_rx = 64; | |
101 | module_param(int_timeout_rx, int, S_IRUGO); | |
102 | MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); | |
1da177e4 LT |
103 | #endif |
104 | ||
f5279ffd | 105 | #include <asm/sibyte/board.h> |
1da177e4 | 106 | #include <asm/sibyte/sb1250.h> |
f90fdc3c RB |
107 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
108 | #include <asm/sibyte/bcm1480_regs.h> | |
109 | #include <asm/sibyte/bcm1480_int.h> | |
693aa947 | 110 | #define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST |
f90fdc3c | 111 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) |
1da177e4 | 112 | #include <asm/sibyte/sb1250_regs.h> |
1da177e4 | 113 | #include <asm/sibyte/sb1250_int.h> |
f90fdc3c RB |
114 | #else |
115 | #error invalid SiByte MAC configuation | |
116 | #endif | |
1da177e4 | 117 | #include <asm/sibyte/sb1250_scd.h> |
f90fdc3c RB |
118 | #include <asm/sibyte/sb1250_mac.h> |
119 | #include <asm/sibyte/sb1250_dma.h> | |
1da177e4 | 120 | |
f90fdc3c RB |
121 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
122 | #define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2)) | |
123 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) | |
124 | #define UNIT_INT(n) (K_INT_MAC_0 + (n)) | |
125 | #else | |
126 | #error invalid SiByte MAC configuation | |
127 | #endif | |
1da177e4 | 128 | |
f5279ffd MR |
129 | #ifdef K_INT_PHY |
130 | #define SBMAC_PHY_INT K_INT_PHY | |
131 | #else | |
132 | #define SBMAC_PHY_INT PHY_POLL | |
133 | #endif | |
134 | ||
1da177e4 LT |
135 | /********************************************************************** |
136 | * Simple types | |
137 | ********************************************************************* */ | |
138 | ||
f5279ffd MR |
139 | enum sbmac_speed { |
140 | sbmac_speed_none = 0, | |
141 | sbmac_speed_10 = SPEED_10, | |
142 | sbmac_speed_100 = SPEED_100, | |
143 | sbmac_speed_1000 = SPEED_1000, | |
144 | }; | |
1da177e4 | 145 | |
f5279ffd MR |
146 | enum sbmac_duplex { |
147 | sbmac_duplex_none = -1, | |
148 | sbmac_duplex_half = DUPLEX_HALF, | |
149 | sbmac_duplex_full = DUPLEX_FULL, | |
150 | }; | |
1da177e4 | 151 | |
f5279ffd MR |
152 | enum sbmac_fc { |
153 | sbmac_fc_none, | |
154 | sbmac_fc_disabled, | |
155 | sbmac_fc_frame, | |
156 | sbmac_fc_collision, | |
157 | sbmac_fc_carrier, | |
158 | }; | |
1da177e4 | 159 | |
f5279ffd MR |
160 | enum sbmac_state { |
161 | sbmac_state_uninit, | |
162 | sbmac_state_off, | |
163 | sbmac_state_on, | |
164 | sbmac_state_broken, | |
165 | }; | |
1da177e4 LT |
166 | |
167 | ||
168 | /********************************************************************** | |
169 | * Macros | |
170 | ********************************************************************* */ | |
171 | ||
172 | ||
173 | #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ | |
174 | (d)->sbdma_dscrtable : (d)->f+1) | |
175 | ||
176 | ||
177 | #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) | |
178 | ||
693aa947 MM |
179 | #define SBMAC_MAX_TXDESCR 256 |
180 | #define SBMAC_MAX_RXDESCR 256 | |
1da177e4 | 181 | |
789585e9 | 182 | #define ETHER_ADDR_LEN 6 |
74b0247f RB |
183 | #define ENET_PACKET_SIZE 1518 |
184 | /*#define ENET_PACKET_SIZE 9216 */ | |
1da177e4 LT |
185 | |
186 | /********************************************************************** | |
187 | * DMA Descriptor structure | |
188 | ********************************************************************* */ | |
189 | ||
73d73969 | 190 | struct sbdmadscr { |
1da177e4 LT |
191 | uint64_t dscr_a; |
192 | uint64_t dscr_b; | |
73d73969 | 193 | }; |
1da177e4 LT |
194 | |
195 | /********************************************************************** | |
196 | * DMA Controller structure | |
197 | ********************************************************************* */ | |
198 | ||
73d73969 | 199 | struct sbmacdma { |
74b0247f RB |
200 | |
201 | /* | |
1da177e4 LT |
202 | * This stuff is used to identify the channel and the registers |
203 | * associated with it. | |
204 | */ | |
73d73969 MR |
205 | struct sbmac_softc *sbdma_eth; /* back pointer to associated |
206 | MAC */ | |
207 | int sbdma_channel; /* channel number */ | |
208 | int sbdma_txdir; /* direction (1=transmit) */ | |
209 | int sbdma_maxdescr; /* total # of descriptors | |
210 | in ring */ | |
1da177e4 | 211 | #ifdef CONFIG_SBMAC_COALESCE |
73d73969 MR |
212 | int sbdma_int_pktcnt; |
213 | /* # descriptors rx/tx | |
214 | before interrupt */ | |
215 | int sbdma_int_timeout; | |
216 | /* # usec rx/tx interrupt */ | |
1da177e4 | 217 | #endif |
73d73969 MR |
218 | void __iomem *sbdma_config0; /* DMA config register 0 */ |
219 | void __iomem *sbdma_config1; /* DMA config register 1 */ | |
220 | void __iomem *sbdma_dscrbase; | |
221 | /* descriptor base address */ | |
222 | void __iomem *sbdma_dscrcnt; /* descriptor count register */ | |
223 | void __iomem *sbdma_curdscr; /* current descriptor | |
224 | address */ | |
225 | void __iomem *sbdma_oodpktlost; | |
226 | /* pkt drop (rx only) */ | |
74b0247f | 227 | |
1da177e4 LT |
228 | /* |
229 | * This stuff is for maintenance of the ring | |
230 | */ | |
73d73969 MR |
231 | void *sbdma_dscrtable_unaligned; |
232 | struct sbdmadscr *sbdma_dscrtable; | |
233 | /* base of descriptor table */ | |
234 | struct sbdmadscr *sbdma_dscrtable_end; | |
235 | /* end of descriptor table */ | |
236 | struct sk_buff **sbdma_ctxtable; | |
237 | /* context table, one | |
238 | per descr */ | |
239 | dma_addr_t sbdma_dscrtable_phys; | |
240 | /* and also the phys addr */ | |
241 | struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */ | |
242 | struct sbdmadscr *sbdma_remptr; /* next dscr for sw | |
243 | to remove */ | |
244 | }; | |
1da177e4 LT |
245 | |
246 | ||
247 | /********************************************************************** | |
248 | * Ethernet softc structure | |
249 | ********************************************************************* */ | |
250 | ||
251 | struct sbmac_softc { | |
74b0247f | 252 | |
1da177e4 LT |
253 | /* |
254 | * Linux-specific things | |
255 | */ | |
73d73969 MR |
256 | struct net_device *sbm_dev; /* pointer to linux device */ |
257 | struct napi_struct napi; | |
f5279ffd | 258 | struct phy_device *phy_dev; /* the associated PHY device */ |
298cf9be | 259 | struct mii_bus *mii_bus; /* the MII bus */ |
f5279ffd | 260 | int phy_irq[PHY_MAX_ADDR]; |
73d73969 | 261 | spinlock_t sbm_lock; /* spin lock */ |
73d73969 | 262 | int sbm_devflags; /* current device flags */ |
74b0247f | 263 | |
1da177e4 LT |
264 | /* |
265 | * Controller-specific things | |
266 | */ | |
73d73969 MR |
267 | void __iomem *sbm_base; /* MAC's base address */ |
268 | enum sbmac_state sbm_state; /* current state */ | |
74b0247f | 269 | |
73d73969 MR |
270 | void __iomem *sbm_macenable; /* MAC Enable Register */ |
271 | void __iomem *sbm_maccfg; /* MAC Config Register */ | |
272 | void __iomem *sbm_fifocfg; /* FIFO Config Register */ | |
273 | void __iomem *sbm_framecfg; /* Frame Config Register */ | |
274 | void __iomem *sbm_rxfilter; /* Receive Filter Register */ | |
275 | void __iomem *sbm_isr; /* Interrupt Status Register */ | |
276 | void __iomem *sbm_imr; /* Interrupt Mask Register */ | |
277 | void __iomem *sbm_mdio; /* MDIO Register */ | |
74b0247f | 278 | |
73d73969 MR |
279 | enum sbmac_speed sbm_speed; /* current speed */ |
280 | enum sbmac_duplex sbm_duplex; /* current duplex */ | |
281 | enum sbmac_fc sbm_fc; /* cur. flow control setting */ | |
f5279ffd MR |
282 | int sbm_pause; /* current pause setting */ |
283 | int sbm_link; /* current link state */ | |
74b0247f | 284 | |
73d73969 | 285 | unsigned char sbm_hwaddr[ETHER_ADDR_LEN]; |
74b0247f | 286 | |
73d73969 MR |
287 | struct sbmacdma sbm_txdma; /* only channel 0 for now */ |
288 | struct sbmacdma sbm_rxdma; | |
289 | int rx_hw_checksum; | |
290 | int sbe_idx; | |
1da177e4 LT |
291 | }; |
292 | ||
293 | ||
294 | /********************************************************************** | |
295 | * Externs | |
296 | ********************************************************************* */ | |
297 | ||
298 | /********************************************************************** | |
299 | * Prototypes | |
300 | ********************************************************************* */ | |
301 | ||
73d73969 MR |
302 | static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, |
303 | int txrx, int maxdescr); | |
304 | static void sbdma_channel_start(struct sbmacdma *d, int rxtx); | |
789585e9 SH |
305 | static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, |
306 | struct sk_buff *m); | |
73d73969 MR |
307 | static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m); |
308 | static void sbdma_emptyring(struct sbmacdma *d); | |
789585e9 | 309 | static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d); |
73d73969 MR |
310 | static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
311 | int work_to_do, int poll); | |
312 | static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, | |
313 | int poll); | |
1da177e4 LT |
314 | static int sbmac_initctx(struct sbmac_softc *s); |
315 | static void sbmac_channel_start(struct sbmac_softc *s); | |
316 | static void sbmac_channel_stop(struct sbmac_softc *s); | |
73d73969 MR |
317 | static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *, |
318 | enum sbmac_state); | |
319 | static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); | |
1da177e4 | 320 | static uint64_t sbmac_addr2reg(unsigned char *ptr); |
73d73969 | 321 | static irqreturn_t sbmac_intr(int irq, void *dev_instance); |
1da177e4 LT |
322 | static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); |
323 | static void sbmac_setmulti(struct sbmac_softc *sc); | |
f5279ffd | 324 | static int sbmac_init(struct platform_device *pldev, long long base); |
73d73969 MR |
325 | static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed); |
326 | static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, | |
327 | enum sbmac_fc fc); | |
1da177e4 LT |
328 | |
329 | static int sbmac_open(struct net_device *dev); | |
1da177e4 | 330 | static void sbmac_tx_timeout (struct net_device *dev); |
1da177e4 LT |
331 | static void sbmac_set_rx_mode(struct net_device *dev); |
332 | static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
333 | static int sbmac_close(struct net_device *dev); | |
bea3348e | 334 | static int sbmac_poll(struct napi_struct *napi, int budget); |
693aa947 | 335 | |
f5279ffd | 336 | static void sbmac_mii_poll(struct net_device *dev); |
59b81827 | 337 | static int sbmac_mii_probe(struct net_device *dev); |
1da177e4 | 338 | |
f5279ffd MR |
339 | static void sbmac_mii_sync(void __iomem *sbm_mdio); |
340 | static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, | |
73d73969 | 341 | int bitcnt); |
f5279ffd MR |
342 | static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx); |
343 | static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, | |
344 | u16 val); | |
1da177e4 LT |
345 | |
346 | ||
347 | /********************************************************************** | |
348 | * Globals | |
349 | ********************************************************************* */ | |
350 | ||
f5279ffd MR |
351 | static char sbmac_string[] = "sb1250-mac"; |
352 | static char sbmac_pretty[] = "SB1250 MAC"; | |
353 | ||
354 | static char sbmac_mdio_string[] = "sb1250-mac-mdio"; | |
1da177e4 LT |
355 | |
356 | ||
357 | /********************************************************************** | |
358 | * MDIO constants | |
359 | ********************************************************************* */ | |
360 | ||
361 | #define MII_COMMAND_START 0x01 | |
362 | #define MII_COMMAND_READ 0x02 | |
363 | #define MII_COMMAND_WRITE 0x01 | |
364 | #define MII_COMMAND_ACK 0x02 | |
365 | ||
1da177e4 LT |
366 | #define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ |
367 | ||
368 | #define ENABLE 1 | |
369 | #define DISABLE 0 | |
370 | ||
371 | /********************************************************************** | |
f5279ffd | 372 | * SBMAC_MII_SYNC(sbm_mdio) |
74b0247f | 373 | * |
1da177e4 LT |
374 | * Synchronize with the MII - send a pattern of bits to the MII |
375 | * that will guarantee that it is ready to accept a command. | |
74b0247f RB |
376 | * |
377 | * Input parameters: | |
f5279ffd | 378 | * sbm_mdio - address of the MAC's MDIO register |
74b0247f | 379 | * |
1da177e4 LT |
380 | * Return value: |
381 | * nothing | |
382 | ********************************************************************* */ | |
383 | ||
f5279ffd | 384 | static void sbmac_mii_sync(void __iomem *sbm_mdio) |
1da177e4 LT |
385 | { |
386 | int cnt; | |
387 | uint64_t bits; | |
388 | int mac_mdio_genc; | |
389 | ||
f5279ffd | 390 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f | 391 | |
1da177e4 | 392 | bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; |
74b0247f | 393 | |
f5279ffd | 394 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
74b0247f | 395 | |
1da177e4 | 396 | for (cnt = 0; cnt < 32; cnt++) { |
f5279ffd MR |
397 | __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); |
398 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); | |
1da177e4 LT |
399 | } |
400 | } | |
401 | ||
402 | /********************************************************************** | |
f5279ffd | 403 | * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt) |
74b0247f | 404 | * |
1da177e4 LT |
405 | * Send some bits to the MII. The bits to be sent are right- |
406 | * justified in the 'data' parameter. | |
74b0247f RB |
407 | * |
408 | * Input parameters: | |
f5279ffd MR |
409 | * sbm_mdio - address of the MAC's MDIO register |
410 | * data - data to send | |
411 | * bitcnt - number of bits to send | |
1da177e4 LT |
412 | ********************************************************************* */ |
413 | ||
f5279ffd MR |
414 | static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, |
415 | int bitcnt) | |
1da177e4 LT |
416 | { |
417 | int i; | |
418 | uint64_t bits; | |
419 | unsigned int curmask; | |
420 | int mac_mdio_genc; | |
421 | ||
f5279ffd | 422 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f | 423 | |
1da177e4 | 424 | bits = M_MAC_MDIO_DIR_OUTPUT; |
f5279ffd | 425 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
74b0247f | 426 | |
1da177e4 | 427 | curmask = 1 << (bitcnt - 1); |
74b0247f | 428 | |
1da177e4 LT |
429 | for (i = 0; i < bitcnt; i++) { |
430 | if (data & curmask) | |
431 | bits |= M_MAC_MDIO_OUT; | |
432 | else bits &= ~M_MAC_MDIO_OUT; | |
f5279ffd MR |
433 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); |
434 | __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); | |
435 | __raw_writeq(bits | mac_mdio_genc, sbm_mdio); | |
1da177e4 LT |
436 | curmask >>= 1; |
437 | } | |
438 | } | |
439 | ||
440 | ||
441 | ||
442 | /********************************************************************** | |
f5279ffd | 443 | * SBMAC_MII_READ(bus, phyaddr, regidx) |
1da177e4 | 444 | * Read a PHY register. |
74b0247f RB |
445 | * |
446 | * Input parameters: | |
f5279ffd | 447 | * bus - MDIO bus handle |
1da177e4 | 448 | * phyaddr - PHY's address |
f5279ffd | 449 | * regnum - index of register to read |
74b0247f | 450 | * |
1da177e4 | 451 | * Return value: |
f5279ffd | 452 | * value read, or 0xffff if an error occurred. |
1da177e4 LT |
453 | ********************************************************************* */ |
454 | ||
f5279ffd | 455 | static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx) |
1da177e4 | 456 | { |
f5279ffd MR |
457 | struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; |
458 | void __iomem *sbm_mdio = sc->sbm_mdio; | |
1da177e4 LT |
459 | int idx; |
460 | int error; | |
461 | int regval; | |
462 | int mac_mdio_genc; | |
463 | ||
464 | /* | |
465 | * Synchronize ourselves so that the PHY knows the next | |
466 | * thing coming down is a command | |
467 | */ | |
f5279ffd | 468 | sbmac_mii_sync(sbm_mdio); |
74b0247f | 469 | |
1da177e4 LT |
470 | /* |
471 | * Send the data to the PHY. The sequence is | |
472 | * a "start" command (2 bits) | |
473 | * a "read" command (2 bits) | |
474 | * the PHY addr (5 bits) | |
475 | * the register index (5 bits) | |
476 | */ | |
f5279ffd MR |
477 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); |
478 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2); | |
479 | sbmac_mii_senddata(sbm_mdio, phyaddr, 5); | |
480 | sbmac_mii_senddata(sbm_mdio, regidx, 5); | |
74b0247f | 481 | |
f5279ffd | 482 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
74b0247f RB |
483 | |
484 | /* | |
1da177e4 LT |
485 | * Switch the port around without a clock transition. |
486 | */ | |
f5279ffd | 487 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); |
74b0247f | 488 | |
1da177e4 LT |
489 | /* |
490 | * Send out a clock pulse to signal we want the status | |
491 | */ | |
f5279ffd MR |
492 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
493 | sbm_mdio); | |
494 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
74b0247f RB |
495 | |
496 | /* | |
1da177e4 LT |
497 | * If an error occurred, the PHY will signal '1' back |
498 | */ | |
f5279ffd | 499 | error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN; |
74b0247f RB |
500 | |
501 | /* | |
1da177e4 LT |
502 | * Issue an 'idle' clock pulse, but keep the direction |
503 | * the same. | |
504 | */ | |
f5279ffd MR |
505 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
506 | sbm_mdio); | |
507 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
74b0247f | 508 | |
1da177e4 | 509 | regval = 0; |
74b0247f | 510 | |
1da177e4 LT |
511 | for (idx = 0; idx < 16; idx++) { |
512 | regval <<= 1; | |
74b0247f | 513 | |
1da177e4 | 514 | if (error == 0) { |
f5279ffd | 515 | if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN) |
1da177e4 LT |
516 | regval |= 1; |
517 | } | |
74b0247f | 518 | |
f5279ffd MR |
519 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, |
520 | sbm_mdio); | |
521 | __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); | |
1da177e4 | 522 | } |
74b0247f | 523 | |
1da177e4 | 524 | /* Switch back to output */ |
f5279ffd | 525 | __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); |
74b0247f | 526 | |
1da177e4 LT |
527 | if (error == 0) |
528 | return regval; | |
f5279ffd | 529 | return 0xffff; |
1da177e4 LT |
530 | } |
531 | ||
532 | ||
533 | /********************************************************************** | |
f5279ffd | 534 | * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval) |
74b0247f | 535 | * |
1da177e4 | 536 | * Write a value to a PHY register. |
74b0247f RB |
537 | * |
538 | * Input parameters: | |
f5279ffd | 539 | * bus - MDIO bus handle |
1da177e4 | 540 | * phyaddr - PHY to use |
f5279ffd MR |
541 | * regidx - register within the PHY |
542 | * regval - data to write to register | |
74b0247f | 543 | * |
1da177e4 | 544 | * Return value: |
f5279ffd | 545 | * 0 for success |
1da177e4 LT |
546 | ********************************************************************* */ |
547 | ||
f5279ffd MR |
548 | static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, |
549 | u16 regval) | |
1da177e4 | 550 | { |
f5279ffd MR |
551 | struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; |
552 | void __iomem *sbm_mdio = sc->sbm_mdio; | |
1da177e4 LT |
553 | int mac_mdio_genc; |
554 | ||
f5279ffd | 555 | sbmac_mii_sync(sbm_mdio); |
74b0247f | 556 | |
f5279ffd MR |
557 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); |
558 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2); | |
559 | sbmac_mii_senddata(sbm_mdio, phyaddr, 5); | |
560 | sbmac_mii_senddata(sbm_mdio, regidx, 5); | |
561 | sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2); | |
562 | sbmac_mii_senddata(sbm_mdio, regval, 16); | |
1da177e4 | 563 | |
f5279ffd | 564 | mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; |
1da177e4 | 565 | |
f5279ffd MR |
566 | __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); |
567 | ||
568 | return 0; | |
1da177e4 LT |
569 | } |
570 | ||
571 | ||
572 | ||
573 | /********************************************************************** | |
574 | * SBDMA_INITCTX(d,s,chan,txrx,maxdescr) | |
74b0247f | 575 | * |
1da177e4 LT |
576 | * Initialize a DMA channel context. Since there are potentially |
577 | * eight DMA channels per MAC, it's nice to do this in a standard | |
74b0247f RB |
578 | * way. |
579 | * | |
580 | * Input parameters: | |
73d73969 MR |
581 | * d - struct sbmacdma (DMA channel context) |
582 | * s - struct sbmac_softc (pointer to a MAC) | |
1da177e4 LT |
583 | * chan - channel number (0..1 right now) |
584 | * txrx - Identifies DMA_TX or DMA_RX for channel direction | |
585 | * maxdescr - number of descriptors | |
74b0247f | 586 | * |
1da177e4 LT |
587 | * Return value: |
588 | * nothing | |
589 | ********************************************************************* */ | |
590 | ||
73d73969 MR |
591 | static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, |
592 | int txrx, int maxdescr) | |
1da177e4 | 593 | { |
693aa947 MM |
594 | #ifdef CONFIG_SBMAC_COALESCE |
595 | int int_pktcnt, int_timeout; | |
596 | #endif | |
597 | ||
74b0247f RB |
598 | /* |
599 | * Save away interesting stuff in the structure | |
1da177e4 | 600 | */ |
74b0247f | 601 | |
1da177e4 LT |
602 | d->sbdma_eth = s; |
603 | d->sbdma_channel = chan; | |
604 | d->sbdma_txdir = txrx; | |
74b0247f | 605 | |
1da177e4 LT |
606 | #if 0 |
607 | /* RMON clearing */ | |
608 | s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; | |
609 | #endif | |
610 | ||
f5279ffd MR |
611 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES); |
612 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS); | |
613 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL); | |
614 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL); | |
615 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR); | |
616 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT); | |
617 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD); | |
618 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD); | |
619 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT); | |
620 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE); | |
621 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES); | |
622 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST); | |
623 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST); | |
624 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD); | |
625 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD); | |
626 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT); | |
627 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE); | |
628 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR); | |
629 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR); | |
630 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR); | |
631 | __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR); | |
1da177e4 | 632 | |
74b0247f RB |
633 | /* |
634 | * initialize register pointers | |
1da177e4 | 635 | */ |
74b0247f RB |
636 | |
637 | d->sbdma_config0 = | |
1da177e4 | 638 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); |
74b0247f | 639 | d->sbdma_config1 = |
1da177e4 | 640 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); |
74b0247f | 641 | d->sbdma_dscrbase = |
1da177e4 | 642 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); |
74b0247f | 643 | d->sbdma_dscrcnt = |
1da177e4 | 644 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); |
74b0247f | 645 | d->sbdma_curdscr = |
1da177e4 | 646 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); |
693aa947 MM |
647 | if (d->sbdma_txdir) |
648 | d->sbdma_oodpktlost = NULL; | |
649 | else | |
650 | d->sbdma_oodpktlost = | |
651 | s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX); | |
74b0247f | 652 | |
1da177e4 LT |
653 | /* |
654 | * Allocate memory for the ring | |
655 | */ | |
74b0247f | 656 | |
1da177e4 | 657 | d->sbdma_maxdescr = maxdescr; |
74b0247f | 658 | |
73d73969 MR |
659 | d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1, |
660 | sizeof(*d->sbdma_dscrtable), | |
661 | GFP_KERNEL); | |
04115def RB |
662 | |
663 | /* | |
664 | * The descriptor table must be aligned to at least 16 bytes or the | |
665 | * MAC will corrupt it. | |
666 | */ | |
73d73969 MR |
667 | d->sbdma_dscrtable = (struct sbdmadscr *) |
668 | ALIGN((unsigned long)d->sbdma_dscrtable_unaligned, | |
669 | sizeof(*d->sbdma_dscrtable)); | |
74b0247f | 670 | |
1da177e4 | 671 | d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; |
74b0247f | 672 | |
1da177e4 | 673 | d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); |
74b0247f | 674 | |
1da177e4 LT |
675 | /* |
676 | * And context table | |
677 | */ | |
74b0247f | 678 | |
c477f334 | 679 | d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr, |
73d73969 | 680 | sizeof(*d->sbdma_ctxtable), GFP_KERNEL); |
74b0247f | 681 | |
1da177e4 LT |
682 | #ifdef CONFIG_SBMAC_COALESCE |
683 | /* | |
684 | * Setup Rx/Tx DMA coalescing defaults | |
685 | */ | |
686 | ||
693aa947 | 687 | int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx; |
1da177e4 LT |
688 | if ( int_pktcnt ) { |
689 | d->sbdma_int_pktcnt = int_pktcnt; | |
690 | } else { | |
691 | d->sbdma_int_pktcnt = 1; | |
692 | } | |
74b0247f | 693 | |
693aa947 | 694 | int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx; |
1da177e4 LT |
695 | if ( int_timeout ) { |
696 | d->sbdma_int_timeout = int_timeout; | |
697 | } else { | |
698 | d->sbdma_int_timeout = 0; | |
699 | } | |
700 | #endif | |
701 | ||
702 | } | |
703 | ||
704 | /********************************************************************** | |
705 | * SBDMA_CHANNEL_START(d) | |
74b0247f | 706 | * |
1da177e4 | 707 | * Initialize the hardware registers for a DMA channel. |
74b0247f RB |
708 | * |
709 | * Input parameters: | |
1da177e4 LT |
710 | * d - DMA channel to init (context must be previously init'd |
711 | * rxtx - DMA_RX or DMA_TX depending on what type of channel | |
74b0247f | 712 | * |
1da177e4 LT |
713 | * Return value: |
714 | * nothing | |
715 | ********************************************************************* */ | |
716 | ||
73d73969 | 717 | static void sbdma_channel_start(struct sbmacdma *d, int rxtx) |
1da177e4 LT |
718 | { |
719 | /* | |
720 | * Turn on the DMA channel | |
721 | */ | |
74b0247f | 722 | |
1da177e4 | 723 | #ifdef CONFIG_SBMAC_COALESCE |
2039973a RB |
724 | __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | |
725 | 0, d->sbdma_config1); | |
726 | __raw_writeq(M_DMA_EOP_INT_EN | | |
1da177e4 LT |
727 | V_DMA_RINGSZ(d->sbdma_maxdescr) | |
728 | V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | | |
2039973a | 729 | 0, d->sbdma_config0); |
1da177e4 | 730 | #else |
2039973a RB |
731 | __raw_writeq(0, d->sbdma_config1); |
732 | __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) | | |
733 | 0, d->sbdma_config0); | |
1da177e4 LT |
734 | #endif |
735 | ||
2039973a | 736 | __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase); |
1da177e4 LT |
737 | |
738 | /* | |
739 | * Initialize ring pointers | |
740 | */ | |
741 | ||
742 | d->sbdma_addptr = d->sbdma_dscrtable; | |
743 | d->sbdma_remptr = d->sbdma_dscrtable; | |
744 | } | |
745 | ||
746 | /********************************************************************** | |
747 | * SBDMA_CHANNEL_STOP(d) | |
74b0247f | 748 | * |
1da177e4 | 749 | * Initialize the hardware registers for a DMA channel. |
74b0247f RB |
750 | * |
751 | * Input parameters: | |
1da177e4 | 752 | * d - DMA channel to init (context must be previously init'd |
74b0247f | 753 | * |
1da177e4 LT |
754 | * Return value: |
755 | * nothing | |
756 | ********************************************************************* */ | |
757 | ||
73d73969 | 758 | static void sbdma_channel_stop(struct sbmacdma *d) |
1da177e4 LT |
759 | { |
760 | /* | |
761 | * Turn off the DMA channel | |
762 | */ | |
74b0247f | 763 | |
2039973a | 764 | __raw_writeq(0, d->sbdma_config1); |
74b0247f | 765 | |
2039973a | 766 | __raw_writeq(0, d->sbdma_dscrbase); |
74b0247f | 767 | |
2039973a | 768 | __raw_writeq(0, d->sbdma_config0); |
74b0247f | 769 | |
1da177e4 LT |
770 | /* |
771 | * Zero ring pointers | |
772 | */ | |
74b0247f | 773 | |
2039973a RB |
774 | d->sbdma_addptr = NULL; |
775 | d->sbdma_remptr = NULL; | |
1da177e4 LT |
776 | } |
777 | ||
789585e9 SH |
778 | static inline void sbdma_align_skb(struct sk_buff *skb, |
779 | unsigned int power2, unsigned int offset) | |
1da177e4 | 780 | { |
789585e9 SH |
781 | unsigned char *addr = skb->data; |
782 | unsigned char *newaddr = PTR_ALIGN(addr, power2); | |
74b0247f | 783 | |
789585e9 | 784 | skb_reserve(skb, newaddr - addr + offset); |
1da177e4 LT |
785 | } |
786 | ||
787 | ||
788 | /********************************************************************** | |
789 | * SBDMA_ADD_RCVBUFFER(d,sb) | |
74b0247f | 790 | * |
1da177e4 LT |
791 | * Add a buffer to the specified DMA channel. For receive channels, |
792 | * this queues a buffer for inbound packets. | |
74b0247f RB |
793 | * |
794 | * Input parameters: | |
789585e9 SH |
795 | * sc - softc structure |
796 | * d - DMA channel descriptor | |
1da177e4 | 797 | * sb - sk_buff to add, or NULL if we should allocate one |
74b0247f | 798 | * |
1da177e4 LT |
799 | * Return value: |
800 | * 0 if buffer could not be added (ring is full) | |
801 | * 1 if buffer added successfully | |
802 | ********************************************************************* */ | |
803 | ||
804 | ||
789585e9 SH |
805 | static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, |
806 | struct sk_buff *sb) | |
1da177e4 | 807 | { |
789585e9 | 808 | struct net_device *dev = sc->sbm_dev; |
73d73969 MR |
809 | struct sbdmadscr *dsc; |
810 | struct sbdmadscr *nextdsc; | |
1da177e4 LT |
811 | struct sk_buff *sb_new = NULL; |
812 | int pktsize = ENET_PACKET_SIZE; | |
74b0247f | 813 | |
1da177e4 | 814 | /* get pointer to our current place in the ring */ |
74b0247f | 815 | |
1da177e4 LT |
816 | dsc = d->sbdma_addptr; |
817 | nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); | |
74b0247f | 818 | |
1da177e4 LT |
819 | /* |
820 | * figure out if the ring is full - if the next descriptor | |
821 | * is the same as the one that we're going to remove from | |
822 | * the ring, the ring is full | |
823 | */ | |
74b0247f | 824 | |
1da177e4 LT |
825 | if (nextdsc == d->sbdma_remptr) { |
826 | return -ENOSPC; | |
827 | } | |
828 | ||
74b0247f RB |
829 | /* |
830 | * Allocate a sk_buff if we don't already have one. | |
1da177e4 LT |
831 | * If we do have an sk_buff, reset it so that it's empty. |
832 | * | |
833 | * Note: sk_buffs don't seem to be guaranteed to have any sort | |
834 | * of alignment when they are allocated. Therefore, allocate enough | |
835 | * extra space to make sure that: | |
836 | * | |
837 | * 1. the data does not start in the middle of a cache line. | |
838 | * 2. The data does not end in the middle of a cache line | |
74b0247f | 839 | * 3. The buffer can be aligned such that the IP addresses are |
1da177e4 LT |
840 | * naturally aligned. |
841 | * | |
842 | * Remember, the SOCs MAC writes whole cache lines at a time, | |
843 | * without reading the old contents first. So, if the sk_buff's | |
844 | * data portion starts in the middle of a cache line, the SOC | |
845 | * DMA will trash the beginning (and ending) portions. | |
846 | */ | |
74b0247f | 847 | |
1da177e4 | 848 | if (sb == NULL) { |
789585e9 SH |
849 | sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE + |
850 | SMP_CACHE_BYTES * 2 + | |
851 | NET_IP_ALIGN); | |
1da177e4 | 852 | if (sb_new == NULL) { |
f5279ffd | 853 | pr_info("%s: sk_buff allocation failed\n", |
1da177e4 LT |
854 | d->sbdma_eth->sbm_dev->name); |
855 | return -ENOBUFS; | |
856 | } | |
857 | ||
789585e9 | 858 | sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN); |
1da177e4 LT |
859 | } |
860 | else { | |
861 | sb_new = sb; | |
74b0247f | 862 | /* |
1da177e4 LT |
863 | * nothing special to reinit buffer, it's already aligned |
864 | * and sb->data already points to a good place. | |
865 | */ | |
866 | } | |
74b0247f | 867 | |
1da177e4 | 868 | /* |
74b0247f | 869 | * fill in the descriptor |
1da177e4 | 870 | */ |
74b0247f | 871 | |
1da177e4 LT |
872 | #ifdef CONFIG_SBMAC_COALESCE |
873 | /* | |
874 | * Do not interrupt per DMA transfer. | |
875 | */ | |
689be439 | 876 | dsc->dscr_a = virt_to_phys(sb_new->data) | |
789585e9 | 877 | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0; |
1da177e4 | 878 | #else |
689be439 | 879 | dsc->dscr_a = virt_to_phys(sb_new->data) | |
789585e9 | 880 | V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | |
1da177e4 LT |
881 | M_DMA_DSCRA_INTERRUPT; |
882 | #endif | |
883 | ||
884 | /* receiving: no options */ | |
885 | dsc->dscr_b = 0; | |
74b0247f | 886 | |
1da177e4 | 887 | /* |
74b0247f | 888 | * fill in the context |
1da177e4 | 889 | */ |
74b0247f | 890 | |
1da177e4 | 891 | d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; |
74b0247f RB |
892 | |
893 | /* | |
894 | * point at next packet | |
1da177e4 | 895 | */ |
74b0247f | 896 | |
1da177e4 | 897 | d->sbdma_addptr = nextdsc; |
74b0247f RB |
898 | |
899 | /* | |
1da177e4 LT |
900 | * Give the buffer to the DMA engine. |
901 | */ | |
74b0247f | 902 | |
2039973a | 903 | __raw_writeq(1, d->sbdma_dscrcnt); |
74b0247f | 904 | |
1da177e4 LT |
905 | return 0; /* we did it */ |
906 | } | |
907 | ||
908 | /********************************************************************** | |
909 | * SBDMA_ADD_TXBUFFER(d,sb) | |
74b0247f | 910 | * |
1da177e4 LT |
911 | * Add a transmit buffer to the specified DMA channel, causing a |
912 | * transmit to start. | |
74b0247f RB |
913 | * |
914 | * Input parameters: | |
1da177e4 LT |
915 | * d - DMA channel descriptor |
916 | * sb - sk_buff to add | |
74b0247f | 917 | * |
1da177e4 LT |
918 | * Return value: |
919 | * 0 transmit queued successfully | |
920 | * otherwise error code | |
921 | ********************************************************************* */ | |
922 | ||
923 | ||
73d73969 | 924 | static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb) |
1da177e4 | 925 | { |
73d73969 MR |
926 | struct sbdmadscr *dsc; |
927 | struct sbdmadscr *nextdsc; | |
1da177e4 LT |
928 | uint64_t phys; |
929 | uint64_t ncb; | |
930 | int length; | |
74b0247f | 931 | |
1da177e4 | 932 | /* get pointer to our current place in the ring */ |
74b0247f | 933 | |
1da177e4 LT |
934 | dsc = d->sbdma_addptr; |
935 | nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); | |
74b0247f | 936 | |
1da177e4 LT |
937 | /* |
938 | * figure out if the ring is full - if the next descriptor | |
939 | * is the same as the one that we're going to remove from | |
940 | * the ring, the ring is full | |
941 | */ | |
74b0247f | 942 | |
1da177e4 LT |
943 | if (nextdsc == d->sbdma_remptr) { |
944 | return -ENOSPC; | |
945 | } | |
74b0247f | 946 | |
1da177e4 LT |
947 | /* |
948 | * Under Linux, it's not necessary to copy/coalesce buffers | |
949 | * like it is on NetBSD. We think they're all contiguous, | |
950 | * but that may not be true for GBE. | |
951 | */ | |
74b0247f | 952 | |
1da177e4 | 953 | length = sb->len; |
74b0247f | 954 | |
1da177e4 LT |
955 | /* |
956 | * fill in the descriptor. Note that the number of cache | |
957 | * blocks in the descriptor is the number of blocks | |
958 | * *spanned*, so we need to add in the offset (if any) | |
959 | * while doing the calculation. | |
960 | */ | |
74b0247f | 961 | |
1da177e4 LT |
962 | phys = virt_to_phys(sb->data); |
963 | ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); | |
964 | ||
74b0247f | 965 | dsc->dscr_a = phys | |
1da177e4 LT |
966 | V_DMA_DSCRA_A_SIZE(ncb) | |
967 | #ifndef CONFIG_SBMAC_COALESCE | |
968 | M_DMA_DSCRA_INTERRUPT | | |
969 | #endif | |
970 | M_DMA_ETHTX_SOP; | |
74b0247f | 971 | |
1da177e4 LT |
972 | /* transmitting: set outbound options and length */ |
973 | ||
974 | dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | | |
975 | V_DMA_DSCRB_PKT_SIZE(length); | |
74b0247f | 976 | |
1da177e4 | 977 | /* |
74b0247f | 978 | * fill in the context |
1da177e4 | 979 | */ |
74b0247f | 980 | |
1da177e4 | 981 | d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; |
74b0247f RB |
982 | |
983 | /* | |
984 | * point at next packet | |
1da177e4 | 985 | */ |
74b0247f | 986 | |
1da177e4 | 987 | d->sbdma_addptr = nextdsc; |
74b0247f RB |
988 | |
989 | /* | |
1da177e4 LT |
990 | * Give the buffer to the DMA engine. |
991 | */ | |
74b0247f | 992 | |
2039973a | 993 | __raw_writeq(1, d->sbdma_dscrcnt); |
74b0247f | 994 | |
1da177e4 LT |
995 | return 0; /* we did it */ |
996 | } | |
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | /********************************************************************** | |
1002 | * SBDMA_EMPTYRING(d) | |
74b0247f | 1003 | * |
1da177e4 | 1004 | * Free all allocated sk_buffs on the specified DMA channel; |
74b0247f RB |
1005 | * |
1006 | * Input parameters: | |
1da177e4 | 1007 | * d - DMA channel |
74b0247f | 1008 | * |
1da177e4 LT |
1009 | * Return value: |
1010 | * nothing | |
1011 | ********************************************************************* */ | |
1012 | ||
73d73969 | 1013 | static void sbdma_emptyring(struct sbmacdma *d) |
1da177e4 LT |
1014 | { |
1015 | int idx; | |
1016 | struct sk_buff *sb; | |
74b0247f | 1017 | |
1da177e4 LT |
1018 | for (idx = 0; idx < d->sbdma_maxdescr; idx++) { |
1019 | sb = d->sbdma_ctxtable[idx]; | |
1020 | if (sb) { | |
1021 | dev_kfree_skb(sb); | |
1022 | d->sbdma_ctxtable[idx] = NULL; | |
1023 | } | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | ||
1028 | /********************************************************************** | |
1029 | * SBDMA_FILLRING(d) | |
74b0247f | 1030 | * |
1da177e4 LT |
1031 | * Fill the specified DMA channel (must be receive channel) |
1032 | * with sk_buffs | |
74b0247f RB |
1033 | * |
1034 | * Input parameters: | |
789585e9 SH |
1035 | * sc - softc structure |
1036 | * d - DMA channel | |
74b0247f | 1037 | * |
1da177e4 LT |
1038 | * Return value: |
1039 | * nothing | |
1040 | ********************************************************************* */ | |
1041 | ||
789585e9 | 1042 | static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d) |
1da177e4 LT |
1043 | { |
1044 | int idx; | |
74b0247f | 1045 | |
789585e9 SH |
1046 | for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) { |
1047 | if (sbdma_add_rcvbuffer(sc, d, NULL) != 0) | |
1da177e4 LT |
1048 | break; |
1049 | } | |
1050 | } | |
1051 | ||
d6830018 DS |
1052 | #ifdef CONFIG_NET_POLL_CONTROLLER |
1053 | static void sbmac_netpoll(struct net_device *netdev) | |
1054 | { | |
1055 | struct sbmac_softc *sc = netdev_priv(netdev); | |
1056 | int irq = sc->sbm_dev->irq; | |
1057 | ||
1058 | __raw_writeq(0, sc->sbm_imr); | |
1059 | ||
0da2f0f1 | 1060 | sbmac_intr(irq, netdev); |
d6830018 DS |
1061 | |
1062 | #ifdef CONFIG_SBMAC_COALESCE | |
1063 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | | |
1064 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), | |
1065 | sc->sbm_imr); | |
1066 | #else | |
7d2e3cb7 | 1067 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | |
d6830018 DS |
1068 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); |
1069 | #endif | |
1070 | } | |
1071 | #endif | |
1da177e4 LT |
1072 | |
1073 | /********************************************************************** | |
693aa947 | 1074 | * SBDMA_RX_PROCESS(sc,d,work_to_do,poll) |
74b0247f RB |
1075 | * |
1076 | * Process "completed" receive buffers on the specified DMA channel. | |
1da177e4 | 1077 | * |
74b0247f | 1078 | * Input parameters: |
693aa947 MM |
1079 | * sc - softc structure |
1080 | * d - DMA channel context | |
1081 | * work_to_do - no. of packets to process before enabling interrupt | |
1082 | * again (for NAPI) | |
1083 | * poll - 1: using polling (for NAPI) | |
74b0247f | 1084 | * |
1da177e4 LT |
1085 | * Return value: |
1086 | * nothing | |
1087 | ********************************************************************* */ | |
1088 | ||
73d73969 MR |
1089 | static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
1090 | int work_to_do, int poll) | |
1da177e4 | 1091 | { |
09f75cd7 | 1092 | struct net_device *dev = sc->sbm_dev; |
1da177e4 LT |
1093 | int curidx; |
1094 | int hwidx; | |
73d73969 | 1095 | struct sbdmadscr *dsc; |
1da177e4 LT |
1096 | struct sk_buff *sb; |
1097 | int len; | |
693aa947 MM |
1098 | int work_done = 0; |
1099 | int dropped = 0; | |
74b0247f | 1100 | |
693aa947 MM |
1101 | prefetch(d); |
1102 | ||
1103 | again: | |
1104 | /* Check if the HW dropped any frames */ | |
09f75cd7 | 1105 | dev->stats.rx_fifo_errors |
693aa947 MM |
1106 | += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff; |
1107 | __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost); | |
1108 | ||
1109 | while (work_to_do-- > 0) { | |
74b0247f | 1110 | /* |
1da177e4 LT |
1111 | * figure out where we are (as an index) and where |
1112 | * the hardware is (also as an index) | |
1113 | * | |
74b0247f | 1114 | * This could be done faster if (for example) the |
1da177e4 LT |
1115 | * descriptor table was page-aligned and contiguous in |
1116 | * both virtual and physical memory -- you could then | |
1117 | * just compare the low-order bits of the virtual address | |
1118 | * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) | |
1119 | */ | |
74b0247f | 1120 | |
693aa947 MM |
1121 | dsc = d->sbdma_remptr; |
1122 | curidx = dsc - d->sbdma_dscrtable; | |
1123 | ||
1124 | prefetch(dsc); | |
1125 | prefetch(&d->sbdma_ctxtable[curidx]); | |
1126 | ||
73d73969 MR |
1127 | hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - |
1128 | d->sbdma_dscrtable_phys) / | |
1129 | sizeof(*d->sbdma_dscrtable); | |
74b0247f | 1130 | |
1da177e4 LT |
1131 | /* |
1132 | * If they're the same, that means we've processed all | |
1133 | * of the descriptors up to (but not including) the one that | |
1134 | * the hardware is working on right now. | |
1135 | */ | |
74b0247f | 1136 | |
1da177e4 | 1137 | if (curidx == hwidx) |
693aa947 | 1138 | goto done; |
74b0247f | 1139 | |
1da177e4 LT |
1140 | /* |
1141 | * Otherwise, get the packet's sk_buff ptr back | |
1142 | */ | |
74b0247f | 1143 | |
1da177e4 LT |
1144 | sb = d->sbdma_ctxtable[curidx]; |
1145 | d->sbdma_ctxtable[curidx] = NULL; | |
74b0247f | 1146 | |
1da177e4 | 1147 | len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; |
74b0247f | 1148 | |
1da177e4 LT |
1149 | /* |
1150 | * Check packet status. If good, process it. | |
1151 | * If not, silently drop it and put it back on the | |
1152 | * receive ring. | |
1153 | */ | |
74b0247f | 1154 | |
693aa947 | 1155 | if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) { |
74b0247f | 1156 | |
1da177e4 LT |
1157 | /* |
1158 | * Add a new buffer to replace the old one. If we fail | |
1159 | * to allocate a buffer, we're going to drop this | |
1160 | * packet and put it right back on the receive ring. | |
1161 | */ | |
74b0247f | 1162 | |
789585e9 SH |
1163 | if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) == |
1164 | -ENOBUFS)) { | |
09f75cd7 | 1165 | dev->stats.rx_dropped++; |
789585e9 SH |
1166 | /* Re-add old buffer */ |
1167 | sbdma_add_rcvbuffer(sc, d, sb); | |
693aa947 MM |
1168 | /* No point in continuing at the moment */ |
1169 | printk(KERN_ERR "dropped packet (1)\n"); | |
1170 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
1171 | goto done; | |
1da177e4 LT |
1172 | } else { |
1173 | /* | |
1174 | * Set length into the packet | |
1175 | */ | |
1176 | skb_put(sb,len); | |
74b0247f | 1177 | |
1da177e4 LT |
1178 | /* |
1179 | * Buffer has been replaced on the | |
1180 | * receive ring. Pass the buffer to | |
1181 | * the kernel | |
1182 | */ | |
1da177e4 LT |
1183 | sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); |
1184 | /* Check hw IPv4/TCP checksum if supported */ | |
1185 | if (sc->rx_hw_checksum == ENABLE) { | |
1186 | if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) && | |
1187 | !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) { | |
1188 | sb->ip_summed = CHECKSUM_UNNECESSARY; | |
1189 | /* don't need to set sb->csum */ | |
1190 | } else { | |
1191 | sb->ip_summed = CHECKSUM_NONE; | |
1192 | } | |
1193 | } | |
693aa947 MM |
1194 | prefetch(sb->data); |
1195 | prefetch((const void *)(((char *)sb->data)+32)); | |
1196 | if (poll) | |
1197 | dropped = netif_receive_skb(sb); | |
1198 | else | |
1199 | dropped = netif_rx(sb); | |
1200 | ||
1201 | if (dropped == NET_RX_DROP) { | |
09f75cd7 | 1202 | dev->stats.rx_dropped++; |
693aa947 MM |
1203 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); |
1204 | goto done; | |
1205 | } | |
1206 | else { | |
09f75cd7 JG |
1207 | dev->stats.rx_bytes += len; |
1208 | dev->stats.rx_packets++; | |
693aa947 | 1209 | } |
1da177e4 LT |
1210 | } |
1211 | } else { | |
1212 | /* | |
1213 | * Packet was mangled somehow. Just drop it and | |
1214 | * put it back on the receive ring. | |
1215 | */ | |
09f75cd7 | 1216 | dev->stats.rx_errors++; |
789585e9 | 1217 | sbdma_add_rcvbuffer(sc, d, sb); |
1da177e4 | 1218 | } |
74b0247f RB |
1219 | |
1220 | ||
1221 | /* | |
1da177e4 LT |
1222 | * .. and advance to the next buffer. |
1223 | */ | |
74b0247f | 1224 | |
1da177e4 | 1225 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); |
693aa947 MM |
1226 | work_done++; |
1227 | } | |
1228 | if (!poll) { | |
1229 | work_to_do = 32; | |
1230 | goto again; /* collect fifo drop statistics again */ | |
1da177e4 | 1231 | } |
693aa947 MM |
1232 | done: |
1233 | return work_done; | |
1da177e4 LT |
1234 | } |
1235 | ||
1da177e4 LT |
1236 | /********************************************************************** |
1237 | * SBDMA_TX_PROCESS(sc,d) | |
74b0247f RB |
1238 | * |
1239 | * Process "completed" transmit buffers on the specified DMA channel. | |
1da177e4 LT |
1240 | * This is normally called within the interrupt service routine. |
1241 | * Note that this isn't really ideal for priority channels, since | |
74b0247f RB |
1242 | * it processes all of the packets on a given channel before |
1243 | * returning. | |
1da177e4 | 1244 | * |
74b0247f | 1245 | * Input parameters: |
1da177e4 | 1246 | * sc - softc structure |
693aa947 MM |
1247 | * d - DMA channel context |
1248 | * poll - 1: using polling (for NAPI) | |
74b0247f | 1249 | * |
1da177e4 LT |
1250 | * Return value: |
1251 | * nothing | |
1252 | ********************************************************************* */ | |
1253 | ||
73d73969 MR |
1254 | static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, |
1255 | int poll) | |
1da177e4 | 1256 | { |
09f75cd7 | 1257 | struct net_device *dev = sc->sbm_dev; |
1da177e4 LT |
1258 | int curidx; |
1259 | int hwidx; | |
73d73969 | 1260 | struct sbdmadscr *dsc; |
1da177e4 LT |
1261 | struct sk_buff *sb; |
1262 | unsigned long flags; | |
693aa947 | 1263 | int packets_handled = 0; |
1da177e4 LT |
1264 | |
1265 | spin_lock_irqsave(&(sc->sbm_lock), flags); | |
74b0247f | 1266 | |
693aa947 MM |
1267 | if (d->sbdma_remptr == d->sbdma_addptr) |
1268 | goto end_unlock; | |
1269 | ||
73d73969 MR |
1270 | hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - |
1271 | d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable); | |
693aa947 | 1272 | |
1da177e4 | 1273 | for (;;) { |
74b0247f | 1274 | /* |
1da177e4 LT |
1275 | * figure out where we are (as an index) and where |
1276 | * the hardware is (also as an index) | |
1277 | * | |
74b0247f | 1278 | * This could be done faster if (for example) the |
1da177e4 LT |
1279 | * descriptor table was page-aligned and contiguous in |
1280 | * both virtual and physical memory -- you could then | |
1281 | * just compare the low-order bits of the virtual address | |
1282 | * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) | |
1283 | */ | |
74b0247f | 1284 | |
1da177e4 | 1285 | curidx = d->sbdma_remptr - d->sbdma_dscrtable; |
1da177e4 LT |
1286 | |
1287 | /* | |
1288 | * If they're the same, that means we've processed all | |
1289 | * of the descriptors up to (but not including) the one that | |
1290 | * the hardware is working on right now. | |
1291 | */ | |
74b0247f | 1292 | |
1da177e4 LT |
1293 | if (curidx == hwidx) |
1294 | break; | |
74b0247f | 1295 | |
1da177e4 LT |
1296 | /* |
1297 | * Otherwise, get the packet's sk_buff ptr back | |
1298 | */ | |
74b0247f | 1299 | |
1da177e4 LT |
1300 | dsc = &(d->sbdma_dscrtable[curidx]); |
1301 | sb = d->sbdma_ctxtable[curidx]; | |
1302 | d->sbdma_ctxtable[curidx] = NULL; | |
74b0247f | 1303 | |
1da177e4 LT |
1304 | /* |
1305 | * Stats | |
1306 | */ | |
74b0247f | 1307 | |
09f75cd7 JG |
1308 | dev->stats.tx_bytes += sb->len; |
1309 | dev->stats.tx_packets++; | |
74b0247f | 1310 | |
1da177e4 LT |
1311 | /* |
1312 | * for transmits, we just free buffers. | |
1313 | */ | |
74b0247f | 1314 | |
1da177e4 | 1315 | dev_kfree_skb_irq(sb); |
74b0247f RB |
1316 | |
1317 | /* | |
1da177e4 LT |
1318 | * .. and advance to the next buffer. |
1319 | */ | |
1320 | ||
1321 | d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); | |
74b0247f | 1322 | |
693aa947 MM |
1323 | packets_handled++; |
1324 | ||
1da177e4 | 1325 | } |
74b0247f | 1326 | |
1da177e4 LT |
1327 | /* |
1328 | * Decide if we should wake up the protocol or not. | |
1329 | * Other drivers seem to do this when we reach a low | |
1330 | * watermark on the transmit queue. | |
1331 | */ | |
74b0247f | 1332 | |
693aa947 MM |
1333 | if (packets_handled) |
1334 | netif_wake_queue(d->sbdma_eth->sbm_dev); | |
74b0247f | 1335 | |
693aa947 | 1336 | end_unlock: |
1da177e4 | 1337 | spin_unlock_irqrestore(&(sc->sbm_lock), flags); |
74b0247f | 1338 | |
1da177e4 LT |
1339 | } |
1340 | ||
1341 | ||
1342 | ||
1343 | /********************************************************************** | |
1344 | * SBMAC_INITCTX(s) | |
74b0247f | 1345 | * |
1da177e4 LT |
1346 | * Initialize an Ethernet context structure - this is called |
1347 | * once per MAC on the 1250. Memory is allocated here, so don't | |
1348 | * call it again from inside the ioctl routines that bring the | |
1349 | * interface up/down | |
74b0247f RB |
1350 | * |
1351 | * Input parameters: | |
1da177e4 | 1352 | * s - sbmac context structure |
74b0247f | 1353 | * |
1da177e4 LT |
1354 | * Return value: |
1355 | * 0 | |
1356 | ********************************************************************* */ | |
1357 | ||
1358 | static int sbmac_initctx(struct sbmac_softc *s) | |
1359 | { | |
74b0247f RB |
1360 | |
1361 | /* | |
1362 | * figure out the addresses of some ports | |
1da177e4 | 1363 | */ |
74b0247f | 1364 | |
1da177e4 LT |
1365 | s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; |
1366 | s->sbm_maccfg = s->sbm_base + R_MAC_CFG; | |
1367 | s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; | |
1368 | s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG; | |
1369 | s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG; | |
1370 | s->sbm_isr = s->sbm_base + R_MAC_STATUS; | |
1371 | s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; | |
1372 | s->sbm_mdio = s->sbm_base + R_MAC_MDIO; | |
1373 | ||
1da177e4 LT |
1374 | /* |
1375 | * Initialize the DMA channels. Right now, only one per MAC is used | |
1376 | * Note: Only do this _once_, as it allocates memory from the kernel! | |
1377 | */ | |
74b0247f | 1378 | |
1da177e4 LT |
1379 | sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR); |
1380 | sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR); | |
74b0247f | 1381 | |
1da177e4 LT |
1382 | /* |
1383 | * initial state is OFF | |
1384 | */ | |
74b0247f | 1385 | |
1da177e4 | 1386 | s->sbm_state = sbmac_state_off; |
74b0247f | 1387 | |
1da177e4 LT |
1388 | return 0; |
1389 | } | |
1390 | ||
1391 | ||
73d73969 | 1392 | static void sbdma_uninitctx(struct sbmacdma *d) |
1da177e4 | 1393 | { |
693aa947 MM |
1394 | if (d->sbdma_dscrtable_unaligned) { |
1395 | kfree(d->sbdma_dscrtable_unaligned); | |
1396 | d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL; | |
1da177e4 | 1397 | } |
74b0247f | 1398 | |
1da177e4 LT |
1399 | if (d->sbdma_ctxtable) { |
1400 | kfree(d->sbdma_ctxtable); | |
1401 | d->sbdma_ctxtable = NULL; | |
1402 | } | |
1403 | } | |
1404 | ||
1405 | ||
1406 | static void sbmac_uninitctx(struct sbmac_softc *sc) | |
1407 | { | |
1408 | sbdma_uninitctx(&(sc->sbm_txdma)); | |
1409 | sbdma_uninitctx(&(sc->sbm_rxdma)); | |
1410 | } | |
1411 | ||
1412 | ||
1413 | /********************************************************************** | |
1414 | * SBMAC_CHANNEL_START(s) | |
74b0247f | 1415 | * |
1da177e4 | 1416 | * Start packet processing on this MAC. |
74b0247f RB |
1417 | * |
1418 | * Input parameters: | |
1da177e4 | 1419 | * s - sbmac structure |
74b0247f | 1420 | * |
1da177e4 LT |
1421 | * Return value: |
1422 | * nothing | |
1423 | ********************************************************************* */ | |
1424 | ||
1425 | static void sbmac_channel_start(struct sbmac_softc *s) | |
1426 | { | |
1427 | uint64_t reg; | |
73d73969 | 1428 | void __iomem *port; |
1da177e4 LT |
1429 | uint64_t cfg,fifo,framecfg; |
1430 | int idx, th_value; | |
74b0247f | 1431 | |
1da177e4 LT |
1432 | /* |
1433 | * Don't do this if running | |
1434 | */ | |
1435 | ||
1436 | if (s->sbm_state == sbmac_state_on) | |
1437 | return; | |
74b0247f | 1438 | |
1da177e4 LT |
1439 | /* |
1440 | * Bring the controller out of reset, but leave it off. | |
1441 | */ | |
74b0247f | 1442 | |
2039973a | 1443 | __raw_writeq(0, s->sbm_macenable); |
74b0247f | 1444 | |
1da177e4 LT |
1445 | /* |
1446 | * Ignore all received packets | |
1447 | */ | |
74b0247f | 1448 | |
2039973a | 1449 | __raw_writeq(0, s->sbm_rxfilter); |
74b0247f RB |
1450 | |
1451 | /* | |
1da177e4 LT |
1452 | * Calculate values for various control registers. |
1453 | */ | |
74b0247f | 1454 | |
1da177e4 | 1455 | cfg = M_MAC_RETRY_EN | |
74b0247f | 1456 | M_MAC_TX_HOLD_SOP_EN | |
1da177e4 LT |
1457 | V_MAC_TX_PAUSE_CNT_16K | |
1458 | M_MAC_AP_STAT_EN | | |
1459 | M_MAC_FAST_SYNC | | |
1460 | M_MAC_SS_EN | | |
1461 | 0; | |
74b0247f RB |
1462 | |
1463 | /* | |
1da177e4 LT |
1464 | * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars |
1465 | * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above | |
1466 | * Use a larger RD_THRSH for gigabit | |
1467 | */ | |
f90fdc3c | 1468 | if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) |
1da177e4 | 1469 | th_value = 28; |
f90fdc3c RB |
1470 | else |
1471 | th_value = 64; | |
1da177e4 LT |
1472 | |
1473 | fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ | |
1474 | ((s->sbm_speed == sbmac_speed_1000) | |
1475 | ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) | | |
1476 | V_MAC_TX_RL_THRSH(4) | | |
1477 | V_MAC_RX_PL_THRSH(4) | | |
1478 | V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ | |
1479 | V_MAC_RX_PL_THRSH(4) | | |
1480 | V_MAC_RX_RL_THRSH(8) | | |
1481 | 0; | |
1482 | ||
1483 | framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | | |
1484 | V_MAC_MAX_FRAMESZ_DEFAULT | | |
1485 | V_MAC_BACKOFF_SEL(1); | |
1486 | ||
1487 | /* | |
74b0247f | 1488 | * Clear out the hash address map |
1da177e4 | 1489 | */ |
74b0247f | 1490 | |
1da177e4 LT |
1491 | port = s->sbm_base + R_MAC_HASH_BASE; |
1492 | for (idx = 0; idx < MAC_HASH_COUNT; idx++) { | |
2039973a | 1493 | __raw_writeq(0, port); |
1da177e4 LT |
1494 | port += sizeof(uint64_t); |
1495 | } | |
74b0247f | 1496 | |
1da177e4 LT |
1497 | /* |
1498 | * Clear out the exact-match table | |
1499 | */ | |
74b0247f | 1500 | |
1da177e4 LT |
1501 | port = s->sbm_base + R_MAC_ADDR_BASE; |
1502 | for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { | |
2039973a | 1503 | __raw_writeq(0, port); |
1da177e4 LT |
1504 | port += sizeof(uint64_t); |
1505 | } | |
74b0247f | 1506 | |
1da177e4 LT |
1507 | /* |
1508 | * Clear out the DMA Channel mapping table registers | |
1509 | */ | |
74b0247f | 1510 | |
1da177e4 LT |
1511 | port = s->sbm_base + R_MAC_CHUP0_BASE; |
1512 | for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { | |
2039973a | 1513 | __raw_writeq(0, port); |
1da177e4 LT |
1514 | port += sizeof(uint64_t); |
1515 | } | |
1516 | ||
1517 | ||
1518 | port = s->sbm_base + R_MAC_CHLO0_BASE; | |
1519 | for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { | |
2039973a | 1520 | __raw_writeq(0, port); |
1da177e4 LT |
1521 | port += sizeof(uint64_t); |
1522 | } | |
74b0247f | 1523 | |
1da177e4 LT |
1524 | /* |
1525 | * Program the hardware address. It goes into the hardware-address | |
1526 | * register as well as the first filter register. | |
1527 | */ | |
74b0247f | 1528 | |
1da177e4 | 1529 | reg = sbmac_addr2reg(s->sbm_hwaddr); |
74b0247f | 1530 | |
1da177e4 | 1531 | port = s->sbm_base + R_MAC_ADDR_BASE; |
2039973a | 1532 | __raw_writeq(reg, port); |
1da177e4 LT |
1533 | port = s->sbm_base + R_MAC_ETHERNET_ADDR; |
1534 | ||
1535 | #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS | |
1536 | /* | |
1537 | * Pass1 SOCs do not receive packets addressed to the | |
1538 | * destination address in the R_MAC_ETHERNET_ADDR register. | |
1539 | * Set the value to zero. | |
1540 | */ | |
2039973a | 1541 | __raw_writeq(0, port); |
1da177e4 | 1542 | #else |
2039973a | 1543 | __raw_writeq(reg, port); |
1da177e4 | 1544 | #endif |
74b0247f | 1545 | |
1da177e4 LT |
1546 | /* |
1547 | * Set the receive filter for no packets, and write values | |
1548 | * to the various config registers | |
1549 | */ | |
74b0247f | 1550 | |
2039973a RB |
1551 | __raw_writeq(0, s->sbm_rxfilter); |
1552 | __raw_writeq(0, s->sbm_imr); | |
1553 | __raw_writeq(framecfg, s->sbm_framecfg); | |
1554 | __raw_writeq(fifo, s->sbm_fifocfg); | |
1555 | __raw_writeq(cfg, s->sbm_maccfg); | |
74b0247f | 1556 | |
1da177e4 LT |
1557 | /* |
1558 | * Initialize DMA channels (rings should be ok now) | |
1559 | */ | |
74b0247f | 1560 | |
1da177e4 LT |
1561 | sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); |
1562 | sbdma_channel_start(&(s->sbm_txdma), DMA_TX); | |
74b0247f | 1563 | |
1da177e4 LT |
1564 | /* |
1565 | * Configure the speed, duplex, and flow control | |
1566 | */ | |
1567 | ||
1568 | sbmac_set_speed(s,s->sbm_speed); | |
1569 | sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc); | |
74b0247f | 1570 | |
1da177e4 LT |
1571 | /* |
1572 | * Fill the receive ring | |
1573 | */ | |
74b0247f | 1574 | |
789585e9 | 1575 | sbdma_fillring(s, &(s->sbm_rxdma)); |
74b0247f RB |
1576 | |
1577 | /* | |
1da177e4 | 1578 | * Turn on the rest of the bits in the enable register |
74b0247f RB |
1579 | */ |
1580 | ||
f90fdc3c RB |
1581 | #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) |
1582 | __raw_writeq(M_MAC_RXDMA_EN0 | | |
1583 | M_MAC_TXDMA_EN0, s->sbm_macenable); | |
1584 | #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) | |
2039973a | 1585 | __raw_writeq(M_MAC_RXDMA_EN0 | |
1da177e4 LT |
1586 | M_MAC_TXDMA_EN0 | |
1587 | M_MAC_RX_ENABLE | | |
2039973a | 1588 | M_MAC_TX_ENABLE, s->sbm_macenable); |
f90fdc3c RB |
1589 | #else |
1590 | #error invalid SiByte MAC configuation | |
1591 | #endif | |
1da177e4 LT |
1592 | |
1593 | #ifdef CONFIG_SBMAC_COALESCE | |
2039973a RB |
1594 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | |
1595 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr); | |
1da177e4 | 1596 | #else |
2039973a RB |
1597 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | |
1598 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr); | |
1da177e4 | 1599 | #endif |
74b0247f RB |
1600 | |
1601 | /* | |
1602 | * Enable receiving unicasts and broadcasts | |
1da177e4 | 1603 | */ |
74b0247f | 1604 | |
2039973a | 1605 | __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter); |
74b0247f | 1606 | |
1da177e4 | 1607 | /* |
74b0247f | 1608 | * we're running now. |
1da177e4 | 1609 | */ |
74b0247f | 1610 | |
1da177e4 | 1611 | s->sbm_state = sbmac_state_on; |
74b0247f RB |
1612 | |
1613 | /* | |
1614 | * Program multicast addresses | |
1da177e4 | 1615 | */ |
74b0247f | 1616 | |
1da177e4 | 1617 | sbmac_setmulti(s); |
74b0247f RB |
1618 | |
1619 | /* | |
1620 | * If channel was in promiscuous mode before, turn that on | |
1da177e4 | 1621 | */ |
74b0247f | 1622 | |
1da177e4 LT |
1623 | if (s->sbm_devflags & IFF_PROMISC) { |
1624 | sbmac_promiscuous_mode(s,1); | |
1625 | } | |
74b0247f | 1626 | |
1da177e4 LT |
1627 | } |
1628 | ||
1629 | ||
1630 | /********************************************************************** | |
1631 | * SBMAC_CHANNEL_STOP(s) | |
74b0247f | 1632 | * |
1da177e4 | 1633 | * Stop packet processing on this MAC. |
74b0247f RB |
1634 | * |
1635 | * Input parameters: | |
1da177e4 | 1636 | * s - sbmac structure |
74b0247f | 1637 | * |
1da177e4 LT |
1638 | * Return value: |
1639 | * nothing | |
1640 | ********************************************************************* */ | |
1641 | ||
1642 | static void sbmac_channel_stop(struct sbmac_softc *s) | |
1643 | { | |
1644 | /* don't do this if already stopped */ | |
74b0247f | 1645 | |
1da177e4 LT |
1646 | if (s->sbm_state == sbmac_state_off) |
1647 | return; | |
74b0247f | 1648 | |
1da177e4 | 1649 | /* don't accept any packets, disable all interrupts */ |
74b0247f | 1650 | |
2039973a RB |
1651 | __raw_writeq(0, s->sbm_rxfilter); |
1652 | __raw_writeq(0, s->sbm_imr); | |
74b0247f | 1653 | |
1da177e4 | 1654 | /* Turn off ticker */ |
74b0247f | 1655 | |
1da177e4 | 1656 | /* XXX */ |
74b0247f | 1657 | |
1da177e4 | 1658 | /* turn off receiver and transmitter */ |
74b0247f | 1659 | |
2039973a | 1660 | __raw_writeq(0, s->sbm_macenable); |
74b0247f | 1661 | |
1da177e4 | 1662 | /* We're stopped now. */ |
74b0247f | 1663 | |
1da177e4 | 1664 | s->sbm_state = sbmac_state_off; |
74b0247f | 1665 | |
1da177e4 LT |
1666 | /* |
1667 | * Stop DMA channels (rings should be ok now) | |
1668 | */ | |
74b0247f | 1669 | |
1da177e4 LT |
1670 | sbdma_channel_stop(&(s->sbm_rxdma)); |
1671 | sbdma_channel_stop(&(s->sbm_txdma)); | |
74b0247f | 1672 | |
1da177e4 | 1673 | /* Empty the receive and transmit rings */ |
74b0247f | 1674 | |
1da177e4 LT |
1675 | sbdma_emptyring(&(s->sbm_rxdma)); |
1676 | sbdma_emptyring(&(s->sbm_txdma)); | |
74b0247f | 1677 | |
1da177e4 LT |
1678 | } |
1679 | ||
1680 | /********************************************************************** | |
1681 | * SBMAC_SET_CHANNEL_STATE(state) | |
74b0247f | 1682 | * |
1da177e4 | 1683 | * Set the channel's state ON or OFF |
74b0247f RB |
1684 | * |
1685 | * Input parameters: | |
1da177e4 | 1686 | * state - new state |
74b0247f | 1687 | * |
1da177e4 LT |
1688 | * Return value: |
1689 | * old state | |
1690 | ********************************************************************* */ | |
73d73969 MR |
1691 | static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc, |
1692 | enum sbmac_state state) | |
1da177e4 | 1693 | { |
73d73969 | 1694 | enum sbmac_state oldstate = sc->sbm_state; |
74b0247f | 1695 | |
1da177e4 LT |
1696 | /* |
1697 | * If same as previous state, return | |
1698 | */ | |
74b0247f | 1699 | |
1da177e4 LT |
1700 | if (state == oldstate) { |
1701 | return oldstate; | |
1702 | } | |
74b0247f | 1703 | |
1da177e4 | 1704 | /* |
74b0247f | 1705 | * If new state is ON, turn channel on |
1da177e4 | 1706 | */ |
74b0247f | 1707 | |
1da177e4 LT |
1708 | if (state == sbmac_state_on) { |
1709 | sbmac_channel_start(sc); | |
1710 | } | |
1711 | else { | |
1712 | sbmac_channel_stop(sc); | |
1713 | } | |
74b0247f | 1714 | |
1da177e4 LT |
1715 | /* |
1716 | * Return previous state | |
1717 | */ | |
74b0247f | 1718 | |
1da177e4 LT |
1719 | return oldstate; |
1720 | } | |
1721 | ||
1722 | ||
1723 | /********************************************************************** | |
1724 | * SBMAC_PROMISCUOUS_MODE(sc,onoff) | |
74b0247f | 1725 | * |
1da177e4 | 1726 | * Turn on or off promiscuous mode |
74b0247f RB |
1727 | * |
1728 | * Input parameters: | |
1da177e4 LT |
1729 | * sc - softc |
1730 | * onoff - 1 to turn on, 0 to turn off | |
74b0247f | 1731 | * |
1da177e4 LT |
1732 | * Return value: |
1733 | * nothing | |
1734 | ********************************************************************* */ | |
1735 | ||
1736 | static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff) | |
1737 | { | |
1738 | uint64_t reg; | |
74b0247f | 1739 | |
1da177e4 LT |
1740 | if (sc->sbm_state != sbmac_state_on) |
1741 | return; | |
74b0247f | 1742 | |
1da177e4 | 1743 | if (onoff) { |
2039973a | 1744 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1745 | reg |= M_MAC_ALLPKT_EN; |
2039973a | 1746 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 1747 | } |
1da177e4 | 1748 | else { |
2039973a | 1749 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1750 | reg &= ~M_MAC_ALLPKT_EN; |
2039973a | 1751 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
1752 | } |
1753 | } | |
1754 | ||
1755 | /********************************************************************** | |
1756 | * SBMAC_SETIPHDR_OFFSET(sc,onoff) | |
74b0247f | 1757 | * |
1da177e4 | 1758 | * Set the iphdr offset as 15 assuming ethernet encapsulation |
74b0247f RB |
1759 | * |
1760 | * Input parameters: | |
1da177e4 | 1761 | * sc - softc |
74b0247f | 1762 | * |
1da177e4 LT |
1763 | * Return value: |
1764 | * nothing | |
1765 | ********************************************************************* */ | |
1766 | ||
1767 | static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) | |
1768 | { | |
1769 | uint64_t reg; | |
74b0247f | 1770 | |
1da177e4 | 1771 | /* Hard code the off set to 15 for now */ |
2039973a | 1772 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 1773 | reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); |
2039973a | 1774 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 1775 | |
f90fdc3c RB |
1776 | /* BCM1250 pass1 didn't have hardware checksum. Everything |
1777 | later does. */ | |
1778 | if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) { | |
1da177e4 | 1779 | sc->rx_hw_checksum = DISABLE; |
f90fdc3c RB |
1780 | } else { |
1781 | sc->rx_hw_checksum = ENABLE; | |
1da177e4 LT |
1782 | } |
1783 | } | |
1784 | ||
1785 | ||
1786 | /********************************************************************** | |
1787 | * SBMAC_ADDR2REG(ptr) | |
74b0247f | 1788 | * |
1da177e4 LT |
1789 | * Convert six bytes into the 64-bit register value that |
1790 | * we typically write into the SBMAC's address/mcast registers | |
74b0247f RB |
1791 | * |
1792 | * Input parameters: | |
1da177e4 | 1793 | * ptr - pointer to 6 bytes |
74b0247f | 1794 | * |
1da177e4 LT |
1795 | * Return value: |
1796 | * register value | |
1797 | ********************************************************************* */ | |
1798 | ||
1799 | static uint64_t sbmac_addr2reg(unsigned char *ptr) | |
1800 | { | |
1801 | uint64_t reg = 0; | |
74b0247f | 1802 | |
1da177e4 | 1803 | ptr += 6; |
74b0247f RB |
1804 | |
1805 | reg |= (uint64_t) *(--ptr); | |
1da177e4 | 1806 | reg <<= 8; |
74b0247f | 1807 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1808 | reg <<= 8; |
74b0247f | 1809 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1810 | reg <<= 8; |
74b0247f | 1811 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1812 | reg <<= 8; |
74b0247f | 1813 | reg |= (uint64_t) *(--ptr); |
1da177e4 | 1814 | reg <<= 8; |
74b0247f RB |
1815 | reg |= (uint64_t) *(--ptr); |
1816 | ||
1da177e4 LT |
1817 | return reg; |
1818 | } | |
1819 | ||
1820 | ||
1821 | /********************************************************************** | |
1822 | * SBMAC_SET_SPEED(s,speed) | |
74b0247f | 1823 | * |
1da177e4 LT |
1824 | * Configure LAN speed for the specified MAC. |
1825 | * Warning: must be called when MAC is off! | |
74b0247f RB |
1826 | * |
1827 | * Input parameters: | |
1da177e4 | 1828 | * s - sbmac structure |
73d73969 | 1829 | * speed - speed to set MAC to (see enum sbmac_speed) |
74b0247f | 1830 | * |
1da177e4 LT |
1831 | * Return value: |
1832 | * 1 if successful | |
1833 | * 0 indicates invalid parameters | |
1834 | ********************************************************************* */ | |
1835 | ||
73d73969 | 1836 | static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed) |
1da177e4 LT |
1837 | { |
1838 | uint64_t cfg; | |
1839 | uint64_t framecfg; | |
1840 | ||
1841 | /* | |
1842 | * Save new current values | |
1843 | */ | |
74b0247f | 1844 | |
1da177e4 | 1845 | s->sbm_speed = speed; |
74b0247f | 1846 | |
1da177e4 LT |
1847 | if (s->sbm_state == sbmac_state_on) |
1848 | return 0; /* save for next restart */ | |
1849 | ||
1850 | /* | |
74b0247f | 1851 | * Read current register values |
1da177e4 | 1852 | */ |
74b0247f | 1853 | |
2039973a RB |
1854 | cfg = __raw_readq(s->sbm_maccfg); |
1855 | framecfg = __raw_readq(s->sbm_framecfg); | |
74b0247f | 1856 | |
1da177e4 LT |
1857 | /* |
1858 | * Mask out the stuff we want to change | |
1859 | */ | |
74b0247f | 1860 | |
1da177e4 LT |
1861 | cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); |
1862 | framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | | |
1863 | M_MAC_SLOT_SIZE); | |
74b0247f | 1864 | |
1da177e4 LT |
1865 | /* |
1866 | * Now add in the new bits | |
1867 | */ | |
74b0247f | 1868 | |
1da177e4 LT |
1869 | switch (speed) { |
1870 | case sbmac_speed_10: | |
1871 | framecfg |= V_MAC_IFG_RX_10 | | |
1872 | V_MAC_IFG_TX_10 | | |
1873 | K_MAC_IFG_THRSH_10 | | |
1874 | V_MAC_SLOT_SIZE_10; | |
1875 | cfg |= V_MAC_SPEED_SEL_10MBPS; | |
1876 | break; | |
74b0247f | 1877 | |
1da177e4 LT |
1878 | case sbmac_speed_100: |
1879 | framecfg |= V_MAC_IFG_RX_100 | | |
1880 | V_MAC_IFG_TX_100 | | |
1881 | V_MAC_IFG_THRSH_100 | | |
1882 | V_MAC_SLOT_SIZE_100; | |
1883 | cfg |= V_MAC_SPEED_SEL_100MBPS ; | |
1884 | break; | |
74b0247f | 1885 | |
1da177e4 LT |
1886 | case sbmac_speed_1000: |
1887 | framecfg |= V_MAC_IFG_RX_1000 | | |
1888 | V_MAC_IFG_TX_1000 | | |
1889 | V_MAC_IFG_THRSH_1000 | | |
1890 | V_MAC_SLOT_SIZE_1000; | |
1891 | cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; | |
1892 | break; | |
74b0247f | 1893 | |
1da177e4 LT |
1894 | default: |
1895 | return 0; | |
1896 | } | |
74b0247f | 1897 | |
1da177e4 | 1898 | /* |
74b0247f | 1899 | * Send the bits back to the hardware |
1da177e4 | 1900 | */ |
74b0247f | 1901 | |
2039973a RB |
1902 | __raw_writeq(framecfg, s->sbm_framecfg); |
1903 | __raw_writeq(cfg, s->sbm_maccfg); | |
74b0247f | 1904 | |
1da177e4 LT |
1905 | return 1; |
1906 | } | |
1907 | ||
1908 | /********************************************************************** | |
1909 | * SBMAC_SET_DUPLEX(s,duplex,fc) | |
74b0247f | 1910 | * |
1da177e4 LT |
1911 | * Set Ethernet duplex and flow control options for this MAC |
1912 | * Warning: must be called when MAC is off! | |
74b0247f RB |
1913 | * |
1914 | * Input parameters: | |
1da177e4 | 1915 | * s - sbmac structure |
73d73969 MR |
1916 | * duplex - duplex setting (see enum sbmac_duplex) |
1917 | * fc - flow control setting (see enum sbmac_fc) | |
74b0247f | 1918 | * |
1da177e4 LT |
1919 | * Return value: |
1920 | * 1 if ok | |
1921 | * 0 if an invalid parameter combination was specified | |
1922 | ********************************************************************* */ | |
1923 | ||
73d73969 MR |
1924 | static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, |
1925 | enum sbmac_fc fc) | |
1da177e4 LT |
1926 | { |
1927 | uint64_t cfg; | |
74b0247f | 1928 | |
1da177e4 LT |
1929 | /* |
1930 | * Save new current values | |
1931 | */ | |
74b0247f | 1932 | |
1da177e4 LT |
1933 | s->sbm_duplex = duplex; |
1934 | s->sbm_fc = fc; | |
74b0247f | 1935 | |
1da177e4 LT |
1936 | if (s->sbm_state == sbmac_state_on) |
1937 | return 0; /* save for next restart */ | |
74b0247f | 1938 | |
1da177e4 | 1939 | /* |
74b0247f | 1940 | * Read current register values |
1da177e4 | 1941 | */ |
74b0247f | 1942 | |
2039973a | 1943 | cfg = __raw_readq(s->sbm_maccfg); |
74b0247f | 1944 | |
1da177e4 LT |
1945 | /* |
1946 | * Mask off the stuff we're about to change | |
1947 | */ | |
74b0247f | 1948 | |
1da177e4 | 1949 | cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); |
74b0247f RB |
1950 | |
1951 | ||
1da177e4 LT |
1952 | switch (duplex) { |
1953 | case sbmac_duplex_half: | |
1954 | switch (fc) { | |
1955 | case sbmac_fc_disabled: | |
1956 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; | |
1957 | break; | |
74b0247f | 1958 | |
1da177e4 LT |
1959 | case sbmac_fc_collision: |
1960 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; | |
1961 | break; | |
74b0247f | 1962 | |
1da177e4 LT |
1963 | case sbmac_fc_carrier: |
1964 | cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; | |
1965 | break; | |
74b0247f | 1966 | |
1da177e4 LT |
1967 | case sbmac_fc_frame: /* not valid in half duplex */ |
1968 | default: /* invalid selection */ | |
1969 | return 0; | |
1970 | } | |
1971 | break; | |
74b0247f | 1972 | |
1da177e4 LT |
1973 | case sbmac_duplex_full: |
1974 | switch (fc) { | |
1975 | case sbmac_fc_disabled: | |
1976 | cfg |= V_MAC_FC_CMD_DISABLED; | |
1977 | break; | |
74b0247f | 1978 | |
1da177e4 LT |
1979 | case sbmac_fc_frame: |
1980 | cfg |= V_MAC_FC_CMD_ENABLED; | |
1981 | break; | |
74b0247f | 1982 | |
1da177e4 LT |
1983 | case sbmac_fc_collision: /* not valid in full duplex */ |
1984 | case sbmac_fc_carrier: /* not valid in full duplex */ | |
1da177e4 LT |
1985 | default: |
1986 | return 0; | |
1987 | } | |
1988 | break; | |
f5279ffd MR |
1989 | default: |
1990 | return 0; | |
1da177e4 | 1991 | } |
74b0247f | 1992 | |
1da177e4 | 1993 | /* |
74b0247f | 1994 | * Send the bits back to the hardware |
1da177e4 | 1995 | */ |
74b0247f | 1996 | |
2039973a | 1997 | __raw_writeq(cfg, s->sbm_maccfg); |
74b0247f | 1998 | |
1da177e4 LT |
1999 | return 1; |
2000 | } | |
2001 | ||
2002 | ||
2003 | ||
2004 | ||
2005 | /********************************************************************** | |
2006 | * SBMAC_INTR() | |
74b0247f | 2007 | * |
1da177e4 | 2008 | * Interrupt handler for MAC interrupts |
74b0247f RB |
2009 | * |
2010 | * Input parameters: | |
1da177e4 | 2011 | * MAC structure |
74b0247f | 2012 | * |
1da177e4 LT |
2013 | * Return value: |
2014 | * nothing | |
2015 | ********************************************************************* */ | |
7d12e780 | 2016 | static irqreturn_t sbmac_intr(int irq,void *dev_instance) |
1da177e4 LT |
2017 | { |
2018 | struct net_device *dev = (struct net_device *) dev_instance; | |
2019 | struct sbmac_softc *sc = netdev_priv(dev); | |
2020 | uint64_t isr; | |
2021 | int handled = 0; | |
2022 | ||
693aa947 MM |
2023 | /* |
2024 | * Read the ISR (this clears the bits in the real | |
2025 | * register, except for counter addr) | |
2026 | */ | |
74b0247f | 2027 | |
693aa947 | 2028 | isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; |
1da177e4 | 2029 | |
693aa947 MM |
2030 | if (isr == 0) |
2031 | return IRQ_RETVAL(0); | |
2032 | handled = 1; | |
74b0247f | 2033 | |
693aa947 MM |
2034 | /* |
2035 | * Transmits on channel 0 | |
2036 | */ | |
74b0247f | 2037 | |
bea3348e | 2038 | if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) |
693aa947 | 2039 | sbdma_tx_process(sc,&(sc->sbm_txdma), 0); |
74b0247f | 2040 | |
693aa947 | 2041 | if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { |
bea3348e | 2042 | if (netif_rx_schedule_prep(dev, &sc->napi)) { |
693aa947 | 2043 | __raw_writeq(0, sc->sbm_imr); |
bea3348e | 2044 | __netif_rx_schedule(dev, &sc->napi); |
693aa947 MM |
2045 | /* Depend on the exit from poll to reenable intr */ |
2046 | } | |
2047 | else { | |
2048 | /* may leave some packets behind */ | |
2049 | sbdma_rx_process(sc,&(sc->sbm_rxdma), | |
2050 | SBMAC_MAX_RXDESCR * 2, 0); | |
1da177e4 LT |
2051 | } |
2052 | } | |
2053 | return IRQ_RETVAL(handled); | |
2054 | } | |
2055 | ||
1da177e4 LT |
2056 | /********************************************************************** |
2057 | * SBMAC_START_TX(skb,dev) | |
74b0247f RB |
2058 | * |
2059 | * Start output on the specified interface. Basically, we | |
1da177e4 LT |
2060 | * queue as many buffers as we can until the ring fills up, or |
2061 | * we run off the end of the queue, whichever comes first. | |
74b0247f RB |
2062 | * |
2063 | * Input parameters: | |
2064 | * | |
2065 | * | |
1da177e4 LT |
2066 | * Return value: |
2067 | * nothing | |
2068 | ********************************************************************* */ | |
2069 | static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev) | |
2070 | { | |
2071 | struct sbmac_softc *sc = netdev_priv(dev); | |
be61ea52 | 2072 | unsigned long flags; |
74b0247f | 2073 | |
1da177e4 | 2074 | /* lock eth irq */ |
be61ea52 | 2075 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f | 2076 | |
1da177e4 | 2077 | /* |
74b0247f | 2078 | * Put the buffer on the transmit ring. If we |
1da177e4 LT |
2079 | * don't have room, stop the queue. |
2080 | */ | |
74b0247f | 2081 | |
1da177e4 LT |
2082 | if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { |
2083 | /* XXX save skb that we could not send */ | |
2084 | netif_stop_queue(dev); | |
be61ea52 | 2085 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 LT |
2086 | |
2087 | return 1; | |
2088 | } | |
74b0247f | 2089 | |
1da177e4 | 2090 | dev->trans_start = jiffies; |
74b0247f | 2091 | |
be61ea52 | 2092 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
74b0247f | 2093 | |
1da177e4 LT |
2094 | return 0; |
2095 | } | |
2096 | ||
2097 | /********************************************************************** | |
2098 | * SBMAC_SETMULTI(sc) | |
74b0247f | 2099 | * |
1da177e4 LT |
2100 | * Reprogram the multicast table into the hardware, given |
2101 | * the list of multicasts associated with the interface | |
2102 | * structure. | |
74b0247f RB |
2103 | * |
2104 | * Input parameters: | |
1da177e4 | 2105 | * sc - softc |
74b0247f | 2106 | * |
1da177e4 LT |
2107 | * Return value: |
2108 | * nothing | |
2109 | ********************************************************************* */ | |
2110 | ||
2111 | static void sbmac_setmulti(struct sbmac_softc *sc) | |
2112 | { | |
2113 | uint64_t reg; | |
73d73969 | 2114 | void __iomem *port; |
1da177e4 LT |
2115 | int idx; |
2116 | struct dev_mc_list *mclist; | |
2117 | struct net_device *dev = sc->sbm_dev; | |
74b0247f RB |
2118 | |
2119 | /* | |
1da177e4 LT |
2120 | * Clear out entire multicast table. We do this by nuking |
2121 | * the entire hash table and all the direct matches except | |
74b0247f | 2122 | * the first one, which is used for our station address |
1da177e4 | 2123 | */ |
74b0247f | 2124 | |
1da177e4 LT |
2125 | for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { |
2126 | port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); | |
2039973a | 2127 | __raw_writeq(0, port); |
1da177e4 | 2128 | } |
74b0247f | 2129 | |
1da177e4 LT |
2130 | for (idx = 0; idx < MAC_HASH_COUNT; idx++) { |
2131 | port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); | |
2039973a | 2132 | __raw_writeq(0, port); |
1da177e4 | 2133 | } |
74b0247f | 2134 | |
1da177e4 LT |
2135 | /* |
2136 | * Clear the filter to say we don't want any multicasts. | |
2137 | */ | |
74b0247f | 2138 | |
2039973a | 2139 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2140 | reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); |
2039973a | 2141 | __raw_writeq(reg, sc->sbm_rxfilter); |
74b0247f | 2142 | |
1da177e4 | 2143 | if (dev->flags & IFF_ALLMULTI) { |
74b0247f RB |
2144 | /* |
2145 | * Enable ALL multicasts. Do this by inverting the | |
2146 | * multicast enable bit. | |
1da177e4 | 2147 | */ |
2039973a | 2148 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2149 | reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); |
2039973a | 2150 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
2151 | return; |
2152 | } | |
1da177e4 | 2153 | |
74b0247f RB |
2154 | |
2155 | /* | |
1da177e4 LT |
2156 | * Progam new multicast entries. For now, only use the |
2157 | * perfect filter. In the future we'll need to use the | |
2158 | * hash filter if the perfect filter overflows | |
2159 | */ | |
74b0247f | 2160 | |
1da177e4 LT |
2161 | /* XXX only using perfect filter for now, need to use hash |
2162 | * XXX if the table overflows */ | |
74b0247f | 2163 | |
1da177e4 LT |
2164 | idx = 1; /* skip station address */ |
2165 | mclist = dev->mc_list; | |
2166 | while (mclist && (idx < MAC_ADDR_COUNT)) { | |
2167 | reg = sbmac_addr2reg(mclist->dmi_addr); | |
2168 | port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); | |
2039973a | 2169 | __raw_writeq(reg, port); |
1da177e4 LT |
2170 | idx++; |
2171 | mclist = mclist->next; | |
2172 | } | |
74b0247f RB |
2173 | |
2174 | /* | |
1da177e4 | 2175 | * Enable the "accept multicast bits" if we programmed at least one |
74b0247f | 2176 | * multicast. |
1da177e4 | 2177 | */ |
74b0247f | 2178 | |
1da177e4 | 2179 | if (idx > 1) { |
2039973a | 2180 | reg = __raw_readq(sc->sbm_rxfilter); |
1da177e4 | 2181 | reg |= M_MAC_MCAST_EN; |
2039973a | 2182 | __raw_writeq(reg, sc->sbm_rxfilter); |
1da177e4 LT |
2183 | } |
2184 | } | |
2185 | ||
f90fdc3c | 2186 | #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR) |
1da177e4 LT |
2187 | /********************************************************************** |
2188 | * SBMAC_PARSE_XDIGIT(str) | |
74b0247f | 2189 | * |
1da177e4 | 2190 | * Parse a hex digit, returning its value |
74b0247f RB |
2191 | * |
2192 | * Input parameters: | |
1da177e4 | 2193 | * str - character |
74b0247f | 2194 | * |
1da177e4 LT |
2195 | * Return value: |
2196 | * hex value, or -1 if invalid | |
2197 | ********************************************************************* */ | |
2198 | ||
2199 | static int sbmac_parse_xdigit(char str) | |
2200 | { | |
2201 | int digit; | |
74b0247f | 2202 | |
1da177e4 LT |
2203 | if ((str >= '0') && (str <= '9')) |
2204 | digit = str - '0'; | |
2205 | else if ((str >= 'a') && (str <= 'f')) | |
2206 | digit = str - 'a' + 10; | |
2207 | else if ((str >= 'A') && (str <= 'F')) | |
2208 | digit = str - 'A' + 10; | |
2209 | else | |
2210 | return -1; | |
74b0247f | 2211 | |
1da177e4 LT |
2212 | return digit; |
2213 | } | |
2214 | ||
2215 | /********************************************************************** | |
2216 | * SBMAC_PARSE_HWADDR(str,hwaddr) | |
74b0247f | 2217 | * |
1da177e4 LT |
2218 | * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte |
2219 | * Ethernet address. | |
74b0247f RB |
2220 | * |
2221 | * Input parameters: | |
1da177e4 LT |
2222 | * str - string |
2223 | * hwaddr - pointer to hardware address | |
74b0247f | 2224 | * |
1da177e4 LT |
2225 | * Return value: |
2226 | * 0 if ok, else -1 | |
2227 | ********************************************************************* */ | |
2228 | ||
2229 | static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr) | |
2230 | { | |
2231 | int digit1,digit2; | |
2232 | int idx = 6; | |
74b0247f | 2233 | |
1da177e4 LT |
2234 | while (*str && (idx > 0)) { |
2235 | digit1 = sbmac_parse_xdigit(*str); | |
2236 | if (digit1 < 0) | |
2237 | return -1; | |
2238 | str++; | |
2239 | if (!*str) | |
2240 | return -1; | |
74b0247f | 2241 | |
1da177e4 LT |
2242 | if ((*str == ':') || (*str == '-')) { |
2243 | digit2 = digit1; | |
2244 | digit1 = 0; | |
2245 | } | |
2246 | else { | |
2247 | digit2 = sbmac_parse_xdigit(*str); | |
2248 | if (digit2 < 0) | |
2249 | return -1; | |
2250 | str++; | |
2251 | } | |
74b0247f | 2252 | |
1da177e4 LT |
2253 | *hwaddr++ = (digit1 << 4) | digit2; |
2254 | idx--; | |
74b0247f | 2255 | |
1da177e4 LT |
2256 | if (*str == '-') |
2257 | str++; | |
2258 | if (*str == ':') | |
2259 | str++; | |
2260 | } | |
2261 | return 0; | |
2262 | } | |
2263 | #endif | |
2264 | ||
2265 | static int sb1250_change_mtu(struct net_device *_dev, int new_mtu) | |
2266 | { | |
2267 | if (new_mtu > ENET_PACKET_SIZE) | |
2268 | return -EINVAL; | |
2269 | _dev->mtu = new_mtu; | |
f5279ffd | 2270 | pr_info("changing the mtu to %d\n", new_mtu); |
1da177e4 LT |
2271 | return 0; |
2272 | } | |
2273 | ||
2274 | /********************************************************************** | |
2275 | * SBMAC_INIT(dev) | |
74b0247f | 2276 | * |
1da177e4 | 2277 | * Attach routine - init hardware and hook ourselves into linux |
74b0247f RB |
2278 | * |
2279 | * Input parameters: | |
1da177e4 | 2280 | * dev - net_device structure |
74b0247f | 2281 | * |
1da177e4 LT |
2282 | * Return value: |
2283 | * status | |
2284 | ********************************************************************* */ | |
2285 | ||
f5279ffd | 2286 | static int sbmac_init(struct platform_device *pldev, long long base) |
1da177e4 | 2287 | { |
f5279ffd MR |
2288 | struct net_device *dev = pldev->dev.driver_data; |
2289 | int idx = pldev->id; | |
2290 | struct sbmac_softc *sc = netdev_priv(dev); | |
1da177e4 LT |
2291 | unsigned char *eaddr; |
2292 | uint64_t ea_reg; | |
2293 | int i; | |
2294 | int err; | |
0795af57 | 2295 | DECLARE_MAC_BUF(mac); |
74b0247f | 2296 | |
1da177e4 LT |
2297 | sc->sbm_dev = dev; |
2298 | sc->sbe_idx = idx; | |
74b0247f | 2299 | |
1da177e4 | 2300 | eaddr = sc->sbm_hwaddr; |
74b0247f RB |
2301 | |
2302 | /* | |
1da177e4 LT |
2303 | * Read the ethernet address. The firwmare left this programmed |
2304 | * for us in the ethernet address register for each mac. | |
2305 | */ | |
74b0247f | 2306 | |
2039973a RB |
2307 | ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR); |
2308 | __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR); | |
1da177e4 LT |
2309 | for (i = 0; i < 6; i++) { |
2310 | eaddr[i] = (uint8_t) (ea_reg & 0xFF); | |
2311 | ea_reg >>= 8; | |
2312 | } | |
74b0247f | 2313 | |
1da177e4 LT |
2314 | for (i = 0; i < 6; i++) { |
2315 | dev->dev_addr[i] = eaddr[i]; | |
2316 | } | |
74b0247f | 2317 | |
74b0247f | 2318 | /* |
1da177e4 LT |
2319 | * Initialize context (get pointers to registers and stuff), then |
2320 | * allocate the memory for the descriptor tables. | |
2321 | */ | |
74b0247f | 2322 | |
1da177e4 | 2323 | sbmac_initctx(sc); |
74b0247f | 2324 | |
1da177e4 LT |
2325 | /* |
2326 | * Set up Linux device callins | |
2327 | */ | |
74b0247f | 2328 | |
1da177e4 | 2329 | spin_lock_init(&(sc->sbm_lock)); |
74b0247f | 2330 | |
1da177e4 LT |
2331 | dev->open = sbmac_open; |
2332 | dev->hard_start_xmit = sbmac_start_tx; | |
2333 | dev->stop = sbmac_close; | |
1da177e4 LT |
2334 | dev->set_multicast_list = sbmac_set_rx_mode; |
2335 | dev->do_ioctl = sbmac_mii_ioctl; | |
2336 | dev->tx_timeout = sbmac_tx_timeout; | |
2337 | dev->watchdog_timeo = TX_TIMEOUT; | |
bea3348e SH |
2338 | |
2339 | netif_napi_add(dev, &sc->napi, sbmac_poll, 16); | |
1da177e4 LT |
2340 | |
2341 | dev->change_mtu = sb1250_change_mtu; | |
d6830018 DS |
2342 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2343 | dev->poll_controller = sbmac_netpoll; | |
2344 | #endif | |
1da177e4 | 2345 | |
f5279ffd MR |
2346 | dev->irq = UNIT_INT(idx); |
2347 | ||
1da177e4 LT |
2348 | /* This is needed for PASS2 for Rx H/W checksum feature */ |
2349 | sbmac_set_iphdr_offset(sc); | |
2350 | ||
298cf9be LB |
2351 | sc->mii_bus = mdiobus_alloc(); |
2352 | if (sc->mii_bus == NULL) { | |
2353 | sbmac_uninitctx(sc); | |
2354 | return -ENOMEM; | |
2355 | } | |
2356 | ||
1da177e4 | 2357 | err = register_netdev(dev); |
f5279ffd MR |
2358 | if (err) { |
2359 | printk(KERN_ERR "%s.%d: unable to register netdev\n", | |
2360 | sbmac_string, idx); | |
298cf9be | 2361 | mdiobus_free(sc->mii_bus); |
f5279ffd MR |
2362 | sbmac_uninitctx(sc); |
2363 | return err; | |
1da177e4 LT |
2364 | } |
2365 | ||
f5279ffd MR |
2366 | pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name); |
2367 | ||
2368 | if (sc->rx_hw_checksum == ENABLE) | |
2369 | pr_info("%s: enabling TCP rcv checksum\n", dev->name); | |
2370 | ||
1da177e4 LT |
2371 | /* |
2372 | * Display Ethernet address (this is called during the config | |
2373 | * process so we need to finish off the config message that | |
2374 | * was being displayed) | |
2375 | */ | |
f5279ffd MR |
2376 | pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %s\n", |
2377 | dev->name, base, print_mac(mac, eaddr)); | |
1da177e4 | 2378 | |
298cf9be LB |
2379 | sc->mii_bus->name = sbmac_mdio_string; |
2380 | snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%x", idx); | |
2381 | sc->mii_bus->priv = sc; | |
2382 | sc->mii_bus->read = sbmac_mii_read; | |
2383 | sc->mii_bus->write = sbmac_mii_write; | |
2384 | sc->mii_bus->irq = sc->phy_irq; | |
f5279ffd | 2385 | for (i = 0; i < PHY_MAX_ADDR; ++i) |
298cf9be | 2386 | sc->mii_bus->irq[i] = SBMAC_PHY_INT; |
1da177e4 | 2387 | |
298cf9be LB |
2388 | sc->mii_bus->parent = &pldev->dev; |
2389 | dev_set_drvdata(&pldev->dev, sc->mii_bus); | |
1da177e4 | 2390 | |
f5279ffd | 2391 | return 0; |
1da177e4 LT |
2392 | } |
2393 | ||
2394 | ||
2395 | static int sbmac_open(struct net_device *dev) | |
2396 | { | |
2397 | struct sbmac_softc *sc = netdev_priv(dev); | |
f5279ffd | 2398 | int err; |
74b0247f | 2399 | |
f5279ffd MR |
2400 | if (debug > 1) |
2401 | pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq); | |
74b0247f RB |
2402 | |
2403 | /* | |
1da177e4 LT |
2404 | * map/route interrupt (clear status first, in case something |
2405 | * weird is pending; we haven't initialized the mac registers | |
2406 | * yet) | |
2407 | */ | |
2408 | ||
2039973a | 2409 | __raw_readq(sc->sbm_isr); |
f5279ffd MR |
2410 | err = request_irq(dev->irq, &sbmac_intr, IRQF_SHARED, dev->name, dev); |
2411 | if (err) { | |
2412 | printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, | |
2413 | dev->irq); | |
2414 | goto out_err; | |
2415 | } | |
1da177e4 | 2416 | |
59b81827 | 2417 | /* |
f5279ffd | 2418 | * Probe PHY address |
59b81827 | 2419 | */ |
298cf9be | 2420 | err = mdiobus_register(sc->mii_bus); |
f5279ffd MR |
2421 | if (err) { |
2422 | printk(KERN_ERR "%s: unable to register MDIO bus\n", | |
2423 | dev->name); | |
2424 | goto out_unirq; | |
59b81827 RB |
2425 | } |
2426 | ||
f5279ffd MR |
2427 | sc->sbm_speed = sbmac_speed_none; |
2428 | sc->sbm_duplex = sbmac_duplex_none; | |
2429 | sc->sbm_fc = sbmac_fc_none; | |
2430 | sc->sbm_pause = -1; | |
2431 | sc->sbm_link = 0; | |
bea3348e | 2432 | |
1da177e4 | 2433 | /* |
f5279ffd | 2434 | * Attach to the PHY |
1da177e4 | 2435 | */ |
f5279ffd MR |
2436 | err = sbmac_mii_probe(dev); |
2437 | if (err) | |
2438 | goto out_unregister; | |
74b0247f | 2439 | |
1da177e4 LT |
2440 | /* |
2441 | * Turn on the channel | |
2442 | */ | |
2443 | ||
2444 | sbmac_set_channel_state(sc,sbmac_state_on); | |
74b0247f | 2445 | |
1da177e4 | 2446 | netif_start_queue(dev); |
74b0247f | 2447 | |
1da177e4 | 2448 | sbmac_set_rx_mode(dev); |
74b0247f | 2449 | |
f5279ffd MR |
2450 | phy_start(sc->phy_dev); |
2451 | ||
2452 | napi_enable(&sc->napi); | |
74b0247f | 2453 | |
1da177e4 | 2454 | return 0; |
f5279ffd MR |
2455 | |
2456 | out_unregister: | |
298cf9be | 2457 | mdiobus_unregister(sc->mii_bus); |
f5279ffd MR |
2458 | |
2459 | out_unirq: | |
2460 | free_irq(dev->irq, dev); | |
2461 | ||
2462 | out_err: | |
2463 | return err; | |
1da177e4 LT |
2464 | } |
2465 | ||
59b81827 RB |
2466 | static int sbmac_mii_probe(struct net_device *dev) |
2467 | { | |
f5279ffd MR |
2468 | struct sbmac_softc *sc = netdev_priv(dev); |
2469 | struct phy_device *phy_dev; | |
59b81827 | 2470 | int i; |
1da177e4 | 2471 | |
f5279ffd | 2472 | for (i = 0; i < PHY_MAX_ADDR; i++) { |
298cf9be | 2473 | phy_dev = sc->mii_bus->phy_map[i]; |
f5279ffd MR |
2474 | if (phy_dev) |
2475 | break; | |
1da177e4 | 2476 | } |
f5279ffd MR |
2477 | if (!phy_dev) { |
2478 | printk(KERN_ERR "%s: no PHY found\n", dev->name); | |
2479 | return -ENXIO; | |
1da177e4 LT |
2480 | } |
2481 | ||
f5279ffd MR |
2482 | phy_dev = phy_connect(dev, phy_dev->dev.bus_id, &sbmac_mii_poll, 0, |
2483 | PHY_INTERFACE_MODE_GMII); | |
2484 | if (IS_ERR(phy_dev)) { | |
2485 | printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); | |
2486 | return PTR_ERR(phy_dev); | |
1da177e4 LT |
2487 | } |
2488 | ||
f5279ffd MR |
2489 | /* Remove any features not supported by the controller */ |
2490 | phy_dev->supported &= SUPPORTED_10baseT_Half | | |
2491 | SUPPORTED_10baseT_Full | | |
2492 | SUPPORTED_100baseT_Half | | |
2493 | SUPPORTED_100baseT_Full | | |
2494 | SUPPORTED_1000baseT_Half | | |
2495 | SUPPORTED_1000baseT_Full | | |
2496 | SUPPORTED_Autoneg | | |
2497 | SUPPORTED_MII | | |
2498 | SUPPORTED_Pause | | |
2499 | SUPPORTED_Asym_Pause; | |
2500 | phy_dev->advertising = phy_dev->supported; | |
2501 | ||
2502 | pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", | |
2503 | dev->name, phy_dev->drv->name, | |
2504 | phy_dev->dev.bus_id, phy_dev->irq); | |
2505 | ||
2506 | sc->phy_dev = phy_dev; | |
1da177e4 | 2507 | |
f5279ffd | 2508 | return 0; |
1da177e4 LT |
2509 | } |
2510 | ||
2511 | ||
f5279ffd | 2512 | static void sbmac_mii_poll(struct net_device *dev) |
1da177e4 | 2513 | { |
1da177e4 | 2514 | struct sbmac_softc *sc = netdev_priv(dev); |
f5279ffd MR |
2515 | struct phy_device *phy_dev = sc->phy_dev; |
2516 | unsigned long flags; | |
2517 | enum sbmac_fc fc; | |
2518 | int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg; | |
2519 | ||
2520 | link_chg = (sc->sbm_link != phy_dev->link); | |
2521 | speed_chg = (sc->sbm_speed != phy_dev->speed); | |
2522 | duplex_chg = (sc->sbm_duplex != phy_dev->duplex); | |
2523 | pause_chg = (sc->sbm_pause != phy_dev->pause); | |
2524 | ||
2525 | if (!link_chg && !speed_chg && !duplex_chg && !pause_chg) | |
2526 | return; /* Hmmm... */ | |
2527 | ||
2528 | if (!phy_dev->link) { | |
2529 | if (link_chg) { | |
2530 | sc->sbm_link = phy_dev->link; | |
2531 | sc->sbm_speed = sbmac_speed_none; | |
2532 | sc->sbm_duplex = sbmac_duplex_none; | |
2533 | sc->sbm_fc = sbmac_fc_disabled; | |
2534 | sc->sbm_pause = -1; | |
2535 | pr_info("%s: link unavailable\n", dev->name); | |
2536 | } | |
2537 | return; | |
2538 | } | |
1da177e4 | 2539 | |
f5279ffd MR |
2540 | if (phy_dev->duplex == DUPLEX_FULL) { |
2541 | if (phy_dev->pause) | |
2542 | fc = sbmac_fc_frame; | |
2543 | else | |
2544 | fc = sbmac_fc_disabled; | |
2545 | } else | |
2546 | fc = sbmac_fc_collision; | |
2547 | fc_chg = (sc->sbm_fc != fc); | |
74b0247f | 2548 | |
f5279ffd MR |
2549 | pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed, |
2550 | phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H'); | |
74b0247f | 2551 | |
f5279ffd | 2552 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f | 2553 | |
f5279ffd MR |
2554 | sc->sbm_speed = phy_dev->speed; |
2555 | sc->sbm_duplex = phy_dev->duplex; | |
2556 | sc->sbm_fc = fc; | |
2557 | sc->sbm_pause = phy_dev->pause; | |
2558 | sc->sbm_link = phy_dev->link; | |
1da177e4 | 2559 | |
f5279ffd MR |
2560 | if ((speed_chg || duplex_chg || fc_chg) && |
2561 | sc->sbm_state != sbmac_state_off) { | |
2562 | /* | |
2563 | * something changed, restart the channel | |
2564 | */ | |
2565 | if (debug > 1) | |
2566 | pr_debug("%s: restarting channel " | |
2567 | "because PHY state changed\n", dev->name); | |
2568 | sbmac_channel_stop(sc); | |
2569 | sbmac_channel_start(sc); | |
1da177e4 | 2570 | } |
74b0247f | 2571 | |
f5279ffd | 2572 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 LT |
2573 | } |
2574 | ||
2575 | ||
2576 | static void sbmac_tx_timeout (struct net_device *dev) | |
2577 | { | |
2578 | struct sbmac_softc *sc = netdev_priv(dev); | |
be61ea52 | 2579 | unsigned long flags; |
74b0247f | 2580 | |
be61ea52 | 2581 | spin_lock_irqsave(&sc->sbm_lock, flags); |
74b0247f RB |
2582 | |
2583 | ||
1da177e4 | 2584 | dev->trans_start = jiffies; |
09f75cd7 | 2585 | dev->stats.tx_errors++; |
74b0247f | 2586 | |
be61ea52 | 2587 | spin_unlock_irqrestore(&sc->sbm_lock, flags); |
1da177e4 LT |
2588 | |
2589 | printk (KERN_WARNING "%s: Transmit timed out\n",dev->name); | |
2590 | } | |
2591 | ||
2592 | ||
2593 | ||
2594 | ||
1da177e4 LT |
2595 | static void sbmac_set_rx_mode(struct net_device *dev) |
2596 | { | |
2597 | unsigned long flags; | |
1da177e4 LT |
2598 | struct sbmac_softc *sc = netdev_priv(dev); |
2599 | ||
2600 | spin_lock_irqsave(&sc->sbm_lock, flags); | |
2601 | if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) { | |
2602 | /* | |
2603 | * Promiscuous changed. | |
2604 | */ | |
74b0247f RB |
2605 | |
2606 | if (dev->flags & IFF_PROMISC) { | |
1da177e4 LT |
2607 | sbmac_promiscuous_mode(sc,1); |
2608 | } | |
2609 | else { | |
1da177e4 LT |
2610 | sbmac_promiscuous_mode(sc,0); |
2611 | } | |
2612 | } | |
2613 | spin_unlock_irqrestore(&sc->sbm_lock, flags); | |
74b0247f | 2614 | |
1da177e4 LT |
2615 | /* |
2616 | * Program the multicasts. Do this every time. | |
2617 | */ | |
74b0247f | 2618 | |
1da177e4 | 2619 | sbmac_setmulti(sc); |
74b0247f | 2620 | |
1da177e4 LT |
2621 | } |
2622 | ||
2623 | static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
2624 | { | |
2625 | struct sbmac_softc *sc = netdev_priv(dev); | |
74b0247f | 2626 | |
f5279ffd MR |
2627 | if (!netif_running(dev) || !sc->phy_dev) |
2628 | return -EINVAL; | |
74b0247f | 2629 | |
f5279ffd | 2630 | return phy_mii_ioctl(sc->phy_dev, if_mii(rq), cmd); |
1da177e4 LT |
2631 | } |
2632 | ||
2633 | static int sbmac_close(struct net_device *dev) | |
2634 | { | |
2635 | struct sbmac_softc *sc = netdev_priv(dev); | |
1da177e4 | 2636 | |
bea3348e SH |
2637 | napi_disable(&sc->napi); |
2638 | ||
f5279ffd | 2639 | phy_stop(sc->phy_dev); |
1da177e4 | 2640 | |
f5279ffd | 2641 | sbmac_set_channel_state(sc, sbmac_state_off); |
1da177e4 LT |
2642 | |
2643 | netif_stop_queue(dev); | |
2644 | ||
f5279ffd MR |
2645 | if (debug > 1) |
2646 | pr_debug("%s: Shutting down ethercard\n", dev->name); | |
1da177e4 | 2647 | |
f5279ffd MR |
2648 | phy_disconnect(sc->phy_dev); |
2649 | sc->phy_dev = NULL; | |
2650 | ||
298cf9be | 2651 | mdiobus_unregister(sc->mii_bus); |
1da177e4 | 2652 | |
f5279ffd | 2653 | free_irq(dev->irq, dev); |
1da177e4 LT |
2654 | |
2655 | sbdma_emptyring(&(sc->sbm_txdma)); | |
2656 | sbdma_emptyring(&(sc->sbm_rxdma)); | |
74b0247f | 2657 | |
1da177e4 LT |
2658 | return 0; |
2659 | } | |
2660 | ||
bea3348e | 2661 | static int sbmac_poll(struct napi_struct *napi, int budget) |
693aa947 | 2662 | { |
bea3348e SH |
2663 | struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi); |
2664 | struct net_device *dev = sc->sbm_dev; | |
693aa947 | 2665 | int work_done; |
1da177e4 | 2666 | |
bea3348e | 2667 | work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1); |
693aa947 MM |
2668 | sbdma_tx_process(sc, &(sc->sbm_txdma), 1); |
2669 | ||
bea3348e SH |
2670 | if (work_done < budget) { |
2671 | netif_rx_complete(dev, napi); | |
693aa947 MM |
2672 | |
2673 | #ifdef CONFIG_SBMAC_COALESCE | |
2674 | __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | | |
2675 | ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), | |
2676 | sc->sbm_imr); | |
2677 | #else | |
2678 | __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | | |
2679 | (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); | |
2680 | #endif | |
2681 | } | |
2682 | ||
bea3348e | 2683 | return work_done; |
693aa947 | 2684 | } |
1da177e4 | 2685 | |
f5279ffd MR |
2686 | |
2687 | static int __init sbmac_probe(struct platform_device *pldev) | |
2688 | { | |
2689 | struct net_device *dev; | |
2690 | struct sbmac_softc *sc; | |
2691 | void __iomem *sbm_base; | |
2692 | struct resource *res; | |
2693 | u64 sbmac_orig_hwaddr; | |
2694 | int err; | |
2695 | ||
2696 | res = platform_get_resource(pldev, IORESOURCE_MEM, 0); | |
2697 | BUG_ON(!res); | |
2698 | sbm_base = ioremap_nocache(res->start, res->end - res->start + 1); | |
2699 | if (!sbm_base) { | |
2700 | printk(KERN_ERR "%s: unable to map device registers\n", | |
2701 | pldev->dev.bus_id); | |
2702 | err = -ENOMEM; | |
2703 | goto out_out; | |
2704 | } | |
2705 | ||
2706 | /* | |
2707 | * The R_MAC_ETHERNET_ADDR register will be set to some nonzero | |
2708 | * value for us by the firmware if we're going to use this MAC. | |
2709 | * If we find a zero, skip this MAC. | |
2710 | */ | |
2711 | sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); | |
2712 | pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", pldev->dev.bus_id, | |
2713 | sbmac_orig_hwaddr ? "" : "not ", (long long)res->start); | |
2714 | if (sbmac_orig_hwaddr == 0) { | |
2715 | err = 0; | |
2716 | goto out_unmap; | |
2717 | } | |
2718 | ||
2719 | /* | |
2720 | * Okay, cool. Initialize this MAC. | |
2721 | */ | |
2722 | dev = alloc_etherdev(sizeof(struct sbmac_softc)); | |
2723 | if (!dev) { | |
2724 | printk(KERN_ERR "%s: unable to allocate etherdev\n", | |
2725 | pldev->dev.bus_id); | |
2726 | err = -ENOMEM; | |
2727 | goto out_unmap; | |
2728 | } | |
2729 | ||
2730 | pldev->dev.driver_data = dev; | |
2731 | SET_NETDEV_DEV(dev, &pldev->dev); | |
2732 | ||
2733 | sc = netdev_priv(dev); | |
2734 | sc->sbm_base = sbm_base; | |
2735 | ||
2736 | err = sbmac_init(pldev, res->start); | |
2737 | if (err) | |
2738 | goto out_kfree; | |
2739 | ||
2740 | return 0; | |
2741 | ||
2742 | out_kfree: | |
2743 | free_netdev(dev); | |
2744 | __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR); | |
2745 | ||
2746 | out_unmap: | |
2747 | iounmap(sbm_base); | |
2748 | ||
2749 | out_out: | |
2750 | return err; | |
2751 | } | |
2752 | ||
2753 | static int __exit sbmac_remove(struct platform_device *pldev) | |
2754 | { | |
2755 | struct net_device *dev = pldev->dev.driver_data; | |
2756 | struct sbmac_softc *sc = netdev_priv(dev); | |
2757 | ||
2758 | unregister_netdev(dev); | |
2759 | sbmac_uninitctx(sc); | |
298cf9be | 2760 | mdiobus_free(sc->mii_bus); |
f5279ffd MR |
2761 | iounmap(sc->sbm_base); |
2762 | free_netdev(dev); | |
2763 | ||
2764 | return 0; | |
2765 | } | |
2766 | ||
2767 | ||
2768 | static struct platform_device **sbmac_pldev; | |
2769 | static int sbmac_max_units; | |
2770 | ||
f90fdc3c | 2771 | #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR) |
f5279ffd | 2772 | static void __init sbmac_setup_hwaddr(int idx, char *addr) |
1da177e4 | 2773 | { |
f5279ffd MR |
2774 | void __iomem *sbm_base; |
2775 | unsigned long start, end; | |
1da177e4 LT |
2776 | uint8_t eaddr[6]; |
2777 | uint64_t val; | |
1da177e4 | 2778 | |
f5279ffd MR |
2779 | if (idx >= sbmac_max_units) |
2780 | return; | |
2781 | ||
2782 | start = A_MAC_CHANNEL_BASE(idx); | |
2783 | end = A_MAC_CHANNEL_BASE(idx + 1) - 1; | |
2784 | ||
2785 | sbm_base = ioremap_nocache(start, end - start + 1); | |
2786 | if (!sbm_base) { | |
2787 | printk(KERN_ERR "%s: unable to map device registers\n", | |
2788 | sbmac_string); | |
2789 | return; | |
2790 | } | |
2791 | ||
2792 | sbmac_parse_hwaddr(addr, eaddr); | |
1da177e4 | 2793 | val = sbmac_addr2reg(eaddr); |
f5279ffd MR |
2794 | __raw_writeq(val, sbm_base + R_MAC_ETHERNET_ADDR); |
2795 | val = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); | |
2796 | ||
2797 | iounmap(sbm_base); | |
1da177e4 LT |
2798 | } |
2799 | #endif | |
2800 | ||
f5279ffd MR |
2801 | static int __init sbmac_platform_probe_one(int idx) |
2802 | { | |
2803 | struct platform_device *pldev; | |
2804 | struct { | |
2805 | struct resource r; | |
2806 | char name[strlen(sbmac_pretty) + 4]; | |
2807 | } *res; | |
2808 | int err; | |
2809 | ||
2810 | res = kzalloc(sizeof(*res), GFP_KERNEL); | |
2811 | if (!res) { | |
2812 | printk(KERN_ERR "%s.%d: unable to allocate memory\n", | |
2813 | sbmac_string, idx); | |
2814 | err = -ENOMEM; | |
2815 | goto out_err; | |
2816 | } | |
2817 | ||
2818 | /* | |
2819 | * This is the base address of the MAC. | |
2820 | */ | |
2821 | snprintf(res->name, sizeof(res->name), "%s %d", sbmac_pretty, idx); | |
2822 | res->r.name = res->name; | |
2823 | res->r.flags = IORESOURCE_MEM; | |
2824 | res->r.start = A_MAC_CHANNEL_BASE(idx); | |
2825 | res->r.end = A_MAC_CHANNEL_BASE(idx + 1) - 1; | |
2826 | ||
2827 | pldev = platform_device_register_simple(sbmac_string, idx, &res->r, 1); | |
2828 | if (IS_ERR(pldev)) { | |
2829 | printk(KERN_ERR "%s.%d: unable to register platform device\n", | |
2830 | sbmac_string, idx); | |
2831 | err = PTR_ERR(pldev); | |
2832 | goto out_kfree; | |
2833 | } | |
2834 | ||
2835 | if (!pldev->dev.driver) { | |
2836 | err = 0; /* No hardware at this address. */ | |
2837 | goto out_unregister; | |
2838 | } | |
2839 | ||
2840 | sbmac_pldev[idx] = pldev; | |
2841 | return 0; | |
2842 | ||
2843 | out_unregister: | |
2844 | platform_device_unregister(pldev); | |
1da177e4 | 2845 | |
f5279ffd MR |
2846 | out_kfree: |
2847 | kfree(res); | |
2848 | ||
2849 | out_err: | |
2850 | return err; | |
2851 | } | |
2852 | ||
2853 | static void __init sbmac_platform_probe(void) | |
1da177e4 | 2854 | { |
f5279ffd | 2855 | int i; |
74b0247f | 2856 | |
f90fdc3c | 2857 | /* Set the number of available units based on the SOC type. */ |
1da177e4 LT |
2858 | switch (soc_type) { |
2859 | case K_SYS_SOC_TYPE_BCM1250: | |
2860 | case K_SYS_SOC_TYPE_BCM1250_ALT: | |
f5279ffd | 2861 | sbmac_max_units = 3; |
1da177e4 LT |
2862 | break; |
2863 | case K_SYS_SOC_TYPE_BCM1120: | |
2864 | case K_SYS_SOC_TYPE_BCM1125: | |
2865 | case K_SYS_SOC_TYPE_BCM1125H: | |
f5279ffd MR |
2866 | case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */ |
2867 | sbmac_max_units = 2; | |
1da177e4 | 2868 | break; |
f90fdc3c RB |
2869 | case K_SYS_SOC_TYPE_BCM1x55: |
2870 | case K_SYS_SOC_TYPE_BCM1x80: | |
f5279ffd | 2871 | sbmac_max_units = 4; |
f90fdc3c | 2872 | break; |
1da177e4 | 2873 | default: |
f5279ffd | 2874 | return; /* none */ |
1da177e4 | 2875 | } |
1da177e4 | 2876 | |
f90fdc3c RB |
2877 | /* |
2878 | * For bringup when not using the firmware, we can pre-fill | |
2879 | * the MAC addresses using the environment variables | |
2880 | * specified in this file (or maybe from the config file?) | |
2881 | */ | |
2882 | #ifdef SBMAC_ETH0_HWADDR | |
f5279ffd | 2883 | sbmac_setup_hwaddr(0, SBMAC_ETH0_HWADDR); |
f90fdc3c RB |
2884 | #endif |
2885 | #ifdef SBMAC_ETH1_HWADDR | |
f5279ffd | 2886 | sbmac_setup_hwaddr(1, SBMAC_ETH1_HWADDR); |
f90fdc3c RB |
2887 | #endif |
2888 | #ifdef SBMAC_ETH2_HWADDR | |
f5279ffd | 2889 | sbmac_setup_hwaddr(2, SBMAC_ETH2_HWADDR); |
f90fdc3c RB |
2890 | #endif |
2891 | #ifdef SBMAC_ETH3_HWADDR | |
f5279ffd | 2892 | sbmac_setup_hwaddr(3, SBMAC_ETH3_HWADDR); |
f90fdc3c RB |
2893 | #endif |
2894 | ||
f5279ffd MR |
2895 | sbmac_pldev = kcalloc(sbmac_max_units, sizeof(*sbmac_pldev), |
2896 | GFP_KERNEL); | |
2897 | if (!sbmac_pldev) { | |
2898 | printk(KERN_ERR "%s: unable to allocate memory\n", | |
2899 | sbmac_string); | |
2900 | return; | |
2901 | } | |
2902 | ||
f90fdc3c RB |
2903 | /* |
2904 | * Walk through the Ethernet controllers and find | |
2905 | * those who have their MAC addresses set. | |
2906 | */ | |
f5279ffd MR |
2907 | for (i = 0; i < sbmac_max_units; i++) |
2908 | if (sbmac_platform_probe_one(i)) | |
2909 | break; | |
2910 | } | |
1da177e4 | 2911 | |
1da177e4 | 2912 | |
f5279ffd MR |
2913 | static void __exit sbmac_platform_cleanup(void) |
2914 | { | |
2915 | int i; | |
1da177e4 | 2916 | |
f5279ffd MR |
2917 | for (i = 0; i < sbmac_max_units; i++) |
2918 | platform_device_unregister(sbmac_pldev[i]); | |
2919 | kfree(sbmac_pldev); | |
2920 | } | |
1da177e4 | 2921 | |
1da177e4 | 2922 | |
f5279ffd MR |
2923 | static struct platform_driver sbmac_driver = { |
2924 | .probe = sbmac_probe, | |
2925 | .remove = __exit_p(sbmac_remove), | |
2926 | .driver = { | |
2927 | .name = sbmac_string, | |
2928 | }, | |
2929 | }; | |
1da177e4 | 2930 | |
f5279ffd MR |
2931 | static int __init sbmac_init_module(void) |
2932 | { | |
2933 | int err; | |
1da177e4 | 2934 | |
f5279ffd MR |
2935 | err = platform_driver_register(&sbmac_driver); |
2936 | if (err) | |
2937 | return err; | |
1da177e4 | 2938 | |
f5279ffd | 2939 | sbmac_platform_probe(); |
1da177e4 | 2940 | |
f5279ffd MR |
2941 | return err; |
2942 | } | |
1da177e4 | 2943 | |
f5279ffd | 2944 | static void __exit sbmac_cleanup_module(void) |
1da177e4 | 2945 | { |
f5279ffd MR |
2946 | sbmac_platform_cleanup(); |
2947 | platform_driver_unregister(&sbmac_driver); | |
1da177e4 LT |
2948 | } |
2949 | ||
2950 | module_init(sbmac_init_module); | |
2951 | module_exit(sbmac_cleanup_module); |