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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 | 23 | #include "net_driver.h" |
8ceee660 BH |
24 | #include "ethtool.h" |
25 | #include "tx.h" | |
26 | #include "rx.h" | |
27 | #include "efx.h" | |
28 | #include "mdio_10g.h" | |
29 | #include "falcon.h" | |
8ceee660 BH |
30 | |
31 | #define EFX_MAX_MTU (9 * 1024) | |
32 | ||
33 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
34 | * a work item is pushed onto this work queue to retry the allocation later, | |
35 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
36 | * workqueue, there is nothing to be gained in making it per NIC | |
37 | */ | |
38 | static struct workqueue_struct *refill_workqueue; | |
39 | ||
1ab00629 SH |
40 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
41 | * queued onto this work queue. This is not a per-nic work queue, because | |
42 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
43 | */ | |
44 | static struct workqueue_struct *reset_workqueue; | |
45 | ||
8ceee660 BH |
46 | /************************************************************************** |
47 | * | |
48 | * Configurable values | |
49 | * | |
50 | *************************************************************************/ | |
51 | ||
52 | /* | |
53 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
54 | * | |
55 | * This sets the default for new devices. It can be controlled later | |
56 | * using ethtool. | |
57 | */ | |
dc8cfa55 | 58 | static int lro = true; |
8ceee660 BH |
59 | module_param(lro, int, 0644); |
60 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
61 | ||
62 | /* | |
63 | * Use separate channels for TX and RX events | |
64 | * | |
28b581ab NT |
65 | * Set this to 1 to use separate channels for TX and RX. It allows us |
66 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 67 | * |
28b581ab | 68 | * This is only used in MSI-X interrupt mode |
8ceee660 | 69 | */ |
28b581ab NT |
70 | static unsigned int separate_tx_channels; |
71 | module_param(separate_tx_channels, uint, 0644); | |
72 | MODULE_PARM_DESC(separate_tx_channels, | |
73 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
74 | |
75 | /* This is the weight assigned to each of the (per-channel) virtual | |
76 | * NAPI devices. | |
77 | */ | |
78 | static int napi_weight = 64; | |
79 | ||
80 | /* This is the time (in jiffies) between invocations of the hardware | |
81 | * monitor, which checks for known hardware bugs and resets the | |
82 | * hardware and driver as necessary. | |
83 | */ | |
84 | unsigned int efx_monitor_interval = 1 * HZ; | |
85 | ||
8ceee660 BH |
86 | /* This controls whether or not the driver will initialise devices |
87 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
88 | * such devices will be initialised with a random locally-generated | |
89 | * MAC address. This allows for loading the sfc_mtd driver to | |
90 | * reprogram the flash, even if the flash contents (including the MAC | |
91 | * address) have previously been erased. | |
92 | */ | |
93 | static unsigned int allow_bad_hwaddr; | |
94 | ||
95 | /* Initial interrupt moderation settings. They can be modified after | |
96 | * module load with ethtool. | |
97 | * | |
98 | * The default for RX should strike a balance between increasing the | |
99 | * round-trip latency and reducing overhead. | |
100 | */ | |
101 | static unsigned int rx_irq_mod_usec = 60; | |
102 | ||
103 | /* Initial interrupt moderation settings. They can be modified after | |
104 | * module load with ethtool. | |
105 | * | |
106 | * This default is chosen to ensure that a 10G link does not go idle | |
107 | * while a TX queue is stopped after it has become full. A queue is | |
108 | * restarted when it drops below half full. The time this takes (assuming | |
109 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
110 | * 512 / 3 * 1.2 = 205 usec. | |
111 | */ | |
112 | static unsigned int tx_irq_mod_usec = 150; | |
113 | ||
114 | /* This is the first interrupt mode to try out of: | |
115 | * 0 => MSI-X | |
116 | * 1 => MSI | |
117 | * 2 => legacy | |
118 | */ | |
119 | static unsigned int interrupt_mode; | |
120 | ||
121 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
122 | * i.e. the number of CPUs among which we may distribute simultaneous | |
123 | * interrupt handling. | |
124 | * | |
125 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
126 | * The default (0) means to assign an interrupt to each package (level II cache) | |
127 | */ | |
128 | static unsigned int rss_cpus; | |
129 | module_param(rss_cpus, uint, 0444); | |
130 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
131 | ||
84ae48fe BH |
132 | static int phy_flash_cfg; |
133 | module_param(phy_flash_cfg, int, 0644); | |
134 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
135 | ||
6fb70fd1 BH |
136 | static unsigned irq_adapt_low_thresh = 10000; |
137 | module_param(irq_adapt_low_thresh, uint, 0644); | |
138 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
139 | "Threshold score for reducing IRQ moderation"); | |
140 | ||
141 | static unsigned irq_adapt_high_thresh = 20000; | |
142 | module_param(irq_adapt_high_thresh, uint, 0644); | |
143 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
144 | "Threshold score for increasing IRQ moderation"); | |
145 | ||
8ceee660 BH |
146 | /************************************************************************** |
147 | * | |
148 | * Utility functions and prototypes | |
149 | * | |
150 | *************************************************************************/ | |
151 | static void efx_remove_channel(struct efx_channel *channel); | |
152 | static void efx_remove_port(struct efx_nic *efx); | |
153 | static void efx_fini_napi(struct efx_nic *efx); | |
154 | static void efx_fini_channels(struct efx_nic *efx); | |
155 | ||
156 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
157 | do { \ | |
3c78708f | 158 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
159 | ASSERT_RTNL(); \ |
160 | } while (0) | |
161 | ||
162 | /************************************************************************** | |
163 | * | |
164 | * Event queue processing | |
165 | * | |
166 | *************************************************************************/ | |
167 | ||
168 | /* Process channel's event queue | |
169 | * | |
170 | * This function is responsible for processing the event queue of a | |
171 | * single channel. The caller must guarantee that this function will | |
172 | * never be concurrently called more than once on the same channel, | |
173 | * though different channels may be being processed concurrently. | |
174 | */ | |
4d566063 | 175 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 176 | { |
42cbe2d7 BH |
177 | struct efx_nic *efx = channel->efx; |
178 | int rx_packets; | |
8ceee660 | 179 | |
42cbe2d7 | 180 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 181 | !channel->enabled)) |
42cbe2d7 | 182 | return 0; |
8ceee660 | 183 | |
42cbe2d7 BH |
184 | rx_packets = falcon_process_eventq(channel, rx_quota); |
185 | if (rx_packets == 0) | |
186 | return 0; | |
8ceee660 BH |
187 | |
188 | /* Deliver last RX packet. */ | |
189 | if (channel->rx_pkt) { | |
190 | __efx_rx_packet(channel, channel->rx_pkt, | |
191 | channel->rx_pkt_csummed); | |
192 | channel->rx_pkt = NULL; | |
193 | } | |
194 | ||
8ceee660 BH |
195 | efx_rx_strategy(channel); |
196 | ||
42cbe2d7 | 197 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 198 | |
42cbe2d7 | 199 | return rx_packets; |
8ceee660 BH |
200 | } |
201 | ||
202 | /* Mark channel as finished processing | |
203 | * | |
204 | * Note that since we will not receive further interrupts for this | |
205 | * channel before we finish processing and call the eventq_read_ack() | |
206 | * method, there is no need to use the interrupt hold-off timers. | |
207 | */ | |
208 | static inline void efx_channel_processed(struct efx_channel *channel) | |
209 | { | |
5b9e207c BH |
210 | /* The interrupt handler for this channel may set work_pending |
211 | * as soon as we acknowledge the events we've seen. Make sure | |
212 | * it's cleared before then. */ | |
dc8cfa55 | 213 | channel->work_pending = false; |
5b9e207c BH |
214 | smp_wmb(); |
215 | ||
8ceee660 BH |
216 | falcon_eventq_read_ack(channel); |
217 | } | |
218 | ||
219 | /* NAPI poll handler | |
220 | * | |
221 | * NAPI guarantees serialisation of polls of the same device, which | |
222 | * provides the guarantee required by efx_process_channel(). | |
223 | */ | |
224 | static int efx_poll(struct napi_struct *napi, int budget) | |
225 | { | |
226 | struct efx_channel *channel = | |
227 | container_of(napi, struct efx_channel, napi_str); | |
8ceee660 BH |
228 | int rx_packets; |
229 | ||
230 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
231 | channel->channel, raw_smp_processor_id()); | |
232 | ||
42cbe2d7 | 233 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
234 | |
235 | if (rx_packets < budget) { | |
6fb70fd1 BH |
236 | struct efx_nic *efx = channel->efx; |
237 | ||
238 | if (channel->used_flags & EFX_USED_BY_RX && | |
239 | efx->irq_rx_adaptive && | |
240 | unlikely(++channel->irq_count == 1000)) { | |
241 | unsigned old_irq_moderation = channel->irq_moderation; | |
242 | ||
243 | if (unlikely(channel->irq_mod_score < | |
244 | irq_adapt_low_thresh)) { | |
245 | channel->irq_moderation = | |
246 | max_t(int, | |
247 | channel->irq_moderation - | |
248 | FALCON_IRQ_MOD_RESOLUTION, | |
249 | FALCON_IRQ_MOD_RESOLUTION); | |
250 | } else if (unlikely(channel->irq_mod_score > | |
251 | irq_adapt_high_thresh)) { | |
252 | channel->irq_moderation = | |
253 | min(channel->irq_moderation + | |
254 | FALCON_IRQ_MOD_RESOLUTION, | |
255 | efx->irq_rx_moderation); | |
256 | } | |
257 | ||
258 | if (channel->irq_moderation != old_irq_moderation) | |
259 | falcon_set_int_moderation(channel); | |
260 | ||
261 | channel->irq_count = 0; | |
262 | channel->irq_mod_score = 0; | |
263 | } | |
264 | ||
8ceee660 | 265 | /* There is no race here; although napi_disable() will |
288379f0 | 266 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
267 | * since efx_channel_processed() will have no effect if |
268 | * interrupts have already been disabled. | |
269 | */ | |
288379f0 | 270 | napi_complete(napi); |
8ceee660 BH |
271 | efx_channel_processed(channel); |
272 | } | |
273 | ||
274 | return rx_packets; | |
275 | } | |
276 | ||
277 | /* Process the eventq of the specified channel immediately on this CPU | |
278 | * | |
279 | * Disable hardware generated interrupts, wait for any existing | |
280 | * processing to finish, then directly poll (and ack ) the eventq. | |
281 | * Finally reenable NAPI and interrupts. | |
282 | * | |
283 | * Since we are touching interrupts the caller should hold the suspend lock | |
284 | */ | |
285 | void efx_process_channel_now(struct efx_channel *channel) | |
286 | { | |
287 | struct efx_nic *efx = channel->efx; | |
288 | ||
289 | BUG_ON(!channel->used_flags); | |
290 | BUG_ON(!channel->enabled); | |
291 | ||
292 | /* Disable interrupts and wait for ISRs to complete */ | |
293 | falcon_disable_interrupts(efx); | |
294 | if (efx->legacy_irq) | |
295 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 296 | if (channel->irq) |
8ceee660 BH |
297 | synchronize_irq(channel->irq); |
298 | ||
299 | /* Wait for any NAPI processing to complete */ | |
300 | napi_disable(&channel->napi_str); | |
301 | ||
302 | /* Poll the channel */ | |
91ad757c | 303 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
304 | |
305 | /* Ack the eventq. This may cause an interrupt to be generated | |
306 | * when they are reenabled */ | |
307 | efx_channel_processed(channel); | |
308 | ||
309 | napi_enable(&channel->napi_str); | |
310 | falcon_enable_interrupts(efx); | |
311 | } | |
312 | ||
313 | /* Create event queue | |
314 | * Event queue memory allocations are done only once. If the channel | |
315 | * is reset, the memory buffer will be reused; this guards against | |
316 | * errors during channel reset and also simplifies interrupt handling. | |
317 | */ | |
318 | static int efx_probe_eventq(struct efx_channel *channel) | |
319 | { | |
320 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
321 | ||
322 | return falcon_probe_eventq(channel); | |
323 | } | |
324 | ||
325 | /* Prepare channel's event queue */ | |
bc3c90a2 | 326 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
327 | { |
328 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
329 | ||
330 | channel->eventq_read_ptr = 0; | |
331 | ||
bc3c90a2 | 332 | falcon_init_eventq(channel); |
8ceee660 BH |
333 | } |
334 | ||
335 | static void efx_fini_eventq(struct efx_channel *channel) | |
336 | { | |
337 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
338 | ||
339 | falcon_fini_eventq(channel); | |
340 | } | |
341 | ||
342 | static void efx_remove_eventq(struct efx_channel *channel) | |
343 | { | |
344 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
345 | ||
346 | falcon_remove_eventq(channel); | |
347 | } | |
348 | ||
349 | /************************************************************************** | |
350 | * | |
351 | * Channel handling | |
352 | * | |
353 | *************************************************************************/ | |
354 | ||
8ceee660 BH |
355 | static int efx_probe_channel(struct efx_channel *channel) |
356 | { | |
357 | struct efx_tx_queue *tx_queue; | |
358 | struct efx_rx_queue *rx_queue; | |
359 | int rc; | |
360 | ||
361 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
362 | ||
363 | rc = efx_probe_eventq(channel); | |
364 | if (rc) | |
365 | goto fail1; | |
366 | ||
367 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
368 | rc = efx_probe_tx_queue(tx_queue); | |
369 | if (rc) | |
370 | goto fail2; | |
371 | } | |
372 | ||
373 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
374 | rc = efx_probe_rx_queue(rx_queue); | |
375 | if (rc) | |
376 | goto fail3; | |
377 | } | |
378 | ||
379 | channel->n_rx_frm_trunc = 0; | |
380 | ||
381 | return 0; | |
382 | ||
383 | fail3: | |
384 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
385 | efx_remove_rx_queue(rx_queue); | |
386 | fail2: | |
387 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
388 | efx_remove_tx_queue(tx_queue); | |
389 | fail1: | |
390 | return rc; | |
391 | } | |
392 | ||
393 | ||
56536e9c BH |
394 | static void efx_set_channel_names(struct efx_nic *efx) |
395 | { | |
396 | struct efx_channel *channel; | |
397 | const char *type = ""; | |
398 | int number; | |
399 | ||
400 | efx_for_each_channel(channel, efx) { | |
401 | number = channel->channel; | |
402 | if (efx->n_channels > efx->n_rx_queues) { | |
403 | if (channel->channel < efx->n_rx_queues) { | |
404 | type = "-rx"; | |
405 | } else { | |
406 | type = "-tx"; | |
407 | number -= efx->n_rx_queues; | |
408 | } | |
409 | } | |
410 | snprintf(channel->name, sizeof(channel->name), | |
411 | "%s%s-%d", efx->name, type, number); | |
412 | } | |
413 | } | |
414 | ||
8ceee660 BH |
415 | /* Channels are shutdown and reinitialised whilst the NIC is running |
416 | * to propagate configuration changes (mtu, checksum offload), or | |
417 | * to clear hardware error conditions | |
418 | */ | |
bc3c90a2 | 419 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
420 | { |
421 | struct efx_tx_queue *tx_queue; | |
422 | struct efx_rx_queue *rx_queue; | |
423 | struct efx_channel *channel; | |
8ceee660 | 424 | |
f7f13b0b BH |
425 | /* Calculate the rx buffer allocation parameters required to |
426 | * support the current MTU, including padding for header | |
427 | * alignment and overruns. | |
428 | */ | |
429 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
430 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
431 | efx->type->rx_buffer_padding); | |
432 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
433 | |
434 | /* Initialise the channels */ | |
435 | efx_for_each_channel(channel, efx) { | |
436 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
437 | ||
bc3c90a2 | 438 | efx_init_eventq(channel); |
8ceee660 | 439 | |
bc3c90a2 BH |
440 | efx_for_each_channel_tx_queue(tx_queue, channel) |
441 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
442 | |
443 | /* The rx buffer allocation strategy is MTU dependent */ | |
444 | efx_rx_strategy(channel); | |
445 | ||
bc3c90a2 BH |
446 | efx_for_each_channel_rx_queue(rx_queue, channel) |
447 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
448 | |
449 | WARN_ON(channel->rx_pkt != NULL); | |
450 | efx_rx_strategy(channel); | |
7e765cb4 BH |
451 | |
452 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
453 | efx_poll, napi_weight); | |
8ceee660 | 454 | } |
8ceee660 BH |
455 | } |
456 | ||
457 | /* This enables event queue processing and packet transmission. | |
458 | * | |
459 | * Note that this function is not allowed to fail, since that would | |
460 | * introduce too much complexity into the suspend/resume path. | |
461 | */ | |
462 | static void efx_start_channel(struct efx_channel *channel) | |
463 | { | |
464 | struct efx_rx_queue *rx_queue; | |
465 | ||
466 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
467 | ||
5b9e207c BH |
468 | /* The interrupt handler for this channel may set work_pending |
469 | * as soon as we enable it. Make sure it's cleared before | |
470 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
471 | channel->work_pending = false; |
472 | channel->enabled = true; | |
5b9e207c | 473 | smp_wmb(); |
8ceee660 BH |
474 | |
475 | napi_enable(&channel->napi_str); | |
476 | ||
477 | /* Load up RX descriptors */ | |
478 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
479 | efx_fast_push_rx_descriptors(rx_queue); | |
480 | } | |
481 | ||
482 | /* This disables event queue processing and packet transmission. | |
483 | * This function does not guarantee that all queue processing | |
484 | * (e.g. RX refill) is complete. | |
485 | */ | |
486 | static void efx_stop_channel(struct efx_channel *channel) | |
487 | { | |
488 | struct efx_rx_queue *rx_queue; | |
489 | ||
490 | if (!channel->enabled) | |
491 | return; | |
492 | ||
493 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
494 | ||
dc8cfa55 | 495 | channel->enabled = false; |
8ceee660 BH |
496 | napi_disable(&channel->napi_str); |
497 | ||
498 | /* Ensure that any worker threads have exited or will be no-ops */ | |
499 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
500 | spin_lock_bh(&rx_queue->add_lock); | |
501 | spin_unlock_bh(&rx_queue->add_lock); | |
502 | } | |
503 | } | |
504 | ||
505 | static void efx_fini_channels(struct efx_nic *efx) | |
506 | { | |
507 | struct efx_channel *channel; | |
508 | struct efx_tx_queue *tx_queue; | |
509 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 510 | int rc; |
8ceee660 BH |
511 | |
512 | EFX_ASSERT_RESET_SERIALISED(efx); | |
513 | BUG_ON(efx->port_enabled); | |
514 | ||
6bc5d3a9 BH |
515 | rc = falcon_flush_queues(efx); |
516 | if (rc) | |
517 | EFX_ERR(efx, "failed to flush queues\n"); | |
518 | else | |
519 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
520 | ||
8ceee660 BH |
521 | efx_for_each_channel(channel, efx) { |
522 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
523 | ||
524 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
525 | efx_fini_rx_queue(rx_queue); | |
526 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
527 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
528 | efx_fini_eventq(channel); |
529 | } | |
530 | } | |
531 | ||
532 | static void efx_remove_channel(struct efx_channel *channel) | |
533 | { | |
534 | struct efx_tx_queue *tx_queue; | |
535 | struct efx_rx_queue *rx_queue; | |
536 | ||
537 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
538 | ||
539 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
540 | efx_remove_rx_queue(rx_queue); | |
541 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
542 | efx_remove_tx_queue(tx_queue); | |
543 | efx_remove_eventq(channel); | |
544 | ||
545 | channel->used_flags = 0; | |
546 | } | |
547 | ||
548 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
549 | { | |
550 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
551 | } | |
552 | ||
553 | /************************************************************************** | |
554 | * | |
555 | * Port handling | |
556 | * | |
557 | **************************************************************************/ | |
558 | ||
559 | /* This ensures that the kernel is kept informed (via | |
560 | * netif_carrier_on/off) of the link status, and also maintains the | |
561 | * link status's stop on the port's TX queue. | |
562 | */ | |
563 | static void efx_link_status_changed(struct efx_nic *efx) | |
564 | { | |
8ceee660 BH |
565 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
566 | * that no events are triggered between unregister_netdev() and the | |
567 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
568 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
569 | if (!netif_running(efx->net_dev)) | |
570 | return; | |
571 | ||
8c8661e4 BH |
572 | if (efx->port_inhibited) { |
573 | netif_carrier_off(efx->net_dev); | |
574 | return; | |
575 | } | |
576 | ||
dc8cfa55 | 577 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
578 | efx->n_link_state_changes++; |
579 | ||
580 | if (efx->link_up) | |
581 | netif_carrier_on(efx->net_dev); | |
582 | else | |
583 | netif_carrier_off(efx->net_dev); | |
584 | } | |
585 | ||
586 | /* Status message for kernel log */ | |
587 | if (efx->link_up) { | |
f31a45d2 BH |
588 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
589 | efx->link_speed, efx->link_fd ? "full" : "half", | |
8ceee660 BH |
590 | efx->net_dev->mtu, |
591 | (efx->promiscuous ? " [PROMISC]" : "")); | |
592 | } else { | |
593 | EFX_INFO(efx, "link down\n"); | |
594 | } | |
595 | ||
596 | } | |
597 | ||
115122af BH |
598 | static void efx_fini_port(struct efx_nic *efx); |
599 | ||
8ceee660 BH |
600 | /* This call reinitialises the MAC to pick up new PHY settings. The |
601 | * caller must hold the mac_lock */ | |
8c8661e4 | 602 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
603 | { |
604 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
605 | ||
606 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
607 | raw_smp_processor_id()); | |
608 | ||
a816f75a BH |
609 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
610 | if (efx_dev_registered(efx)) { | |
611 | netif_addr_lock_bh(efx->net_dev); | |
612 | netif_addr_unlock_bh(efx->net_dev); | |
613 | } | |
614 | ||
177dfcd8 BH |
615 | falcon_deconfigure_mac_wrapper(efx); |
616 | ||
617 | /* Reconfigure the PHY, disabling transmit in mac level loopback. */ | |
618 | if (LOOPBACK_INTERNAL(efx)) | |
619 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
620 | else | |
621 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
622 | efx->phy_op->reconfigure(efx); | |
623 | ||
624 | if (falcon_switch_mac(efx)) | |
625 | goto fail; | |
626 | ||
627 | efx->mac_op->reconfigure(efx); | |
8ceee660 BH |
628 | |
629 | /* Inform kernel of loss/gain of carrier */ | |
630 | efx_link_status_changed(efx); | |
177dfcd8 BH |
631 | return; |
632 | ||
633 | fail: | |
634 | EFX_ERR(efx, "failed to reconfigure MAC\n"); | |
115122af BH |
635 | efx->port_enabled = false; |
636 | efx_fini_port(efx); | |
8ceee660 BH |
637 | } |
638 | ||
639 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
640 | * disabled. */ | |
641 | void efx_reconfigure_port(struct efx_nic *efx) | |
642 | { | |
643 | EFX_ASSERT_RESET_SERIALISED(efx); | |
644 | ||
645 | mutex_lock(&efx->mac_lock); | |
646 | __efx_reconfigure_port(efx); | |
647 | mutex_unlock(&efx->mac_lock); | |
648 | } | |
649 | ||
650 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
651 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
652 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
766ca0fa | 653 | static void efx_phy_work(struct work_struct *data) |
8ceee660 | 654 | { |
766ca0fa | 655 | struct efx_nic *efx = container_of(data, struct efx_nic, phy_work); |
8ceee660 BH |
656 | |
657 | mutex_lock(&efx->mac_lock); | |
658 | if (efx->port_enabled) | |
659 | __efx_reconfigure_port(efx); | |
660 | mutex_unlock(&efx->mac_lock); | |
661 | } | |
662 | ||
766ca0fa BH |
663 | static void efx_mac_work(struct work_struct *data) |
664 | { | |
665 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
666 | ||
667 | mutex_lock(&efx->mac_lock); | |
668 | if (efx->port_enabled) | |
669 | efx->mac_op->irq(efx); | |
670 | mutex_unlock(&efx->mac_lock); | |
671 | } | |
672 | ||
8ceee660 BH |
673 | static int efx_probe_port(struct efx_nic *efx) |
674 | { | |
675 | int rc; | |
676 | ||
677 | EFX_LOG(efx, "create port\n"); | |
678 | ||
679 | /* Connect up MAC/PHY operations table and read MAC address */ | |
680 | rc = falcon_probe_port(efx); | |
681 | if (rc) | |
682 | goto err; | |
683 | ||
84ae48fe BH |
684 | if (phy_flash_cfg) |
685 | efx->phy_mode = PHY_MODE_SPECIAL; | |
686 | ||
8ceee660 BH |
687 | /* Sanity check MAC address */ |
688 | if (is_valid_ether_addr(efx->mac_address)) { | |
689 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
690 | } else { | |
e174961c JB |
691 | EFX_ERR(efx, "invalid MAC address %pM\n", |
692 | efx->mac_address); | |
8ceee660 BH |
693 | if (!allow_bad_hwaddr) { |
694 | rc = -EINVAL; | |
695 | goto err; | |
696 | } | |
697 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
698 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
699 | efx->net_dev->dev_addr); | |
8ceee660 BH |
700 | } |
701 | ||
702 | return 0; | |
703 | ||
704 | err: | |
705 | efx_remove_port(efx); | |
706 | return rc; | |
707 | } | |
708 | ||
709 | static int efx_init_port(struct efx_nic *efx) | |
710 | { | |
711 | int rc; | |
712 | ||
713 | EFX_LOG(efx, "init port\n"); | |
714 | ||
177dfcd8 | 715 | rc = efx->phy_op->init(efx); |
8ceee660 BH |
716 | if (rc) |
717 | return rc; | |
177dfcd8 | 718 | mutex_lock(&efx->mac_lock); |
4b988280 | 719 | efx->phy_op->reconfigure(efx); |
177dfcd8 BH |
720 | rc = falcon_switch_mac(efx); |
721 | mutex_unlock(&efx->mac_lock); | |
722 | if (rc) | |
723 | goto fail; | |
724 | efx->mac_op->reconfigure(efx); | |
8ceee660 | 725 | |
dc8cfa55 | 726 | efx->port_initialized = true; |
1974cc20 | 727 | efx_stats_enable(efx); |
8ceee660 | 728 | return 0; |
177dfcd8 BH |
729 | |
730 | fail: | |
731 | efx->phy_op->fini(efx); | |
732 | return rc; | |
8ceee660 BH |
733 | } |
734 | ||
735 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
736 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
766ca0fa | 737 | * efx_phy_work()/efx_mac_work() may have been cancelled */ |
8ceee660 BH |
738 | static void efx_start_port(struct efx_nic *efx) |
739 | { | |
740 | EFX_LOG(efx, "start port\n"); | |
741 | BUG_ON(efx->port_enabled); | |
742 | ||
743 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 744 | efx->port_enabled = true; |
8ceee660 | 745 | __efx_reconfigure_port(efx); |
766ca0fa | 746 | efx->mac_op->irq(efx); |
8ceee660 BH |
747 | mutex_unlock(&efx->mac_lock); |
748 | } | |
749 | ||
766ca0fa BH |
750 | /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing, |
751 | * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work | |
752 | * and efx_mac_work may still be scheduled via NAPI processing until | |
753 | * efx_flush_all() is called */ | |
8ceee660 BH |
754 | static void efx_stop_port(struct efx_nic *efx) |
755 | { | |
756 | EFX_LOG(efx, "stop port\n"); | |
757 | ||
758 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 759 | efx->port_enabled = false; |
8ceee660 BH |
760 | mutex_unlock(&efx->mac_lock); |
761 | ||
762 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 763 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
764 | netif_addr_lock_bh(efx->net_dev); |
765 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
766 | } |
767 | } | |
768 | ||
769 | static void efx_fini_port(struct efx_nic *efx) | |
770 | { | |
771 | EFX_LOG(efx, "shut down port\n"); | |
772 | ||
773 | if (!efx->port_initialized) | |
774 | return; | |
775 | ||
1974cc20 | 776 | efx_stats_disable(efx); |
177dfcd8 | 777 | efx->phy_op->fini(efx); |
dc8cfa55 | 778 | efx->port_initialized = false; |
8ceee660 | 779 | |
dc8cfa55 | 780 | efx->link_up = false; |
8ceee660 BH |
781 | efx_link_status_changed(efx); |
782 | } | |
783 | ||
784 | static void efx_remove_port(struct efx_nic *efx) | |
785 | { | |
786 | EFX_LOG(efx, "destroying port\n"); | |
787 | ||
788 | falcon_remove_port(efx); | |
789 | } | |
790 | ||
791 | /************************************************************************** | |
792 | * | |
793 | * NIC handling | |
794 | * | |
795 | **************************************************************************/ | |
796 | ||
797 | /* This configures the PCI device to enable I/O and DMA. */ | |
798 | static int efx_init_io(struct efx_nic *efx) | |
799 | { | |
800 | struct pci_dev *pci_dev = efx->pci_dev; | |
801 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
802 | int rc; | |
803 | ||
804 | EFX_LOG(efx, "initialising I/O\n"); | |
805 | ||
806 | rc = pci_enable_device(pci_dev); | |
807 | if (rc) { | |
808 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
809 | goto fail1; | |
810 | } | |
811 | ||
812 | pci_set_master(pci_dev); | |
813 | ||
814 | /* Set the PCI DMA mask. Try all possibilities from our | |
815 | * genuine mask down to 32 bits, because some architectures | |
816 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
817 | * masks event though they reject 46 bit masks. | |
818 | */ | |
819 | while (dma_mask > 0x7fffffffUL) { | |
820 | if (pci_dma_supported(pci_dev, dma_mask) && | |
821 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
822 | break; | |
823 | dma_mask >>= 1; | |
824 | } | |
825 | if (rc) { | |
826 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
827 | goto fail2; | |
828 | } | |
829 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
830 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
831 | if (rc) { | |
832 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
833 | * fail with a mask that pci_set_dma_mask() accepted, | |
834 | * but just in case... | |
835 | */ | |
836 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
837 | goto fail2; | |
838 | } | |
839 | ||
840 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
841 | efx->type->mem_bar); | |
842 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
843 | if (rc) { | |
844 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
845 | rc = -EIO; | |
846 | goto fail3; | |
847 | } | |
848 | efx->membase = ioremap_nocache(efx->membase_phys, | |
849 | efx->type->mem_map_size); | |
850 | if (!efx->membase) { | |
086ea356 BH |
851 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
852 | efx->type->mem_bar, | |
853 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
854 | efx->type->mem_map_size); |
855 | rc = -ENOMEM; | |
856 | goto fail4; | |
857 | } | |
086ea356 BH |
858 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
859 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
860 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
861 | |
862 | return 0; | |
863 | ||
864 | fail4: | |
e1074a0d | 865 | pci_release_region(efx->pci_dev, efx->type->mem_bar); |
8ceee660 | 866 | fail3: |
2c118e0f | 867 | efx->membase_phys = 0; |
8ceee660 BH |
868 | fail2: |
869 | pci_disable_device(efx->pci_dev); | |
870 | fail1: | |
871 | return rc; | |
872 | } | |
873 | ||
874 | static void efx_fini_io(struct efx_nic *efx) | |
875 | { | |
876 | EFX_LOG(efx, "shutting down I/O\n"); | |
877 | ||
878 | if (efx->membase) { | |
879 | iounmap(efx->membase); | |
880 | efx->membase = NULL; | |
881 | } | |
882 | ||
883 | if (efx->membase_phys) { | |
884 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 885 | efx->membase_phys = 0; |
8ceee660 BH |
886 | } |
887 | ||
888 | pci_disable_device(efx->pci_dev); | |
889 | } | |
890 | ||
46123d04 BH |
891 | /* Get number of RX queues wanted. Return number of online CPU |
892 | * packages in the expectation that an IRQ balancer will spread | |
893 | * interrupts across them. */ | |
894 | static int efx_wanted_rx_queues(void) | |
895 | { | |
2f8975fb | 896 | cpumask_var_t core_mask; |
46123d04 BH |
897 | int count; |
898 | int cpu; | |
899 | ||
2f8975fb RR |
900 | if (!alloc_cpumask_var(&core_mask, GFP_KERNEL)) { |
901 | printk(KERN_WARNING | |
902 | "efx.c: allocation failure, irq balancing hobbled\n"); | |
903 | return 1; | |
904 | } | |
905 | ||
906 | cpumask_clear(core_mask); | |
46123d04 BH |
907 | count = 0; |
908 | for_each_online_cpu(cpu) { | |
2f8975fb | 909 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 910 | ++count; |
2f8975fb | 911 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 912 | topology_core_cpumask(cpu)); |
46123d04 BH |
913 | } |
914 | } | |
915 | ||
2f8975fb | 916 | free_cpumask_var(core_mask); |
46123d04 BH |
917 | return count; |
918 | } | |
919 | ||
920 | /* Probe the number and type of interrupts we are able to obtain, and | |
921 | * the resulting numbers of channels and RX queues. | |
922 | */ | |
8ceee660 BH |
923 | static void efx_probe_interrupts(struct efx_nic *efx) |
924 | { | |
46123d04 BH |
925 | int max_channels = |
926 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
927 | int rc, i; |
928 | ||
929 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
930 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
931 | int wanted_ints; | |
28b581ab | 932 | int rx_queues; |
aa6ef27e | 933 | |
46123d04 BH |
934 | /* We want one RX queue and interrupt per CPU package |
935 | * (or as specified by the rss_cpus module parameter). | |
936 | * We will need one channel per interrupt. | |
937 | */ | |
28b581ab NT |
938 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
939 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
940 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 941 | |
28b581ab | 942 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 943 | xentries[i].entry = i; |
28b581ab | 944 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 945 | if (rc > 0) { |
28b581ab NT |
946 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
947 | " available (%d < %d).\n", rc, wanted_ints); | |
948 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
949 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
950 | wanted_ints = rc; | |
8ceee660 | 951 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 952 | wanted_ints); |
8ceee660 BH |
953 | } |
954 | ||
955 | if (rc == 0) { | |
28b581ab NT |
956 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
957 | efx->n_channels = wanted_ints; | |
958 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 959 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
960 | } else { |
961 | /* Fall back to single channel MSI */ | |
962 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
963 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
964 | } | |
965 | } | |
966 | ||
967 | /* Try single interrupt MSI */ | |
968 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 969 | efx->n_rx_queues = 1; |
28b581ab | 970 | efx->n_channels = 1; |
8ceee660 BH |
971 | rc = pci_enable_msi(efx->pci_dev); |
972 | if (rc == 0) { | |
973 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
974 | } else { |
975 | EFX_ERR(efx, "could not enable MSI\n"); | |
976 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
977 | } | |
978 | } | |
979 | ||
980 | /* Assume legacy interrupts */ | |
981 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 982 | efx->n_rx_queues = 1; |
28b581ab | 983 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
984 | efx->legacy_irq = efx->pci_dev->irq; |
985 | } | |
986 | } | |
987 | ||
988 | static void efx_remove_interrupts(struct efx_nic *efx) | |
989 | { | |
990 | struct efx_channel *channel; | |
991 | ||
992 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 993 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
994 | channel->irq = 0; |
995 | pci_disable_msi(efx->pci_dev); | |
996 | pci_disable_msix(efx->pci_dev); | |
997 | ||
998 | /* Remove legacy interrupt */ | |
999 | efx->legacy_irq = 0; | |
1000 | } | |
1001 | ||
8831da7b | 1002 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
1003 | { |
1004 | struct efx_tx_queue *tx_queue; | |
1005 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 1006 | |
60ac1065 | 1007 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
1008 | if (separate_tx_channels) |
1009 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
1010 | else |
1011 | tx_queue->channel = &efx->channel[0]; | |
1012 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
1013 | } | |
8ceee660 | 1014 | |
8831da7b BH |
1015 | efx_for_each_rx_queue(rx_queue, efx) { |
1016 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
1017 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
1018 | } |
1019 | } | |
1020 | ||
1021 | static int efx_probe_nic(struct efx_nic *efx) | |
1022 | { | |
1023 | int rc; | |
1024 | ||
1025 | EFX_LOG(efx, "creating NIC\n"); | |
1026 | ||
1027 | /* Carry out hardware-type specific initialisation */ | |
1028 | rc = falcon_probe_nic(efx); | |
1029 | if (rc) | |
1030 | return rc; | |
1031 | ||
1032 | /* Determine the number of channels and RX queues by trying to hook | |
1033 | * in MSI-X interrupts. */ | |
1034 | efx_probe_interrupts(efx); | |
1035 | ||
8831da7b | 1036 | efx_set_channels(efx); |
8ceee660 BH |
1037 | |
1038 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1039 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1040 | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static void efx_remove_nic(struct efx_nic *efx) | |
1045 | { | |
1046 | EFX_LOG(efx, "destroying NIC\n"); | |
1047 | ||
1048 | efx_remove_interrupts(efx); | |
1049 | falcon_remove_nic(efx); | |
1050 | } | |
1051 | ||
1052 | /************************************************************************** | |
1053 | * | |
1054 | * NIC startup/shutdown | |
1055 | * | |
1056 | *************************************************************************/ | |
1057 | ||
1058 | static int efx_probe_all(struct efx_nic *efx) | |
1059 | { | |
1060 | struct efx_channel *channel; | |
1061 | int rc; | |
1062 | ||
1063 | /* Create NIC */ | |
1064 | rc = efx_probe_nic(efx); | |
1065 | if (rc) { | |
1066 | EFX_ERR(efx, "failed to create NIC\n"); | |
1067 | goto fail1; | |
1068 | } | |
1069 | ||
1070 | /* Create port */ | |
1071 | rc = efx_probe_port(efx); | |
1072 | if (rc) { | |
1073 | EFX_ERR(efx, "failed to create port\n"); | |
1074 | goto fail2; | |
1075 | } | |
1076 | ||
1077 | /* Create channels */ | |
1078 | efx_for_each_channel(channel, efx) { | |
1079 | rc = efx_probe_channel(channel); | |
1080 | if (rc) { | |
1081 | EFX_ERR(efx, "failed to create channel %d\n", | |
1082 | channel->channel); | |
1083 | goto fail3; | |
1084 | } | |
1085 | } | |
56536e9c | 1086 | efx_set_channel_names(efx); |
8ceee660 BH |
1087 | |
1088 | return 0; | |
1089 | ||
1090 | fail3: | |
1091 | efx_for_each_channel(channel, efx) | |
1092 | efx_remove_channel(channel); | |
1093 | efx_remove_port(efx); | |
1094 | fail2: | |
1095 | efx_remove_nic(efx); | |
1096 | fail1: | |
1097 | return rc; | |
1098 | } | |
1099 | ||
1100 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1101 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1102 | * and ensures that the port is scheduled to be reconfigured. | |
1103 | * This function is safe to call multiple times when the NIC is in any | |
1104 | * state. */ | |
1105 | static void efx_start_all(struct efx_nic *efx) | |
1106 | { | |
1107 | struct efx_channel *channel; | |
1108 | ||
1109 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1110 | ||
1111 | /* Check that it is appropriate to restart the interface. All | |
1112 | * of these flags are safe to read under just the rtnl lock */ | |
1113 | if (efx->port_enabled) | |
1114 | return; | |
1115 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1116 | return; | |
55668611 | 1117 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1118 | return; |
1119 | ||
1120 | /* Mark the port as enabled so port reconfigurations can start, then | |
1121 | * restart the transmit interface early so the watchdog timer stops */ | |
1122 | efx_start_port(efx); | |
dacccc74 SH |
1123 | if (efx_dev_registered(efx)) |
1124 | efx_wake_queue(efx); | |
8ceee660 BH |
1125 | |
1126 | efx_for_each_channel(channel, efx) | |
1127 | efx_start_channel(channel); | |
1128 | ||
1129 | falcon_enable_interrupts(efx); | |
1130 | ||
1131 | /* Start hardware monitor if we're in RUNNING */ | |
1132 | if (efx->state == STATE_RUNNING) | |
1133 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1134 | efx_monitor_interval); | |
1135 | } | |
1136 | ||
1137 | /* Flush all delayed work. Should only be called when no more delayed work | |
1138 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1139 | * since we're holding the rtnl_lock at this point. */ | |
1140 | static void efx_flush_all(struct efx_nic *efx) | |
1141 | { | |
1142 | struct efx_rx_queue *rx_queue; | |
1143 | ||
1144 | /* Make sure the hardware monitor is stopped */ | |
1145 | cancel_delayed_work_sync(&efx->monitor_work); | |
1146 | ||
1147 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1148 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1149 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1150 | |
1151 | /* Stop scheduled port reconfigurations */ | |
766ca0fa BH |
1152 | cancel_work_sync(&efx->mac_work); |
1153 | cancel_work_sync(&efx->phy_work); | |
8ceee660 BH |
1154 | |
1155 | } | |
1156 | ||
1157 | /* Quiesce hardware and software without bringing the link down. | |
1158 | * Safe to call multiple times, when the nic and interface is in any | |
1159 | * state. The caller is guaranteed to subsequently be in a position | |
1160 | * to modify any hardware and software state they see fit without | |
1161 | * taking locks. */ | |
1162 | static void efx_stop_all(struct efx_nic *efx) | |
1163 | { | |
1164 | struct efx_channel *channel; | |
1165 | ||
1166 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1167 | ||
1168 | /* port_enabled can be read safely under the rtnl lock */ | |
1169 | if (!efx->port_enabled) | |
1170 | return; | |
1171 | ||
1172 | /* Disable interrupts and wait for ISR to complete */ | |
1173 | falcon_disable_interrupts(efx); | |
1174 | if (efx->legacy_irq) | |
1175 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1176 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1177 | if (channel->irq) |
1178 | synchronize_irq(channel->irq); | |
b3475645 | 1179 | } |
8ceee660 BH |
1180 | |
1181 | /* Stop all NAPI processing and synchronous rx refills */ | |
1182 | efx_for_each_channel(channel, efx) | |
1183 | efx_stop_channel(channel); | |
1184 | ||
1185 | /* Stop all asynchronous port reconfigurations. Since all | |
1186 | * event processing has already been stopped, there is no | |
1187 | * window to loose phy events */ | |
1188 | efx_stop_port(efx); | |
1189 | ||
766ca0fa | 1190 | /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */ |
8ceee660 BH |
1191 | efx_flush_all(efx); |
1192 | ||
1193 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1194 | * flushes will complete in a timely fashion. */ | |
8ceee660 BH |
1195 | falcon_drain_tx_fifo(efx); |
1196 | ||
1197 | /* Stop the kernel transmit interface late, so the watchdog | |
1198 | * timer isn't ticking over the flush */ | |
55668611 | 1199 | if (efx_dev_registered(efx)) { |
dacccc74 | 1200 | efx_stop_queue(efx); |
8ceee660 BH |
1201 | netif_tx_lock_bh(efx->net_dev); |
1202 | netif_tx_unlock_bh(efx->net_dev); | |
1203 | } | |
1204 | } | |
1205 | ||
1206 | static void efx_remove_all(struct efx_nic *efx) | |
1207 | { | |
1208 | struct efx_channel *channel; | |
1209 | ||
1210 | efx_for_each_channel(channel, efx) | |
1211 | efx_remove_channel(channel); | |
1212 | efx_remove_port(efx); | |
1213 | efx_remove_nic(efx); | |
1214 | } | |
1215 | ||
1216 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1217 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1218 | { |
8ceee660 BH |
1219 | EFX_ASSERT_RESET_SERIALISED(efx); |
1220 | ||
1221 | efx_stop_all(efx); | |
1222 | ||
1223 | efx_fini_channels(efx); | |
bc3c90a2 | 1224 | efx_init_channels(efx); |
8ceee660 BH |
1225 | |
1226 | efx_start_all(efx); | |
8ceee660 BH |
1227 | } |
1228 | ||
1229 | /************************************************************************** | |
1230 | * | |
1231 | * Interrupt moderation | |
1232 | * | |
1233 | **************************************************************************/ | |
1234 | ||
1235 | /* Set interrupt moderation parameters */ | |
6fb70fd1 BH |
1236 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1237 | bool rx_adaptive) | |
8ceee660 BH |
1238 | { |
1239 | struct efx_tx_queue *tx_queue; | |
1240 | struct efx_rx_queue *rx_queue; | |
1241 | ||
1242 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1243 | ||
1244 | efx_for_each_tx_queue(tx_queue, efx) | |
1245 | tx_queue->channel->irq_moderation = tx_usecs; | |
1246 | ||
6fb70fd1 BH |
1247 | efx->irq_rx_adaptive = rx_adaptive; |
1248 | efx->irq_rx_moderation = rx_usecs; | |
8ceee660 BH |
1249 | efx_for_each_rx_queue(rx_queue, efx) |
1250 | rx_queue->channel->irq_moderation = rx_usecs; | |
1251 | } | |
1252 | ||
1253 | /************************************************************************** | |
1254 | * | |
1255 | * Hardware monitor | |
1256 | * | |
1257 | **************************************************************************/ | |
1258 | ||
1259 | /* Run periodically off the general workqueue. Serialised against | |
1260 | * efx_reconfigure_port via the mac_lock */ | |
1261 | static void efx_monitor(struct work_struct *data) | |
1262 | { | |
1263 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1264 | monitor_work.work); | |
766ca0fa | 1265 | int rc; |
8ceee660 BH |
1266 | |
1267 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1268 | raw_smp_processor_id()); | |
1269 | ||
8ceee660 BH |
1270 | /* If the mac_lock is already held then it is likely a port |
1271 | * reconfiguration is already in place, which will likely do | |
1272 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1273 | if (!mutex_trylock(&efx->mac_lock)) |
1274 | goto out_requeue; | |
1275 | if (!efx->port_enabled) | |
1276 | goto out_unlock; | |
1277 | rc = efx->board_info.monitor(efx); | |
1278 | if (rc) { | |
1279 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
1280 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
1281 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
1282 | falcon_sim_phy_event(efx); | |
8ceee660 | 1283 | } |
766ca0fa BH |
1284 | efx->phy_op->poll(efx); |
1285 | efx->mac_op->poll(efx); | |
8ceee660 | 1286 | |
766ca0fa | 1287 | out_unlock: |
8ceee660 | 1288 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1289 | out_requeue: |
8ceee660 BH |
1290 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1291 | efx_monitor_interval); | |
1292 | } | |
1293 | ||
1294 | /************************************************************************** | |
1295 | * | |
1296 | * ioctls | |
1297 | * | |
1298 | *************************************************************************/ | |
1299 | ||
1300 | /* Net device ioctl | |
1301 | * Context: process, rtnl_lock() held. | |
1302 | */ | |
1303 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1304 | { | |
767e468c | 1305 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1306 | |
1307 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1308 | ||
1309 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1310 | } | |
1311 | ||
1312 | /************************************************************************** | |
1313 | * | |
1314 | * NAPI interface | |
1315 | * | |
1316 | **************************************************************************/ | |
1317 | ||
1318 | static int efx_init_napi(struct efx_nic *efx) | |
1319 | { | |
1320 | struct efx_channel *channel; | |
8ceee660 BH |
1321 | |
1322 | efx_for_each_channel(channel, efx) { | |
1323 | channel->napi_dev = efx->net_dev; | |
8ceee660 BH |
1324 | } |
1325 | return 0; | |
8ceee660 BH |
1326 | } |
1327 | ||
1328 | static void efx_fini_napi(struct efx_nic *efx) | |
1329 | { | |
1330 | struct efx_channel *channel; | |
1331 | ||
1332 | efx_for_each_channel(channel, efx) { | |
8ceee660 BH |
1333 | channel->napi_dev = NULL; |
1334 | } | |
1335 | } | |
1336 | ||
1337 | /************************************************************************** | |
1338 | * | |
1339 | * Kernel netpoll interface | |
1340 | * | |
1341 | *************************************************************************/ | |
1342 | ||
1343 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1344 | ||
1345 | /* Although in the common case interrupts will be disabled, this is not | |
1346 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1347 | * so no locking is required. | |
1348 | */ | |
1349 | static void efx_netpoll(struct net_device *net_dev) | |
1350 | { | |
767e468c | 1351 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1352 | struct efx_channel *channel; |
1353 | ||
64ee3120 | 1354 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1355 | efx_schedule_channel(channel); |
1356 | } | |
1357 | ||
1358 | #endif | |
1359 | ||
1360 | /************************************************************************** | |
1361 | * | |
1362 | * Kernel net device interface | |
1363 | * | |
1364 | *************************************************************************/ | |
1365 | ||
1366 | /* Context: process, rtnl_lock() held. */ | |
1367 | static int efx_net_open(struct net_device *net_dev) | |
1368 | { | |
767e468c | 1369 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1370 | EFX_ASSERT_RESET_SERIALISED(efx); |
1371 | ||
1372 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1373 | raw_smp_processor_id()); | |
1374 | ||
f4bd954e BH |
1375 | if (efx->state == STATE_DISABLED) |
1376 | return -EIO; | |
f8b87c17 BH |
1377 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1378 | return -EBUSY; | |
1379 | ||
8ceee660 BH |
1380 | efx_start_all(efx); |
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | /* Context: process, rtnl_lock() held. | |
1385 | * Note that the kernel will ignore our return code; this method | |
1386 | * should really be a void. | |
1387 | */ | |
1388 | static int efx_net_stop(struct net_device *net_dev) | |
1389 | { | |
767e468c | 1390 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1391 | |
1392 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1393 | raw_smp_processor_id()); | |
1394 | ||
f4bd954e BH |
1395 | if (efx->state != STATE_DISABLED) { |
1396 | /* Stop the device and flush all the channels */ | |
1397 | efx_stop_all(efx); | |
1398 | efx_fini_channels(efx); | |
1399 | efx_init_channels(efx); | |
1400 | } | |
8ceee660 BH |
1401 | |
1402 | return 0; | |
1403 | } | |
1404 | ||
1974cc20 BH |
1405 | void efx_stats_disable(struct efx_nic *efx) |
1406 | { | |
1407 | spin_lock(&efx->stats_lock); | |
1408 | ++efx->stats_disable_count; | |
1409 | spin_unlock(&efx->stats_lock); | |
1410 | } | |
1411 | ||
1412 | void efx_stats_enable(struct efx_nic *efx) | |
1413 | { | |
1414 | spin_lock(&efx->stats_lock); | |
1415 | --efx->stats_disable_count; | |
1416 | spin_unlock(&efx->stats_lock); | |
1417 | } | |
1418 | ||
5b9e207c | 1419 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1420 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1421 | { | |
767e468c | 1422 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1423 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1424 | struct net_device_stats *stats = &net_dev->stats; | |
1425 | ||
5b9e207c | 1426 | /* Update stats if possible, but do not wait if another thread |
1974cc20 BH |
1427 | * is updating them or if MAC stats fetches are temporarily |
1428 | * disabled; slightly stale stats are acceptable. | |
5b9e207c | 1429 | */ |
8ceee660 BH |
1430 | if (!spin_trylock(&efx->stats_lock)) |
1431 | return stats; | |
1974cc20 | 1432 | if (!efx->stats_disable_count) { |
177dfcd8 | 1433 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1434 | falcon_update_nic_stats(efx); |
1435 | } | |
1436 | spin_unlock(&efx->stats_lock); | |
1437 | ||
1438 | stats->rx_packets = mac_stats->rx_packets; | |
1439 | stats->tx_packets = mac_stats->tx_packets; | |
1440 | stats->rx_bytes = mac_stats->rx_bytes; | |
1441 | stats->tx_bytes = mac_stats->tx_bytes; | |
1442 | stats->multicast = mac_stats->rx_multicast; | |
1443 | stats->collisions = mac_stats->tx_collision; | |
1444 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1445 | mac_stats->rx_length_error); | |
1446 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1447 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1448 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1449 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1450 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1451 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1452 | ||
1453 | stats->rx_errors = (stats->rx_length_errors + | |
1454 | stats->rx_over_errors + | |
1455 | stats->rx_crc_errors + | |
1456 | stats->rx_frame_errors + | |
1457 | stats->rx_fifo_errors + | |
1458 | stats->rx_missed_errors + | |
1459 | mac_stats->rx_symbol_error); | |
1460 | stats->tx_errors = (stats->tx_window_errors + | |
1461 | mac_stats->tx_bad); | |
1462 | ||
1463 | return stats; | |
1464 | } | |
1465 | ||
1466 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1467 | static void efx_watchdog(struct net_device *net_dev) | |
1468 | { | |
767e468c | 1469 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1470 | |
739bb23d BH |
1471 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1472 | " resetting channels\n", | |
1473 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1474 | |
739bb23d | 1475 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1476 | } |
1477 | ||
1478 | ||
1479 | /* Context: process, rtnl_lock() held. */ | |
1480 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1481 | { | |
767e468c | 1482 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1483 | int rc = 0; |
1484 | ||
1485 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1486 | ||
1487 | if (new_mtu > EFX_MAX_MTU) | |
1488 | return -EINVAL; | |
1489 | ||
1490 | efx_stop_all(efx); | |
1491 | ||
1492 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1493 | ||
1494 | efx_fini_channels(efx); | |
1495 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1496 | efx_init_channels(efx); |
8ceee660 BH |
1497 | |
1498 | efx_start_all(efx); | |
1499 | return rc; | |
8ceee660 BH |
1500 | } |
1501 | ||
1502 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1503 | { | |
767e468c | 1504 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1505 | struct sockaddr *addr = data; |
1506 | char *new_addr = addr->sa_data; | |
1507 | ||
1508 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1509 | ||
1510 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1511 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1512 | new_addr); | |
8ceee660 BH |
1513 | return -EINVAL; |
1514 | } | |
1515 | ||
1516 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1517 | ||
1518 | /* Reconfigure the MAC */ | |
1519 | efx_reconfigure_port(efx); | |
1520 | ||
1521 | return 0; | |
1522 | } | |
1523 | ||
a816f75a | 1524 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1525 | static void efx_set_multicast_list(struct net_device *net_dev) |
1526 | { | |
767e468c | 1527 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1528 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1529 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1530 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1531 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1532 | u32 crc; |
1533 | int bit; | |
1534 | int i; | |
1535 | ||
a816f75a | 1536 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1537 | |
1538 | /* Build multicast hash table */ | |
1539 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1540 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1541 | } else { | |
1542 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1543 | for (i = 0; i < net_dev->mc_count; i++) { | |
1544 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1545 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1546 | set_bit_le(bit, mc_hash->byte); | |
1547 | mc_list = mc_list->next; | |
1548 | } | |
1549 | } | |
1550 | ||
a816f75a BH |
1551 | if (!efx->port_enabled) |
1552 | /* Delay pushing settings until efx_start_port() */ | |
1553 | return; | |
1554 | ||
1555 | if (changed) | |
766ca0fa | 1556 | queue_work(efx->workqueue, &efx->phy_work); |
a816f75a | 1557 | |
8ceee660 BH |
1558 | /* Create and activate new global multicast hash table */ |
1559 | falcon_set_multicast_hash(efx); | |
1560 | } | |
1561 | ||
c3ecb9f3 SH |
1562 | static const struct net_device_ops efx_netdev_ops = { |
1563 | .ndo_open = efx_net_open, | |
1564 | .ndo_stop = efx_net_stop, | |
1565 | .ndo_get_stats = efx_net_stats, | |
1566 | .ndo_tx_timeout = efx_watchdog, | |
1567 | .ndo_start_xmit = efx_hard_start_xmit, | |
1568 | .ndo_validate_addr = eth_validate_addr, | |
1569 | .ndo_do_ioctl = efx_ioctl, | |
1570 | .ndo_change_mtu = efx_change_mtu, | |
1571 | .ndo_set_mac_address = efx_set_mac_address, | |
1572 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1573 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1574 | .ndo_poll_controller = efx_netpoll, | |
1575 | #endif | |
1576 | }; | |
1577 | ||
7dde596e BH |
1578 | static void efx_update_name(struct efx_nic *efx) |
1579 | { | |
1580 | strcpy(efx->name, efx->net_dev->name); | |
1581 | efx_mtd_rename(efx); | |
1582 | efx_set_channel_names(efx); | |
1583 | } | |
1584 | ||
8ceee660 BH |
1585 | static int efx_netdev_event(struct notifier_block *this, |
1586 | unsigned long event, void *ptr) | |
1587 | { | |
d3208b5e | 1588 | struct net_device *net_dev = ptr; |
8ceee660 | 1589 | |
7dde596e BH |
1590 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1591 | event == NETDEV_CHANGENAME) | |
1592 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1593 | |
1594 | return NOTIFY_DONE; | |
1595 | } | |
1596 | ||
1597 | static struct notifier_block efx_netdev_notifier = { | |
1598 | .notifier_call = efx_netdev_event, | |
1599 | }; | |
1600 | ||
06d5e193 BH |
1601 | static ssize_t |
1602 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1603 | { | |
1604 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1605 | return sprintf(buf, "%d\n", efx->phy_type); | |
1606 | } | |
1607 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1608 | ||
8ceee660 BH |
1609 | static int efx_register_netdev(struct efx_nic *efx) |
1610 | { | |
1611 | struct net_device *net_dev = efx->net_dev; | |
1612 | int rc; | |
1613 | ||
1614 | net_dev->watchdog_timeo = 5 * HZ; | |
1615 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1616 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1617 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1618 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1619 | ||
1620 | /* Always start with carrier off; PHY events will detect the link */ | |
1621 | netif_carrier_off(efx->net_dev); | |
1622 | ||
1623 | /* Clear MAC statistics */ | |
177dfcd8 | 1624 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1625 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1626 | ||
1627 | rc = register_netdev(net_dev); | |
1628 | if (rc) { | |
1629 | EFX_ERR(efx, "could not register net dev\n"); | |
1630 | return rc; | |
1631 | } | |
7dde596e BH |
1632 | |
1633 | rtnl_lock(); | |
1634 | efx_update_name(efx); | |
1635 | rtnl_unlock(); | |
8ceee660 | 1636 | |
06d5e193 BH |
1637 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1638 | if (rc) { | |
1639 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1640 | goto fail_registered; | |
1641 | } | |
1642 | ||
8ceee660 | 1643 | return 0; |
06d5e193 BH |
1644 | |
1645 | fail_registered: | |
1646 | unregister_netdev(net_dev); | |
1647 | return rc; | |
8ceee660 BH |
1648 | } |
1649 | ||
1650 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1651 | { | |
1652 | struct efx_tx_queue *tx_queue; | |
1653 | ||
1654 | if (!efx->net_dev) | |
1655 | return; | |
1656 | ||
767e468c | 1657 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1658 | |
1659 | /* Free up any skbs still remaining. This has to happen before | |
1660 | * we try to unregister the netdev as running their destructors | |
1661 | * may be needed to get the device ref. count to 0. */ | |
1662 | efx_for_each_tx_queue(tx_queue, efx) | |
1663 | efx_release_tx_buffers(tx_queue); | |
1664 | ||
55668611 | 1665 | if (efx_dev_registered(efx)) { |
8ceee660 | 1666 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1667 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1668 | unregister_netdev(efx->net_dev); |
1669 | } | |
1670 | } | |
1671 | ||
1672 | /************************************************************************** | |
1673 | * | |
1674 | * Device reset and suspend | |
1675 | * | |
1676 | **************************************************************************/ | |
1677 | ||
2467ca46 BH |
1678 | /* Tears down the entire software state and most of the hardware state |
1679 | * before reset. */ | |
4b988280 SH |
1680 | void efx_reset_down(struct efx_nic *efx, enum reset_type method, |
1681 | struct ethtool_cmd *ecmd) | |
8ceee660 | 1682 | { |
8ceee660 BH |
1683 | EFX_ASSERT_RESET_SERIALISED(efx); |
1684 | ||
1974cc20 | 1685 | efx_stats_disable(efx); |
2467ca46 BH |
1686 | efx_stop_all(efx); |
1687 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1688 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1689 | |
177dfcd8 | 1690 | efx->phy_op->get_settings(efx, ecmd); |
8ceee660 BH |
1691 | |
1692 | efx_fini_channels(efx); | |
4b988280 SH |
1693 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1694 | efx->phy_op->fini(efx); | |
8ceee660 BH |
1695 | } |
1696 | ||
2467ca46 BH |
1697 | /* This function will always ensure that the locks acquired in |
1698 | * efx_reset_down() are released. A failure return code indicates | |
1699 | * that we were unable to reinitialise the hardware, and the | |
1700 | * driver should be disabled. If ok is false, then the rx and tx | |
1701 | * engines are not restarted, pending a RESET_DISABLE. */ | |
4b988280 SH |
1702 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, |
1703 | struct ethtool_cmd *ecmd, bool ok) | |
8ceee660 BH |
1704 | { |
1705 | int rc; | |
1706 | ||
2467ca46 | 1707 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1708 | |
2467ca46 | 1709 | rc = falcon_init_nic(efx); |
8ceee660 | 1710 | if (rc) { |
2467ca46 BH |
1711 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1712 | ok = false; | |
8ceee660 BH |
1713 | } |
1714 | ||
4b988280 SH |
1715 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
1716 | if (ok) { | |
1717 | rc = efx->phy_op->init(efx); | |
1718 | if (rc) | |
1719 | ok = false; | |
115122af BH |
1720 | } |
1721 | if (!ok) | |
4b988280 SH |
1722 | efx->port_initialized = false; |
1723 | } | |
1724 | ||
2467ca46 BH |
1725 | if (ok) { |
1726 | efx_init_channels(efx); | |
8ceee660 | 1727 | |
177dfcd8 | 1728 | if (efx->phy_op->set_settings(efx, ecmd)) |
2467ca46 BH |
1729 | EFX_ERR(efx, "could not restore PHY settings\n"); |
1730 | } | |
1731 | ||
f4150724 | 1732 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1733 | mutex_unlock(&efx->mac_lock); |
1734 | ||
8c8661e4 | 1735 | if (ok) { |
2467ca46 | 1736 | efx_start_all(efx); |
1974cc20 | 1737 | efx_stats_enable(efx); |
8c8661e4 | 1738 | } |
8ceee660 BH |
1739 | return rc; |
1740 | } | |
1741 | ||
1742 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1743 | * Note that the reset may fail, in which case the card will be left | |
1744 | * in a most-probably-unusable state. | |
1745 | * | |
1746 | * This function will sleep. You cannot reset from within an atomic | |
1747 | * state; use efx_schedule_reset() instead. | |
1748 | * | |
1749 | * Grabs the rtnl_lock. | |
1750 | */ | |
1751 | static int efx_reset(struct efx_nic *efx) | |
1752 | { | |
1753 | struct ethtool_cmd ecmd; | |
1754 | enum reset_type method = efx->reset_pending; | |
f4bd954e | 1755 | int rc = 0; |
8ceee660 BH |
1756 | |
1757 | /* Serialise with kernel interfaces */ | |
1758 | rtnl_lock(); | |
1759 | ||
1760 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1761 | * flag set so that efx_pci_probe_main will be retried */ | |
1762 | if (efx->state != STATE_RUNNING) { | |
1763 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
f4bd954e | 1764 | goto out_unlock; |
8ceee660 BH |
1765 | } |
1766 | ||
8ceee660 BH |
1767 | EFX_INFO(efx, "resetting (%d)\n", method); |
1768 | ||
4b988280 | 1769 | efx_reset_down(efx, method, &ecmd); |
8ceee660 BH |
1770 | |
1771 | rc = falcon_reset_hw(efx, method); | |
1772 | if (rc) { | |
1773 | EFX_ERR(efx, "failed to reset hardware\n"); | |
f4bd954e | 1774 | goto out_disable; |
8ceee660 BH |
1775 | } |
1776 | ||
1777 | /* Allow resets to be rescheduled. */ | |
1778 | efx->reset_pending = RESET_TYPE_NONE; | |
1779 | ||
1780 | /* Reinitialise bus-mastering, which may have been turned off before | |
1781 | * the reset was scheduled. This is still appropriate, even in the | |
1782 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1783 | * can respond to requests. */ | |
1784 | pci_set_master(efx->pci_dev); | |
1785 | ||
8ceee660 BH |
1786 | /* Leave device stopped if necessary */ |
1787 | if (method == RESET_TYPE_DISABLE) { | |
4b988280 | 1788 | efx_reset_up(efx, method, &ecmd, false); |
8ceee660 | 1789 | rc = -EIO; |
f4bd954e | 1790 | } else { |
4b988280 | 1791 | rc = efx_reset_up(efx, method, &ecmd, true); |
8ceee660 BH |
1792 | } |
1793 | ||
f4bd954e BH |
1794 | out_disable: |
1795 | if (rc) { | |
1796 | EFX_ERR(efx, "has been disabled\n"); | |
1797 | efx->state = STATE_DISABLED; | |
1798 | dev_close(efx->net_dev); | |
1799 | } else { | |
1800 | EFX_LOG(efx, "reset complete\n"); | |
1801 | } | |
8ceee660 | 1802 | |
f4bd954e | 1803 | out_unlock: |
8ceee660 | 1804 | rtnl_unlock(); |
8ceee660 BH |
1805 | return rc; |
1806 | } | |
1807 | ||
1808 | /* The worker thread exists so that code that cannot sleep can | |
1809 | * schedule a reset for later. | |
1810 | */ | |
1811 | static void efx_reset_work(struct work_struct *data) | |
1812 | { | |
1813 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1814 | ||
1815 | efx_reset(nic); | |
1816 | } | |
1817 | ||
1818 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1819 | { | |
1820 | enum reset_type method; | |
1821 | ||
1822 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1823 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1824 | return; | |
1825 | } | |
1826 | ||
1827 | switch (type) { | |
1828 | case RESET_TYPE_INVISIBLE: | |
1829 | case RESET_TYPE_ALL: | |
1830 | case RESET_TYPE_WORLD: | |
1831 | case RESET_TYPE_DISABLE: | |
1832 | method = type; | |
1833 | break; | |
1834 | case RESET_TYPE_RX_RECOVERY: | |
1835 | case RESET_TYPE_RX_DESC_FETCH: | |
1836 | case RESET_TYPE_TX_DESC_FETCH: | |
1837 | case RESET_TYPE_TX_SKIP: | |
1838 | method = RESET_TYPE_INVISIBLE; | |
1839 | break; | |
1840 | default: | |
1841 | method = RESET_TYPE_ALL; | |
1842 | break; | |
1843 | } | |
1844 | ||
1845 | if (method != type) | |
1846 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1847 | else | |
1848 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1849 | ||
1850 | efx->reset_pending = method; | |
1851 | ||
1ab00629 | 1852 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1853 | } |
1854 | ||
1855 | /************************************************************************** | |
1856 | * | |
1857 | * List of NICs we support | |
1858 | * | |
1859 | **************************************************************************/ | |
1860 | ||
1861 | /* PCI device ID table */ | |
1862 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1863 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1864 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1865 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1866 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1867 | {0} /* end of list */ | |
1868 | }; | |
1869 | ||
1870 | /************************************************************************** | |
1871 | * | |
1872 | * Dummy PHY/MAC/Board operations | |
1873 | * | |
01aad7b6 | 1874 | * Can be used for some unimplemented operations |
8ceee660 BH |
1875 | * Needed so all function pointers are valid and do not have to be tested |
1876 | * before use | |
1877 | * | |
1878 | **************************************************************************/ | |
1879 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1880 | { | |
1881 | return 0; | |
1882 | } | |
1883 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1884 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 | 1885 | |
177dfcd8 BH |
1886 | static struct efx_mac_operations efx_dummy_mac_operations = { |
1887 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa BH |
1888 | .poll = efx_port_dummy_op_void, |
1889 | .irq = efx_port_dummy_op_void, | |
177dfcd8 BH |
1890 | }; |
1891 | ||
8ceee660 BH |
1892 | static struct efx_phy_operations efx_dummy_phy_operations = { |
1893 | .init = efx_port_dummy_op_int, | |
1894 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa | 1895 | .poll = efx_port_dummy_op_void, |
8ceee660 BH |
1896 | .fini = efx_port_dummy_op_void, |
1897 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1898 | }; |
1899 | ||
8ceee660 | 1900 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 | 1901 | .init = efx_port_dummy_op_int, |
8129d217 BH |
1902 | .init_leds = efx_port_dummy_op_void, |
1903 | .set_id_led = efx_port_dummy_op_blink, | |
a17102b1 | 1904 | .monitor = efx_port_dummy_op_int, |
01aad7b6 BH |
1905 | .blink = efx_port_dummy_op_blink, |
1906 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1907 | }; |
1908 | ||
1909 | /************************************************************************** | |
1910 | * | |
1911 | * Data housekeeping | |
1912 | * | |
1913 | **************************************************************************/ | |
1914 | ||
1915 | /* This zeroes out and then fills in the invariants in a struct | |
1916 | * efx_nic (including all sub-structures). | |
1917 | */ | |
1918 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1919 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1920 | { | |
1921 | struct efx_channel *channel; | |
1922 | struct efx_tx_queue *tx_queue; | |
1923 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1924 | int i; |
8ceee660 BH |
1925 | |
1926 | /* Initialise common structures */ | |
1927 | memset(efx, 0, sizeof(*efx)); | |
1928 | spin_lock_init(&efx->biu_lock); | |
1929 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1930 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1931 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1932 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1933 | efx->pci_dev = pci_dev; | |
1934 | efx->state = STATE_INIT; | |
1935 | efx->reset_pending = RESET_TYPE_NONE; | |
1936 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1937 | efx->board_info = efx_dummy_board_info; | |
1938 | ||
1939 | efx->net_dev = net_dev; | |
dc8cfa55 | 1940 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1941 | spin_lock_init(&efx->netif_stop_lock); |
1942 | spin_lock_init(&efx->stats_lock); | |
1974cc20 | 1943 | efx->stats_disable_count = 1; |
8ceee660 | 1944 | mutex_init(&efx->mac_lock); |
177dfcd8 | 1945 | efx->mac_op = &efx_dummy_mac_operations; |
8ceee660 BH |
1946 | efx->phy_op = &efx_dummy_phy_operations; |
1947 | efx->mii.dev = net_dev; | |
766ca0fa BH |
1948 | INIT_WORK(&efx->phy_work, efx_phy_work); |
1949 | INIT_WORK(&efx->mac_work, efx_mac_work); | |
8ceee660 BH |
1950 | atomic_set(&efx->netif_stop_count, 1); |
1951 | ||
1952 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1953 | channel = &efx->channel[i]; | |
1954 | channel->efx = efx; | |
1955 | channel->channel = i; | |
dc8cfa55 | 1956 | channel->work_pending = false; |
8ceee660 | 1957 | } |
60ac1065 | 1958 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1959 | tx_queue = &efx->tx_queue[i]; |
1960 | tx_queue->efx = efx; | |
1961 | tx_queue->queue = i; | |
1962 | tx_queue->buffer = NULL; | |
1963 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1964 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1965 | } |
1966 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1967 | rx_queue = &efx->rx_queue[i]; | |
1968 | rx_queue->efx = efx; | |
1969 | rx_queue->queue = i; | |
1970 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1971 | rx_queue->buffer = NULL; | |
1972 | spin_lock_init(&rx_queue->add_lock); | |
1973 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1974 | } | |
1975 | ||
1976 | efx->type = type; | |
1977 | ||
1978 | /* Sanity-check NIC type */ | |
1979 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1980 | (efx->type->txd_ring_mask + 1)); | |
1981 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1982 | (efx->type->rxd_ring_mask + 1)); | |
1983 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1984 | (efx->type->evq_size - 1)); | |
1985 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1986 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1987 | (efx->type->txd_ring_mask + 1 + | |
1988 | efx->type->rxd_ring_mask + 1)); | |
1989 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1990 | ||
1991 | /* Higher numbered interrupt modes are less capable! */ | |
1992 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1993 | interrupt_mode); | |
1994 | ||
6977dc63 BH |
1995 | /* Would be good to use the net_dev name, but we're too early */ |
1996 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
1997 | pci_name(pci_dev)); | |
1998 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
1999 | if (!efx->workqueue) |
2000 | return -ENOMEM; | |
8d9853d9 | 2001 | |
8ceee660 | 2002 | return 0; |
8ceee660 BH |
2003 | } |
2004 | ||
2005 | static void efx_fini_struct(struct efx_nic *efx) | |
2006 | { | |
2007 | if (efx->workqueue) { | |
2008 | destroy_workqueue(efx->workqueue); | |
2009 | efx->workqueue = NULL; | |
2010 | } | |
2011 | } | |
2012 | ||
2013 | /************************************************************************** | |
2014 | * | |
2015 | * PCI interface | |
2016 | * | |
2017 | **************************************************************************/ | |
2018 | ||
2019 | /* Main body of final NIC shutdown code | |
2020 | * This is called only at module unload (or hotplug removal). | |
2021 | */ | |
2022 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2023 | { | |
2024 | EFX_ASSERT_RESET_SERIALISED(efx); | |
2025 | ||
2026 | /* Skip everything if we never obtained a valid membase */ | |
2027 | if (!efx->membase) | |
2028 | return; | |
2029 | ||
2030 | efx_fini_channels(efx); | |
2031 | efx_fini_port(efx); | |
2032 | ||
2033 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 2034 | efx->board_info.fini(efx); |
8ceee660 BH |
2035 | falcon_fini_interrupt(efx); |
2036 | ||
2037 | efx_fini_napi(efx); | |
2038 | efx_remove_all(efx); | |
2039 | } | |
2040 | ||
2041 | /* Final NIC shutdown | |
2042 | * This is called only at module unload (or hotplug removal). | |
2043 | */ | |
2044 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2045 | { | |
2046 | struct efx_nic *efx; | |
2047 | ||
2048 | efx = pci_get_drvdata(pci_dev); | |
2049 | if (!efx) | |
2050 | return; | |
2051 | ||
2052 | /* Mark the NIC as fini, then stop the interface */ | |
2053 | rtnl_lock(); | |
2054 | efx->state = STATE_FINI; | |
2055 | dev_close(efx->net_dev); | |
2056 | ||
2057 | /* Allow any queued efx_resets() to complete */ | |
2058 | rtnl_unlock(); | |
2059 | ||
2060 | if (efx->membase == NULL) | |
2061 | goto out; | |
2062 | ||
2063 | efx_unregister_netdev(efx); | |
2064 | ||
7dde596e BH |
2065 | efx_mtd_remove(efx); |
2066 | ||
8ceee660 BH |
2067 | /* Wait for any scheduled resets to complete. No more will be |
2068 | * scheduled from this point because efx_stop_all() has been | |
2069 | * called, we are no longer registered with driverlink, and | |
2070 | * the net_device's have been removed. */ | |
1ab00629 | 2071 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2072 | |
2073 | efx_pci_remove_main(efx); | |
2074 | ||
2075 | out: | |
2076 | efx_fini_io(efx); | |
2077 | EFX_LOG(efx, "shutdown successful\n"); | |
2078 | ||
2079 | pci_set_drvdata(pci_dev, NULL); | |
2080 | efx_fini_struct(efx); | |
2081 | free_netdev(efx->net_dev); | |
2082 | }; | |
2083 | ||
2084 | /* Main body of NIC initialisation | |
2085 | * This is called at module load (or hotplug insertion, theoretically). | |
2086 | */ | |
2087 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2088 | { | |
2089 | int rc; | |
2090 | ||
2091 | /* Do start-of-day initialisation */ | |
2092 | rc = efx_probe_all(efx); | |
2093 | if (rc) | |
2094 | goto fail1; | |
2095 | ||
2096 | rc = efx_init_napi(efx); | |
2097 | if (rc) | |
2098 | goto fail2; | |
2099 | ||
2100 | /* Initialise the board */ | |
2101 | rc = efx->board_info.init(efx); | |
2102 | if (rc) { | |
2103 | EFX_ERR(efx, "failed to initialise board\n"); | |
2104 | goto fail3; | |
2105 | } | |
2106 | ||
2107 | rc = falcon_init_nic(efx); | |
2108 | if (rc) { | |
2109 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
2110 | goto fail4; | |
2111 | } | |
2112 | ||
2113 | rc = efx_init_port(efx); | |
2114 | if (rc) { | |
2115 | EFX_ERR(efx, "failed to initialise port\n"); | |
2116 | goto fail5; | |
2117 | } | |
2118 | ||
bc3c90a2 | 2119 | efx_init_channels(efx); |
8ceee660 BH |
2120 | |
2121 | rc = falcon_init_interrupt(efx); | |
2122 | if (rc) | |
bc3c90a2 | 2123 | goto fail6; |
8ceee660 BH |
2124 | |
2125 | return 0; | |
2126 | ||
8ceee660 | 2127 | fail6: |
bc3c90a2 | 2128 | efx_fini_channels(efx); |
8ceee660 BH |
2129 | efx_fini_port(efx); |
2130 | fail5: | |
2131 | fail4: | |
a17102b1 | 2132 | efx->board_info.fini(efx); |
8ceee660 BH |
2133 | fail3: |
2134 | efx_fini_napi(efx); | |
2135 | fail2: | |
2136 | efx_remove_all(efx); | |
2137 | fail1: | |
2138 | return rc; | |
2139 | } | |
2140 | ||
2141 | /* NIC initialisation | |
2142 | * | |
2143 | * This is called at module load (or hotplug insertion, | |
2144 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2145 | * sets up and registers the network devices with the kernel and hooks | |
2146 | * the interrupt service routine. It does not prepare the device for | |
2147 | * transmission; this is left to the first time one of the network | |
2148 | * interfaces is brought up (i.e. efx_net_open). | |
2149 | */ | |
2150 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2151 | const struct pci_device_id *entry) | |
2152 | { | |
2153 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2154 | struct net_device *net_dev; | |
2155 | struct efx_nic *efx; | |
2156 | int i, rc; | |
2157 | ||
2158 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2159 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2160 | if (!net_dev) | |
2161 | return -ENOMEM; | |
b9b39b62 BH |
2162 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2163 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 | 2164 | if (lro) |
da3bc071 | 2165 | net_dev->features |= NETIF_F_GRO; |
28506563 BH |
2166 | /* Mask for features that also apply to VLAN devices */ |
2167 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2168 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2169 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2170 | pci_set_drvdata(pci_dev, efx); |
2171 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2172 | if (rc) | |
2173 | goto fail1; | |
2174 | ||
2175 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2176 | ||
2177 | /* Set up basic I/O (BAR mappings etc) */ | |
2178 | rc = efx_init_io(efx); | |
2179 | if (rc) | |
2180 | goto fail2; | |
2181 | ||
2182 | /* No serialisation is required with the reset path because | |
2183 | * we're in STATE_INIT. */ | |
2184 | for (i = 0; i < 5; i++) { | |
2185 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2186 | |
2187 | /* Serialise against efx_reset(). No more resets will be | |
2188 | * scheduled since efx_stop_all() has been called, and we | |
2189 | * have not and never have been registered with either | |
2190 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2191 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2192 | |
fa402b2e SH |
2193 | if (rc == 0) { |
2194 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2195 | /* If there was a scheduled reset during | |
2196 | * probe, the NIC is probably hosed anyway */ | |
2197 | efx_pci_remove_main(efx); | |
2198 | rc = -EIO; | |
2199 | } else { | |
2200 | break; | |
2201 | } | |
2202 | } | |
2203 | ||
8ceee660 BH |
2204 | /* Retry if a recoverably reset event has been scheduled */ |
2205 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2206 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2207 | goto fail3; | |
2208 | ||
2209 | efx->reset_pending = RESET_TYPE_NONE; | |
2210 | } | |
2211 | ||
2212 | if (rc) { | |
2213 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2214 | goto fail4; | |
2215 | } | |
2216 | ||
2217 | /* Switch to the running state before we expose the device to | |
2218 | * the OS. This is to ensure that the initial gathering of | |
2219 | * MAC stats succeeds. */ | |
8ceee660 | 2220 | efx->state = STATE_RUNNING; |
7dde596e BH |
2221 | |
2222 | efx_mtd_probe(efx); /* allowed to fail */ | |
8ceee660 BH |
2223 | |
2224 | rc = efx_register_netdev(efx); | |
2225 | if (rc) | |
2226 | goto fail5; | |
2227 | ||
2228 | EFX_LOG(efx, "initialisation successful\n"); | |
8ceee660 BH |
2229 | return 0; |
2230 | ||
2231 | fail5: | |
2232 | efx_pci_remove_main(efx); | |
2233 | fail4: | |
2234 | fail3: | |
2235 | efx_fini_io(efx); | |
2236 | fail2: | |
2237 | efx_fini_struct(efx); | |
2238 | fail1: | |
2239 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2240 | free_netdev(net_dev); | |
2241 | return rc; | |
2242 | } | |
2243 | ||
2244 | static struct pci_driver efx_pci_driver = { | |
2245 | .name = EFX_DRIVER_NAME, | |
2246 | .id_table = efx_pci_table, | |
2247 | .probe = efx_pci_probe, | |
2248 | .remove = efx_pci_remove, | |
2249 | }; | |
2250 | ||
2251 | /************************************************************************** | |
2252 | * | |
2253 | * Kernel module interface | |
2254 | * | |
2255 | *************************************************************************/ | |
2256 | ||
2257 | module_param(interrupt_mode, uint, 0444); | |
2258 | MODULE_PARM_DESC(interrupt_mode, | |
2259 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2260 | ||
2261 | static int __init efx_init_module(void) | |
2262 | { | |
2263 | int rc; | |
2264 | ||
2265 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2266 | ||
2267 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2268 | if (rc) | |
2269 | goto err_notifier; | |
2270 | ||
2271 | refill_workqueue = create_workqueue("sfc_refill"); | |
2272 | if (!refill_workqueue) { | |
2273 | rc = -ENOMEM; | |
2274 | goto err_refill; | |
2275 | } | |
1ab00629 SH |
2276 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2277 | if (!reset_workqueue) { | |
2278 | rc = -ENOMEM; | |
2279 | goto err_reset; | |
2280 | } | |
8ceee660 BH |
2281 | |
2282 | rc = pci_register_driver(&efx_pci_driver); | |
2283 | if (rc < 0) | |
2284 | goto err_pci; | |
2285 | ||
2286 | return 0; | |
2287 | ||
2288 | err_pci: | |
1ab00629 SH |
2289 | destroy_workqueue(reset_workqueue); |
2290 | err_reset: | |
8ceee660 BH |
2291 | destroy_workqueue(refill_workqueue); |
2292 | err_refill: | |
2293 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2294 | err_notifier: | |
2295 | return rc; | |
2296 | } | |
2297 | ||
2298 | static void __exit efx_exit_module(void) | |
2299 | { | |
2300 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2301 | ||
2302 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2303 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2304 | destroy_workqueue(refill_workqueue); |
2305 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2306 | ||
2307 | } | |
2308 | ||
2309 | module_init(efx_init_module); | |
2310 | module_exit(efx_exit_module); | |
2311 | ||
2312 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2313 | "Solarflare Communications"); | |
2314 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2315 | MODULE_LICENSE("GPL"); | |
2316 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |