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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 | 23 | #include "net_driver.h" |
8ceee660 BH |
24 | #include "ethtool.h" |
25 | #include "tx.h" | |
26 | #include "rx.h" | |
27 | #include "efx.h" | |
28 | #include "mdio_10g.h" | |
29 | #include "falcon.h" | |
8ceee660 BH |
30 | #include "mac.h" |
31 | ||
32 | #define EFX_MAX_MTU (9 * 1024) | |
33 | ||
34 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
35 | * a work item is pushed onto this work queue to retry the allocation later, | |
36 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
37 | * workqueue, there is nothing to be gained in making it per NIC | |
38 | */ | |
39 | static struct workqueue_struct *refill_workqueue; | |
40 | ||
1ab00629 SH |
41 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
42 | * queued onto this work queue. This is not a per-nic work queue, because | |
43 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
44 | */ | |
45 | static struct workqueue_struct *reset_workqueue; | |
46 | ||
8ceee660 BH |
47 | /************************************************************************** |
48 | * | |
49 | * Configurable values | |
50 | * | |
51 | *************************************************************************/ | |
52 | ||
53 | /* | |
54 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
55 | * | |
56 | * This sets the default for new devices. It can be controlled later | |
57 | * using ethtool. | |
58 | */ | |
dc8cfa55 | 59 | static int lro = true; |
8ceee660 BH |
60 | module_param(lro, int, 0644); |
61 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
62 | ||
63 | /* | |
64 | * Use separate channels for TX and RX events | |
65 | * | |
28b581ab NT |
66 | * Set this to 1 to use separate channels for TX and RX. It allows us |
67 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 68 | * |
28b581ab | 69 | * This is only used in MSI-X interrupt mode |
8ceee660 | 70 | */ |
28b581ab NT |
71 | static unsigned int separate_tx_channels; |
72 | module_param(separate_tx_channels, uint, 0644); | |
73 | MODULE_PARM_DESC(separate_tx_channels, | |
74 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
75 | |
76 | /* This is the weight assigned to each of the (per-channel) virtual | |
77 | * NAPI devices. | |
78 | */ | |
79 | static int napi_weight = 64; | |
80 | ||
81 | /* This is the time (in jiffies) between invocations of the hardware | |
82 | * monitor, which checks for known hardware bugs and resets the | |
83 | * hardware and driver as necessary. | |
84 | */ | |
85 | unsigned int efx_monitor_interval = 1 * HZ; | |
86 | ||
8ceee660 BH |
87 | /* This controls whether or not the driver will initialise devices |
88 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
89 | * such devices will be initialised with a random locally-generated | |
90 | * MAC address. This allows for loading the sfc_mtd driver to | |
91 | * reprogram the flash, even if the flash contents (including the MAC | |
92 | * address) have previously been erased. | |
93 | */ | |
94 | static unsigned int allow_bad_hwaddr; | |
95 | ||
96 | /* Initial interrupt moderation settings. They can be modified after | |
97 | * module load with ethtool. | |
98 | * | |
99 | * The default for RX should strike a balance between increasing the | |
100 | * round-trip latency and reducing overhead. | |
101 | */ | |
102 | static unsigned int rx_irq_mod_usec = 60; | |
103 | ||
104 | /* Initial interrupt moderation settings. They can be modified after | |
105 | * module load with ethtool. | |
106 | * | |
107 | * This default is chosen to ensure that a 10G link does not go idle | |
108 | * while a TX queue is stopped after it has become full. A queue is | |
109 | * restarted when it drops below half full. The time this takes (assuming | |
110 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
111 | * 512 / 3 * 1.2 = 205 usec. | |
112 | */ | |
113 | static unsigned int tx_irq_mod_usec = 150; | |
114 | ||
115 | /* This is the first interrupt mode to try out of: | |
116 | * 0 => MSI-X | |
117 | * 1 => MSI | |
118 | * 2 => legacy | |
119 | */ | |
120 | static unsigned int interrupt_mode; | |
121 | ||
122 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
123 | * i.e. the number of CPUs among which we may distribute simultaneous | |
124 | * interrupt handling. | |
125 | * | |
126 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
127 | * The default (0) means to assign an interrupt to each package (level II cache) | |
128 | */ | |
129 | static unsigned int rss_cpus; | |
130 | module_param(rss_cpus, uint, 0444); | |
131 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
132 | ||
84ae48fe BH |
133 | static int phy_flash_cfg; |
134 | module_param(phy_flash_cfg, int, 0644); | |
135 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
136 | ||
8ceee660 BH |
137 | /************************************************************************** |
138 | * | |
139 | * Utility functions and prototypes | |
140 | * | |
141 | *************************************************************************/ | |
142 | static void efx_remove_channel(struct efx_channel *channel); | |
143 | static void efx_remove_port(struct efx_nic *efx); | |
144 | static void efx_fini_napi(struct efx_nic *efx); | |
145 | static void efx_fini_channels(struct efx_nic *efx); | |
146 | ||
147 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
148 | do { \ | |
3c78708f | 149 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
150 | ASSERT_RTNL(); \ |
151 | } while (0) | |
152 | ||
153 | /************************************************************************** | |
154 | * | |
155 | * Event queue processing | |
156 | * | |
157 | *************************************************************************/ | |
158 | ||
159 | /* Process channel's event queue | |
160 | * | |
161 | * This function is responsible for processing the event queue of a | |
162 | * single channel. The caller must guarantee that this function will | |
163 | * never be concurrently called more than once on the same channel, | |
164 | * though different channels may be being processed concurrently. | |
165 | */ | |
4d566063 | 166 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 167 | { |
42cbe2d7 BH |
168 | struct efx_nic *efx = channel->efx; |
169 | int rx_packets; | |
8ceee660 | 170 | |
42cbe2d7 | 171 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 172 | !channel->enabled)) |
42cbe2d7 | 173 | return 0; |
8ceee660 | 174 | |
42cbe2d7 BH |
175 | rx_packets = falcon_process_eventq(channel, rx_quota); |
176 | if (rx_packets == 0) | |
177 | return 0; | |
8ceee660 BH |
178 | |
179 | /* Deliver last RX packet. */ | |
180 | if (channel->rx_pkt) { | |
181 | __efx_rx_packet(channel, channel->rx_pkt, | |
182 | channel->rx_pkt_csummed); | |
183 | channel->rx_pkt = NULL; | |
184 | } | |
185 | ||
186 | efx_flush_lro(channel); | |
187 | efx_rx_strategy(channel); | |
188 | ||
42cbe2d7 | 189 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 190 | |
42cbe2d7 | 191 | return rx_packets; |
8ceee660 BH |
192 | } |
193 | ||
194 | /* Mark channel as finished processing | |
195 | * | |
196 | * Note that since we will not receive further interrupts for this | |
197 | * channel before we finish processing and call the eventq_read_ack() | |
198 | * method, there is no need to use the interrupt hold-off timers. | |
199 | */ | |
200 | static inline void efx_channel_processed(struct efx_channel *channel) | |
201 | { | |
5b9e207c BH |
202 | /* The interrupt handler for this channel may set work_pending |
203 | * as soon as we acknowledge the events we've seen. Make sure | |
204 | * it's cleared before then. */ | |
dc8cfa55 | 205 | channel->work_pending = false; |
5b9e207c BH |
206 | smp_wmb(); |
207 | ||
8ceee660 BH |
208 | falcon_eventq_read_ack(channel); |
209 | } | |
210 | ||
211 | /* NAPI poll handler | |
212 | * | |
213 | * NAPI guarantees serialisation of polls of the same device, which | |
214 | * provides the guarantee required by efx_process_channel(). | |
215 | */ | |
216 | static int efx_poll(struct napi_struct *napi, int budget) | |
217 | { | |
218 | struct efx_channel *channel = | |
219 | container_of(napi, struct efx_channel, napi_str); | |
220 | struct net_device *napi_dev = channel->napi_dev; | |
8ceee660 BH |
221 | int rx_packets; |
222 | ||
223 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
224 | channel->channel, raw_smp_processor_id()); | |
225 | ||
42cbe2d7 | 226 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
227 | |
228 | if (rx_packets < budget) { | |
229 | /* There is no race here; although napi_disable() will | |
230 | * only wait for netif_rx_complete(), this isn't a problem | |
231 | * since efx_channel_processed() will have no effect if | |
232 | * interrupts have already been disabled. | |
233 | */ | |
234 | netif_rx_complete(napi_dev, napi); | |
235 | efx_channel_processed(channel); | |
236 | } | |
237 | ||
238 | return rx_packets; | |
239 | } | |
240 | ||
241 | /* Process the eventq of the specified channel immediately on this CPU | |
242 | * | |
243 | * Disable hardware generated interrupts, wait for any existing | |
244 | * processing to finish, then directly poll (and ack ) the eventq. | |
245 | * Finally reenable NAPI and interrupts. | |
246 | * | |
247 | * Since we are touching interrupts the caller should hold the suspend lock | |
248 | */ | |
249 | void efx_process_channel_now(struct efx_channel *channel) | |
250 | { | |
251 | struct efx_nic *efx = channel->efx; | |
252 | ||
253 | BUG_ON(!channel->used_flags); | |
254 | BUG_ON(!channel->enabled); | |
255 | ||
256 | /* Disable interrupts and wait for ISRs to complete */ | |
257 | falcon_disable_interrupts(efx); | |
258 | if (efx->legacy_irq) | |
259 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 260 | if (channel->irq) |
8ceee660 BH |
261 | synchronize_irq(channel->irq); |
262 | ||
263 | /* Wait for any NAPI processing to complete */ | |
264 | napi_disable(&channel->napi_str); | |
265 | ||
266 | /* Poll the channel */ | |
91ad757c | 267 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
268 | |
269 | /* Ack the eventq. This may cause an interrupt to be generated | |
270 | * when they are reenabled */ | |
271 | efx_channel_processed(channel); | |
272 | ||
273 | napi_enable(&channel->napi_str); | |
274 | falcon_enable_interrupts(efx); | |
275 | } | |
276 | ||
277 | /* Create event queue | |
278 | * Event queue memory allocations are done only once. If the channel | |
279 | * is reset, the memory buffer will be reused; this guards against | |
280 | * errors during channel reset and also simplifies interrupt handling. | |
281 | */ | |
282 | static int efx_probe_eventq(struct efx_channel *channel) | |
283 | { | |
284 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
285 | ||
286 | return falcon_probe_eventq(channel); | |
287 | } | |
288 | ||
289 | /* Prepare channel's event queue */ | |
bc3c90a2 | 290 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
291 | { |
292 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
293 | ||
294 | channel->eventq_read_ptr = 0; | |
295 | ||
bc3c90a2 | 296 | falcon_init_eventq(channel); |
8ceee660 BH |
297 | } |
298 | ||
299 | static void efx_fini_eventq(struct efx_channel *channel) | |
300 | { | |
301 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
302 | ||
303 | falcon_fini_eventq(channel); | |
304 | } | |
305 | ||
306 | static void efx_remove_eventq(struct efx_channel *channel) | |
307 | { | |
308 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
309 | ||
310 | falcon_remove_eventq(channel); | |
311 | } | |
312 | ||
313 | /************************************************************************** | |
314 | * | |
315 | * Channel handling | |
316 | * | |
317 | *************************************************************************/ | |
318 | ||
8ceee660 BH |
319 | static int efx_probe_channel(struct efx_channel *channel) |
320 | { | |
321 | struct efx_tx_queue *tx_queue; | |
322 | struct efx_rx_queue *rx_queue; | |
323 | int rc; | |
324 | ||
325 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
326 | ||
327 | rc = efx_probe_eventq(channel); | |
328 | if (rc) | |
329 | goto fail1; | |
330 | ||
331 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
332 | rc = efx_probe_tx_queue(tx_queue); | |
333 | if (rc) | |
334 | goto fail2; | |
335 | } | |
336 | ||
337 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
338 | rc = efx_probe_rx_queue(rx_queue); | |
339 | if (rc) | |
340 | goto fail3; | |
341 | } | |
342 | ||
343 | channel->n_rx_frm_trunc = 0; | |
344 | ||
345 | return 0; | |
346 | ||
347 | fail3: | |
348 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
349 | efx_remove_rx_queue(rx_queue); | |
350 | fail2: | |
351 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
352 | efx_remove_tx_queue(tx_queue); | |
353 | fail1: | |
354 | return rc; | |
355 | } | |
356 | ||
357 | ||
56536e9c BH |
358 | static void efx_set_channel_names(struct efx_nic *efx) |
359 | { | |
360 | struct efx_channel *channel; | |
361 | const char *type = ""; | |
362 | int number; | |
363 | ||
364 | efx_for_each_channel(channel, efx) { | |
365 | number = channel->channel; | |
366 | if (efx->n_channels > efx->n_rx_queues) { | |
367 | if (channel->channel < efx->n_rx_queues) { | |
368 | type = "-rx"; | |
369 | } else { | |
370 | type = "-tx"; | |
371 | number -= efx->n_rx_queues; | |
372 | } | |
373 | } | |
374 | snprintf(channel->name, sizeof(channel->name), | |
375 | "%s%s-%d", efx->name, type, number); | |
376 | } | |
377 | } | |
378 | ||
8ceee660 BH |
379 | /* Channels are shutdown and reinitialised whilst the NIC is running |
380 | * to propagate configuration changes (mtu, checksum offload), or | |
381 | * to clear hardware error conditions | |
382 | */ | |
bc3c90a2 | 383 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
384 | { |
385 | struct efx_tx_queue *tx_queue; | |
386 | struct efx_rx_queue *rx_queue; | |
387 | struct efx_channel *channel; | |
8ceee660 | 388 | |
f7f13b0b BH |
389 | /* Calculate the rx buffer allocation parameters required to |
390 | * support the current MTU, including padding for header | |
391 | * alignment and overruns. | |
392 | */ | |
393 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
394 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
395 | efx->type->rx_buffer_padding); | |
396 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
397 | |
398 | /* Initialise the channels */ | |
399 | efx_for_each_channel(channel, efx) { | |
400 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
401 | ||
bc3c90a2 | 402 | efx_init_eventq(channel); |
8ceee660 | 403 | |
bc3c90a2 BH |
404 | efx_for_each_channel_tx_queue(tx_queue, channel) |
405 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
406 | |
407 | /* The rx buffer allocation strategy is MTU dependent */ | |
408 | efx_rx_strategy(channel); | |
409 | ||
bc3c90a2 BH |
410 | efx_for_each_channel_rx_queue(rx_queue, channel) |
411 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
412 | |
413 | WARN_ON(channel->rx_pkt != NULL); | |
414 | efx_rx_strategy(channel); | |
415 | } | |
8ceee660 BH |
416 | } |
417 | ||
418 | /* This enables event queue processing and packet transmission. | |
419 | * | |
420 | * Note that this function is not allowed to fail, since that would | |
421 | * introduce too much complexity into the suspend/resume path. | |
422 | */ | |
423 | static void efx_start_channel(struct efx_channel *channel) | |
424 | { | |
425 | struct efx_rx_queue *rx_queue; | |
426 | ||
427 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
428 | ||
429 | if (!(channel->efx->net_dev->flags & IFF_UP)) | |
430 | netif_napi_add(channel->napi_dev, &channel->napi_str, | |
431 | efx_poll, napi_weight); | |
432 | ||
5b9e207c BH |
433 | /* The interrupt handler for this channel may set work_pending |
434 | * as soon as we enable it. Make sure it's cleared before | |
435 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
436 | channel->work_pending = false; |
437 | channel->enabled = true; | |
5b9e207c | 438 | smp_wmb(); |
8ceee660 BH |
439 | |
440 | napi_enable(&channel->napi_str); | |
441 | ||
442 | /* Load up RX descriptors */ | |
443 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
444 | efx_fast_push_rx_descriptors(rx_queue); | |
445 | } | |
446 | ||
447 | /* This disables event queue processing and packet transmission. | |
448 | * This function does not guarantee that all queue processing | |
449 | * (e.g. RX refill) is complete. | |
450 | */ | |
451 | static void efx_stop_channel(struct efx_channel *channel) | |
452 | { | |
453 | struct efx_rx_queue *rx_queue; | |
454 | ||
455 | if (!channel->enabled) | |
456 | return; | |
457 | ||
458 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
459 | ||
dc8cfa55 | 460 | channel->enabled = false; |
8ceee660 BH |
461 | napi_disable(&channel->napi_str); |
462 | ||
463 | /* Ensure that any worker threads have exited or will be no-ops */ | |
464 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
465 | spin_lock_bh(&rx_queue->add_lock); | |
466 | spin_unlock_bh(&rx_queue->add_lock); | |
467 | } | |
468 | } | |
469 | ||
470 | static void efx_fini_channels(struct efx_nic *efx) | |
471 | { | |
472 | struct efx_channel *channel; | |
473 | struct efx_tx_queue *tx_queue; | |
474 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 475 | int rc; |
8ceee660 BH |
476 | |
477 | EFX_ASSERT_RESET_SERIALISED(efx); | |
478 | BUG_ON(efx->port_enabled); | |
479 | ||
6bc5d3a9 BH |
480 | rc = falcon_flush_queues(efx); |
481 | if (rc) | |
482 | EFX_ERR(efx, "failed to flush queues\n"); | |
483 | else | |
484 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
485 | ||
8ceee660 BH |
486 | efx_for_each_channel(channel, efx) { |
487 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
488 | ||
489 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
490 | efx_fini_rx_queue(rx_queue); | |
491 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
492 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
493 | efx_fini_eventq(channel); |
494 | } | |
495 | } | |
496 | ||
497 | static void efx_remove_channel(struct efx_channel *channel) | |
498 | { | |
499 | struct efx_tx_queue *tx_queue; | |
500 | struct efx_rx_queue *rx_queue; | |
501 | ||
502 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
503 | ||
504 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
505 | efx_remove_rx_queue(rx_queue); | |
506 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
507 | efx_remove_tx_queue(tx_queue); | |
508 | efx_remove_eventq(channel); | |
509 | ||
510 | channel->used_flags = 0; | |
511 | } | |
512 | ||
513 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
514 | { | |
515 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
516 | } | |
517 | ||
518 | /************************************************************************** | |
519 | * | |
520 | * Port handling | |
521 | * | |
522 | **************************************************************************/ | |
523 | ||
524 | /* This ensures that the kernel is kept informed (via | |
525 | * netif_carrier_on/off) of the link status, and also maintains the | |
526 | * link status's stop on the port's TX queue. | |
527 | */ | |
528 | static void efx_link_status_changed(struct efx_nic *efx) | |
529 | { | |
8ceee660 BH |
530 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
531 | * that no events are triggered between unregister_netdev() and the | |
532 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
533 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
534 | if (!netif_running(efx->net_dev)) | |
535 | return; | |
536 | ||
8c8661e4 BH |
537 | if (efx->port_inhibited) { |
538 | netif_carrier_off(efx->net_dev); | |
539 | return; | |
540 | } | |
541 | ||
dc8cfa55 | 542 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
543 | efx->n_link_state_changes++; |
544 | ||
545 | if (efx->link_up) | |
546 | netif_carrier_on(efx->net_dev); | |
547 | else | |
548 | netif_carrier_off(efx->net_dev); | |
549 | } | |
550 | ||
551 | /* Status message for kernel log */ | |
552 | if (efx->link_up) { | |
f31a45d2 BH |
553 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
554 | efx->link_speed, efx->link_fd ? "full" : "half", | |
8ceee660 BH |
555 | efx->net_dev->mtu, |
556 | (efx->promiscuous ? " [PROMISC]" : "")); | |
557 | } else { | |
558 | EFX_INFO(efx, "link down\n"); | |
559 | } | |
560 | ||
561 | } | |
562 | ||
563 | /* This call reinitialises the MAC to pick up new PHY settings. The | |
564 | * caller must hold the mac_lock */ | |
8c8661e4 | 565 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
566 | { |
567 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
568 | ||
569 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
570 | raw_smp_processor_id()); | |
571 | ||
a816f75a BH |
572 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
573 | if (efx_dev_registered(efx)) { | |
574 | netif_addr_lock_bh(efx->net_dev); | |
575 | netif_addr_unlock_bh(efx->net_dev); | |
576 | } | |
577 | ||
8ceee660 BH |
578 | falcon_reconfigure_xmac(efx); |
579 | ||
580 | /* Inform kernel of loss/gain of carrier */ | |
581 | efx_link_status_changed(efx); | |
582 | } | |
583 | ||
584 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
585 | * disabled. */ | |
586 | void efx_reconfigure_port(struct efx_nic *efx) | |
587 | { | |
588 | EFX_ASSERT_RESET_SERIALISED(efx); | |
589 | ||
590 | mutex_lock(&efx->mac_lock); | |
591 | __efx_reconfigure_port(efx); | |
592 | mutex_unlock(&efx->mac_lock); | |
593 | } | |
594 | ||
595 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
596 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
597 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
598 | static void efx_reconfigure_work(struct work_struct *data) | |
599 | { | |
600 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
601 | reconfigure_work); | |
602 | ||
603 | mutex_lock(&efx->mac_lock); | |
604 | if (efx->port_enabled) | |
605 | __efx_reconfigure_port(efx); | |
606 | mutex_unlock(&efx->mac_lock); | |
607 | } | |
608 | ||
609 | static int efx_probe_port(struct efx_nic *efx) | |
610 | { | |
611 | int rc; | |
612 | ||
613 | EFX_LOG(efx, "create port\n"); | |
614 | ||
615 | /* Connect up MAC/PHY operations table and read MAC address */ | |
616 | rc = falcon_probe_port(efx); | |
617 | if (rc) | |
618 | goto err; | |
619 | ||
84ae48fe BH |
620 | if (phy_flash_cfg) |
621 | efx->phy_mode = PHY_MODE_SPECIAL; | |
622 | ||
8ceee660 BH |
623 | /* Sanity check MAC address */ |
624 | if (is_valid_ether_addr(efx->mac_address)) { | |
625 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
626 | } else { | |
e174961c JB |
627 | EFX_ERR(efx, "invalid MAC address %pM\n", |
628 | efx->mac_address); | |
8ceee660 BH |
629 | if (!allow_bad_hwaddr) { |
630 | rc = -EINVAL; | |
631 | goto err; | |
632 | } | |
633 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
634 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
635 | efx->net_dev->dev_addr); | |
8ceee660 BH |
636 | } |
637 | ||
638 | return 0; | |
639 | ||
640 | err: | |
641 | efx_remove_port(efx); | |
642 | return rc; | |
643 | } | |
644 | ||
645 | static int efx_init_port(struct efx_nic *efx) | |
646 | { | |
647 | int rc; | |
648 | ||
649 | EFX_LOG(efx, "init port\n"); | |
650 | ||
651 | /* Initialise the MAC and PHY */ | |
652 | rc = falcon_init_xmac(efx); | |
653 | if (rc) | |
654 | return rc; | |
655 | ||
dc8cfa55 | 656 | efx->port_initialized = true; |
8c8661e4 | 657 | efx->stats_enabled = true; |
8ceee660 BH |
658 | |
659 | /* Reconfigure port to program MAC registers */ | |
660 | falcon_reconfigure_xmac(efx); | |
661 | ||
662 | return 0; | |
663 | } | |
664 | ||
665 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
666 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
667 | * efx_reconfigure_port() may have been cancelled */ | |
668 | static void efx_start_port(struct efx_nic *efx) | |
669 | { | |
670 | EFX_LOG(efx, "start port\n"); | |
671 | BUG_ON(efx->port_enabled); | |
672 | ||
673 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 674 | efx->port_enabled = true; |
8ceee660 BH |
675 | __efx_reconfigure_port(efx); |
676 | mutex_unlock(&efx->mac_lock); | |
677 | } | |
678 | ||
679 | /* Prevent efx_reconfigure_work and efx_monitor() from executing, and | |
680 | * efx_set_multicast_list() from scheduling efx_reconfigure_work. | |
681 | * efx_reconfigure_work can still be scheduled via NAPI processing | |
682 | * until efx_flush_all() is called */ | |
683 | static void efx_stop_port(struct efx_nic *efx) | |
684 | { | |
685 | EFX_LOG(efx, "stop port\n"); | |
686 | ||
687 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 688 | efx->port_enabled = false; |
8ceee660 BH |
689 | mutex_unlock(&efx->mac_lock); |
690 | ||
691 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 692 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
693 | netif_addr_lock_bh(efx->net_dev); |
694 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
695 | } |
696 | } | |
697 | ||
698 | static void efx_fini_port(struct efx_nic *efx) | |
699 | { | |
700 | EFX_LOG(efx, "shut down port\n"); | |
701 | ||
702 | if (!efx->port_initialized) | |
703 | return; | |
704 | ||
705 | falcon_fini_xmac(efx); | |
dc8cfa55 | 706 | efx->port_initialized = false; |
8ceee660 | 707 | |
dc8cfa55 | 708 | efx->link_up = false; |
8ceee660 BH |
709 | efx_link_status_changed(efx); |
710 | } | |
711 | ||
712 | static void efx_remove_port(struct efx_nic *efx) | |
713 | { | |
714 | EFX_LOG(efx, "destroying port\n"); | |
715 | ||
716 | falcon_remove_port(efx); | |
717 | } | |
718 | ||
719 | /************************************************************************** | |
720 | * | |
721 | * NIC handling | |
722 | * | |
723 | **************************************************************************/ | |
724 | ||
725 | /* This configures the PCI device to enable I/O and DMA. */ | |
726 | static int efx_init_io(struct efx_nic *efx) | |
727 | { | |
728 | struct pci_dev *pci_dev = efx->pci_dev; | |
729 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
730 | int rc; | |
731 | ||
732 | EFX_LOG(efx, "initialising I/O\n"); | |
733 | ||
734 | rc = pci_enable_device(pci_dev); | |
735 | if (rc) { | |
736 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
737 | goto fail1; | |
738 | } | |
739 | ||
740 | pci_set_master(pci_dev); | |
741 | ||
742 | /* Set the PCI DMA mask. Try all possibilities from our | |
743 | * genuine mask down to 32 bits, because some architectures | |
744 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
745 | * masks event though they reject 46 bit masks. | |
746 | */ | |
747 | while (dma_mask > 0x7fffffffUL) { | |
748 | if (pci_dma_supported(pci_dev, dma_mask) && | |
749 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
750 | break; | |
751 | dma_mask >>= 1; | |
752 | } | |
753 | if (rc) { | |
754 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
755 | goto fail2; | |
756 | } | |
757 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
758 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
759 | if (rc) { | |
760 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
761 | * fail with a mask that pci_set_dma_mask() accepted, | |
762 | * but just in case... | |
763 | */ | |
764 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
765 | goto fail2; | |
766 | } | |
767 | ||
768 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
769 | efx->type->mem_bar); | |
770 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
771 | if (rc) { | |
772 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
773 | rc = -EIO; | |
774 | goto fail3; | |
775 | } | |
776 | efx->membase = ioremap_nocache(efx->membase_phys, | |
777 | efx->type->mem_map_size); | |
778 | if (!efx->membase) { | |
086ea356 BH |
779 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
780 | efx->type->mem_bar, | |
781 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
782 | efx->type->mem_map_size); |
783 | rc = -ENOMEM; | |
784 | goto fail4; | |
785 | } | |
086ea356 BH |
786 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
787 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
788 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
789 | |
790 | return 0; | |
791 | ||
792 | fail4: | |
e1074a0d | 793 | pci_release_region(efx->pci_dev, efx->type->mem_bar); |
8ceee660 | 794 | fail3: |
2c118e0f | 795 | efx->membase_phys = 0; |
8ceee660 BH |
796 | fail2: |
797 | pci_disable_device(efx->pci_dev); | |
798 | fail1: | |
799 | return rc; | |
800 | } | |
801 | ||
802 | static void efx_fini_io(struct efx_nic *efx) | |
803 | { | |
804 | EFX_LOG(efx, "shutting down I/O\n"); | |
805 | ||
806 | if (efx->membase) { | |
807 | iounmap(efx->membase); | |
808 | efx->membase = NULL; | |
809 | } | |
810 | ||
811 | if (efx->membase_phys) { | |
812 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 813 | efx->membase_phys = 0; |
8ceee660 BH |
814 | } |
815 | ||
816 | pci_disable_device(efx->pci_dev); | |
817 | } | |
818 | ||
46123d04 BH |
819 | /* Get number of RX queues wanted. Return number of online CPU |
820 | * packages in the expectation that an IRQ balancer will spread | |
821 | * interrupts across them. */ | |
822 | static int efx_wanted_rx_queues(void) | |
823 | { | |
824 | cpumask_t core_mask; | |
825 | int count; | |
826 | int cpu; | |
827 | ||
828 | cpus_clear(core_mask); | |
829 | count = 0; | |
830 | for_each_online_cpu(cpu) { | |
831 | if (!cpu_isset(cpu, core_mask)) { | |
832 | ++count; | |
833 | cpus_or(core_mask, core_mask, | |
834 | topology_core_siblings(cpu)); | |
835 | } | |
836 | } | |
837 | ||
838 | return count; | |
839 | } | |
840 | ||
841 | /* Probe the number and type of interrupts we are able to obtain, and | |
842 | * the resulting numbers of channels and RX queues. | |
843 | */ | |
8ceee660 BH |
844 | static void efx_probe_interrupts(struct efx_nic *efx) |
845 | { | |
46123d04 BH |
846 | int max_channels = |
847 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
848 | int rc, i; |
849 | ||
850 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
851 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
852 | int wanted_ints; | |
28b581ab | 853 | int rx_queues; |
aa6ef27e | 854 | |
46123d04 BH |
855 | /* We want one RX queue and interrupt per CPU package |
856 | * (or as specified by the rss_cpus module parameter). | |
857 | * We will need one channel per interrupt. | |
858 | */ | |
28b581ab NT |
859 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
860 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
861 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 862 | |
28b581ab | 863 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 864 | xentries[i].entry = i; |
28b581ab | 865 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 866 | if (rc > 0) { |
28b581ab NT |
867 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
868 | " available (%d < %d).\n", rc, wanted_ints); | |
869 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
870 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
871 | wanted_ints = rc; | |
8ceee660 | 872 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 873 | wanted_ints); |
8ceee660 BH |
874 | } |
875 | ||
876 | if (rc == 0) { | |
28b581ab NT |
877 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
878 | efx->n_channels = wanted_ints; | |
879 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 880 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
881 | } else { |
882 | /* Fall back to single channel MSI */ | |
883 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
884 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
885 | } | |
886 | } | |
887 | ||
888 | /* Try single interrupt MSI */ | |
889 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 890 | efx->n_rx_queues = 1; |
28b581ab | 891 | efx->n_channels = 1; |
8ceee660 BH |
892 | rc = pci_enable_msi(efx->pci_dev); |
893 | if (rc == 0) { | |
894 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
895 | } else { |
896 | EFX_ERR(efx, "could not enable MSI\n"); | |
897 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
898 | } | |
899 | } | |
900 | ||
901 | /* Assume legacy interrupts */ | |
902 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 903 | efx->n_rx_queues = 1; |
28b581ab | 904 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
905 | efx->legacy_irq = efx->pci_dev->irq; |
906 | } | |
907 | } | |
908 | ||
909 | static void efx_remove_interrupts(struct efx_nic *efx) | |
910 | { | |
911 | struct efx_channel *channel; | |
912 | ||
913 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 914 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
915 | channel->irq = 0; |
916 | pci_disable_msi(efx->pci_dev); | |
917 | pci_disable_msix(efx->pci_dev); | |
918 | ||
919 | /* Remove legacy interrupt */ | |
920 | efx->legacy_irq = 0; | |
921 | } | |
922 | ||
8831da7b | 923 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
924 | { |
925 | struct efx_tx_queue *tx_queue; | |
926 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 927 | |
60ac1065 | 928 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
929 | if (separate_tx_channels) |
930 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
931 | else |
932 | tx_queue->channel = &efx->channel[0]; | |
933 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
934 | } | |
8ceee660 | 935 | |
8831da7b BH |
936 | efx_for_each_rx_queue(rx_queue, efx) { |
937 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
938 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
939 | } |
940 | } | |
941 | ||
942 | static int efx_probe_nic(struct efx_nic *efx) | |
943 | { | |
944 | int rc; | |
945 | ||
946 | EFX_LOG(efx, "creating NIC\n"); | |
947 | ||
948 | /* Carry out hardware-type specific initialisation */ | |
949 | rc = falcon_probe_nic(efx); | |
950 | if (rc) | |
951 | return rc; | |
952 | ||
953 | /* Determine the number of channels and RX queues by trying to hook | |
954 | * in MSI-X interrupts. */ | |
955 | efx_probe_interrupts(efx); | |
956 | ||
8831da7b | 957 | efx_set_channels(efx); |
8ceee660 BH |
958 | |
959 | /* Initialise the interrupt moderation settings */ | |
960 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec); | |
961 | ||
962 | return 0; | |
963 | } | |
964 | ||
965 | static void efx_remove_nic(struct efx_nic *efx) | |
966 | { | |
967 | EFX_LOG(efx, "destroying NIC\n"); | |
968 | ||
969 | efx_remove_interrupts(efx); | |
970 | falcon_remove_nic(efx); | |
971 | } | |
972 | ||
973 | /************************************************************************** | |
974 | * | |
975 | * NIC startup/shutdown | |
976 | * | |
977 | *************************************************************************/ | |
978 | ||
979 | static int efx_probe_all(struct efx_nic *efx) | |
980 | { | |
981 | struct efx_channel *channel; | |
982 | int rc; | |
983 | ||
984 | /* Create NIC */ | |
985 | rc = efx_probe_nic(efx); | |
986 | if (rc) { | |
987 | EFX_ERR(efx, "failed to create NIC\n"); | |
988 | goto fail1; | |
989 | } | |
990 | ||
991 | /* Create port */ | |
992 | rc = efx_probe_port(efx); | |
993 | if (rc) { | |
994 | EFX_ERR(efx, "failed to create port\n"); | |
995 | goto fail2; | |
996 | } | |
997 | ||
998 | /* Create channels */ | |
999 | efx_for_each_channel(channel, efx) { | |
1000 | rc = efx_probe_channel(channel); | |
1001 | if (rc) { | |
1002 | EFX_ERR(efx, "failed to create channel %d\n", | |
1003 | channel->channel); | |
1004 | goto fail3; | |
1005 | } | |
1006 | } | |
56536e9c | 1007 | efx_set_channel_names(efx); |
8ceee660 BH |
1008 | |
1009 | return 0; | |
1010 | ||
1011 | fail3: | |
1012 | efx_for_each_channel(channel, efx) | |
1013 | efx_remove_channel(channel); | |
1014 | efx_remove_port(efx); | |
1015 | fail2: | |
1016 | efx_remove_nic(efx); | |
1017 | fail1: | |
1018 | return rc; | |
1019 | } | |
1020 | ||
1021 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1022 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1023 | * and ensures that the port is scheduled to be reconfigured. | |
1024 | * This function is safe to call multiple times when the NIC is in any | |
1025 | * state. */ | |
1026 | static void efx_start_all(struct efx_nic *efx) | |
1027 | { | |
1028 | struct efx_channel *channel; | |
1029 | ||
1030 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1031 | ||
1032 | /* Check that it is appropriate to restart the interface. All | |
1033 | * of these flags are safe to read under just the rtnl lock */ | |
1034 | if (efx->port_enabled) | |
1035 | return; | |
1036 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1037 | return; | |
55668611 | 1038 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1039 | return; |
1040 | ||
1041 | /* Mark the port as enabled so port reconfigurations can start, then | |
1042 | * restart the transmit interface early so the watchdog timer stops */ | |
1043 | efx_start_port(efx); | |
dacccc74 SH |
1044 | if (efx_dev_registered(efx)) |
1045 | efx_wake_queue(efx); | |
8ceee660 BH |
1046 | |
1047 | efx_for_each_channel(channel, efx) | |
1048 | efx_start_channel(channel); | |
1049 | ||
1050 | falcon_enable_interrupts(efx); | |
1051 | ||
1052 | /* Start hardware monitor if we're in RUNNING */ | |
1053 | if (efx->state == STATE_RUNNING) | |
1054 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1055 | efx_monitor_interval); | |
1056 | } | |
1057 | ||
1058 | /* Flush all delayed work. Should only be called when no more delayed work | |
1059 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1060 | * since we're holding the rtnl_lock at this point. */ | |
1061 | static void efx_flush_all(struct efx_nic *efx) | |
1062 | { | |
1063 | struct efx_rx_queue *rx_queue; | |
1064 | ||
1065 | /* Make sure the hardware monitor is stopped */ | |
1066 | cancel_delayed_work_sync(&efx->monitor_work); | |
1067 | ||
1068 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1069 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1070 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1071 | |
1072 | /* Stop scheduled port reconfigurations */ | |
1073 | cancel_work_sync(&efx->reconfigure_work); | |
1074 | ||
1075 | } | |
1076 | ||
1077 | /* Quiesce hardware and software without bringing the link down. | |
1078 | * Safe to call multiple times, when the nic and interface is in any | |
1079 | * state. The caller is guaranteed to subsequently be in a position | |
1080 | * to modify any hardware and software state they see fit without | |
1081 | * taking locks. */ | |
1082 | static void efx_stop_all(struct efx_nic *efx) | |
1083 | { | |
1084 | struct efx_channel *channel; | |
1085 | ||
1086 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1087 | ||
1088 | /* port_enabled can be read safely under the rtnl lock */ | |
1089 | if (!efx->port_enabled) | |
1090 | return; | |
1091 | ||
1092 | /* Disable interrupts and wait for ISR to complete */ | |
1093 | falcon_disable_interrupts(efx); | |
1094 | if (efx->legacy_irq) | |
1095 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1096 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1097 | if (channel->irq) |
1098 | synchronize_irq(channel->irq); | |
b3475645 | 1099 | } |
8ceee660 BH |
1100 | |
1101 | /* Stop all NAPI processing and synchronous rx refills */ | |
1102 | efx_for_each_channel(channel, efx) | |
1103 | efx_stop_channel(channel); | |
1104 | ||
1105 | /* Stop all asynchronous port reconfigurations. Since all | |
1106 | * event processing has already been stopped, there is no | |
1107 | * window to loose phy events */ | |
1108 | efx_stop_port(efx); | |
1109 | ||
1110 | /* Flush reconfigure_work, refill_workqueue, monitor_work */ | |
1111 | efx_flush_all(efx); | |
1112 | ||
1113 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1114 | * flushes will complete in a timely fashion. */ | |
8ceee660 BH |
1115 | falcon_drain_tx_fifo(efx); |
1116 | ||
1117 | /* Stop the kernel transmit interface late, so the watchdog | |
1118 | * timer isn't ticking over the flush */ | |
55668611 | 1119 | if (efx_dev_registered(efx)) { |
dacccc74 | 1120 | efx_stop_queue(efx); |
8ceee660 BH |
1121 | netif_tx_lock_bh(efx->net_dev); |
1122 | netif_tx_unlock_bh(efx->net_dev); | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | static void efx_remove_all(struct efx_nic *efx) | |
1127 | { | |
1128 | struct efx_channel *channel; | |
1129 | ||
1130 | efx_for_each_channel(channel, efx) | |
1131 | efx_remove_channel(channel); | |
1132 | efx_remove_port(efx); | |
1133 | efx_remove_nic(efx); | |
1134 | } | |
1135 | ||
1136 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1137 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1138 | { |
8ceee660 BH |
1139 | EFX_ASSERT_RESET_SERIALISED(efx); |
1140 | ||
1141 | efx_stop_all(efx); | |
1142 | ||
1143 | efx_fini_channels(efx); | |
bc3c90a2 | 1144 | efx_init_channels(efx); |
8ceee660 BH |
1145 | |
1146 | efx_start_all(efx); | |
8ceee660 BH |
1147 | } |
1148 | ||
1149 | /************************************************************************** | |
1150 | * | |
1151 | * Interrupt moderation | |
1152 | * | |
1153 | **************************************************************************/ | |
1154 | ||
1155 | /* Set interrupt moderation parameters */ | |
1156 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs) | |
1157 | { | |
1158 | struct efx_tx_queue *tx_queue; | |
1159 | struct efx_rx_queue *rx_queue; | |
1160 | ||
1161 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1162 | ||
1163 | efx_for_each_tx_queue(tx_queue, efx) | |
1164 | tx_queue->channel->irq_moderation = tx_usecs; | |
1165 | ||
1166 | efx_for_each_rx_queue(rx_queue, efx) | |
1167 | rx_queue->channel->irq_moderation = rx_usecs; | |
1168 | } | |
1169 | ||
1170 | /************************************************************************** | |
1171 | * | |
1172 | * Hardware monitor | |
1173 | * | |
1174 | **************************************************************************/ | |
1175 | ||
1176 | /* Run periodically off the general workqueue. Serialised against | |
1177 | * efx_reconfigure_port via the mac_lock */ | |
1178 | static void efx_monitor(struct work_struct *data) | |
1179 | { | |
1180 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1181 | monitor_work.work); | |
1182 | int rc = 0; | |
1183 | ||
1184 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1185 | raw_smp_processor_id()); | |
1186 | ||
1187 | ||
1188 | /* If the mac_lock is already held then it is likely a port | |
1189 | * reconfiguration is already in place, which will likely do | |
1190 | * most of the work of check_hw() anyway. */ | |
1191 | if (!mutex_trylock(&efx->mac_lock)) { | |
1192 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1193 | efx_monitor_interval); | |
1194 | return; | |
1195 | } | |
1196 | ||
1197 | if (efx->port_enabled) | |
1198 | rc = falcon_check_xmac(efx); | |
1199 | mutex_unlock(&efx->mac_lock); | |
1200 | ||
8ceee660 BH |
1201 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1202 | efx_monitor_interval); | |
1203 | } | |
1204 | ||
1205 | /************************************************************************** | |
1206 | * | |
1207 | * ioctls | |
1208 | * | |
1209 | *************************************************************************/ | |
1210 | ||
1211 | /* Net device ioctl | |
1212 | * Context: process, rtnl_lock() held. | |
1213 | */ | |
1214 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1215 | { | |
767e468c | 1216 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1217 | |
1218 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1219 | ||
1220 | return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL); | |
1221 | } | |
1222 | ||
1223 | /************************************************************************** | |
1224 | * | |
1225 | * NAPI interface | |
1226 | * | |
1227 | **************************************************************************/ | |
1228 | ||
1229 | static int efx_init_napi(struct efx_nic *efx) | |
1230 | { | |
1231 | struct efx_channel *channel; | |
1232 | int rc; | |
1233 | ||
1234 | efx_for_each_channel(channel, efx) { | |
1235 | channel->napi_dev = efx->net_dev; | |
1236 | rc = efx_lro_init(&channel->lro_mgr, efx); | |
1237 | if (rc) | |
1238 | goto err; | |
1239 | } | |
1240 | return 0; | |
1241 | err: | |
1242 | efx_fini_napi(efx); | |
1243 | return rc; | |
1244 | } | |
1245 | ||
1246 | static void efx_fini_napi(struct efx_nic *efx) | |
1247 | { | |
1248 | struct efx_channel *channel; | |
1249 | ||
1250 | efx_for_each_channel(channel, efx) { | |
1251 | efx_lro_fini(&channel->lro_mgr); | |
1252 | channel->napi_dev = NULL; | |
1253 | } | |
1254 | } | |
1255 | ||
1256 | /************************************************************************** | |
1257 | * | |
1258 | * Kernel netpoll interface | |
1259 | * | |
1260 | *************************************************************************/ | |
1261 | ||
1262 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1263 | ||
1264 | /* Although in the common case interrupts will be disabled, this is not | |
1265 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1266 | * so no locking is required. | |
1267 | */ | |
1268 | static void efx_netpoll(struct net_device *net_dev) | |
1269 | { | |
767e468c | 1270 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1271 | struct efx_channel *channel; |
1272 | ||
64ee3120 | 1273 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1274 | efx_schedule_channel(channel); |
1275 | } | |
1276 | ||
1277 | #endif | |
1278 | ||
1279 | /************************************************************************** | |
1280 | * | |
1281 | * Kernel net device interface | |
1282 | * | |
1283 | *************************************************************************/ | |
1284 | ||
1285 | /* Context: process, rtnl_lock() held. */ | |
1286 | static int efx_net_open(struct net_device *net_dev) | |
1287 | { | |
767e468c | 1288 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1289 | EFX_ASSERT_RESET_SERIALISED(efx); |
1290 | ||
1291 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1292 | raw_smp_processor_id()); | |
1293 | ||
f8b87c17 BH |
1294 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1295 | return -EBUSY; | |
1296 | ||
8ceee660 BH |
1297 | efx_start_all(efx); |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | /* Context: process, rtnl_lock() held. | |
1302 | * Note that the kernel will ignore our return code; this method | |
1303 | * should really be a void. | |
1304 | */ | |
1305 | static int efx_net_stop(struct net_device *net_dev) | |
1306 | { | |
767e468c | 1307 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1308 | |
1309 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1310 | raw_smp_processor_id()); | |
1311 | ||
1312 | /* Stop the device and flush all the channels */ | |
1313 | efx_stop_all(efx); | |
1314 | efx_fini_channels(efx); | |
bc3c90a2 | 1315 | efx_init_channels(efx); |
8ceee660 BH |
1316 | |
1317 | return 0; | |
1318 | } | |
1319 | ||
5b9e207c | 1320 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1321 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1322 | { | |
767e468c | 1323 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1324 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1325 | struct net_device_stats *stats = &net_dev->stats; | |
1326 | ||
5b9e207c BH |
1327 | /* Update stats if possible, but do not wait if another thread |
1328 | * is updating them (or resetting the NIC); slightly stale | |
1329 | * stats are acceptable. | |
1330 | */ | |
8ceee660 BH |
1331 | if (!spin_trylock(&efx->stats_lock)) |
1332 | return stats; | |
8c8661e4 | 1333 | if (efx->stats_enabled) { |
8ceee660 BH |
1334 | falcon_update_stats_xmac(efx); |
1335 | falcon_update_nic_stats(efx); | |
1336 | } | |
1337 | spin_unlock(&efx->stats_lock); | |
1338 | ||
1339 | stats->rx_packets = mac_stats->rx_packets; | |
1340 | stats->tx_packets = mac_stats->tx_packets; | |
1341 | stats->rx_bytes = mac_stats->rx_bytes; | |
1342 | stats->tx_bytes = mac_stats->tx_bytes; | |
1343 | stats->multicast = mac_stats->rx_multicast; | |
1344 | stats->collisions = mac_stats->tx_collision; | |
1345 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1346 | mac_stats->rx_length_error); | |
1347 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1348 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1349 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1350 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1351 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1352 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1353 | ||
1354 | stats->rx_errors = (stats->rx_length_errors + | |
1355 | stats->rx_over_errors + | |
1356 | stats->rx_crc_errors + | |
1357 | stats->rx_frame_errors + | |
1358 | stats->rx_fifo_errors + | |
1359 | stats->rx_missed_errors + | |
1360 | mac_stats->rx_symbol_error); | |
1361 | stats->tx_errors = (stats->tx_window_errors + | |
1362 | mac_stats->tx_bad); | |
1363 | ||
1364 | return stats; | |
1365 | } | |
1366 | ||
1367 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1368 | static void efx_watchdog(struct net_device *net_dev) | |
1369 | { | |
767e468c | 1370 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1371 | |
739bb23d BH |
1372 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1373 | " resetting channels\n", | |
1374 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1375 | |
739bb23d | 1376 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1377 | } |
1378 | ||
1379 | ||
1380 | /* Context: process, rtnl_lock() held. */ | |
1381 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1382 | { | |
767e468c | 1383 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1384 | int rc = 0; |
1385 | ||
1386 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1387 | ||
1388 | if (new_mtu > EFX_MAX_MTU) | |
1389 | return -EINVAL; | |
1390 | ||
1391 | efx_stop_all(efx); | |
1392 | ||
1393 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1394 | ||
1395 | efx_fini_channels(efx); | |
1396 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1397 | efx_init_channels(efx); |
8ceee660 BH |
1398 | |
1399 | efx_start_all(efx); | |
1400 | return rc; | |
8ceee660 BH |
1401 | } |
1402 | ||
1403 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1404 | { | |
767e468c | 1405 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1406 | struct sockaddr *addr = data; |
1407 | char *new_addr = addr->sa_data; | |
1408 | ||
1409 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1410 | ||
1411 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1412 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1413 | new_addr); | |
8ceee660 BH |
1414 | return -EINVAL; |
1415 | } | |
1416 | ||
1417 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1418 | ||
1419 | /* Reconfigure the MAC */ | |
1420 | efx_reconfigure_port(efx); | |
1421 | ||
1422 | return 0; | |
1423 | } | |
1424 | ||
a816f75a | 1425 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1426 | static void efx_set_multicast_list(struct net_device *net_dev) |
1427 | { | |
767e468c | 1428 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1429 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1430 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1431 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1432 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1433 | u32 crc; |
1434 | int bit; | |
1435 | int i; | |
1436 | ||
a816f75a | 1437 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1438 | |
1439 | /* Build multicast hash table */ | |
1440 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1441 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1442 | } else { | |
1443 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1444 | for (i = 0; i < net_dev->mc_count; i++) { | |
1445 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1446 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1447 | set_bit_le(bit, mc_hash->byte); | |
1448 | mc_list = mc_list->next; | |
1449 | } | |
1450 | } | |
1451 | ||
a816f75a BH |
1452 | if (!efx->port_enabled) |
1453 | /* Delay pushing settings until efx_start_port() */ | |
1454 | return; | |
1455 | ||
1456 | if (changed) | |
1457 | queue_work(efx->workqueue, &efx->reconfigure_work); | |
1458 | ||
8ceee660 BH |
1459 | /* Create and activate new global multicast hash table */ |
1460 | falcon_set_multicast_hash(efx); | |
1461 | } | |
1462 | ||
c3ecb9f3 SH |
1463 | static const struct net_device_ops efx_netdev_ops = { |
1464 | .ndo_open = efx_net_open, | |
1465 | .ndo_stop = efx_net_stop, | |
1466 | .ndo_get_stats = efx_net_stats, | |
1467 | .ndo_tx_timeout = efx_watchdog, | |
1468 | .ndo_start_xmit = efx_hard_start_xmit, | |
1469 | .ndo_validate_addr = eth_validate_addr, | |
1470 | .ndo_do_ioctl = efx_ioctl, | |
1471 | .ndo_change_mtu = efx_change_mtu, | |
1472 | .ndo_set_mac_address = efx_set_mac_address, | |
1473 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1474 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1475 | .ndo_poll_controller = efx_netpoll, | |
1476 | #endif | |
1477 | }; | |
1478 | ||
8ceee660 BH |
1479 | static int efx_netdev_event(struct notifier_block *this, |
1480 | unsigned long event, void *ptr) | |
1481 | { | |
d3208b5e | 1482 | struct net_device *net_dev = ptr; |
8ceee660 | 1483 | |
c3ecb9f3 | 1484 | if (net_dev->netdev_ops == &efx_netdev_ops && event == NETDEV_CHANGENAME) { |
767e468c | 1485 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1486 | |
1487 | strcpy(efx->name, net_dev->name); | |
f4150724 | 1488 | efx_mtd_rename(efx); |
56536e9c | 1489 | efx_set_channel_names(efx); |
8ceee660 BH |
1490 | } |
1491 | ||
1492 | return NOTIFY_DONE; | |
1493 | } | |
1494 | ||
1495 | static struct notifier_block efx_netdev_notifier = { | |
1496 | .notifier_call = efx_netdev_event, | |
1497 | }; | |
1498 | ||
1499 | static int efx_register_netdev(struct efx_nic *efx) | |
1500 | { | |
1501 | struct net_device *net_dev = efx->net_dev; | |
1502 | int rc; | |
1503 | ||
1504 | net_dev->watchdog_timeo = 5 * HZ; | |
1505 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1506 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1507 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1508 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1509 | ||
1510 | /* Always start with carrier off; PHY events will detect the link */ | |
1511 | netif_carrier_off(efx->net_dev); | |
1512 | ||
1513 | /* Clear MAC statistics */ | |
1514 | falcon_update_stats_xmac(efx); | |
1515 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); | |
1516 | ||
1517 | rc = register_netdev(net_dev); | |
1518 | if (rc) { | |
1519 | EFX_ERR(efx, "could not register net dev\n"); | |
1520 | return rc; | |
1521 | } | |
1522 | strcpy(efx->name, net_dev->name); | |
56536e9c | 1523 | efx_set_channel_names(efx); |
8ceee660 BH |
1524 | |
1525 | return 0; | |
1526 | } | |
1527 | ||
1528 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1529 | { | |
1530 | struct efx_tx_queue *tx_queue; | |
1531 | ||
1532 | if (!efx->net_dev) | |
1533 | return; | |
1534 | ||
767e468c | 1535 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1536 | |
1537 | /* Free up any skbs still remaining. This has to happen before | |
1538 | * we try to unregister the netdev as running their destructors | |
1539 | * may be needed to get the device ref. count to 0. */ | |
1540 | efx_for_each_tx_queue(tx_queue, efx) | |
1541 | efx_release_tx_buffers(tx_queue); | |
1542 | ||
55668611 | 1543 | if (efx_dev_registered(efx)) { |
8ceee660 BH |
1544 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
1545 | unregister_netdev(efx->net_dev); | |
1546 | } | |
1547 | } | |
1548 | ||
1549 | /************************************************************************** | |
1550 | * | |
1551 | * Device reset and suspend | |
1552 | * | |
1553 | **************************************************************************/ | |
1554 | ||
2467ca46 BH |
1555 | /* Tears down the entire software state and most of the hardware state |
1556 | * before reset. */ | |
8c8661e4 | 1557 | void efx_reset_down(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
8ceee660 BH |
1558 | { |
1559 | int rc; | |
1560 | ||
1561 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1562 | ||
2467ca46 BH |
1563 | /* The net_dev->get_stats handler is quite slow, and will fail |
1564 | * if a fetch is pending over reset. Serialise against it. */ | |
1565 | spin_lock(&efx->stats_lock); | |
8c8661e4 | 1566 | efx->stats_enabled = false; |
2467ca46 BH |
1567 | spin_unlock(&efx->stats_lock); |
1568 | ||
1569 | efx_stop_all(efx); | |
1570 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1571 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1572 | |
8ceee660 | 1573 | rc = falcon_xmac_get_settings(efx, ecmd); |
2467ca46 | 1574 | if (rc) |
8ceee660 | 1575 | EFX_ERR(efx, "could not back up PHY settings\n"); |
8ceee660 BH |
1576 | |
1577 | efx_fini_channels(efx); | |
8ceee660 BH |
1578 | } |
1579 | ||
2467ca46 BH |
1580 | /* This function will always ensure that the locks acquired in |
1581 | * efx_reset_down() are released. A failure return code indicates | |
1582 | * that we were unable to reinitialise the hardware, and the | |
1583 | * driver should be disabled. If ok is false, then the rx and tx | |
1584 | * engines are not restarted, pending a RESET_DISABLE. */ | |
8c8661e4 | 1585 | int efx_reset_up(struct efx_nic *efx, struct ethtool_cmd *ecmd, bool ok) |
8ceee660 BH |
1586 | { |
1587 | int rc; | |
1588 | ||
2467ca46 | 1589 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1590 | |
2467ca46 | 1591 | rc = falcon_init_nic(efx); |
8ceee660 | 1592 | if (rc) { |
2467ca46 BH |
1593 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1594 | ok = false; | |
8ceee660 BH |
1595 | } |
1596 | ||
2467ca46 BH |
1597 | if (ok) { |
1598 | efx_init_channels(efx); | |
8ceee660 | 1599 | |
2467ca46 BH |
1600 | if (falcon_xmac_set_settings(efx, ecmd)) |
1601 | EFX_ERR(efx, "could not restore PHY settings\n"); | |
1602 | } | |
1603 | ||
f4150724 | 1604 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1605 | mutex_unlock(&efx->mac_lock); |
1606 | ||
8c8661e4 | 1607 | if (ok) { |
2467ca46 | 1608 | efx_start_all(efx); |
8c8661e4 BH |
1609 | efx->stats_enabled = true; |
1610 | } | |
8ceee660 BH |
1611 | return rc; |
1612 | } | |
1613 | ||
1614 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1615 | * Note that the reset may fail, in which case the card will be left | |
1616 | * in a most-probably-unusable state. | |
1617 | * | |
1618 | * This function will sleep. You cannot reset from within an atomic | |
1619 | * state; use efx_schedule_reset() instead. | |
1620 | * | |
1621 | * Grabs the rtnl_lock. | |
1622 | */ | |
1623 | static int efx_reset(struct efx_nic *efx) | |
1624 | { | |
1625 | struct ethtool_cmd ecmd; | |
1626 | enum reset_type method = efx->reset_pending; | |
1627 | int rc; | |
1628 | ||
1629 | /* Serialise with kernel interfaces */ | |
1630 | rtnl_lock(); | |
1631 | ||
1632 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1633 | * flag set so that efx_pci_probe_main will be retried */ | |
1634 | if (efx->state != STATE_RUNNING) { | |
1635 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
1636 | goto unlock_rtnl; | |
1637 | } | |
1638 | ||
8ceee660 BH |
1639 | EFX_INFO(efx, "resetting (%d)\n", method); |
1640 | ||
2467ca46 | 1641 | efx_reset_down(efx, &ecmd); |
8ceee660 BH |
1642 | |
1643 | rc = falcon_reset_hw(efx, method); | |
1644 | if (rc) { | |
1645 | EFX_ERR(efx, "failed to reset hardware\n"); | |
2467ca46 | 1646 | goto fail; |
8ceee660 BH |
1647 | } |
1648 | ||
1649 | /* Allow resets to be rescheduled. */ | |
1650 | efx->reset_pending = RESET_TYPE_NONE; | |
1651 | ||
1652 | /* Reinitialise bus-mastering, which may have been turned off before | |
1653 | * the reset was scheduled. This is still appropriate, even in the | |
1654 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1655 | * can respond to requests. */ | |
1656 | pci_set_master(efx->pci_dev); | |
1657 | ||
8ceee660 BH |
1658 | /* Leave device stopped if necessary */ |
1659 | if (method == RESET_TYPE_DISABLE) { | |
8ceee660 | 1660 | rc = -EIO; |
2467ca46 | 1661 | goto fail; |
8ceee660 BH |
1662 | } |
1663 | ||
2467ca46 | 1664 | rc = efx_reset_up(efx, &ecmd, true); |
8ceee660 | 1665 | if (rc) |
2467ca46 | 1666 | goto disable; |
8ceee660 | 1667 | |
8ceee660 | 1668 | EFX_LOG(efx, "reset complete\n"); |
8ceee660 BH |
1669 | unlock_rtnl: |
1670 | rtnl_unlock(); | |
1671 | return 0; | |
1672 | ||
2467ca46 BH |
1673 | fail: |
1674 | efx_reset_up(efx, &ecmd, false); | |
1675 | disable: | |
8ceee660 BH |
1676 | EFX_ERR(efx, "has been disabled\n"); |
1677 | efx->state = STATE_DISABLED; | |
1678 | ||
8ceee660 BH |
1679 | rtnl_unlock(); |
1680 | efx_unregister_netdev(efx); | |
1681 | efx_fini_port(efx); | |
1682 | return rc; | |
1683 | } | |
1684 | ||
1685 | /* The worker thread exists so that code that cannot sleep can | |
1686 | * schedule a reset for later. | |
1687 | */ | |
1688 | static void efx_reset_work(struct work_struct *data) | |
1689 | { | |
1690 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1691 | ||
1692 | efx_reset(nic); | |
1693 | } | |
1694 | ||
1695 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1696 | { | |
1697 | enum reset_type method; | |
1698 | ||
1699 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1700 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1701 | return; | |
1702 | } | |
1703 | ||
1704 | switch (type) { | |
1705 | case RESET_TYPE_INVISIBLE: | |
1706 | case RESET_TYPE_ALL: | |
1707 | case RESET_TYPE_WORLD: | |
1708 | case RESET_TYPE_DISABLE: | |
1709 | method = type; | |
1710 | break; | |
1711 | case RESET_TYPE_RX_RECOVERY: | |
1712 | case RESET_TYPE_RX_DESC_FETCH: | |
1713 | case RESET_TYPE_TX_DESC_FETCH: | |
1714 | case RESET_TYPE_TX_SKIP: | |
1715 | method = RESET_TYPE_INVISIBLE; | |
1716 | break; | |
1717 | default: | |
1718 | method = RESET_TYPE_ALL; | |
1719 | break; | |
1720 | } | |
1721 | ||
1722 | if (method != type) | |
1723 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1724 | else | |
1725 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1726 | ||
1727 | efx->reset_pending = method; | |
1728 | ||
1ab00629 | 1729 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1730 | } |
1731 | ||
1732 | /************************************************************************** | |
1733 | * | |
1734 | * List of NICs we support | |
1735 | * | |
1736 | **************************************************************************/ | |
1737 | ||
1738 | /* PCI device ID table */ | |
1739 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1740 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1741 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1742 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1743 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1744 | {0} /* end of list */ | |
1745 | }; | |
1746 | ||
1747 | /************************************************************************** | |
1748 | * | |
1749 | * Dummy PHY/MAC/Board operations | |
1750 | * | |
01aad7b6 | 1751 | * Can be used for some unimplemented operations |
8ceee660 BH |
1752 | * Needed so all function pointers are valid and do not have to be tested |
1753 | * before use | |
1754 | * | |
1755 | **************************************************************************/ | |
1756 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1757 | { | |
1758 | return 0; | |
1759 | } | |
1760 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1761 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 BH |
1762 | |
1763 | static struct efx_phy_operations efx_dummy_phy_operations = { | |
1764 | .init = efx_port_dummy_op_int, | |
1765 | .reconfigure = efx_port_dummy_op_void, | |
1766 | .check_hw = efx_port_dummy_op_int, | |
1767 | .fini = efx_port_dummy_op_void, | |
1768 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1769 | }; |
1770 | ||
8ceee660 | 1771 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 BH |
1772 | .init = efx_port_dummy_op_int, |
1773 | .init_leds = efx_port_dummy_op_int, | |
1774 | .set_fault_led = efx_port_dummy_op_blink, | |
a17102b1 | 1775 | .monitor = efx_port_dummy_op_int, |
01aad7b6 BH |
1776 | .blink = efx_port_dummy_op_blink, |
1777 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1778 | }; |
1779 | ||
1780 | /************************************************************************** | |
1781 | * | |
1782 | * Data housekeeping | |
1783 | * | |
1784 | **************************************************************************/ | |
1785 | ||
1786 | /* This zeroes out and then fills in the invariants in a struct | |
1787 | * efx_nic (including all sub-structures). | |
1788 | */ | |
1789 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1790 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1791 | { | |
1792 | struct efx_channel *channel; | |
1793 | struct efx_tx_queue *tx_queue; | |
1794 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1795 | int i; |
8ceee660 BH |
1796 | |
1797 | /* Initialise common structures */ | |
1798 | memset(efx, 0, sizeof(*efx)); | |
1799 | spin_lock_init(&efx->biu_lock); | |
1800 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1801 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1802 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1803 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1804 | efx->pci_dev = pci_dev; | |
1805 | efx->state = STATE_INIT; | |
1806 | efx->reset_pending = RESET_TYPE_NONE; | |
1807 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1808 | efx->board_info = efx_dummy_board_info; | |
1809 | ||
1810 | efx->net_dev = net_dev; | |
dc8cfa55 | 1811 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1812 | spin_lock_init(&efx->netif_stop_lock); |
1813 | spin_lock_init(&efx->stats_lock); | |
1814 | mutex_init(&efx->mac_lock); | |
1815 | efx->phy_op = &efx_dummy_phy_operations; | |
1816 | efx->mii.dev = net_dev; | |
1817 | INIT_WORK(&efx->reconfigure_work, efx_reconfigure_work); | |
1818 | atomic_set(&efx->netif_stop_count, 1); | |
1819 | ||
1820 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1821 | channel = &efx->channel[i]; | |
1822 | channel->efx = efx; | |
1823 | channel->channel = i; | |
dc8cfa55 | 1824 | channel->work_pending = false; |
8ceee660 | 1825 | } |
60ac1065 | 1826 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1827 | tx_queue = &efx->tx_queue[i]; |
1828 | tx_queue->efx = efx; | |
1829 | tx_queue->queue = i; | |
1830 | tx_queue->buffer = NULL; | |
1831 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1832 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1833 | } |
1834 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1835 | rx_queue = &efx->rx_queue[i]; | |
1836 | rx_queue->efx = efx; | |
1837 | rx_queue->queue = i; | |
1838 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1839 | rx_queue->buffer = NULL; | |
1840 | spin_lock_init(&rx_queue->add_lock); | |
1841 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1842 | } | |
1843 | ||
1844 | efx->type = type; | |
1845 | ||
1846 | /* Sanity-check NIC type */ | |
1847 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1848 | (efx->type->txd_ring_mask + 1)); | |
1849 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1850 | (efx->type->rxd_ring_mask + 1)); | |
1851 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1852 | (efx->type->evq_size - 1)); | |
1853 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1854 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1855 | (efx->type->txd_ring_mask + 1 + | |
1856 | efx->type->rxd_ring_mask + 1)); | |
1857 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1858 | ||
1859 | /* Higher numbered interrupt modes are less capable! */ | |
1860 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1861 | interrupt_mode); | |
1862 | ||
1863 | efx->workqueue = create_singlethread_workqueue("sfc_work"); | |
1ab00629 SH |
1864 | if (!efx->workqueue) |
1865 | return -ENOMEM; | |
8d9853d9 | 1866 | |
8ceee660 | 1867 | return 0; |
8ceee660 BH |
1868 | } |
1869 | ||
1870 | static void efx_fini_struct(struct efx_nic *efx) | |
1871 | { | |
1872 | if (efx->workqueue) { | |
1873 | destroy_workqueue(efx->workqueue); | |
1874 | efx->workqueue = NULL; | |
1875 | } | |
1876 | } | |
1877 | ||
1878 | /************************************************************************** | |
1879 | * | |
1880 | * PCI interface | |
1881 | * | |
1882 | **************************************************************************/ | |
1883 | ||
1884 | /* Main body of final NIC shutdown code | |
1885 | * This is called only at module unload (or hotplug removal). | |
1886 | */ | |
1887 | static void efx_pci_remove_main(struct efx_nic *efx) | |
1888 | { | |
1889 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1890 | ||
1891 | /* Skip everything if we never obtained a valid membase */ | |
1892 | if (!efx->membase) | |
1893 | return; | |
1894 | ||
1895 | efx_fini_channels(efx); | |
1896 | efx_fini_port(efx); | |
1897 | ||
1898 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 1899 | efx->board_info.fini(efx); |
8ceee660 BH |
1900 | falcon_fini_interrupt(efx); |
1901 | ||
1902 | efx_fini_napi(efx); | |
1903 | efx_remove_all(efx); | |
1904 | } | |
1905 | ||
1906 | /* Final NIC shutdown | |
1907 | * This is called only at module unload (or hotplug removal). | |
1908 | */ | |
1909 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
1910 | { | |
1911 | struct efx_nic *efx; | |
1912 | ||
1913 | efx = pci_get_drvdata(pci_dev); | |
1914 | if (!efx) | |
1915 | return; | |
1916 | ||
f4150724 BH |
1917 | efx_mtd_remove(efx); |
1918 | ||
8ceee660 BH |
1919 | /* Mark the NIC as fini, then stop the interface */ |
1920 | rtnl_lock(); | |
1921 | efx->state = STATE_FINI; | |
1922 | dev_close(efx->net_dev); | |
1923 | ||
1924 | /* Allow any queued efx_resets() to complete */ | |
1925 | rtnl_unlock(); | |
1926 | ||
1927 | if (efx->membase == NULL) | |
1928 | goto out; | |
1929 | ||
1930 | efx_unregister_netdev(efx); | |
1931 | ||
1932 | /* Wait for any scheduled resets to complete. No more will be | |
1933 | * scheduled from this point because efx_stop_all() has been | |
1934 | * called, we are no longer registered with driverlink, and | |
1935 | * the net_device's have been removed. */ | |
1ab00629 | 1936 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
1937 | |
1938 | efx_pci_remove_main(efx); | |
1939 | ||
1940 | out: | |
1941 | efx_fini_io(efx); | |
1942 | EFX_LOG(efx, "shutdown successful\n"); | |
1943 | ||
1944 | pci_set_drvdata(pci_dev, NULL); | |
1945 | efx_fini_struct(efx); | |
1946 | free_netdev(efx->net_dev); | |
1947 | }; | |
1948 | ||
1949 | /* Main body of NIC initialisation | |
1950 | * This is called at module load (or hotplug insertion, theoretically). | |
1951 | */ | |
1952 | static int efx_pci_probe_main(struct efx_nic *efx) | |
1953 | { | |
1954 | int rc; | |
1955 | ||
1956 | /* Do start-of-day initialisation */ | |
1957 | rc = efx_probe_all(efx); | |
1958 | if (rc) | |
1959 | goto fail1; | |
1960 | ||
1961 | rc = efx_init_napi(efx); | |
1962 | if (rc) | |
1963 | goto fail2; | |
1964 | ||
1965 | /* Initialise the board */ | |
1966 | rc = efx->board_info.init(efx); | |
1967 | if (rc) { | |
1968 | EFX_ERR(efx, "failed to initialise board\n"); | |
1969 | goto fail3; | |
1970 | } | |
1971 | ||
1972 | rc = falcon_init_nic(efx); | |
1973 | if (rc) { | |
1974 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
1975 | goto fail4; | |
1976 | } | |
1977 | ||
1978 | rc = efx_init_port(efx); | |
1979 | if (rc) { | |
1980 | EFX_ERR(efx, "failed to initialise port\n"); | |
1981 | goto fail5; | |
1982 | } | |
1983 | ||
bc3c90a2 | 1984 | efx_init_channels(efx); |
8ceee660 BH |
1985 | |
1986 | rc = falcon_init_interrupt(efx); | |
1987 | if (rc) | |
bc3c90a2 | 1988 | goto fail6; |
8ceee660 BH |
1989 | |
1990 | return 0; | |
1991 | ||
8ceee660 | 1992 | fail6: |
bc3c90a2 | 1993 | efx_fini_channels(efx); |
8ceee660 BH |
1994 | efx_fini_port(efx); |
1995 | fail5: | |
1996 | fail4: | |
a17102b1 | 1997 | efx->board_info.fini(efx); |
8ceee660 BH |
1998 | fail3: |
1999 | efx_fini_napi(efx); | |
2000 | fail2: | |
2001 | efx_remove_all(efx); | |
2002 | fail1: | |
2003 | return rc; | |
2004 | } | |
2005 | ||
2006 | /* NIC initialisation | |
2007 | * | |
2008 | * This is called at module load (or hotplug insertion, | |
2009 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2010 | * sets up and registers the network devices with the kernel and hooks | |
2011 | * the interrupt service routine. It does not prepare the device for | |
2012 | * transmission; this is left to the first time one of the network | |
2013 | * interfaces is brought up (i.e. efx_net_open). | |
2014 | */ | |
2015 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2016 | const struct pci_device_id *entry) | |
2017 | { | |
2018 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2019 | struct net_device *net_dev; | |
2020 | struct efx_nic *efx; | |
2021 | int i, rc; | |
2022 | ||
2023 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2024 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2025 | if (!net_dev) | |
2026 | return -ENOMEM; | |
b9b39b62 BH |
2027 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2028 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 BH |
2029 | if (lro) |
2030 | net_dev->features |= NETIF_F_LRO; | |
28506563 BH |
2031 | /* Mask for features that also apply to VLAN devices */ |
2032 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2033 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2034 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2035 | pci_set_drvdata(pci_dev, efx); |
2036 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2037 | if (rc) | |
2038 | goto fail1; | |
2039 | ||
2040 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2041 | ||
2042 | /* Set up basic I/O (BAR mappings etc) */ | |
2043 | rc = efx_init_io(efx); | |
2044 | if (rc) | |
2045 | goto fail2; | |
2046 | ||
2047 | /* No serialisation is required with the reset path because | |
2048 | * we're in STATE_INIT. */ | |
2049 | for (i = 0; i < 5; i++) { | |
2050 | rc = efx_pci_probe_main(efx); | |
2051 | if (rc == 0) | |
2052 | break; | |
2053 | ||
2054 | /* Serialise against efx_reset(). No more resets will be | |
2055 | * scheduled since efx_stop_all() has been called, and we | |
2056 | * have not and never have been registered with either | |
2057 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2058 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2059 | |
2060 | /* Retry if a recoverably reset event has been scheduled */ | |
2061 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2062 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2063 | goto fail3; | |
2064 | ||
2065 | efx->reset_pending = RESET_TYPE_NONE; | |
2066 | } | |
2067 | ||
2068 | if (rc) { | |
2069 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2070 | goto fail4; | |
2071 | } | |
2072 | ||
2073 | /* Switch to the running state before we expose the device to | |
2074 | * the OS. This is to ensure that the initial gathering of | |
2075 | * MAC stats succeeds. */ | |
2076 | rtnl_lock(); | |
2077 | efx->state = STATE_RUNNING; | |
2078 | rtnl_unlock(); | |
2079 | ||
2080 | rc = efx_register_netdev(efx); | |
2081 | if (rc) | |
2082 | goto fail5; | |
2083 | ||
2084 | EFX_LOG(efx, "initialisation successful\n"); | |
2085 | ||
f4150724 | 2086 | efx_mtd_probe(efx); /* allowed to fail */ |
8ceee660 BH |
2087 | return 0; |
2088 | ||
2089 | fail5: | |
2090 | efx_pci_remove_main(efx); | |
2091 | fail4: | |
2092 | fail3: | |
2093 | efx_fini_io(efx); | |
2094 | fail2: | |
2095 | efx_fini_struct(efx); | |
2096 | fail1: | |
2097 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2098 | free_netdev(net_dev); | |
2099 | return rc; | |
2100 | } | |
2101 | ||
2102 | static struct pci_driver efx_pci_driver = { | |
2103 | .name = EFX_DRIVER_NAME, | |
2104 | .id_table = efx_pci_table, | |
2105 | .probe = efx_pci_probe, | |
2106 | .remove = efx_pci_remove, | |
2107 | }; | |
2108 | ||
2109 | /************************************************************************** | |
2110 | * | |
2111 | * Kernel module interface | |
2112 | * | |
2113 | *************************************************************************/ | |
2114 | ||
2115 | module_param(interrupt_mode, uint, 0444); | |
2116 | MODULE_PARM_DESC(interrupt_mode, | |
2117 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2118 | ||
2119 | static int __init efx_init_module(void) | |
2120 | { | |
2121 | int rc; | |
2122 | ||
2123 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2124 | ||
2125 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2126 | if (rc) | |
2127 | goto err_notifier; | |
2128 | ||
2129 | refill_workqueue = create_workqueue("sfc_refill"); | |
2130 | if (!refill_workqueue) { | |
2131 | rc = -ENOMEM; | |
2132 | goto err_refill; | |
2133 | } | |
1ab00629 SH |
2134 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2135 | if (!reset_workqueue) { | |
2136 | rc = -ENOMEM; | |
2137 | goto err_reset; | |
2138 | } | |
8ceee660 BH |
2139 | |
2140 | rc = pci_register_driver(&efx_pci_driver); | |
2141 | if (rc < 0) | |
2142 | goto err_pci; | |
2143 | ||
2144 | return 0; | |
2145 | ||
2146 | err_pci: | |
1ab00629 SH |
2147 | destroy_workqueue(reset_workqueue); |
2148 | err_reset: | |
8ceee660 BH |
2149 | destroy_workqueue(refill_workqueue); |
2150 | err_refill: | |
2151 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2152 | err_notifier: | |
2153 | return rc; | |
2154 | } | |
2155 | ||
2156 | static void __exit efx_exit_module(void) | |
2157 | { | |
2158 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2159 | ||
2160 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2161 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2162 | destroy_workqueue(refill_workqueue); |
2163 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2164 | ||
2165 | } | |
2166 | ||
2167 | module_init(efx_init_module); | |
2168 | module_exit(efx_exit_module); | |
2169 | ||
2170 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2171 | "Solarflare Communications"); | |
2172 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2173 | MODULE_LICENSE("GPL"); | |
2174 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |