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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 | 23 | #include "net_driver.h" |
8ceee660 BH |
24 | #include "ethtool.h" |
25 | #include "tx.h" | |
26 | #include "rx.h" | |
27 | #include "efx.h" | |
28 | #include "mdio_10g.h" | |
29 | #include "falcon.h" | |
8ceee660 BH |
30 | |
31 | #define EFX_MAX_MTU (9 * 1024) | |
32 | ||
33 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
34 | * a work item is pushed onto this work queue to retry the allocation later, | |
35 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
36 | * workqueue, there is nothing to be gained in making it per NIC | |
37 | */ | |
38 | static struct workqueue_struct *refill_workqueue; | |
39 | ||
1ab00629 SH |
40 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
41 | * queued onto this work queue. This is not a per-nic work queue, because | |
42 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
43 | */ | |
44 | static struct workqueue_struct *reset_workqueue; | |
45 | ||
8ceee660 BH |
46 | /************************************************************************** |
47 | * | |
48 | * Configurable values | |
49 | * | |
50 | *************************************************************************/ | |
51 | ||
52 | /* | |
53 | * Enable large receive offload (LRO) aka soft segment reassembly (SSR) | |
54 | * | |
55 | * This sets the default for new devices. It can be controlled later | |
56 | * using ethtool. | |
57 | */ | |
dc8cfa55 | 58 | static int lro = true; |
8ceee660 BH |
59 | module_param(lro, int, 0644); |
60 | MODULE_PARM_DESC(lro, "Large receive offload acceleration"); | |
61 | ||
62 | /* | |
63 | * Use separate channels for TX and RX events | |
64 | * | |
28b581ab NT |
65 | * Set this to 1 to use separate channels for TX and RX. It allows us |
66 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 67 | * |
28b581ab | 68 | * This is only used in MSI-X interrupt mode |
8ceee660 | 69 | */ |
28b581ab NT |
70 | static unsigned int separate_tx_channels; |
71 | module_param(separate_tx_channels, uint, 0644); | |
72 | MODULE_PARM_DESC(separate_tx_channels, | |
73 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
74 | |
75 | /* This is the weight assigned to each of the (per-channel) virtual | |
76 | * NAPI devices. | |
77 | */ | |
78 | static int napi_weight = 64; | |
79 | ||
80 | /* This is the time (in jiffies) between invocations of the hardware | |
81 | * monitor, which checks for known hardware bugs and resets the | |
82 | * hardware and driver as necessary. | |
83 | */ | |
84 | unsigned int efx_monitor_interval = 1 * HZ; | |
85 | ||
8ceee660 BH |
86 | /* This controls whether or not the driver will initialise devices |
87 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
88 | * such devices will be initialised with a random locally-generated | |
89 | * MAC address. This allows for loading the sfc_mtd driver to | |
90 | * reprogram the flash, even if the flash contents (including the MAC | |
91 | * address) have previously been erased. | |
92 | */ | |
93 | static unsigned int allow_bad_hwaddr; | |
94 | ||
95 | /* Initial interrupt moderation settings. They can be modified after | |
96 | * module load with ethtool. | |
97 | * | |
98 | * The default for RX should strike a balance between increasing the | |
99 | * round-trip latency and reducing overhead. | |
100 | */ | |
101 | static unsigned int rx_irq_mod_usec = 60; | |
102 | ||
103 | /* Initial interrupt moderation settings. They can be modified after | |
104 | * module load with ethtool. | |
105 | * | |
106 | * This default is chosen to ensure that a 10G link does not go idle | |
107 | * while a TX queue is stopped after it has become full. A queue is | |
108 | * restarted when it drops below half full. The time this takes (assuming | |
109 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
110 | * 512 / 3 * 1.2 = 205 usec. | |
111 | */ | |
112 | static unsigned int tx_irq_mod_usec = 150; | |
113 | ||
114 | /* This is the first interrupt mode to try out of: | |
115 | * 0 => MSI-X | |
116 | * 1 => MSI | |
117 | * 2 => legacy | |
118 | */ | |
119 | static unsigned int interrupt_mode; | |
120 | ||
121 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
122 | * i.e. the number of CPUs among which we may distribute simultaneous | |
123 | * interrupt handling. | |
124 | * | |
125 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
126 | * The default (0) means to assign an interrupt to each package (level II cache) | |
127 | */ | |
128 | static unsigned int rss_cpus; | |
129 | module_param(rss_cpus, uint, 0444); | |
130 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
131 | ||
84ae48fe BH |
132 | static int phy_flash_cfg; |
133 | module_param(phy_flash_cfg, int, 0644); | |
134 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
135 | ||
6fb70fd1 BH |
136 | static unsigned irq_adapt_low_thresh = 10000; |
137 | module_param(irq_adapt_low_thresh, uint, 0644); | |
138 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
139 | "Threshold score for reducing IRQ moderation"); | |
140 | ||
141 | static unsigned irq_adapt_high_thresh = 20000; | |
142 | module_param(irq_adapt_high_thresh, uint, 0644); | |
143 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
144 | "Threshold score for increasing IRQ moderation"); | |
145 | ||
8ceee660 BH |
146 | /************************************************************************** |
147 | * | |
148 | * Utility functions and prototypes | |
149 | * | |
150 | *************************************************************************/ | |
151 | static void efx_remove_channel(struct efx_channel *channel); | |
152 | static void efx_remove_port(struct efx_nic *efx); | |
153 | static void efx_fini_napi(struct efx_nic *efx); | |
154 | static void efx_fini_channels(struct efx_nic *efx); | |
155 | ||
156 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
157 | do { \ | |
3c78708f | 158 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
159 | ASSERT_RTNL(); \ |
160 | } while (0) | |
161 | ||
162 | /************************************************************************** | |
163 | * | |
164 | * Event queue processing | |
165 | * | |
166 | *************************************************************************/ | |
167 | ||
168 | /* Process channel's event queue | |
169 | * | |
170 | * This function is responsible for processing the event queue of a | |
171 | * single channel. The caller must guarantee that this function will | |
172 | * never be concurrently called more than once on the same channel, | |
173 | * though different channels may be being processed concurrently. | |
174 | */ | |
4d566063 | 175 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 176 | { |
42cbe2d7 BH |
177 | struct efx_nic *efx = channel->efx; |
178 | int rx_packets; | |
8ceee660 | 179 | |
42cbe2d7 | 180 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 181 | !channel->enabled)) |
42cbe2d7 | 182 | return 0; |
8ceee660 | 183 | |
42cbe2d7 BH |
184 | rx_packets = falcon_process_eventq(channel, rx_quota); |
185 | if (rx_packets == 0) | |
186 | return 0; | |
8ceee660 BH |
187 | |
188 | /* Deliver last RX packet. */ | |
189 | if (channel->rx_pkt) { | |
190 | __efx_rx_packet(channel, channel->rx_pkt, | |
191 | channel->rx_pkt_csummed); | |
192 | channel->rx_pkt = NULL; | |
193 | } | |
194 | ||
8ceee660 BH |
195 | efx_rx_strategy(channel); |
196 | ||
42cbe2d7 | 197 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 198 | |
42cbe2d7 | 199 | return rx_packets; |
8ceee660 BH |
200 | } |
201 | ||
202 | /* Mark channel as finished processing | |
203 | * | |
204 | * Note that since we will not receive further interrupts for this | |
205 | * channel before we finish processing and call the eventq_read_ack() | |
206 | * method, there is no need to use the interrupt hold-off timers. | |
207 | */ | |
208 | static inline void efx_channel_processed(struct efx_channel *channel) | |
209 | { | |
5b9e207c BH |
210 | /* The interrupt handler for this channel may set work_pending |
211 | * as soon as we acknowledge the events we've seen. Make sure | |
212 | * it's cleared before then. */ | |
dc8cfa55 | 213 | channel->work_pending = false; |
5b9e207c BH |
214 | smp_wmb(); |
215 | ||
8ceee660 BH |
216 | falcon_eventq_read_ack(channel); |
217 | } | |
218 | ||
219 | /* NAPI poll handler | |
220 | * | |
221 | * NAPI guarantees serialisation of polls of the same device, which | |
222 | * provides the guarantee required by efx_process_channel(). | |
223 | */ | |
224 | static int efx_poll(struct napi_struct *napi, int budget) | |
225 | { | |
226 | struct efx_channel *channel = | |
227 | container_of(napi, struct efx_channel, napi_str); | |
8ceee660 BH |
228 | int rx_packets; |
229 | ||
230 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
231 | channel->channel, raw_smp_processor_id()); | |
232 | ||
42cbe2d7 | 233 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
234 | |
235 | if (rx_packets < budget) { | |
6fb70fd1 BH |
236 | struct efx_nic *efx = channel->efx; |
237 | ||
238 | if (channel->used_flags & EFX_USED_BY_RX && | |
239 | efx->irq_rx_adaptive && | |
240 | unlikely(++channel->irq_count == 1000)) { | |
241 | unsigned old_irq_moderation = channel->irq_moderation; | |
242 | ||
243 | if (unlikely(channel->irq_mod_score < | |
244 | irq_adapt_low_thresh)) { | |
245 | channel->irq_moderation = | |
246 | max_t(int, | |
247 | channel->irq_moderation - | |
248 | FALCON_IRQ_MOD_RESOLUTION, | |
249 | FALCON_IRQ_MOD_RESOLUTION); | |
250 | } else if (unlikely(channel->irq_mod_score > | |
251 | irq_adapt_high_thresh)) { | |
252 | channel->irq_moderation = | |
253 | min(channel->irq_moderation + | |
254 | FALCON_IRQ_MOD_RESOLUTION, | |
255 | efx->irq_rx_moderation); | |
256 | } | |
257 | ||
258 | if (channel->irq_moderation != old_irq_moderation) | |
259 | falcon_set_int_moderation(channel); | |
260 | ||
261 | channel->irq_count = 0; | |
262 | channel->irq_mod_score = 0; | |
263 | } | |
264 | ||
8ceee660 | 265 | /* There is no race here; although napi_disable() will |
288379f0 | 266 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
267 | * since efx_channel_processed() will have no effect if |
268 | * interrupts have already been disabled. | |
269 | */ | |
288379f0 | 270 | napi_complete(napi); |
8ceee660 BH |
271 | efx_channel_processed(channel); |
272 | } | |
273 | ||
274 | return rx_packets; | |
275 | } | |
276 | ||
277 | /* Process the eventq of the specified channel immediately on this CPU | |
278 | * | |
279 | * Disable hardware generated interrupts, wait for any existing | |
280 | * processing to finish, then directly poll (and ack ) the eventq. | |
281 | * Finally reenable NAPI and interrupts. | |
282 | * | |
283 | * Since we are touching interrupts the caller should hold the suspend lock | |
284 | */ | |
285 | void efx_process_channel_now(struct efx_channel *channel) | |
286 | { | |
287 | struct efx_nic *efx = channel->efx; | |
288 | ||
289 | BUG_ON(!channel->used_flags); | |
290 | BUG_ON(!channel->enabled); | |
291 | ||
292 | /* Disable interrupts and wait for ISRs to complete */ | |
293 | falcon_disable_interrupts(efx); | |
294 | if (efx->legacy_irq) | |
295 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 296 | if (channel->irq) |
8ceee660 BH |
297 | synchronize_irq(channel->irq); |
298 | ||
299 | /* Wait for any NAPI processing to complete */ | |
300 | napi_disable(&channel->napi_str); | |
301 | ||
302 | /* Poll the channel */ | |
91ad757c | 303 | efx_process_channel(channel, efx->type->evq_size); |
8ceee660 BH |
304 | |
305 | /* Ack the eventq. This may cause an interrupt to be generated | |
306 | * when they are reenabled */ | |
307 | efx_channel_processed(channel); | |
308 | ||
309 | napi_enable(&channel->napi_str); | |
310 | falcon_enable_interrupts(efx); | |
311 | } | |
312 | ||
313 | /* Create event queue | |
314 | * Event queue memory allocations are done only once. If the channel | |
315 | * is reset, the memory buffer will be reused; this guards against | |
316 | * errors during channel reset and also simplifies interrupt handling. | |
317 | */ | |
318 | static int efx_probe_eventq(struct efx_channel *channel) | |
319 | { | |
320 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
321 | ||
322 | return falcon_probe_eventq(channel); | |
323 | } | |
324 | ||
325 | /* Prepare channel's event queue */ | |
bc3c90a2 | 326 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
327 | { |
328 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
329 | ||
330 | channel->eventq_read_ptr = 0; | |
331 | ||
bc3c90a2 | 332 | falcon_init_eventq(channel); |
8ceee660 BH |
333 | } |
334 | ||
335 | static void efx_fini_eventq(struct efx_channel *channel) | |
336 | { | |
337 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
338 | ||
339 | falcon_fini_eventq(channel); | |
340 | } | |
341 | ||
342 | static void efx_remove_eventq(struct efx_channel *channel) | |
343 | { | |
344 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
345 | ||
346 | falcon_remove_eventq(channel); | |
347 | } | |
348 | ||
349 | /************************************************************************** | |
350 | * | |
351 | * Channel handling | |
352 | * | |
353 | *************************************************************************/ | |
354 | ||
8ceee660 BH |
355 | static int efx_probe_channel(struct efx_channel *channel) |
356 | { | |
357 | struct efx_tx_queue *tx_queue; | |
358 | struct efx_rx_queue *rx_queue; | |
359 | int rc; | |
360 | ||
361 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
362 | ||
363 | rc = efx_probe_eventq(channel); | |
364 | if (rc) | |
365 | goto fail1; | |
366 | ||
367 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
368 | rc = efx_probe_tx_queue(tx_queue); | |
369 | if (rc) | |
370 | goto fail2; | |
371 | } | |
372 | ||
373 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
374 | rc = efx_probe_rx_queue(rx_queue); | |
375 | if (rc) | |
376 | goto fail3; | |
377 | } | |
378 | ||
379 | channel->n_rx_frm_trunc = 0; | |
380 | ||
381 | return 0; | |
382 | ||
383 | fail3: | |
384 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
385 | efx_remove_rx_queue(rx_queue); | |
386 | fail2: | |
387 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
388 | efx_remove_tx_queue(tx_queue); | |
389 | fail1: | |
390 | return rc; | |
391 | } | |
392 | ||
393 | ||
56536e9c BH |
394 | static void efx_set_channel_names(struct efx_nic *efx) |
395 | { | |
396 | struct efx_channel *channel; | |
397 | const char *type = ""; | |
398 | int number; | |
399 | ||
400 | efx_for_each_channel(channel, efx) { | |
401 | number = channel->channel; | |
402 | if (efx->n_channels > efx->n_rx_queues) { | |
403 | if (channel->channel < efx->n_rx_queues) { | |
404 | type = "-rx"; | |
405 | } else { | |
406 | type = "-tx"; | |
407 | number -= efx->n_rx_queues; | |
408 | } | |
409 | } | |
410 | snprintf(channel->name, sizeof(channel->name), | |
411 | "%s%s-%d", efx->name, type, number); | |
412 | } | |
413 | } | |
414 | ||
8ceee660 BH |
415 | /* Channels are shutdown and reinitialised whilst the NIC is running |
416 | * to propagate configuration changes (mtu, checksum offload), or | |
417 | * to clear hardware error conditions | |
418 | */ | |
bc3c90a2 | 419 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
420 | { |
421 | struct efx_tx_queue *tx_queue; | |
422 | struct efx_rx_queue *rx_queue; | |
423 | struct efx_channel *channel; | |
8ceee660 | 424 | |
f7f13b0b BH |
425 | /* Calculate the rx buffer allocation parameters required to |
426 | * support the current MTU, including padding for header | |
427 | * alignment and overruns. | |
428 | */ | |
429 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
430 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
431 | efx->type->rx_buffer_padding); | |
432 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
433 | |
434 | /* Initialise the channels */ | |
435 | efx_for_each_channel(channel, efx) { | |
436 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
437 | ||
bc3c90a2 | 438 | efx_init_eventq(channel); |
8ceee660 | 439 | |
bc3c90a2 BH |
440 | efx_for_each_channel_tx_queue(tx_queue, channel) |
441 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
442 | |
443 | /* The rx buffer allocation strategy is MTU dependent */ | |
444 | efx_rx_strategy(channel); | |
445 | ||
bc3c90a2 BH |
446 | efx_for_each_channel_rx_queue(rx_queue, channel) |
447 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
448 | |
449 | WARN_ON(channel->rx_pkt != NULL); | |
450 | efx_rx_strategy(channel); | |
451 | } | |
8ceee660 BH |
452 | } |
453 | ||
454 | /* This enables event queue processing and packet transmission. | |
455 | * | |
456 | * Note that this function is not allowed to fail, since that would | |
457 | * introduce too much complexity into the suspend/resume path. | |
458 | */ | |
459 | static void efx_start_channel(struct efx_channel *channel) | |
460 | { | |
461 | struct efx_rx_queue *rx_queue; | |
462 | ||
463 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
464 | ||
5b9e207c BH |
465 | /* The interrupt handler for this channel may set work_pending |
466 | * as soon as we enable it. Make sure it's cleared before | |
467 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
468 | channel->work_pending = false; |
469 | channel->enabled = true; | |
5b9e207c | 470 | smp_wmb(); |
8ceee660 BH |
471 | |
472 | napi_enable(&channel->napi_str); | |
473 | ||
474 | /* Load up RX descriptors */ | |
475 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
476 | efx_fast_push_rx_descriptors(rx_queue); | |
477 | } | |
478 | ||
479 | /* This disables event queue processing and packet transmission. | |
480 | * This function does not guarantee that all queue processing | |
481 | * (e.g. RX refill) is complete. | |
482 | */ | |
483 | static void efx_stop_channel(struct efx_channel *channel) | |
484 | { | |
485 | struct efx_rx_queue *rx_queue; | |
486 | ||
487 | if (!channel->enabled) | |
488 | return; | |
489 | ||
490 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
491 | ||
dc8cfa55 | 492 | channel->enabled = false; |
8ceee660 BH |
493 | napi_disable(&channel->napi_str); |
494 | ||
495 | /* Ensure that any worker threads have exited or will be no-ops */ | |
496 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
497 | spin_lock_bh(&rx_queue->add_lock); | |
498 | spin_unlock_bh(&rx_queue->add_lock); | |
499 | } | |
500 | } | |
501 | ||
502 | static void efx_fini_channels(struct efx_nic *efx) | |
503 | { | |
504 | struct efx_channel *channel; | |
505 | struct efx_tx_queue *tx_queue; | |
506 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 507 | int rc; |
8ceee660 BH |
508 | |
509 | EFX_ASSERT_RESET_SERIALISED(efx); | |
510 | BUG_ON(efx->port_enabled); | |
511 | ||
6bc5d3a9 BH |
512 | rc = falcon_flush_queues(efx); |
513 | if (rc) | |
514 | EFX_ERR(efx, "failed to flush queues\n"); | |
515 | else | |
516 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
517 | ||
8ceee660 BH |
518 | efx_for_each_channel(channel, efx) { |
519 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
520 | ||
521 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
522 | efx_fini_rx_queue(rx_queue); | |
523 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
524 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
525 | efx_fini_eventq(channel); |
526 | } | |
527 | } | |
528 | ||
529 | static void efx_remove_channel(struct efx_channel *channel) | |
530 | { | |
531 | struct efx_tx_queue *tx_queue; | |
532 | struct efx_rx_queue *rx_queue; | |
533 | ||
534 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
535 | ||
536 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
537 | efx_remove_rx_queue(rx_queue); | |
538 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
539 | efx_remove_tx_queue(tx_queue); | |
540 | efx_remove_eventq(channel); | |
541 | ||
542 | channel->used_flags = 0; | |
543 | } | |
544 | ||
545 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
546 | { | |
547 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
548 | } | |
549 | ||
550 | /************************************************************************** | |
551 | * | |
552 | * Port handling | |
553 | * | |
554 | **************************************************************************/ | |
555 | ||
556 | /* This ensures that the kernel is kept informed (via | |
557 | * netif_carrier_on/off) of the link status, and also maintains the | |
558 | * link status's stop on the port's TX queue. | |
559 | */ | |
560 | static void efx_link_status_changed(struct efx_nic *efx) | |
561 | { | |
8ceee660 BH |
562 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
563 | * that no events are triggered between unregister_netdev() and the | |
564 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
565 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
566 | if (!netif_running(efx->net_dev)) | |
567 | return; | |
568 | ||
8c8661e4 BH |
569 | if (efx->port_inhibited) { |
570 | netif_carrier_off(efx->net_dev); | |
571 | return; | |
572 | } | |
573 | ||
dc8cfa55 | 574 | if (efx->link_up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
575 | efx->n_link_state_changes++; |
576 | ||
577 | if (efx->link_up) | |
578 | netif_carrier_on(efx->net_dev); | |
579 | else | |
580 | netif_carrier_off(efx->net_dev); | |
581 | } | |
582 | ||
583 | /* Status message for kernel log */ | |
584 | if (efx->link_up) { | |
f31a45d2 BH |
585 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
586 | efx->link_speed, efx->link_fd ? "full" : "half", | |
8ceee660 BH |
587 | efx->net_dev->mtu, |
588 | (efx->promiscuous ? " [PROMISC]" : "")); | |
589 | } else { | |
590 | EFX_INFO(efx, "link down\n"); | |
591 | } | |
592 | ||
593 | } | |
594 | ||
115122af BH |
595 | static void efx_fini_port(struct efx_nic *efx); |
596 | ||
8ceee660 BH |
597 | /* This call reinitialises the MAC to pick up new PHY settings. The |
598 | * caller must hold the mac_lock */ | |
8c8661e4 | 599 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
600 | { |
601 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
602 | ||
603 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
604 | raw_smp_processor_id()); | |
605 | ||
a816f75a BH |
606 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
607 | if (efx_dev_registered(efx)) { | |
608 | netif_addr_lock_bh(efx->net_dev); | |
609 | netif_addr_unlock_bh(efx->net_dev); | |
610 | } | |
611 | ||
177dfcd8 BH |
612 | falcon_deconfigure_mac_wrapper(efx); |
613 | ||
614 | /* Reconfigure the PHY, disabling transmit in mac level loopback. */ | |
615 | if (LOOPBACK_INTERNAL(efx)) | |
616 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
617 | else | |
618 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
619 | efx->phy_op->reconfigure(efx); | |
620 | ||
621 | if (falcon_switch_mac(efx)) | |
622 | goto fail; | |
623 | ||
624 | efx->mac_op->reconfigure(efx); | |
8ceee660 BH |
625 | |
626 | /* Inform kernel of loss/gain of carrier */ | |
627 | efx_link_status_changed(efx); | |
177dfcd8 BH |
628 | return; |
629 | ||
630 | fail: | |
631 | EFX_ERR(efx, "failed to reconfigure MAC\n"); | |
115122af BH |
632 | efx->port_enabled = false; |
633 | efx_fini_port(efx); | |
8ceee660 BH |
634 | } |
635 | ||
636 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
637 | * disabled. */ | |
638 | void efx_reconfigure_port(struct efx_nic *efx) | |
639 | { | |
640 | EFX_ASSERT_RESET_SERIALISED(efx); | |
641 | ||
642 | mutex_lock(&efx->mac_lock); | |
643 | __efx_reconfigure_port(efx); | |
644 | mutex_unlock(&efx->mac_lock); | |
645 | } | |
646 | ||
647 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
648 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
649 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
766ca0fa | 650 | static void efx_phy_work(struct work_struct *data) |
8ceee660 | 651 | { |
766ca0fa | 652 | struct efx_nic *efx = container_of(data, struct efx_nic, phy_work); |
8ceee660 BH |
653 | |
654 | mutex_lock(&efx->mac_lock); | |
655 | if (efx->port_enabled) | |
656 | __efx_reconfigure_port(efx); | |
657 | mutex_unlock(&efx->mac_lock); | |
658 | } | |
659 | ||
766ca0fa BH |
660 | static void efx_mac_work(struct work_struct *data) |
661 | { | |
662 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
663 | ||
664 | mutex_lock(&efx->mac_lock); | |
665 | if (efx->port_enabled) | |
666 | efx->mac_op->irq(efx); | |
667 | mutex_unlock(&efx->mac_lock); | |
668 | } | |
669 | ||
8ceee660 BH |
670 | static int efx_probe_port(struct efx_nic *efx) |
671 | { | |
672 | int rc; | |
673 | ||
674 | EFX_LOG(efx, "create port\n"); | |
675 | ||
676 | /* Connect up MAC/PHY operations table and read MAC address */ | |
677 | rc = falcon_probe_port(efx); | |
678 | if (rc) | |
679 | goto err; | |
680 | ||
84ae48fe BH |
681 | if (phy_flash_cfg) |
682 | efx->phy_mode = PHY_MODE_SPECIAL; | |
683 | ||
8ceee660 BH |
684 | /* Sanity check MAC address */ |
685 | if (is_valid_ether_addr(efx->mac_address)) { | |
686 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
687 | } else { | |
e174961c JB |
688 | EFX_ERR(efx, "invalid MAC address %pM\n", |
689 | efx->mac_address); | |
8ceee660 BH |
690 | if (!allow_bad_hwaddr) { |
691 | rc = -EINVAL; | |
692 | goto err; | |
693 | } | |
694 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
695 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
696 | efx->net_dev->dev_addr); | |
8ceee660 BH |
697 | } |
698 | ||
699 | return 0; | |
700 | ||
701 | err: | |
702 | efx_remove_port(efx); | |
703 | return rc; | |
704 | } | |
705 | ||
706 | static int efx_init_port(struct efx_nic *efx) | |
707 | { | |
708 | int rc; | |
709 | ||
710 | EFX_LOG(efx, "init port\n"); | |
711 | ||
177dfcd8 | 712 | rc = efx->phy_op->init(efx); |
8ceee660 BH |
713 | if (rc) |
714 | return rc; | |
177dfcd8 | 715 | mutex_lock(&efx->mac_lock); |
4b988280 | 716 | efx->phy_op->reconfigure(efx); |
177dfcd8 BH |
717 | rc = falcon_switch_mac(efx); |
718 | mutex_unlock(&efx->mac_lock); | |
719 | if (rc) | |
720 | goto fail; | |
721 | efx->mac_op->reconfigure(efx); | |
8ceee660 | 722 | |
dc8cfa55 | 723 | efx->port_initialized = true; |
1974cc20 | 724 | efx_stats_enable(efx); |
8ceee660 | 725 | return 0; |
177dfcd8 BH |
726 | |
727 | fail: | |
728 | efx->phy_op->fini(efx); | |
729 | return rc; | |
8ceee660 BH |
730 | } |
731 | ||
732 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
733 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
766ca0fa | 734 | * efx_phy_work()/efx_mac_work() may have been cancelled */ |
8ceee660 BH |
735 | static void efx_start_port(struct efx_nic *efx) |
736 | { | |
737 | EFX_LOG(efx, "start port\n"); | |
738 | BUG_ON(efx->port_enabled); | |
739 | ||
740 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 741 | efx->port_enabled = true; |
8ceee660 | 742 | __efx_reconfigure_port(efx); |
766ca0fa | 743 | efx->mac_op->irq(efx); |
8ceee660 BH |
744 | mutex_unlock(&efx->mac_lock); |
745 | } | |
746 | ||
766ca0fa BH |
747 | /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing, |
748 | * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work | |
749 | * and efx_mac_work may still be scheduled via NAPI processing until | |
750 | * efx_flush_all() is called */ | |
8ceee660 BH |
751 | static void efx_stop_port(struct efx_nic *efx) |
752 | { | |
753 | EFX_LOG(efx, "stop port\n"); | |
754 | ||
755 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 756 | efx->port_enabled = false; |
8ceee660 BH |
757 | mutex_unlock(&efx->mac_lock); |
758 | ||
759 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 760 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
761 | netif_addr_lock_bh(efx->net_dev); |
762 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
763 | } |
764 | } | |
765 | ||
766 | static void efx_fini_port(struct efx_nic *efx) | |
767 | { | |
768 | EFX_LOG(efx, "shut down port\n"); | |
769 | ||
770 | if (!efx->port_initialized) | |
771 | return; | |
772 | ||
1974cc20 | 773 | efx_stats_disable(efx); |
177dfcd8 | 774 | efx->phy_op->fini(efx); |
dc8cfa55 | 775 | efx->port_initialized = false; |
8ceee660 | 776 | |
dc8cfa55 | 777 | efx->link_up = false; |
8ceee660 BH |
778 | efx_link_status_changed(efx); |
779 | } | |
780 | ||
781 | static void efx_remove_port(struct efx_nic *efx) | |
782 | { | |
783 | EFX_LOG(efx, "destroying port\n"); | |
784 | ||
785 | falcon_remove_port(efx); | |
786 | } | |
787 | ||
788 | /************************************************************************** | |
789 | * | |
790 | * NIC handling | |
791 | * | |
792 | **************************************************************************/ | |
793 | ||
794 | /* This configures the PCI device to enable I/O and DMA. */ | |
795 | static int efx_init_io(struct efx_nic *efx) | |
796 | { | |
797 | struct pci_dev *pci_dev = efx->pci_dev; | |
798 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
799 | int rc; | |
800 | ||
801 | EFX_LOG(efx, "initialising I/O\n"); | |
802 | ||
803 | rc = pci_enable_device(pci_dev); | |
804 | if (rc) { | |
805 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
806 | goto fail1; | |
807 | } | |
808 | ||
809 | pci_set_master(pci_dev); | |
810 | ||
811 | /* Set the PCI DMA mask. Try all possibilities from our | |
812 | * genuine mask down to 32 bits, because some architectures | |
813 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
814 | * masks event though they reject 46 bit masks. | |
815 | */ | |
816 | while (dma_mask > 0x7fffffffUL) { | |
817 | if (pci_dma_supported(pci_dev, dma_mask) && | |
818 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
819 | break; | |
820 | dma_mask >>= 1; | |
821 | } | |
822 | if (rc) { | |
823 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
824 | goto fail2; | |
825 | } | |
826 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
827 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
828 | if (rc) { | |
829 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
830 | * fail with a mask that pci_set_dma_mask() accepted, | |
831 | * but just in case... | |
832 | */ | |
833 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
834 | goto fail2; | |
835 | } | |
836 | ||
837 | efx->membase_phys = pci_resource_start(efx->pci_dev, | |
838 | efx->type->mem_bar); | |
839 | rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc"); | |
840 | if (rc) { | |
841 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
842 | rc = -EIO; | |
843 | goto fail3; | |
844 | } | |
845 | efx->membase = ioremap_nocache(efx->membase_phys, | |
846 | efx->type->mem_map_size); | |
847 | if (!efx->membase) { | |
086ea356 BH |
848 | EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n", |
849 | efx->type->mem_bar, | |
850 | (unsigned long long)efx->membase_phys, | |
8ceee660 BH |
851 | efx->type->mem_map_size); |
852 | rc = -ENOMEM; | |
853 | goto fail4; | |
854 | } | |
086ea356 BH |
855 | EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n", |
856 | efx->type->mem_bar, (unsigned long long)efx->membase_phys, | |
857 | efx->type->mem_map_size, efx->membase); | |
8ceee660 BH |
858 | |
859 | return 0; | |
860 | ||
861 | fail4: | |
e1074a0d | 862 | pci_release_region(efx->pci_dev, efx->type->mem_bar); |
8ceee660 | 863 | fail3: |
2c118e0f | 864 | efx->membase_phys = 0; |
8ceee660 BH |
865 | fail2: |
866 | pci_disable_device(efx->pci_dev); | |
867 | fail1: | |
868 | return rc; | |
869 | } | |
870 | ||
871 | static void efx_fini_io(struct efx_nic *efx) | |
872 | { | |
873 | EFX_LOG(efx, "shutting down I/O\n"); | |
874 | ||
875 | if (efx->membase) { | |
876 | iounmap(efx->membase); | |
877 | efx->membase = NULL; | |
878 | } | |
879 | ||
880 | if (efx->membase_phys) { | |
881 | pci_release_region(efx->pci_dev, efx->type->mem_bar); | |
2c118e0f | 882 | efx->membase_phys = 0; |
8ceee660 BH |
883 | } |
884 | ||
885 | pci_disable_device(efx->pci_dev); | |
886 | } | |
887 | ||
46123d04 BH |
888 | /* Get number of RX queues wanted. Return number of online CPU |
889 | * packages in the expectation that an IRQ balancer will spread | |
890 | * interrupts across them. */ | |
891 | static int efx_wanted_rx_queues(void) | |
892 | { | |
2f8975fb | 893 | cpumask_var_t core_mask; |
46123d04 BH |
894 | int count; |
895 | int cpu; | |
896 | ||
2f8975fb RR |
897 | if (!alloc_cpumask_var(&core_mask, GFP_KERNEL)) { |
898 | printk(KERN_WARNING | |
899 | "efx.c: allocation failure, irq balancing hobbled\n"); | |
900 | return 1; | |
901 | } | |
902 | ||
903 | cpumask_clear(core_mask); | |
46123d04 BH |
904 | count = 0; |
905 | for_each_online_cpu(cpu) { | |
2f8975fb | 906 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 907 | ++count; |
2f8975fb | 908 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 909 | topology_core_cpumask(cpu)); |
46123d04 BH |
910 | } |
911 | } | |
912 | ||
2f8975fb | 913 | free_cpumask_var(core_mask); |
46123d04 BH |
914 | return count; |
915 | } | |
916 | ||
917 | /* Probe the number and type of interrupts we are able to obtain, and | |
918 | * the resulting numbers of channels and RX queues. | |
919 | */ | |
8ceee660 BH |
920 | static void efx_probe_interrupts(struct efx_nic *efx) |
921 | { | |
46123d04 BH |
922 | int max_channels = |
923 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
924 | int rc, i; |
925 | ||
926 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
927 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
928 | int wanted_ints; | |
28b581ab | 929 | int rx_queues; |
aa6ef27e | 930 | |
46123d04 BH |
931 | /* We want one RX queue and interrupt per CPU package |
932 | * (or as specified by the rss_cpus module parameter). | |
933 | * We will need one channel per interrupt. | |
934 | */ | |
28b581ab NT |
935 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
936 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
937 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 938 | |
28b581ab | 939 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 940 | xentries[i].entry = i; |
28b581ab | 941 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 942 | if (rc > 0) { |
28b581ab NT |
943 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
944 | " available (%d < %d).\n", rc, wanted_ints); | |
945 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
946 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
947 | wanted_ints = rc; | |
8ceee660 | 948 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 949 | wanted_ints); |
8ceee660 BH |
950 | } |
951 | ||
952 | if (rc == 0) { | |
28b581ab NT |
953 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
954 | efx->n_channels = wanted_ints; | |
955 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 956 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
957 | } else { |
958 | /* Fall back to single channel MSI */ | |
959 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
960 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
961 | } | |
962 | } | |
963 | ||
964 | /* Try single interrupt MSI */ | |
965 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 966 | efx->n_rx_queues = 1; |
28b581ab | 967 | efx->n_channels = 1; |
8ceee660 BH |
968 | rc = pci_enable_msi(efx->pci_dev); |
969 | if (rc == 0) { | |
970 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
971 | } else { |
972 | EFX_ERR(efx, "could not enable MSI\n"); | |
973 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
974 | } | |
975 | } | |
976 | ||
977 | /* Assume legacy interrupts */ | |
978 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 979 | efx->n_rx_queues = 1; |
28b581ab | 980 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
981 | efx->legacy_irq = efx->pci_dev->irq; |
982 | } | |
983 | } | |
984 | ||
985 | static void efx_remove_interrupts(struct efx_nic *efx) | |
986 | { | |
987 | struct efx_channel *channel; | |
988 | ||
989 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 990 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
991 | channel->irq = 0; |
992 | pci_disable_msi(efx->pci_dev); | |
993 | pci_disable_msix(efx->pci_dev); | |
994 | ||
995 | /* Remove legacy interrupt */ | |
996 | efx->legacy_irq = 0; | |
997 | } | |
998 | ||
8831da7b | 999 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
1000 | { |
1001 | struct efx_tx_queue *tx_queue; | |
1002 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 1003 | |
60ac1065 | 1004 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
1005 | if (separate_tx_channels) |
1006 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
1007 | else |
1008 | tx_queue->channel = &efx->channel[0]; | |
1009 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
1010 | } | |
8ceee660 | 1011 | |
8831da7b BH |
1012 | efx_for_each_rx_queue(rx_queue, efx) { |
1013 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
1014 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
1015 | } |
1016 | } | |
1017 | ||
1018 | static int efx_probe_nic(struct efx_nic *efx) | |
1019 | { | |
1020 | int rc; | |
1021 | ||
1022 | EFX_LOG(efx, "creating NIC\n"); | |
1023 | ||
1024 | /* Carry out hardware-type specific initialisation */ | |
1025 | rc = falcon_probe_nic(efx); | |
1026 | if (rc) | |
1027 | return rc; | |
1028 | ||
1029 | /* Determine the number of channels and RX queues by trying to hook | |
1030 | * in MSI-X interrupts. */ | |
1031 | efx_probe_interrupts(efx); | |
1032 | ||
8831da7b | 1033 | efx_set_channels(efx); |
8ceee660 BH |
1034 | |
1035 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1036 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1037 | |
1038 | return 0; | |
1039 | } | |
1040 | ||
1041 | static void efx_remove_nic(struct efx_nic *efx) | |
1042 | { | |
1043 | EFX_LOG(efx, "destroying NIC\n"); | |
1044 | ||
1045 | efx_remove_interrupts(efx); | |
1046 | falcon_remove_nic(efx); | |
1047 | } | |
1048 | ||
1049 | /************************************************************************** | |
1050 | * | |
1051 | * NIC startup/shutdown | |
1052 | * | |
1053 | *************************************************************************/ | |
1054 | ||
1055 | static int efx_probe_all(struct efx_nic *efx) | |
1056 | { | |
1057 | struct efx_channel *channel; | |
1058 | int rc; | |
1059 | ||
1060 | /* Create NIC */ | |
1061 | rc = efx_probe_nic(efx); | |
1062 | if (rc) { | |
1063 | EFX_ERR(efx, "failed to create NIC\n"); | |
1064 | goto fail1; | |
1065 | } | |
1066 | ||
1067 | /* Create port */ | |
1068 | rc = efx_probe_port(efx); | |
1069 | if (rc) { | |
1070 | EFX_ERR(efx, "failed to create port\n"); | |
1071 | goto fail2; | |
1072 | } | |
1073 | ||
1074 | /* Create channels */ | |
1075 | efx_for_each_channel(channel, efx) { | |
1076 | rc = efx_probe_channel(channel); | |
1077 | if (rc) { | |
1078 | EFX_ERR(efx, "failed to create channel %d\n", | |
1079 | channel->channel); | |
1080 | goto fail3; | |
1081 | } | |
1082 | } | |
56536e9c | 1083 | efx_set_channel_names(efx); |
8ceee660 BH |
1084 | |
1085 | return 0; | |
1086 | ||
1087 | fail3: | |
1088 | efx_for_each_channel(channel, efx) | |
1089 | efx_remove_channel(channel); | |
1090 | efx_remove_port(efx); | |
1091 | fail2: | |
1092 | efx_remove_nic(efx); | |
1093 | fail1: | |
1094 | return rc; | |
1095 | } | |
1096 | ||
1097 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1098 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1099 | * and ensures that the port is scheduled to be reconfigured. | |
1100 | * This function is safe to call multiple times when the NIC is in any | |
1101 | * state. */ | |
1102 | static void efx_start_all(struct efx_nic *efx) | |
1103 | { | |
1104 | struct efx_channel *channel; | |
1105 | ||
1106 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1107 | ||
1108 | /* Check that it is appropriate to restart the interface. All | |
1109 | * of these flags are safe to read under just the rtnl lock */ | |
1110 | if (efx->port_enabled) | |
1111 | return; | |
1112 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1113 | return; | |
55668611 | 1114 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1115 | return; |
1116 | ||
1117 | /* Mark the port as enabled so port reconfigurations can start, then | |
1118 | * restart the transmit interface early so the watchdog timer stops */ | |
1119 | efx_start_port(efx); | |
dacccc74 SH |
1120 | if (efx_dev_registered(efx)) |
1121 | efx_wake_queue(efx); | |
8ceee660 BH |
1122 | |
1123 | efx_for_each_channel(channel, efx) | |
1124 | efx_start_channel(channel); | |
1125 | ||
1126 | falcon_enable_interrupts(efx); | |
1127 | ||
1128 | /* Start hardware monitor if we're in RUNNING */ | |
1129 | if (efx->state == STATE_RUNNING) | |
1130 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1131 | efx_monitor_interval); | |
1132 | } | |
1133 | ||
1134 | /* Flush all delayed work. Should only be called when no more delayed work | |
1135 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1136 | * since we're holding the rtnl_lock at this point. */ | |
1137 | static void efx_flush_all(struct efx_nic *efx) | |
1138 | { | |
1139 | struct efx_rx_queue *rx_queue; | |
1140 | ||
1141 | /* Make sure the hardware monitor is stopped */ | |
1142 | cancel_delayed_work_sync(&efx->monitor_work); | |
1143 | ||
1144 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1145 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1146 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1147 | |
1148 | /* Stop scheduled port reconfigurations */ | |
766ca0fa BH |
1149 | cancel_work_sync(&efx->mac_work); |
1150 | cancel_work_sync(&efx->phy_work); | |
8ceee660 BH |
1151 | |
1152 | } | |
1153 | ||
1154 | /* Quiesce hardware and software without bringing the link down. | |
1155 | * Safe to call multiple times, when the nic and interface is in any | |
1156 | * state. The caller is guaranteed to subsequently be in a position | |
1157 | * to modify any hardware and software state they see fit without | |
1158 | * taking locks. */ | |
1159 | static void efx_stop_all(struct efx_nic *efx) | |
1160 | { | |
1161 | struct efx_channel *channel; | |
1162 | ||
1163 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1164 | ||
1165 | /* port_enabled can be read safely under the rtnl lock */ | |
1166 | if (!efx->port_enabled) | |
1167 | return; | |
1168 | ||
1169 | /* Disable interrupts and wait for ISR to complete */ | |
1170 | falcon_disable_interrupts(efx); | |
1171 | if (efx->legacy_irq) | |
1172 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1173 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1174 | if (channel->irq) |
1175 | synchronize_irq(channel->irq); | |
b3475645 | 1176 | } |
8ceee660 BH |
1177 | |
1178 | /* Stop all NAPI processing and synchronous rx refills */ | |
1179 | efx_for_each_channel(channel, efx) | |
1180 | efx_stop_channel(channel); | |
1181 | ||
1182 | /* Stop all asynchronous port reconfigurations. Since all | |
1183 | * event processing has already been stopped, there is no | |
1184 | * window to loose phy events */ | |
1185 | efx_stop_port(efx); | |
1186 | ||
766ca0fa | 1187 | /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */ |
8ceee660 BH |
1188 | efx_flush_all(efx); |
1189 | ||
1190 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1191 | * flushes will complete in a timely fashion. */ | |
8ceee660 BH |
1192 | falcon_drain_tx_fifo(efx); |
1193 | ||
1194 | /* Stop the kernel transmit interface late, so the watchdog | |
1195 | * timer isn't ticking over the flush */ | |
55668611 | 1196 | if (efx_dev_registered(efx)) { |
dacccc74 | 1197 | efx_stop_queue(efx); |
8ceee660 BH |
1198 | netif_tx_lock_bh(efx->net_dev); |
1199 | netif_tx_unlock_bh(efx->net_dev); | |
1200 | } | |
1201 | } | |
1202 | ||
1203 | static void efx_remove_all(struct efx_nic *efx) | |
1204 | { | |
1205 | struct efx_channel *channel; | |
1206 | ||
1207 | efx_for_each_channel(channel, efx) | |
1208 | efx_remove_channel(channel); | |
1209 | efx_remove_port(efx); | |
1210 | efx_remove_nic(efx); | |
1211 | } | |
1212 | ||
1213 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1214 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1215 | { |
8ceee660 BH |
1216 | EFX_ASSERT_RESET_SERIALISED(efx); |
1217 | ||
1218 | efx_stop_all(efx); | |
1219 | ||
1220 | efx_fini_channels(efx); | |
bc3c90a2 | 1221 | efx_init_channels(efx); |
8ceee660 BH |
1222 | |
1223 | efx_start_all(efx); | |
8ceee660 BH |
1224 | } |
1225 | ||
1226 | /************************************************************************** | |
1227 | * | |
1228 | * Interrupt moderation | |
1229 | * | |
1230 | **************************************************************************/ | |
1231 | ||
1232 | /* Set interrupt moderation parameters */ | |
6fb70fd1 BH |
1233 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1234 | bool rx_adaptive) | |
8ceee660 BH |
1235 | { |
1236 | struct efx_tx_queue *tx_queue; | |
1237 | struct efx_rx_queue *rx_queue; | |
1238 | ||
1239 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1240 | ||
1241 | efx_for_each_tx_queue(tx_queue, efx) | |
1242 | tx_queue->channel->irq_moderation = tx_usecs; | |
1243 | ||
6fb70fd1 BH |
1244 | efx->irq_rx_adaptive = rx_adaptive; |
1245 | efx->irq_rx_moderation = rx_usecs; | |
8ceee660 BH |
1246 | efx_for_each_rx_queue(rx_queue, efx) |
1247 | rx_queue->channel->irq_moderation = rx_usecs; | |
1248 | } | |
1249 | ||
1250 | /************************************************************************** | |
1251 | * | |
1252 | * Hardware monitor | |
1253 | * | |
1254 | **************************************************************************/ | |
1255 | ||
1256 | /* Run periodically off the general workqueue. Serialised against | |
1257 | * efx_reconfigure_port via the mac_lock */ | |
1258 | static void efx_monitor(struct work_struct *data) | |
1259 | { | |
1260 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1261 | monitor_work.work); | |
766ca0fa | 1262 | int rc; |
8ceee660 BH |
1263 | |
1264 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1265 | raw_smp_processor_id()); | |
1266 | ||
8ceee660 BH |
1267 | /* If the mac_lock is already held then it is likely a port |
1268 | * reconfiguration is already in place, which will likely do | |
1269 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1270 | if (!mutex_trylock(&efx->mac_lock)) |
1271 | goto out_requeue; | |
1272 | if (!efx->port_enabled) | |
1273 | goto out_unlock; | |
1274 | rc = efx->board_info.monitor(efx); | |
1275 | if (rc) { | |
1276 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
1277 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
1278 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
1279 | falcon_sim_phy_event(efx); | |
8ceee660 | 1280 | } |
766ca0fa BH |
1281 | efx->phy_op->poll(efx); |
1282 | efx->mac_op->poll(efx); | |
8ceee660 | 1283 | |
766ca0fa | 1284 | out_unlock: |
8ceee660 | 1285 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1286 | out_requeue: |
8ceee660 BH |
1287 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1288 | efx_monitor_interval); | |
1289 | } | |
1290 | ||
1291 | /************************************************************************** | |
1292 | * | |
1293 | * ioctls | |
1294 | * | |
1295 | *************************************************************************/ | |
1296 | ||
1297 | /* Net device ioctl | |
1298 | * Context: process, rtnl_lock() held. | |
1299 | */ | |
1300 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1301 | { | |
767e468c | 1302 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1303 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1304 | |
1305 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1306 | ||
68e7f45e BH |
1307 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1308 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1309 | (data->phy_id & 0xfc00) == 0x0400) | |
1310 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1311 | ||
1312 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1313 | } |
1314 | ||
1315 | /************************************************************************** | |
1316 | * | |
1317 | * NAPI interface | |
1318 | * | |
1319 | **************************************************************************/ | |
1320 | ||
1321 | static int efx_init_napi(struct efx_nic *efx) | |
1322 | { | |
1323 | struct efx_channel *channel; | |
8ceee660 BH |
1324 | |
1325 | efx_for_each_channel(channel, efx) { | |
1326 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1327 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1328 | efx_poll, napi_weight); | |
8ceee660 BH |
1329 | } |
1330 | return 0; | |
8ceee660 BH |
1331 | } |
1332 | ||
1333 | static void efx_fini_napi(struct efx_nic *efx) | |
1334 | { | |
1335 | struct efx_channel *channel; | |
1336 | ||
1337 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1338 | if (channel->napi_dev) |
1339 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1340 | channel->napi_dev = NULL; |
1341 | } | |
1342 | } | |
1343 | ||
1344 | /************************************************************************** | |
1345 | * | |
1346 | * Kernel netpoll interface | |
1347 | * | |
1348 | *************************************************************************/ | |
1349 | ||
1350 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1351 | ||
1352 | /* Although in the common case interrupts will be disabled, this is not | |
1353 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1354 | * so no locking is required. | |
1355 | */ | |
1356 | static void efx_netpoll(struct net_device *net_dev) | |
1357 | { | |
767e468c | 1358 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1359 | struct efx_channel *channel; |
1360 | ||
64ee3120 | 1361 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1362 | efx_schedule_channel(channel); |
1363 | } | |
1364 | ||
1365 | #endif | |
1366 | ||
1367 | /************************************************************************** | |
1368 | * | |
1369 | * Kernel net device interface | |
1370 | * | |
1371 | *************************************************************************/ | |
1372 | ||
1373 | /* Context: process, rtnl_lock() held. */ | |
1374 | static int efx_net_open(struct net_device *net_dev) | |
1375 | { | |
767e468c | 1376 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1377 | EFX_ASSERT_RESET_SERIALISED(efx); |
1378 | ||
1379 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1380 | raw_smp_processor_id()); | |
1381 | ||
f4bd954e BH |
1382 | if (efx->state == STATE_DISABLED) |
1383 | return -EIO; | |
f8b87c17 BH |
1384 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1385 | return -EBUSY; | |
1386 | ||
8ceee660 BH |
1387 | efx_start_all(efx); |
1388 | return 0; | |
1389 | } | |
1390 | ||
1391 | /* Context: process, rtnl_lock() held. | |
1392 | * Note that the kernel will ignore our return code; this method | |
1393 | * should really be a void. | |
1394 | */ | |
1395 | static int efx_net_stop(struct net_device *net_dev) | |
1396 | { | |
767e468c | 1397 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1398 | |
1399 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1400 | raw_smp_processor_id()); | |
1401 | ||
f4bd954e BH |
1402 | if (efx->state != STATE_DISABLED) { |
1403 | /* Stop the device and flush all the channels */ | |
1404 | efx_stop_all(efx); | |
1405 | efx_fini_channels(efx); | |
1406 | efx_init_channels(efx); | |
1407 | } | |
8ceee660 BH |
1408 | |
1409 | return 0; | |
1410 | } | |
1411 | ||
1974cc20 BH |
1412 | void efx_stats_disable(struct efx_nic *efx) |
1413 | { | |
1414 | spin_lock(&efx->stats_lock); | |
1415 | ++efx->stats_disable_count; | |
1416 | spin_unlock(&efx->stats_lock); | |
1417 | } | |
1418 | ||
1419 | void efx_stats_enable(struct efx_nic *efx) | |
1420 | { | |
1421 | spin_lock(&efx->stats_lock); | |
1422 | --efx->stats_disable_count; | |
1423 | spin_unlock(&efx->stats_lock); | |
1424 | } | |
1425 | ||
5b9e207c | 1426 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1427 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1428 | { | |
767e468c | 1429 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1430 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1431 | struct net_device_stats *stats = &net_dev->stats; | |
1432 | ||
5b9e207c | 1433 | /* Update stats if possible, but do not wait if another thread |
1974cc20 BH |
1434 | * is updating them or if MAC stats fetches are temporarily |
1435 | * disabled; slightly stale stats are acceptable. | |
5b9e207c | 1436 | */ |
8ceee660 BH |
1437 | if (!spin_trylock(&efx->stats_lock)) |
1438 | return stats; | |
1974cc20 | 1439 | if (!efx->stats_disable_count) { |
177dfcd8 | 1440 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1441 | falcon_update_nic_stats(efx); |
1442 | } | |
1443 | spin_unlock(&efx->stats_lock); | |
1444 | ||
1445 | stats->rx_packets = mac_stats->rx_packets; | |
1446 | stats->tx_packets = mac_stats->tx_packets; | |
1447 | stats->rx_bytes = mac_stats->rx_bytes; | |
1448 | stats->tx_bytes = mac_stats->tx_bytes; | |
1449 | stats->multicast = mac_stats->rx_multicast; | |
1450 | stats->collisions = mac_stats->tx_collision; | |
1451 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1452 | mac_stats->rx_length_error); | |
1453 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1454 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1455 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1456 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1457 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1458 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1459 | ||
1460 | stats->rx_errors = (stats->rx_length_errors + | |
1461 | stats->rx_over_errors + | |
1462 | stats->rx_crc_errors + | |
1463 | stats->rx_frame_errors + | |
1464 | stats->rx_fifo_errors + | |
1465 | stats->rx_missed_errors + | |
1466 | mac_stats->rx_symbol_error); | |
1467 | stats->tx_errors = (stats->tx_window_errors + | |
1468 | mac_stats->tx_bad); | |
1469 | ||
1470 | return stats; | |
1471 | } | |
1472 | ||
1473 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1474 | static void efx_watchdog(struct net_device *net_dev) | |
1475 | { | |
767e468c | 1476 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1477 | |
739bb23d BH |
1478 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1479 | " resetting channels\n", | |
1480 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1481 | |
739bb23d | 1482 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1483 | } |
1484 | ||
1485 | ||
1486 | /* Context: process, rtnl_lock() held. */ | |
1487 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1488 | { | |
767e468c | 1489 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1490 | int rc = 0; |
1491 | ||
1492 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1493 | ||
1494 | if (new_mtu > EFX_MAX_MTU) | |
1495 | return -EINVAL; | |
1496 | ||
1497 | efx_stop_all(efx); | |
1498 | ||
1499 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1500 | ||
1501 | efx_fini_channels(efx); | |
1502 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1503 | efx_init_channels(efx); |
8ceee660 BH |
1504 | |
1505 | efx_start_all(efx); | |
1506 | return rc; | |
8ceee660 BH |
1507 | } |
1508 | ||
1509 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1510 | { | |
767e468c | 1511 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1512 | struct sockaddr *addr = data; |
1513 | char *new_addr = addr->sa_data; | |
1514 | ||
1515 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1516 | ||
1517 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1518 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1519 | new_addr); | |
8ceee660 BH |
1520 | return -EINVAL; |
1521 | } | |
1522 | ||
1523 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1524 | ||
1525 | /* Reconfigure the MAC */ | |
1526 | efx_reconfigure_port(efx); | |
1527 | ||
1528 | return 0; | |
1529 | } | |
1530 | ||
a816f75a | 1531 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1532 | static void efx_set_multicast_list(struct net_device *net_dev) |
1533 | { | |
767e468c | 1534 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1535 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1536 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1537 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1538 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1539 | u32 crc; |
1540 | int bit; | |
1541 | int i; | |
1542 | ||
a816f75a | 1543 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1544 | |
1545 | /* Build multicast hash table */ | |
1546 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1547 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1548 | } else { | |
1549 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1550 | for (i = 0; i < net_dev->mc_count; i++) { | |
1551 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1552 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1553 | set_bit_le(bit, mc_hash->byte); | |
1554 | mc_list = mc_list->next; | |
1555 | } | |
1556 | } | |
1557 | ||
a816f75a BH |
1558 | if (!efx->port_enabled) |
1559 | /* Delay pushing settings until efx_start_port() */ | |
1560 | return; | |
1561 | ||
1562 | if (changed) | |
766ca0fa | 1563 | queue_work(efx->workqueue, &efx->phy_work); |
a816f75a | 1564 | |
8ceee660 BH |
1565 | /* Create and activate new global multicast hash table */ |
1566 | falcon_set_multicast_hash(efx); | |
1567 | } | |
1568 | ||
c3ecb9f3 SH |
1569 | static const struct net_device_ops efx_netdev_ops = { |
1570 | .ndo_open = efx_net_open, | |
1571 | .ndo_stop = efx_net_stop, | |
1572 | .ndo_get_stats = efx_net_stats, | |
1573 | .ndo_tx_timeout = efx_watchdog, | |
1574 | .ndo_start_xmit = efx_hard_start_xmit, | |
1575 | .ndo_validate_addr = eth_validate_addr, | |
1576 | .ndo_do_ioctl = efx_ioctl, | |
1577 | .ndo_change_mtu = efx_change_mtu, | |
1578 | .ndo_set_mac_address = efx_set_mac_address, | |
1579 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1580 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1581 | .ndo_poll_controller = efx_netpoll, | |
1582 | #endif | |
1583 | }; | |
1584 | ||
7dde596e BH |
1585 | static void efx_update_name(struct efx_nic *efx) |
1586 | { | |
1587 | strcpy(efx->name, efx->net_dev->name); | |
1588 | efx_mtd_rename(efx); | |
1589 | efx_set_channel_names(efx); | |
1590 | } | |
1591 | ||
8ceee660 BH |
1592 | static int efx_netdev_event(struct notifier_block *this, |
1593 | unsigned long event, void *ptr) | |
1594 | { | |
d3208b5e | 1595 | struct net_device *net_dev = ptr; |
8ceee660 | 1596 | |
7dde596e BH |
1597 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1598 | event == NETDEV_CHANGENAME) | |
1599 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1600 | |
1601 | return NOTIFY_DONE; | |
1602 | } | |
1603 | ||
1604 | static struct notifier_block efx_netdev_notifier = { | |
1605 | .notifier_call = efx_netdev_event, | |
1606 | }; | |
1607 | ||
06d5e193 BH |
1608 | static ssize_t |
1609 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1610 | { | |
1611 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1612 | return sprintf(buf, "%d\n", efx->phy_type); | |
1613 | } | |
1614 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1615 | ||
8ceee660 BH |
1616 | static int efx_register_netdev(struct efx_nic *efx) |
1617 | { | |
1618 | struct net_device *net_dev = efx->net_dev; | |
1619 | int rc; | |
1620 | ||
1621 | net_dev->watchdog_timeo = 5 * HZ; | |
1622 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1623 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1624 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1625 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1626 | ||
1627 | /* Always start with carrier off; PHY events will detect the link */ | |
1628 | netif_carrier_off(efx->net_dev); | |
1629 | ||
1630 | /* Clear MAC statistics */ | |
177dfcd8 | 1631 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1632 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1633 | ||
1634 | rc = register_netdev(net_dev); | |
1635 | if (rc) { | |
1636 | EFX_ERR(efx, "could not register net dev\n"); | |
1637 | return rc; | |
1638 | } | |
7dde596e BH |
1639 | |
1640 | rtnl_lock(); | |
1641 | efx_update_name(efx); | |
1642 | rtnl_unlock(); | |
8ceee660 | 1643 | |
06d5e193 BH |
1644 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1645 | if (rc) { | |
1646 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1647 | goto fail_registered; | |
1648 | } | |
1649 | ||
8ceee660 | 1650 | return 0; |
06d5e193 BH |
1651 | |
1652 | fail_registered: | |
1653 | unregister_netdev(net_dev); | |
1654 | return rc; | |
8ceee660 BH |
1655 | } |
1656 | ||
1657 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1658 | { | |
1659 | struct efx_tx_queue *tx_queue; | |
1660 | ||
1661 | if (!efx->net_dev) | |
1662 | return; | |
1663 | ||
767e468c | 1664 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1665 | |
1666 | /* Free up any skbs still remaining. This has to happen before | |
1667 | * we try to unregister the netdev as running their destructors | |
1668 | * may be needed to get the device ref. count to 0. */ | |
1669 | efx_for_each_tx_queue(tx_queue, efx) | |
1670 | efx_release_tx_buffers(tx_queue); | |
1671 | ||
55668611 | 1672 | if (efx_dev_registered(efx)) { |
8ceee660 | 1673 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1674 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1675 | unregister_netdev(efx->net_dev); |
1676 | } | |
1677 | } | |
1678 | ||
1679 | /************************************************************************** | |
1680 | * | |
1681 | * Device reset and suspend | |
1682 | * | |
1683 | **************************************************************************/ | |
1684 | ||
2467ca46 BH |
1685 | /* Tears down the entire software state and most of the hardware state |
1686 | * before reset. */ | |
4b988280 SH |
1687 | void efx_reset_down(struct efx_nic *efx, enum reset_type method, |
1688 | struct ethtool_cmd *ecmd) | |
8ceee660 | 1689 | { |
8ceee660 BH |
1690 | EFX_ASSERT_RESET_SERIALISED(efx); |
1691 | ||
1974cc20 | 1692 | efx_stats_disable(efx); |
2467ca46 BH |
1693 | efx_stop_all(efx); |
1694 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1695 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1696 | |
177dfcd8 | 1697 | efx->phy_op->get_settings(efx, ecmd); |
8ceee660 BH |
1698 | |
1699 | efx_fini_channels(efx); | |
4b988280 SH |
1700 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1701 | efx->phy_op->fini(efx); | |
8ceee660 BH |
1702 | } |
1703 | ||
2467ca46 BH |
1704 | /* This function will always ensure that the locks acquired in |
1705 | * efx_reset_down() are released. A failure return code indicates | |
1706 | * that we were unable to reinitialise the hardware, and the | |
1707 | * driver should be disabled. If ok is false, then the rx and tx | |
1708 | * engines are not restarted, pending a RESET_DISABLE. */ | |
4b988280 SH |
1709 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, |
1710 | struct ethtool_cmd *ecmd, bool ok) | |
8ceee660 BH |
1711 | { |
1712 | int rc; | |
1713 | ||
2467ca46 | 1714 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1715 | |
2467ca46 | 1716 | rc = falcon_init_nic(efx); |
8ceee660 | 1717 | if (rc) { |
2467ca46 BH |
1718 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1719 | ok = false; | |
8ceee660 BH |
1720 | } |
1721 | ||
4b988280 SH |
1722 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
1723 | if (ok) { | |
1724 | rc = efx->phy_op->init(efx); | |
1725 | if (rc) | |
1726 | ok = false; | |
115122af BH |
1727 | } |
1728 | if (!ok) | |
4b988280 SH |
1729 | efx->port_initialized = false; |
1730 | } | |
1731 | ||
2467ca46 BH |
1732 | if (ok) { |
1733 | efx_init_channels(efx); | |
8ceee660 | 1734 | |
177dfcd8 | 1735 | if (efx->phy_op->set_settings(efx, ecmd)) |
2467ca46 BH |
1736 | EFX_ERR(efx, "could not restore PHY settings\n"); |
1737 | } | |
1738 | ||
f4150724 | 1739 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1740 | mutex_unlock(&efx->mac_lock); |
1741 | ||
8c8661e4 | 1742 | if (ok) { |
2467ca46 | 1743 | efx_start_all(efx); |
1974cc20 | 1744 | efx_stats_enable(efx); |
8c8661e4 | 1745 | } |
8ceee660 BH |
1746 | return rc; |
1747 | } | |
1748 | ||
1749 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1750 | * Note that the reset may fail, in which case the card will be left | |
1751 | * in a most-probably-unusable state. | |
1752 | * | |
1753 | * This function will sleep. You cannot reset from within an atomic | |
1754 | * state; use efx_schedule_reset() instead. | |
1755 | * | |
1756 | * Grabs the rtnl_lock. | |
1757 | */ | |
1758 | static int efx_reset(struct efx_nic *efx) | |
1759 | { | |
1760 | struct ethtool_cmd ecmd; | |
1761 | enum reset_type method = efx->reset_pending; | |
f4bd954e | 1762 | int rc = 0; |
8ceee660 BH |
1763 | |
1764 | /* Serialise with kernel interfaces */ | |
1765 | rtnl_lock(); | |
1766 | ||
1767 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1768 | * flag set so that efx_pci_probe_main will be retried */ | |
1769 | if (efx->state != STATE_RUNNING) { | |
1770 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
f4bd954e | 1771 | goto out_unlock; |
8ceee660 BH |
1772 | } |
1773 | ||
8ceee660 BH |
1774 | EFX_INFO(efx, "resetting (%d)\n", method); |
1775 | ||
4b988280 | 1776 | efx_reset_down(efx, method, &ecmd); |
8ceee660 BH |
1777 | |
1778 | rc = falcon_reset_hw(efx, method); | |
1779 | if (rc) { | |
1780 | EFX_ERR(efx, "failed to reset hardware\n"); | |
f4bd954e | 1781 | goto out_disable; |
8ceee660 BH |
1782 | } |
1783 | ||
1784 | /* Allow resets to be rescheduled. */ | |
1785 | efx->reset_pending = RESET_TYPE_NONE; | |
1786 | ||
1787 | /* Reinitialise bus-mastering, which may have been turned off before | |
1788 | * the reset was scheduled. This is still appropriate, even in the | |
1789 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1790 | * can respond to requests. */ | |
1791 | pci_set_master(efx->pci_dev); | |
1792 | ||
8ceee660 BH |
1793 | /* Leave device stopped if necessary */ |
1794 | if (method == RESET_TYPE_DISABLE) { | |
4b988280 | 1795 | efx_reset_up(efx, method, &ecmd, false); |
8ceee660 | 1796 | rc = -EIO; |
f4bd954e | 1797 | } else { |
4b988280 | 1798 | rc = efx_reset_up(efx, method, &ecmd, true); |
8ceee660 BH |
1799 | } |
1800 | ||
f4bd954e BH |
1801 | out_disable: |
1802 | if (rc) { | |
1803 | EFX_ERR(efx, "has been disabled\n"); | |
1804 | efx->state = STATE_DISABLED; | |
1805 | dev_close(efx->net_dev); | |
1806 | } else { | |
1807 | EFX_LOG(efx, "reset complete\n"); | |
1808 | } | |
8ceee660 | 1809 | |
f4bd954e | 1810 | out_unlock: |
8ceee660 | 1811 | rtnl_unlock(); |
8ceee660 BH |
1812 | return rc; |
1813 | } | |
1814 | ||
1815 | /* The worker thread exists so that code that cannot sleep can | |
1816 | * schedule a reset for later. | |
1817 | */ | |
1818 | static void efx_reset_work(struct work_struct *data) | |
1819 | { | |
1820 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1821 | ||
1822 | efx_reset(nic); | |
1823 | } | |
1824 | ||
1825 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1826 | { | |
1827 | enum reset_type method; | |
1828 | ||
1829 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1830 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1831 | return; | |
1832 | } | |
1833 | ||
1834 | switch (type) { | |
1835 | case RESET_TYPE_INVISIBLE: | |
1836 | case RESET_TYPE_ALL: | |
1837 | case RESET_TYPE_WORLD: | |
1838 | case RESET_TYPE_DISABLE: | |
1839 | method = type; | |
1840 | break; | |
1841 | case RESET_TYPE_RX_RECOVERY: | |
1842 | case RESET_TYPE_RX_DESC_FETCH: | |
1843 | case RESET_TYPE_TX_DESC_FETCH: | |
1844 | case RESET_TYPE_TX_SKIP: | |
1845 | method = RESET_TYPE_INVISIBLE; | |
1846 | break; | |
1847 | default: | |
1848 | method = RESET_TYPE_ALL; | |
1849 | break; | |
1850 | } | |
1851 | ||
1852 | if (method != type) | |
1853 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1854 | else | |
1855 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1856 | ||
1857 | efx->reset_pending = method; | |
1858 | ||
1ab00629 | 1859 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1860 | } |
1861 | ||
1862 | /************************************************************************** | |
1863 | * | |
1864 | * List of NICs we support | |
1865 | * | |
1866 | **************************************************************************/ | |
1867 | ||
1868 | /* PCI device ID table */ | |
1869 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1870 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1871 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1872 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1873 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1874 | {0} /* end of list */ | |
1875 | }; | |
1876 | ||
1877 | /************************************************************************** | |
1878 | * | |
1879 | * Dummy PHY/MAC/Board operations | |
1880 | * | |
01aad7b6 | 1881 | * Can be used for some unimplemented operations |
8ceee660 BH |
1882 | * Needed so all function pointers are valid and do not have to be tested |
1883 | * before use | |
1884 | * | |
1885 | **************************************************************************/ | |
1886 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1887 | { | |
1888 | return 0; | |
1889 | } | |
1890 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
dc8cfa55 | 1891 | void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {} |
8ceee660 | 1892 | |
177dfcd8 BH |
1893 | static struct efx_mac_operations efx_dummy_mac_operations = { |
1894 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa BH |
1895 | .poll = efx_port_dummy_op_void, |
1896 | .irq = efx_port_dummy_op_void, | |
177dfcd8 BH |
1897 | }; |
1898 | ||
8ceee660 BH |
1899 | static struct efx_phy_operations efx_dummy_phy_operations = { |
1900 | .init = efx_port_dummy_op_int, | |
1901 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa | 1902 | .poll = efx_port_dummy_op_void, |
8ceee660 BH |
1903 | .fini = efx_port_dummy_op_void, |
1904 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1905 | }; |
1906 | ||
8ceee660 | 1907 | static struct efx_board efx_dummy_board_info = { |
01aad7b6 | 1908 | .init = efx_port_dummy_op_int, |
8129d217 BH |
1909 | .init_leds = efx_port_dummy_op_void, |
1910 | .set_id_led = efx_port_dummy_op_blink, | |
a17102b1 | 1911 | .monitor = efx_port_dummy_op_int, |
01aad7b6 BH |
1912 | .blink = efx_port_dummy_op_blink, |
1913 | .fini = efx_port_dummy_op_void, | |
8ceee660 BH |
1914 | }; |
1915 | ||
1916 | /************************************************************************** | |
1917 | * | |
1918 | * Data housekeeping | |
1919 | * | |
1920 | **************************************************************************/ | |
1921 | ||
1922 | /* This zeroes out and then fills in the invariants in a struct | |
1923 | * efx_nic (including all sub-structures). | |
1924 | */ | |
1925 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1926 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1927 | { | |
1928 | struct efx_channel *channel; | |
1929 | struct efx_tx_queue *tx_queue; | |
1930 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1931 | int i; |
8ceee660 BH |
1932 | |
1933 | /* Initialise common structures */ | |
1934 | memset(efx, 0, sizeof(*efx)); | |
1935 | spin_lock_init(&efx->biu_lock); | |
1936 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1937 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1938 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1939 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1940 | efx->pci_dev = pci_dev; | |
1941 | efx->state = STATE_INIT; | |
1942 | efx->reset_pending = RESET_TYPE_NONE; | |
1943 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
1944 | efx->board_info = efx_dummy_board_info; | |
1945 | ||
1946 | efx->net_dev = net_dev; | |
dc8cfa55 | 1947 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1948 | spin_lock_init(&efx->netif_stop_lock); |
1949 | spin_lock_init(&efx->stats_lock); | |
1974cc20 | 1950 | efx->stats_disable_count = 1; |
8ceee660 | 1951 | mutex_init(&efx->mac_lock); |
177dfcd8 | 1952 | efx->mac_op = &efx_dummy_mac_operations; |
8ceee660 | 1953 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 1954 | efx->mdio.dev = net_dev; |
766ca0fa BH |
1955 | INIT_WORK(&efx->phy_work, efx_phy_work); |
1956 | INIT_WORK(&efx->mac_work, efx_mac_work); | |
8ceee660 BH |
1957 | atomic_set(&efx->netif_stop_count, 1); |
1958 | ||
1959 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1960 | channel = &efx->channel[i]; | |
1961 | channel->efx = efx; | |
1962 | channel->channel = i; | |
dc8cfa55 | 1963 | channel->work_pending = false; |
8ceee660 | 1964 | } |
60ac1065 | 1965 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1966 | tx_queue = &efx->tx_queue[i]; |
1967 | tx_queue->efx = efx; | |
1968 | tx_queue->queue = i; | |
1969 | tx_queue->buffer = NULL; | |
1970 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1971 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1972 | } |
1973 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1974 | rx_queue = &efx->rx_queue[i]; | |
1975 | rx_queue->efx = efx; | |
1976 | rx_queue->queue = i; | |
1977 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1978 | rx_queue->buffer = NULL; | |
1979 | spin_lock_init(&rx_queue->add_lock); | |
1980 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1981 | } | |
1982 | ||
1983 | efx->type = type; | |
1984 | ||
1985 | /* Sanity-check NIC type */ | |
1986 | EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask & | |
1987 | (efx->type->txd_ring_mask + 1)); | |
1988 | EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask & | |
1989 | (efx->type->rxd_ring_mask + 1)); | |
1990 | EFX_BUG_ON_PARANOID(efx->type->evq_size & | |
1991 | (efx->type->evq_size - 1)); | |
1992 | /* As close as we can get to guaranteeing that we don't overflow */ | |
1993 | EFX_BUG_ON_PARANOID(efx->type->evq_size < | |
1994 | (efx->type->txd_ring_mask + 1 + | |
1995 | efx->type->rxd_ring_mask + 1)); | |
1996 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); | |
1997 | ||
1998 | /* Higher numbered interrupt modes are less capable! */ | |
1999 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
2000 | interrupt_mode); | |
2001 | ||
6977dc63 BH |
2002 | /* Would be good to use the net_dev name, but we're too early */ |
2003 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
2004 | pci_name(pci_dev)); | |
2005 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
2006 | if (!efx->workqueue) |
2007 | return -ENOMEM; | |
8d9853d9 | 2008 | |
8ceee660 | 2009 | return 0; |
8ceee660 BH |
2010 | } |
2011 | ||
2012 | static void efx_fini_struct(struct efx_nic *efx) | |
2013 | { | |
2014 | if (efx->workqueue) { | |
2015 | destroy_workqueue(efx->workqueue); | |
2016 | efx->workqueue = NULL; | |
2017 | } | |
2018 | } | |
2019 | ||
2020 | /************************************************************************** | |
2021 | * | |
2022 | * PCI interface | |
2023 | * | |
2024 | **************************************************************************/ | |
2025 | ||
2026 | /* Main body of final NIC shutdown code | |
2027 | * This is called only at module unload (or hotplug removal). | |
2028 | */ | |
2029 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2030 | { | |
2031 | EFX_ASSERT_RESET_SERIALISED(efx); | |
2032 | ||
2033 | /* Skip everything if we never obtained a valid membase */ | |
2034 | if (!efx->membase) | |
2035 | return; | |
2036 | ||
2037 | efx_fini_channels(efx); | |
2038 | efx_fini_port(efx); | |
2039 | ||
2040 | /* Shutdown the board, then the NIC and board state */ | |
37b5a603 | 2041 | efx->board_info.fini(efx); |
8ceee660 BH |
2042 | falcon_fini_interrupt(efx); |
2043 | ||
2044 | efx_fini_napi(efx); | |
2045 | efx_remove_all(efx); | |
2046 | } | |
2047 | ||
2048 | /* Final NIC shutdown | |
2049 | * This is called only at module unload (or hotplug removal). | |
2050 | */ | |
2051 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2052 | { | |
2053 | struct efx_nic *efx; | |
2054 | ||
2055 | efx = pci_get_drvdata(pci_dev); | |
2056 | if (!efx) | |
2057 | return; | |
2058 | ||
2059 | /* Mark the NIC as fini, then stop the interface */ | |
2060 | rtnl_lock(); | |
2061 | efx->state = STATE_FINI; | |
2062 | dev_close(efx->net_dev); | |
2063 | ||
2064 | /* Allow any queued efx_resets() to complete */ | |
2065 | rtnl_unlock(); | |
2066 | ||
2067 | if (efx->membase == NULL) | |
2068 | goto out; | |
2069 | ||
2070 | efx_unregister_netdev(efx); | |
2071 | ||
7dde596e BH |
2072 | efx_mtd_remove(efx); |
2073 | ||
8ceee660 BH |
2074 | /* Wait for any scheduled resets to complete. No more will be |
2075 | * scheduled from this point because efx_stop_all() has been | |
2076 | * called, we are no longer registered with driverlink, and | |
2077 | * the net_device's have been removed. */ | |
1ab00629 | 2078 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2079 | |
2080 | efx_pci_remove_main(efx); | |
2081 | ||
2082 | out: | |
2083 | efx_fini_io(efx); | |
2084 | EFX_LOG(efx, "shutdown successful\n"); | |
2085 | ||
2086 | pci_set_drvdata(pci_dev, NULL); | |
2087 | efx_fini_struct(efx); | |
2088 | free_netdev(efx->net_dev); | |
2089 | }; | |
2090 | ||
2091 | /* Main body of NIC initialisation | |
2092 | * This is called at module load (or hotplug insertion, theoretically). | |
2093 | */ | |
2094 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2095 | { | |
2096 | int rc; | |
2097 | ||
2098 | /* Do start-of-day initialisation */ | |
2099 | rc = efx_probe_all(efx); | |
2100 | if (rc) | |
2101 | goto fail1; | |
2102 | ||
2103 | rc = efx_init_napi(efx); | |
2104 | if (rc) | |
2105 | goto fail2; | |
2106 | ||
2107 | /* Initialise the board */ | |
2108 | rc = efx->board_info.init(efx); | |
2109 | if (rc) { | |
2110 | EFX_ERR(efx, "failed to initialise board\n"); | |
2111 | goto fail3; | |
2112 | } | |
2113 | ||
2114 | rc = falcon_init_nic(efx); | |
2115 | if (rc) { | |
2116 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
2117 | goto fail4; | |
2118 | } | |
2119 | ||
2120 | rc = efx_init_port(efx); | |
2121 | if (rc) { | |
2122 | EFX_ERR(efx, "failed to initialise port\n"); | |
2123 | goto fail5; | |
2124 | } | |
2125 | ||
bc3c90a2 | 2126 | efx_init_channels(efx); |
8ceee660 BH |
2127 | |
2128 | rc = falcon_init_interrupt(efx); | |
2129 | if (rc) | |
bc3c90a2 | 2130 | goto fail6; |
8ceee660 BH |
2131 | |
2132 | return 0; | |
2133 | ||
8ceee660 | 2134 | fail6: |
bc3c90a2 | 2135 | efx_fini_channels(efx); |
8ceee660 BH |
2136 | efx_fini_port(efx); |
2137 | fail5: | |
2138 | fail4: | |
a17102b1 | 2139 | efx->board_info.fini(efx); |
8ceee660 BH |
2140 | fail3: |
2141 | efx_fini_napi(efx); | |
2142 | fail2: | |
2143 | efx_remove_all(efx); | |
2144 | fail1: | |
2145 | return rc; | |
2146 | } | |
2147 | ||
2148 | /* NIC initialisation | |
2149 | * | |
2150 | * This is called at module load (or hotplug insertion, | |
2151 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2152 | * sets up and registers the network devices with the kernel and hooks | |
2153 | * the interrupt service routine. It does not prepare the device for | |
2154 | * transmission; this is left to the first time one of the network | |
2155 | * interfaces is brought up (i.e. efx_net_open). | |
2156 | */ | |
2157 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2158 | const struct pci_device_id *entry) | |
2159 | { | |
2160 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2161 | struct net_device *net_dev; | |
2162 | struct efx_nic *efx; | |
2163 | int i, rc; | |
2164 | ||
2165 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2166 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2167 | if (!net_dev) | |
2168 | return -ENOMEM; | |
b9b39b62 BH |
2169 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
2170 | NETIF_F_HIGHDMA | NETIF_F_TSO); | |
8ceee660 | 2171 | if (lro) |
da3bc071 | 2172 | net_dev->features |= NETIF_F_GRO; |
28506563 BH |
2173 | /* Mask for features that also apply to VLAN devices */ |
2174 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2175 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2176 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2177 | pci_set_drvdata(pci_dev, efx); |
2178 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2179 | if (rc) | |
2180 | goto fail1; | |
2181 | ||
2182 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2183 | ||
2184 | /* Set up basic I/O (BAR mappings etc) */ | |
2185 | rc = efx_init_io(efx); | |
2186 | if (rc) | |
2187 | goto fail2; | |
2188 | ||
2189 | /* No serialisation is required with the reset path because | |
2190 | * we're in STATE_INIT. */ | |
2191 | for (i = 0; i < 5; i++) { | |
2192 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2193 | |
2194 | /* Serialise against efx_reset(). No more resets will be | |
2195 | * scheduled since efx_stop_all() has been called, and we | |
2196 | * have not and never have been registered with either | |
2197 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2198 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2199 | |
fa402b2e SH |
2200 | if (rc == 0) { |
2201 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2202 | /* If there was a scheduled reset during | |
2203 | * probe, the NIC is probably hosed anyway */ | |
2204 | efx_pci_remove_main(efx); | |
2205 | rc = -EIO; | |
2206 | } else { | |
2207 | break; | |
2208 | } | |
2209 | } | |
2210 | ||
8ceee660 BH |
2211 | /* Retry if a recoverably reset event has been scheduled */ |
2212 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2213 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2214 | goto fail3; | |
2215 | ||
2216 | efx->reset_pending = RESET_TYPE_NONE; | |
2217 | } | |
2218 | ||
2219 | if (rc) { | |
2220 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2221 | goto fail4; | |
2222 | } | |
2223 | ||
2224 | /* Switch to the running state before we expose the device to | |
2225 | * the OS. This is to ensure that the initial gathering of | |
2226 | * MAC stats succeeds. */ | |
8ceee660 | 2227 | efx->state = STATE_RUNNING; |
7dde596e BH |
2228 | |
2229 | efx_mtd_probe(efx); /* allowed to fail */ | |
8ceee660 BH |
2230 | |
2231 | rc = efx_register_netdev(efx); | |
2232 | if (rc) | |
2233 | goto fail5; | |
2234 | ||
2235 | EFX_LOG(efx, "initialisation successful\n"); | |
8ceee660 BH |
2236 | return 0; |
2237 | ||
2238 | fail5: | |
2239 | efx_pci_remove_main(efx); | |
2240 | fail4: | |
2241 | fail3: | |
2242 | efx_fini_io(efx); | |
2243 | fail2: | |
2244 | efx_fini_struct(efx); | |
2245 | fail1: | |
2246 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2247 | free_netdev(net_dev); | |
2248 | return rc; | |
2249 | } | |
2250 | ||
2251 | static struct pci_driver efx_pci_driver = { | |
2252 | .name = EFX_DRIVER_NAME, | |
2253 | .id_table = efx_pci_table, | |
2254 | .probe = efx_pci_probe, | |
2255 | .remove = efx_pci_remove, | |
2256 | }; | |
2257 | ||
2258 | /************************************************************************** | |
2259 | * | |
2260 | * Kernel module interface | |
2261 | * | |
2262 | *************************************************************************/ | |
2263 | ||
2264 | module_param(interrupt_mode, uint, 0444); | |
2265 | MODULE_PARM_DESC(interrupt_mode, | |
2266 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2267 | ||
2268 | static int __init efx_init_module(void) | |
2269 | { | |
2270 | int rc; | |
2271 | ||
2272 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2273 | ||
2274 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2275 | if (rc) | |
2276 | goto err_notifier; | |
2277 | ||
2278 | refill_workqueue = create_workqueue("sfc_refill"); | |
2279 | if (!refill_workqueue) { | |
2280 | rc = -ENOMEM; | |
2281 | goto err_refill; | |
2282 | } | |
1ab00629 SH |
2283 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2284 | if (!reset_workqueue) { | |
2285 | rc = -ENOMEM; | |
2286 | goto err_reset; | |
2287 | } | |
8ceee660 BH |
2288 | |
2289 | rc = pci_register_driver(&efx_pci_driver); | |
2290 | if (rc < 0) | |
2291 | goto err_pci; | |
2292 | ||
2293 | return 0; | |
2294 | ||
2295 | err_pci: | |
1ab00629 SH |
2296 | destroy_workqueue(reset_workqueue); |
2297 | err_reset: | |
8ceee660 BH |
2298 | destroy_workqueue(refill_workqueue); |
2299 | err_refill: | |
2300 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2301 | err_notifier: | |
2302 | return rc; | |
2303 | } | |
2304 | ||
2305 | static void __exit efx_exit_module(void) | |
2306 | { | |
2307 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2308 | ||
2309 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2310 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2311 | destroy_workqueue(refill_workqueue); |
2312 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2313 | ||
2314 | } | |
2315 | ||
2316 | module_init(efx_init_module); | |
2317 | module_exit(efx_exit_module); | |
2318 | ||
2319 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2320 | "Solarflare Communications"); | |
2321 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2322 | MODULE_LICENSE("GPL"); | |
2323 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |