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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2005-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/netdevice.h> | |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/notifier.h> | |
17 | #include <linux/ip.h> | |
18 | #include <linux/tcp.h> | |
19 | #include <linux/in.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/ethtool.h> | |
aa6ef27e | 22 | #include <linux/topology.h> |
8ceee660 | 23 | #include "net_driver.h" |
8ceee660 BH |
24 | #include "efx.h" |
25 | #include "mdio_10g.h" | |
26 | #include "falcon.h" | |
8ceee660 BH |
27 | |
28 | #define EFX_MAX_MTU (9 * 1024) | |
29 | ||
30 | /* RX slow fill workqueue. If memory allocation fails in the fast path, | |
31 | * a work item is pushed onto this work queue to retry the allocation later, | |
32 | * to avoid the NIC being starved of RX buffers. Since this is a per cpu | |
33 | * workqueue, there is nothing to be gained in making it per NIC | |
34 | */ | |
35 | static struct workqueue_struct *refill_workqueue; | |
36 | ||
1ab00629 SH |
37 | /* Reset workqueue. If any NIC has a hardware failure then a reset will be |
38 | * queued onto this work queue. This is not a per-nic work queue, because | |
39 | * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised. | |
40 | */ | |
41 | static struct workqueue_struct *reset_workqueue; | |
42 | ||
8ceee660 BH |
43 | /************************************************************************** |
44 | * | |
45 | * Configurable values | |
46 | * | |
47 | *************************************************************************/ | |
48 | ||
8ceee660 BH |
49 | /* |
50 | * Use separate channels for TX and RX events | |
51 | * | |
28b581ab NT |
52 | * Set this to 1 to use separate channels for TX and RX. It allows us |
53 | * to control interrupt affinity separately for TX and RX. | |
8ceee660 | 54 | * |
28b581ab | 55 | * This is only used in MSI-X interrupt mode |
8ceee660 | 56 | */ |
28b581ab NT |
57 | static unsigned int separate_tx_channels; |
58 | module_param(separate_tx_channels, uint, 0644); | |
59 | MODULE_PARM_DESC(separate_tx_channels, | |
60 | "Use separate channels for TX and RX"); | |
8ceee660 BH |
61 | |
62 | /* This is the weight assigned to each of the (per-channel) virtual | |
63 | * NAPI devices. | |
64 | */ | |
65 | static int napi_weight = 64; | |
66 | ||
67 | /* This is the time (in jiffies) between invocations of the hardware | |
68 | * monitor, which checks for known hardware bugs and resets the | |
69 | * hardware and driver as necessary. | |
70 | */ | |
71 | unsigned int efx_monitor_interval = 1 * HZ; | |
72 | ||
8ceee660 BH |
73 | /* This controls whether or not the driver will initialise devices |
74 | * with invalid MAC addresses stored in the EEPROM or flash. If true, | |
75 | * such devices will be initialised with a random locally-generated | |
76 | * MAC address. This allows for loading the sfc_mtd driver to | |
77 | * reprogram the flash, even if the flash contents (including the MAC | |
78 | * address) have previously been erased. | |
79 | */ | |
80 | static unsigned int allow_bad_hwaddr; | |
81 | ||
82 | /* Initial interrupt moderation settings. They can be modified after | |
83 | * module load with ethtool. | |
84 | * | |
85 | * The default for RX should strike a balance between increasing the | |
86 | * round-trip latency and reducing overhead. | |
87 | */ | |
88 | static unsigned int rx_irq_mod_usec = 60; | |
89 | ||
90 | /* Initial interrupt moderation settings. They can be modified after | |
91 | * module load with ethtool. | |
92 | * | |
93 | * This default is chosen to ensure that a 10G link does not go idle | |
94 | * while a TX queue is stopped after it has become full. A queue is | |
95 | * restarted when it drops below half full. The time this takes (assuming | |
96 | * worst case 3 descriptors per packet and 1024 descriptors) is | |
97 | * 512 / 3 * 1.2 = 205 usec. | |
98 | */ | |
99 | static unsigned int tx_irq_mod_usec = 150; | |
100 | ||
101 | /* This is the first interrupt mode to try out of: | |
102 | * 0 => MSI-X | |
103 | * 1 => MSI | |
104 | * 2 => legacy | |
105 | */ | |
106 | static unsigned int interrupt_mode; | |
107 | ||
108 | /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS), | |
109 | * i.e. the number of CPUs among which we may distribute simultaneous | |
110 | * interrupt handling. | |
111 | * | |
112 | * Cards without MSI-X will only target one CPU via legacy or MSI interrupt. | |
113 | * The default (0) means to assign an interrupt to each package (level II cache) | |
114 | */ | |
115 | static unsigned int rss_cpus; | |
116 | module_param(rss_cpus, uint, 0444); | |
117 | MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling"); | |
118 | ||
84ae48fe BH |
119 | static int phy_flash_cfg; |
120 | module_param(phy_flash_cfg, int, 0644); | |
121 | MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially"); | |
122 | ||
6fb70fd1 BH |
123 | static unsigned irq_adapt_low_thresh = 10000; |
124 | module_param(irq_adapt_low_thresh, uint, 0644); | |
125 | MODULE_PARM_DESC(irq_adapt_low_thresh, | |
126 | "Threshold score for reducing IRQ moderation"); | |
127 | ||
128 | static unsigned irq_adapt_high_thresh = 20000; | |
129 | module_param(irq_adapt_high_thresh, uint, 0644); | |
130 | MODULE_PARM_DESC(irq_adapt_high_thresh, | |
131 | "Threshold score for increasing IRQ moderation"); | |
132 | ||
8ceee660 BH |
133 | /************************************************************************** |
134 | * | |
135 | * Utility functions and prototypes | |
136 | * | |
137 | *************************************************************************/ | |
138 | static void efx_remove_channel(struct efx_channel *channel); | |
139 | static void efx_remove_port(struct efx_nic *efx); | |
140 | static void efx_fini_napi(struct efx_nic *efx); | |
141 | static void efx_fini_channels(struct efx_nic *efx); | |
142 | ||
143 | #define EFX_ASSERT_RESET_SERIALISED(efx) \ | |
144 | do { \ | |
3c78708f | 145 | if (efx->state == STATE_RUNNING) \ |
8ceee660 BH |
146 | ASSERT_RTNL(); \ |
147 | } while (0) | |
148 | ||
149 | /************************************************************************** | |
150 | * | |
151 | * Event queue processing | |
152 | * | |
153 | *************************************************************************/ | |
154 | ||
155 | /* Process channel's event queue | |
156 | * | |
157 | * This function is responsible for processing the event queue of a | |
158 | * single channel. The caller must guarantee that this function will | |
159 | * never be concurrently called more than once on the same channel, | |
160 | * though different channels may be being processed concurrently. | |
161 | */ | |
4d566063 | 162 | static int efx_process_channel(struct efx_channel *channel, int rx_quota) |
8ceee660 | 163 | { |
42cbe2d7 BH |
164 | struct efx_nic *efx = channel->efx; |
165 | int rx_packets; | |
8ceee660 | 166 | |
42cbe2d7 | 167 | if (unlikely(efx->reset_pending != RESET_TYPE_NONE || |
8ceee660 | 168 | !channel->enabled)) |
42cbe2d7 | 169 | return 0; |
8ceee660 | 170 | |
42cbe2d7 BH |
171 | rx_packets = falcon_process_eventq(channel, rx_quota); |
172 | if (rx_packets == 0) | |
173 | return 0; | |
8ceee660 BH |
174 | |
175 | /* Deliver last RX packet. */ | |
176 | if (channel->rx_pkt) { | |
177 | __efx_rx_packet(channel, channel->rx_pkt, | |
178 | channel->rx_pkt_csummed); | |
179 | channel->rx_pkt = NULL; | |
180 | } | |
181 | ||
8ceee660 BH |
182 | efx_rx_strategy(channel); |
183 | ||
42cbe2d7 | 184 | efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]); |
8ceee660 | 185 | |
42cbe2d7 | 186 | return rx_packets; |
8ceee660 BH |
187 | } |
188 | ||
189 | /* Mark channel as finished processing | |
190 | * | |
191 | * Note that since we will not receive further interrupts for this | |
192 | * channel before we finish processing and call the eventq_read_ack() | |
193 | * method, there is no need to use the interrupt hold-off timers. | |
194 | */ | |
195 | static inline void efx_channel_processed(struct efx_channel *channel) | |
196 | { | |
5b9e207c BH |
197 | /* The interrupt handler for this channel may set work_pending |
198 | * as soon as we acknowledge the events we've seen. Make sure | |
199 | * it's cleared before then. */ | |
dc8cfa55 | 200 | channel->work_pending = false; |
5b9e207c BH |
201 | smp_wmb(); |
202 | ||
8ceee660 BH |
203 | falcon_eventq_read_ack(channel); |
204 | } | |
205 | ||
206 | /* NAPI poll handler | |
207 | * | |
208 | * NAPI guarantees serialisation of polls of the same device, which | |
209 | * provides the guarantee required by efx_process_channel(). | |
210 | */ | |
211 | static int efx_poll(struct napi_struct *napi, int budget) | |
212 | { | |
213 | struct efx_channel *channel = | |
214 | container_of(napi, struct efx_channel, napi_str); | |
8ceee660 BH |
215 | int rx_packets; |
216 | ||
217 | EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n", | |
218 | channel->channel, raw_smp_processor_id()); | |
219 | ||
42cbe2d7 | 220 | rx_packets = efx_process_channel(channel, budget); |
8ceee660 BH |
221 | |
222 | if (rx_packets < budget) { | |
6fb70fd1 BH |
223 | struct efx_nic *efx = channel->efx; |
224 | ||
225 | if (channel->used_flags & EFX_USED_BY_RX && | |
226 | efx->irq_rx_adaptive && | |
227 | unlikely(++channel->irq_count == 1000)) { | |
6fb70fd1 BH |
228 | if (unlikely(channel->irq_mod_score < |
229 | irq_adapt_low_thresh)) { | |
0d86ebd8 BH |
230 | if (channel->irq_moderation > 1) { |
231 | channel->irq_moderation -= 1; | |
232 | falcon_set_int_moderation(channel); | |
233 | } | |
6fb70fd1 BH |
234 | } else if (unlikely(channel->irq_mod_score > |
235 | irq_adapt_high_thresh)) { | |
0d86ebd8 BH |
236 | if (channel->irq_moderation < |
237 | efx->irq_rx_moderation) { | |
238 | channel->irq_moderation += 1; | |
239 | falcon_set_int_moderation(channel); | |
240 | } | |
6fb70fd1 | 241 | } |
6fb70fd1 BH |
242 | channel->irq_count = 0; |
243 | channel->irq_mod_score = 0; | |
244 | } | |
245 | ||
8ceee660 | 246 | /* There is no race here; although napi_disable() will |
288379f0 | 247 | * only wait for napi_complete(), this isn't a problem |
8ceee660 BH |
248 | * since efx_channel_processed() will have no effect if |
249 | * interrupts have already been disabled. | |
250 | */ | |
288379f0 | 251 | napi_complete(napi); |
8ceee660 BH |
252 | efx_channel_processed(channel); |
253 | } | |
254 | ||
255 | return rx_packets; | |
256 | } | |
257 | ||
258 | /* Process the eventq of the specified channel immediately on this CPU | |
259 | * | |
260 | * Disable hardware generated interrupts, wait for any existing | |
261 | * processing to finish, then directly poll (and ack ) the eventq. | |
262 | * Finally reenable NAPI and interrupts. | |
263 | * | |
264 | * Since we are touching interrupts the caller should hold the suspend lock | |
265 | */ | |
266 | void efx_process_channel_now(struct efx_channel *channel) | |
267 | { | |
268 | struct efx_nic *efx = channel->efx; | |
269 | ||
270 | BUG_ON(!channel->used_flags); | |
271 | BUG_ON(!channel->enabled); | |
272 | ||
273 | /* Disable interrupts and wait for ISRs to complete */ | |
274 | falcon_disable_interrupts(efx); | |
275 | if (efx->legacy_irq) | |
276 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 277 | if (channel->irq) |
8ceee660 BH |
278 | synchronize_irq(channel->irq); |
279 | ||
280 | /* Wait for any NAPI processing to complete */ | |
281 | napi_disable(&channel->napi_str); | |
282 | ||
283 | /* Poll the channel */ | |
3ffeabdd | 284 | efx_process_channel(channel, EFX_EVQ_SIZE); |
8ceee660 BH |
285 | |
286 | /* Ack the eventq. This may cause an interrupt to be generated | |
287 | * when they are reenabled */ | |
288 | efx_channel_processed(channel); | |
289 | ||
290 | napi_enable(&channel->napi_str); | |
291 | falcon_enable_interrupts(efx); | |
292 | } | |
293 | ||
294 | /* Create event queue | |
295 | * Event queue memory allocations are done only once. If the channel | |
296 | * is reset, the memory buffer will be reused; this guards against | |
297 | * errors during channel reset and also simplifies interrupt handling. | |
298 | */ | |
299 | static int efx_probe_eventq(struct efx_channel *channel) | |
300 | { | |
301 | EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel); | |
302 | ||
303 | return falcon_probe_eventq(channel); | |
304 | } | |
305 | ||
306 | /* Prepare channel's event queue */ | |
bc3c90a2 | 307 | static void efx_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
308 | { |
309 | EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel); | |
310 | ||
311 | channel->eventq_read_ptr = 0; | |
312 | ||
bc3c90a2 | 313 | falcon_init_eventq(channel); |
8ceee660 BH |
314 | } |
315 | ||
316 | static void efx_fini_eventq(struct efx_channel *channel) | |
317 | { | |
318 | EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel); | |
319 | ||
320 | falcon_fini_eventq(channel); | |
321 | } | |
322 | ||
323 | static void efx_remove_eventq(struct efx_channel *channel) | |
324 | { | |
325 | EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel); | |
326 | ||
327 | falcon_remove_eventq(channel); | |
328 | } | |
329 | ||
330 | /************************************************************************** | |
331 | * | |
332 | * Channel handling | |
333 | * | |
334 | *************************************************************************/ | |
335 | ||
8ceee660 BH |
336 | static int efx_probe_channel(struct efx_channel *channel) |
337 | { | |
338 | struct efx_tx_queue *tx_queue; | |
339 | struct efx_rx_queue *rx_queue; | |
340 | int rc; | |
341 | ||
342 | EFX_LOG(channel->efx, "creating channel %d\n", channel->channel); | |
343 | ||
344 | rc = efx_probe_eventq(channel); | |
345 | if (rc) | |
346 | goto fail1; | |
347 | ||
348 | efx_for_each_channel_tx_queue(tx_queue, channel) { | |
349 | rc = efx_probe_tx_queue(tx_queue); | |
350 | if (rc) | |
351 | goto fail2; | |
352 | } | |
353 | ||
354 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
355 | rc = efx_probe_rx_queue(rx_queue); | |
356 | if (rc) | |
357 | goto fail3; | |
358 | } | |
359 | ||
360 | channel->n_rx_frm_trunc = 0; | |
361 | ||
362 | return 0; | |
363 | ||
364 | fail3: | |
365 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
366 | efx_remove_rx_queue(rx_queue); | |
367 | fail2: | |
368 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
369 | efx_remove_tx_queue(tx_queue); | |
370 | fail1: | |
371 | return rc; | |
372 | } | |
373 | ||
374 | ||
56536e9c BH |
375 | static void efx_set_channel_names(struct efx_nic *efx) |
376 | { | |
377 | struct efx_channel *channel; | |
378 | const char *type = ""; | |
379 | int number; | |
380 | ||
381 | efx_for_each_channel(channel, efx) { | |
382 | number = channel->channel; | |
383 | if (efx->n_channels > efx->n_rx_queues) { | |
384 | if (channel->channel < efx->n_rx_queues) { | |
385 | type = "-rx"; | |
386 | } else { | |
387 | type = "-tx"; | |
388 | number -= efx->n_rx_queues; | |
389 | } | |
390 | } | |
391 | snprintf(channel->name, sizeof(channel->name), | |
392 | "%s%s-%d", efx->name, type, number); | |
393 | } | |
394 | } | |
395 | ||
8ceee660 BH |
396 | /* Channels are shutdown and reinitialised whilst the NIC is running |
397 | * to propagate configuration changes (mtu, checksum offload), or | |
398 | * to clear hardware error conditions | |
399 | */ | |
bc3c90a2 | 400 | static void efx_init_channels(struct efx_nic *efx) |
8ceee660 BH |
401 | { |
402 | struct efx_tx_queue *tx_queue; | |
403 | struct efx_rx_queue *rx_queue; | |
404 | struct efx_channel *channel; | |
8ceee660 | 405 | |
f7f13b0b BH |
406 | /* Calculate the rx buffer allocation parameters required to |
407 | * support the current MTU, including padding for header | |
408 | * alignment and overruns. | |
409 | */ | |
410 | efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) + | |
411 | EFX_MAX_FRAME_LEN(efx->net_dev->mtu) + | |
412 | efx->type->rx_buffer_padding); | |
413 | efx->rx_buffer_order = get_order(efx->rx_buffer_len); | |
8ceee660 BH |
414 | |
415 | /* Initialise the channels */ | |
416 | efx_for_each_channel(channel, efx) { | |
417 | EFX_LOG(channel->efx, "init chan %d\n", channel->channel); | |
418 | ||
bc3c90a2 | 419 | efx_init_eventq(channel); |
8ceee660 | 420 | |
bc3c90a2 BH |
421 | efx_for_each_channel_tx_queue(tx_queue, channel) |
422 | efx_init_tx_queue(tx_queue); | |
8ceee660 BH |
423 | |
424 | /* The rx buffer allocation strategy is MTU dependent */ | |
425 | efx_rx_strategy(channel); | |
426 | ||
bc3c90a2 BH |
427 | efx_for_each_channel_rx_queue(rx_queue, channel) |
428 | efx_init_rx_queue(rx_queue); | |
8ceee660 BH |
429 | |
430 | WARN_ON(channel->rx_pkt != NULL); | |
431 | efx_rx_strategy(channel); | |
432 | } | |
8ceee660 BH |
433 | } |
434 | ||
435 | /* This enables event queue processing and packet transmission. | |
436 | * | |
437 | * Note that this function is not allowed to fail, since that would | |
438 | * introduce too much complexity into the suspend/resume path. | |
439 | */ | |
440 | static void efx_start_channel(struct efx_channel *channel) | |
441 | { | |
442 | struct efx_rx_queue *rx_queue; | |
443 | ||
444 | EFX_LOG(channel->efx, "starting chan %d\n", channel->channel); | |
445 | ||
5b9e207c BH |
446 | /* The interrupt handler for this channel may set work_pending |
447 | * as soon as we enable it. Make sure it's cleared before | |
448 | * then. Similarly, make sure it sees the enabled flag set. */ | |
dc8cfa55 BH |
449 | channel->work_pending = false; |
450 | channel->enabled = true; | |
5b9e207c | 451 | smp_wmb(); |
8ceee660 BH |
452 | |
453 | napi_enable(&channel->napi_str); | |
454 | ||
455 | /* Load up RX descriptors */ | |
456 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
457 | efx_fast_push_rx_descriptors(rx_queue); | |
458 | } | |
459 | ||
460 | /* This disables event queue processing and packet transmission. | |
461 | * This function does not guarantee that all queue processing | |
462 | * (e.g. RX refill) is complete. | |
463 | */ | |
464 | static void efx_stop_channel(struct efx_channel *channel) | |
465 | { | |
466 | struct efx_rx_queue *rx_queue; | |
467 | ||
468 | if (!channel->enabled) | |
469 | return; | |
470 | ||
471 | EFX_LOG(channel->efx, "stop chan %d\n", channel->channel); | |
472 | ||
dc8cfa55 | 473 | channel->enabled = false; |
8ceee660 BH |
474 | napi_disable(&channel->napi_str); |
475 | ||
476 | /* Ensure that any worker threads have exited or will be no-ops */ | |
477 | efx_for_each_channel_rx_queue(rx_queue, channel) { | |
478 | spin_lock_bh(&rx_queue->add_lock); | |
479 | spin_unlock_bh(&rx_queue->add_lock); | |
480 | } | |
481 | } | |
482 | ||
483 | static void efx_fini_channels(struct efx_nic *efx) | |
484 | { | |
485 | struct efx_channel *channel; | |
486 | struct efx_tx_queue *tx_queue; | |
487 | struct efx_rx_queue *rx_queue; | |
6bc5d3a9 | 488 | int rc; |
8ceee660 BH |
489 | |
490 | EFX_ASSERT_RESET_SERIALISED(efx); | |
491 | BUG_ON(efx->port_enabled); | |
492 | ||
6bc5d3a9 BH |
493 | rc = falcon_flush_queues(efx); |
494 | if (rc) | |
495 | EFX_ERR(efx, "failed to flush queues\n"); | |
496 | else | |
497 | EFX_LOG(efx, "successfully flushed all queues\n"); | |
498 | ||
8ceee660 BH |
499 | efx_for_each_channel(channel, efx) { |
500 | EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel); | |
501 | ||
502 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
503 | efx_fini_rx_queue(rx_queue); | |
504 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
505 | efx_fini_tx_queue(tx_queue); | |
8ceee660 BH |
506 | efx_fini_eventq(channel); |
507 | } | |
508 | } | |
509 | ||
510 | static void efx_remove_channel(struct efx_channel *channel) | |
511 | { | |
512 | struct efx_tx_queue *tx_queue; | |
513 | struct efx_rx_queue *rx_queue; | |
514 | ||
515 | EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel); | |
516 | ||
517 | efx_for_each_channel_rx_queue(rx_queue, channel) | |
518 | efx_remove_rx_queue(rx_queue); | |
519 | efx_for_each_channel_tx_queue(tx_queue, channel) | |
520 | efx_remove_tx_queue(tx_queue); | |
521 | efx_remove_eventq(channel); | |
522 | ||
523 | channel->used_flags = 0; | |
524 | } | |
525 | ||
526 | void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay) | |
527 | { | |
528 | queue_delayed_work(refill_workqueue, &rx_queue->work, delay); | |
529 | } | |
530 | ||
531 | /************************************************************************** | |
532 | * | |
533 | * Port handling | |
534 | * | |
535 | **************************************************************************/ | |
536 | ||
537 | /* This ensures that the kernel is kept informed (via | |
538 | * netif_carrier_on/off) of the link status, and also maintains the | |
539 | * link status's stop on the port's TX queue. | |
540 | */ | |
541 | static void efx_link_status_changed(struct efx_nic *efx) | |
542 | { | |
eb50c0d6 BH |
543 | struct efx_link_state *link_state = &efx->link_state; |
544 | ||
8ceee660 BH |
545 | /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure |
546 | * that no events are triggered between unregister_netdev() and the | |
547 | * driver unloading. A more general condition is that NETDEV_CHANGE | |
548 | * can only be generated between NETDEV_UP and NETDEV_DOWN */ | |
549 | if (!netif_running(efx->net_dev)) | |
550 | return; | |
551 | ||
8c8661e4 BH |
552 | if (efx->port_inhibited) { |
553 | netif_carrier_off(efx->net_dev); | |
554 | return; | |
555 | } | |
556 | ||
eb50c0d6 | 557 | if (link_state->up != netif_carrier_ok(efx->net_dev)) { |
8ceee660 BH |
558 | efx->n_link_state_changes++; |
559 | ||
eb50c0d6 | 560 | if (link_state->up) |
8ceee660 BH |
561 | netif_carrier_on(efx->net_dev); |
562 | else | |
563 | netif_carrier_off(efx->net_dev); | |
564 | } | |
565 | ||
566 | /* Status message for kernel log */ | |
eb50c0d6 | 567 | if (link_state->up) { |
f31a45d2 | 568 | EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n", |
eb50c0d6 | 569 | link_state->speed, link_state->fd ? "full" : "half", |
8ceee660 BH |
570 | efx->net_dev->mtu, |
571 | (efx->promiscuous ? " [PROMISC]" : "")); | |
572 | } else { | |
573 | EFX_INFO(efx, "link down\n"); | |
574 | } | |
575 | ||
576 | } | |
577 | ||
115122af BH |
578 | static void efx_fini_port(struct efx_nic *efx); |
579 | ||
8ceee660 BH |
580 | /* This call reinitialises the MAC to pick up new PHY settings. The |
581 | * caller must hold the mac_lock */ | |
8c8661e4 | 582 | void __efx_reconfigure_port(struct efx_nic *efx) |
8ceee660 BH |
583 | { |
584 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
585 | ||
586 | EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n", | |
587 | raw_smp_processor_id()); | |
588 | ||
a816f75a BH |
589 | /* Serialise the promiscuous flag with efx_set_multicast_list. */ |
590 | if (efx_dev_registered(efx)) { | |
591 | netif_addr_lock_bh(efx->net_dev); | |
592 | netif_addr_unlock_bh(efx->net_dev); | |
593 | } | |
594 | ||
177dfcd8 BH |
595 | falcon_deconfigure_mac_wrapper(efx); |
596 | ||
597 | /* Reconfigure the PHY, disabling transmit in mac level loopback. */ | |
598 | if (LOOPBACK_INTERNAL(efx)) | |
599 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
600 | else | |
601 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
602 | efx->phy_op->reconfigure(efx); | |
603 | ||
604 | if (falcon_switch_mac(efx)) | |
605 | goto fail; | |
606 | ||
607 | efx->mac_op->reconfigure(efx); | |
8ceee660 BH |
608 | |
609 | /* Inform kernel of loss/gain of carrier */ | |
610 | efx_link_status_changed(efx); | |
177dfcd8 BH |
611 | return; |
612 | ||
613 | fail: | |
614 | EFX_ERR(efx, "failed to reconfigure MAC\n"); | |
115122af BH |
615 | efx->port_enabled = false; |
616 | efx_fini_port(efx); | |
8ceee660 BH |
617 | } |
618 | ||
619 | /* Reinitialise the MAC to pick up new PHY settings, even if the port is | |
620 | * disabled. */ | |
621 | void efx_reconfigure_port(struct efx_nic *efx) | |
622 | { | |
623 | EFX_ASSERT_RESET_SERIALISED(efx); | |
624 | ||
625 | mutex_lock(&efx->mac_lock); | |
626 | __efx_reconfigure_port(efx); | |
627 | mutex_unlock(&efx->mac_lock); | |
628 | } | |
629 | ||
630 | /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all() | |
631 | * we don't efx_reconfigure_port() if the port is disabled. Care is taken | |
632 | * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */ | |
766ca0fa | 633 | static void efx_phy_work(struct work_struct *data) |
8ceee660 | 634 | { |
766ca0fa | 635 | struct efx_nic *efx = container_of(data, struct efx_nic, phy_work); |
8ceee660 BH |
636 | |
637 | mutex_lock(&efx->mac_lock); | |
638 | if (efx->port_enabled) | |
639 | __efx_reconfigure_port(efx); | |
640 | mutex_unlock(&efx->mac_lock); | |
641 | } | |
642 | ||
766ca0fa BH |
643 | static void efx_mac_work(struct work_struct *data) |
644 | { | |
645 | struct efx_nic *efx = container_of(data, struct efx_nic, mac_work); | |
646 | ||
647 | mutex_lock(&efx->mac_lock); | |
648 | if (efx->port_enabled) | |
649 | efx->mac_op->irq(efx); | |
650 | mutex_unlock(&efx->mac_lock); | |
651 | } | |
652 | ||
8ceee660 BH |
653 | static int efx_probe_port(struct efx_nic *efx) |
654 | { | |
655 | int rc; | |
656 | ||
657 | EFX_LOG(efx, "create port\n"); | |
658 | ||
659 | /* Connect up MAC/PHY operations table and read MAC address */ | |
660 | rc = falcon_probe_port(efx); | |
661 | if (rc) | |
662 | goto err; | |
663 | ||
84ae48fe BH |
664 | if (phy_flash_cfg) |
665 | efx->phy_mode = PHY_MODE_SPECIAL; | |
666 | ||
8ceee660 BH |
667 | /* Sanity check MAC address */ |
668 | if (is_valid_ether_addr(efx->mac_address)) { | |
669 | memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN); | |
670 | } else { | |
e174961c JB |
671 | EFX_ERR(efx, "invalid MAC address %pM\n", |
672 | efx->mac_address); | |
8ceee660 BH |
673 | if (!allow_bad_hwaddr) { |
674 | rc = -EINVAL; | |
675 | goto err; | |
676 | } | |
677 | random_ether_addr(efx->net_dev->dev_addr); | |
e174961c JB |
678 | EFX_INFO(efx, "using locally-generated MAC %pM\n", |
679 | efx->net_dev->dev_addr); | |
8ceee660 BH |
680 | } |
681 | ||
682 | return 0; | |
683 | ||
684 | err: | |
685 | efx_remove_port(efx); | |
686 | return rc; | |
687 | } | |
688 | ||
689 | static int efx_init_port(struct efx_nic *efx) | |
690 | { | |
691 | int rc; | |
692 | ||
693 | EFX_LOG(efx, "init port\n"); | |
694 | ||
177dfcd8 | 695 | rc = efx->phy_op->init(efx); |
8ceee660 BH |
696 | if (rc) |
697 | return rc; | |
177dfcd8 | 698 | mutex_lock(&efx->mac_lock); |
4b988280 | 699 | efx->phy_op->reconfigure(efx); |
177dfcd8 BH |
700 | rc = falcon_switch_mac(efx); |
701 | mutex_unlock(&efx->mac_lock); | |
702 | if (rc) | |
703 | goto fail; | |
704 | efx->mac_op->reconfigure(efx); | |
8ceee660 | 705 | |
dc8cfa55 | 706 | efx->port_initialized = true; |
1974cc20 | 707 | efx_stats_enable(efx); |
8ceee660 | 708 | return 0; |
177dfcd8 BH |
709 | |
710 | fail: | |
711 | efx->phy_op->fini(efx); | |
712 | return rc; | |
8ceee660 BH |
713 | } |
714 | ||
715 | /* Allow efx_reconfigure_port() to be scheduled, and close the window | |
716 | * between efx_stop_port and efx_flush_all whereby a previously scheduled | |
766ca0fa | 717 | * efx_phy_work()/efx_mac_work() may have been cancelled */ |
8ceee660 BH |
718 | static void efx_start_port(struct efx_nic *efx) |
719 | { | |
720 | EFX_LOG(efx, "start port\n"); | |
721 | BUG_ON(efx->port_enabled); | |
722 | ||
723 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 724 | efx->port_enabled = true; |
8ceee660 | 725 | __efx_reconfigure_port(efx); |
766ca0fa | 726 | efx->mac_op->irq(efx); |
8ceee660 BH |
727 | mutex_unlock(&efx->mac_lock); |
728 | } | |
729 | ||
766ca0fa BH |
730 | /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing, |
731 | * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work | |
732 | * and efx_mac_work may still be scheduled via NAPI processing until | |
733 | * efx_flush_all() is called */ | |
8ceee660 BH |
734 | static void efx_stop_port(struct efx_nic *efx) |
735 | { | |
736 | EFX_LOG(efx, "stop port\n"); | |
737 | ||
738 | mutex_lock(&efx->mac_lock); | |
dc8cfa55 | 739 | efx->port_enabled = false; |
8ceee660 BH |
740 | mutex_unlock(&efx->mac_lock); |
741 | ||
742 | /* Serialise against efx_set_multicast_list() */ | |
55668611 | 743 | if (efx_dev_registered(efx)) { |
b9e40857 DM |
744 | netif_addr_lock_bh(efx->net_dev); |
745 | netif_addr_unlock_bh(efx->net_dev); | |
8ceee660 BH |
746 | } |
747 | } | |
748 | ||
749 | static void efx_fini_port(struct efx_nic *efx) | |
750 | { | |
751 | EFX_LOG(efx, "shut down port\n"); | |
752 | ||
753 | if (!efx->port_initialized) | |
754 | return; | |
755 | ||
1974cc20 | 756 | efx_stats_disable(efx); |
177dfcd8 | 757 | efx->phy_op->fini(efx); |
dc8cfa55 | 758 | efx->port_initialized = false; |
8ceee660 | 759 | |
eb50c0d6 | 760 | efx->link_state.up = false; |
8ceee660 BH |
761 | efx_link_status_changed(efx); |
762 | } | |
763 | ||
764 | static void efx_remove_port(struct efx_nic *efx) | |
765 | { | |
766 | EFX_LOG(efx, "destroying port\n"); | |
767 | ||
768 | falcon_remove_port(efx); | |
769 | } | |
770 | ||
771 | /************************************************************************** | |
772 | * | |
773 | * NIC handling | |
774 | * | |
775 | **************************************************************************/ | |
776 | ||
777 | /* This configures the PCI device to enable I/O and DMA. */ | |
778 | static int efx_init_io(struct efx_nic *efx) | |
779 | { | |
780 | struct pci_dev *pci_dev = efx->pci_dev; | |
781 | dma_addr_t dma_mask = efx->type->max_dma_mask; | |
782 | int rc; | |
783 | ||
784 | EFX_LOG(efx, "initialising I/O\n"); | |
785 | ||
786 | rc = pci_enable_device(pci_dev); | |
787 | if (rc) { | |
788 | EFX_ERR(efx, "failed to enable PCI device\n"); | |
789 | goto fail1; | |
790 | } | |
791 | ||
792 | pci_set_master(pci_dev); | |
793 | ||
794 | /* Set the PCI DMA mask. Try all possibilities from our | |
795 | * genuine mask down to 32 bits, because some architectures | |
796 | * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit | |
797 | * masks event though they reject 46 bit masks. | |
798 | */ | |
799 | while (dma_mask > 0x7fffffffUL) { | |
800 | if (pci_dma_supported(pci_dev, dma_mask) && | |
801 | ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0)) | |
802 | break; | |
803 | dma_mask >>= 1; | |
804 | } | |
805 | if (rc) { | |
806 | EFX_ERR(efx, "could not find a suitable DMA mask\n"); | |
807 | goto fail2; | |
808 | } | |
809 | EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask); | |
810 | rc = pci_set_consistent_dma_mask(pci_dev, dma_mask); | |
811 | if (rc) { | |
812 | /* pci_set_consistent_dma_mask() is not *allowed* to | |
813 | * fail with a mask that pci_set_dma_mask() accepted, | |
814 | * but just in case... | |
815 | */ | |
816 | EFX_ERR(efx, "failed to set consistent DMA mask\n"); | |
817 | goto fail2; | |
818 | } | |
819 | ||
dc803df8 BH |
820 | efx->membase_phys = pci_resource_start(efx->pci_dev, EFX_MEM_BAR); |
821 | rc = pci_request_region(pci_dev, EFX_MEM_BAR, "sfc"); | |
8ceee660 BH |
822 | if (rc) { |
823 | EFX_ERR(efx, "request for memory BAR failed\n"); | |
824 | rc = -EIO; | |
825 | goto fail3; | |
826 | } | |
827 | efx->membase = ioremap_nocache(efx->membase_phys, | |
828 | efx->type->mem_map_size); | |
829 | if (!efx->membase) { | |
dc803df8 | 830 | EFX_ERR(efx, "could not map memory BAR at %llx+%x\n", |
086ea356 | 831 | (unsigned long long)efx->membase_phys, |
8ceee660 BH |
832 | efx->type->mem_map_size); |
833 | rc = -ENOMEM; | |
834 | goto fail4; | |
835 | } | |
dc803df8 BH |
836 | EFX_LOG(efx, "memory BAR at %llx+%x (virtual %p)\n", |
837 | (unsigned long long)efx->membase_phys, | |
086ea356 | 838 | efx->type->mem_map_size, efx->membase); |
8ceee660 BH |
839 | |
840 | return 0; | |
841 | ||
842 | fail4: | |
dc803df8 | 843 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
8ceee660 | 844 | fail3: |
2c118e0f | 845 | efx->membase_phys = 0; |
8ceee660 BH |
846 | fail2: |
847 | pci_disable_device(efx->pci_dev); | |
848 | fail1: | |
849 | return rc; | |
850 | } | |
851 | ||
852 | static void efx_fini_io(struct efx_nic *efx) | |
853 | { | |
854 | EFX_LOG(efx, "shutting down I/O\n"); | |
855 | ||
856 | if (efx->membase) { | |
857 | iounmap(efx->membase); | |
858 | efx->membase = NULL; | |
859 | } | |
860 | ||
861 | if (efx->membase_phys) { | |
dc803df8 | 862 | pci_release_region(efx->pci_dev, EFX_MEM_BAR); |
2c118e0f | 863 | efx->membase_phys = 0; |
8ceee660 BH |
864 | } |
865 | ||
866 | pci_disable_device(efx->pci_dev); | |
867 | } | |
868 | ||
46123d04 BH |
869 | /* Get number of RX queues wanted. Return number of online CPU |
870 | * packages in the expectation that an IRQ balancer will spread | |
871 | * interrupts across them. */ | |
872 | static int efx_wanted_rx_queues(void) | |
873 | { | |
2f8975fb | 874 | cpumask_var_t core_mask; |
46123d04 BH |
875 | int count; |
876 | int cpu; | |
877 | ||
79f55997 | 878 | if (unlikely(!zalloc_cpumask_var(&core_mask, GFP_KERNEL))) { |
2f8975fb | 879 | printk(KERN_WARNING |
3977d033 | 880 | "sfc: RSS disabled due to allocation failure\n"); |
2f8975fb RR |
881 | return 1; |
882 | } | |
883 | ||
46123d04 BH |
884 | count = 0; |
885 | for_each_online_cpu(cpu) { | |
2f8975fb | 886 | if (!cpumask_test_cpu(cpu, core_mask)) { |
46123d04 | 887 | ++count; |
2f8975fb | 888 | cpumask_or(core_mask, core_mask, |
fbd59a8d | 889 | topology_core_cpumask(cpu)); |
46123d04 BH |
890 | } |
891 | } | |
892 | ||
2f8975fb | 893 | free_cpumask_var(core_mask); |
46123d04 BH |
894 | return count; |
895 | } | |
896 | ||
897 | /* Probe the number and type of interrupts we are able to obtain, and | |
898 | * the resulting numbers of channels and RX queues. | |
899 | */ | |
8ceee660 BH |
900 | static void efx_probe_interrupts(struct efx_nic *efx) |
901 | { | |
46123d04 BH |
902 | int max_channels = |
903 | min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS); | |
8ceee660 BH |
904 | int rc, i; |
905 | ||
906 | if (efx->interrupt_mode == EFX_INT_MODE_MSIX) { | |
46123d04 BH |
907 | struct msix_entry xentries[EFX_MAX_CHANNELS]; |
908 | int wanted_ints; | |
28b581ab | 909 | int rx_queues; |
aa6ef27e | 910 | |
46123d04 BH |
911 | /* We want one RX queue and interrupt per CPU package |
912 | * (or as specified by the rss_cpus module parameter). | |
913 | * We will need one channel per interrupt. | |
914 | */ | |
28b581ab NT |
915 | rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues(); |
916 | wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0); | |
917 | wanted_ints = min(wanted_ints, max_channels); | |
8ceee660 | 918 | |
28b581ab | 919 | for (i = 0; i < wanted_ints; i++) |
8ceee660 | 920 | xentries[i].entry = i; |
28b581ab | 921 | rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints); |
8ceee660 | 922 | if (rc > 0) { |
28b581ab NT |
923 | EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors" |
924 | " available (%d < %d).\n", rc, wanted_ints); | |
925 | EFX_ERR(efx, "WARNING: Performance may be reduced.\n"); | |
926 | EFX_BUG_ON_PARANOID(rc >= wanted_ints); | |
927 | wanted_ints = rc; | |
8ceee660 | 928 | rc = pci_enable_msix(efx->pci_dev, xentries, |
28b581ab | 929 | wanted_ints); |
8ceee660 BH |
930 | } |
931 | ||
932 | if (rc == 0) { | |
28b581ab NT |
933 | efx->n_rx_queues = min(rx_queues, wanted_ints); |
934 | efx->n_channels = wanted_ints; | |
935 | for (i = 0; i < wanted_ints; i++) | |
8ceee660 | 936 | efx->channel[i].irq = xentries[i].vector; |
8ceee660 BH |
937 | } else { |
938 | /* Fall back to single channel MSI */ | |
939 | efx->interrupt_mode = EFX_INT_MODE_MSI; | |
940 | EFX_ERR(efx, "could not enable MSI-X\n"); | |
941 | } | |
942 | } | |
943 | ||
944 | /* Try single interrupt MSI */ | |
945 | if (efx->interrupt_mode == EFX_INT_MODE_MSI) { | |
8831da7b | 946 | efx->n_rx_queues = 1; |
28b581ab | 947 | efx->n_channels = 1; |
8ceee660 BH |
948 | rc = pci_enable_msi(efx->pci_dev); |
949 | if (rc == 0) { | |
950 | efx->channel[0].irq = efx->pci_dev->irq; | |
8ceee660 BH |
951 | } else { |
952 | EFX_ERR(efx, "could not enable MSI\n"); | |
953 | efx->interrupt_mode = EFX_INT_MODE_LEGACY; | |
954 | } | |
955 | } | |
956 | ||
957 | /* Assume legacy interrupts */ | |
958 | if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) { | |
8831da7b | 959 | efx->n_rx_queues = 1; |
28b581ab | 960 | efx->n_channels = 1 + (separate_tx_channels ? 1 : 0); |
8ceee660 BH |
961 | efx->legacy_irq = efx->pci_dev->irq; |
962 | } | |
963 | } | |
964 | ||
965 | static void efx_remove_interrupts(struct efx_nic *efx) | |
966 | { | |
967 | struct efx_channel *channel; | |
968 | ||
969 | /* Remove MSI/MSI-X interrupts */ | |
64ee3120 | 970 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
971 | channel->irq = 0; |
972 | pci_disable_msi(efx->pci_dev); | |
973 | pci_disable_msix(efx->pci_dev); | |
974 | ||
975 | /* Remove legacy interrupt */ | |
976 | efx->legacy_irq = 0; | |
977 | } | |
978 | ||
8831da7b | 979 | static void efx_set_channels(struct efx_nic *efx) |
8ceee660 BH |
980 | { |
981 | struct efx_tx_queue *tx_queue; | |
982 | struct efx_rx_queue *rx_queue; | |
8ceee660 | 983 | |
60ac1065 | 984 | efx_for_each_tx_queue(tx_queue, efx) { |
28b581ab NT |
985 | if (separate_tx_channels) |
986 | tx_queue->channel = &efx->channel[efx->n_channels-1]; | |
60ac1065 BH |
987 | else |
988 | tx_queue->channel = &efx->channel[0]; | |
989 | tx_queue->channel->used_flags |= EFX_USED_BY_TX; | |
990 | } | |
8ceee660 | 991 | |
8831da7b BH |
992 | efx_for_each_rx_queue(rx_queue, efx) { |
993 | rx_queue->channel = &efx->channel[rx_queue->queue]; | |
994 | rx_queue->channel->used_flags |= EFX_USED_BY_RX; | |
8ceee660 BH |
995 | } |
996 | } | |
997 | ||
998 | static int efx_probe_nic(struct efx_nic *efx) | |
999 | { | |
1000 | int rc; | |
1001 | ||
1002 | EFX_LOG(efx, "creating NIC\n"); | |
1003 | ||
1004 | /* Carry out hardware-type specific initialisation */ | |
1005 | rc = falcon_probe_nic(efx); | |
1006 | if (rc) | |
1007 | return rc; | |
1008 | ||
1009 | /* Determine the number of channels and RX queues by trying to hook | |
1010 | * in MSI-X interrupts. */ | |
1011 | efx_probe_interrupts(efx); | |
1012 | ||
8831da7b | 1013 | efx_set_channels(efx); |
8ceee660 BH |
1014 | |
1015 | /* Initialise the interrupt moderation settings */ | |
6fb70fd1 | 1016 | efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true); |
8ceee660 BH |
1017 | |
1018 | return 0; | |
1019 | } | |
1020 | ||
1021 | static void efx_remove_nic(struct efx_nic *efx) | |
1022 | { | |
1023 | EFX_LOG(efx, "destroying NIC\n"); | |
1024 | ||
1025 | efx_remove_interrupts(efx); | |
1026 | falcon_remove_nic(efx); | |
1027 | } | |
1028 | ||
1029 | /************************************************************************** | |
1030 | * | |
1031 | * NIC startup/shutdown | |
1032 | * | |
1033 | *************************************************************************/ | |
1034 | ||
1035 | static int efx_probe_all(struct efx_nic *efx) | |
1036 | { | |
1037 | struct efx_channel *channel; | |
1038 | int rc; | |
1039 | ||
1040 | /* Create NIC */ | |
1041 | rc = efx_probe_nic(efx); | |
1042 | if (rc) { | |
1043 | EFX_ERR(efx, "failed to create NIC\n"); | |
1044 | goto fail1; | |
1045 | } | |
1046 | ||
1047 | /* Create port */ | |
1048 | rc = efx_probe_port(efx); | |
1049 | if (rc) { | |
1050 | EFX_ERR(efx, "failed to create port\n"); | |
1051 | goto fail2; | |
1052 | } | |
1053 | ||
1054 | /* Create channels */ | |
1055 | efx_for_each_channel(channel, efx) { | |
1056 | rc = efx_probe_channel(channel); | |
1057 | if (rc) { | |
1058 | EFX_ERR(efx, "failed to create channel %d\n", | |
1059 | channel->channel); | |
1060 | goto fail3; | |
1061 | } | |
1062 | } | |
56536e9c | 1063 | efx_set_channel_names(efx); |
8ceee660 BH |
1064 | |
1065 | return 0; | |
1066 | ||
1067 | fail3: | |
1068 | efx_for_each_channel(channel, efx) | |
1069 | efx_remove_channel(channel); | |
1070 | efx_remove_port(efx); | |
1071 | fail2: | |
1072 | efx_remove_nic(efx); | |
1073 | fail1: | |
1074 | return rc; | |
1075 | } | |
1076 | ||
1077 | /* Called after previous invocation(s) of efx_stop_all, restarts the | |
1078 | * port, kernel transmit queue, NAPI processing and hardware interrupts, | |
1079 | * and ensures that the port is scheduled to be reconfigured. | |
1080 | * This function is safe to call multiple times when the NIC is in any | |
1081 | * state. */ | |
1082 | static void efx_start_all(struct efx_nic *efx) | |
1083 | { | |
1084 | struct efx_channel *channel; | |
1085 | ||
1086 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1087 | ||
1088 | /* Check that it is appropriate to restart the interface. All | |
1089 | * of these flags are safe to read under just the rtnl lock */ | |
1090 | if (efx->port_enabled) | |
1091 | return; | |
1092 | if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT)) | |
1093 | return; | |
55668611 | 1094 | if (efx_dev_registered(efx) && !netif_running(efx->net_dev)) |
8ceee660 BH |
1095 | return; |
1096 | ||
1097 | /* Mark the port as enabled so port reconfigurations can start, then | |
1098 | * restart the transmit interface early so the watchdog timer stops */ | |
1099 | efx_start_port(efx); | |
dacccc74 SH |
1100 | if (efx_dev_registered(efx)) |
1101 | efx_wake_queue(efx); | |
8ceee660 BH |
1102 | |
1103 | efx_for_each_channel(channel, efx) | |
1104 | efx_start_channel(channel); | |
1105 | ||
1106 | falcon_enable_interrupts(efx); | |
1107 | ||
1108 | /* Start hardware monitor if we're in RUNNING */ | |
1109 | if (efx->state == STATE_RUNNING) | |
1110 | queue_delayed_work(efx->workqueue, &efx->monitor_work, | |
1111 | efx_monitor_interval); | |
1112 | } | |
1113 | ||
1114 | /* Flush all delayed work. Should only be called when no more delayed work | |
1115 | * will be scheduled. This doesn't flush pending online resets (efx_reset), | |
1116 | * since we're holding the rtnl_lock at this point. */ | |
1117 | static void efx_flush_all(struct efx_nic *efx) | |
1118 | { | |
1119 | struct efx_rx_queue *rx_queue; | |
1120 | ||
1121 | /* Make sure the hardware monitor is stopped */ | |
1122 | cancel_delayed_work_sync(&efx->monitor_work); | |
1123 | ||
1124 | /* Ensure that all RX slow refills are complete. */ | |
b3475645 | 1125 | efx_for_each_rx_queue(rx_queue, efx) |
8ceee660 | 1126 | cancel_delayed_work_sync(&rx_queue->work); |
8ceee660 BH |
1127 | |
1128 | /* Stop scheduled port reconfigurations */ | |
766ca0fa BH |
1129 | cancel_work_sync(&efx->mac_work); |
1130 | cancel_work_sync(&efx->phy_work); | |
8ceee660 BH |
1131 | |
1132 | } | |
1133 | ||
1134 | /* Quiesce hardware and software without bringing the link down. | |
1135 | * Safe to call multiple times, when the nic and interface is in any | |
1136 | * state. The caller is guaranteed to subsequently be in a position | |
1137 | * to modify any hardware and software state they see fit without | |
1138 | * taking locks. */ | |
1139 | static void efx_stop_all(struct efx_nic *efx) | |
1140 | { | |
1141 | struct efx_channel *channel; | |
1142 | ||
1143 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1144 | ||
1145 | /* port_enabled can be read safely under the rtnl lock */ | |
1146 | if (!efx->port_enabled) | |
1147 | return; | |
1148 | ||
1149 | /* Disable interrupts and wait for ISR to complete */ | |
1150 | falcon_disable_interrupts(efx); | |
1151 | if (efx->legacy_irq) | |
1152 | synchronize_irq(efx->legacy_irq); | |
64ee3120 | 1153 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1154 | if (channel->irq) |
1155 | synchronize_irq(channel->irq); | |
b3475645 | 1156 | } |
8ceee660 BH |
1157 | |
1158 | /* Stop all NAPI processing and synchronous rx refills */ | |
1159 | efx_for_each_channel(channel, efx) | |
1160 | efx_stop_channel(channel); | |
1161 | ||
1162 | /* Stop all asynchronous port reconfigurations. Since all | |
1163 | * event processing has already been stopped, there is no | |
1164 | * window to loose phy events */ | |
1165 | efx_stop_port(efx); | |
1166 | ||
766ca0fa | 1167 | /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */ |
8ceee660 BH |
1168 | efx_flush_all(efx); |
1169 | ||
1170 | /* Isolate the MAC from the TX and RX engines, so that queue | |
1171 | * flushes will complete in a timely fashion. */ | |
5c8af3b9 BH |
1172 | falcon_deconfigure_mac_wrapper(efx); |
1173 | msleep(10); /* Let the Rx FIFO drain */ | |
8ceee660 BH |
1174 | falcon_drain_tx_fifo(efx); |
1175 | ||
1176 | /* Stop the kernel transmit interface late, so the watchdog | |
1177 | * timer isn't ticking over the flush */ | |
55668611 | 1178 | if (efx_dev_registered(efx)) { |
dacccc74 | 1179 | efx_stop_queue(efx); |
8ceee660 BH |
1180 | netif_tx_lock_bh(efx->net_dev); |
1181 | netif_tx_unlock_bh(efx->net_dev); | |
1182 | } | |
1183 | } | |
1184 | ||
1185 | static void efx_remove_all(struct efx_nic *efx) | |
1186 | { | |
1187 | struct efx_channel *channel; | |
1188 | ||
1189 | efx_for_each_channel(channel, efx) | |
1190 | efx_remove_channel(channel); | |
1191 | efx_remove_port(efx); | |
1192 | efx_remove_nic(efx); | |
1193 | } | |
1194 | ||
1195 | /* A convinience function to safely flush all the queues */ | |
bc3c90a2 | 1196 | void efx_flush_queues(struct efx_nic *efx) |
8ceee660 | 1197 | { |
8ceee660 BH |
1198 | EFX_ASSERT_RESET_SERIALISED(efx); |
1199 | ||
1200 | efx_stop_all(efx); | |
1201 | ||
1202 | efx_fini_channels(efx); | |
bc3c90a2 | 1203 | efx_init_channels(efx); |
8ceee660 BH |
1204 | |
1205 | efx_start_all(efx); | |
8ceee660 BH |
1206 | } |
1207 | ||
1208 | /************************************************************************** | |
1209 | * | |
1210 | * Interrupt moderation | |
1211 | * | |
1212 | **************************************************************************/ | |
1213 | ||
0d86ebd8 BH |
1214 | static unsigned irq_mod_ticks(int usecs, int resolution) |
1215 | { | |
1216 | if (usecs <= 0) | |
1217 | return 0; /* cannot receive interrupts ahead of time :-) */ | |
1218 | if (usecs < resolution) | |
1219 | return 1; /* never round down to 0 */ | |
1220 | return usecs / resolution; | |
1221 | } | |
1222 | ||
8ceee660 | 1223 | /* Set interrupt moderation parameters */ |
6fb70fd1 BH |
1224 | void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs, |
1225 | bool rx_adaptive) | |
8ceee660 BH |
1226 | { |
1227 | struct efx_tx_queue *tx_queue; | |
1228 | struct efx_rx_queue *rx_queue; | |
0d86ebd8 BH |
1229 | unsigned tx_ticks = irq_mod_ticks(tx_usecs, FALCON_IRQ_MOD_RESOLUTION); |
1230 | unsigned rx_ticks = irq_mod_ticks(rx_usecs, FALCON_IRQ_MOD_RESOLUTION); | |
8ceee660 BH |
1231 | |
1232 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1233 | ||
1234 | efx_for_each_tx_queue(tx_queue, efx) | |
0d86ebd8 | 1235 | tx_queue->channel->irq_moderation = tx_ticks; |
8ceee660 | 1236 | |
6fb70fd1 | 1237 | efx->irq_rx_adaptive = rx_adaptive; |
0d86ebd8 | 1238 | efx->irq_rx_moderation = rx_ticks; |
8ceee660 | 1239 | efx_for_each_rx_queue(rx_queue, efx) |
0d86ebd8 | 1240 | rx_queue->channel->irq_moderation = rx_ticks; |
8ceee660 BH |
1241 | } |
1242 | ||
1243 | /************************************************************************** | |
1244 | * | |
1245 | * Hardware monitor | |
1246 | * | |
1247 | **************************************************************************/ | |
1248 | ||
1249 | /* Run periodically off the general workqueue. Serialised against | |
1250 | * efx_reconfigure_port via the mac_lock */ | |
1251 | static void efx_monitor(struct work_struct *data) | |
1252 | { | |
1253 | struct efx_nic *efx = container_of(data, struct efx_nic, | |
1254 | monitor_work.work); | |
766ca0fa | 1255 | int rc; |
8ceee660 BH |
1256 | |
1257 | EFX_TRACE(efx, "hardware monitor executing on CPU %d\n", | |
1258 | raw_smp_processor_id()); | |
1259 | ||
8ceee660 BH |
1260 | /* If the mac_lock is already held then it is likely a port |
1261 | * reconfiguration is already in place, which will likely do | |
1262 | * most of the work of check_hw() anyway. */ | |
766ca0fa BH |
1263 | if (!mutex_trylock(&efx->mac_lock)) |
1264 | goto out_requeue; | |
1265 | if (!efx->port_enabled) | |
1266 | goto out_unlock; | |
278c0621 | 1267 | rc = falcon_board(efx)->monitor(efx); |
766ca0fa BH |
1268 | if (rc) { |
1269 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
1270 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
1271 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
1272 | falcon_sim_phy_event(efx); | |
8ceee660 | 1273 | } |
766ca0fa BH |
1274 | efx->phy_op->poll(efx); |
1275 | efx->mac_op->poll(efx); | |
8ceee660 | 1276 | |
766ca0fa | 1277 | out_unlock: |
8ceee660 | 1278 | mutex_unlock(&efx->mac_lock); |
766ca0fa | 1279 | out_requeue: |
8ceee660 BH |
1280 | queue_delayed_work(efx->workqueue, &efx->monitor_work, |
1281 | efx_monitor_interval); | |
1282 | } | |
1283 | ||
1284 | /************************************************************************** | |
1285 | * | |
1286 | * ioctls | |
1287 | * | |
1288 | *************************************************************************/ | |
1289 | ||
1290 | /* Net device ioctl | |
1291 | * Context: process, rtnl_lock() held. | |
1292 | */ | |
1293 | static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd) | |
1294 | { | |
767e468c | 1295 | struct efx_nic *efx = netdev_priv(net_dev); |
68e7f45e | 1296 | struct mii_ioctl_data *data = if_mii(ifr); |
8ceee660 BH |
1297 | |
1298 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1299 | ||
68e7f45e BH |
1300 | /* Convert phy_id from older PRTAD/DEVAD format */ |
1301 | if ((cmd == SIOCGMIIREG || cmd == SIOCSMIIREG) && | |
1302 | (data->phy_id & 0xfc00) == 0x0400) | |
1303 | data->phy_id ^= MDIO_PHY_ID_C45 | 0x0400; | |
1304 | ||
1305 | return mdio_mii_ioctl(&efx->mdio, data, cmd); | |
8ceee660 BH |
1306 | } |
1307 | ||
1308 | /************************************************************************** | |
1309 | * | |
1310 | * NAPI interface | |
1311 | * | |
1312 | **************************************************************************/ | |
1313 | ||
1314 | static int efx_init_napi(struct efx_nic *efx) | |
1315 | { | |
1316 | struct efx_channel *channel; | |
8ceee660 BH |
1317 | |
1318 | efx_for_each_channel(channel, efx) { | |
1319 | channel->napi_dev = efx->net_dev; | |
718cff1e BH |
1320 | netif_napi_add(channel->napi_dev, &channel->napi_str, |
1321 | efx_poll, napi_weight); | |
8ceee660 BH |
1322 | } |
1323 | return 0; | |
8ceee660 BH |
1324 | } |
1325 | ||
1326 | static void efx_fini_napi(struct efx_nic *efx) | |
1327 | { | |
1328 | struct efx_channel *channel; | |
1329 | ||
1330 | efx_for_each_channel(channel, efx) { | |
718cff1e BH |
1331 | if (channel->napi_dev) |
1332 | netif_napi_del(&channel->napi_str); | |
8ceee660 BH |
1333 | channel->napi_dev = NULL; |
1334 | } | |
1335 | } | |
1336 | ||
1337 | /************************************************************************** | |
1338 | * | |
1339 | * Kernel netpoll interface | |
1340 | * | |
1341 | *************************************************************************/ | |
1342 | ||
1343 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1344 | ||
1345 | /* Although in the common case interrupts will be disabled, this is not | |
1346 | * guaranteed. However, all our work happens inside the NAPI callback, | |
1347 | * so no locking is required. | |
1348 | */ | |
1349 | static void efx_netpoll(struct net_device *net_dev) | |
1350 | { | |
767e468c | 1351 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1352 | struct efx_channel *channel; |
1353 | ||
64ee3120 | 1354 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1355 | efx_schedule_channel(channel); |
1356 | } | |
1357 | ||
1358 | #endif | |
1359 | ||
1360 | /************************************************************************** | |
1361 | * | |
1362 | * Kernel net device interface | |
1363 | * | |
1364 | *************************************************************************/ | |
1365 | ||
1366 | /* Context: process, rtnl_lock() held. */ | |
1367 | static int efx_net_open(struct net_device *net_dev) | |
1368 | { | |
767e468c | 1369 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1370 | EFX_ASSERT_RESET_SERIALISED(efx); |
1371 | ||
1372 | EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name, | |
1373 | raw_smp_processor_id()); | |
1374 | ||
f4bd954e BH |
1375 | if (efx->state == STATE_DISABLED) |
1376 | return -EIO; | |
f8b87c17 BH |
1377 | if (efx->phy_mode & PHY_MODE_SPECIAL) |
1378 | return -EBUSY; | |
1379 | ||
8ceee660 BH |
1380 | efx_start_all(efx); |
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | /* Context: process, rtnl_lock() held. | |
1385 | * Note that the kernel will ignore our return code; this method | |
1386 | * should really be a void. | |
1387 | */ | |
1388 | static int efx_net_stop(struct net_device *net_dev) | |
1389 | { | |
767e468c | 1390 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1391 | |
1392 | EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name, | |
1393 | raw_smp_processor_id()); | |
1394 | ||
f4bd954e BH |
1395 | if (efx->state != STATE_DISABLED) { |
1396 | /* Stop the device and flush all the channels */ | |
1397 | efx_stop_all(efx); | |
1398 | efx_fini_channels(efx); | |
1399 | efx_init_channels(efx); | |
1400 | } | |
8ceee660 BH |
1401 | |
1402 | return 0; | |
1403 | } | |
1404 | ||
1974cc20 BH |
1405 | void efx_stats_disable(struct efx_nic *efx) |
1406 | { | |
1407 | spin_lock(&efx->stats_lock); | |
1408 | ++efx->stats_disable_count; | |
1409 | spin_unlock(&efx->stats_lock); | |
1410 | } | |
1411 | ||
1412 | void efx_stats_enable(struct efx_nic *efx) | |
1413 | { | |
1414 | spin_lock(&efx->stats_lock); | |
1415 | --efx->stats_disable_count; | |
1416 | spin_unlock(&efx->stats_lock); | |
1417 | } | |
1418 | ||
5b9e207c | 1419 | /* Context: process, dev_base_lock or RTNL held, non-blocking. */ |
8ceee660 BH |
1420 | static struct net_device_stats *efx_net_stats(struct net_device *net_dev) |
1421 | { | |
767e468c | 1422 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1423 | struct efx_mac_stats *mac_stats = &efx->mac_stats; |
1424 | struct net_device_stats *stats = &net_dev->stats; | |
1425 | ||
5b9e207c | 1426 | /* Update stats if possible, but do not wait if another thread |
1974cc20 BH |
1427 | * is updating them or if MAC stats fetches are temporarily |
1428 | * disabled; slightly stale stats are acceptable. | |
5b9e207c | 1429 | */ |
8ceee660 BH |
1430 | if (!spin_trylock(&efx->stats_lock)) |
1431 | return stats; | |
1974cc20 | 1432 | if (!efx->stats_disable_count) { |
177dfcd8 | 1433 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1434 | falcon_update_nic_stats(efx); |
1435 | } | |
1436 | spin_unlock(&efx->stats_lock); | |
1437 | ||
1438 | stats->rx_packets = mac_stats->rx_packets; | |
1439 | stats->tx_packets = mac_stats->tx_packets; | |
1440 | stats->rx_bytes = mac_stats->rx_bytes; | |
1441 | stats->tx_bytes = mac_stats->tx_bytes; | |
1442 | stats->multicast = mac_stats->rx_multicast; | |
1443 | stats->collisions = mac_stats->tx_collision; | |
1444 | stats->rx_length_errors = (mac_stats->rx_gtjumbo + | |
1445 | mac_stats->rx_length_error); | |
1446 | stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt; | |
1447 | stats->rx_crc_errors = mac_stats->rx_bad; | |
1448 | stats->rx_frame_errors = mac_stats->rx_align_error; | |
1449 | stats->rx_fifo_errors = mac_stats->rx_overflow; | |
1450 | stats->rx_missed_errors = mac_stats->rx_missed; | |
1451 | stats->tx_window_errors = mac_stats->tx_late_collision; | |
1452 | ||
1453 | stats->rx_errors = (stats->rx_length_errors + | |
1454 | stats->rx_over_errors + | |
1455 | stats->rx_crc_errors + | |
1456 | stats->rx_frame_errors + | |
1457 | stats->rx_fifo_errors + | |
1458 | stats->rx_missed_errors + | |
1459 | mac_stats->rx_symbol_error); | |
1460 | stats->tx_errors = (stats->tx_window_errors + | |
1461 | mac_stats->tx_bad); | |
1462 | ||
1463 | return stats; | |
1464 | } | |
1465 | ||
1466 | /* Context: netif_tx_lock held, BHs disabled. */ | |
1467 | static void efx_watchdog(struct net_device *net_dev) | |
1468 | { | |
767e468c | 1469 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 1470 | |
739bb23d BH |
1471 | EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:" |
1472 | " resetting channels\n", | |
1473 | atomic_read(&efx->netif_stop_count), efx->port_enabled); | |
8ceee660 | 1474 | |
739bb23d | 1475 | efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG); |
8ceee660 BH |
1476 | } |
1477 | ||
1478 | ||
1479 | /* Context: process, rtnl_lock() held. */ | |
1480 | static int efx_change_mtu(struct net_device *net_dev, int new_mtu) | |
1481 | { | |
767e468c | 1482 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1483 | int rc = 0; |
1484 | ||
1485 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1486 | ||
1487 | if (new_mtu > EFX_MAX_MTU) | |
1488 | return -EINVAL; | |
1489 | ||
1490 | efx_stop_all(efx); | |
1491 | ||
1492 | EFX_LOG(efx, "changing MTU to %d\n", new_mtu); | |
1493 | ||
1494 | efx_fini_channels(efx); | |
1495 | net_dev->mtu = new_mtu; | |
bc3c90a2 | 1496 | efx_init_channels(efx); |
8ceee660 BH |
1497 | |
1498 | efx_start_all(efx); | |
1499 | return rc; | |
8ceee660 BH |
1500 | } |
1501 | ||
1502 | static int efx_set_mac_address(struct net_device *net_dev, void *data) | |
1503 | { | |
767e468c | 1504 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1505 | struct sockaddr *addr = data; |
1506 | char *new_addr = addr->sa_data; | |
1507 | ||
1508 | EFX_ASSERT_RESET_SERIALISED(efx); | |
1509 | ||
1510 | if (!is_valid_ether_addr(new_addr)) { | |
e174961c JB |
1511 | EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n", |
1512 | new_addr); | |
8ceee660 BH |
1513 | return -EINVAL; |
1514 | } | |
1515 | ||
1516 | memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len); | |
1517 | ||
1518 | /* Reconfigure the MAC */ | |
1519 | efx_reconfigure_port(efx); | |
1520 | ||
1521 | return 0; | |
1522 | } | |
1523 | ||
a816f75a | 1524 | /* Context: netif_addr_lock held, BHs disabled. */ |
8ceee660 BH |
1525 | static void efx_set_multicast_list(struct net_device *net_dev) |
1526 | { | |
767e468c | 1527 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1528 | struct dev_mc_list *mc_list = net_dev->mc_list; |
1529 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
a816f75a BH |
1530 | bool promiscuous = !!(net_dev->flags & IFF_PROMISC); |
1531 | bool changed = (efx->promiscuous != promiscuous); | |
8ceee660 BH |
1532 | u32 crc; |
1533 | int bit; | |
1534 | int i; | |
1535 | ||
a816f75a | 1536 | efx->promiscuous = promiscuous; |
8ceee660 BH |
1537 | |
1538 | /* Build multicast hash table */ | |
1539 | if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) { | |
1540 | memset(mc_hash, 0xff, sizeof(*mc_hash)); | |
1541 | } else { | |
1542 | memset(mc_hash, 0x00, sizeof(*mc_hash)); | |
1543 | for (i = 0; i < net_dev->mc_count; i++) { | |
1544 | crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr); | |
1545 | bit = crc & (EFX_MCAST_HASH_ENTRIES - 1); | |
1546 | set_bit_le(bit, mc_hash->byte); | |
1547 | mc_list = mc_list->next; | |
1548 | } | |
1549 | } | |
1550 | ||
a816f75a BH |
1551 | if (!efx->port_enabled) |
1552 | /* Delay pushing settings until efx_start_port() */ | |
1553 | return; | |
1554 | ||
1555 | if (changed) | |
766ca0fa | 1556 | queue_work(efx->workqueue, &efx->phy_work); |
a816f75a | 1557 | |
8ceee660 BH |
1558 | /* Create and activate new global multicast hash table */ |
1559 | falcon_set_multicast_hash(efx); | |
1560 | } | |
1561 | ||
c3ecb9f3 SH |
1562 | static const struct net_device_ops efx_netdev_ops = { |
1563 | .ndo_open = efx_net_open, | |
1564 | .ndo_stop = efx_net_stop, | |
1565 | .ndo_get_stats = efx_net_stats, | |
1566 | .ndo_tx_timeout = efx_watchdog, | |
1567 | .ndo_start_xmit = efx_hard_start_xmit, | |
1568 | .ndo_validate_addr = eth_validate_addr, | |
1569 | .ndo_do_ioctl = efx_ioctl, | |
1570 | .ndo_change_mtu = efx_change_mtu, | |
1571 | .ndo_set_mac_address = efx_set_mac_address, | |
1572 | .ndo_set_multicast_list = efx_set_multicast_list, | |
1573 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1574 | .ndo_poll_controller = efx_netpoll, | |
1575 | #endif | |
1576 | }; | |
1577 | ||
7dde596e BH |
1578 | static void efx_update_name(struct efx_nic *efx) |
1579 | { | |
1580 | strcpy(efx->name, efx->net_dev->name); | |
1581 | efx_mtd_rename(efx); | |
1582 | efx_set_channel_names(efx); | |
1583 | } | |
1584 | ||
8ceee660 BH |
1585 | static int efx_netdev_event(struct notifier_block *this, |
1586 | unsigned long event, void *ptr) | |
1587 | { | |
d3208b5e | 1588 | struct net_device *net_dev = ptr; |
8ceee660 | 1589 | |
7dde596e BH |
1590 | if (net_dev->netdev_ops == &efx_netdev_ops && |
1591 | event == NETDEV_CHANGENAME) | |
1592 | efx_update_name(netdev_priv(net_dev)); | |
8ceee660 BH |
1593 | |
1594 | return NOTIFY_DONE; | |
1595 | } | |
1596 | ||
1597 | static struct notifier_block efx_netdev_notifier = { | |
1598 | .notifier_call = efx_netdev_event, | |
1599 | }; | |
1600 | ||
06d5e193 BH |
1601 | static ssize_t |
1602 | show_phy_type(struct device *dev, struct device_attribute *attr, char *buf) | |
1603 | { | |
1604 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
1605 | return sprintf(buf, "%d\n", efx->phy_type); | |
1606 | } | |
1607 | static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL); | |
1608 | ||
8ceee660 BH |
1609 | static int efx_register_netdev(struct efx_nic *efx) |
1610 | { | |
1611 | struct net_device *net_dev = efx->net_dev; | |
1612 | int rc; | |
1613 | ||
1614 | net_dev->watchdog_timeo = 5 * HZ; | |
1615 | net_dev->irq = efx->pci_dev->irq; | |
c3ecb9f3 | 1616 | net_dev->netdev_ops = &efx_netdev_ops; |
8ceee660 BH |
1617 | SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev); |
1618 | SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops); | |
1619 | ||
8ceee660 | 1620 | /* Clear MAC statistics */ |
177dfcd8 | 1621 | efx->mac_op->update_stats(efx); |
8ceee660 BH |
1622 | memset(&efx->mac_stats, 0, sizeof(efx->mac_stats)); |
1623 | ||
7dde596e | 1624 | rtnl_lock(); |
aed0628d BH |
1625 | |
1626 | rc = dev_alloc_name(net_dev, net_dev->name); | |
1627 | if (rc < 0) | |
1628 | goto fail_locked; | |
7dde596e | 1629 | efx_update_name(efx); |
aed0628d BH |
1630 | |
1631 | rc = register_netdevice(net_dev); | |
1632 | if (rc) | |
1633 | goto fail_locked; | |
1634 | ||
1635 | /* Always start with carrier off; PHY events will detect the link */ | |
1636 | netif_carrier_off(efx->net_dev); | |
1637 | ||
7dde596e | 1638 | rtnl_unlock(); |
8ceee660 | 1639 | |
06d5e193 BH |
1640 | rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
1641 | if (rc) { | |
1642 | EFX_ERR(efx, "failed to init net dev attributes\n"); | |
1643 | goto fail_registered; | |
1644 | } | |
1645 | ||
8ceee660 | 1646 | return 0; |
06d5e193 | 1647 | |
aed0628d BH |
1648 | fail_locked: |
1649 | rtnl_unlock(); | |
1650 | EFX_ERR(efx, "could not register net dev\n"); | |
1651 | return rc; | |
1652 | ||
06d5e193 BH |
1653 | fail_registered: |
1654 | unregister_netdev(net_dev); | |
1655 | return rc; | |
8ceee660 BH |
1656 | } |
1657 | ||
1658 | static void efx_unregister_netdev(struct efx_nic *efx) | |
1659 | { | |
1660 | struct efx_tx_queue *tx_queue; | |
1661 | ||
1662 | if (!efx->net_dev) | |
1663 | return; | |
1664 | ||
767e468c | 1665 | BUG_ON(netdev_priv(efx->net_dev) != efx); |
8ceee660 BH |
1666 | |
1667 | /* Free up any skbs still remaining. This has to happen before | |
1668 | * we try to unregister the netdev as running their destructors | |
1669 | * may be needed to get the device ref. count to 0. */ | |
1670 | efx_for_each_tx_queue(tx_queue, efx) | |
1671 | efx_release_tx_buffers(tx_queue); | |
1672 | ||
55668611 | 1673 | if (efx_dev_registered(efx)) { |
8ceee660 | 1674 | strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name)); |
06d5e193 | 1675 | device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type); |
8ceee660 BH |
1676 | unregister_netdev(efx->net_dev); |
1677 | } | |
1678 | } | |
1679 | ||
1680 | /************************************************************************** | |
1681 | * | |
1682 | * Device reset and suspend | |
1683 | * | |
1684 | **************************************************************************/ | |
1685 | ||
2467ca46 BH |
1686 | /* Tears down the entire software state and most of the hardware state |
1687 | * before reset. */ | |
4b988280 SH |
1688 | void efx_reset_down(struct efx_nic *efx, enum reset_type method, |
1689 | struct ethtool_cmd *ecmd) | |
8ceee660 | 1690 | { |
8ceee660 BH |
1691 | EFX_ASSERT_RESET_SERIALISED(efx); |
1692 | ||
1974cc20 | 1693 | efx_stats_disable(efx); |
2467ca46 BH |
1694 | efx_stop_all(efx); |
1695 | mutex_lock(&efx->mac_lock); | |
f4150724 | 1696 | mutex_lock(&efx->spi_lock); |
2467ca46 | 1697 | |
177dfcd8 | 1698 | efx->phy_op->get_settings(efx, ecmd); |
8ceee660 BH |
1699 | |
1700 | efx_fini_channels(efx); | |
4b988280 SH |
1701 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) |
1702 | efx->phy_op->fini(efx); | |
8ceee660 BH |
1703 | } |
1704 | ||
2467ca46 BH |
1705 | /* This function will always ensure that the locks acquired in |
1706 | * efx_reset_down() are released. A failure return code indicates | |
1707 | * that we were unable to reinitialise the hardware, and the | |
1708 | * driver should be disabled. If ok is false, then the rx and tx | |
1709 | * engines are not restarted, pending a RESET_DISABLE. */ | |
4b988280 SH |
1710 | int efx_reset_up(struct efx_nic *efx, enum reset_type method, |
1711 | struct ethtool_cmd *ecmd, bool ok) | |
8ceee660 BH |
1712 | { |
1713 | int rc; | |
1714 | ||
2467ca46 | 1715 | EFX_ASSERT_RESET_SERIALISED(efx); |
8ceee660 | 1716 | |
2467ca46 | 1717 | rc = falcon_init_nic(efx); |
8ceee660 | 1718 | if (rc) { |
2467ca46 BH |
1719 | EFX_ERR(efx, "failed to initialise NIC\n"); |
1720 | ok = false; | |
8ceee660 BH |
1721 | } |
1722 | ||
4b988280 SH |
1723 | if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) { |
1724 | if (ok) { | |
1725 | rc = efx->phy_op->init(efx); | |
1726 | if (rc) | |
1727 | ok = false; | |
115122af BH |
1728 | } |
1729 | if (!ok) | |
4b988280 SH |
1730 | efx->port_initialized = false; |
1731 | } | |
1732 | ||
2467ca46 BH |
1733 | if (ok) { |
1734 | efx_init_channels(efx); | |
8ceee660 | 1735 | |
177dfcd8 | 1736 | if (efx->phy_op->set_settings(efx, ecmd)) |
2467ca46 BH |
1737 | EFX_ERR(efx, "could not restore PHY settings\n"); |
1738 | } | |
1739 | ||
f4150724 | 1740 | mutex_unlock(&efx->spi_lock); |
2467ca46 BH |
1741 | mutex_unlock(&efx->mac_lock); |
1742 | ||
8c8661e4 | 1743 | if (ok) { |
2467ca46 | 1744 | efx_start_all(efx); |
1974cc20 | 1745 | efx_stats_enable(efx); |
8c8661e4 | 1746 | } |
8ceee660 BH |
1747 | return rc; |
1748 | } | |
1749 | ||
1750 | /* Reset the NIC as transparently as possible. Do not reset the PHY | |
1751 | * Note that the reset may fail, in which case the card will be left | |
1752 | * in a most-probably-unusable state. | |
1753 | * | |
1754 | * This function will sleep. You cannot reset from within an atomic | |
1755 | * state; use efx_schedule_reset() instead. | |
1756 | * | |
1757 | * Grabs the rtnl_lock. | |
1758 | */ | |
1759 | static int efx_reset(struct efx_nic *efx) | |
1760 | { | |
1761 | struct ethtool_cmd ecmd; | |
1762 | enum reset_type method = efx->reset_pending; | |
f4bd954e | 1763 | int rc = 0; |
8ceee660 BH |
1764 | |
1765 | /* Serialise with kernel interfaces */ | |
1766 | rtnl_lock(); | |
1767 | ||
1768 | /* If we're not RUNNING then don't reset. Leave the reset_pending | |
1769 | * flag set so that efx_pci_probe_main will be retried */ | |
1770 | if (efx->state != STATE_RUNNING) { | |
1771 | EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n"); | |
f4bd954e | 1772 | goto out_unlock; |
8ceee660 BH |
1773 | } |
1774 | ||
8ceee660 BH |
1775 | EFX_INFO(efx, "resetting (%d)\n", method); |
1776 | ||
4b988280 | 1777 | efx_reset_down(efx, method, &ecmd); |
8ceee660 BH |
1778 | |
1779 | rc = falcon_reset_hw(efx, method); | |
1780 | if (rc) { | |
1781 | EFX_ERR(efx, "failed to reset hardware\n"); | |
f4bd954e | 1782 | goto out_disable; |
8ceee660 BH |
1783 | } |
1784 | ||
1785 | /* Allow resets to be rescheduled. */ | |
1786 | efx->reset_pending = RESET_TYPE_NONE; | |
1787 | ||
1788 | /* Reinitialise bus-mastering, which may have been turned off before | |
1789 | * the reset was scheduled. This is still appropriate, even in the | |
1790 | * RESET_TYPE_DISABLE since this driver generally assumes the hardware | |
1791 | * can respond to requests. */ | |
1792 | pci_set_master(efx->pci_dev); | |
1793 | ||
8ceee660 BH |
1794 | /* Leave device stopped if necessary */ |
1795 | if (method == RESET_TYPE_DISABLE) { | |
4b988280 | 1796 | efx_reset_up(efx, method, &ecmd, false); |
8ceee660 | 1797 | rc = -EIO; |
f4bd954e | 1798 | } else { |
4b988280 | 1799 | rc = efx_reset_up(efx, method, &ecmd, true); |
8ceee660 BH |
1800 | } |
1801 | ||
f4bd954e BH |
1802 | out_disable: |
1803 | if (rc) { | |
1804 | EFX_ERR(efx, "has been disabled\n"); | |
1805 | efx->state = STATE_DISABLED; | |
1806 | dev_close(efx->net_dev); | |
1807 | } else { | |
1808 | EFX_LOG(efx, "reset complete\n"); | |
1809 | } | |
8ceee660 | 1810 | |
f4bd954e | 1811 | out_unlock: |
8ceee660 | 1812 | rtnl_unlock(); |
8ceee660 BH |
1813 | return rc; |
1814 | } | |
1815 | ||
1816 | /* The worker thread exists so that code that cannot sleep can | |
1817 | * schedule a reset for later. | |
1818 | */ | |
1819 | static void efx_reset_work(struct work_struct *data) | |
1820 | { | |
1821 | struct efx_nic *nic = container_of(data, struct efx_nic, reset_work); | |
1822 | ||
1823 | efx_reset(nic); | |
1824 | } | |
1825 | ||
1826 | void efx_schedule_reset(struct efx_nic *efx, enum reset_type type) | |
1827 | { | |
1828 | enum reset_type method; | |
1829 | ||
1830 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
1831 | EFX_INFO(efx, "quenching already scheduled reset\n"); | |
1832 | return; | |
1833 | } | |
1834 | ||
1835 | switch (type) { | |
1836 | case RESET_TYPE_INVISIBLE: | |
1837 | case RESET_TYPE_ALL: | |
1838 | case RESET_TYPE_WORLD: | |
1839 | case RESET_TYPE_DISABLE: | |
1840 | method = type; | |
1841 | break; | |
1842 | case RESET_TYPE_RX_RECOVERY: | |
1843 | case RESET_TYPE_RX_DESC_FETCH: | |
1844 | case RESET_TYPE_TX_DESC_FETCH: | |
1845 | case RESET_TYPE_TX_SKIP: | |
1846 | method = RESET_TYPE_INVISIBLE; | |
1847 | break; | |
1848 | default: | |
1849 | method = RESET_TYPE_ALL; | |
1850 | break; | |
1851 | } | |
1852 | ||
1853 | if (method != type) | |
1854 | EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method); | |
1855 | else | |
1856 | EFX_LOG(efx, "scheduling reset (%d)\n", method); | |
1857 | ||
1858 | efx->reset_pending = method; | |
1859 | ||
1ab00629 | 1860 | queue_work(reset_workqueue, &efx->reset_work); |
8ceee660 BH |
1861 | } |
1862 | ||
1863 | /************************************************************************** | |
1864 | * | |
1865 | * List of NICs we support | |
1866 | * | |
1867 | **************************************************************************/ | |
1868 | ||
1869 | /* PCI device ID table */ | |
1870 | static struct pci_device_id efx_pci_table[] __devinitdata = { | |
1871 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID), | |
1872 | .driver_data = (unsigned long) &falcon_a_nic_type}, | |
1873 | {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID), | |
1874 | .driver_data = (unsigned long) &falcon_b_nic_type}, | |
1875 | {0} /* end of list */ | |
1876 | }; | |
1877 | ||
1878 | /************************************************************************** | |
1879 | * | |
3759433d | 1880 | * Dummy PHY/MAC operations |
8ceee660 | 1881 | * |
01aad7b6 | 1882 | * Can be used for some unimplemented operations |
8ceee660 BH |
1883 | * Needed so all function pointers are valid and do not have to be tested |
1884 | * before use | |
1885 | * | |
1886 | **************************************************************************/ | |
1887 | int efx_port_dummy_op_int(struct efx_nic *efx) | |
1888 | { | |
1889 | return 0; | |
1890 | } | |
1891 | void efx_port_dummy_op_void(struct efx_nic *efx) {} | |
398468ed BH |
1892 | void efx_port_dummy_op_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1893 | { | |
1894 | } | |
8ceee660 | 1895 | |
177dfcd8 BH |
1896 | static struct efx_mac_operations efx_dummy_mac_operations = { |
1897 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa BH |
1898 | .poll = efx_port_dummy_op_void, |
1899 | .irq = efx_port_dummy_op_void, | |
177dfcd8 BH |
1900 | }; |
1901 | ||
8ceee660 BH |
1902 | static struct efx_phy_operations efx_dummy_phy_operations = { |
1903 | .init = efx_port_dummy_op_int, | |
1904 | .reconfigure = efx_port_dummy_op_void, | |
766ca0fa | 1905 | .poll = efx_port_dummy_op_void, |
8ceee660 BH |
1906 | .fini = efx_port_dummy_op_void, |
1907 | .clear_interrupt = efx_port_dummy_op_void, | |
8ceee660 BH |
1908 | }; |
1909 | ||
8ceee660 BH |
1910 | /************************************************************************** |
1911 | * | |
1912 | * Data housekeeping | |
1913 | * | |
1914 | **************************************************************************/ | |
1915 | ||
1916 | /* This zeroes out and then fills in the invariants in a struct | |
1917 | * efx_nic (including all sub-structures). | |
1918 | */ | |
1919 | static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type, | |
1920 | struct pci_dev *pci_dev, struct net_device *net_dev) | |
1921 | { | |
1922 | struct efx_channel *channel; | |
1923 | struct efx_tx_queue *tx_queue; | |
1924 | struct efx_rx_queue *rx_queue; | |
1ab00629 | 1925 | int i; |
8ceee660 BH |
1926 | |
1927 | /* Initialise common structures */ | |
1928 | memset(efx, 0, sizeof(*efx)); | |
1929 | spin_lock_init(&efx->biu_lock); | |
1930 | spin_lock_init(&efx->phy_lock); | |
f4150724 | 1931 | mutex_init(&efx->spi_lock); |
8ceee660 BH |
1932 | INIT_WORK(&efx->reset_work, efx_reset_work); |
1933 | INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor); | |
1934 | efx->pci_dev = pci_dev; | |
1935 | efx->state = STATE_INIT; | |
1936 | efx->reset_pending = RESET_TYPE_NONE; | |
1937 | strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name)); | |
8ceee660 BH |
1938 | |
1939 | efx->net_dev = net_dev; | |
dc8cfa55 | 1940 | efx->rx_checksum_enabled = true; |
8ceee660 BH |
1941 | spin_lock_init(&efx->netif_stop_lock); |
1942 | spin_lock_init(&efx->stats_lock); | |
1974cc20 | 1943 | efx->stats_disable_count = 1; |
8ceee660 | 1944 | mutex_init(&efx->mac_lock); |
177dfcd8 | 1945 | efx->mac_op = &efx_dummy_mac_operations; |
8ceee660 | 1946 | efx->phy_op = &efx_dummy_phy_operations; |
68e7f45e | 1947 | efx->mdio.dev = net_dev; |
766ca0fa BH |
1948 | INIT_WORK(&efx->phy_work, efx_phy_work); |
1949 | INIT_WORK(&efx->mac_work, efx_mac_work); | |
8ceee660 BH |
1950 | atomic_set(&efx->netif_stop_count, 1); |
1951 | ||
1952 | for (i = 0; i < EFX_MAX_CHANNELS; i++) { | |
1953 | channel = &efx->channel[i]; | |
1954 | channel->efx = efx; | |
1955 | channel->channel = i; | |
dc8cfa55 | 1956 | channel->work_pending = false; |
8ceee660 | 1957 | } |
60ac1065 | 1958 | for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) { |
8ceee660 BH |
1959 | tx_queue = &efx->tx_queue[i]; |
1960 | tx_queue->efx = efx; | |
1961 | tx_queue->queue = i; | |
1962 | tx_queue->buffer = NULL; | |
1963 | tx_queue->channel = &efx->channel[0]; /* for safety */ | |
b9b39b62 | 1964 | tx_queue->tso_headers_free = NULL; |
8ceee660 BH |
1965 | } |
1966 | for (i = 0; i < EFX_MAX_RX_QUEUES; i++) { | |
1967 | rx_queue = &efx->rx_queue[i]; | |
1968 | rx_queue->efx = efx; | |
1969 | rx_queue->queue = i; | |
1970 | rx_queue->channel = &efx->channel[0]; /* for safety */ | |
1971 | rx_queue->buffer = NULL; | |
1972 | spin_lock_init(&rx_queue->add_lock); | |
1973 | INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work); | |
1974 | } | |
1975 | ||
1976 | efx->type = type; | |
1977 | ||
8ceee660 | 1978 | /* As close as we can get to guaranteeing that we don't overflow */ |
3ffeabdd BH |
1979 | BUILD_BUG_ON(EFX_EVQ_SIZE < EFX_TXQ_SIZE + EFX_RXQ_SIZE); |
1980 | ||
8ceee660 BH |
1981 | EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS); |
1982 | ||
1983 | /* Higher numbered interrupt modes are less capable! */ | |
1984 | efx->interrupt_mode = max(efx->type->max_interrupt_mode, | |
1985 | interrupt_mode); | |
1986 | ||
6977dc63 BH |
1987 | /* Would be good to use the net_dev name, but we're too early */ |
1988 | snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s", | |
1989 | pci_name(pci_dev)); | |
1990 | efx->workqueue = create_singlethread_workqueue(efx->workqueue_name); | |
1ab00629 SH |
1991 | if (!efx->workqueue) |
1992 | return -ENOMEM; | |
8d9853d9 | 1993 | |
8ceee660 | 1994 | return 0; |
8ceee660 BH |
1995 | } |
1996 | ||
1997 | static void efx_fini_struct(struct efx_nic *efx) | |
1998 | { | |
1999 | if (efx->workqueue) { | |
2000 | destroy_workqueue(efx->workqueue); | |
2001 | efx->workqueue = NULL; | |
2002 | } | |
2003 | } | |
2004 | ||
2005 | /************************************************************************** | |
2006 | * | |
2007 | * PCI interface | |
2008 | * | |
2009 | **************************************************************************/ | |
2010 | ||
2011 | /* Main body of final NIC shutdown code | |
2012 | * This is called only at module unload (or hotplug removal). | |
2013 | */ | |
2014 | static void efx_pci_remove_main(struct efx_nic *efx) | |
2015 | { | |
f01865f0 | 2016 | falcon_fini_interrupt(efx); |
8ceee660 BH |
2017 | efx_fini_channels(efx); |
2018 | efx_fini_port(efx); | |
8ceee660 BH |
2019 | efx_fini_napi(efx); |
2020 | efx_remove_all(efx); | |
2021 | } | |
2022 | ||
2023 | /* Final NIC shutdown | |
2024 | * This is called only at module unload (or hotplug removal). | |
2025 | */ | |
2026 | static void efx_pci_remove(struct pci_dev *pci_dev) | |
2027 | { | |
2028 | struct efx_nic *efx; | |
2029 | ||
2030 | efx = pci_get_drvdata(pci_dev); | |
2031 | if (!efx) | |
2032 | return; | |
2033 | ||
2034 | /* Mark the NIC as fini, then stop the interface */ | |
2035 | rtnl_lock(); | |
2036 | efx->state = STATE_FINI; | |
2037 | dev_close(efx->net_dev); | |
2038 | ||
2039 | /* Allow any queued efx_resets() to complete */ | |
2040 | rtnl_unlock(); | |
2041 | ||
8ceee660 BH |
2042 | efx_unregister_netdev(efx); |
2043 | ||
7dde596e BH |
2044 | efx_mtd_remove(efx); |
2045 | ||
8ceee660 BH |
2046 | /* Wait for any scheduled resets to complete. No more will be |
2047 | * scheduled from this point because efx_stop_all() has been | |
2048 | * called, we are no longer registered with driverlink, and | |
2049 | * the net_device's have been removed. */ | |
1ab00629 | 2050 | cancel_work_sync(&efx->reset_work); |
8ceee660 BH |
2051 | |
2052 | efx_pci_remove_main(efx); | |
2053 | ||
8ceee660 BH |
2054 | efx_fini_io(efx); |
2055 | EFX_LOG(efx, "shutdown successful\n"); | |
2056 | ||
2057 | pci_set_drvdata(pci_dev, NULL); | |
2058 | efx_fini_struct(efx); | |
2059 | free_netdev(efx->net_dev); | |
2060 | }; | |
2061 | ||
2062 | /* Main body of NIC initialisation | |
2063 | * This is called at module load (or hotplug insertion, theoretically). | |
2064 | */ | |
2065 | static int efx_pci_probe_main(struct efx_nic *efx) | |
2066 | { | |
2067 | int rc; | |
2068 | ||
2069 | /* Do start-of-day initialisation */ | |
2070 | rc = efx_probe_all(efx); | |
2071 | if (rc) | |
2072 | goto fail1; | |
2073 | ||
2074 | rc = efx_init_napi(efx); | |
2075 | if (rc) | |
2076 | goto fail2; | |
2077 | ||
8ceee660 BH |
2078 | rc = falcon_init_nic(efx); |
2079 | if (rc) { | |
2080 | EFX_ERR(efx, "failed to initialise NIC\n"); | |
278c0621 | 2081 | goto fail3; |
8ceee660 BH |
2082 | } |
2083 | ||
2084 | rc = efx_init_port(efx); | |
2085 | if (rc) { | |
2086 | EFX_ERR(efx, "failed to initialise port\n"); | |
278c0621 | 2087 | goto fail4; |
8ceee660 BH |
2088 | } |
2089 | ||
bc3c90a2 | 2090 | efx_init_channels(efx); |
8ceee660 BH |
2091 | |
2092 | rc = falcon_init_interrupt(efx); | |
2093 | if (rc) | |
278c0621 | 2094 | goto fail5; |
8ceee660 BH |
2095 | |
2096 | return 0; | |
2097 | ||
278c0621 | 2098 | fail5: |
bc3c90a2 | 2099 | efx_fini_channels(efx); |
8ceee660 | 2100 | efx_fini_port(efx); |
8ceee660 BH |
2101 | fail4: |
2102 | fail3: | |
2103 | efx_fini_napi(efx); | |
2104 | fail2: | |
2105 | efx_remove_all(efx); | |
2106 | fail1: | |
2107 | return rc; | |
2108 | } | |
2109 | ||
2110 | /* NIC initialisation | |
2111 | * | |
2112 | * This is called at module load (or hotplug insertion, | |
2113 | * theoretically). It sets up PCI mappings, tests and resets the NIC, | |
2114 | * sets up and registers the network devices with the kernel and hooks | |
2115 | * the interrupt service routine. It does not prepare the device for | |
2116 | * transmission; this is left to the first time one of the network | |
2117 | * interfaces is brought up (i.e. efx_net_open). | |
2118 | */ | |
2119 | static int __devinit efx_pci_probe(struct pci_dev *pci_dev, | |
2120 | const struct pci_device_id *entry) | |
2121 | { | |
2122 | struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data; | |
2123 | struct net_device *net_dev; | |
2124 | struct efx_nic *efx; | |
2125 | int i, rc; | |
2126 | ||
2127 | /* Allocate and initialise a struct net_device and struct efx_nic */ | |
2128 | net_dev = alloc_etherdev(sizeof(*efx)); | |
2129 | if (!net_dev) | |
2130 | return -ENOMEM; | |
b9b39b62 | 2131 | net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG | |
97bc5415 BH |
2132 | NETIF_F_HIGHDMA | NETIF_F_TSO | |
2133 | NETIF_F_GRO); | |
28506563 BH |
2134 | /* Mask for features that also apply to VLAN devices */ |
2135 | net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG | | |
740847da | 2136 | NETIF_F_HIGHDMA | NETIF_F_TSO); |
767e468c | 2137 | efx = netdev_priv(net_dev); |
8ceee660 BH |
2138 | pci_set_drvdata(pci_dev, efx); |
2139 | rc = efx_init_struct(efx, type, pci_dev, net_dev); | |
2140 | if (rc) | |
2141 | goto fail1; | |
2142 | ||
2143 | EFX_INFO(efx, "Solarflare Communications NIC detected\n"); | |
2144 | ||
2145 | /* Set up basic I/O (BAR mappings etc) */ | |
2146 | rc = efx_init_io(efx); | |
2147 | if (rc) | |
2148 | goto fail2; | |
2149 | ||
2150 | /* No serialisation is required with the reset path because | |
2151 | * we're in STATE_INIT. */ | |
2152 | for (i = 0; i < 5; i++) { | |
2153 | rc = efx_pci_probe_main(efx); | |
8ceee660 BH |
2154 | |
2155 | /* Serialise against efx_reset(). No more resets will be | |
2156 | * scheduled since efx_stop_all() has been called, and we | |
2157 | * have not and never have been registered with either | |
2158 | * the rtnetlink or driverlink layers. */ | |
1ab00629 | 2159 | cancel_work_sync(&efx->reset_work); |
8ceee660 | 2160 | |
fa402b2e SH |
2161 | if (rc == 0) { |
2162 | if (efx->reset_pending != RESET_TYPE_NONE) { | |
2163 | /* If there was a scheduled reset during | |
2164 | * probe, the NIC is probably hosed anyway */ | |
2165 | efx_pci_remove_main(efx); | |
2166 | rc = -EIO; | |
2167 | } else { | |
2168 | break; | |
2169 | } | |
2170 | } | |
2171 | ||
8ceee660 BH |
2172 | /* Retry if a recoverably reset event has been scheduled */ |
2173 | if ((efx->reset_pending != RESET_TYPE_INVISIBLE) && | |
2174 | (efx->reset_pending != RESET_TYPE_ALL)) | |
2175 | goto fail3; | |
2176 | ||
2177 | efx->reset_pending = RESET_TYPE_NONE; | |
2178 | } | |
2179 | ||
2180 | if (rc) { | |
2181 | EFX_ERR(efx, "Could not reset NIC\n"); | |
2182 | goto fail4; | |
2183 | } | |
2184 | ||
2185 | /* Switch to the running state before we expose the device to | |
2186 | * the OS. This is to ensure that the initial gathering of | |
2187 | * MAC stats succeeds. */ | |
8ceee660 | 2188 | efx->state = STATE_RUNNING; |
7dde596e | 2189 | |
8ceee660 BH |
2190 | rc = efx_register_netdev(efx); |
2191 | if (rc) | |
2192 | goto fail5; | |
2193 | ||
2194 | EFX_LOG(efx, "initialisation successful\n"); | |
a5211bb5 BH |
2195 | |
2196 | rtnl_lock(); | |
2197 | efx_mtd_probe(efx); /* allowed to fail */ | |
2198 | rtnl_unlock(); | |
8ceee660 BH |
2199 | return 0; |
2200 | ||
2201 | fail5: | |
2202 | efx_pci_remove_main(efx); | |
2203 | fail4: | |
2204 | fail3: | |
2205 | efx_fini_io(efx); | |
2206 | fail2: | |
2207 | efx_fini_struct(efx); | |
2208 | fail1: | |
2209 | EFX_LOG(efx, "initialisation failed. rc=%d\n", rc); | |
2210 | free_netdev(net_dev); | |
2211 | return rc; | |
2212 | } | |
2213 | ||
2214 | static struct pci_driver efx_pci_driver = { | |
2215 | .name = EFX_DRIVER_NAME, | |
2216 | .id_table = efx_pci_table, | |
2217 | .probe = efx_pci_probe, | |
2218 | .remove = efx_pci_remove, | |
2219 | }; | |
2220 | ||
2221 | /************************************************************************** | |
2222 | * | |
2223 | * Kernel module interface | |
2224 | * | |
2225 | *************************************************************************/ | |
2226 | ||
2227 | module_param(interrupt_mode, uint, 0444); | |
2228 | MODULE_PARM_DESC(interrupt_mode, | |
2229 | "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)"); | |
2230 | ||
2231 | static int __init efx_init_module(void) | |
2232 | { | |
2233 | int rc; | |
2234 | ||
2235 | printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n"); | |
2236 | ||
2237 | rc = register_netdevice_notifier(&efx_netdev_notifier); | |
2238 | if (rc) | |
2239 | goto err_notifier; | |
2240 | ||
2241 | refill_workqueue = create_workqueue("sfc_refill"); | |
2242 | if (!refill_workqueue) { | |
2243 | rc = -ENOMEM; | |
2244 | goto err_refill; | |
2245 | } | |
1ab00629 SH |
2246 | reset_workqueue = create_singlethread_workqueue("sfc_reset"); |
2247 | if (!reset_workqueue) { | |
2248 | rc = -ENOMEM; | |
2249 | goto err_reset; | |
2250 | } | |
8ceee660 BH |
2251 | |
2252 | rc = pci_register_driver(&efx_pci_driver); | |
2253 | if (rc < 0) | |
2254 | goto err_pci; | |
2255 | ||
2256 | return 0; | |
2257 | ||
2258 | err_pci: | |
1ab00629 SH |
2259 | destroy_workqueue(reset_workqueue); |
2260 | err_reset: | |
8ceee660 BH |
2261 | destroy_workqueue(refill_workqueue); |
2262 | err_refill: | |
2263 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2264 | err_notifier: | |
2265 | return rc; | |
2266 | } | |
2267 | ||
2268 | static void __exit efx_exit_module(void) | |
2269 | { | |
2270 | printk(KERN_INFO "Solarflare NET driver unloading\n"); | |
2271 | ||
2272 | pci_unregister_driver(&efx_pci_driver); | |
1ab00629 | 2273 | destroy_workqueue(reset_workqueue); |
8ceee660 BH |
2274 | destroy_workqueue(refill_workqueue); |
2275 | unregister_netdevice_notifier(&efx_netdev_notifier); | |
2276 | ||
2277 | } | |
2278 | ||
2279 | module_init(efx_init_module); | |
2280 | module_exit(efx_exit_module); | |
2281 | ||
2282 | MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and " | |
2283 | "Solarflare Communications"); | |
2284 | MODULE_DESCRIPTION("Solarflare Communications network driver"); | |
2285 | MODULE_LICENSE("GPL"); | |
2286 | MODULE_DEVICE_TABLE(pci, efx_pci_table); |