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1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 BH |
16 | #include <linux/i2c.h> |
17 | #include <linux/i2c-algo-bit.h> | |
8ceee660 BH |
18 | #include "net_driver.h" |
19 | #include "bitfield.h" | |
20 | #include "efx.h" | |
21 | #include "mac.h" | |
22 | #include "gmii.h" | |
23 | #include "spi.h" | |
24 | #include "falcon.h" | |
25 | #include "falcon_hwdefs.h" | |
26 | #include "falcon_io.h" | |
27 | #include "mdio_10g.h" | |
28 | #include "phy.h" | |
29 | #include "boards.h" | |
30 | #include "workarounds.h" | |
31 | ||
32 | /* Falcon hardware control. | |
33 | * Falcon is the internal codename for the SFC4000 controller that is | |
34 | * present in SFE400X evaluation boards | |
35 | */ | |
36 | ||
37 | /** | |
38 | * struct falcon_nic_data - Falcon NIC state | |
39 | * @next_buffer_table: First available buffer table id | |
40 | * @pci_dev2: The secondary PCI device if present | |
37b5a603 | 41 | * @i2c_data: Operations and state for I2C bit-bashing algorithm |
8ceee660 BH |
42 | */ |
43 | struct falcon_nic_data { | |
44 | unsigned next_buffer_table; | |
45 | struct pci_dev *pci_dev2; | |
37b5a603 | 46 | struct i2c_algo_bit_data i2c_data; |
8ceee660 BH |
47 | }; |
48 | ||
49 | /************************************************************************** | |
50 | * | |
51 | * Configurable values | |
52 | * | |
53 | ************************************************************************** | |
54 | */ | |
55 | ||
56 | static int disable_dma_stats; | |
57 | ||
58 | /* This is set to 16 for a good reason. In summary, if larger than | |
59 | * 16, the descriptor cache holds more than a default socket | |
60 | * buffer's worth of packets (for UDP we can only have at most one | |
61 | * socket buffer's worth outstanding). This combined with the fact | |
62 | * that we only get 1 TX event per descriptor cache means the NIC | |
63 | * goes idle. | |
64 | */ | |
65 | #define TX_DC_ENTRIES 16 | |
66 | #define TX_DC_ENTRIES_ORDER 0 | |
67 | #define TX_DC_BASE 0x130000 | |
68 | ||
69 | #define RX_DC_ENTRIES 64 | |
70 | #define RX_DC_ENTRIES_ORDER 2 | |
71 | #define RX_DC_BASE 0x100000 | |
72 | ||
73 | /* RX FIFO XOFF watermark | |
74 | * | |
75 | * When the amount of the RX FIFO increases used increases past this | |
76 | * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A) | |
77 | * This also has an effect on RX/TX arbitration | |
78 | */ | |
79 | static int rx_xoff_thresh_bytes = -1; | |
80 | module_param(rx_xoff_thresh_bytes, int, 0644); | |
81 | MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold"); | |
82 | ||
83 | /* RX FIFO XON watermark | |
84 | * | |
85 | * When the amount of the RX FIFO used decreases below this | |
86 | * watermark send XON. Only used if TX flow control is enabled (ethtool -A) | |
87 | * This also has an effect on RX/TX arbitration | |
88 | */ | |
89 | static int rx_xon_thresh_bytes = -1; | |
90 | module_param(rx_xon_thresh_bytes, int, 0644); | |
91 | MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold"); | |
92 | ||
93 | /* TX descriptor ring size - min 512 max 4k */ | |
94 | #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K | |
95 | #define FALCON_TXD_RING_SIZE 1024 | |
96 | #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1) | |
97 | ||
98 | /* RX descriptor ring size - min 512 max 4k */ | |
99 | #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K | |
100 | #define FALCON_RXD_RING_SIZE 1024 | |
101 | #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1) | |
102 | ||
103 | /* Event queue size - max 32k */ | |
104 | #define FALCON_EVQ_ORDER EVQ_SIZE_4K | |
105 | #define FALCON_EVQ_SIZE 4096 | |
106 | #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1) | |
107 | ||
108 | /* Max number of internal errors. After this resets will not be performed */ | |
109 | #define FALCON_MAX_INT_ERRORS 4 | |
110 | ||
111 | /* Maximum period that we wait for flush events. If the flush event | |
112 | * doesn't arrive in this period of time then we check if the queue | |
113 | * was disabled anyway. */ | |
114 | #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */ | |
115 | ||
116 | /************************************************************************** | |
117 | * | |
118 | * Falcon constants | |
119 | * | |
120 | ************************************************************************** | |
121 | */ | |
122 | ||
9bbd7d9a BH |
123 | /* DMA address mask */ |
124 | #define FALCON_DMA_MASK DMA_BIT_MASK(46) | |
8ceee660 BH |
125 | |
126 | /* TX DMA length mask (13-bit) */ | |
127 | #define FALCON_TX_DMA_MASK (4096 - 1) | |
128 | ||
129 | /* Size and alignment of special buffers (4KB) */ | |
130 | #define FALCON_BUF_SIZE 4096 | |
131 | ||
132 | /* Dummy SRAM size code */ | |
133 | #define SRM_NB_BSZ_ONCHIP_ONLY (-1) | |
134 | ||
135 | /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */ | |
136 | #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18 | |
137 | #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26 | |
138 | #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5 | |
139 | #define PCI_EXP_LNKSTA_LNK_WID 0x3f0 | |
140 | #define PCI_EXP_LNKSTA_LNK_WID_LBN 4 | |
141 | ||
142 | #define FALCON_IS_DUAL_FUNC(efx) \ | |
55668611 | 143 | (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
144 | |
145 | /************************************************************************** | |
146 | * | |
147 | * Falcon hardware access | |
148 | * | |
149 | **************************************************************************/ | |
150 | ||
151 | /* Read the current event from the event queue */ | |
152 | static inline efx_qword_t *falcon_event(struct efx_channel *channel, | |
153 | unsigned int index) | |
154 | { | |
155 | return (((efx_qword_t *) (channel->eventq.addr)) + index); | |
156 | } | |
157 | ||
158 | /* See if an event is present | |
159 | * | |
160 | * We check both the high and low dword of the event for all ones. We | |
161 | * wrote all ones when we cleared the event, and no valid event can | |
162 | * have all ones in either its high or low dwords. This approach is | |
163 | * robust against reordering. | |
164 | * | |
165 | * Note that using a single 64-bit comparison is incorrect; even | |
166 | * though the CPU read will be atomic, the DMA write may not be. | |
167 | */ | |
168 | static inline int falcon_event_present(efx_qword_t *event) | |
169 | { | |
170 | return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | | |
171 | EFX_DWORD_IS_ALL_ONES(event->dword[1]))); | |
172 | } | |
173 | ||
174 | /************************************************************************** | |
175 | * | |
176 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
177 | * Note that it uses the output enables to tristate the outputs | |
178 | * SDA is the data pin and SCL is the clock | |
179 | * | |
180 | ************************************************************************** | |
181 | */ | |
37b5a603 | 182 | static void falcon_setsda(void *data, int state) |
8ceee660 | 183 | { |
37b5a603 | 184 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
185 | efx_oword_t reg; |
186 | ||
37b5a603 BH |
187 | falcon_read(efx, ®, GPIO_CTL_REG_KER); |
188 | EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state); | |
189 | falcon_write(efx, ®, GPIO_CTL_REG_KER); | |
8ceee660 BH |
190 | } |
191 | ||
37b5a603 | 192 | static void falcon_setscl(void *data, int state) |
8ceee660 | 193 | { |
37b5a603 | 194 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
195 | efx_oword_t reg; |
196 | ||
37b5a603 BH |
197 | falcon_read(efx, ®, GPIO_CTL_REG_KER); |
198 | EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state); | |
199 | falcon_write(efx, ®, GPIO_CTL_REG_KER); | |
200 | } | |
201 | ||
202 | static int falcon_getsda(void *data) | |
203 | { | |
204 | struct efx_nic *efx = (struct efx_nic *)data; | |
205 | efx_oword_t reg; | |
206 | ||
207 | falcon_read(efx, ®, GPIO_CTL_REG_KER); | |
8ceee660 BH |
208 | return EFX_OWORD_FIELD(reg, GPIO3_IN); |
209 | } | |
210 | ||
37b5a603 | 211 | static int falcon_getscl(void *data) |
8ceee660 | 212 | { |
37b5a603 | 213 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
214 | efx_oword_t reg; |
215 | ||
37b5a603 BH |
216 | falcon_read(efx, ®, GPIO_CTL_REG_KER); |
217 | return EFX_OWORD_FIELD(reg, GPIO0_IN); | |
8ceee660 BH |
218 | } |
219 | ||
37b5a603 BH |
220 | static struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
221 | .setsda = falcon_setsda, | |
222 | .setscl = falcon_setscl, | |
8ceee660 BH |
223 | .getsda = falcon_getsda, |
224 | .getscl = falcon_getscl, | |
62c78329 | 225 | .udelay = 5, |
9dadae68 BH |
226 | /* Wait up to 50 ms for slave to let us pull SCL high */ |
227 | .timeout = DIV_ROUND_UP(HZ, 20), | |
8ceee660 BH |
228 | }; |
229 | ||
230 | /************************************************************************** | |
231 | * | |
232 | * Falcon special buffer handling | |
233 | * Special buffers are used for event queues and the TX and RX | |
234 | * descriptor rings. | |
235 | * | |
236 | *************************************************************************/ | |
237 | ||
238 | /* | |
239 | * Initialise a Falcon special buffer | |
240 | * | |
241 | * This will define a buffer (previously allocated via | |
242 | * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing | |
243 | * it to be used for event queues, descriptor rings etc. | |
244 | */ | |
245 | static int | |
246 | falcon_init_special_buffer(struct efx_nic *efx, | |
247 | struct efx_special_buffer *buffer) | |
248 | { | |
249 | efx_qword_t buf_desc; | |
250 | int index; | |
251 | dma_addr_t dma_addr; | |
252 | int i; | |
253 | ||
254 | EFX_BUG_ON_PARANOID(!buffer->addr); | |
255 | ||
256 | /* Write buffer descriptors to NIC */ | |
257 | for (i = 0; i < buffer->entries; i++) { | |
258 | index = buffer->index + i; | |
259 | dma_addr = buffer->dma_addr + (i * 4096); | |
260 | EFX_LOG(efx, "mapping special buffer %d at %llx\n", | |
261 | index, (unsigned long long)dma_addr); | |
262 | EFX_POPULATE_QWORD_4(buf_desc, | |
263 | IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K, | |
264 | BUF_ADR_REGION, 0, | |
265 | BUF_ADR_FBUF, (dma_addr >> 12), | |
266 | BUF_OWNER_ID_FBUF, 0); | |
267 | falcon_write_sram(efx, &buf_desc, index); | |
268 | } | |
269 | ||
270 | return 0; | |
271 | } | |
272 | ||
273 | /* Unmaps a buffer from Falcon and clears the buffer table entries */ | |
274 | static void | |
275 | falcon_fini_special_buffer(struct efx_nic *efx, | |
276 | struct efx_special_buffer *buffer) | |
277 | { | |
278 | efx_oword_t buf_tbl_upd; | |
279 | unsigned int start = buffer->index; | |
280 | unsigned int end = (buffer->index + buffer->entries - 1); | |
281 | ||
282 | if (!buffer->entries) | |
283 | return; | |
284 | ||
285 | EFX_LOG(efx, "unmapping special buffers %d-%d\n", | |
286 | buffer->index, buffer->index + buffer->entries - 1); | |
287 | ||
288 | EFX_POPULATE_OWORD_4(buf_tbl_upd, | |
289 | BUF_UPD_CMD, 0, | |
290 | BUF_CLR_CMD, 1, | |
291 | BUF_CLR_END_ID, end, | |
292 | BUF_CLR_START_ID, start); | |
293 | falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER); | |
294 | } | |
295 | ||
296 | /* | |
297 | * Allocate a new Falcon special buffer | |
298 | * | |
299 | * This allocates memory for a new buffer, clears it and allocates a | |
300 | * new buffer ID range. It does not write into Falcon's buffer table. | |
301 | * | |
302 | * This call will allocate 4KB buffers, since Falcon can't use 8KB | |
303 | * buffers for event queues and descriptor rings. | |
304 | */ | |
305 | static int falcon_alloc_special_buffer(struct efx_nic *efx, | |
306 | struct efx_special_buffer *buffer, | |
307 | unsigned int len) | |
308 | { | |
309 | struct falcon_nic_data *nic_data = efx->nic_data; | |
310 | ||
311 | len = ALIGN(len, FALCON_BUF_SIZE); | |
312 | ||
313 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
314 | &buffer->dma_addr); | |
315 | if (!buffer->addr) | |
316 | return -ENOMEM; | |
317 | buffer->len = len; | |
318 | buffer->entries = len / FALCON_BUF_SIZE; | |
319 | BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1)); | |
320 | ||
321 | /* All zeros is a potentially valid event so memset to 0xff */ | |
322 | memset(buffer->addr, 0xff, len); | |
323 | ||
324 | /* Select new buffer ID */ | |
325 | buffer->index = nic_data->next_buffer_table; | |
326 | nic_data->next_buffer_table += buffer->entries; | |
327 | ||
328 | EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x " | |
329 | "(virt %p phys %lx)\n", buffer->index, | |
330 | buffer->index + buffer->entries - 1, | |
331 | (unsigned long long)buffer->dma_addr, len, | |
332 | buffer->addr, virt_to_phys(buffer->addr)); | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static void falcon_free_special_buffer(struct efx_nic *efx, | |
338 | struct efx_special_buffer *buffer) | |
339 | { | |
340 | if (!buffer->addr) | |
341 | return; | |
342 | ||
343 | EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x " | |
344 | "(virt %p phys %lx)\n", buffer->index, | |
345 | buffer->index + buffer->entries - 1, | |
346 | (unsigned long long)buffer->dma_addr, buffer->len, | |
347 | buffer->addr, virt_to_phys(buffer->addr)); | |
348 | ||
349 | pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr, | |
350 | buffer->dma_addr); | |
351 | buffer->addr = NULL; | |
352 | buffer->entries = 0; | |
353 | } | |
354 | ||
355 | /************************************************************************** | |
356 | * | |
357 | * Falcon generic buffer handling | |
358 | * These buffers are used for interrupt status and MAC stats | |
359 | * | |
360 | **************************************************************************/ | |
361 | ||
362 | static int falcon_alloc_buffer(struct efx_nic *efx, | |
363 | struct efx_buffer *buffer, unsigned int len) | |
364 | { | |
365 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
366 | &buffer->dma_addr); | |
367 | if (!buffer->addr) | |
368 | return -ENOMEM; | |
369 | buffer->len = len; | |
370 | memset(buffer->addr, 0, len); | |
371 | return 0; | |
372 | } | |
373 | ||
374 | static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) | |
375 | { | |
376 | if (buffer->addr) { | |
377 | pci_free_consistent(efx->pci_dev, buffer->len, | |
378 | buffer->addr, buffer->dma_addr); | |
379 | buffer->addr = NULL; | |
380 | } | |
381 | } | |
382 | ||
383 | /************************************************************************** | |
384 | * | |
385 | * Falcon TX path | |
386 | * | |
387 | **************************************************************************/ | |
388 | ||
389 | /* Returns a pointer to the specified transmit descriptor in the TX | |
390 | * descriptor queue belonging to the specified channel. | |
391 | */ | |
392 | static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue, | |
393 | unsigned int index) | |
394 | { | |
395 | return (((efx_qword_t *) (tx_queue->txd.addr)) + index); | |
396 | } | |
397 | ||
398 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ | |
399 | static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue) | |
400 | { | |
401 | unsigned write_ptr; | |
402 | efx_dword_t reg; | |
403 | ||
404 | write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK; | |
405 | EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr); | |
406 | falcon_writel_page(tx_queue->efx, ®, | |
407 | TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue); | |
408 | } | |
409 | ||
410 | ||
411 | /* For each entry inserted into the software descriptor ring, create a | |
412 | * descriptor in the hardware TX descriptor ring (in host memory), and | |
413 | * write a doorbell. | |
414 | */ | |
415 | void falcon_push_buffers(struct efx_tx_queue *tx_queue) | |
416 | { | |
417 | ||
418 | struct efx_tx_buffer *buffer; | |
419 | efx_qword_t *txd; | |
420 | unsigned write_ptr; | |
421 | ||
422 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); | |
423 | ||
424 | do { | |
425 | write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK; | |
426 | buffer = &tx_queue->buffer[write_ptr]; | |
427 | txd = falcon_tx_desc(tx_queue, write_ptr); | |
428 | ++tx_queue->write_count; | |
429 | ||
430 | /* Create TX descriptor ring entry */ | |
431 | EFX_POPULATE_QWORD_5(*txd, | |
432 | TX_KER_PORT, 0, | |
433 | TX_KER_CONT, buffer->continuation, | |
434 | TX_KER_BYTE_CNT, buffer->len, | |
435 | TX_KER_BUF_REGION, 0, | |
436 | TX_KER_BUF_ADR, buffer->dma_addr); | |
437 | } while (tx_queue->write_count != tx_queue->insert_count); | |
438 | ||
439 | wmb(); /* Ensure descriptors are written before they are fetched */ | |
440 | falcon_notify_tx_desc(tx_queue); | |
441 | } | |
442 | ||
443 | /* Allocate hardware resources for a TX queue */ | |
444 | int falcon_probe_tx(struct efx_tx_queue *tx_queue) | |
445 | { | |
446 | struct efx_nic *efx = tx_queue->efx; | |
447 | return falcon_alloc_special_buffer(efx, &tx_queue->txd, | |
448 | FALCON_TXD_RING_SIZE * | |
449 | sizeof(efx_qword_t)); | |
450 | } | |
451 | ||
452 | int falcon_init_tx(struct efx_tx_queue *tx_queue) | |
453 | { | |
454 | efx_oword_t tx_desc_ptr; | |
455 | struct efx_nic *efx = tx_queue->efx; | |
456 | int rc; | |
457 | ||
458 | /* Pin TX descriptor ring */ | |
459 | rc = falcon_init_special_buffer(efx, &tx_queue->txd); | |
460 | if (rc) | |
461 | return rc; | |
462 | ||
463 | /* Push TX descriptor ring to card */ | |
464 | EFX_POPULATE_OWORD_10(tx_desc_ptr, | |
465 | TX_DESCQ_EN, 1, | |
466 | TX_ISCSI_DDIG_EN, 0, | |
467 | TX_ISCSI_HDIG_EN, 0, | |
468 | TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, | |
469 | TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum, | |
470 | TX_DESCQ_OWNER_ID, 0, | |
471 | TX_DESCQ_LABEL, tx_queue->queue, | |
472 | TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER, | |
473 | TX_DESCQ_TYPE, 0, | |
474 | TX_NON_IP_DROP_DIS_B0, 1); | |
475 | ||
55668611 | 476 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
60ac1065 BH |
477 | int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM; |
478 | EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum); | |
479 | EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum); | |
8ceee660 BH |
480 | } |
481 | ||
482 | falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, | |
483 | tx_queue->queue); | |
484 | ||
55668611 | 485 | if (falcon_rev(efx) < FALCON_REV_B0) { |
8ceee660 BH |
486 | efx_oword_t reg; |
487 | ||
60ac1065 BH |
488 | /* Only 128 bits in this register */ |
489 | BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); | |
8ceee660 BH |
490 | |
491 | falcon_read(efx, ®, TX_CHKSM_CFG_REG_KER_A1); | |
60ac1065 | 492 | if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) |
8ceee660 BH |
493 | clear_bit_le(tx_queue->queue, (void *)®); |
494 | else | |
495 | set_bit_le(tx_queue->queue, (void *)®); | |
496 | falcon_write(efx, ®, TX_CHKSM_CFG_REG_KER_A1); | |
497 | } | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
502 | static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue) | |
503 | { | |
504 | struct efx_nic *efx = tx_queue->efx; | |
505 | struct efx_channel *channel = &efx->channel[0]; | |
506 | efx_oword_t tx_flush_descq; | |
507 | unsigned int read_ptr, i; | |
508 | ||
509 | /* Post a flush command */ | |
510 | EFX_POPULATE_OWORD_2(tx_flush_descq, | |
511 | TX_FLUSH_DESCQ_CMD, 1, | |
512 | TX_FLUSH_DESCQ, tx_queue->queue); | |
513 | falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER); | |
514 | msleep(FALCON_FLUSH_TIMEOUT); | |
515 | ||
516 | if (EFX_WORKAROUND_7803(efx)) | |
517 | return 0; | |
518 | ||
519 | /* Look for a flush completed event */ | |
520 | read_ptr = channel->eventq_read_ptr; | |
521 | for (i = 0; i < FALCON_EVQ_SIZE; ++i) { | |
522 | efx_qword_t *event = falcon_event(channel, read_ptr); | |
523 | int ev_code, ev_sub_code, ev_queue; | |
524 | if (!falcon_event_present(event)) | |
525 | break; | |
526 | ||
527 | ev_code = EFX_QWORD_FIELD(*event, EV_CODE); | |
528 | ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE); | |
529 | ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID); | |
530 | if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) && | |
531 | (ev_queue == tx_queue->queue)) { | |
532 | EFX_LOG(efx, "tx queue %d flush command succesful\n", | |
533 | tx_queue->queue); | |
534 | return 0; | |
535 | } | |
536 | ||
537 | read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK; | |
538 | } | |
539 | ||
540 | if (EFX_WORKAROUND_11557(efx)) { | |
541 | efx_oword_t reg; | |
dc8cfa55 | 542 | bool enabled; |
8ceee660 BH |
543 | |
544 | falcon_read_table(efx, ®, efx->type->txd_ptr_tbl_base, | |
545 | tx_queue->queue); | |
546 | enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN); | |
547 | if (!enabled) { | |
548 | EFX_LOG(efx, "tx queue %d disabled without a " | |
549 | "flush event seen\n", tx_queue->queue); | |
550 | return 0; | |
551 | } | |
552 | } | |
553 | ||
554 | EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue); | |
555 | return -ETIMEDOUT; | |
556 | } | |
557 | ||
558 | void falcon_fini_tx(struct efx_tx_queue *tx_queue) | |
559 | { | |
560 | struct efx_nic *efx = tx_queue->efx; | |
561 | efx_oword_t tx_desc_ptr; | |
562 | ||
563 | /* Stop the hardware using the queue */ | |
564 | if (falcon_flush_tx_queue(tx_queue)) | |
565 | EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue); | |
566 | ||
567 | /* Remove TX descriptor ring from card */ | |
568 | EFX_ZERO_OWORD(tx_desc_ptr); | |
569 | falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, | |
570 | tx_queue->queue); | |
571 | ||
572 | /* Unpin TX descriptor ring */ | |
573 | falcon_fini_special_buffer(efx, &tx_queue->txd); | |
574 | } | |
575 | ||
576 | /* Free buffers backing TX queue */ | |
577 | void falcon_remove_tx(struct efx_tx_queue *tx_queue) | |
578 | { | |
579 | falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd); | |
580 | } | |
581 | ||
582 | /************************************************************************** | |
583 | * | |
584 | * Falcon RX path | |
585 | * | |
586 | **************************************************************************/ | |
587 | ||
588 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ | |
589 | static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue, | |
590 | unsigned int index) | |
591 | { | |
592 | return (((efx_qword_t *) (rx_queue->rxd.addr)) + index); | |
593 | } | |
594 | ||
595 | /* This creates an entry in the RX descriptor queue */ | |
596 | static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue, | |
597 | unsigned index) | |
598 | { | |
599 | struct efx_rx_buffer *rx_buf; | |
600 | efx_qword_t *rxd; | |
601 | ||
602 | rxd = falcon_rx_desc(rx_queue, index); | |
603 | rx_buf = efx_rx_buffer(rx_queue, index); | |
604 | EFX_POPULATE_QWORD_3(*rxd, | |
605 | RX_KER_BUF_SIZE, | |
606 | rx_buf->len - | |
607 | rx_queue->efx->type->rx_buffer_padding, | |
608 | RX_KER_BUF_REGION, 0, | |
609 | RX_KER_BUF_ADR, rx_buf->dma_addr); | |
610 | } | |
611 | ||
612 | /* This writes to the RX_DESC_WPTR register for the specified receive | |
613 | * descriptor ring. | |
614 | */ | |
615 | void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue) | |
616 | { | |
617 | efx_dword_t reg; | |
618 | unsigned write_ptr; | |
619 | ||
620 | while (rx_queue->notified_count != rx_queue->added_count) { | |
621 | falcon_build_rx_desc(rx_queue, | |
622 | rx_queue->notified_count & | |
623 | FALCON_RXD_RING_MASK); | |
624 | ++rx_queue->notified_count; | |
625 | } | |
626 | ||
627 | wmb(); | |
628 | write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK; | |
629 | EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr); | |
630 | falcon_writel_page(rx_queue->efx, ®, | |
631 | RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue); | |
632 | } | |
633 | ||
634 | int falcon_probe_rx(struct efx_rx_queue *rx_queue) | |
635 | { | |
636 | struct efx_nic *efx = rx_queue->efx; | |
637 | return falcon_alloc_special_buffer(efx, &rx_queue->rxd, | |
638 | FALCON_RXD_RING_SIZE * | |
639 | sizeof(efx_qword_t)); | |
640 | } | |
641 | ||
642 | int falcon_init_rx(struct efx_rx_queue *rx_queue) | |
643 | { | |
644 | efx_oword_t rx_desc_ptr; | |
645 | struct efx_nic *efx = rx_queue->efx; | |
646 | int rc; | |
dc8cfa55 BH |
647 | bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0; |
648 | bool iscsi_digest_en = is_b0; | |
8ceee660 BH |
649 | |
650 | EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n", | |
651 | rx_queue->queue, rx_queue->rxd.index, | |
652 | rx_queue->rxd.index + rx_queue->rxd.entries - 1); | |
653 | ||
654 | /* Pin RX descriptor ring */ | |
655 | rc = falcon_init_special_buffer(efx, &rx_queue->rxd); | |
656 | if (rc) | |
657 | return rc; | |
658 | ||
659 | /* Push RX descriptor ring to card */ | |
660 | EFX_POPULATE_OWORD_10(rx_desc_ptr, | |
661 | RX_ISCSI_DDIG_EN, iscsi_digest_en, | |
662 | RX_ISCSI_HDIG_EN, iscsi_digest_en, | |
663 | RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, | |
664 | RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum, | |
665 | RX_DESCQ_OWNER_ID, 0, | |
666 | RX_DESCQ_LABEL, rx_queue->queue, | |
667 | RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER, | |
668 | RX_DESCQ_TYPE, 0 /* kernel queue */ , | |
669 | /* For >=B0 this is scatter so disable */ | |
670 | RX_DESCQ_JUMBO, !is_b0, | |
671 | RX_DESCQ_EN, 1); | |
672 | falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, | |
673 | rx_queue->queue); | |
674 | return 0; | |
675 | } | |
676 | ||
677 | static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue) | |
678 | { | |
679 | struct efx_nic *efx = rx_queue->efx; | |
680 | struct efx_channel *channel = &efx->channel[0]; | |
681 | unsigned int read_ptr, i; | |
682 | efx_oword_t rx_flush_descq; | |
683 | ||
684 | /* Post a flush command */ | |
685 | EFX_POPULATE_OWORD_2(rx_flush_descq, | |
686 | RX_FLUSH_DESCQ_CMD, 1, | |
687 | RX_FLUSH_DESCQ, rx_queue->queue); | |
688 | falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER); | |
689 | msleep(FALCON_FLUSH_TIMEOUT); | |
690 | ||
691 | if (EFX_WORKAROUND_7803(efx)) | |
692 | return 0; | |
693 | ||
694 | /* Look for a flush completed event */ | |
695 | read_ptr = channel->eventq_read_ptr; | |
696 | for (i = 0; i < FALCON_EVQ_SIZE; ++i) { | |
697 | efx_qword_t *event = falcon_event(channel, read_ptr); | |
dc8cfa55 BH |
698 | int ev_code, ev_sub_code, ev_queue; |
699 | bool ev_failed; | |
8ceee660 BH |
700 | if (!falcon_event_present(event)) |
701 | break; | |
702 | ||
703 | ev_code = EFX_QWORD_FIELD(*event, EV_CODE); | |
704 | ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE); | |
705 | ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID); | |
706 | ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL); | |
707 | ||
708 | if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) && | |
709 | (ev_queue == rx_queue->queue)) { | |
710 | if (ev_failed) { | |
711 | EFX_INFO(efx, "rx queue %d flush command " | |
712 | "failed\n", rx_queue->queue); | |
713 | return -EAGAIN; | |
714 | } else { | |
715 | EFX_LOG(efx, "rx queue %d flush command " | |
716 | "succesful\n", rx_queue->queue); | |
717 | return 0; | |
718 | } | |
719 | } | |
720 | ||
721 | read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK; | |
722 | } | |
723 | ||
724 | if (EFX_WORKAROUND_11557(efx)) { | |
725 | efx_oword_t reg; | |
dc8cfa55 | 726 | bool enabled; |
8ceee660 BH |
727 | |
728 | falcon_read_table(efx, ®, efx->type->rxd_ptr_tbl_base, | |
729 | rx_queue->queue); | |
730 | enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN); | |
731 | if (!enabled) { | |
732 | EFX_LOG(efx, "rx queue %d disabled without a " | |
733 | "flush event seen\n", rx_queue->queue); | |
734 | return 0; | |
735 | } | |
736 | } | |
737 | ||
738 | EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue); | |
739 | return -ETIMEDOUT; | |
740 | } | |
741 | ||
742 | void falcon_fini_rx(struct efx_rx_queue *rx_queue) | |
743 | { | |
744 | efx_oword_t rx_desc_ptr; | |
745 | struct efx_nic *efx = rx_queue->efx; | |
746 | int i, rc; | |
747 | ||
748 | /* Try and flush the rx queue. This may need to be repeated */ | |
749 | for (i = 0; i < 5; i++) { | |
750 | rc = falcon_flush_rx_queue(rx_queue); | |
751 | if (rc == -EAGAIN) | |
752 | continue; | |
753 | break; | |
754 | } | |
23bdfdd3 | 755 | if (rc) { |
8ceee660 | 756 | EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue); |
23bdfdd3 SH |
757 | efx_schedule_reset(efx, RESET_TYPE_INVISIBLE); |
758 | } | |
8ceee660 BH |
759 | |
760 | /* Remove RX descriptor ring from card */ | |
761 | EFX_ZERO_OWORD(rx_desc_ptr); | |
762 | falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, | |
763 | rx_queue->queue); | |
764 | ||
765 | /* Unpin RX descriptor ring */ | |
766 | falcon_fini_special_buffer(efx, &rx_queue->rxd); | |
767 | } | |
768 | ||
769 | /* Free buffers backing RX queue */ | |
770 | void falcon_remove_rx(struct efx_rx_queue *rx_queue) | |
771 | { | |
772 | falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd); | |
773 | } | |
774 | ||
775 | /************************************************************************** | |
776 | * | |
777 | * Falcon event queue processing | |
778 | * Event queues are processed by per-channel tasklets. | |
779 | * | |
780 | **************************************************************************/ | |
781 | ||
782 | /* Update a channel's event queue's read pointer (RPTR) register | |
783 | * | |
784 | * This writes the EVQ_RPTR_REG register for the specified channel's | |
785 | * event queue. | |
786 | * | |
787 | * Note that EVQ_RPTR_REG contains the index of the "last read" event, | |
788 | * whereas channel->eventq_read_ptr contains the index of the "next to | |
789 | * read" event. | |
790 | */ | |
791 | void falcon_eventq_read_ack(struct efx_channel *channel) | |
792 | { | |
793 | efx_dword_t reg; | |
794 | struct efx_nic *efx = channel->efx; | |
795 | ||
796 | EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr); | |
797 | falcon_writel_table(efx, ®, efx->type->evq_rptr_tbl_base, | |
798 | channel->evqnum); | |
799 | } | |
800 | ||
801 | /* Use HW to insert a SW defined event */ | |
802 | void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event) | |
803 | { | |
804 | efx_oword_t drv_ev_reg; | |
805 | ||
806 | EFX_POPULATE_OWORD_2(drv_ev_reg, | |
807 | DRV_EV_QID, channel->evqnum, | |
808 | DRV_EV_DATA, | |
809 | EFX_QWORD_FIELD64(*event, WHOLE_EVENT)); | |
810 | falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER); | |
811 | } | |
812 | ||
813 | /* Handle a transmit completion event | |
814 | * | |
815 | * Falcon batches TX completion events; the message we receive is of | |
816 | * the form "complete all TX events up to this index". | |
817 | */ | |
818 | static inline void falcon_handle_tx_event(struct efx_channel *channel, | |
819 | efx_qword_t *event) | |
820 | { | |
821 | unsigned int tx_ev_desc_ptr; | |
822 | unsigned int tx_ev_q_label; | |
823 | struct efx_tx_queue *tx_queue; | |
824 | struct efx_nic *efx = channel->efx; | |
825 | ||
826 | if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) { | |
827 | /* Transmit completion */ | |
828 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR); | |
829 | tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL); | |
830 | tx_queue = &efx->tx_queue[tx_ev_q_label]; | |
831 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); | |
832 | } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) { | |
833 | /* Rewrite the FIFO write pointer */ | |
834 | tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL); | |
835 | tx_queue = &efx->tx_queue[tx_ev_q_label]; | |
836 | ||
55668611 | 837 | if (efx_dev_registered(efx)) |
8ceee660 BH |
838 | netif_tx_lock(efx->net_dev); |
839 | falcon_notify_tx_desc(tx_queue); | |
55668611 | 840 | if (efx_dev_registered(efx)) |
8ceee660 BH |
841 | netif_tx_unlock(efx->net_dev); |
842 | } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) && | |
843 | EFX_WORKAROUND_10727(efx)) { | |
844 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
845 | } else { | |
846 | EFX_ERR(efx, "channel %d unexpected TX event " | |
847 | EFX_QWORD_FMT"\n", channel->channel, | |
848 | EFX_QWORD_VAL(*event)); | |
849 | } | |
850 | } | |
851 | ||
8ceee660 BH |
852 | /* Detect errors included in the rx_evt_pkt_ok bit. */ |
853 | static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue, | |
854 | const efx_qword_t *event, | |
dc8cfa55 BH |
855 | bool *rx_ev_pkt_ok, |
856 | bool *discard) | |
8ceee660 BH |
857 | { |
858 | struct efx_nic *efx = rx_queue->efx; | |
dc8cfa55 BH |
859 | bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; |
860 | bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; | |
861 | bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; | |
862 | bool rx_ev_other_err, rx_ev_pause_frm; | |
863 | bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt; | |
864 | unsigned rx_ev_pkt_type; | |
8ceee660 BH |
865 | |
866 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE); | |
867 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT); | |
868 | rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC); | |
869 | rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE); | |
870 | rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, | |
871 | RX_EV_BUF_OWNER_ID_ERR); | |
872 | rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR); | |
873 | rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, | |
874 | RX_EV_IP_HDR_CHKSUM_ERR); | |
875 | rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, | |
876 | RX_EV_TCP_UDP_CHKSUM_ERR); | |
877 | rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR); | |
878 | rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC); | |
55668611 | 879 | rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ? |
8ceee660 BH |
880 | 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB)); |
881 | rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR); | |
882 | ||
883 | /* Every error apart from tobe_disc and pause_frm */ | |
884 | rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | | |
885 | rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | | |
886 | rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); | |
887 | ||
8ceee660 BH |
888 | /* Count errors that are not in MAC stats. */ |
889 | if (rx_ev_frm_trunc) | |
890 | ++rx_queue->channel->n_rx_frm_trunc; | |
891 | else if (rx_ev_tobe_disc) | |
892 | ++rx_queue->channel->n_rx_tobe_disc; | |
893 | else if (rx_ev_ip_hdr_chksum_err) | |
894 | ++rx_queue->channel->n_rx_ip_hdr_chksum_err; | |
895 | else if (rx_ev_tcp_udp_chksum_err) | |
896 | ++rx_queue->channel->n_rx_tcp_udp_chksum_err; | |
897 | if (rx_ev_ip_frag_err) | |
898 | ++rx_queue->channel->n_rx_ip_frag_err; | |
899 | ||
900 | /* The frame must be discarded if any of these are true. */ | |
901 | *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | | |
902 | rx_ev_tobe_disc | rx_ev_pause_frm); | |
903 | ||
904 | /* TOBE_DISC is expected on unicast mismatches; don't print out an | |
905 | * error message. FRM_TRUNC indicates RXDP dropped the packet due | |
906 | * to a FIFO overflow. | |
907 | */ | |
908 | #ifdef EFX_ENABLE_DEBUG | |
909 | if (rx_ev_other_err) { | |
910 | EFX_INFO_RL(efx, " RX queue %d unexpected RX event " | |
5b39fe30 | 911 | EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", |
8ceee660 BH |
912 | rx_queue->queue, EFX_QWORD_VAL(*event), |
913 | rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", | |
914 | rx_ev_ip_hdr_chksum_err ? | |
915 | " [IP_HDR_CHKSUM_ERR]" : "", | |
916 | rx_ev_tcp_udp_chksum_err ? | |
917 | " [TCP_UDP_CHKSUM_ERR]" : "", | |
918 | rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", | |
919 | rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", | |
920 | rx_ev_drib_nib ? " [DRIB_NIB]" : "", | |
921 | rx_ev_tobe_disc ? " [TOBE_DISC]" : "", | |
5b39fe30 | 922 | rx_ev_pause_frm ? " [PAUSE]" : ""); |
8ceee660 BH |
923 | } |
924 | #endif | |
925 | ||
926 | if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) && | |
927 | efx->phy_type == PHY_TYPE_10XPRESS)) | |
928 | tenxpress_crc_err(efx); | |
929 | } | |
930 | ||
931 | /* Handle receive events that are not in-order. */ | |
932 | static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue, | |
933 | unsigned index) | |
934 | { | |
935 | struct efx_nic *efx = rx_queue->efx; | |
936 | unsigned expected, dropped; | |
937 | ||
938 | expected = rx_queue->removed_count & FALCON_RXD_RING_MASK; | |
939 | dropped = ((index + FALCON_RXD_RING_SIZE - expected) & | |
940 | FALCON_RXD_RING_MASK); | |
941 | EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n", | |
942 | dropped, index, expected); | |
943 | ||
944 | efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? | |
945 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
946 | } | |
947 | ||
948 | /* Handle a packet received event | |
949 | * | |
950 | * Falcon silicon gives a "discard" flag if it's a unicast packet with the | |
951 | * wrong destination address | |
952 | * Also "is multicast" and "matches multicast filter" flags can be used to | |
953 | * discard non-matching multicast packets. | |
954 | */ | |
955 | static inline int falcon_handle_rx_event(struct efx_channel *channel, | |
956 | const efx_qword_t *event) | |
957 | { | |
958 | unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt; | |
dc8cfa55 | 959 | unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; |
8ceee660 | 960 | unsigned expected_ptr; |
dc8cfa55 | 961 | bool rx_ev_pkt_ok, discard = false, checksummed; |
8ceee660 BH |
962 | struct efx_rx_queue *rx_queue; |
963 | struct efx_nic *efx = channel->efx; | |
964 | ||
965 | /* Basic packet information */ | |
966 | rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT); | |
967 | rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK); | |
968 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE); | |
969 | WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT)); | |
970 | WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1); | |
971 | ||
972 | rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL); | |
973 | rx_queue = &efx->rx_queue[rx_ev_q_label]; | |
974 | ||
975 | rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR); | |
976 | expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK; | |
977 | if (unlikely(rx_ev_desc_ptr != expected_ptr)) { | |
978 | falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); | |
979 | return rx_ev_q_label; | |
980 | } | |
981 | ||
982 | if (likely(rx_ev_pkt_ok)) { | |
983 | /* If packet is marked as OK and packet type is TCP/IPv4 or | |
984 | * UDP/IPv4, then we can rely on the hardware checksum. | |
985 | */ | |
986 | checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type); | |
987 | } else { | |
988 | falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, | |
5b39fe30 | 989 | &discard); |
dc8cfa55 | 990 | checksummed = false; |
8ceee660 BH |
991 | } |
992 | ||
993 | /* Detect multicast packets that didn't match the filter */ | |
994 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT); | |
995 | if (rx_ev_mcast_pkt) { | |
996 | unsigned int rx_ev_mcast_hash_match = | |
997 | EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH); | |
998 | ||
999 | if (unlikely(!rx_ev_mcast_hash_match)) | |
dc8cfa55 | 1000 | discard = true; |
8ceee660 BH |
1001 | } |
1002 | ||
1003 | /* Handle received packet */ | |
1004 | efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, | |
1005 | checksummed, discard); | |
1006 | ||
1007 | return rx_ev_q_label; | |
1008 | } | |
1009 | ||
1010 | /* Global events are basically PHY events */ | |
1011 | static void falcon_handle_global_event(struct efx_channel *channel, | |
1012 | efx_qword_t *event) | |
1013 | { | |
1014 | struct efx_nic *efx = channel->efx; | |
dc8cfa55 | 1015 | bool is_phy_event = false, handled = false; |
8ceee660 BH |
1016 | |
1017 | /* Check for interrupt on either port. Some boards have a | |
1018 | * single PHY wired to the interrupt line for port 1. */ | |
1019 | if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) || | |
1020 | EFX_QWORD_FIELD(*event, G_PHY1_INTR) || | |
1021 | EFX_QWORD_FIELD(*event, XG_PHY_INTR)) | |
dc8cfa55 | 1022 | is_phy_event = true; |
8ceee660 | 1023 | |
55668611 | 1024 | if ((falcon_rev(efx) >= FALCON_REV_B0) && |
8ceee660 | 1025 | EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0)) |
dc8cfa55 | 1026 | is_phy_event = true; |
8ceee660 BH |
1027 | |
1028 | if (is_phy_event) { | |
1029 | efx->phy_op->clear_interrupt(efx); | |
1030 | queue_work(efx->workqueue, &efx->reconfigure_work); | |
dc8cfa55 | 1031 | handled = true; |
8ceee660 BH |
1032 | } |
1033 | ||
1034 | if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) { | |
1035 | EFX_ERR(efx, "channel %d seen global RX_RESET " | |
1036 | "event. Resetting.\n", channel->channel); | |
1037 | ||
1038 | atomic_inc(&efx->rx_reset); | |
1039 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? | |
1040 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
dc8cfa55 | 1041 | handled = true; |
8ceee660 BH |
1042 | } |
1043 | ||
1044 | if (!handled) | |
1045 | EFX_ERR(efx, "channel %d unknown global event " | |
1046 | EFX_QWORD_FMT "\n", channel->channel, | |
1047 | EFX_QWORD_VAL(*event)); | |
1048 | } | |
1049 | ||
1050 | static void falcon_handle_driver_event(struct efx_channel *channel, | |
1051 | efx_qword_t *event) | |
1052 | { | |
1053 | struct efx_nic *efx = channel->efx; | |
1054 | unsigned int ev_sub_code; | |
1055 | unsigned int ev_sub_data; | |
1056 | ||
1057 | ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE); | |
1058 | ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA); | |
1059 | ||
1060 | switch (ev_sub_code) { | |
1061 | case TX_DESCQ_FLS_DONE_EV_DECODE: | |
1062 | EFX_TRACE(efx, "channel %d TXQ %d flushed\n", | |
1063 | channel->channel, ev_sub_data); | |
1064 | break; | |
1065 | case RX_DESCQ_FLS_DONE_EV_DECODE: | |
1066 | EFX_TRACE(efx, "channel %d RXQ %d flushed\n", | |
1067 | channel->channel, ev_sub_data); | |
1068 | break; | |
1069 | case EVQ_INIT_DONE_EV_DECODE: | |
1070 | EFX_LOG(efx, "channel %d EVQ %d initialised\n", | |
1071 | channel->channel, ev_sub_data); | |
1072 | break; | |
1073 | case SRM_UPD_DONE_EV_DECODE: | |
1074 | EFX_TRACE(efx, "channel %d SRAM update done\n", | |
1075 | channel->channel); | |
1076 | break; | |
1077 | case WAKE_UP_EV_DECODE: | |
1078 | EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n", | |
1079 | channel->channel, ev_sub_data); | |
1080 | break; | |
1081 | case TIMER_EV_DECODE: | |
1082 | EFX_TRACE(efx, "channel %d RX queue %d timer expired\n", | |
1083 | channel->channel, ev_sub_data); | |
1084 | break; | |
1085 | case RX_RECOVERY_EV_DECODE: | |
1086 | EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. " | |
1087 | "Resetting.\n", channel->channel); | |
05e3ec04 | 1088 | atomic_inc(&efx->rx_reset); |
8ceee660 BH |
1089 | efx_schedule_reset(efx, |
1090 | EFX_WORKAROUND_6555(efx) ? | |
1091 | RESET_TYPE_RX_RECOVERY : | |
1092 | RESET_TYPE_DISABLE); | |
1093 | break; | |
1094 | case RX_DSC_ERROR_EV_DECODE: | |
1095 | EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error." | |
1096 | " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
1097 | efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); | |
1098 | break; | |
1099 | case TX_DSC_ERROR_EV_DECODE: | |
1100 | EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error." | |
1101 | " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
1102 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
1103 | break; | |
1104 | default: | |
1105 | EFX_TRACE(efx, "channel %d unknown driver event code %d " | |
1106 | "data %04x\n", channel->channel, ev_sub_code, | |
1107 | ev_sub_data); | |
1108 | break; | |
1109 | } | |
1110 | } | |
1111 | ||
1112 | int falcon_process_eventq(struct efx_channel *channel, int *rx_quota) | |
1113 | { | |
1114 | unsigned int read_ptr; | |
1115 | efx_qword_t event, *p_event; | |
1116 | int ev_code; | |
1117 | int rxq; | |
1118 | int rxdmaqs = 0; | |
1119 | ||
1120 | read_ptr = channel->eventq_read_ptr; | |
1121 | ||
1122 | do { | |
1123 | p_event = falcon_event(channel, read_ptr); | |
1124 | event = *p_event; | |
1125 | ||
1126 | if (!falcon_event_present(&event)) | |
1127 | /* End of events */ | |
1128 | break; | |
1129 | ||
1130 | EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n", | |
1131 | channel->channel, EFX_QWORD_VAL(event)); | |
1132 | ||
1133 | /* Clear this event by marking it all ones */ | |
1134 | EFX_SET_QWORD(*p_event); | |
1135 | ||
1136 | ev_code = EFX_QWORD_FIELD(event, EV_CODE); | |
1137 | ||
1138 | switch (ev_code) { | |
1139 | case RX_IP_EV_DECODE: | |
1140 | rxq = falcon_handle_rx_event(channel, &event); | |
1141 | rxdmaqs |= (1 << rxq); | |
1142 | (*rx_quota)--; | |
1143 | break; | |
1144 | case TX_IP_EV_DECODE: | |
1145 | falcon_handle_tx_event(channel, &event); | |
1146 | break; | |
1147 | case DRV_GEN_EV_DECODE: | |
1148 | channel->eventq_magic | |
1149 | = EFX_QWORD_FIELD(event, EVQ_MAGIC); | |
1150 | EFX_LOG(channel->efx, "channel %d received generated " | |
1151 | "event "EFX_QWORD_FMT"\n", channel->channel, | |
1152 | EFX_QWORD_VAL(event)); | |
1153 | break; | |
1154 | case GLOBAL_EV_DECODE: | |
1155 | falcon_handle_global_event(channel, &event); | |
1156 | break; | |
1157 | case DRIVER_EV_DECODE: | |
1158 | falcon_handle_driver_event(channel, &event); | |
1159 | break; | |
1160 | default: | |
1161 | EFX_ERR(channel->efx, "channel %d unknown event type %d" | |
1162 | " (data " EFX_QWORD_FMT ")\n", channel->channel, | |
1163 | ev_code, EFX_QWORD_VAL(event)); | |
1164 | } | |
1165 | ||
1166 | /* Increment read pointer */ | |
1167 | read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK; | |
1168 | ||
1169 | } while (*rx_quota); | |
1170 | ||
1171 | channel->eventq_read_ptr = read_ptr; | |
1172 | return rxdmaqs; | |
1173 | } | |
1174 | ||
1175 | void falcon_set_int_moderation(struct efx_channel *channel) | |
1176 | { | |
1177 | efx_dword_t timer_cmd; | |
1178 | struct efx_nic *efx = channel->efx; | |
1179 | ||
1180 | /* Set timer register */ | |
1181 | if (channel->irq_moderation) { | |
1182 | /* Round to resolution supported by hardware. The value we | |
1183 | * program is based at 0. So actual interrupt moderation | |
1184 | * achieved is ((x + 1) * res). | |
1185 | */ | |
1186 | unsigned int res = 5; | |
1187 | channel->irq_moderation -= (channel->irq_moderation % res); | |
1188 | if (channel->irq_moderation < res) | |
1189 | channel->irq_moderation = res; | |
1190 | EFX_POPULATE_DWORD_2(timer_cmd, | |
1191 | TIMER_MODE, TIMER_MODE_INT_HLDOFF, | |
1192 | TIMER_VAL, | |
1193 | (channel->irq_moderation / res) - 1); | |
1194 | } else { | |
1195 | EFX_POPULATE_DWORD_2(timer_cmd, | |
1196 | TIMER_MODE, TIMER_MODE_DIS, | |
1197 | TIMER_VAL, 0); | |
1198 | } | |
1199 | falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER, | |
1200 | channel->evqnum); | |
1201 | ||
1202 | } | |
1203 | ||
1204 | /* Allocate buffer table entries for event queue */ | |
1205 | int falcon_probe_eventq(struct efx_channel *channel) | |
1206 | { | |
1207 | struct efx_nic *efx = channel->efx; | |
1208 | unsigned int evq_size; | |
1209 | ||
1210 | evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t); | |
1211 | return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size); | |
1212 | } | |
1213 | ||
1214 | int falcon_init_eventq(struct efx_channel *channel) | |
1215 | { | |
1216 | efx_oword_t evq_ptr; | |
1217 | struct efx_nic *efx = channel->efx; | |
1218 | int rc; | |
1219 | ||
1220 | EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n", | |
1221 | channel->channel, channel->eventq.index, | |
1222 | channel->eventq.index + channel->eventq.entries - 1); | |
1223 | ||
1224 | /* Pin event queue buffer */ | |
1225 | rc = falcon_init_special_buffer(efx, &channel->eventq); | |
1226 | if (rc) | |
1227 | return rc; | |
1228 | ||
1229 | /* Fill event queue with all ones (i.e. empty events) */ | |
1230 | memset(channel->eventq.addr, 0xff, channel->eventq.len); | |
1231 | ||
1232 | /* Push event queue to card */ | |
1233 | EFX_POPULATE_OWORD_3(evq_ptr, | |
1234 | EVQ_EN, 1, | |
1235 | EVQ_SIZE, FALCON_EVQ_ORDER, | |
1236 | EVQ_BUF_BASE_ID, channel->eventq.index); | |
1237 | falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base, | |
1238 | channel->evqnum); | |
1239 | ||
1240 | falcon_set_int_moderation(channel); | |
1241 | ||
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | void falcon_fini_eventq(struct efx_channel *channel) | |
1246 | { | |
1247 | efx_oword_t eventq_ptr; | |
1248 | struct efx_nic *efx = channel->efx; | |
1249 | ||
1250 | /* Remove event queue from card */ | |
1251 | EFX_ZERO_OWORD(eventq_ptr); | |
1252 | falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base, | |
1253 | channel->evqnum); | |
1254 | ||
1255 | /* Unpin event queue */ | |
1256 | falcon_fini_special_buffer(efx, &channel->eventq); | |
1257 | } | |
1258 | ||
1259 | /* Free buffers backing event queue */ | |
1260 | void falcon_remove_eventq(struct efx_channel *channel) | |
1261 | { | |
1262 | falcon_free_special_buffer(channel->efx, &channel->eventq); | |
1263 | } | |
1264 | ||
1265 | ||
1266 | /* Generates a test event on the event queue. A subsequent call to | |
1267 | * process_eventq() should pick up the event and place the value of | |
1268 | * "magic" into channel->eventq_magic; | |
1269 | */ | |
1270 | void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic) | |
1271 | { | |
1272 | efx_qword_t test_event; | |
1273 | ||
1274 | EFX_POPULATE_QWORD_2(test_event, | |
1275 | EV_CODE, DRV_GEN_EV_DECODE, | |
1276 | EVQ_MAGIC, magic); | |
1277 | falcon_generate_event(channel, &test_event); | |
1278 | } | |
1279 | ||
1280 | ||
1281 | /************************************************************************** | |
1282 | * | |
1283 | * Falcon hardware interrupts | |
1284 | * The hardware interrupt handler does very little work; all the event | |
1285 | * queue processing is carried out by per-channel tasklets. | |
1286 | * | |
1287 | **************************************************************************/ | |
1288 | ||
1289 | /* Enable/disable/generate Falcon interrupts */ | |
1290 | static inline void falcon_interrupts(struct efx_nic *efx, int enabled, | |
1291 | int force) | |
1292 | { | |
1293 | efx_oword_t int_en_reg_ker; | |
1294 | ||
1295 | EFX_POPULATE_OWORD_2(int_en_reg_ker, | |
1296 | KER_INT_KER, force, | |
1297 | DRV_INT_EN_KER, enabled); | |
1298 | falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER); | |
1299 | } | |
1300 | ||
1301 | void falcon_enable_interrupts(struct efx_nic *efx) | |
1302 | { | |
1303 | efx_oword_t int_adr_reg_ker; | |
1304 | struct efx_channel *channel; | |
1305 | ||
1306 | EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); | |
1307 | wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ | |
1308 | ||
1309 | /* Program address */ | |
1310 | EFX_POPULATE_OWORD_2(int_adr_reg_ker, | |
1311 | NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx), | |
1312 | INT_ADR_KER, efx->irq_status.dma_addr); | |
1313 | falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER); | |
1314 | ||
1315 | /* Enable interrupts */ | |
1316 | falcon_interrupts(efx, 1, 0); | |
1317 | ||
1318 | /* Force processing of all the channels to get the EVQ RPTRs up to | |
1319 | date */ | |
1320 | efx_for_each_channel_with_interrupt(channel, efx) | |
1321 | efx_schedule_channel(channel); | |
1322 | } | |
1323 | ||
1324 | void falcon_disable_interrupts(struct efx_nic *efx) | |
1325 | { | |
1326 | /* Disable interrupts */ | |
1327 | falcon_interrupts(efx, 0, 0); | |
1328 | } | |
1329 | ||
1330 | /* Generate a Falcon test interrupt | |
1331 | * Interrupt must already have been enabled, otherwise nasty things | |
1332 | * may happen. | |
1333 | */ | |
1334 | void falcon_generate_interrupt(struct efx_nic *efx) | |
1335 | { | |
1336 | falcon_interrupts(efx, 1, 1); | |
1337 | } | |
1338 | ||
1339 | /* Acknowledge a legacy interrupt from Falcon | |
1340 | * | |
1341 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
1342 | * | |
1343 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
1344 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
1345 | * (then read to ensure the BIU collector is flushed) | |
1346 | * | |
1347 | * NB most hardware supports MSI interrupts | |
1348 | */ | |
1349 | static inline void falcon_irq_ack_a1(struct efx_nic *efx) | |
1350 | { | |
1351 | efx_dword_t reg; | |
1352 | ||
1353 | EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e); | |
1354 | falcon_writel(efx, ®, INT_ACK_REG_KER_A1); | |
1355 | falcon_readl(efx, ®, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1); | |
1356 | } | |
1357 | ||
1358 | /* Process a fatal interrupt | |
1359 | * Disable bus mastering ASAP and schedule a reset | |
1360 | */ | |
1361 | static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx) | |
1362 | { | |
1363 | struct falcon_nic_data *nic_data = efx->nic_data; | |
d3208b5e | 1364 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1365 | efx_oword_t fatal_intr; |
1366 | int error, mem_perr; | |
1367 | static int n_int_errors; | |
1368 | ||
1369 | falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER); | |
1370 | error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR); | |
1371 | ||
1372 | EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status " | |
1373 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), | |
1374 | EFX_OWORD_VAL(fatal_intr), | |
1375 | error ? "disabling bus mastering" : "no recognised error"); | |
1376 | if (error == 0) | |
1377 | goto out; | |
1378 | ||
1379 | /* If this is a memory parity error dump which blocks are offending */ | |
1380 | mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER); | |
1381 | if (mem_perr) { | |
1382 | efx_oword_t reg; | |
1383 | falcon_read(efx, ®, MEM_STAT_REG_KER); | |
1384 | EFX_ERR(efx, "SYSTEM ERROR: memory parity error " | |
1385 | EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg)); | |
1386 | } | |
1387 | ||
1388 | /* Disable DMA bus mastering on both devices */ | |
1389 | pci_disable_device(efx->pci_dev); | |
1390 | if (FALCON_IS_DUAL_FUNC(efx)) | |
1391 | pci_disable_device(nic_data->pci_dev2); | |
1392 | ||
1393 | if (++n_int_errors < FALCON_MAX_INT_ERRORS) { | |
1394 | EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n"); | |
1395 | efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); | |
1396 | } else { | |
1397 | EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen." | |
1398 | "NIC will be disabled\n"); | |
1399 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1400 | } | |
1401 | out: | |
1402 | return IRQ_HANDLED; | |
1403 | } | |
1404 | ||
1405 | /* Handle a legacy interrupt from Falcon | |
1406 | * Acknowledges the interrupt and schedule event queue processing. | |
1407 | */ | |
1408 | static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id) | |
1409 | { | |
d3208b5e BH |
1410 | struct efx_nic *efx = dev_id; |
1411 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
1412 | struct efx_channel *channel; |
1413 | efx_dword_t reg; | |
1414 | u32 queues; | |
1415 | int syserr; | |
1416 | ||
1417 | /* Read the ISR which also ACKs the interrupts */ | |
1418 | falcon_readl(efx, ®, INT_ISR0_B0); | |
1419 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); | |
1420 | ||
1421 | /* Check to see if we have a serious error condition */ | |
1422 | syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); | |
1423 | if (unlikely(syserr)) | |
1424 | return falcon_fatal_interrupt(efx); | |
1425 | ||
1426 | if (queues == 0) | |
1427 | return IRQ_NONE; | |
1428 | ||
1429 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1430 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | |
1431 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | |
1432 | ||
1433 | /* Schedule processing of any interrupting queues */ | |
1434 | channel = &efx->channel[0]; | |
1435 | while (queues) { | |
1436 | if (queues & 0x01) | |
1437 | efx_schedule_channel(channel); | |
1438 | channel++; | |
1439 | queues >>= 1; | |
1440 | } | |
1441 | ||
1442 | return IRQ_HANDLED; | |
1443 | } | |
1444 | ||
1445 | ||
1446 | static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) | |
1447 | { | |
d3208b5e BH |
1448 | struct efx_nic *efx = dev_id; |
1449 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
1450 | struct efx_channel *channel; |
1451 | int syserr; | |
1452 | int queues; | |
1453 | ||
1454 | /* Check to see if this is our interrupt. If it isn't, we | |
1455 | * exit without having touched the hardware. | |
1456 | */ | |
1457 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | |
1458 | EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq, | |
1459 | raw_smp_processor_id()); | |
1460 | return IRQ_NONE; | |
1461 | } | |
1462 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1463 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1464 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1465 | ||
1466 | /* Check to see if we have a serious error condition */ | |
1467 | syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); | |
1468 | if (unlikely(syserr)) | |
1469 | return falcon_fatal_interrupt(efx); | |
1470 | ||
1471 | /* Determine interrupting queues, clear interrupt status | |
1472 | * register and acknowledge the device interrupt. | |
1473 | */ | |
1474 | BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS); | |
1475 | queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS); | |
1476 | EFX_ZERO_OWORD(*int_ker); | |
1477 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | |
1478 | falcon_irq_ack_a1(efx); | |
1479 | ||
1480 | /* Schedule processing of any interrupting queues */ | |
1481 | channel = &efx->channel[0]; | |
1482 | while (queues) { | |
1483 | if (queues & 0x01) | |
1484 | efx_schedule_channel(channel); | |
1485 | channel++; | |
1486 | queues >>= 1; | |
1487 | } | |
1488 | ||
1489 | return IRQ_HANDLED; | |
1490 | } | |
1491 | ||
1492 | /* Handle an MSI interrupt from Falcon | |
1493 | * | |
1494 | * Handle an MSI hardware interrupt. This routine schedules event | |
1495 | * queue processing. No interrupt acknowledgement cycle is necessary. | |
1496 | * Also, we never need to check that the interrupt is for us, since | |
1497 | * MSI interrupts cannot be shared. | |
1498 | */ | |
1499 | static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id) | |
1500 | { | |
d3208b5e | 1501 | struct efx_channel *channel = dev_id; |
8ceee660 | 1502 | struct efx_nic *efx = channel->efx; |
d3208b5e | 1503 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1504 | int syserr; |
1505 | ||
1506 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1507 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1508 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1509 | ||
1510 | /* Check to see if we have a serious error condition */ | |
1511 | syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); | |
1512 | if (unlikely(syserr)) | |
1513 | return falcon_fatal_interrupt(efx); | |
1514 | ||
1515 | /* Schedule processing of the channel */ | |
1516 | efx_schedule_channel(channel); | |
1517 | ||
1518 | return IRQ_HANDLED; | |
1519 | } | |
1520 | ||
1521 | ||
1522 | /* Setup RSS indirection table. | |
1523 | * This maps from the hash value of the packet to RXQ | |
1524 | */ | |
1525 | static void falcon_setup_rss_indir_table(struct efx_nic *efx) | |
1526 | { | |
1527 | int i = 0; | |
1528 | unsigned long offset; | |
1529 | efx_dword_t dword; | |
1530 | ||
55668611 | 1531 | if (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
1532 | return; |
1533 | ||
1534 | for (offset = RX_RSS_INDIR_TBL_B0; | |
1535 | offset < RX_RSS_INDIR_TBL_B0 + 0x800; | |
1536 | offset += 0x10) { | |
1537 | EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0, | |
1538 | i % efx->rss_queues); | |
1539 | falcon_writel(efx, &dword, offset); | |
1540 | i++; | |
1541 | } | |
1542 | } | |
1543 | ||
1544 | /* Hook interrupt handler(s) | |
1545 | * Try MSI and then legacy interrupts. | |
1546 | */ | |
1547 | int falcon_init_interrupt(struct efx_nic *efx) | |
1548 | { | |
1549 | struct efx_channel *channel; | |
1550 | int rc; | |
1551 | ||
1552 | if (!EFX_INT_MODE_USE_MSI(efx)) { | |
1553 | irq_handler_t handler; | |
55668611 | 1554 | if (falcon_rev(efx) >= FALCON_REV_B0) |
8ceee660 BH |
1555 | handler = falcon_legacy_interrupt_b0; |
1556 | else | |
1557 | handler = falcon_legacy_interrupt_a1; | |
1558 | ||
1559 | rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, | |
1560 | efx->name, efx); | |
1561 | if (rc) { | |
1562 | EFX_ERR(efx, "failed to hook legacy IRQ %d\n", | |
1563 | efx->pci_dev->irq); | |
1564 | goto fail1; | |
1565 | } | |
1566 | return 0; | |
1567 | } | |
1568 | ||
1569 | /* Hook MSI or MSI-X interrupt */ | |
1570 | efx_for_each_channel_with_interrupt(channel, efx) { | |
1571 | rc = request_irq(channel->irq, falcon_msi_interrupt, | |
1572 | IRQF_PROBE_SHARED, /* Not shared */ | |
1573 | efx->name, channel); | |
1574 | if (rc) { | |
1575 | EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq); | |
1576 | goto fail2; | |
1577 | } | |
1578 | } | |
1579 | ||
1580 | return 0; | |
1581 | ||
1582 | fail2: | |
1583 | efx_for_each_channel_with_interrupt(channel, efx) | |
1584 | free_irq(channel->irq, channel); | |
1585 | fail1: | |
1586 | return rc; | |
1587 | } | |
1588 | ||
1589 | void falcon_fini_interrupt(struct efx_nic *efx) | |
1590 | { | |
1591 | struct efx_channel *channel; | |
1592 | efx_oword_t reg; | |
1593 | ||
1594 | /* Disable MSI/MSI-X interrupts */ | |
b3475645 | 1595 | efx_for_each_channel_with_interrupt(channel, efx) { |
8ceee660 BH |
1596 | if (channel->irq) |
1597 | free_irq(channel->irq, channel); | |
b3475645 | 1598 | } |
8ceee660 BH |
1599 | |
1600 | /* ACK legacy interrupt */ | |
55668611 | 1601 | if (falcon_rev(efx) >= FALCON_REV_B0) |
8ceee660 BH |
1602 | falcon_read(efx, ®, INT_ISR0_B0); |
1603 | else | |
1604 | falcon_irq_ack_a1(efx); | |
1605 | ||
1606 | /* Disable legacy interrupt */ | |
1607 | if (efx->legacy_irq) | |
1608 | free_irq(efx->legacy_irq, efx); | |
1609 | } | |
1610 | ||
1611 | /************************************************************************** | |
1612 | * | |
1613 | * EEPROM/flash | |
1614 | * | |
1615 | ************************************************************************** | |
1616 | */ | |
1617 | ||
1618 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) | |
1619 | ||
1620 | /* Wait for SPI command completion */ | |
1621 | static int falcon_spi_wait(struct efx_nic *efx) | |
1622 | { | |
1623 | efx_oword_t reg; | |
1624 | int cmd_en, timer_active; | |
1625 | int count; | |
1626 | ||
1627 | count = 0; | |
1628 | do { | |
1629 | falcon_read(efx, ®, EE_SPI_HCMD_REG_KER); | |
1630 | cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN); | |
1631 | timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE); | |
1632 | if (!cmd_en && !timer_active) | |
1633 | return 0; | |
1634 | udelay(10); | |
1635 | } while (++count < 10000); /* wait upto 100msec */ | |
1636 | EFX_ERR(efx, "timed out waiting for SPI\n"); | |
1637 | return -ETIMEDOUT; | |
1638 | } | |
1639 | ||
1640 | static int | |
1641 | falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command, | |
1642 | unsigned int address, unsigned int addr_len, | |
1643 | void *data, unsigned int len) | |
1644 | { | |
1645 | efx_oword_t reg; | |
1646 | int rc; | |
1647 | ||
1648 | BUG_ON(len > FALCON_SPI_MAX_LEN); | |
1649 | ||
1650 | /* Check SPI not currently being accessed */ | |
1651 | rc = falcon_spi_wait(efx); | |
1652 | if (rc) | |
1653 | return rc; | |
1654 | ||
1655 | /* Program address register */ | |
1656 | EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address); | |
1657 | falcon_write(efx, ®, EE_SPI_HADR_REG_KER); | |
1658 | ||
1659 | /* Issue read command */ | |
1660 | EFX_POPULATE_OWORD_7(reg, | |
1661 | EE_SPI_HCMD_CMD_EN, 1, | |
1662 | EE_SPI_HCMD_SF_SEL, device_id, | |
1663 | EE_SPI_HCMD_DABCNT, len, | |
1664 | EE_SPI_HCMD_READ, EE_SPI_READ, | |
1665 | EE_SPI_HCMD_DUBCNT, 0, | |
1666 | EE_SPI_HCMD_ADBCNT, addr_len, | |
1667 | EE_SPI_HCMD_ENC, command); | |
1668 | falcon_write(efx, ®, EE_SPI_HCMD_REG_KER); | |
1669 | ||
1670 | /* Wait for read to complete */ | |
1671 | rc = falcon_spi_wait(efx); | |
1672 | if (rc) | |
1673 | return rc; | |
1674 | ||
1675 | /* Read data */ | |
1676 | falcon_read(efx, ®, EE_SPI_HDATA_REG_KER); | |
1677 | memcpy(data, ®, len); | |
1678 | return 0; | |
1679 | } | |
1680 | ||
1681 | /************************************************************************** | |
1682 | * | |
1683 | * MAC wrapper | |
1684 | * | |
1685 | ************************************************************************** | |
1686 | */ | |
1687 | void falcon_drain_tx_fifo(struct efx_nic *efx) | |
1688 | { | |
1689 | efx_oword_t temp; | |
1690 | int count; | |
1691 | ||
55668611 | 1692 | if ((falcon_rev(efx) < FALCON_REV_B0) || |
3273c2e8 | 1693 | (efx->loopback_mode != LOOPBACK_NONE)) |
8ceee660 BH |
1694 | return; |
1695 | ||
1696 | falcon_read(efx, &temp, MAC0_CTRL_REG_KER); | |
1697 | /* There is no point in draining more than once */ | |
1698 | if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0)) | |
1699 | return; | |
1700 | ||
1701 | /* MAC stats will fail whilst the TX fifo is draining. Serialise | |
1702 | * the drain sequence with the statistics fetch */ | |
1703 | spin_lock(&efx->stats_lock); | |
1704 | ||
1705 | EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1); | |
1706 | falcon_write(efx, &temp, MAC0_CTRL_REG_KER); | |
1707 | ||
1708 | /* Reset the MAC and EM block. */ | |
1709 | falcon_read(efx, &temp, GLB_CTL_REG_KER); | |
1710 | EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1); | |
1711 | EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1); | |
1712 | EFX_SET_OWORD_FIELD(temp, RST_EM, 1); | |
1713 | falcon_write(efx, &temp, GLB_CTL_REG_KER); | |
1714 | ||
1715 | count = 0; | |
1716 | while (1) { | |
1717 | falcon_read(efx, &temp, GLB_CTL_REG_KER); | |
1718 | if (!EFX_OWORD_FIELD(temp, RST_XGTX) && | |
1719 | !EFX_OWORD_FIELD(temp, RST_XGRX) && | |
1720 | !EFX_OWORD_FIELD(temp, RST_EM)) { | |
1721 | EFX_LOG(efx, "Completed MAC reset after %d loops\n", | |
1722 | count); | |
1723 | break; | |
1724 | } | |
1725 | if (count > 20) { | |
1726 | EFX_ERR(efx, "MAC reset failed\n"); | |
1727 | break; | |
1728 | } | |
1729 | count++; | |
1730 | udelay(10); | |
1731 | } | |
1732 | ||
1733 | spin_unlock(&efx->stats_lock); | |
1734 | ||
1735 | /* If we've reset the EM block and the link is up, then | |
1736 | * we'll have to kick the XAUI link so the PHY can recover */ | |
1737 | if (efx->link_up && EFX_WORKAROUND_5147(efx)) | |
1738 | falcon_reset_xaui(efx); | |
1739 | } | |
1740 | ||
1741 | void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) | |
1742 | { | |
1743 | efx_oword_t temp; | |
1744 | ||
55668611 | 1745 | if (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
1746 | return; |
1747 | ||
1748 | /* Isolate the MAC -> RX */ | |
1749 | falcon_read(efx, &temp, RX_CFG_REG_KER); | |
1750 | EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0); | |
1751 | falcon_write(efx, &temp, RX_CFG_REG_KER); | |
1752 | ||
1753 | if (!efx->link_up) | |
1754 | falcon_drain_tx_fifo(efx); | |
1755 | } | |
1756 | ||
1757 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | |
1758 | { | |
1759 | efx_oword_t reg; | |
1760 | int link_speed; | |
dc8cfa55 | 1761 | bool tx_fc; |
8ceee660 BH |
1762 | |
1763 | if (efx->link_options & GM_LPA_10000) | |
1764 | link_speed = 0x3; | |
1765 | else if (efx->link_options & GM_LPA_1000) | |
1766 | link_speed = 0x2; | |
1767 | else if (efx->link_options & GM_LPA_100) | |
1768 | link_speed = 0x1; | |
1769 | else | |
1770 | link_speed = 0x0; | |
1771 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work | |
1772 | * as advertised. Disable to ensure packets are not | |
1773 | * indefinitely held and TX queue can be flushed at any point | |
1774 | * while the link is down. */ | |
1775 | EFX_POPULATE_OWORD_5(reg, | |
1776 | MAC_XOFF_VAL, 0xffff /* max pause time */, | |
1777 | MAC_BCAD_ACPT, 1, | |
1778 | MAC_UC_PROM, efx->promiscuous, | |
1779 | MAC_LINK_STATUS, 1, /* always set */ | |
1780 | MAC_SPEED, link_speed); | |
1781 | /* On B0, MAC backpressure can be disabled and packets get | |
1782 | * discarded. */ | |
55668611 | 1783 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
8ceee660 BH |
1784 | EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0, |
1785 | !efx->link_up); | |
1786 | } | |
1787 | ||
1788 | falcon_write(efx, ®, MAC0_CTRL_REG_KER); | |
1789 | ||
1790 | /* Restore the multicast hash registers. */ | |
1791 | falcon_set_multicast_hash(efx); | |
1792 | ||
1793 | /* Transmission of pause frames when RX crosses the threshold is | |
1794 | * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL. | |
1795 | * Action on receipt of pause frames is controller by XM_DIS_FCNTL */ | |
dc8cfa55 | 1796 | tx_fc = !!(efx->flow_control & EFX_FC_TX); |
8ceee660 BH |
1797 | falcon_read(efx, ®, RX_CFG_REG_KER); |
1798 | EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc); | |
1799 | ||
1800 | /* Unisolate the MAC -> RX */ | |
55668611 | 1801 | if (falcon_rev(efx) >= FALCON_REV_B0) |
8ceee660 BH |
1802 | EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1); |
1803 | falcon_write(efx, ®, RX_CFG_REG_KER); | |
1804 | } | |
1805 | ||
1806 | int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset) | |
1807 | { | |
1808 | efx_oword_t reg; | |
1809 | u32 *dma_done; | |
1810 | int i; | |
1811 | ||
1812 | if (disable_dma_stats) | |
1813 | return 0; | |
1814 | ||
1815 | /* Statistics fetch will fail if the MAC is in TX drain */ | |
55668611 | 1816 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
8ceee660 BH |
1817 | efx_oword_t temp; |
1818 | falcon_read(efx, &temp, MAC0_CTRL_REG_KER); | |
1819 | if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0)) | |
1820 | return 0; | |
1821 | } | |
1822 | ||
1823 | dma_done = (efx->stats_buffer.addr + done_offset); | |
1824 | *dma_done = FALCON_STATS_NOT_DONE; | |
1825 | wmb(); /* ensure done flag is clear */ | |
1826 | ||
1827 | /* Initiate DMA transfer of stats */ | |
1828 | EFX_POPULATE_OWORD_2(reg, | |
1829 | MAC_STAT_DMA_CMD, 1, | |
1830 | MAC_STAT_DMA_ADR, | |
1831 | efx->stats_buffer.dma_addr); | |
1832 | falcon_write(efx, ®, MAC0_STAT_DMA_REG_KER); | |
1833 | ||
1834 | /* Wait for transfer to complete */ | |
1835 | for (i = 0; i < 400; i++) { | |
1836 | if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) | |
1837 | return 0; | |
1838 | udelay(10); | |
1839 | } | |
1840 | ||
1841 | EFX_ERR(efx, "timed out waiting for statistics\n"); | |
1842 | return -ETIMEDOUT; | |
1843 | } | |
1844 | ||
1845 | /************************************************************************** | |
1846 | * | |
1847 | * PHY access via GMII | |
1848 | * | |
1849 | ************************************************************************** | |
1850 | */ | |
1851 | ||
1852 | /* Use the top bit of the MII PHY id to indicate the PHY type | |
1853 | * (1G/10G), with the remaining bits as the actual PHY id. | |
1854 | * | |
1855 | * This allows us to avoid leaking information from the mii_if_info | |
1856 | * structure into other data structures. | |
1857 | */ | |
1858 | #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR) | |
1859 | #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1) | |
1860 | #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1) | |
1861 | #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1) | |
1862 | #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1)) | |
1863 | ||
1864 | ||
1865 | /* Packing the clause 45 port and device fields into a single value */ | |
1866 | #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN) | |
1867 | #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH | |
1868 | #define MD_DEV_ADR_COMP_LBN 0 | |
1869 | #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH | |
1870 | ||
1871 | ||
1872 | /* Wait for GMII access to complete */ | |
1873 | static int falcon_gmii_wait(struct efx_nic *efx) | |
1874 | { | |
1875 | efx_dword_t md_stat; | |
1876 | int count; | |
1877 | ||
1878 | for (count = 0; count < 1000; count++) { /* wait upto 10ms */ | |
1879 | falcon_readl(efx, &md_stat, MD_STAT_REG_KER); | |
1880 | if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) { | |
1881 | if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 || | |
1882 | EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) { | |
1883 | EFX_ERR(efx, "error from GMII access " | |
1884 | EFX_DWORD_FMT"\n", | |
1885 | EFX_DWORD_VAL(md_stat)); | |
1886 | return -EIO; | |
1887 | } | |
1888 | return 0; | |
1889 | } | |
1890 | udelay(10); | |
1891 | } | |
1892 | EFX_ERR(efx, "timed out waiting for GMII\n"); | |
1893 | return -ETIMEDOUT; | |
1894 | } | |
1895 | ||
1896 | /* Writes a GMII register of a PHY connected to Falcon using MDIO. */ | |
1897 | static void falcon_mdio_write(struct net_device *net_dev, int phy_id, | |
1898 | int addr, int value) | |
1899 | { | |
767e468c | 1900 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1901 | unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK; |
1902 | efx_oword_t reg; | |
1903 | ||
1904 | /* The 'generic' prt/dev packing in mdio_10g.h is conveniently | |
1905 | * chosen so that the only current user, Falcon, can take the | |
1906 | * packed value and use them directly. | |
1907 | * Fail to build if this assumption is broken. | |
1908 | */ | |
1909 | BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G); | |
1910 | BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH); | |
1911 | BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN); | |
1912 | BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN); | |
1913 | ||
1914 | if (phy_id2 == PHY_ADDR_INVALID) | |
1915 | return; | |
1916 | ||
1917 | /* See falcon_mdio_read for an explanation. */ | |
1918 | if (!(phy_id & FALCON_PHY_ID_10G)) { | |
1919 | int mmd = ffs(efx->phy_op->mmds) - 1; | |
1920 | EFX_TRACE(efx, "Fixing erroneous clause22 write\n"); | |
1921 | phy_id2 = mdio_clause45_pack(phy_id2, mmd) | |
1922 | & FALCON_PHY_ID_ID_MASK; | |
1923 | } | |
1924 | ||
1925 | EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id, | |
1926 | addr, value); | |
1927 | ||
1928 | spin_lock_bh(&efx->phy_lock); | |
1929 | ||
1930 | /* Check MII not currently being accessed */ | |
1931 | if (falcon_gmii_wait(efx) != 0) | |
1932 | goto out; | |
1933 | ||
1934 | /* Write the address/ID register */ | |
1935 | EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr); | |
1936 | falcon_write(efx, ®, MD_PHY_ADR_REG_KER); | |
1937 | ||
1938 | EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2); | |
1939 | falcon_write(efx, ®, MD_ID_REG_KER); | |
1940 | ||
1941 | /* Write data */ | |
1942 | EFX_POPULATE_OWORD_1(reg, MD_TXD, value); | |
1943 | falcon_write(efx, ®, MD_TXD_REG_KER); | |
1944 | ||
1945 | EFX_POPULATE_OWORD_2(reg, | |
1946 | MD_WRC, 1, | |
1947 | MD_GC, 0); | |
1948 | falcon_write(efx, ®, MD_CS_REG_KER); | |
1949 | ||
1950 | /* Wait for data to be written */ | |
1951 | if (falcon_gmii_wait(efx) != 0) { | |
1952 | /* Abort the write operation */ | |
1953 | EFX_POPULATE_OWORD_2(reg, | |
1954 | MD_WRC, 0, | |
1955 | MD_GC, 1); | |
1956 | falcon_write(efx, ®, MD_CS_REG_KER); | |
1957 | udelay(10); | |
1958 | } | |
1959 | ||
1960 | out: | |
1961 | spin_unlock_bh(&efx->phy_lock); | |
1962 | } | |
1963 | ||
1964 | /* Reads a GMII register from a PHY connected to Falcon. If no value | |
1965 | * could be read, -1 will be returned. */ | |
1966 | static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr) | |
1967 | { | |
767e468c | 1968 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 BH |
1969 | unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK; |
1970 | efx_oword_t reg; | |
1971 | int value = -1; | |
1972 | ||
1973 | if (phy_addr == PHY_ADDR_INVALID) | |
1974 | return -1; | |
1975 | ||
1976 | /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G) | |
1977 | * but the generic Linux code does not make any distinction or have | |
1978 | * any state for this. | |
1979 | * We spot the case where someone tried to talk 22 to a 45 PHY and | |
1980 | * redirect the request to the lowest numbered MMD as a clause45 | |
1981 | * request. This is enough to allow simple queries like id and link | |
1982 | * state to succeed. TODO: We may need to do more in future. | |
1983 | */ | |
1984 | if (!(phy_id & FALCON_PHY_ID_10G)) { | |
1985 | int mmd = ffs(efx->phy_op->mmds) - 1; | |
1986 | EFX_TRACE(efx, "Fixing erroneous clause22 read\n"); | |
1987 | phy_addr = mdio_clause45_pack(phy_addr, mmd) | |
1988 | & FALCON_PHY_ID_ID_MASK; | |
1989 | } | |
1990 | ||
1991 | spin_lock_bh(&efx->phy_lock); | |
1992 | ||
1993 | /* Check MII not currently being accessed */ | |
1994 | if (falcon_gmii_wait(efx) != 0) | |
1995 | goto out; | |
1996 | ||
1997 | EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr); | |
1998 | falcon_write(efx, ®, MD_PHY_ADR_REG_KER); | |
1999 | ||
2000 | EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr); | |
2001 | falcon_write(efx, ®, MD_ID_REG_KER); | |
2002 | ||
2003 | /* Request data to be read */ | |
2004 | EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0); | |
2005 | falcon_write(efx, ®, MD_CS_REG_KER); | |
2006 | ||
2007 | /* Wait for data to become available */ | |
2008 | value = falcon_gmii_wait(efx); | |
2009 | if (value == 0) { | |
2010 | falcon_read(efx, ®, MD_RXD_REG_KER); | |
2011 | value = EFX_OWORD_FIELD(reg, MD_RXD); | |
2012 | EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n", | |
2013 | phy_id, addr, value); | |
2014 | } else { | |
2015 | /* Abort the read operation */ | |
2016 | EFX_POPULATE_OWORD_2(reg, | |
2017 | MD_RIC, 0, | |
2018 | MD_GC, 1); | |
2019 | falcon_write(efx, ®, MD_CS_REG_KER); | |
2020 | ||
2021 | EFX_LOG(efx, "read from GMII 0x%x register %02x, got " | |
2022 | "error %d\n", phy_id, addr, value); | |
2023 | } | |
2024 | ||
2025 | out: | |
2026 | spin_unlock_bh(&efx->phy_lock); | |
2027 | ||
2028 | return value; | |
2029 | } | |
2030 | ||
2031 | static void falcon_init_mdio(struct mii_if_info *gmii) | |
2032 | { | |
2033 | gmii->mdio_read = falcon_mdio_read; | |
2034 | gmii->mdio_write = falcon_mdio_write; | |
2035 | gmii->phy_id_mask = FALCON_PHY_ID_MASK; | |
2036 | gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1); | |
2037 | } | |
2038 | ||
2039 | static int falcon_probe_phy(struct efx_nic *efx) | |
2040 | { | |
2041 | switch (efx->phy_type) { | |
2042 | case PHY_TYPE_10XPRESS: | |
2043 | efx->phy_op = &falcon_tenxpress_phy_ops; | |
2044 | break; | |
2045 | case PHY_TYPE_XFP: | |
2046 | efx->phy_op = &falcon_xfp_phy_ops; | |
2047 | break; | |
2048 | default: | |
2049 | EFX_ERR(efx, "Unknown PHY type %d\n", | |
2050 | efx->phy_type); | |
2051 | return -1; | |
2052 | } | |
3273c2e8 BH |
2053 | |
2054 | efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks; | |
8ceee660 BH |
2055 | return 0; |
2056 | } | |
2057 | ||
2058 | /* This call is responsible for hooking in the MAC and PHY operations */ | |
2059 | int falcon_probe_port(struct efx_nic *efx) | |
2060 | { | |
2061 | int rc; | |
2062 | ||
2063 | /* Hook in PHY operations table */ | |
2064 | rc = falcon_probe_phy(efx); | |
2065 | if (rc) | |
2066 | return rc; | |
2067 | ||
2068 | /* Set up GMII structure for PHY */ | |
dc8cfa55 | 2069 | efx->mii.supports_gmii = true; |
8ceee660 BH |
2070 | falcon_init_mdio(&efx->mii); |
2071 | ||
2072 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ | |
55668611 | 2073 | if (falcon_rev(efx) >= FALCON_REV_B0) |
8ceee660 BH |
2074 | efx->flow_control = EFX_FC_RX | EFX_FC_TX; |
2075 | else | |
2076 | efx->flow_control = EFX_FC_RX; | |
2077 | ||
2078 | /* Allocate buffer for stats */ | |
2079 | rc = falcon_alloc_buffer(efx, &efx->stats_buffer, | |
2080 | FALCON_MAC_STATS_SIZE); | |
2081 | if (rc) | |
2082 | return rc; | |
2083 | EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n", | |
2084 | (unsigned long long)efx->stats_buffer.dma_addr, | |
2085 | efx->stats_buffer.addr, | |
2086 | virt_to_phys(efx->stats_buffer.addr)); | |
2087 | ||
2088 | return 0; | |
2089 | } | |
2090 | ||
2091 | void falcon_remove_port(struct efx_nic *efx) | |
2092 | { | |
2093 | falcon_free_buffer(efx, &efx->stats_buffer); | |
2094 | } | |
2095 | ||
2096 | /************************************************************************** | |
2097 | * | |
2098 | * Multicast filtering | |
2099 | * | |
2100 | ************************************************************************** | |
2101 | */ | |
2102 | ||
2103 | void falcon_set_multicast_hash(struct efx_nic *efx) | |
2104 | { | |
2105 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
2106 | ||
2107 | /* Broadcast packets go through the multicast hash filter. | |
2108 | * ether_crc_le() of the broadcast address is 0xbe2612ff | |
2109 | * so we always add bit 0xff to the mask. | |
2110 | */ | |
2111 | set_bit_le(0xff, mc_hash->byte); | |
2112 | ||
2113 | falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER); | |
2114 | falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER); | |
2115 | } | |
2116 | ||
2117 | /************************************************************************** | |
2118 | * | |
2119 | * Device reset | |
2120 | * | |
2121 | ************************************************************************** | |
2122 | */ | |
2123 | ||
2124 | /* Resets NIC to known state. This routine must be called in process | |
2125 | * context and is allowed to sleep. */ | |
2126 | int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) | |
2127 | { | |
2128 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2129 | efx_oword_t glb_ctl_reg_ker; | |
2130 | int rc; | |
2131 | ||
2132 | EFX_LOG(efx, "performing hardware reset (%d)\n", method); | |
2133 | ||
2134 | /* Initiate device reset */ | |
2135 | if (method == RESET_TYPE_WORLD) { | |
2136 | rc = pci_save_state(efx->pci_dev); | |
2137 | if (rc) { | |
2138 | EFX_ERR(efx, "failed to backup PCI state of primary " | |
2139 | "function prior to hardware reset\n"); | |
2140 | goto fail1; | |
2141 | } | |
2142 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2143 | rc = pci_save_state(nic_data->pci_dev2); | |
2144 | if (rc) { | |
2145 | EFX_ERR(efx, "failed to backup PCI state of " | |
2146 | "secondary function prior to " | |
2147 | "hardware reset\n"); | |
2148 | goto fail2; | |
2149 | } | |
2150 | } | |
2151 | ||
2152 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | |
2153 | EXT_PHY_RST_DUR, 0x7, | |
2154 | SWRST, 1); | |
2155 | } else { | |
2156 | int reset_phy = (method == RESET_TYPE_INVISIBLE ? | |
2157 | EXCLUDE_FROM_RESET : 0); | |
2158 | ||
2159 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, | |
2160 | EXT_PHY_RST_CTL, reset_phy, | |
2161 | PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET, | |
2162 | PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET, | |
2163 | PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET, | |
2164 | EE_RST_CTL, EXCLUDE_FROM_RESET, | |
2165 | EXT_PHY_RST_DUR, 0x7 /* 10ms */, | |
2166 | SWRST, 1); | |
2167 | } | |
2168 | falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER); | |
2169 | ||
2170 | EFX_LOG(efx, "waiting for hardware reset\n"); | |
2171 | schedule_timeout_uninterruptible(HZ / 20); | |
2172 | ||
2173 | /* Restore PCI configuration if needed */ | |
2174 | if (method == RESET_TYPE_WORLD) { | |
2175 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2176 | rc = pci_restore_state(nic_data->pci_dev2); | |
2177 | if (rc) { | |
2178 | EFX_ERR(efx, "failed to restore PCI config for " | |
2179 | "the secondary function\n"); | |
2180 | goto fail3; | |
2181 | } | |
2182 | } | |
2183 | rc = pci_restore_state(efx->pci_dev); | |
2184 | if (rc) { | |
2185 | EFX_ERR(efx, "failed to restore PCI config for the " | |
2186 | "primary function\n"); | |
2187 | goto fail4; | |
2188 | } | |
2189 | EFX_LOG(efx, "successfully restored PCI config\n"); | |
2190 | } | |
2191 | ||
2192 | /* Assert that reset complete */ | |
2193 | falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER); | |
2194 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) { | |
2195 | rc = -ETIMEDOUT; | |
2196 | EFX_ERR(efx, "timed out waiting for hardware reset\n"); | |
2197 | goto fail5; | |
2198 | } | |
2199 | EFX_LOG(efx, "hardware reset complete\n"); | |
2200 | ||
2201 | return 0; | |
2202 | ||
2203 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
2204 | fail2: | |
2205 | fail3: | |
2206 | pci_restore_state(efx->pci_dev); | |
2207 | fail1: | |
2208 | fail4: | |
2209 | fail5: | |
2210 | return rc; | |
2211 | } | |
2212 | ||
2213 | /* Zeroes out the SRAM contents. This routine must be called in | |
2214 | * process context and is allowed to sleep. | |
2215 | */ | |
2216 | static int falcon_reset_sram(struct efx_nic *efx) | |
2217 | { | |
2218 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | |
2219 | int count; | |
2220 | ||
2221 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
2222 | falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER); | |
2223 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1); | |
2224 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1); | |
2225 | falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER); | |
2226 | ||
2227 | /* Initiate SRAM reset */ | |
2228 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | |
2229 | SRAM_OOB_BT_INIT_EN, 1, | |
2230 | SRM_NUM_BANKS_AND_BANK_SIZE, 0); | |
2231 | falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER); | |
2232 | ||
2233 | /* Wait for SRAM reset to complete */ | |
2234 | count = 0; | |
2235 | do { | |
2236 | EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count); | |
2237 | ||
2238 | /* SRAM reset is slow; expect around 16ms */ | |
2239 | schedule_timeout_uninterruptible(HZ / 50); | |
2240 | ||
2241 | /* Check for reset complete */ | |
2242 | falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER); | |
2243 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) { | |
2244 | EFX_LOG(efx, "SRAM reset complete\n"); | |
2245 | ||
2246 | return 0; | |
2247 | } | |
2248 | } while (++count < 20); /* wait upto 0.4 sec */ | |
2249 | ||
2250 | EFX_ERR(efx, "timed out waiting for SRAM reset\n"); | |
2251 | return -ETIMEDOUT; | |
2252 | } | |
2253 | ||
2254 | /* Extract non-volatile configuration */ | |
2255 | static int falcon_probe_nvconfig(struct efx_nic *efx) | |
2256 | { | |
2257 | struct falcon_nvconfig *nvconfig; | |
2258 | efx_oword_t nic_stat; | |
2259 | int device_id; | |
2260 | unsigned addr_len; | |
2261 | size_t offset, len; | |
2262 | int magic_num, struct_ver, board_rev; | |
2263 | int rc; | |
2264 | ||
2265 | /* Find the boot device. */ | |
2266 | falcon_read(efx, &nic_stat, NIC_STAT_REG); | |
2267 | if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) { | |
2268 | device_id = EE_SPI_FLASH; | |
2269 | addr_len = 3; | |
2270 | } else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) { | |
2271 | device_id = EE_SPI_EEPROM; | |
2272 | addr_len = 2; | |
2273 | } else { | |
2274 | return -ENODEV; | |
2275 | } | |
2276 | ||
2277 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); | |
2278 | ||
2279 | /* Read the whole configuration structure into memory. */ | |
2280 | for (offset = 0; offset < sizeof(*nvconfig); offset += len) { | |
2281 | len = min(sizeof(*nvconfig) - offset, | |
2282 | (size_t) FALCON_SPI_MAX_LEN); | |
2283 | rc = falcon_spi_read(efx, device_id, SPI_READ, | |
2284 | NVCONFIG_BASE + offset, addr_len, | |
2285 | (char *)nvconfig + offset, len); | |
2286 | if (rc) | |
2287 | goto out; | |
2288 | } | |
2289 | ||
2290 | /* Read the MAC addresses */ | |
2291 | memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); | |
2292 | ||
2293 | /* Read the board configuration. */ | |
2294 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
2295 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
2296 | ||
2297 | if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) { | |
2298 | EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x " | |
2299 | "therefore using defaults\n", magic_num, struct_ver); | |
2300 | efx->phy_type = PHY_TYPE_NONE; | |
2301 | efx->mii.phy_id = PHY_ADDR_INVALID; | |
2302 | board_rev = 0; | |
2303 | } else { | |
2304 | struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; | |
2305 | ||
2306 | efx->phy_type = v2->port0_phy_type; | |
2307 | efx->mii.phy_id = v2->port0_phy_addr; | |
2308 | board_rev = le16_to_cpu(v2->board_revision); | |
2309 | } | |
2310 | ||
2311 | EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id); | |
2312 | ||
2313 | efx_set_board_info(efx, board_rev); | |
2314 | ||
2315 | out: | |
2316 | kfree(nvconfig); | |
2317 | return rc; | |
2318 | } | |
2319 | ||
2320 | /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port | |
2321 | * count, port speed). Set workaround and feature flags accordingly. | |
2322 | */ | |
2323 | static int falcon_probe_nic_variant(struct efx_nic *efx) | |
2324 | { | |
2325 | efx_oword_t altera_build; | |
2326 | ||
2327 | falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER); | |
2328 | if (EFX_OWORD_FIELD(altera_build, VER_ALL)) { | |
2329 | EFX_ERR(efx, "Falcon FPGA not supported\n"); | |
2330 | return -ENODEV; | |
2331 | } | |
2332 | ||
55668611 | 2333 | switch (falcon_rev(efx)) { |
8ceee660 BH |
2334 | case FALCON_REV_A0: |
2335 | case 0xff: | |
2336 | EFX_ERR(efx, "Falcon rev A0 not supported\n"); | |
2337 | return -ENODEV; | |
2338 | ||
2339 | case FALCON_REV_A1:{ | |
2340 | efx_oword_t nic_stat; | |
2341 | ||
2342 | falcon_read(efx, &nic_stat, NIC_STAT_REG); | |
2343 | ||
2344 | if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) { | |
2345 | EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n"); | |
2346 | return -ENODEV; | |
2347 | } | |
2348 | if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) { | |
2349 | EFX_ERR(efx, "1G mode not supported\n"); | |
2350 | return -ENODEV; | |
2351 | } | |
2352 | break; | |
2353 | } | |
2354 | ||
2355 | case FALCON_REV_B0: | |
2356 | break; | |
2357 | ||
2358 | default: | |
55668611 | 2359 | EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx)); |
8ceee660 BH |
2360 | return -ENODEV; |
2361 | } | |
2362 | ||
2363 | return 0; | |
2364 | } | |
2365 | ||
2366 | int falcon_probe_nic(struct efx_nic *efx) | |
2367 | { | |
2368 | struct falcon_nic_data *nic_data; | |
2369 | int rc; | |
2370 | ||
8ceee660 BH |
2371 | /* Allocate storage for hardware specific data */ |
2372 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
5daab96d | 2373 | efx->nic_data = nic_data; |
8ceee660 BH |
2374 | |
2375 | /* Determine number of ports etc. */ | |
2376 | rc = falcon_probe_nic_variant(efx); | |
2377 | if (rc) | |
2378 | goto fail1; | |
2379 | ||
2380 | /* Probe secondary function if expected */ | |
2381 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2382 | struct pci_dev *dev = pci_dev_get(efx->pci_dev); | |
2383 | ||
2384 | while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, | |
2385 | dev))) { | |
2386 | if (dev->bus == efx->pci_dev->bus && | |
2387 | dev->devfn == efx->pci_dev->devfn + 1) { | |
2388 | nic_data->pci_dev2 = dev; | |
2389 | break; | |
2390 | } | |
2391 | } | |
2392 | if (!nic_data->pci_dev2) { | |
2393 | EFX_ERR(efx, "failed to find secondary function\n"); | |
2394 | rc = -ENODEV; | |
2395 | goto fail2; | |
2396 | } | |
2397 | } | |
2398 | ||
2399 | /* Now we can reset the NIC */ | |
2400 | rc = falcon_reset_hw(efx, RESET_TYPE_ALL); | |
2401 | if (rc) { | |
2402 | EFX_ERR(efx, "failed to reset NIC\n"); | |
2403 | goto fail3; | |
2404 | } | |
2405 | ||
2406 | /* Allocate memory for INT_KER */ | |
2407 | rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | |
2408 | if (rc) | |
2409 | goto fail4; | |
2410 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
2411 | ||
2412 | EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n", | |
2413 | (unsigned long long)efx->irq_status.dma_addr, | |
2414 | efx->irq_status.addr, virt_to_phys(efx->irq_status.addr)); | |
2415 | ||
2416 | /* Read in the non-volatile configuration */ | |
2417 | rc = falcon_probe_nvconfig(efx); | |
2418 | if (rc) | |
2419 | goto fail5; | |
2420 | ||
37b5a603 BH |
2421 | /* Initialise I2C adapter */ |
2422 | efx->i2c_adap.owner = THIS_MODULE; | |
37b5a603 BH |
2423 | nic_data->i2c_data = falcon_i2c_bit_operations; |
2424 | nic_data->i2c_data.data = efx; | |
2425 | efx->i2c_adap.algo_data = &nic_data->i2c_data; | |
2426 | efx->i2c_adap.dev.parent = &efx->pci_dev->dev; | |
9dadae68 | 2427 | strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name)); |
37b5a603 BH |
2428 | rc = i2c_bit_add_bus(&efx->i2c_adap); |
2429 | if (rc) | |
2430 | goto fail5; | |
2431 | ||
8ceee660 BH |
2432 | return 0; |
2433 | ||
2434 | fail5: | |
2435 | falcon_free_buffer(efx, &efx->irq_status); | |
2436 | fail4: | |
8ceee660 BH |
2437 | fail3: |
2438 | if (nic_data->pci_dev2) { | |
2439 | pci_dev_put(nic_data->pci_dev2); | |
2440 | nic_data->pci_dev2 = NULL; | |
2441 | } | |
2442 | fail2: | |
8ceee660 BH |
2443 | fail1: |
2444 | kfree(efx->nic_data); | |
2445 | return rc; | |
2446 | } | |
2447 | ||
2448 | /* This call performs hardware-specific global initialisation, such as | |
2449 | * defining the descriptor cache sizes and number of RSS channels. | |
2450 | * It does not set up any buffers, descriptor rings or event queues. | |
2451 | */ | |
2452 | int falcon_init_nic(struct efx_nic *efx) | |
2453 | { | |
8ceee660 BH |
2454 | efx_oword_t temp; |
2455 | unsigned thresh; | |
2456 | int rc; | |
2457 | ||
8ceee660 BH |
2458 | /* Set up the address region register. This is only needed |
2459 | * for the B0 FPGA, but since we are just pushing in the | |
2460 | * reset defaults this may as well be unconditional. */ | |
2461 | EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0, | |
2462 | ADR_REGION1, (1 << 16), | |
2463 | ADR_REGION2, (2 << 16), | |
2464 | ADR_REGION3, (3 << 16)); | |
2465 | falcon_write(efx, &temp, ADR_REGION_REG_KER); | |
2466 | ||
2467 | /* Use on-chip SRAM */ | |
2468 | falcon_read(efx, &temp, NIC_STAT_REG); | |
2469 | EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1); | |
2470 | falcon_write(efx, &temp, NIC_STAT_REG); | |
2471 | ||
2472 | /* Set buffer table mode */ | |
2473 | EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL); | |
2474 | falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER); | |
2475 | ||
2476 | rc = falcon_reset_sram(efx); | |
2477 | if (rc) | |
2478 | return rc; | |
2479 | ||
2480 | /* Set positions of descriptor caches in SRAM. */ | |
2481 | EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); | |
2482 | falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER); | |
2483 | EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); | |
2484 | falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER); | |
2485 | ||
2486 | /* Set TX descriptor cache size. */ | |
2487 | BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER)); | |
2488 | EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER); | |
2489 | falcon_write(efx, &temp, TX_DC_CFG_REG_KER); | |
2490 | ||
2491 | /* Set RX descriptor cache size. Set low watermark to size-8, as | |
2492 | * this allows most efficient prefetching. | |
2493 | */ | |
2494 | BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER)); | |
2495 | EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER); | |
2496 | falcon_write(efx, &temp, RX_DC_CFG_REG_KER); | |
2497 | EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8); | |
2498 | falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER); | |
2499 | ||
2500 | /* Clear the parity enables on the TX data fifos as | |
2501 | * they produce false parity errors because of timing issues | |
2502 | */ | |
2503 | if (EFX_WORKAROUND_5129(efx)) { | |
2504 | falcon_read(efx, &temp, SPARE_REG_KER); | |
2505 | EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0); | |
2506 | falcon_write(efx, &temp, SPARE_REG_KER); | |
2507 | } | |
2508 | ||
2509 | /* Enable all the genuinely fatal interrupts. (They are still | |
2510 | * masked by the overall interrupt mask, controlled by | |
2511 | * falcon_interrupts()). | |
2512 | * | |
2513 | * Note: All other fatal interrupts are enabled | |
2514 | */ | |
2515 | EFX_POPULATE_OWORD_3(temp, | |
2516 | ILL_ADR_INT_KER_EN, 1, | |
2517 | RBUF_OWN_INT_KER_EN, 1, | |
2518 | TBUF_OWN_INT_KER_EN, 1); | |
2519 | EFX_INVERT_OWORD(temp); | |
2520 | falcon_write(efx, &temp, FATAL_INTR_REG_KER); | |
2521 | ||
2522 | /* Set number of RSS queues for receive path. */ | |
2523 | falcon_read(efx, &temp, RX_FILTER_CTL_REG); | |
55668611 | 2524 | if (falcon_rev(efx) >= FALCON_REV_B0) |
8ceee660 BH |
2525 | EFX_SET_OWORD_FIELD(temp, NUM_KER, 0); |
2526 | else | |
2527 | EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1); | |
2528 | if (EFX_WORKAROUND_7244(efx)) { | |
2529 | EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8); | |
2530 | EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8); | |
2531 | EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8); | |
2532 | EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8); | |
2533 | } | |
2534 | falcon_write(efx, &temp, RX_FILTER_CTL_REG); | |
2535 | ||
2536 | falcon_setup_rss_indir_table(efx); | |
2537 | ||
2538 | /* Setup RX. Wait for descriptor is broken and must | |
2539 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
2540 | */ | |
2541 | falcon_read(efx, &temp, RX_SELF_RST_REG_KER); | |
2542 | EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1); | |
2543 | EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1); | |
2544 | if (EFX_WORKAROUND_5583(efx)) | |
2545 | EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1); | |
2546 | falcon_write(efx, &temp, RX_SELF_RST_REG_KER); | |
2547 | ||
2548 | /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be | |
2549 | * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. | |
2550 | */ | |
2551 | falcon_read(efx, &temp, TX_CFG2_REG_KER); | |
2552 | EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe); | |
2553 | EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1); | |
2554 | EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1); | |
2555 | EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0); | |
2556 | EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1); | |
2557 | /* Enable SW_EV to inherit in char driver - assume harmless here */ | |
2558 | EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1); | |
2559 | /* Prefetch threshold 2 => fetch when descriptor cache half empty */ | |
2560 | EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2); | |
2561 | /* Squash TX of packets of 16 bytes or less */ | |
55668611 | 2562 | if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx)) |
8ceee660 BH |
2563 | EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1); |
2564 | falcon_write(efx, &temp, TX_CFG2_REG_KER); | |
2565 | ||
2566 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | |
2567 | * descriptors (which is bad). | |
2568 | */ | |
2569 | falcon_read(efx, &temp, TX_CFG_REG_KER); | |
2570 | EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0); | |
2571 | falcon_write(efx, &temp, TX_CFG_REG_KER); | |
2572 | ||
2573 | /* RX config */ | |
2574 | falcon_read(efx, &temp, RX_CFG_REG_KER); | |
2575 | EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0); | |
2576 | if (EFX_WORKAROUND_7575(efx)) | |
2577 | EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE, | |
2578 | (3 * 4096) / 32); | |
55668611 | 2579 | if (falcon_rev(efx) >= FALCON_REV_B0) |
8ceee660 BH |
2580 | EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1); |
2581 | ||
2582 | /* RX FIFO flow control thresholds */ | |
2583 | thresh = ((rx_xon_thresh_bytes >= 0) ? | |
2584 | rx_xon_thresh_bytes : efx->type->rx_xon_thresh); | |
2585 | EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256); | |
2586 | thresh = ((rx_xoff_thresh_bytes >= 0) ? | |
2587 | rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh); | |
2588 | EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256); | |
2589 | /* RX control FIFO thresholds [32 entries] */ | |
c84a6f18 BH |
2590 | EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20); |
2591 | EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25); | |
8ceee660 BH |
2592 | falcon_write(efx, &temp, RX_CFG_REG_KER); |
2593 | ||
2594 | /* Set destination of both TX and RX Flush events */ | |
55668611 | 2595 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
8ceee660 BH |
2596 | EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0); |
2597 | falcon_write(efx, &temp, DP_CTRL_REG); | |
2598 | } | |
2599 | ||
2600 | return 0; | |
2601 | } | |
2602 | ||
2603 | void falcon_remove_nic(struct efx_nic *efx) | |
2604 | { | |
2605 | struct falcon_nic_data *nic_data = efx->nic_data; | |
37b5a603 BH |
2606 | int rc; |
2607 | ||
2608 | rc = i2c_del_adapter(&efx->i2c_adap); | |
2609 | BUG_ON(rc); | |
8ceee660 BH |
2610 | |
2611 | falcon_free_buffer(efx, &efx->irq_status); | |
2612 | ||
91ad757c | 2613 | falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
2614 | |
2615 | /* Release the second function after the reset */ | |
2616 | if (nic_data->pci_dev2) { | |
2617 | pci_dev_put(nic_data->pci_dev2); | |
2618 | nic_data->pci_dev2 = NULL; | |
2619 | } | |
2620 | ||
2621 | /* Tear down the private nic state */ | |
2622 | kfree(efx->nic_data); | |
2623 | efx->nic_data = NULL; | |
2624 | } | |
2625 | ||
2626 | void falcon_update_nic_stats(struct efx_nic *efx) | |
2627 | { | |
2628 | efx_oword_t cnt; | |
2629 | ||
2630 | falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER); | |
2631 | efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT); | |
2632 | } | |
2633 | ||
2634 | /************************************************************************** | |
2635 | * | |
2636 | * Revision-dependent attributes used by efx.c | |
2637 | * | |
2638 | ************************************************************************** | |
2639 | */ | |
2640 | ||
2641 | struct efx_nic_type falcon_a_nic_type = { | |
2642 | .mem_bar = 2, | |
2643 | .mem_map_size = 0x20000, | |
2644 | .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1, | |
2645 | .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1, | |
2646 | .buf_tbl_base = BUF_TBL_KER_A1, | |
2647 | .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1, | |
2648 | .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1, | |
2649 | .txd_ring_mask = FALCON_TXD_RING_MASK, | |
2650 | .rxd_ring_mask = FALCON_RXD_RING_MASK, | |
2651 | .evq_size = FALCON_EVQ_SIZE, | |
2652 | .max_dma_mask = FALCON_DMA_MASK, | |
2653 | .tx_dma_mask = FALCON_TX_DMA_MASK, | |
2654 | .bug5391_mask = 0xf, | |
2655 | .rx_xoff_thresh = 2048, | |
2656 | .rx_xon_thresh = 512, | |
2657 | .rx_buffer_padding = 0x24, | |
2658 | .max_interrupt_mode = EFX_INT_MODE_MSI, | |
2659 | .phys_addr_channels = 4, | |
2660 | }; | |
2661 | ||
2662 | struct efx_nic_type falcon_b_nic_type = { | |
2663 | .mem_bar = 2, | |
2664 | /* Map everything up to and including the RSS indirection | |
2665 | * table. Don't map MSI-X table, MSI-X PBA since Linux | |
2666 | * requires that they not be mapped. */ | |
2667 | .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800, | |
2668 | .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0, | |
2669 | .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0, | |
2670 | .buf_tbl_base = BUF_TBL_KER_B0, | |
2671 | .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0, | |
2672 | .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0, | |
2673 | .txd_ring_mask = FALCON_TXD_RING_MASK, | |
2674 | .rxd_ring_mask = FALCON_RXD_RING_MASK, | |
2675 | .evq_size = FALCON_EVQ_SIZE, | |
2676 | .max_dma_mask = FALCON_DMA_MASK, | |
2677 | .tx_dma_mask = FALCON_TX_DMA_MASK, | |
2678 | .bug5391_mask = 0, | |
2679 | .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */ | |
2680 | .rx_xon_thresh = 27648, /* ~3*max MTU */ | |
2681 | .rx_buffer_padding = 0, | |
2682 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
2683 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
2684 | * interrupt handler only supports 32 | |
2685 | * channels */ | |
2686 | }; | |
2687 |