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sfc: Removed unncesssary UL suffixes on 0 literals
[deliverable/linux.git] / drivers / net / sfc / falcon.c
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8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
16#include "net_driver.h"
17#include "bitfield.h"
18#include "efx.h"
19#include "mac.h"
20#include "gmii.h"
21#include "spi.h"
22#include "falcon.h"
23#include "falcon_hwdefs.h"
24#include "falcon_io.h"
25#include "mdio_10g.h"
26#include "phy.h"
27#include "boards.h"
28#include "workarounds.h"
29
30/* Falcon hardware control.
31 * Falcon is the internal codename for the SFC4000 controller that is
32 * present in SFE400X evaluation boards
33 */
34
35/**
36 * struct falcon_nic_data - Falcon NIC state
37 * @next_buffer_table: First available buffer table id
38 * @pci_dev2: The secondary PCI device if present
39 */
40struct falcon_nic_data {
41 unsigned next_buffer_table;
42 struct pci_dev *pci_dev2;
43};
44
45/**************************************************************************
46 *
47 * Configurable values
48 *
49 **************************************************************************
50 */
51
52static int disable_dma_stats;
53
54/* This is set to 16 for a good reason. In summary, if larger than
55 * 16, the descriptor cache holds more than a default socket
56 * buffer's worth of packets (for UDP we can only have at most one
57 * socket buffer's worth outstanding). This combined with the fact
58 * that we only get 1 TX event per descriptor cache means the NIC
59 * goes idle.
60 */
61#define TX_DC_ENTRIES 16
62#define TX_DC_ENTRIES_ORDER 0
63#define TX_DC_BASE 0x130000
64
65#define RX_DC_ENTRIES 64
66#define RX_DC_ENTRIES_ORDER 2
67#define RX_DC_BASE 0x100000
68
69/* RX FIFO XOFF watermark
70 *
71 * When the amount of the RX FIFO increases used increases past this
72 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
73 * This also has an effect on RX/TX arbitration
74 */
75static int rx_xoff_thresh_bytes = -1;
76module_param(rx_xoff_thresh_bytes, int, 0644);
77MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
78
79/* RX FIFO XON watermark
80 *
81 * When the amount of the RX FIFO used decreases below this
82 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
83 * This also has an effect on RX/TX arbitration
84 */
85static int rx_xon_thresh_bytes = -1;
86module_param(rx_xon_thresh_bytes, int, 0644);
87MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
88
89/* TX descriptor ring size - min 512 max 4k */
90#define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
91#define FALCON_TXD_RING_SIZE 1024
92#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
93
94/* RX descriptor ring size - min 512 max 4k */
95#define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
96#define FALCON_RXD_RING_SIZE 1024
97#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
98
99/* Event queue size - max 32k */
100#define FALCON_EVQ_ORDER EVQ_SIZE_4K
101#define FALCON_EVQ_SIZE 4096
102#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
103
104/* Max number of internal errors. After this resets will not be performed */
105#define FALCON_MAX_INT_ERRORS 4
106
107/* Maximum period that we wait for flush events. If the flush event
108 * doesn't arrive in this period of time then we check if the queue
109 * was disabled anyway. */
110#define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
111
112/**************************************************************************
113 *
114 * Falcon constants
115 *
116 **************************************************************************
117 */
118
119/* DMA address mask (up to 46-bit, avoiding compiler warnings)
120 *
121 * Note that it is possible to have a platform with 64-bit longs and
122 * 32-bit DMA addresses, or vice versa. EFX_DMA_MASK takes care of the
123 * platform DMA mask.
124 */
125#if BITS_PER_LONG == 64
126#define FALCON_DMA_MASK EFX_DMA_MASK(0x00003fffffffffffUL)
127#else
128#define FALCON_DMA_MASK EFX_DMA_MASK(0x00003fffffffffffULL)
129#endif
130
131/* TX DMA length mask (13-bit) */
132#define FALCON_TX_DMA_MASK (4096 - 1)
133
134/* Size and alignment of special buffers (4KB) */
135#define FALCON_BUF_SIZE 4096
136
137/* Dummy SRAM size code */
138#define SRM_NB_BSZ_ONCHIP_ONLY (-1)
139
140/* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
141#define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
142#define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
143#define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
144#define PCI_EXP_LNKSTA_LNK_WID 0x3f0
145#define PCI_EXP_LNKSTA_LNK_WID_LBN 4
146
147#define FALCON_IS_DUAL_FUNC(efx) \
148 (FALCON_REV(efx) < FALCON_REV_B0)
149
150/**************************************************************************
151 *
152 * Falcon hardware access
153 *
154 **************************************************************************/
155
156/* Read the current event from the event queue */
157static inline efx_qword_t *falcon_event(struct efx_channel *channel,
158 unsigned int index)
159{
160 return (((efx_qword_t *) (channel->eventq.addr)) + index);
161}
162
163/* See if an event is present
164 *
165 * We check both the high and low dword of the event for all ones. We
166 * wrote all ones when we cleared the event, and no valid event can
167 * have all ones in either its high or low dwords. This approach is
168 * robust against reordering.
169 *
170 * Note that using a single 64-bit comparison is incorrect; even
171 * though the CPU read will be atomic, the DMA write may not be.
172 */
173static inline int falcon_event_present(efx_qword_t *event)
174{
175 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
176 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
177}
178
179/**************************************************************************
180 *
181 * I2C bus - this is a bit-bashing interface using GPIO pins
182 * Note that it uses the output enables to tristate the outputs
183 * SDA is the data pin and SCL is the clock
184 *
185 **************************************************************************
186 */
187static void falcon_setsdascl(struct efx_i2c_interface *i2c)
188{
189 efx_oword_t reg;
190
191 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
192 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, (i2c->scl ? 0 : 1));
193 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, (i2c->sda ? 0 : 1));
194 falcon_write(i2c->efx, &reg, GPIO_CTL_REG_KER);
195}
196
197static int falcon_getsda(struct efx_i2c_interface *i2c)
198{
199 efx_oword_t reg;
200
201 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
202 return EFX_OWORD_FIELD(reg, GPIO3_IN);
203}
204
205static int falcon_getscl(struct efx_i2c_interface *i2c)
206{
207 efx_oword_t reg;
208
209 falcon_read(i2c->efx, &reg, GPIO_CTL_REG_KER);
210 return EFX_DWORD_FIELD(reg, GPIO0_IN);
211}
212
213static struct efx_i2c_bit_operations falcon_i2c_bit_operations = {
214 .setsda = falcon_setsdascl,
215 .setscl = falcon_setsdascl,
216 .getsda = falcon_getsda,
217 .getscl = falcon_getscl,
218 .udelay = 100,
219 .mdelay = 10,
220};
221
222/**************************************************************************
223 *
224 * Falcon special buffer handling
225 * Special buffers are used for event queues and the TX and RX
226 * descriptor rings.
227 *
228 *************************************************************************/
229
230/*
231 * Initialise a Falcon special buffer
232 *
233 * This will define a buffer (previously allocated via
234 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
235 * it to be used for event queues, descriptor rings etc.
236 */
237static int
238falcon_init_special_buffer(struct efx_nic *efx,
239 struct efx_special_buffer *buffer)
240{
241 efx_qword_t buf_desc;
242 int index;
243 dma_addr_t dma_addr;
244 int i;
245
246 EFX_BUG_ON_PARANOID(!buffer->addr);
247
248 /* Write buffer descriptors to NIC */
249 for (i = 0; i < buffer->entries; i++) {
250 index = buffer->index + i;
251 dma_addr = buffer->dma_addr + (i * 4096);
252 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
253 index, (unsigned long long)dma_addr);
254 EFX_POPULATE_QWORD_4(buf_desc,
255 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
256 BUF_ADR_REGION, 0,
257 BUF_ADR_FBUF, (dma_addr >> 12),
258 BUF_OWNER_ID_FBUF, 0);
259 falcon_write_sram(efx, &buf_desc, index);
260 }
261
262 return 0;
263}
264
265/* Unmaps a buffer from Falcon and clears the buffer table entries */
266static void
267falcon_fini_special_buffer(struct efx_nic *efx,
268 struct efx_special_buffer *buffer)
269{
270 efx_oword_t buf_tbl_upd;
271 unsigned int start = buffer->index;
272 unsigned int end = (buffer->index + buffer->entries - 1);
273
274 if (!buffer->entries)
275 return;
276
277 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
278 buffer->index, buffer->index + buffer->entries - 1);
279
280 EFX_POPULATE_OWORD_4(buf_tbl_upd,
281 BUF_UPD_CMD, 0,
282 BUF_CLR_CMD, 1,
283 BUF_CLR_END_ID, end,
284 BUF_CLR_START_ID, start);
285 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
286}
287
288/*
289 * Allocate a new Falcon special buffer
290 *
291 * This allocates memory for a new buffer, clears it and allocates a
292 * new buffer ID range. It does not write into Falcon's buffer table.
293 *
294 * This call will allocate 4KB buffers, since Falcon can't use 8KB
295 * buffers for event queues and descriptor rings.
296 */
297static int falcon_alloc_special_buffer(struct efx_nic *efx,
298 struct efx_special_buffer *buffer,
299 unsigned int len)
300{
301 struct falcon_nic_data *nic_data = efx->nic_data;
302
303 len = ALIGN(len, FALCON_BUF_SIZE);
304
305 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
306 &buffer->dma_addr);
307 if (!buffer->addr)
308 return -ENOMEM;
309 buffer->len = len;
310 buffer->entries = len / FALCON_BUF_SIZE;
311 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
312
313 /* All zeros is a potentially valid event so memset to 0xff */
314 memset(buffer->addr, 0xff, len);
315
316 /* Select new buffer ID */
317 buffer->index = nic_data->next_buffer_table;
318 nic_data->next_buffer_table += buffer->entries;
319
320 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
321 "(virt %p phys %lx)\n", buffer->index,
322 buffer->index + buffer->entries - 1,
323 (unsigned long long)buffer->dma_addr, len,
324 buffer->addr, virt_to_phys(buffer->addr));
325
326 return 0;
327}
328
329static void falcon_free_special_buffer(struct efx_nic *efx,
330 struct efx_special_buffer *buffer)
331{
332 if (!buffer->addr)
333 return;
334
335 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
336 "(virt %p phys %lx)\n", buffer->index,
337 buffer->index + buffer->entries - 1,
338 (unsigned long long)buffer->dma_addr, buffer->len,
339 buffer->addr, virt_to_phys(buffer->addr));
340
341 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
342 buffer->dma_addr);
343 buffer->addr = NULL;
344 buffer->entries = 0;
345}
346
347/**************************************************************************
348 *
349 * Falcon generic buffer handling
350 * These buffers are used for interrupt status and MAC stats
351 *
352 **************************************************************************/
353
354static int falcon_alloc_buffer(struct efx_nic *efx,
355 struct efx_buffer *buffer, unsigned int len)
356{
357 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
358 &buffer->dma_addr);
359 if (!buffer->addr)
360 return -ENOMEM;
361 buffer->len = len;
362 memset(buffer->addr, 0, len);
363 return 0;
364}
365
366static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
367{
368 if (buffer->addr) {
369 pci_free_consistent(efx->pci_dev, buffer->len,
370 buffer->addr, buffer->dma_addr);
371 buffer->addr = NULL;
372 }
373}
374
375/**************************************************************************
376 *
377 * Falcon TX path
378 *
379 **************************************************************************/
380
381/* Returns a pointer to the specified transmit descriptor in the TX
382 * descriptor queue belonging to the specified channel.
383 */
384static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
385 unsigned int index)
386{
387 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
388}
389
390/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
391static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
392{
393 unsigned write_ptr;
394 efx_dword_t reg;
395
396 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
397 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
398 falcon_writel_page(tx_queue->efx, &reg,
399 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
400}
401
402
403/* For each entry inserted into the software descriptor ring, create a
404 * descriptor in the hardware TX descriptor ring (in host memory), and
405 * write a doorbell.
406 */
407void falcon_push_buffers(struct efx_tx_queue *tx_queue)
408{
409
410 struct efx_tx_buffer *buffer;
411 efx_qword_t *txd;
412 unsigned write_ptr;
413
414 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
415
416 do {
417 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
418 buffer = &tx_queue->buffer[write_ptr];
419 txd = falcon_tx_desc(tx_queue, write_ptr);
420 ++tx_queue->write_count;
421
422 /* Create TX descriptor ring entry */
423 EFX_POPULATE_QWORD_5(*txd,
424 TX_KER_PORT, 0,
425 TX_KER_CONT, buffer->continuation,
426 TX_KER_BYTE_CNT, buffer->len,
427 TX_KER_BUF_REGION, 0,
428 TX_KER_BUF_ADR, buffer->dma_addr);
429 } while (tx_queue->write_count != tx_queue->insert_count);
430
431 wmb(); /* Ensure descriptors are written before they are fetched */
432 falcon_notify_tx_desc(tx_queue);
433}
434
435/* Allocate hardware resources for a TX queue */
436int falcon_probe_tx(struct efx_tx_queue *tx_queue)
437{
438 struct efx_nic *efx = tx_queue->efx;
439 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
440 FALCON_TXD_RING_SIZE *
441 sizeof(efx_qword_t));
442}
443
444int falcon_init_tx(struct efx_tx_queue *tx_queue)
445{
446 efx_oword_t tx_desc_ptr;
447 struct efx_nic *efx = tx_queue->efx;
448 int rc;
449
450 /* Pin TX descriptor ring */
451 rc = falcon_init_special_buffer(efx, &tx_queue->txd);
452 if (rc)
453 return rc;
454
455 /* Push TX descriptor ring to card */
456 EFX_POPULATE_OWORD_10(tx_desc_ptr,
457 TX_DESCQ_EN, 1,
458 TX_ISCSI_DDIG_EN, 0,
459 TX_ISCSI_HDIG_EN, 0,
460 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
461 TX_DESCQ_EVQ_ID, tx_queue->channel->evqnum,
462 TX_DESCQ_OWNER_ID, 0,
463 TX_DESCQ_LABEL, tx_queue->queue,
464 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
465 TX_DESCQ_TYPE, 0,
466 TX_NON_IP_DROP_DIS_B0, 1);
467
468 if (FALCON_REV(efx) >= FALCON_REV_B0) {
469 int csum = !(efx->net_dev->features & NETIF_F_IP_CSUM);
470 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, csum);
471 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, csum);
472 }
473
474 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
475 tx_queue->queue);
476
477 if (FALCON_REV(efx) < FALCON_REV_B0) {
478 efx_oword_t reg;
479
480 BUG_ON(tx_queue->queue >= 128); /* HW limit */
481
482 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
483 if (efx->net_dev->features & NETIF_F_IP_CSUM)
484 clear_bit_le(tx_queue->queue, (void *)&reg);
485 else
486 set_bit_le(tx_queue->queue, (void *)&reg);
487 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
488 }
489
490 return 0;
491}
492
493static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
494{
495 struct efx_nic *efx = tx_queue->efx;
496 struct efx_channel *channel = &efx->channel[0];
497 efx_oword_t tx_flush_descq;
498 unsigned int read_ptr, i;
499
500 /* Post a flush command */
501 EFX_POPULATE_OWORD_2(tx_flush_descq,
502 TX_FLUSH_DESCQ_CMD, 1,
503 TX_FLUSH_DESCQ, tx_queue->queue);
504 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
505 msleep(FALCON_FLUSH_TIMEOUT);
506
507 if (EFX_WORKAROUND_7803(efx))
508 return 0;
509
510 /* Look for a flush completed event */
511 read_ptr = channel->eventq_read_ptr;
512 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
513 efx_qword_t *event = falcon_event(channel, read_ptr);
514 int ev_code, ev_sub_code, ev_queue;
515 if (!falcon_event_present(event))
516 break;
517
518 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
519 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
520 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
521 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
522 (ev_queue == tx_queue->queue)) {
523 EFX_LOG(efx, "tx queue %d flush command succesful\n",
524 tx_queue->queue);
525 return 0;
526 }
527
528 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
529 }
530
531 if (EFX_WORKAROUND_11557(efx)) {
532 efx_oword_t reg;
533 int enabled;
534
535 falcon_read_table(efx, &reg, efx->type->txd_ptr_tbl_base,
536 tx_queue->queue);
537 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
538 if (!enabled) {
539 EFX_LOG(efx, "tx queue %d disabled without a "
540 "flush event seen\n", tx_queue->queue);
541 return 0;
542 }
543 }
544
545 EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
546 return -ETIMEDOUT;
547}
548
549void falcon_fini_tx(struct efx_tx_queue *tx_queue)
550{
551 struct efx_nic *efx = tx_queue->efx;
552 efx_oword_t tx_desc_ptr;
553
554 /* Stop the hardware using the queue */
555 if (falcon_flush_tx_queue(tx_queue))
556 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
557
558 /* Remove TX descriptor ring from card */
559 EFX_ZERO_OWORD(tx_desc_ptr);
560 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
561 tx_queue->queue);
562
563 /* Unpin TX descriptor ring */
564 falcon_fini_special_buffer(efx, &tx_queue->txd);
565}
566
567/* Free buffers backing TX queue */
568void falcon_remove_tx(struct efx_tx_queue *tx_queue)
569{
570 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
571}
572
573/**************************************************************************
574 *
575 * Falcon RX path
576 *
577 **************************************************************************/
578
579/* Returns a pointer to the specified descriptor in the RX descriptor queue */
580static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
581 unsigned int index)
582{
583 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
584}
585
586/* This creates an entry in the RX descriptor queue */
587static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
588 unsigned index)
589{
590 struct efx_rx_buffer *rx_buf;
591 efx_qword_t *rxd;
592
593 rxd = falcon_rx_desc(rx_queue, index);
594 rx_buf = efx_rx_buffer(rx_queue, index);
595 EFX_POPULATE_QWORD_3(*rxd,
596 RX_KER_BUF_SIZE,
597 rx_buf->len -
598 rx_queue->efx->type->rx_buffer_padding,
599 RX_KER_BUF_REGION, 0,
600 RX_KER_BUF_ADR, rx_buf->dma_addr);
601}
602
603/* This writes to the RX_DESC_WPTR register for the specified receive
604 * descriptor ring.
605 */
606void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
607{
608 efx_dword_t reg;
609 unsigned write_ptr;
610
611 while (rx_queue->notified_count != rx_queue->added_count) {
612 falcon_build_rx_desc(rx_queue,
613 rx_queue->notified_count &
614 FALCON_RXD_RING_MASK);
615 ++rx_queue->notified_count;
616 }
617
618 wmb();
619 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
620 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
621 falcon_writel_page(rx_queue->efx, &reg,
622 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
623}
624
625int falcon_probe_rx(struct efx_rx_queue *rx_queue)
626{
627 struct efx_nic *efx = rx_queue->efx;
628 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
629 FALCON_RXD_RING_SIZE *
630 sizeof(efx_qword_t));
631}
632
633int falcon_init_rx(struct efx_rx_queue *rx_queue)
634{
635 efx_oword_t rx_desc_ptr;
636 struct efx_nic *efx = rx_queue->efx;
637 int rc;
638 int is_b0 = FALCON_REV(efx) >= FALCON_REV_B0;
639 int iscsi_digest_en = is_b0;
640
641 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
642 rx_queue->queue, rx_queue->rxd.index,
643 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
644
645 /* Pin RX descriptor ring */
646 rc = falcon_init_special_buffer(efx, &rx_queue->rxd);
647 if (rc)
648 return rc;
649
650 /* Push RX descriptor ring to card */
651 EFX_POPULATE_OWORD_10(rx_desc_ptr,
652 RX_ISCSI_DDIG_EN, iscsi_digest_en,
653 RX_ISCSI_HDIG_EN, iscsi_digest_en,
654 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
655 RX_DESCQ_EVQ_ID, rx_queue->channel->evqnum,
656 RX_DESCQ_OWNER_ID, 0,
657 RX_DESCQ_LABEL, rx_queue->queue,
658 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
659 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
660 /* For >=B0 this is scatter so disable */
661 RX_DESCQ_JUMBO, !is_b0,
662 RX_DESCQ_EN, 1);
663 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
664 rx_queue->queue);
665 return 0;
666}
667
668static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
669{
670 struct efx_nic *efx = rx_queue->efx;
671 struct efx_channel *channel = &efx->channel[0];
672 unsigned int read_ptr, i;
673 efx_oword_t rx_flush_descq;
674
675 /* Post a flush command */
676 EFX_POPULATE_OWORD_2(rx_flush_descq,
677 RX_FLUSH_DESCQ_CMD, 1,
678 RX_FLUSH_DESCQ, rx_queue->queue);
679 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
680 msleep(FALCON_FLUSH_TIMEOUT);
681
682 if (EFX_WORKAROUND_7803(efx))
683 return 0;
684
685 /* Look for a flush completed event */
686 read_ptr = channel->eventq_read_ptr;
687 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
688 efx_qword_t *event = falcon_event(channel, read_ptr);
689 int ev_code, ev_sub_code, ev_queue, ev_failed;
690 if (!falcon_event_present(event))
691 break;
692
693 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
694 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
695 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
696 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
697
698 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
699 (ev_queue == rx_queue->queue)) {
700 if (ev_failed) {
701 EFX_INFO(efx, "rx queue %d flush command "
702 "failed\n", rx_queue->queue);
703 return -EAGAIN;
704 } else {
705 EFX_LOG(efx, "rx queue %d flush command "
706 "succesful\n", rx_queue->queue);
707 return 0;
708 }
709 }
710
711 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
712 }
713
714 if (EFX_WORKAROUND_11557(efx)) {
715 efx_oword_t reg;
716 int enabled;
717
718 falcon_read_table(efx, &reg, efx->type->rxd_ptr_tbl_base,
719 rx_queue->queue);
720 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
721 if (!enabled) {
722 EFX_LOG(efx, "rx queue %d disabled without a "
723 "flush event seen\n", rx_queue->queue);
724 return 0;
725 }
726 }
727
728 EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
729 return -ETIMEDOUT;
730}
731
732void falcon_fini_rx(struct efx_rx_queue *rx_queue)
733{
734 efx_oword_t rx_desc_ptr;
735 struct efx_nic *efx = rx_queue->efx;
736 int i, rc;
737
738 /* Try and flush the rx queue. This may need to be repeated */
739 for (i = 0; i < 5; i++) {
740 rc = falcon_flush_rx_queue(rx_queue);
741 if (rc == -EAGAIN)
742 continue;
743 break;
744 }
745 if (rc)
746 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
747
748 /* Remove RX descriptor ring from card */
749 EFX_ZERO_OWORD(rx_desc_ptr);
750 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
751 rx_queue->queue);
752
753 /* Unpin RX descriptor ring */
754 falcon_fini_special_buffer(efx, &rx_queue->rxd);
755}
756
757/* Free buffers backing RX queue */
758void falcon_remove_rx(struct efx_rx_queue *rx_queue)
759{
760 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
761}
762
763/**************************************************************************
764 *
765 * Falcon event queue processing
766 * Event queues are processed by per-channel tasklets.
767 *
768 **************************************************************************/
769
770/* Update a channel's event queue's read pointer (RPTR) register
771 *
772 * This writes the EVQ_RPTR_REG register for the specified channel's
773 * event queue.
774 *
775 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
776 * whereas channel->eventq_read_ptr contains the index of the "next to
777 * read" event.
778 */
779void falcon_eventq_read_ack(struct efx_channel *channel)
780{
781 efx_dword_t reg;
782 struct efx_nic *efx = channel->efx;
783
784 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
785 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
786 channel->evqnum);
787}
788
789/* Use HW to insert a SW defined event */
790void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
791{
792 efx_oword_t drv_ev_reg;
793
794 EFX_POPULATE_OWORD_2(drv_ev_reg,
795 DRV_EV_QID, channel->evqnum,
796 DRV_EV_DATA,
797 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
798 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
799}
800
801/* Handle a transmit completion event
802 *
803 * Falcon batches TX completion events; the message we receive is of
804 * the form "complete all TX events up to this index".
805 */
806static inline void falcon_handle_tx_event(struct efx_channel *channel,
807 efx_qword_t *event)
808{
809 unsigned int tx_ev_desc_ptr;
810 unsigned int tx_ev_q_label;
811 struct efx_tx_queue *tx_queue;
812 struct efx_nic *efx = channel->efx;
813
814 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
815 /* Transmit completion */
816 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
817 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
818 tx_queue = &efx->tx_queue[tx_ev_q_label];
819 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
820 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
821 /* Rewrite the FIFO write pointer */
822 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
823 tx_queue = &efx->tx_queue[tx_ev_q_label];
824
825 if (NET_DEV_REGISTERED(efx))
826 netif_tx_lock(efx->net_dev);
827 falcon_notify_tx_desc(tx_queue);
828 if (NET_DEV_REGISTERED(efx))
829 netif_tx_unlock(efx->net_dev);
830 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
831 EFX_WORKAROUND_10727(efx)) {
832 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
833 } else {
834 EFX_ERR(efx, "channel %d unexpected TX event "
835 EFX_QWORD_FMT"\n", channel->channel,
836 EFX_QWORD_VAL(*event));
837 }
838}
839
840/* Check received packet's destination MAC address. */
841static int check_dest_mac(struct efx_rx_queue *rx_queue,
842 const efx_qword_t *event)
843{
844 struct efx_rx_buffer *rx_buf;
845 struct efx_nic *efx = rx_queue->efx;
846 int rx_ev_desc_ptr;
847 struct ethhdr *eh;
848
849 if (efx->promiscuous)
850 return 1;
851
852 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
853 rx_buf = efx_rx_buffer(rx_queue, rx_ev_desc_ptr);
854 eh = (struct ethhdr *)rx_buf->data;
855 if (memcmp(eh->h_dest, efx->net_dev->dev_addr, ETH_ALEN))
856 return 0;
857 return 1;
858}
859
860/* Detect errors included in the rx_evt_pkt_ok bit. */
861static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
862 const efx_qword_t *event,
863 unsigned *rx_ev_pkt_ok,
864 int *discard, int byte_count)
865{
866 struct efx_nic *efx = rx_queue->efx;
867 unsigned rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
868 unsigned rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
869 unsigned rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
870 unsigned rx_ev_pkt_type, rx_ev_other_err, rx_ev_pause_frm;
871 unsigned rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
872 int snap, non_ip;
873
874 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
875 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
876 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
877 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
878 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
879 RX_EV_BUF_OWNER_ID_ERR);
880 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
881 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
882 RX_EV_IP_HDR_CHKSUM_ERR);
883 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
884 RX_EV_TCP_UDP_CHKSUM_ERR);
885 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
886 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
887 rx_ev_drib_nib = ((FALCON_REV(efx) >= FALCON_REV_B0) ?
888 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
889 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
890
891 /* Every error apart from tobe_disc and pause_frm */
892 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
893 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
894 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
895
896 snap = (rx_ev_pkt_type == RX_EV_PKT_TYPE_LLC_DECODE) ||
897 (rx_ev_pkt_type == RX_EV_PKT_TYPE_VLAN_LLC_DECODE);
898 non_ip = (rx_ev_hdr_type == RX_EV_HDR_TYPE_NON_IP_DECODE);
899
900 /* SFC bug 5475/8970: The Falcon XMAC incorrectly calculates the
901 * length field of an LLC frame, which sets TOBE_DISC. We could set
902 * PASS_LEN_ERR, but we want the MAC to filter out short frames (to
903 * protect the RX block).
904 *
905 * bug5475 - LLC/SNAP: Falcon identifies SNAP packets.
906 * bug8970 - LLC/noSNAP: Falcon does not provide an LLC flag.
907 * LLC can't encapsulate IP, so by definition
908 * these packets are NON_IP.
909 *
910 * Unicast mismatch will also cause TOBE_DISC, so the driver needs
911 * to check this.
912 */
913 if (EFX_WORKAROUND_5475(efx) && rx_ev_tobe_disc && (snap || non_ip)) {
914 /* If all the other flags are zero then we can state the
915 * entire packet is ok, which will flag to the kernel not
916 * to recalculate checksums.
917 */
918 if (!(non_ip | rx_ev_other_err | rx_ev_pause_frm))
919 *rx_ev_pkt_ok = 1;
920
921 rx_ev_tobe_disc = 0;
922
923 /* TOBE_DISC is set for unicast mismatch. But given that
924 * we can't trust TOBE_DISC here, we must validate the dest
925 * MAC address ourselves.
926 */
927 if (!rx_ev_mcast_pkt && !check_dest_mac(rx_queue, event))
928 rx_ev_tobe_disc = 1;
929 }
930
931 /* Count errors that are not in MAC stats. */
932 if (rx_ev_frm_trunc)
933 ++rx_queue->channel->n_rx_frm_trunc;
934 else if (rx_ev_tobe_disc)
935 ++rx_queue->channel->n_rx_tobe_disc;
936 else if (rx_ev_ip_hdr_chksum_err)
937 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
938 else if (rx_ev_tcp_udp_chksum_err)
939 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
940 if (rx_ev_ip_frag_err)
941 ++rx_queue->channel->n_rx_ip_frag_err;
942
943 /* The frame must be discarded if any of these are true. */
944 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
945 rx_ev_tobe_disc | rx_ev_pause_frm);
946
947 /* TOBE_DISC is expected on unicast mismatches; don't print out an
948 * error message. FRM_TRUNC indicates RXDP dropped the packet due
949 * to a FIFO overflow.
950 */
951#ifdef EFX_ENABLE_DEBUG
952 if (rx_ev_other_err) {
953 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
954 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s%s\n",
955 rx_queue->queue, EFX_QWORD_VAL(*event),
956 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
957 rx_ev_ip_hdr_chksum_err ?
958 " [IP_HDR_CHKSUM_ERR]" : "",
959 rx_ev_tcp_udp_chksum_err ?
960 " [TCP_UDP_CHKSUM_ERR]" : "",
961 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
962 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
963 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
964 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
965 rx_ev_pause_frm ? " [PAUSE]" : "",
966 snap ? " [SNAP/LLC]" : "");
967 }
968#endif
969
970 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
971 efx->phy_type == PHY_TYPE_10XPRESS))
972 tenxpress_crc_err(efx);
973}
974
975/* Handle receive events that are not in-order. */
976static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
977 unsigned index)
978{
979 struct efx_nic *efx = rx_queue->efx;
980 unsigned expected, dropped;
981
982 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
983 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
984 FALCON_RXD_RING_MASK);
985 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
986 dropped, index, expected);
987
988 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
989 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
990}
991
992/* Handle a packet received event
993 *
994 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
995 * wrong destination address
996 * Also "is multicast" and "matches multicast filter" flags can be used to
997 * discard non-matching multicast packets.
998 */
999static inline int falcon_handle_rx_event(struct efx_channel *channel,
1000 const efx_qword_t *event)
1001{
1002 unsigned int rx_ev_q_label, rx_ev_desc_ptr, rx_ev_byte_cnt;
1003 unsigned int rx_ev_pkt_ok, rx_ev_hdr_type, rx_ev_mcast_pkt;
1004 unsigned expected_ptr;
1005 int discard = 0, checksummed;
1006 struct efx_rx_queue *rx_queue;
1007 struct efx_nic *efx = channel->efx;
1008
1009 /* Basic packet information */
1010 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
1011 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
1012 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
1013 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
1014 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
1015
1016 rx_ev_q_label = EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL);
1017 rx_queue = &efx->rx_queue[rx_ev_q_label];
1018
1019 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
1020 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
1021 if (unlikely(rx_ev_desc_ptr != expected_ptr)) {
1022 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
1023 return rx_ev_q_label;
1024 }
1025
1026 if (likely(rx_ev_pkt_ok)) {
1027 /* If packet is marked as OK and packet type is TCP/IPv4 or
1028 * UDP/IPv4, then we can rely on the hardware checksum.
1029 */
1030 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
1031 } else {
1032 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
1033 &discard, rx_ev_byte_cnt);
1034 checksummed = 0;
1035 }
1036
1037 /* Detect multicast packets that didn't match the filter */
1038 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
1039 if (rx_ev_mcast_pkt) {
1040 unsigned int rx_ev_mcast_hash_match =
1041 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
1042
1043 if (unlikely(!rx_ev_mcast_hash_match))
1044 discard = 1;
1045 }
1046
1047 /* Handle received packet */
1048 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
1049 checksummed, discard);
1050
1051 return rx_ev_q_label;
1052}
1053
1054/* Global events are basically PHY events */
1055static void falcon_handle_global_event(struct efx_channel *channel,
1056 efx_qword_t *event)
1057{
1058 struct efx_nic *efx = channel->efx;
1059 int is_phy_event = 0, handled = 0;
1060
1061 /* Check for interrupt on either port. Some boards have a
1062 * single PHY wired to the interrupt line for port 1. */
1063 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1064 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1065 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
1066 is_phy_event = 1;
1067
1068 if ((FALCON_REV(efx) >= FALCON_REV_B0) &&
1069 EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
1070 is_phy_event = 1;
1071
1072 if (is_phy_event) {
1073 efx->phy_op->clear_interrupt(efx);
1074 queue_work(efx->workqueue, &efx->reconfigure_work);
1075 handled = 1;
1076 }
1077
1078 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1079 EFX_ERR(efx, "channel %d seen global RX_RESET "
1080 "event. Resetting.\n", channel->channel);
1081
1082 atomic_inc(&efx->rx_reset);
1083 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1084 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1085 handled = 1;
1086 }
1087
1088 if (!handled)
1089 EFX_ERR(efx, "channel %d unknown global event "
1090 EFX_QWORD_FMT "\n", channel->channel,
1091 EFX_QWORD_VAL(*event));
1092}
1093
1094static void falcon_handle_driver_event(struct efx_channel *channel,
1095 efx_qword_t *event)
1096{
1097 struct efx_nic *efx = channel->efx;
1098 unsigned int ev_sub_code;
1099 unsigned int ev_sub_data;
1100
1101 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1102 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1103
1104 switch (ev_sub_code) {
1105 case TX_DESCQ_FLS_DONE_EV_DECODE:
1106 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1107 channel->channel, ev_sub_data);
1108 break;
1109 case RX_DESCQ_FLS_DONE_EV_DECODE:
1110 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1111 channel->channel, ev_sub_data);
1112 break;
1113 case EVQ_INIT_DONE_EV_DECODE:
1114 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1115 channel->channel, ev_sub_data);
1116 break;
1117 case SRM_UPD_DONE_EV_DECODE:
1118 EFX_TRACE(efx, "channel %d SRAM update done\n",
1119 channel->channel);
1120 break;
1121 case WAKE_UP_EV_DECODE:
1122 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1123 channel->channel, ev_sub_data);
1124 break;
1125 case TIMER_EV_DECODE:
1126 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1127 channel->channel, ev_sub_data);
1128 break;
1129 case RX_RECOVERY_EV_DECODE:
1130 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1131 "Resetting.\n", channel->channel);
05e3ec04 1132 atomic_inc(&efx->rx_reset);
8ceee660
BH		 1133 efx_schedule_reset(efx,
1134 EFX_WORKAROUND_6555(efx) ?
1135 RESET_TYPE_RX_RECOVERY :
1136 RESET_TYPE_DISABLE);
1137 break;
1138 case RX_DSC_ERROR_EV_DECODE:
1139 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1140 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1141 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1142 break;
1143 case TX_DSC_ERROR_EV_DECODE:
1144 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1145 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1146 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1147 break;
1148 default:
1149 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1150 "data %04x\n", channel->channel, ev_sub_code,
1151 ev_sub_data);
1152 break;
1153 }
1154}
1155
1156int falcon_process_eventq(struct efx_channel *channel, int *rx_quota)
1157{
1158 unsigned int read_ptr;
1159 efx_qword_t event, *p_event;
1160 int ev_code;
1161 int rxq;
1162 int rxdmaqs = 0;
1163
1164 read_ptr = channel->eventq_read_ptr;
1165
1166 do {
1167 p_event = falcon_event(channel, read_ptr);
1168 event = *p_event;
1169
1170 if (!falcon_event_present(&event))
1171 /* End of events */
1172 break;
1173
1174 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1175 channel->channel, EFX_QWORD_VAL(event));
1176
1177 /* Clear this event by marking it all ones */
1178 EFX_SET_QWORD(*p_event);
1179
1180 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1181
1182 switch (ev_code) {
1183 case RX_IP_EV_DECODE:
1184 rxq = falcon_handle_rx_event(channel, &event);
1185 rxdmaqs |= (1 << rxq);
1186 (*rx_quota)--;
1187 break;
1188 case TX_IP_EV_DECODE:
1189 falcon_handle_tx_event(channel, &event);
1190 break;
1191 case DRV_GEN_EV_DECODE:
1192 channel->eventq_magic
1193 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1194 EFX_LOG(channel->efx, "channel %d received generated "
1195 "event "EFX_QWORD_FMT"\n", channel->channel,
1196 EFX_QWORD_VAL(event));
1197 break;
1198 case GLOBAL_EV_DECODE:
1199 falcon_handle_global_event(channel, &event);
1200 break;
1201 case DRIVER_EV_DECODE:
1202 falcon_handle_driver_event(channel, &event);
1203 break;
1204 default:
1205 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1206 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1207 ev_code, EFX_QWORD_VAL(event));
1208 }
1209
1210 /* Increment read pointer */
1211 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1212
1213 } while (*rx_quota);
1214
1215 channel->eventq_read_ptr = read_ptr;
1216 return rxdmaqs;
1217}
1218
1219void falcon_set_int_moderation(struct efx_channel *channel)
1220{
1221 efx_dword_t timer_cmd;
1222 struct efx_nic *efx = channel->efx;
1223
1224 /* Set timer register */
1225 if (channel->irq_moderation) {
1226 /* Round to resolution supported by hardware. The value we
1227 * program is based at 0. So actual interrupt moderation
1228 * achieved is ((x + 1) * res).
1229 */
1230 unsigned int res = 5;
1231 channel->irq_moderation -= (channel->irq_moderation % res);
1232 if (channel->irq_moderation < res)
1233 channel->irq_moderation = res;
1234 EFX_POPULATE_DWORD_2(timer_cmd,
1235 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1236 TIMER_VAL,
1237 (channel->irq_moderation / res) - 1);
1238 } else {
1239 EFX_POPULATE_DWORD_2(timer_cmd,
1240 TIMER_MODE, TIMER_MODE_DIS,
1241 TIMER_VAL, 0);
1242 }
1243 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1244 channel->evqnum);
1245
1246}
1247
1248/* Allocate buffer table entries for event queue */
1249int falcon_probe_eventq(struct efx_channel *channel)
1250{
1251 struct efx_nic *efx = channel->efx;
1252 unsigned int evq_size;
1253
1254 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1255 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1256}
1257
1258int falcon_init_eventq(struct efx_channel *channel)
1259{
1260 efx_oword_t evq_ptr;
1261 struct efx_nic *efx = channel->efx;
1262 int rc;
1263
1264 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1265 channel->channel, channel->eventq.index,
1266 channel->eventq.index + channel->eventq.entries - 1);
1267
1268 /* Pin event queue buffer */
1269 rc = falcon_init_special_buffer(efx, &channel->eventq);
1270 if (rc)
1271 return rc;
1272
1273 /* Fill event queue with all ones (i.e. empty events) */
1274 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1275
1276 /* Push event queue to card */
1277 EFX_POPULATE_OWORD_3(evq_ptr,
1278 EVQ_EN, 1,
1279 EVQ_SIZE, FALCON_EVQ_ORDER,
1280 EVQ_BUF_BASE_ID, channel->eventq.index);
1281 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1282 channel->evqnum);
1283
1284 falcon_set_int_moderation(channel);
1285
1286 return 0;
1287}
1288
1289void falcon_fini_eventq(struct efx_channel *channel)
1290{
1291 efx_oword_t eventq_ptr;
1292 struct efx_nic *efx = channel->efx;
1293
1294 /* Remove event queue from card */
1295 EFX_ZERO_OWORD(eventq_ptr);
1296 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1297 channel->evqnum);
1298
1299 /* Unpin event queue */
1300 falcon_fini_special_buffer(efx, &channel->eventq);
1301}
1302
1303/* Free buffers backing event queue */
1304void falcon_remove_eventq(struct efx_channel *channel)
1305{
1306 falcon_free_special_buffer(channel->efx, &channel->eventq);
1307}
1308
1309
1310/* Generates a test event on the event queue. A subsequent call to
1311 * process_eventq() should pick up the event and place the value of
1312 * "magic" into channel->eventq_magic;
1313 */
1314void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1315{
1316 efx_qword_t test_event;
1317
1318 EFX_POPULATE_QWORD_2(test_event,
1319 EV_CODE, DRV_GEN_EV_DECODE,
1320 EVQ_MAGIC, magic);
1321 falcon_generate_event(channel, &test_event);
1322}
1323
1324
1325/**************************************************************************
1326 *
1327 * Falcon hardware interrupts
1328 * The hardware interrupt handler does very little work; all the event
1329 * queue processing is carried out by per-channel tasklets.
1330 *
1331 **************************************************************************/
1332
1333/* Enable/disable/generate Falcon interrupts */
1334static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1335 int force)
1336{
1337 efx_oword_t int_en_reg_ker;
1338
1339 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1340 KER_INT_KER, force,
1341 DRV_INT_EN_KER, enabled);
1342 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1343}
1344
1345void falcon_enable_interrupts(struct efx_nic *efx)
1346{
1347 efx_oword_t int_adr_reg_ker;
1348 struct efx_channel *channel;
1349
1350 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1351 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1352
1353 /* Program address */
1354 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1355 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1356 INT_ADR_KER, efx->irq_status.dma_addr);
1357 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1358
1359 /* Enable interrupts */
1360 falcon_interrupts(efx, 1, 0);
1361
1362 /* Force processing of all the channels to get the EVQ RPTRs up to
1363 date */
1364 efx_for_each_channel_with_interrupt(channel, efx)
1365 efx_schedule_channel(channel);
1366}
1367
1368void falcon_disable_interrupts(struct efx_nic *efx)
1369{
1370 /* Disable interrupts */
1371 falcon_interrupts(efx, 0, 0);
1372}
1373
1374/* Generate a Falcon test interrupt
1375 * Interrupt must already have been enabled, otherwise nasty things
1376 * may happen.
1377 */
1378void falcon_generate_interrupt(struct efx_nic *efx)
1379{
1380 falcon_interrupts(efx, 1, 1);
1381}
1382
1383/* Acknowledge a legacy interrupt from Falcon
1384 *
1385 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1386 *
1387 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1388 * BIU. Interrupt acknowledge is read sensitive so must write instead
1389 * (then read to ensure the BIU collector is flushed)
1390 *
1391 * NB most hardware supports MSI interrupts
1392 */
1393static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1394{
1395 efx_dword_t reg;
1396
1397 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1398 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1399 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1400}
1401
1402/* Process a fatal interrupt
1403 * Disable bus mastering ASAP and schedule a reset
1404 */
1405static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1406{
1407 struct falcon_nic_data *nic_data = efx->nic_data;
1408 efx_oword_t *int_ker = (efx_oword_t *) efx->irq_status.addr;
1409 efx_oword_t fatal_intr;
1410 int error, mem_perr;
1411 static int n_int_errors;
1412
1413 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1414 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1415
1416 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1417 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1418 EFX_OWORD_VAL(fatal_intr),
1419 error ? "disabling bus mastering" : "no recognised error");
1420 if (error == 0)
1421 goto out;
1422
1423 /* If this is a memory parity error dump which blocks are offending */
1424 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1425 if (mem_perr) {
1426 efx_oword_t reg;
1427 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1428 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1429 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1430 }
1431
1432 /* Disable DMA bus mastering on both devices */
1433 pci_disable_device(efx->pci_dev);
1434 if (FALCON_IS_DUAL_FUNC(efx))
1435 pci_disable_device(nic_data->pci_dev2);
1436
1437 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1438 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1439 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1440 } else {
1441 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1442 "NIC will be disabled\n");
1443 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1444 }
1445out:
1446 return IRQ_HANDLED;
1447}
1448
1449/* Handle a legacy interrupt from Falcon
1450 * Acknowledges the interrupt and schedule event queue processing.
1451 */
1452static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1453{
1454 struct efx_nic *efx = (struct efx_nic *)dev_id;
1455 efx_oword_t *int_ker = (efx_oword_t *) efx->irq_status.addr;
1456 struct efx_channel *channel;
1457 efx_dword_t reg;
1458 u32 queues;
1459 int syserr;
1460
1461 /* Read the ISR which also ACKs the interrupts */
1462 falcon_readl(efx, &reg, INT_ISR0_B0);
1463 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1464
1465 /* Check to see if we have a serious error condition */
1466 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1467 if (unlikely(syserr))
1468 return falcon_fatal_interrupt(efx);
1469
1470 if (queues == 0)
1471 return IRQ_NONE;
1472
1473 efx->last_irq_cpu = raw_smp_processor_id();
1474 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1475 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1476
1477 /* Schedule processing of any interrupting queues */
1478 channel = &efx->channel[0];
1479 while (queues) {
1480 if (queues & 0x01)
1481 efx_schedule_channel(channel);
1482 channel++;
1483 queues >>= 1;
1484 }
1485
1486 return IRQ_HANDLED;
1487}
1488
1489
1490static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1491{
1492 struct efx_nic *efx = (struct efx_nic *)dev_id;
1493 efx_oword_t *int_ker = (efx_oword_t *) efx->irq_status.addr;
1494 struct efx_channel *channel;
1495 int syserr;
1496 int queues;
1497
1498 /* Check to see if this is our interrupt. If it isn't, we
1499 * exit without having touched the hardware.
1500 */
1501 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1502 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1503 raw_smp_processor_id());
1504 return IRQ_NONE;
1505 }
1506 efx->last_irq_cpu = raw_smp_processor_id();
1507 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1508 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1509
1510 /* Check to see if we have a serious error condition */
1511 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1512 if (unlikely(syserr))
1513 return falcon_fatal_interrupt(efx);
1514
1515 /* Determine interrupting queues, clear interrupt status
1516 * register and acknowledge the device interrupt.
1517 */
1518 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1519 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1520 EFX_ZERO_OWORD(*int_ker);
1521 wmb(); /* Ensure the vector is cleared before interrupt ack */
1522 falcon_irq_ack_a1(efx);
1523
1524 /* Schedule processing of any interrupting queues */
1525 channel = &efx->channel[0];
1526 while (queues) {
1527 if (queues & 0x01)
1528 efx_schedule_channel(channel);
1529 channel++;
1530 queues >>= 1;
1531 }
1532
1533 return IRQ_HANDLED;
1534}
1535
1536/* Handle an MSI interrupt from Falcon
1537 *
1538 * Handle an MSI hardware interrupt. This routine schedules event
1539 * queue processing. No interrupt acknowledgement cycle is necessary.
1540 * Also, we never need to check that the interrupt is for us, since
1541 * MSI interrupts cannot be shared.
1542 */
1543static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1544{
1545 struct efx_channel *channel = (struct efx_channel *)dev_id;
1546 struct efx_nic *efx = channel->efx;
1547 efx_oword_t *int_ker = (efx_oword_t *) efx->irq_status.addr;
1548 int syserr;
1549
1550 efx->last_irq_cpu = raw_smp_processor_id();
1551 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1552 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1553
1554 /* Check to see if we have a serious error condition */
1555 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1556 if (unlikely(syserr))
1557 return falcon_fatal_interrupt(efx);
1558
1559 /* Schedule processing of the channel */
1560 efx_schedule_channel(channel);
1561
1562 return IRQ_HANDLED;
1563}
1564
1565
1566/* Setup RSS indirection table.
1567 * This maps from the hash value of the packet to RXQ
1568 */
1569static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1570{
1571 int i = 0;
1572 unsigned long offset;
1573 efx_dword_t dword;
1574
1575 if (FALCON_REV(efx) < FALCON_REV_B0)
1576 return;
1577
1578 for (offset = RX_RSS_INDIR_TBL_B0;
1579 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1580 offset += 0x10) {
1581 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1582 i % efx->rss_queues);
1583 falcon_writel(efx, &dword, offset);
1584 i++;
1585 }
1586}
1587
1588/* Hook interrupt handler(s)
1589 * Try MSI and then legacy interrupts.
1590 */
1591int falcon_init_interrupt(struct efx_nic *efx)
1592{
1593 struct efx_channel *channel;
1594 int rc;
1595
1596 if (!EFX_INT_MODE_USE_MSI(efx)) {
1597 irq_handler_t handler;
1598 if (FALCON_REV(efx) >= FALCON_REV_B0)
1599 handler = falcon_legacy_interrupt_b0;
1600 else
1601 handler = falcon_legacy_interrupt_a1;
1602
1603 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1604 efx->name, efx);
1605 if (rc) {
1606 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1607 efx->pci_dev->irq);
1608 goto fail1;
1609 }
1610 return 0;
1611 }
1612
1613 /* Hook MSI or MSI-X interrupt */
1614 efx_for_each_channel_with_interrupt(channel, efx) {
1615 rc = request_irq(channel->irq, falcon_msi_interrupt,
1616 IRQF_PROBE_SHARED, /* Not shared */
1617 efx->name, channel);
1618 if (rc) {
1619 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1620 goto fail2;
1621 }
1622 }
1623
1624 return 0;
1625
1626 fail2:
1627 efx_for_each_channel_with_interrupt(channel, efx)
1628 free_irq(channel->irq, channel);
1629 fail1:
1630 return rc;
1631}
1632
1633void falcon_fini_interrupt(struct efx_nic *efx)
1634{
1635 struct efx_channel *channel;
1636 efx_oword_t reg;
1637
1638 /* Disable MSI/MSI-X interrupts */
1639 efx_for_each_channel_with_interrupt(channel, efx)
1640 if (channel->irq)
1641 free_irq(channel->irq, channel);
1642
1643 /* ACK legacy interrupt */
1644 if (FALCON_REV(efx) >= FALCON_REV_B0)
1645 falcon_read(efx, &reg, INT_ISR0_B0);
1646 else
1647 falcon_irq_ack_a1(efx);
1648
1649 /* Disable legacy interrupt */
1650 if (efx->legacy_irq)
1651 free_irq(efx->legacy_irq, efx);
1652}
1653
1654/**************************************************************************
1655 *
1656 * EEPROM/flash
1657 *
1658 **************************************************************************
1659 */
1660
1661#define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1662
1663/* Wait for SPI command completion */
1664static int falcon_spi_wait(struct efx_nic *efx)
1665{
1666 efx_oword_t reg;
1667 int cmd_en, timer_active;
1668 int count;
1669
1670 count = 0;
1671 do {
1672 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1673 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1674 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1675 if (!cmd_en && !timer_active)
1676 return 0;
1677 udelay(10);
1678 } while (++count < 10000); /* wait upto 100msec */
1679 EFX_ERR(efx, "timed out waiting for SPI\n");
1680 return -ETIMEDOUT;
1681}
1682
1683static int
1684falcon_spi_read(struct efx_nic *efx, int device_id, unsigned int command,
1685 unsigned int address, unsigned int addr_len,
1686 void *data, unsigned int len)
1687{
1688 efx_oword_t reg;
1689 int rc;
1690
1691 BUG_ON(len > FALCON_SPI_MAX_LEN);
1692
1693 /* Check SPI not currently being accessed */
1694 rc = falcon_spi_wait(efx);
1695 if (rc)
1696 return rc;
1697
1698 /* Program address register */
1699 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1700 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1701
1702 /* Issue read command */
1703 EFX_POPULATE_OWORD_7(reg,
1704 EE_SPI_HCMD_CMD_EN, 1,
1705 EE_SPI_HCMD_SF_SEL, device_id,
1706 EE_SPI_HCMD_DABCNT, len,
1707 EE_SPI_HCMD_READ, EE_SPI_READ,
1708 EE_SPI_HCMD_DUBCNT, 0,
1709 EE_SPI_HCMD_ADBCNT, addr_len,
1710 EE_SPI_HCMD_ENC, command);
1711 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1712
1713 /* Wait for read to complete */
1714 rc = falcon_spi_wait(efx);
1715 if (rc)
1716 return rc;
1717
1718 /* Read data */
1719 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1720 memcpy(data, &reg, len);
1721 return 0;
1722}
1723
1724/**************************************************************************
1725 *
1726 * MAC wrapper
1727 *
1728 **************************************************************************
1729 */
1730void falcon_drain_tx_fifo(struct efx_nic *efx)
1731{
1732 efx_oword_t temp;
1733 int count;
1734
3273c2e8
BH		 1735 if ((FALCON_REV(efx) < FALCON_REV_B0) ||
1736 (efx->loopback_mode != LOOPBACK_NONE))
8ceee660
BH		 1737 return;
1738
1739 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1740 /* There is no point in draining more than once */
1741 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1742 return;
1743
1744 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1745 * the drain sequence with the statistics fetch */
1746 spin_lock(&efx->stats_lock);
1747
1748 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1749 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1750
1751 /* Reset the MAC and EM block. */
1752 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1753 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1754 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1755 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1756 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1757
1758 count = 0;
1759 while (1) {
1760 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1761 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1762 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1763 !EFX_OWORD_FIELD(temp, RST_EM)) {
1764 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1765 count);
1766 break;
1767 }
1768 if (count > 20) {
1769 EFX_ERR(efx, "MAC reset failed\n");
1770 break;
1771 }
1772 count++;
1773 udelay(10);
1774 }
1775
1776 spin_unlock(&efx->stats_lock);
1777
1778 /* If we've reset the EM block and the link is up, then
1779 * we'll have to kick the XAUI link so the PHY can recover */
1780 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1781 falcon_reset_xaui(efx);
1782}
1783
1784void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1785{
1786 efx_oword_t temp;
1787
1788 if (FALCON_REV(efx) < FALCON_REV_B0)
1789 return;
1790
1791 /* Isolate the MAC -> RX */
1792 falcon_read(efx, &temp, RX_CFG_REG_KER);
1793 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1794 falcon_write(efx, &temp, RX_CFG_REG_KER);
1795
1796 if (!efx->link_up)
1797 falcon_drain_tx_fifo(efx);
1798}
1799
1800void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1801{
1802 efx_oword_t reg;
1803 int link_speed;
1804 unsigned int tx_fc;
1805
1806 if (efx->link_options & GM_LPA_10000)
1807 link_speed = 0x3;
1808 else if (efx->link_options & GM_LPA_1000)
1809 link_speed = 0x2;
1810 else if (efx->link_options & GM_LPA_100)
1811 link_speed = 0x1;
1812 else
1813 link_speed = 0x0;
1814 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1815 * as advertised. Disable to ensure packets are not
1816 * indefinitely held and TX queue can be flushed at any point
1817 * while the link is down. */
1818 EFX_POPULATE_OWORD_5(reg,
1819 MAC_XOFF_VAL, 0xffff /* max pause time */,
1820 MAC_BCAD_ACPT, 1,
1821 MAC_UC_PROM, efx->promiscuous,
1822 MAC_LINK_STATUS, 1, /* always set */
1823 MAC_SPEED, link_speed);
1824 /* On B0, MAC backpressure can be disabled and packets get
1825 * discarded. */
1826 if (FALCON_REV(efx) >= FALCON_REV_B0) {
1827 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1828 !efx->link_up);
1829 }
1830
1831 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1832
1833 /* Restore the multicast hash registers. */
1834 falcon_set_multicast_hash(efx);
1835
1836 /* Transmission of pause frames when RX crosses the threshold is
1837 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1838 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1839 tx_fc = (efx->flow_control & EFX_FC_TX) ? 1 : 0;
1840 falcon_read(efx, &reg, RX_CFG_REG_KER);
1841 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1842
1843 /* Unisolate the MAC -> RX */
1844 if (FALCON_REV(efx) >= FALCON_REV_B0)
1845 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1846 falcon_write(efx, &reg, RX_CFG_REG_KER);
1847}
1848
1849int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1850{
1851 efx_oword_t reg;
1852 u32 *dma_done;
1853 int i;
1854
1855 if (disable_dma_stats)
1856 return 0;
1857
1858 /* Statistics fetch will fail if the MAC is in TX drain */
1859 if (FALCON_REV(efx) >= FALCON_REV_B0) {
1860 efx_oword_t temp;
1861 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1862 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1863 return 0;
1864 }
1865
1866 dma_done = (efx->stats_buffer.addr + done_offset);
1867 *dma_done = FALCON_STATS_NOT_DONE;
1868 wmb(); /* ensure done flag is clear */
1869
1870 /* Initiate DMA transfer of stats */
1871 EFX_POPULATE_OWORD_2(reg,
1872 MAC_STAT_DMA_CMD, 1,
1873 MAC_STAT_DMA_ADR,
1874 efx->stats_buffer.dma_addr);
1875 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1876
1877 /* Wait for transfer to complete */
1878 for (i = 0; i < 400; i++) {
1879 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1880 return 0;
1881 udelay(10);
1882 }
1883
1884 EFX_ERR(efx, "timed out waiting for statistics\n");
1885 return -ETIMEDOUT;
1886}
1887
1888/**************************************************************************
1889 *
1890 * PHY access via GMII
1891 *
1892 **************************************************************************
1893 */
1894
1895/* Use the top bit of the MII PHY id to indicate the PHY type
1896 * (1G/10G), with the remaining bits as the actual PHY id.
1897 *
1898 * This allows us to avoid leaking information from the mii_if_info
1899 * structure into other data structures.
1900 */
1901#define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1902#define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1903#define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1904#define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1905#define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1906
1907
1908/* Packing the clause 45 port and device fields into a single value */
1909#define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1910#define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1911#define MD_DEV_ADR_COMP_LBN 0
1912#define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1913
1914
1915/* Wait for GMII access to complete */
1916static int falcon_gmii_wait(struct efx_nic *efx)
1917{
1918 efx_dword_t md_stat;
1919 int count;
1920
1921 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
1922 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
1923 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
1924 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
1925 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
1926 EFX_ERR(efx, "error from GMII access "
1927 EFX_DWORD_FMT"\n",
1928 EFX_DWORD_VAL(md_stat));
1929 return -EIO;
1930 }
1931 return 0;
1932 }
1933 udelay(10);
1934 }
1935 EFX_ERR(efx, "timed out waiting for GMII\n");
1936 return -ETIMEDOUT;
1937}
1938
1939/* Writes a GMII register of a PHY connected to Falcon using MDIO. */
1940static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
1941 int addr, int value)
1942{
1943 struct efx_nic *efx = (struct efx_nic *)net_dev->priv;
1944 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
1945 efx_oword_t reg;
1946
1947 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
1948 * chosen so that the only current user, Falcon, can take the
1949 * packed value and use them directly.
1950 * Fail to build if this assumption is broken.
1951 */
1952 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
1953 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
1954 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
1955 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
1956
1957 if (phy_id2 == PHY_ADDR_INVALID)
1958 return;
1959
1960 /* See falcon_mdio_read for an explanation. */
1961 if (!(phy_id & FALCON_PHY_ID_10G)) {
1962 int mmd = ffs(efx->phy_op->mmds) - 1;
1963 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
1964 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
1965 & FALCON_PHY_ID_ID_MASK;
1966 }
1967
1968 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
1969 addr, value);
1970
1971 spin_lock_bh(&efx->phy_lock);
1972
1973 /* Check MII not currently being accessed */
1974 if (falcon_gmii_wait(efx) != 0)
1975 goto out;
1976
1977 /* Write the address/ID register */
1978 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
1979 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
1980
1981 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
1982 falcon_write(efx, &reg, MD_ID_REG_KER);
1983
1984 /* Write data */
1985 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
1986 falcon_write(efx, &reg, MD_TXD_REG_KER);
1987
1988 EFX_POPULATE_OWORD_2(reg,
1989 MD_WRC, 1,
1990 MD_GC, 0);
1991 falcon_write(efx, &reg, MD_CS_REG_KER);
1992
1993 /* Wait for data to be written */
1994 if (falcon_gmii_wait(efx) != 0) {
1995 /* Abort the write operation */
1996 EFX_POPULATE_OWORD_2(reg,
1997 MD_WRC, 0,
1998 MD_GC, 1);
1999 falcon_write(efx, &reg, MD_CS_REG_KER);
2000 udelay(10);
2001 }
2002
2003 out:
2004 spin_unlock_bh(&efx->phy_lock);
2005}
2006
2007/* Reads a GMII register from a PHY connected to Falcon. If no value
2008 * could be read, -1 will be returned. */
2009static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2010{
2011 struct efx_nic *efx = (struct efx_nic *)net_dev->priv;
2012 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2013 efx_oword_t reg;
2014 int value = -1;
2015
2016 if (phy_addr == PHY_ADDR_INVALID)
2017 return -1;
2018
2019 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2020 * but the generic Linux code does not make any distinction or have
2021 * any state for this.
2022 * We spot the case where someone tried to talk 22 to a 45 PHY and
2023 * redirect the request to the lowest numbered MMD as a clause45
2024 * request. This is enough to allow simple queries like id and link
2025 * state to succeed. TODO: We may need to do more in future.
2026 */
2027 if (!(phy_id & FALCON_PHY_ID_10G)) {
2028 int mmd = ffs(efx->phy_op->mmds) - 1;
2029 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2030 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2031 & FALCON_PHY_ID_ID_MASK;
2032 }
2033
2034 spin_lock_bh(&efx->phy_lock);
2035
2036 /* Check MII not currently being accessed */
2037 if (falcon_gmii_wait(efx) != 0)
2038 goto out;
2039
2040 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2041 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2042
2043 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2044 falcon_write(efx, &reg, MD_ID_REG_KER);
2045
2046 /* Request data to be read */
2047 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2048 falcon_write(efx, &reg, MD_CS_REG_KER);
2049
2050 /* Wait for data to become available */
2051 value = falcon_gmii_wait(efx);
2052 if (value == 0) {
2053 falcon_read(efx, &reg, MD_RXD_REG_KER);
2054 value = EFX_OWORD_FIELD(reg, MD_RXD);
2055 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2056 phy_id, addr, value);
2057 } else {
2058 /* Abort the read operation */
2059 EFX_POPULATE_OWORD_2(reg,
2060 MD_RIC, 0,
2061 MD_GC, 1);
2062 falcon_write(efx, &reg, MD_CS_REG_KER);
2063
2064 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2065 "error %d\n", phy_id, addr, value);
2066 }
2067
2068 out:
2069 spin_unlock_bh(&efx->phy_lock);
2070
2071 return value;
2072}
2073
2074static void falcon_init_mdio(struct mii_if_info *gmii)
2075{
2076 gmii->mdio_read = falcon_mdio_read;
2077 gmii->mdio_write = falcon_mdio_write;
2078 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2079 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2080}
2081
2082static int falcon_probe_phy(struct efx_nic *efx)
2083{
2084 switch (efx->phy_type) {
2085 case PHY_TYPE_10XPRESS:
2086 efx->phy_op = &falcon_tenxpress_phy_ops;
2087 break;
2088 case PHY_TYPE_XFP:
2089 efx->phy_op = &falcon_xfp_phy_ops;
2090 break;
2091 default:
2092 EFX_ERR(efx, "Unknown PHY type %d\n",
2093 efx->phy_type);
2094 return -1;
2095 }
3273c2e8
BH		 2096
2097 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
8ceee660
BH		 2098 return 0;
2099}
2100
2101/* This call is responsible for hooking in the MAC and PHY operations */
2102int falcon_probe_port(struct efx_nic *efx)
2103{
2104 int rc;
2105
2106 /* Hook in PHY operations table */
2107 rc = falcon_probe_phy(efx);
2108 if (rc)
2109 return rc;
2110
2111 /* Set up GMII structure for PHY */
2112 efx->mii.supports_gmii = 1;
2113 falcon_init_mdio(&efx->mii);
2114
2115 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2116 if (FALCON_REV(efx) >= FALCON_REV_B0)
2117 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2118 else
2119 efx->flow_control = EFX_FC_RX;
2120
2121 /* Allocate buffer for stats */
2122 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2123 FALCON_MAC_STATS_SIZE);
2124 if (rc)
2125 return rc;
2126 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2127 (unsigned long long)efx->stats_buffer.dma_addr,
2128 efx->stats_buffer.addr,
2129 virt_to_phys(efx->stats_buffer.addr));
2130
2131 return 0;
2132}
2133
2134void falcon_remove_port(struct efx_nic *efx)
2135{
2136 falcon_free_buffer(efx, &efx->stats_buffer);
2137}
2138
2139/**************************************************************************
2140 *
2141 * Multicast filtering
2142 *
2143 **************************************************************************
2144 */
2145
2146void falcon_set_multicast_hash(struct efx_nic *efx)
2147{
2148 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2149
2150 /* Broadcast packets go through the multicast hash filter.
2151 * ether_crc_le() of the broadcast address is 0xbe2612ff
2152 * so we always add bit 0xff to the mask.
2153 */
2154 set_bit_le(0xff, mc_hash->byte);
2155
2156 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2157 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2158}
2159
2160/**************************************************************************
2161 *
2162 * Device reset
2163 *
2164 **************************************************************************
2165 */
2166
2167/* Resets NIC to known state. This routine must be called in process
2168 * context and is allowed to sleep. */
2169int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2170{
2171 struct falcon_nic_data *nic_data = efx->nic_data;
2172 efx_oword_t glb_ctl_reg_ker;
2173 int rc;
2174
2175 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2176
2177 /* Initiate device reset */
2178 if (method == RESET_TYPE_WORLD) {
2179 rc = pci_save_state(efx->pci_dev);
2180 if (rc) {
2181 EFX_ERR(efx, "failed to backup PCI state of primary "
2182 "function prior to hardware reset\n");
2183 goto fail1;
2184 }
2185 if (FALCON_IS_DUAL_FUNC(efx)) {
2186 rc = pci_save_state(nic_data->pci_dev2);
2187 if (rc) {
2188 EFX_ERR(efx, "failed to backup PCI state of "
2189 "secondary function prior to "
2190 "hardware reset\n");
2191 goto fail2;
2192 }
2193 }
2194
2195 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2196 EXT_PHY_RST_DUR, 0x7,
2197 SWRST, 1);
2198 } else {
2199 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2200 EXCLUDE_FROM_RESET : 0);
2201
2202 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2203 EXT_PHY_RST_CTL, reset_phy,
2204 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2205 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2206 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2207 EE_RST_CTL, EXCLUDE_FROM_RESET,
2208 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2209 SWRST, 1);
2210 }
2211 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2212
2213 EFX_LOG(efx, "waiting for hardware reset\n");
2214 schedule_timeout_uninterruptible(HZ / 20);
2215
2216 /* Restore PCI configuration if needed */
2217 if (method == RESET_TYPE_WORLD) {
2218 if (FALCON_IS_DUAL_FUNC(efx)) {
2219 rc = pci_restore_state(nic_data->pci_dev2);
2220 if (rc) {
2221 EFX_ERR(efx, "failed to restore PCI config for "
2222 "the secondary function\n");
2223 goto fail3;
2224 }
2225 }
2226 rc = pci_restore_state(efx->pci_dev);
2227 if (rc) {
2228 EFX_ERR(efx, "failed to restore PCI config for the "
2229 "primary function\n");
2230 goto fail4;
2231 }
2232 EFX_LOG(efx, "successfully restored PCI config\n");
2233 }
2234
2235 /* Assert that reset complete */
2236 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2237 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2238 rc = -ETIMEDOUT;
2239 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2240 goto fail5;
2241 }
2242 EFX_LOG(efx, "hardware reset complete\n");
2243
2244 return 0;
2245
2246 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2247fail2:
2248fail3:
2249 pci_restore_state(efx->pci_dev);
2250fail1:
2251fail4:
2252fail5:
2253 return rc;
2254}
2255
2256/* Zeroes out the SRAM contents. This routine must be called in
2257 * process context and is allowed to sleep.
2258 */
2259static int falcon_reset_sram(struct efx_nic *efx)
2260{
2261 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2262 int count;
2263
2264 /* Set the SRAM wake/sleep GPIO appropriately. */
2265 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2266 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2267 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2268 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2269
2270 /* Initiate SRAM reset */
2271 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2272 SRAM_OOB_BT_INIT_EN, 1,
2273 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2274 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2275
2276 /* Wait for SRAM reset to complete */
2277 count = 0;
2278 do {
2279 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2280
2281 /* SRAM reset is slow; expect around 16ms */
2282 schedule_timeout_uninterruptible(HZ / 50);
2283
2284 /* Check for reset complete */
2285 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2286 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2287 EFX_LOG(efx, "SRAM reset complete\n");
2288
2289 return 0;
2290 }
2291 } while (++count < 20); /* wait upto 0.4 sec */
2292
2293 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2294 return -ETIMEDOUT;
2295}
2296
2297/* Extract non-volatile configuration */
2298static int falcon_probe_nvconfig(struct efx_nic *efx)
2299{
2300 struct falcon_nvconfig *nvconfig;
2301 efx_oword_t nic_stat;
2302 int device_id;
2303 unsigned addr_len;
2304 size_t offset, len;
2305 int magic_num, struct_ver, board_rev;
2306 int rc;
2307
2308 /* Find the boot device. */
2309 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2310 if (EFX_OWORD_FIELD(nic_stat, SF_PRST)) {
2311 device_id = EE_SPI_FLASH;
2312 addr_len = 3;
2313 } else if (EFX_OWORD_FIELD(nic_stat, EE_PRST)) {
2314 device_id = EE_SPI_EEPROM;
2315 addr_len = 2;
2316 } else {
2317 return -ENODEV;
2318 }
2319
2320 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2321
2322 /* Read the whole configuration structure into memory. */
2323 for (offset = 0; offset < sizeof(*nvconfig); offset += len) {
2324 len = min(sizeof(*nvconfig) - offset,
2325 (size_t) FALCON_SPI_MAX_LEN);
2326 rc = falcon_spi_read(efx, device_id, SPI_READ,
2327 NVCONFIG_BASE + offset, addr_len,
2328 (char *)nvconfig + offset, len);
2329 if (rc)
2330 goto out;
2331 }
2332
2333 /* Read the MAC addresses */
2334 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2335
2336 /* Read the board configuration. */
2337 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2338 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2339
2340 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM || struct_ver < 2) {
2341 EFX_ERR(efx, "Non volatile memory bad magic=%x ver=%x "
2342 "therefore using defaults\n", magic_num, struct_ver);
2343 efx->phy_type = PHY_TYPE_NONE;
2344 efx->mii.phy_id = PHY_ADDR_INVALID;
2345 board_rev = 0;
2346 } else {
2347 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2348
2349 efx->phy_type = v2->port0_phy_type;
2350 efx->mii.phy_id = v2->port0_phy_addr;
2351 board_rev = le16_to_cpu(v2->board_revision);
2352 }
2353
2354 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2355
2356 efx_set_board_info(efx, board_rev);
2357
2358 out:
2359 kfree(nvconfig);
2360 return rc;
2361}
2362
2363/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2364 * count, port speed). Set workaround and feature flags accordingly.
2365 */
2366static int falcon_probe_nic_variant(struct efx_nic *efx)
2367{
2368 efx_oword_t altera_build;
2369
2370 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2371 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2372 EFX_ERR(efx, "Falcon FPGA not supported\n");
2373 return -ENODEV;
2374 }
2375
2376 switch (FALCON_REV(efx)) {
2377 case FALCON_REV_A0:
2378 case 0xff:
2379 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2380 return -ENODEV;
2381
2382 case FALCON_REV_A1:{
2383 efx_oword_t nic_stat;
2384
2385 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2386
2387 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2388 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2389 return -ENODEV;
2390 }
2391 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2392 EFX_ERR(efx, "1G mode not supported\n");
2393 return -ENODEV;
2394 }
2395 break;
2396 }
2397
2398 case FALCON_REV_B0:
2399 break;
2400
2401 default:
2402 EFX_ERR(efx, "Unknown Falcon rev %d\n", FALCON_REV(efx));
2403 return -ENODEV;
2404 }
2405
2406 return 0;
2407}
2408
2409int falcon_probe_nic(struct efx_nic *efx)
2410{
2411 struct falcon_nic_data *nic_data;
2412 int rc;
2413
2414 /* Initialise I2C interface state */
2415 efx->i2c.efx = efx;
2416 efx->i2c.op = &falcon_i2c_bit_operations;
2417 efx->i2c.sda = 1;
2418 efx->i2c.scl = 1;
2419
2420 /* Allocate storage for hardware specific data */
2421 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2422 efx->nic_data = (void *) nic_data;
2423
2424 /* Determine number of ports etc. */
2425 rc = falcon_probe_nic_variant(efx);
2426 if (rc)
2427 goto fail1;
2428
2429 /* Probe secondary function if expected */
2430 if (FALCON_IS_DUAL_FUNC(efx)) {
2431 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2432
2433 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2434 dev))) {
2435 if (dev->bus == efx->pci_dev->bus &&
2436 dev->devfn == efx->pci_dev->devfn + 1) {
2437 nic_data->pci_dev2 = dev;
2438 break;
2439 }
2440 }
2441 if (!nic_data->pci_dev2) {
2442 EFX_ERR(efx, "failed to find secondary function\n");
2443 rc = -ENODEV;
2444 goto fail2;
2445 }
2446 }
2447
2448 /* Now we can reset the NIC */
2449 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2450 if (rc) {
2451 EFX_ERR(efx, "failed to reset NIC\n");
2452 goto fail3;
2453 }
2454
2455 /* Allocate memory for INT_KER */
2456 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2457 if (rc)
2458 goto fail4;
2459 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2460
2461 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2462 (unsigned long long)efx->irq_status.dma_addr,
2463 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2464
2465 /* Read in the non-volatile configuration */
2466 rc = falcon_probe_nvconfig(efx);
2467 if (rc)
2468 goto fail5;
2469
2470 return 0;
2471
2472 fail5:
2473 falcon_free_buffer(efx, &efx->irq_status);
2474 fail4:
8ceee660
BH		 2475 fail3:
2476 if (nic_data->pci_dev2) {
2477 pci_dev_put(nic_data->pci_dev2);
2478 nic_data->pci_dev2 = NULL;
2479 }
2480 fail2:
8ceee660
BH		 2481 fail1:
2482 kfree(efx->nic_data);
2483 return rc;
2484}
2485
2486/* This call performs hardware-specific global initialisation, such as
2487 * defining the descriptor cache sizes and number of RSS channels.
2488 * It does not set up any buffers, descriptor rings or event queues.
2489 */
2490int falcon_init_nic(struct efx_nic *efx)
2491{
2492 struct falcon_nic_data *data;
2493 efx_oword_t temp;
2494 unsigned thresh;
2495 int rc;
2496
2497 data = (struct falcon_nic_data *)efx->nic_data;
2498
2499 /* Set up the address region register. This is only needed
2500 * for the B0 FPGA, but since we are just pushing in the
2501 * reset defaults this may as well be unconditional. */
2502 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2503 ADR_REGION1, (1 << 16),
2504 ADR_REGION2, (2 << 16),
2505 ADR_REGION3, (3 << 16));
2506 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2507
2508 /* Use on-chip SRAM */
2509 falcon_read(efx, &temp, NIC_STAT_REG);
2510 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2511 falcon_write(efx, &temp, NIC_STAT_REG);
2512
2513 /* Set buffer table mode */
2514 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2515 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2516
2517 rc = falcon_reset_sram(efx);
2518 if (rc)
2519 return rc;
2520
2521 /* Set positions of descriptor caches in SRAM. */
2522 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2523 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2524 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2525 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2526
2527 /* Set TX descriptor cache size. */
2528 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2529 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2530 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2531
2532 /* Set RX descriptor cache size. Set low watermark to size-8, as
2533 * this allows most efficient prefetching.
2534 */
2535 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2536 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2537 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2538 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2539 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2540
2541 /* Clear the parity enables on the TX data fifos as
2542 * they produce false parity errors because of timing issues
2543 */
2544 if (EFX_WORKAROUND_5129(efx)) {
2545 falcon_read(efx, &temp, SPARE_REG_KER);
2546 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2547 falcon_write(efx, &temp, SPARE_REG_KER);
2548 }
2549
2550 /* Enable all the genuinely fatal interrupts. (They are still
2551 * masked by the overall interrupt mask, controlled by
2552 * falcon_interrupts()).
2553 *
2554 * Note: All other fatal interrupts are enabled
2555 */
2556 EFX_POPULATE_OWORD_3(temp,
2557 ILL_ADR_INT_KER_EN, 1,
2558 RBUF_OWN_INT_KER_EN, 1,
2559 TBUF_OWN_INT_KER_EN, 1);
2560 EFX_INVERT_OWORD(temp);
2561 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2562
2563 /* Set number of RSS queues for receive path. */
2564 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2565 if (FALCON_REV(efx) >= FALCON_REV_B0)
2566 EFX_SET_OWORD_FIELD(temp, NUM_KER, 0);
2567 else
2568 EFX_SET_OWORD_FIELD(temp, NUM_KER, efx->rss_queues - 1);
2569 if (EFX_WORKAROUND_7244(efx)) {
2570 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2571 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2572 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2573 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2574 }
2575 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2576
2577 falcon_setup_rss_indir_table(efx);
2578
2579 /* Setup RX. Wait for descriptor is broken and must
2580 * be disabled. RXDP recovery shouldn't be needed, but is.
2581 */
2582 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2583 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2584 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2585 if (EFX_WORKAROUND_5583(efx))
2586 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2587 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2588
2589 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2590 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2591 */
2592 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2593 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2594 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2595 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2596 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2597 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2598 /* Enable SW_EV to inherit in char driver - assume harmless here */
2599 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2600 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2601 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2602 /* Squash TX of packets of 16 bytes or less */
2603 if (FALCON_REV(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
2604 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2605 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2606
2607 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2608 * descriptors (which is bad).
2609 */
2610 falcon_read(efx, &temp, TX_CFG_REG_KER);
2611 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2612 falcon_write(efx, &temp, TX_CFG_REG_KER);
2613
2614 /* RX config */
2615 falcon_read(efx, &temp, RX_CFG_REG_KER);
2616 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2617 if (EFX_WORKAROUND_7575(efx))
2618 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2619 (3 * 4096) / 32);
2620 if (FALCON_REV(efx) >= FALCON_REV_B0)
2621 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2622
2623 /* RX FIFO flow control thresholds */
2624 thresh = ((rx_xon_thresh_bytes >= 0) ?
2625 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2626 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2627 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2628 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2629 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2630 /* RX control FIFO thresholds [32 entries] */
2631 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 25);
2632 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 20);
2633 falcon_write(efx, &temp, RX_CFG_REG_KER);
2634
2635 /* Set destination of both TX and RX Flush events */
2636 if (FALCON_REV(efx) >= FALCON_REV_B0) {
2637 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2638 falcon_write(efx, &temp, DP_CTRL_REG);
2639 }
2640
2641 return 0;
2642}
2643
2644void falcon_remove_nic(struct efx_nic *efx)
2645{
2646 struct falcon_nic_data *nic_data = efx->nic_data;
2647
2648 falcon_free_buffer(efx, &efx->irq_status);
2649
91ad757c 2650 falcon_reset_hw(efx, RESET_TYPE_ALL);
8ceee660
BH		 2651
2652 /* Release the second function after the reset */
2653 if (nic_data->pci_dev2) {
2654 pci_dev_put(nic_data->pci_dev2);
2655 nic_data->pci_dev2 = NULL;
2656 }
2657
2658 /* Tear down the private nic state */
2659 kfree(efx->nic_data);
2660 efx->nic_data = NULL;
2661}
2662
2663void falcon_update_nic_stats(struct efx_nic *efx)
2664{
2665 efx_oword_t cnt;
2666
2667 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
2668 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
2669}
2670
2671/**************************************************************************
2672 *
2673 * Revision-dependent attributes used by efx.c
2674 *
2675 **************************************************************************
2676 */
2677
2678struct efx_nic_type falcon_a_nic_type = {
2679 .mem_bar = 2,
2680 .mem_map_size = 0x20000,
2681 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
2682 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
2683 .buf_tbl_base = BUF_TBL_KER_A1,
2684 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
2685 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
2686 .txd_ring_mask = FALCON_TXD_RING_MASK,
2687 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2688 .evq_size = FALCON_EVQ_SIZE,
2689 .max_dma_mask = FALCON_DMA_MASK,
2690 .tx_dma_mask = FALCON_TX_DMA_MASK,
2691 .bug5391_mask = 0xf,
2692 .rx_xoff_thresh = 2048,
2693 .rx_xon_thresh = 512,
2694 .rx_buffer_padding = 0x24,
2695 .max_interrupt_mode = EFX_INT_MODE_MSI,
2696 .phys_addr_channels = 4,
2697};
2698
2699struct efx_nic_type falcon_b_nic_type = {
2700 .mem_bar = 2,
2701 /* Map everything up to and including the RSS indirection
2702 * table. Don't map MSI-X table, MSI-X PBA since Linux
2703 * requires that they not be mapped. */
2704 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
2705 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
2706 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
2707 .buf_tbl_base = BUF_TBL_KER_B0,
2708 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
2709 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
2710 .txd_ring_mask = FALCON_TXD_RING_MASK,
2711 .rxd_ring_mask = FALCON_RXD_RING_MASK,
2712 .evq_size = FALCON_EVQ_SIZE,
2713 .max_dma_mask = FALCON_DMA_MASK,
2714 .tx_dma_mask = FALCON_TX_DMA_MASK,
2715 .bug5391_mask = 0,
2716 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
2717 .rx_xon_thresh = 27648, /* ~3*max MTU */
2718 .rx_buffer_padding = 0,
2719 .max_interrupt_mode = EFX_INT_MODE_MSIX,
2720 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
2721 * interrupt handler only supports 32
2722 * channels */
2723};
2724
Linux kernel - Deliverables
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