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sfc: Board support fixes
[deliverable/linux.git] / drivers / net / sfc / falcon.c
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8ceee660
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
15#include <linux/seq_file.h>
37b5a603
BH		 16#include <linux/i2c.h>
17#include <linux/i2c-algo-bit.h>
8ceee660
BH		 18#include "net_driver.h"
19#include "bitfield.h"
20#include "efx.h"
21#include "mac.h"
22#include "gmii.h"
23#include "spi.h"
24#include "falcon.h"
25#include "falcon_hwdefs.h"
26#include "falcon_io.h"
27#include "mdio_10g.h"
28#include "phy.h"
29#include "boards.h"
30#include "workarounds.h"
31
32/* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
35 */
36
37/**
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
37b5a603 41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
8ceee660
BH		 42 */
43struct falcon_nic_data {
44 unsigned next_buffer_table;
45 struct pci_dev *pci_dev2;
37b5a603 46 struct i2c_algo_bit_data i2c_data;
8ceee660
BH		 47};
48
49/**************************************************************************
50 *
51 * Configurable values
52 *
53 **************************************************************************
54 */
55
56static int disable_dma_stats;
57
58/* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
63 * goes idle.
64 */
65#define TX_DC_ENTRIES 16
66#define TX_DC_ENTRIES_ORDER 0
67#define TX_DC_BASE 0x130000
68
69#define RX_DC_ENTRIES 64
70#define RX_DC_ENTRIES_ORDER 2
71#define RX_DC_BASE 0x100000
72
73/* RX FIFO XOFF watermark
74 *
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
78 */
79static int rx_xoff_thresh_bytes = -1;
80module_param(rx_xoff_thresh_bytes, int, 0644);
81MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
82
83/* RX FIFO XON watermark
84 *
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
88 */
89static int rx_xon_thresh_bytes = -1;
90module_param(rx_xon_thresh_bytes, int, 0644);
91MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
92
93/* TX descriptor ring size - min 512 max 4k */
94#define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95#define FALCON_TXD_RING_SIZE 1024
96#define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
97
98/* RX descriptor ring size - min 512 max 4k */
99#define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100#define FALCON_RXD_RING_SIZE 1024
101#define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
102
103/* Event queue size - max 32k */
104#define FALCON_EVQ_ORDER EVQ_SIZE_4K
105#define FALCON_EVQ_SIZE 4096
106#define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
107
108/* Max number of internal errors. After this resets will not be performed */
109#define FALCON_MAX_INT_ERRORS 4
110
6bc5d3a9
BH		 111/* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times
112 */
113#define FALCON_FLUSH_INTERVAL 10
114#define FALCON_FLUSH_POLL_COUNT 100
8ceee660
BH		 115
116/**************************************************************************
117 *
118 * Falcon constants
119 *
120 **************************************************************************
121 */
122
9bbd7d9a
BH		 123/* DMA address mask */
124#define FALCON_DMA_MASK DMA_BIT_MASK(46)
8ceee660
BH		 125
126/* TX DMA length mask (13-bit) */
127#define FALCON_TX_DMA_MASK (4096 - 1)
128
129/* Size and alignment of special buffers (4KB) */
130#define FALCON_BUF_SIZE 4096
131
132/* Dummy SRAM size code */
133#define SRM_NB_BSZ_ONCHIP_ONLY (-1)
134
135/* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136#define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
137#define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
138#define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
139#define PCI_EXP_LNKSTA_LNK_WID 0x3f0
140#define PCI_EXP_LNKSTA_LNK_WID_LBN 4
141
142#define FALCON_IS_DUAL_FUNC(efx) \
55668611 143 (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 144
145/**************************************************************************
146 *
147 * Falcon hardware access
148 *
149 **************************************************************************/
150
151/* Read the current event from the event queue */
152static inline efx_qword_t *falcon_event(struct efx_channel *channel,
153 unsigned int index)
154{
155 return (((efx_qword_t *) (channel->eventq.addr)) + index);
156}
157
158/* See if an event is present
159 *
160 * We check both the high and low dword of the event for all ones. We
161 * wrote all ones when we cleared the event, and no valid event can
162 * have all ones in either its high or low dwords. This approach is
163 * robust against reordering.
164 *
165 * Note that using a single 64-bit comparison is incorrect; even
166 * though the CPU read will be atomic, the DMA write may not be.
167 */
168static inline int falcon_event_present(efx_qword_t *event)
169{
170 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
171 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
172}
173
174/**************************************************************************
175 *
176 * I2C bus - this is a bit-bashing interface using GPIO pins
177 * Note that it uses the output enables to tristate the outputs
178 * SDA is the data pin and SCL is the clock
179 *
180 **************************************************************************
181 */
37b5a603 182static void falcon_setsda(void *data, int state)
8ceee660 183{
37b5a603 184 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 185 efx_oword_t reg;
186
37b5a603
BH		 187 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
188 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
189 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
8ceee660
BH		 190}
191
37b5a603 192static void falcon_setscl(void *data, int state)
8ceee660 193{
37b5a603 194 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 195 efx_oword_t reg;
196
37b5a603
BH		 197 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
198 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
199 falcon_write(efx, &reg, GPIO_CTL_REG_KER);
200}
201
202static int falcon_getsda(void *data)
203{
204 struct efx_nic *efx = (struct efx_nic *)data;
205 efx_oword_t reg;
206
207 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
8ceee660
BH		 208 return EFX_OWORD_FIELD(reg, GPIO3_IN);
209}
210
37b5a603 211static int falcon_getscl(void *data)
8ceee660 212{
37b5a603 213 struct efx_nic *efx = (struct efx_nic *)data;
8ceee660
BH		 214 efx_oword_t reg;
215
37b5a603
BH		 216 falcon_read(efx, &reg, GPIO_CTL_REG_KER);
217 return EFX_OWORD_FIELD(reg, GPIO0_IN);
8ceee660
BH		 218}
219
37b5a603
BH		 220static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
221 .setsda = falcon_setsda,
222 .setscl = falcon_setscl,
8ceee660
BH		 223 .getsda = falcon_getsda,
224 .getscl = falcon_getscl,
62c78329 225 .udelay = 5,
9dadae68
BH		 226 /* Wait up to 50 ms for slave to let us pull SCL high */
227 .timeout = DIV_ROUND_UP(HZ, 20),
8ceee660
BH		 228};
229
230/**************************************************************************
231 *
232 * Falcon special buffer handling
233 * Special buffers are used for event queues and the TX and RX
234 * descriptor rings.
235 *
236 *************************************************************************/
237
238/*
239 * Initialise a Falcon special buffer
240 *
241 * This will define a buffer (previously allocated via
242 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243 * it to be used for event queues, descriptor rings etc.
244 */
bc3c90a2 245static void
8ceee660
BH		 246falcon_init_special_buffer(struct efx_nic *efx,
247 struct efx_special_buffer *buffer)
248{
249 efx_qword_t buf_desc;
250 int index;
251 dma_addr_t dma_addr;
252 int i;
253
254 EFX_BUG_ON_PARANOID(!buffer->addr);
255
256 /* Write buffer descriptors to NIC */
257 for (i = 0; i < buffer->entries; i++) {
258 index = buffer->index + i;
259 dma_addr = buffer->dma_addr + (i * 4096);
260 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
261 index, (unsigned long long)dma_addr);
262 EFX_POPULATE_QWORD_4(buf_desc,
263 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
264 BUF_ADR_REGION, 0,
265 BUF_ADR_FBUF, (dma_addr >> 12),
266 BUF_OWNER_ID_FBUF, 0);
267 falcon_write_sram(efx, &buf_desc, index);
268 }
8ceee660
BH		 269}
270
271/* Unmaps a buffer from Falcon and clears the buffer table entries */
272static void
273falcon_fini_special_buffer(struct efx_nic *efx,
274 struct efx_special_buffer *buffer)
275{
276 efx_oword_t buf_tbl_upd;
277 unsigned int start = buffer->index;
278 unsigned int end = (buffer->index + buffer->entries - 1);
279
280 if (!buffer->entries)
281 return;
282
283 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
284 buffer->index, buffer->index + buffer->entries - 1);
285
286 EFX_POPULATE_OWORD_4(buf_tbl_upd,
287 BUF_UPD_CMD, 0,
288 BUF_CLR_CMD, 1,
289 BUF_CLR_END_ID, end,
290 BUF_CLR_START_ID, start);
291 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
292}
293
294/*
295 * Allocate a new Falcon special buffer
296 *
297 * This allocates memory for a new buffer, clears it and allocates a
298 * new buffer ID range. It does not write into Falcon's buffer table.
299 *
300 * This call will allocate 4KB buffers, since Falcon can't use 8KB
301 * buffers for event queues and descriptor rings.
302 */
303static int falcon_alloc_special_buffer(struct efx_nic *efx,
304 struct efx_special_buffer *buffer,
305 unsigned int len)
306{
307 struct falcon_nic_data *nic_data = efx->nic_data;
308
309 len = ALIGN(len, FALCON_BUF_SIZE);
310
311 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
312 &buffer->dma_addr);
313 if (!buffer->addr)
314 return -ENOMEM;
315 buffer->len = len;
316 buffer->entries = len / FALCON_BUF_SIZE;
317 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
318
319 /* All zeros is a potentially valid event so memset to 0xff */
320 memset(buffer->addr, 0xff, len);
321
322 /* Select new buffer ID */
323 buffer->index = nic_data->next_buffer_table;
324 nic_data->next_buffer_table += buffer->entries;
325
326 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
327 "(virt %p phys %lx)\n", buffer->index,
328 buffer->index + buffer->entries - 1,
329 (unsigned long long)buffer->dma_addr, len,
330 buffer->addr, virt_to_phys(buffer->addr));
331
332 return 0;
333}
334
335static void falcon_free_special_buffer(struct efx_nic *efx,
336 struct efx_special_buffer *buffer)
337{
338 if (!buffer->addr)
339 return;
340
341 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
342 "(virt %p phys %lx)\n", buffer->index,
343 buffer->index + buffer->entries - 1,
344 (unsigned long long)buffer->dma_addr, buffer->len,
345 buffer->addr, virt_to_phys(buffer->addr));
346
347 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
348 buffer->dma_addr);
349 buffer->addr = NULL;
350 buffer->entries = 0;
351}
352
353/**************************************************************************
354 *
355 * Falcon generic buffer handling
356 * These buffers are used for interrupt status and MAC stats
357 *
358 **************************************************************************/
359
360static int falcon_alloc_buffer(struct efx_nic *efx,
361 struct efx_buffer *buffer, unsigned int len)
362{
363 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
364 &buffer->dma_addr);
365 if (!buffer->addr)
366 return -ENOMEM;
367 buffer->len = len;
368 memset(buffer->addr, 0, len);
369 return 0;
370}
371
372static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
373{
374 if (buffer->addr) {
375 pci_free_consistent(efx->pci_dev, buffer->len,
376 buffer->addr, buffer->dma_addr);
377 buffer->addr = NULL;
378 }
379}
380
381/**************************************************************************
382 *
383 * Falcon TX path
384 *
385 **************************************************************************/
386
387/* Returns a pointer to the specified transmit descriptor in the TX
388 * descriptor queue belonging to the specified channel.
389 */
390static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
391 unsigned int index)
392{
393 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
394}
395
396/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
397static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
398{
399 unsigned write_ptr;
400 efx_dword_t reg;
401
402 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
403 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
404 falcon_writel_page(tx_queue->efx, &reg,
405 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
406}
407
408
409/* For each entry inserted into the software descriptor ring, create a
410 * descriptor in the hardware TX descriptor ring (in host memory), and
411 * write a doorbell.
412 */
413void falcon_push_buffers(struct efx_tx_queue *tx_queue)
414{
415
416 struct efx_tx_buffer *buffer;
417 efx_qword_t *txd;
418 unsigned write_ptr;
419
420 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
421
422 do {
423 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
424 buffer = &tx_queue->buffer[write_ptr];
425 txd = falcon_tx_desc(tx_queue, write_ptr);
426 ++tx_queue->write_count;
427
428 /* Create TX descriptor ring entry */
429 EFX_POPULATE_QWORD_5(*txd,
430 TX_KER_PORT, 0,
431 TX_KER_CONT, buffer->continuation,
432 TX_KER_BYTE_CNT, buffer->len,
433 TX_KER_BUF_REGION, 0,
434 TX_KER_BUF_ADR, buffer->dma_addr);
435 } while (tx_queue->write_count != tx_queue->insert_count);
436
437 wmb(); /* Ensure descriptors are written before they are fetched */
438 falcon_notify_tx_desc(tx_queue);
439}
440
441/* Allocate hardware resources for a TX queue */
442int falcon_probe_tx(struct efx_tx_queue *tx_queue)
443{
444 struct efx_nic *efx = tx_queue->efx;
445 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
446 FALCON_TXD_RING_SIZE *
447 sizeof(efx_qword_t));
448}
449
bc3c90a2 450void falcon_init_tx(struct efx_tx_queue *tx_queue)
8ceee660
BH		 451{
452 efx_oword_t tx_desc_ptr;
453 struct efx_nic *efx = tx_queue->efx;
8ceee660 454
6bc5d3a9
BH		 455 tx_queue->flushed = false;
456
8ceee660 457 /* Pin TX descriptor ring */
bc3c90a2 458 falcon_init_special_buffer(efx, &tx_queue->txd);
8ceee660
BH		 459
460 /* Push TX descriptor ring to card */
461 EFX_POPULATE_OWORD_10(tx_desc_ptr,
462 TX_DESCQ_EN, 1,
463 TX_ISCSI_DDIG_EN, 0,
464 TX_ISCSI_HDIG_EN, 0,
465 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
d3074025 466 TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
8ceee660
BH		 467 TX_DESCQ_OWNER_ID, 0,
468 TX_DESCQ_LABEL, tx_queue->queue,
469 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
470 TX_DESCQ_TYPE, 0,
471 TX_NON_IP_DROP_DIS_B0, 1);
472
55668611 473 if (falcon_rev(efx) >= FALCON_REV_B0) {
60ac1065
BH		 474 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
475 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
476 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
8ceee660
BH		 477 }
478
479 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
480 tx_queue->queue);
481
55668611 482 if (falcon_rev(efx) < FALCON_REV_B0) {
8ceee660
BH		 483 efx_oword_t reg;
484
60ac1065
BH		 485 /* Only 128 bits in this register */
486 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
8ceee660
BH		 487
488 falcon_read(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
60ac1065 489 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
8ceee660
BH		 490 clear_bit_le(tx_queue->queue, (void *)&reg);
491 else
492 set_bit_le(tx_queue->queue, (void *)&reg);
493 falcon_write(efx, &reg, TX_CHKSM_CFG_REG_KER_A1);
494 }
8ceee660
BH		 495}
496
6bc5d3a9 497static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
8ceee660
BH		 498{
499 struct efx_nic *efx = tx_queue->efx;
8ceee660 500 efx_oword_t tx_flush_descq;
8ceee660
BH		 501
502 /* Post a flush command */
503 EFX_POPULATE_OWORD_2(tx_flush_descq,
504 TX_FLUSH_DESCQ_CMD, 1,
505 TX_FLUSH_DESCQ, tx_queue->queue);
506 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
8ceee660
BH		 507}
508
509void falcon_fini_tx(struct efx_tx_queue *tx_queue)
510{
511 struct efx_nic *efx = tx_queue->efx;
512 efx_oword_t tx_desc_ptr;
513
6bc5d3a9
BH		 514 /* The queue should have been flushed */
515 WARN_ON(!tx_queue->flushed);
8ceee660
BH		 516
517 /* Remove TX descriptor ring from card */
518 EFX_ZERO_OWORD(tx_desc_ptr);
519 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
520 tx_queue->queue);
521
522 /* Unpin TX descriptor ring */
523 falcon_fini_special_buffer(efx, &tx_queue->txd);
524}
525
526/* Free buffers backing TX queue */
527void falcon_remove_tx(struct efx_tx_queue *tx_queue)
528{
529 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
530}
531
532/**************************************************************************
533 *
534 * Falcon RX path
535 *
536 **************************************************************************/
537
538/* Returns a pointer to the specified descriptor in the RX descriptor queue */
539static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
540 unsigned int index)
541{
542 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
543}
544
545/* This creates an entry in the RX descriptor queue */
546static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
547 unsigned index)
548{
549 struct efx_rx_buffer *rx_buf;
550 efx_qword_t *rxd;
551
552 rxd = falcon_rx_desc(rx_queue, index);
553 rx_buf = efx_rx_buffer(rx_queue, index);
554 EFX_POPULATE_QWORD_3(*rxd,
555 RX_KER_BUF_SIZE,
556 rx_buf->len -
557 rx_queue->efx->type->rx_buffer_padding,
558 RX_KER_BUF_REGION, 0,
559 RX_KER_BUF_ADR, rx_buf->dma_addr);
560}
561
562/* This writes to the RX_DESC_WPTR register for the specified receive
563 * descriptor ring.
564 */
565void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
566{
567 efx_dword_t reg;
568 unsigned write_ptr;
569
570 while (rx_queue->notified_count != rx_queue->added_count) {
571 falcon_build_rx_desc(rx_queue,
572 rx_queue->notified_count &
573 FALCON_RXD_RING_MASK);
574 ++rx_queue->notified_count;
575 }
576
577 wmb();
578 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
579 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
580 falcon_writel_page(rx_queue->efx, &reg,
581 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
582}
583
584int falcon_probe_rx(struct efx_rx_queue *rx_queue)
585{
586 struct efx_nic *efx = rx_queue->efx;
587 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
588 FALCON_RXD_RING_SIZE *
589 sizeof(efx_qword_t));
590}
591
bc3c90a2 592void falcon_init_rx(struct efx_rx_queue *rx_queue)
8ceee660
BH		 593{
594 efx_oword_t rx_desc_ptr;
595 struct efx_nic *efx = rx_queue->efx;
dc8cfa55
BH		 596 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
597 bool iscsi_digest_en = is_b0;
8ceee660
BH		 598
599 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
600 rx_queue->queue, rx_queue->rxd.index,
601 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
602
6bc5d3a9
BH		 603 rx_queue->flushed = false;
604
8ceee660 605 /* Pin RX descriptor ring */
bc3c90a2 606 falcon_init_special_buffer(efx, &rx_queue->rxd);
8ceee660
BH		 607
608 /* Push RX descriptor ring to card */
609 EFX_POPULATE_OWORD_10(rx_desc_ptr,
610 RX_ISCSI_DDIG_EN, iscsi_digest_en,
611 RX_ISCSI_HDIG_EN, iscsi_digest_en,
612 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
d3074025 613 RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
8ceee660
BH		 614 RX_DESCQ_OWNER_ID, 0,
615 RX_DESCQ_LABEL, rx_queue->queue,
616 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
617 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
618 /* For >=B0 this is scatter so disable */
619 RX_DESCQ_JUMBO, !is_b0,
620 RX_DESCQ_EN, 1);
621 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
622 rx_queue->queue);
8ceee660
BH		 623}
624
6bc5d3a9 625static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
8ceee660
BH		 626{
627 struct efx_nic *efx = rx_queue->efx;
8ceee660
BH		 628 efx_oword_t rx_flush_descq;
629
630 /* Post a flush command */
631 EFX_POPULATE_OWORD_2(rx_flush_descq,
632 RX_FLUSH_DESCQ_CMD, 1,
633 RX_FLUSH_DESCQ, rx_queue->queue);
634 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
8ceee660
BH		 635}
636
637void falcon_fini_rx(struct efx_rx_queue *rx_queue)
638{
639 efx_oword_t rx_desc_ptr;
640 struct efx_nic *efx = rx_queue->efx;
8ceee660 641
6bc5d3a9
BH		 642 /* The queue should already have been flushed */
643 WARN_ON(!rx_queue->flushed);
8ceee660
BH		 644
645 /* Remove RX descriptor ring from card */
646 EFX_ZERO_OWORD(rx_desc_ptr);
647 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
648 rx_queue->queue);
649
650 /* Unpin RX descriptor ring */
651 falcon_fini_special_buffer(efx, &rx_queue->rxd);
652}
653
654/* Free buffers backing RX queue */
655void falcon_remove_rx(struct efx_rx_queue *rx_queue)
656{
657 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
658}
659
660/**************************************************************************
661 *
662 * Falcon event queue processing
663 * Event queues are processed by per-channel tasklets.
664 *
665 **************************************************************************/
666
667/* Update a channel's event queue's read pointer (RPTR) register
668 *
669 * This writes the EVQ_RPTR_REG register for the specified channel's
670 * event queue.
671 *
672 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
673 * whereas channel->eventq_read_ptr contains the index of the "next to
674 * read" event.
675 */
676void falcon_eventq_read_ack(struct efx_channel *channel)
677{
678 efx_dword_t reg;
679 struct efx_nic *efx = channel->efx;
680
681 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
682 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base,
d3074025 683 channel->channel);
8ceee660
BH		 684}
685
686/* Use HW to insert a SW defined event */
687void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
688{
689 efx_oword_t drv_ev_reg;
690
691 EFX_POPULATE_OWORD_2(drv_ev_reg,
d3074025 692 DRV_EV_QID, channel->channel,
8ceee660
BH		 693 DRV_EV_DATA,
694 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
695 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
696}
697
698/* Handle a transmit completion event
699 *
700 * Falcon batches TX completion events; the message we receive is of
701 * the form "complete all TX events up to this index".
702 */
4d566063
BH		 703static void falcon_handle_tx_event(struct efx_channel *channel,
704 efx_qword_t *event)
8ceee660
BH		 705{
706 unsigned int tx_ev_desc_ptr;
707 unsigned int tx_ev_q_label;
708 struct efx_tx_queue *tx_queue;
709 struct efx_nic *efx = channel->efx;
710
711 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
712 /* Transmit completion */
713 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
714 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
715 tx_queue = &efx->tx_queue[tx_ev_q_label];
716 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
717 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
718 /* Rewrite the FIFO write pointer */
719 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
720 tx_queue = &efx->tx_queue[tx_ev_q_label];
721
55668611 722 if (efx_dev_registered(efx))
8ceee660
BH		 723 netif_tx_lock(efx->net_dev);
724 falcon_notify_tx_desc(tx_queue);
55668611 725 if (efx_dev_registered(efx))
8ceee660
BH		 726 netif_tx_unlock(efx->net_dev);
727 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
728 EFX_WORKAROUND_10727(efx)) {
729 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
730 } else {
731 EFX_ERR(efx, "channel %d unexpected TX event "
732 EFX_QWORD_FMT"\n", channel->channel,
733 EFX_QWORD_VAL(*event));
734 }
735}
736
8ceee660
BH		 737/* Detect errors included in the rx_evt_pkt_ok bit. */
738static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
739 const efx_qword_t *event,
dc8cfa55
BH		 740 bool *rx_ev_pkt_ok,
741 bool *discard)
8ceee660
BH		 742{
743 struct efx_nic *efx = rx_queue->efx;
dc8cfa55
BH		 744 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
745 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
746 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
747 bool rx_ev_other_err, rx_ev_pause_frm;
748 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
749 unsigned rx_ev_pkt_type;
8ceee660
BH		 750
751 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
752 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
753 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
754 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
755 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
756 RX_EV_BUF_OWNER_ID_ERR);
757 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
758 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
759 RX_EV_IP_HDR_CHKSUM_ERR);
760 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
761 RX_EV_TCP_UDP_CHKSUM_ERR);
762 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
763 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
55668611 764 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
8ceee660
BH		 765 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
766 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
767
768 /* Every error apart from tobe_disc and pause_frm */
769 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
770 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
771 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
772
8ceee660
BH		 773 /* Count errors that are not in MAC stats. */
774 if (rx_ev_frm_trunc)
775 ++rx_queue->channel->n_rx_frm_trunc;
776 else if (rx_ev_tobe_disc)
777 ++rx_queue->channel->n_rx_tobe_disc;
778 else if (rx_ev_ip_hdr_chksum_err)
779 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
780 else if (rx_ev_tcp_udp_chksum_err)
781 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
782 if (rx_ev_ip_frag_err)
783 ++rx_queue->channel->n_rx_ip_frag_err;
784
785 /* The frame must be discarded if any of these are true. */
786 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
787 rx_ev_tobe_disc | rx_ev_pause_frm);
788
789 /* TOBE_DISC is expected on unicast mismatches; don't print out an
790 * error message. FRM_TRUNC indicates RXDP dropped the packet due
791 * to a FIFO overflow.
792 */
793#ifdef EFX_ENABLE_DEBUG
794 if (rx_ev_other_err) {
795 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
5b39fe30 796 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
8ceee660
BH		 797 rx_queue->queue, EFX_QWORD_VAL(*event),
798 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
799 rx_ev_ip_hdr_chksum_err ?
800 " [IP_HDR_CHKSUM_ERR]" : "",
801 rx_ev_tcp_udp_chksum_err ?
802 " [TCP_UDP_CHKSUM_ERR]" : "",
803 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
804 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
805 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
806 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
5b39fe30 807 rx_ev_pause_frm ? " [PAUSE]" : "");
8ceee660
BH		 808 }
809#endif
810
811 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
812 efx->phy_type == PHY_TYPE_10XPRESS))
813 tenxpress_crc_err(efx);
814}
815
816/* Handle receive events that are not in-order. */
817static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
818 unsigned index)
819{
820 struct efx_nic *efx = rx_queue->efx;
821 unsigned expected, dropped;
822
823 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
824 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
825 FALCON_RXD_RING_MASK);
826 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
827 dropped, index, expected);
828
829 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
830 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
831}
832
833/* Handle a packet received event
834 *
835 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
836 * wrong destination address
837 * Also "is multicast" and "matches multicast filter" flags can be used to
838 * discard non-matching multicast packets.
839 */
42cbe2d7
BH		 840static void falcon_handle_rx_event(struct efx_channel *channel,
841 const efx_qword_t *event)
8ceee660 842{
42cbe2d7 843 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
dc8cfa55 844 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
8ceee660 845 unsigned expected_ptr;
dc8cfa55 846 bool rx_ev_pkt_ok, discard = false, checksummed;
8ceee660
BH		 847 struct efx_rx_queue *rx_queue;
848 struct efx_nic *efx = channel->efx;
849
850 /* Basic packet information */
851 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
852 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
853 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
854 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
855 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
42cbe2d7 856 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
8ceee660 857
42cbe2d7 858 rx_queue = &efx->rx_queue[channel->channel];
8ceee660
BH		 859
860 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
861 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
42cbe2d7 862 if (unlikely(rx_ev_desc_ptr != expected_ptr))
8ceee660 863 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
8ceee660
BH		 864
865 if (likely(rx_ev_pkt_ok)) {
866 /* If packet is marked as OK and packet type is TCP/IPv4 or
867 * UDP/IPv4, then we can rely on the hardware checksum.
868 */
869 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
870 } else {
871 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
5b39fe30 872 &discard);
dc8cfa55 873 checksummed = false;
8ceee660
BH		 874 }
875
876 /* Detect multicast packets that didn't match the filter */
877 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
878 if (rx_ev_mcast_pkt) {
879 unsigned int rx_ev_mcast_hash_match =
880 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
881
882 if (unlikely(!rx_ev_mcast_hash_match))
dc8cfa55 883 discard = true;
8ceee660
BH		 884 }
885
886 /* Handle received packet */
887 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
888 checksummed, discard);
8ceee660
BH		 889}
890
891/* Global events are basically PHY events */
892static void falcon_handle_global_event(struct efx_channel *channel,
893 efx_qword_t *event)
894{
895 struct efx_nic *efx = channel->efx;
dc8cfa55 896 bool is_phy_event = false, handled = false;
8ceee660
BH		 897
898 /* Check for interrupt on either port. Some boards have a
899 * single PHY wired to the interrupt line for port 1. */
900 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
901 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
902 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
dc8cfa55 903 is_phy_event = true;
8ceee660 904
55668611 905 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
92ade881 906 EFX_QWORD_FIELD(*event, XG_MNT_INTR_B0))
dc8cfa55 907 is_phy_event = true;
8ceee660
BH		 908
909 if (is_phy_event) {
910 efx->phy_op->clear_interrupt(efx);
911 queue_work(efx->workqueue, &efx->reconfigure_work);
dc8cfa55 912 handled = true;
8ceee660
BH		 913 }
914
915 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
916 EFX_ERR(efx, "channel %d seen global RX_RESET "
917 "event. Resetting.\n", channel->channel);
918
919 atomic_inc(&efx->rx_reset);
920 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
921 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
dc8cfa55 922 handled = true;
8ceee660
BH		 923 }
924
925 if (!handled)
926 EFX_ERR(efx, "channel %d unknown global event "
927 EFX_QWORD_FMT "\n", channel->channel,
928 EFX_QWORD_VAL(*event));
929}
930
931static void falcon_handle_driver_event(struct efx_channel *channel,
932 efx_qword_t *event)
933{
934 struct efx_nic *efx = channel->efx;
935 unsigned int ev_sub_code;
936 unsigned int ev_sub_data;
937
938 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
939 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
940
941 switch (ev_sub_code) {
942 case TX_DESCQ_FLS_DONE_EV_DECODE:
943 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
944 channel->channel, ev_sub_data);
945 break;
946 case RX_DESCQ_FLS_DONE_EV_DECODE:
947 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
948 channel->channel, ev_sub_data);
949 break;
950 case EVQ_INIT_DONE_EV_DECODE:
951 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
952 channel->channel, ev_sub_data);
953 break;
954 case SRM_UPD_DONE_EV_DECODE:
955 EFX_TRACE(efx, "channel %d SRAM update done\n",
956 channel->channel);
957 break;
958 case WAKE_UP_EV_DECODE:
959 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
960 channel->channel, ev_sub_data);
961 break;
962 case TIMER_EV_DECODE:
963 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
964 channel->channel, ev_sub_data);
965 break;
966 case RX_RECOVERY_EV_DECODE:
967 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
968 "Resetting.\n", channel->channel);
05e3ec04 969 atomic_inc(&efx->rx_reset);
8ceee660
BH		 970 efx_schedule_reset(efx,
971 EFX_WORKAROUND_6555(efx) ?
972 RESET_TYPE_RX_RECOVERY :
973 RESET_TYPE_DISABLE);
974 break;
975 case RX_DSC_ERROR_EV_DECODE:
976 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
977 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
978 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
979 break;
980 case TX_DSC_ERROR_EV_DECODE:
981 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
982 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
983 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
984 break;
985 default:
986 EFX_TRACE(efx, "channel %d unknown driver event code %d "
987 "data %04x\n", channel->channel, ev_sub_code,
988 ev_sub_data);
989 break;
990 }
991}
992
42cbe2d7 993int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
8ceee660
BH		 994{
995 unsigned int read_ptr;
996 efx_qword_t event, *p_event;
997 int ev_code;
42cbe2d7 998 int rx_packets = 0;
8ceee660
BH		 999
1000 read_ptr = channel->eventq_read_ptr;
1001
1002 do {
1003 p_event = falcon_event(channel, read_ptr);
1004 event = *p_event;
1005
1006 if (!falcon_event_present(&event))
1007 /* End of events */
1008 break;
1009
1010 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1011 channel->channel, EFX_QWORD_VAL(event));
1012
1013 /* Clear this event by marking it all ones */
1014 EFX_SET_QWORD(*p_event);
1015
1016 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1017
1018 switch (ev_code) {
1019 case RX_IP_EV_DECODE:
42cbe2d7
BH		 1020 falcon_handle_rx_event(channel, &event);
1021 ++rx_packets;
8ceee660
BH		 1022 break;
1023 case TX_IP_EV_DECODE:
1024 falcon_handle_tx_event(channel, &event);
1025 break;
1026 case DRV_GEN_EV_DECODE:
1027 channel->eventq_magic
1028 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1029 EFX_LOG(channel->efx, "channel %d received generated "
1030 "event "EFX_QWORD_FMT"\n", channel->channel,
1031 EFX_QWORD_VAL(event));
1032 break;
1033 case GLOBAL_EV_DECODE:
1034 falcon_handle_global_event(channel, &event);
1035 break;
1036 case DRIVER_EV_DECODE:
1037 falcon_handle_driver_event(channel, &event);
1038 break;
1039 default:
1040 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1041 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1042 ev_code, EFX_QWORD_VAL(event));
1043 }
1044
1045 /* Increment read pointer */
1046 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1047
42cbe2d7 1048 } while (rx_packets < rx_quota);
8ceee660
BH		 1049
1050 channel->eventq_read_ptr = read_ptr;
42cbe2d7 1051 return rx_packets;
8ceee660
BH		 1052}
1053
1054void falcon_set_int_moderation(struct efx_channel *channel)
1055{
1056 efx_dword_t timer_cmd;
1057 struct efx_nic *efx = channel->efx;
1058
1059 /* Set timer register */
1060 if (channel->irq_moderation) {
1061 /* Round to resolution supported by hardware. The value we
1062 * program is based at 0. So actual interrupt moderation
1063 * achieved is ((x + 1) * res).
1064 */
1065 unsigned int res = 5;
1066 channel->irq_moderation -= (channel->irq_moderation % res);
1067 if (channel->irq_moderation < res)
1068 channel->irq_moderation = res;
1069 EFX_POPULATE_DWORD_2(timer_cmd,
1070 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1071 TIMER_VAL,
1072 (channel->irq_moderation / res) - 1);
1073 } else {
1074 EFX_POPULATE_DWORD_2(timer_cmd,
1075 TIMER_MODE, TIMER_MODE_DIS,
1076 TIMER_VAL, 0);
1077 }
1078 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
d3074025 1079 channel->channel);
8ceee660
BH		 1080
1081}
1082
1083/* Allocate buffer table entries for event queue */
1084int falcon_probe_eventq(struct efx_channel *channel)
1085{
1086 struct efx_nic *efx = channel->efx;
1087 unsigned int evq_size;
1088
1089 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1090 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1091}
1092
bc3c90a2 1093void falcon_init_eventq(struct efx_channel *channel)
8ceee660
BH		 1094{
1095 efx_oword_t evq_ptr;
1096 struct efx_nic *efx = channel->efx;
8ceee660
BH		 1097
1098 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1099 channel->channel, channel->eventq.index,
1100 channel->eventq.index + channel->eventq.entries - 1);
1101
1102 /* Pin event queue buffer */
bc3c90a2 1103 falcon_init_special_buffer(efx, &channel->eventq);
8ceee660
BH		 1104
1105 /* Fill event queue with all ones (i.e. empty events) */
1106 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1107
1108 /* Push event queue to card */
1109 EFX_POPULATE_OWORD_3(evq_ptr,
1110 EVQ_EN, 1,
1111 EVQ_SIZE, FALCON_EVQ_ORDER,
1112 EVQ_BUF_BASE_ID, channel->eventq.index);
1113 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
d3074025 1114 channel->channel);
8ceee660
BH		 1115
1116 falcon_set_int_moderation(channel);
8ceee660
BH		 1117}
1118
1119void falcon_fini_eventq(struct efx_channel *channel)
1120{
1121 efx_oword_t eventq_ptr;
1122 struct efx_nic *efx = channel->efx;
1123
1124 /* Remove event queue from card */
1125 EFX_ZERO_OWORD(eventq_ptr);
1126 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
d3074025 1127 channel->channel);
8ceee660
BH		 1128
1129 /* Unpin event queue */
1130 falcon_fini_special_buffer(efx, &channel->eventq);
1131}
1132
1133/* Free buffers backing event queue */
1134void falcon_remove_eventq(struct efx_channel *channel)
1135{
1136 falcon_free_special_buffer(channel->efx, &channel->eventq);
1137}
1138
1139
1140/* Generates a test event on the event queue. A subsequent call to
1141 * process_eventq() should pick up the event and place the value of
1142 * "magic" into channel->eventq_magic;
1143 */
1144void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1145{
1146 efx_qword_t test_event;
1147
1148 EFX_POPULATE_QWORD_2(test_event,
1149 EV_CODE, DRV_GEN_EV_DECODE,
1150 EVQ_MAGIC, magic);
1151 falcon_generate_event(channel, &test_event);
1152}
1153
6bc5d3a9
BH		 1154/**************************************************************************
1155 *
1156 * Flush handling
1157 *
1158 **************************************************************************/
1159
1160
1161static void falcon_poll_flush_events(struct efx_nic *efx)
1162{
1163 struct efx_channel *channel = &efx->channel[0];
1164 struct efx_tx_queue *tx_queue;
1165 struct efx_rx_queue *rx_queue;
1166 unsigned int read_ptr, i;
1167
1168 read_ptr = channel->eventq_read_ptr;
1169 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
1170 efx_qword_t *event = falcon_event(channel, read_ptr);
1171 int ev_code, ev_sub_code, ev_queue;
1172 bool ev_failed;
1173 if (!falcon_event_present(event))
1174 break;
1175
1176 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
1177 if (ev_code != DRIVER_EV_DECODE)
1178 continue;
1179
1180 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1181 switch (ev_sub_code) {
1182 case TX_DESCQ_FLS_DONE_EV_DECODE:
1183 ev_queue = EFX_QWORD_FIELD(*event,
1184 DRIVER_EV_TX_DESCQ_ID);
1185 if (ev_queue < EFX_TX_QUEUE_COUNT) {
1186 tx_queue = efx->tx_queue + ev_queue;
1187 tx_queue->flushed = true;
1188 }
1189 break;
1190 case RX_DESCQ_FLS_DONE_EV_DECODE:
1191 ev_queue = EFX_QWORD_FIELD(*event,
1192 DRIVER_EV_RX_DESCQ_ID);
1193 ev_failed = EFX_QWORD_FIELD(*event,
1194 DRIVER_EV_RX_FLUSH_FAIL);
1195 if (ev_queue < efx->n_rx_queues) {
1196 rx_queue = efx->rx_queue + ev_queue;
1197
1198 /* retry the rx flush */
1199 if (ev_failed)
1200 falcon_flush_rx_queue(rx_queue);
1201 else
1202 rx_queue->flushed = true;
1203 }
1204 break;
1205 }
1206
1207 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1208 }
1209}
1210
1211/* Handle tx and rx flushes at the same time, since they run in
1212 * parallel in the hardware and there's no reason for us to
1213 * serialise them */
1214int falcon_flush_queues(struct efx_nic *efx)
1215{
1216 struct efx_rx_queue *rx_queue;
1217 struct efx_tx_queue *tx_queue;
1218 int i;
1219 bool outstanding;
1220
1221 /* Issue flush requests */
1222 efx_for_each_tx_queue(tx_queue, efx) {
1223 tx_queue->flushed = false;
1224 falcon_flush_tx_queue(tx_queue);
1225 }
1226 efx_for_each_rx_queue(rx_queue, efx) {
1227 rx_queue->flushed = false;
1228 falcon_flush_rx_queue(rx_queue);
1229 }
1230
1231 /* Poll the evq looking for flush completions. Since we're not pushing
1232 * any more rx or tx descriptors at this point, we're in no danger of
1233 * overflowing the evq whilst we wait */
1234 for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) {
1235 msleep(FALCON_FLUSH_INTERVAL);
1236 falcon_poll_flush_events(efx);
1237
1238 /* Check if every queue has been succesfully flushed */
1239 outstanding = false;
1240 efx_for_each_tx_queue(tx_queue, efx)
1241 outstanding |= !tx_queue->flushed;
1242 efx_for_each_rx_queue(rx_queue, efx)
1243 outstanding |= !rx_queue->flushed;
1244 if (!outstanding)
1245 return 0;
1246 }
1247
1248 /* Mark the queues as all flushed. We're going to return failure
1249 * leading to a reset, or fake up success anyway. "flushed" now
1250 * indicates that we tried to flush. */
1251 efx_for_each_tx_queue(tx_queue, efx) {
1252 if (!tx_queue->flushed)
1253 EFX_ERR(efx, "tx queue %d flush command timed out\n",
1254 tx_queue->queue);
1255 tx_queue->flushed = true;
1256 }
1257 efx_for_each_rx_queue(rx_queue, efx) {
1258 if (!rx_queue->flushed)
1259 EFX_ERR(efx, "rx queue %d flush command timed out\n",
1260 rx_queue->queue);
1261 rx_queue->flushed = true;
1262 }
1263
1264 if (EFX_WORKAROUND_7803(efx))
1265 return 0;
1266
1267 return -ETIMEDOUT;
1268}
8ceee660
BH		 1269
1270/**************************************************************************
1271 *
1272 * Falcon hardware interrupts
1273 * The hardware interrupt handler does very little work; all the event
1274 * queue processing is carried out by per-channel tasklets.
1275 *
1276 **************************************************************************/
1277
1278/* Enable/disable/generate Falcon interrupts */
1279static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1280 int force)
1281{
1282 efx_oword_t int_en_reg_ker;
1283
1284 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1285 KER_INT_KER, force,
1286 DRV_INT_EN_KER, enabled);
1287 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1288}
1289
1290void falcon_enable_interrupts(struct efx_nic *efx)
1291{
1292 efx_oword_t int_adr_reg_ker;
1293 struct efx_channel *channel;
1294
1295 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1296 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1297
1298 /* Program address */
1299 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1300 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1301 INT_ADR_KER, efx->irq_status.dma_addr);
1302 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1303
1304 /* Enable interrupts */
1305 falcon_interrupts(efx, 1, 0);
1306
1307 /* Force processing of all the channels to get the EVQ RPTRs up to
1308 date */
64ee3120 1309 efx_for_each_channel(channel, efx)
8ceee660
BH		 1310 efx_schedule_channel(channel);
1311}
1312
1313void falcon_disable_interrupts(struct efx_nic *efx)
1314{
1315 /* Disable interrupts */
1316 falcon_interrupts(efx, 0, 0);
1317}
1318
1319/* Generate a Falcon test interrupt
1320 * Interrupt must already have been enabled, otherwise nasty things
1321 * may happen.
1322 */
1323void falcon_generate_interrupt(struct efx_nic *efx)
1324{
1325 falcon_interrupts(efx, 1, 1);
1326}
1327
1328/* Acknowledge a legacy interrupt from Falcon
1329 *
1330 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1331 *
1332 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1333 * BIU. Interrupt acknowledge is read sensitive so must write instead
1334 * (then read to ensure the BIU collector is flushed)
1335 *
1336 * NB most hardware supports MSI interrupts
1337 */
1338static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1339{
1340 efx_dword_t reg;
1341
1342 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1343 falcon_writel(efx, &reg, INT_ACK_REG_KER_A1);
1344 falcon_readl(efx, &reg, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1345}
1346
1347/* Process a fatal interrupt
1348 * Disable bus mastering ASAP and schedule a reset
1349 */
1350static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1351{
1352 struct falcon_nic_data *nic_data = efx->nic_data;
d3208b5e 1353 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1354 efx_oword_t fatal_intr;
1355 int error, mem_perr;
1356 static int n_int_errors;
1357
1358 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1359 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1360
1361 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1362 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1363 EFX_OWORD_VAL(fatal_intr),
1364 error ? "disabling bus mastering" : "no recognised error");
1365 if (error == 0)
1366 goto out;
1367
1368 /* If this is a memory parity error dump which blocks are offending */
1369 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1370 if (mem_perr) {
1371 efx_oword_t reg;
1372 falcon_read(efx, &reg, MEM_STAT_REG_KER);
1373 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1374 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1375 }
1376
0a62f1a6 1377 /* Disable both devices */
8ceee660
BH		 1378 pci_disable_device(efx->pci_dev);
1379 if (FALCON_IS_DUAL_FUNC(efx))
1380 pci_disable_device(nic_data->pci_dev2);
0a62f1a6 1381 falcon_disable_interrupts(efx);
8ceee660
BH		 1382
1383 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1384 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1385 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1386 } else {
1387 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1388 "NIC will be disabled\n");
1389 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1390 }
1391out:
1392 return IRQ_HANDLED;
1393}
1394
1395/* Handle a legacy interrupt from Falcon
1396 * Acknowledges the interrupt and schedule event queue processing.
1397 */
1398static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1399{
d3208b5e
BH		 1400 struct efx_nic *efx = dev_id;
1401 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1402 struct efx_channel *channel;
1403 efx_dword_t reg;
1404 u32 queues;
1405 int syserr;
1406
1407 /* Read the ISR which also ACKs the interrupts */
1408 falcon_readl(efx, &reg, INT_ISR0_B0);
1409 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1410
1411 /* Check to see if we have a serious error condition */
1412 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1413 if (unlikely(syserr))
1414 return falcon_fatal_interrupt(efx);
1415
1416 if (queues == 0)
1417 return IRQ_NONE;
1418
1419 efx->last_irq_cpu = raw_smp_processor_id();
1420 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1421 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1422
1423 /* Schedule processing of any interrupting queues */
1424 channel = &efx->channel[0];
1425 while (queues) {
1426 if (queues & 0x01)
1427 efx_schedule_channel(channel);
1428 channel++;
1429 queues >>= 1;
1430 }
1431
1432 return IRQ_HANDLED;
1433}
1434
1435
1436static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1437{
d3208b5e
BH		 1438 struct efx_nic *efx = dev_id;
1439 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1440 struct efx_channel *channel;
1441 int syserr;
1442 int queues;
1443
1444 /* Check to see if this is our interrupt. If it isn't, we
1445 * exit without having touched the hardware.
1446 */
1447 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1448 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1449 raw_smp_processor_id());
1450 return IRQ_NONE;
1451 }
1452 efx->last_irq_cpu = raw_smp_processor_id();
1453 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1454 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1455
1456 /* Check to see if we have a serious error condition */
1457 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1458 if (unlikely(syserr))
1459 return falcon_fatal_interrupt(efx);
1460
1461 /* Determine interrupting queues, clear interrupt status
1462 * register and acknowledge the device interrupt.
1463 */
1464 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1465 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1466 EFX_ZERO_OWORD(*int_ker);
1467 wmb(); /* Ensure the vector is cleared before interrupt ack */
1468 falcon_irq_ack_a1(efx);
1469
1470 /* Schedule processing of any interrupting queues */
1471 channel = &efx->channel[0];
1472 while (queues) {
1473 if (queues & 0x01)
1474 efx_schedule_channel(channel);
1475 channel++;
1476 queues >>= 1;
1477 }
1478
1479 return IRQ_HANDLED;
1480}
1481
1482/* Handle an MSI interrupt from Falcon
1483 *
1484 * Handle an MSI hardware interrupt. This routine schedules event
1485 * queue processing. No interrupt acknowledgement cycle is necessary.
1486 * Also, we never need to check that the interrupt is for us, since
1487 * MSI interrupts cannot be shared.
1488 */
1489static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1490{
d3208b5e 1491 struct efx_channel *channel = dev_id;
8ceee660 1492 struct efx_nic *efx = channel->efx;
d3208b5e 1493 efx_oword_t *int_ker = efx->irq_status.addr;
8ceee660
BH		 1494 int syserr;
1495
1496 efx->last_irq_cpu = raw_smp_processor_id();
1497 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1498 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1499
1500 /* Check to see if we have a serious error condition */
1501 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1502 if (unlikely(syserr))
1503 return falcon_fatal_interrupt(efx);
1504
1505 /* Schedule processing of the channel */
1506 efx_schedule_channel(channel);
1507
1508 return IRQ_HANDLED;
1509}
1510
1511
1512/* Setup RSS indirection table.
1513 * This maps from the hash value of the packet to RXQ
1514 */
1515static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1516{
1517 int i = 0;
1518 unsigned long offset;
1519 efx_dword_t dword;
1520
55668611 1521 if (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 1522 return;
1523
1524 for (offset = RX_RSS_INDIR_TBL_B0;
1525 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1526 offset += 0x10) {
1527 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
8831da7b 1528 i % efx->n_rx_queues);
8ceee660
BH		 1529 falcon_writel(efx, &dword, offset);
1530 i++;
1531 }
1532}
1533
1534/* Hook interrupt handler(s)
1535 * Try MSI and then legacy interrupts.
1536 */
1537int falcon_init_interrupt(struct efx_nic *efx)
1538{
1539 struct efx_channel *channel;
1540 int rc;
1541
1542 if (!EFX_INT_MODE_USE_MSI(efx)) {
1543 irq_handler_t handler;
55668611 1544 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 1545 handler = falcon_legacy_interrupt_b0;
1546 else
1547 handler = falcon_legacy_interrupt_a1;
1548
1549 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1550 efx->name, efx);
1551 if (rc) {
1552 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1553 efx->pci_dev->irq);
1554 goto fail1;
1555 }
1556 return 0;
1557 }
1558
1559 /* Hook MSI or MSI-X interrupt */
64ee3120 1560 efx_for_each_channel(channel, efx) {
8ceee660
BH		 1561 rc = request_irq(channel->irq, falcon_msi_interrupt,
1562 IRQF_PROBE_SHARED, /* Not shared */
1563 efx->name, channel);
1564 if (rc) {
1565 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1566 goto fail2;
1567 }
1568 }
1569
1570 return 0;
1571
1572 fail2:
64ee3120 1573 efx_for_each_channel(channel, efx)
8ceee660
BH		 1574 free_irq(channel->irq, channel);
1575 fail1:
1576 return rc;
1577}
1578
1579void falcon_fini_interrupt(struct efx_nic *efx)
1580{
1581 struct efx_channel *channel;
1582 efx_oword_t reg;
1583
1584 /* Disable MSI/MSI-X interrupts */
64ee3120 1585 efx_for_each_channel(channel, efx) {
8ceee660
BH		 1586 if (channel->irq)
1587 free_irq(channel->irq, channel);
b3475645 1588 }
8ceee660
BH		 1589
1590 /* ACK legacy interrupt */
55668611 1591 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 1592 falcon_read(efx, &reg, INT_ISR0_B0);
1593 else
1594 falcon_irq_ack_a1(efx);
1595
1596 /* Disable legacy interrupt */
1597 if (efx->legacy_irq)
1598 free_irq(efx->legacy_irq, efx);
1599}
1600
1601/**************************************************************************
1602 *
1603 * EEPROM/flash
1604 *
1605 **************************************************************************
1606 */
1607
31b76020 1608#define FALCON_SPI_MAX_LEN ((unsigned) sizeof(efx_oword_t))
8ceee660
BH		 1609
1610/* Wait for SPI command completion */
1611static int falcon_spi_wait(struct efx_nic *efx)
1612{
4a5b504d 1613 unsigned long timeout = jiffies + DIV_ROUND_UP(HZ, 10);
8ceee660 1614 efx_oword_t reg;
4a5b504d 1615 bool cmd_en, timer_active;
8ceee660 1616
4a5b504d 1617 for (;;) {
8ceee660
BH		 1618 falcon_read(efx, &reg, EE_SPI_HCMD_REG_KER);
1619 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1620 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1621 if (!cmd_en && !timer_active)
1622 return 0;
4a5b504d
BH		 1623 if (time_after_eq(jiffies, timeout)) {
1624 EFX_ERR(efx, "timed out waiting for SPI\n");
1625 return -ETIMEDOUT;
1626 }
1627 cpu_relax();
1628 }
8ceee660
BH		 1629}
1630
f4150724
BH		 1631int falcon_spi_cmd(const struct efx_spi_device *spi,
1632 unsigned int command, int address,
1633 const void *in, void *out, unsigned int len)
8ceee660 1634{
4a5b504d
BH		 1635 struct efx_nic *efx = spi->efx;
1636 bool addressed = (address >= 0);
1637 bool reading = (out != NULL);
8ceee660
BH		 1638 efx_oword_t reg;
1639 int rc;
1640
4a5b504d
BH		 1641 /* Input validation */
1642 if (len > FALCON_SPI_MAX_LEN)
1643 return -EINVAL;
f4150724 1644 BUG_ON(!mutex_is_locked(&efx->spi_lock));
8ceee660
BH		 1645
1646 /* Check SPI not currently being accessed */
1647 rc = falcon_spi_wait(efx);
1648 if (rc)
1649 return rc;
1650
4a5b504d
BH		 1651 /* Program address register, if we have an address */
1652 if (addressed) {
1653 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1654 falcon_write(efx, &reg, EE_SPI_HADR_REG_KER);
1655 }
1656
1657 /* Program data register, if we have data */
1658 if (in != NULL) {
1659 memcpy(&reg, in, len);
1660 falcon_write(efx, &reg, EE_SPI_HDATA_REG_KER);
1661 }
8ceee660 1662
4a5b504d 1663 /* Issue read/write command */
8ceee660
BH		 1664 EFX_POPULATE_OWORD_7(reg,
1665 EE_SPI_HCMD_CMD_EN, 1,
4a5b504d 1666 EE_SPI_HCMD_SF_SEL, spi->device_id,
8ceee660 1667 EE_SPI_HCMD_DABCNT, len,
4a5b504d 1668 EE_SPI_HCMD_READ, reading,
8ceee660 1669 EE_SPI_HCMD_DUBCNT, 0,
4a5b504d
BH		 1670 EE_SPI_HCMD_ADBCNT,
1671 (addressed ? spi->addr_len : 0),
8ceee660
BH		 1672 EE_SPI_HCMD_ENC, command);
1673 falcon_write(efx, &reg, EE_SPI_HCMD_REG_KER);
1674
4a5b504d 1675 /* Wait for read/write to complete */
8ceee660
BH		 1676 rc = falcon_spi_wait(efx);
1677 if (rc)
1678 return rc;
1679
1680 /* Read data */
4a5b504d
BH		 1681 if (out != NULL) {
1682 falcon_read(efx, &reg, EE_SPI_HDATA_REG_KER);
1683 memcpy(out, &reg, len);
1684 }
1685
8ceee660
BH		 1686 return 0;
1687}
1688
4a5b504d
BH		 1689static unsigned int
1690falcon_spi_write_limit(const struct efx_spi_device *spi, unsigned int start)
1691{
1692 return min(FALCON_SPI_MAX_LEN,
1693 (spi->block_size - (start & (spi->block_size - 1))));
1694}
1695
1696static inline u8
1697efx_spi_munge_command(const struct efx_spi_device *spi,
1698 const u8 command, const unsigned int address)
1699{
1700 return command | (((address >> 8) & spi->munge_address) << 3);
1701}
1702
f4150724 1703int falcon_spi_fast_wait(const struct efx_spi_device *spi)
4a5b504d
BH		 1704{
1705 u8 status;
1706 int i, rc;
1707
1708 /* Wait up to 1000us for flash/EEPROM to finish a fast operation. */
1709 for (i = 0; i < 50; i++) {
1710 udelay(20);
1711
1712 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1713 &status, sizeof(status));
1714 if (rc)
1715 return rc;
1716 if (!(status & SPI_STATUS_NRDY))
1717 return 0;
1718 }
1719 EFX_ERR(spi->efx,
1720 "timed out waiting for device %d last status=0x%02x\n",
1721 spi->device_id, status);
1722 return -ETIMEDOUT;
1723}
1724
1725int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1726 size_t len, size_t *retlen, u8 *buffer)
1727{
1728 unsigned int command, block_len, pos = 0;
1729 int rc = 0;
1730
1731 while (pos < len) {
1732 block_len = min((unsigned int)len - pos,
1733 FALCON_SPI_MAX_LEN);
1734
1735 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1736 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1737 buffer + pos, block_len);
1738 if (rc)
1739 break;
1740 pos += block_len;
1741
1742 /* Avoid locking up the system */
1743 cond_resched();
1744 if (signal_pending(current)) {
1745 rc = -EINTR;
1746 break;
1747 }
1748 }
1749
1750 if (retlen)
1751 *retlen = pos;
1752 return rc;
1753}
1754
1755int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1756 size_t len, size_t *retlen, const u8 *buffer)
1757{
1758 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1759 unsigned int command, block_len, pos = 0;
1760 int rc = 0;
1761
1762 while (pos < len) {
1763 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1764 if (rc)
1765 break;
1766
1767 block_len = min((unsigned int)len - pos,
1768 falcon_spi_write_limit(spi, start + pos));
1769 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1770 rc = falcon_spi_cmd(spi, command, start + pos,
1771 buffer + pos, NULL, block_len);
1772 if (rc)
1773 break;
1774
1775 rc = falcon_spi_fast_wait(spi);
1776 if (rc)
1777 break;
1778
1779 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1780 rc = falcon_spi_cmd(spi, command, start + pos,
1781 NULL, verify_buffer, block_len);
1782 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1783 rc = -EIO;
1784 break;
1785 }
1786
1787 pos += block_len;
1788
1789 /* Avoid locking up the system */
1790 cond_resched();
1791 if (signal_pending(current)) {
1792 rc = -EINTR;
1793 break;
1794 }
1795 }
1796
1797 if (retlen)
1798 *retlen = pos;
1799 return rc;
1800}
1801
8ceee660
BH		 1802/**************************************************************************
1803 *
1804 * MAC wrapper
1805 *
1806 **************************************************************************
1807 */
1808void falcon_drain_tx_fifo(struct efx_nic *efx)
1809{
1810 efx_oword_t temp;
1811 int count;
1812
55668611 1813 if ((falcon_rev(efx) < FALCON_REV_B0) ||
3273c2e8 1814 (efx->loopback_mode != LOOPBACK_NONE))
8ceee660
BH		 1815 return;
1816
1817 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1818 /* There is no point in draining more than once */
1819 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1820 return;
1821
1822 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1823 * the drain sequence with the statistics fetch */
1824 spin_lock(&efx->stats_lock);
1825
1826 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1827 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1828
1829 /* Reset the MAC and EM block. */
1830 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1831 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1832 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1833 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1834 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1835
1836 count = 0;
1837 while (1) {
1838 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1839 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1840 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1841 !EFX_OWORD_FIELD(temp, RST_EM)) {
1842 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1843 count);
1844 break;
1845 }
1846 if (count > 20) {
1847 EFX_ERR(efx, "MAC reset failed\n");
1848 break;
1849 }
1850 count++;
1851 udelay(10);
1852 }
1853
1854 spin_unlock(&efx->stats_lock);
1855
1856 /* If we've reset the EM block and the link is up, then
1857 * we'll have to kick the XAUI link so the PHY can recover */
1858 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1859 falcon_reset_xaui(efx);
1860}
1861
1862void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1863{
1864 efx_oword_t temp;
1865
55668611 1866 if (falcon_rev(efx) < FALCON_REV_B0)
8ceee660
BH		 1867 return;
1868
1869 /* Isolate the MAC -> RX */
1870 falcon_read(efx, &temp, RX_CFG_REG_KER);
1871 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1872 falcon_write(efx, &temp, RX_CFG_REG_KER);
1873
1874 if (!efx->link_up)
1875 falcon_drain_tx_fifo(efx);
1876}
1877
1878void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1879{
1880 efx_oword_t reg;
1881 int link_speed;
dc8cfa55 1882 bool tx_fc;
8ceee660
BH		 1883
1884 if (efx->link_options & GM_LPA_10000)
1885 link_speed = 0x3;
1886 else if (efx->link_options & GM_LPA_1000)
1887 link_speed = 0x2;
1888 else if (efx->link_options & GM_LPA_100)
1889 link_speed = 0x1;
1890 else
1891 link_speed = 0x0;
1892 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1893 * as advertised. Disable to ensure packets are not
1894 * indefinitely held and TX queue can be flushed at any point
1895 * while the link is down. */
1896 EFX_POPULATE_OWORD_5(reg,
1897 MAC_XOFF_VAL, 0xffff /* max pause time */,
1898 MAC_BCAD_ACPT, 1,
1899 MAC_UC_PROM, efx->promiscuous,
1900 MAC_LINK_STATUS, 1, /* always set */
1901 MAC_SPEED, link_speed);
1902 /* On B0, MAC backpressure can be disabled and packets get
1903 * discarded. */
55668611 1904 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660
BH		 1905 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1906 !efx->link_up);
1907 }
1908
1909 falcon_write(efx, &reg, MAC0_CTRL_REG_KER);
1910
1911 /* Restore the multicast hash registers. */
1912 falcon_set_multicast_hash(efx);
1913
1914 /* Transmission of pause frames when RX crosses the threshold is
1915 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1916 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
dc8cfa55 1917 tx_fc = !!(efx->flow_control & EFX_FC_TX);
8ceee660
BH		 1918 falcon_read(efx, &reg, RX_CFG_REG_KER);
1919 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1920
1921 /* Unisolate the MAC -> RX */
55668611 1922 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 1923 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1924 falcon_write(efx, &reg, RX_CFG_REG_KER);
1925}
1926
1927int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1928{
1929 efx_oword_t reg;
1930 u32 *dma_done;
1931 int i;
1932
1933 if (disable_dma_stats)
1934 return 0;
1935
1936 /* Statistics fetch will fail if the MAC is in TX drain */
55668611 1937 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660
BH		 1938 efx_oword_t temp;
1939 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1940 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1941 return 0;
1942 }
1943
1944 dma_done = (efx->stats_buffer.addr + done_offset);
1945 *dma_done = FALCON_STATS_NOT_DONE;
1946 wmb(); /* ensure done flag is clear */
1947
1948 /* Initiate DMA transfer of stats */
1949 EFX_POPULATE_OWORD_2(reg,
1950 MAC_STAT_DMA_CMD, 1,
1951 MAC_STAT_DMA_ADR,
1952 efx->stats_buffer.dma_addr);
1953 falcon_write(efx, &reg, MAC0_STAT_DMA_REG_KER);
1954
1955 /* Wait for transfer to complete */
1956 for (i = 0; i < 400; i++) {
1d0680fd
BH		 1957 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE) {
1958 rmb(); /* Ensure the stats are valid. */
8ceee660 1959 return 0;
1d0680fd 1960 }
8ceee660
BH		 1961 udelay(10);
1962 }
1963
1964 EFX_ERR(efx, "timed out waiting for statistics\n");
1965 return -ETIMEDOUT;
1966}
1967
1968/**************************************************************************
1969 *
1970 * PHY access via GMII
1971 *
1972 **************************************************************************
1973 */
1974
1975/* Use the top bit of the MII PHY id to indicate the PHY type
1976 * (1G/10G), with the remaining bits as the actual PHY id.
1977 *
1978 * This allows us to avoid leaking information from the mii_if_info
1979 * structure into other data structures.
1980 */
1981#define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1982#define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1983#define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1984#define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1985#define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1986
1987
1988/* Packing the clause 45 port and device fields into a single value */
1989#define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1990#define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1991#define MD_DEV_ADR_COMP_LBN 0
1992#define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1993
1994
1995/* Wait for GMII access to complete */
1996static int falcon_gmii_wait(struct efx_nic *efx)
1997{
1998 efx_dword_t md_stat;
1999 int count;
2000
2001 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
2002 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
2003 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
2004 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
2005 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
2006 EFX_ERR(efx, "error from GMII access "
2007 EFX_DWORD_FMT"\n",
2008 EFX_DWORD_VAL(md_stat));
2009 return -EIO;
2010 }
2011 return 0;
2012 }
2013 udelay(10);
2014 }
2015 EFX_ERR(efx, "timed out waiting for GMII\n");
2016 return -ETIMEDOUT;
2017}
2018
2019/* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2020static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2021 int addr, int value)
2022{
767e468c 2023 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2024 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2025 efx_oword_t reg;
2026
2027 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2028 * chosen so that the only current user, Falcon, can take the
2029 * packed value and use them directly.
2030 * Fail to build if this assumption is broken.
2031 */
2032 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2033 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2034 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2035 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2036
2037 if (phy_id2 == PHY_ADDR_INVALID)
2038 return;
2039
2040 /* See falcon_mdio_read for an explanation. */
2041 if (!(phy_id & FALCON_PHY_ID_10G)) {
2042 int mmd = ffs(efx->phy_op->mmds) - 1;
2043 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2044 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2045 & FALCON_PHY_ID_ID_MASK;
2046 }
2047
2048 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2049 addr, value);
2050
2051 spin_lock_bh(&efx->phy_lock);
2052
2053 /* Check MII not currently being accessed */
2054 if (falcon_gmii_wait(efx) != 0)
2055 goto out;
2056
2057 /* Write the address/ID register */
2058 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2059 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2060
2061 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2062 falcon_write(efx, &reg, MD_ID_REG_KER);
2063
2064 /* Write data */
2065 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2066 falcon_write(efx, &reg, MD_TXD_REG_KER);
2067
2068 EFX_POPULATE_OWORD_2(reg,
2069 MD_WRC, 1,
2070 MD_GC, 0);
2071 falcon_write(efx, &reg, MD_CS_REG_KER);
2072
2073 /* Wait for data to be written */
2074 if (falcon_gmii_wait(efx) != 0) {
2075 /* Abort the write operation */
2076 EFX_POPULATE_OWORD_2(reg,
2077 MD_WRC, 0,
2078 MD_GC, 1);
2079 falcon_write(efx, &reg, MD_CS_REG_KER);
2080 udelay(10);
2081 }
2082
2083 out:
2084 spin_unlock_bh(&efx->phy_lock);
2085}
2086
2087/* Reads a GMII register from a PHY connected to Falcon. If no value
2088 * could be read, -1 will be returned. */
2089static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2090{
767e468c 2091 struct efx_nic *efx = netdev_priv(net_dev);
8ceee660
BH		 2092 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2093 efx_oword_t reg;
2094 int value = -1;
2095
2096 if (phy_addr == PHY_ADDR_INVALID)
2097 return -1;
2098
2099 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2100 * but the generic Linux code does not make any distinction or have
2101 * any state for this.
2102 * We spot the case where someone tried to talk 22 to a 45 PHY and
2103 * redirect the request to the lowest numbered MMD as a clause45
2104 * request. This is enough to allow simple queries like id and link
2105 * state to succeed. TODO: We may need to do more in future.
2106 */
2107 if (!(phy_id & FALCON_PHY_ID_10G)) {
2108 int mmd = ffs(efx->phy_op->mmds) - 1;
2109 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2110 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2111 & FALCON_PHY_ID_ID_MASK;
2112 }
2113
2114 spin_lock_bh(&efx->phy_lock);
2115
2116 /* Check MII not currently being accessed */
2117 if (falcon_gmii_wait(efx) != 0)
2118 goto out;
2119
2120 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2121 falcon_write(efx, &reg, MD_PHY_ADR_REG_KER);
2122
2123 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2124 falcon_write(efx, &reg, MD_ID_REG_KER);
2125
2126 /* Request data to be read */
2127 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2128 falcon_write(efx, &reg, MD_CS_REG_KER);
2129
2130 /* Wait for data to become available */
2131 value = falcon_gmii_wait(efx);
2132 if (value == 0) {
2133 falcon_read(efx, &reg, MD_RXD_REG_KER);
2134 value = EFX_OWORD_FIELD(reg, MD_RXD);
2135 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2136 phy_id, addr, value);
2137 } else {
2138 /* Abort the read operation */
2139 EFX_POPULATE_OWORD_2(reg,
2140 MD_RIC, 0,
2141 MD_GC, 1);
2142 falcon_write(efx, &reg, MD_CS_REG_KER);
2143
2144 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2145 "error %d\n", phy_id, addr, value);
2146 }
2147
2148 out:
2149 spin_unlock_bh(&efx->phy_lock);
2150
2151 return value;
2152}
2153
2154static void falcon_init_mdio(struct mii_if_info *gmii)
2155{
2156 gmii->mdio_read = falcon_mdio_read;
2157 gmii->mdio_write = falcon_mdio_write;
2158 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2159 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2160}
2161
2162static int falcon_probe_phy(struct efx_nic *efx)
2163{
2164 switch (efx->phy_type) {
2165 case PHY_TYPE_10XPRESS:
2166 efx->phy_op = &falcon_tenxpress_phy_ops;
2167 break;
2168 case PHY_TYPE_XFP:
2169 efx->phy_op = &falcon_xfp_phy_ops;
2170 break;
2171 default:
2172 EFX_ERR(efx, "Unknown PHY type %d\n",
2173 efx->phy_type);
2174 return -1;
2175 }
3273c2e8
BH		 2176
2177 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
8ceee660
BH		 2178 return 0;
2179}
2180
2181/* This call is responsible for hooking in the MAC and PHY operations */
2182int falcon_probe_port(struct efx_nic *efx)
2183{
2184 int rc;
2185
2186 /* Hook in PHY operations table */
2187 rc = falcon_probe_phy(efx);
2188 if (rc)
2189 return rc;
2190
2191 /* Set up GMII structure for PHY */
dc8cfa55 2192 efx->mii.supports_gmii = true;
8ceee660
BH		 2193 falcon_init_mdio(&efx->mii);
2194
2195 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
55668611 2196 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 2197 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2198 else
2199 efx->flow_control = EFX_FC_RX;
2200
2201 /* Allocate buffer for stats */
2202 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2203 FALCON_MAC_STATS_SIZE);
2204 if (rc)
2205 return rc;
2206 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2207 (unsigned long long)efx->stats_buffer.dma_addr,
2208 efx->stats_buffer.addr,
2209 virt_to_phys(efx->stats_buffer.addr));
2210
2211 return 0;
2212}
2213
2214void falcon_remove_port(struct efx_nic *efx)
2215{
2216 falcon_free_buffer(efx, &efx->stats_buffer);
2217}
2218
2219/**************************************************************************
2220 *
2221 * Multicast filtering
2222 *
2223 **************************************************************************
2224 */
2225
2226void falcon_set_multicast_hash(struct efx_nic *efx)
2227{
2228 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2229
2230 /* Broadcast packets go through the multicast hash filter.
2231 * ether_crc_le() of the broadcast address is 0xbe2612ff
2232 * so we always add bit 0xff to the mask.
2233 */
2234 set_bit_le(0xff, mc_hash->byte);
2235
2236 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2237 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2238}
2239
8c8661e4
BH		 2240
2241/**************************************************************************
2242 *
2243 * Falcon test code
2244 *
2245 **************************************************************************/
2246
2247int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2248{
2249 struct falcon_nvconfig *nvconfig;
2250 struct efx_spi_device *spi;
2251 void *region;
2252 int rc, magic_num, struct_ver;
2253 __le16 *word, *limit;
2254 u32 csum;
2255
0a95f563 2256 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
8c8661e4
BH		 2257 if (!region)
2258 return -ENOMEM;
2259 nvconfig = region + NVCONFIG_OFFSET;
2260
2261 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
f4150724 2262 mutex_lock(&efx->spi_lock);
0a95f563 2263 rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region);
f4150724 2264 mutex_unlock(&efx->spi_lock);
8c8661e4
BH		 2265 if (rc) {
2266 EFX_ERR(efx, "Failed to read %s\n",
2267 efx->spi_flash ? "flash" : "EEPROM");
2268 rc = -EIO;
2269 goto out;
2270 }
2271
2272 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2273 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2274
2275 rc = -EINVAL;
2276 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2277 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2278 goto out;
2279 }
2280 if (struct_ver < 2) {
2281 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2282 goto out;
2283 } else if (struct_ver < 4) {
2284 word = &nvconfig->board_magic_num;
2285 limit = (__le16 *) (nvconfig + 1);
2286 } else {
2287 word = region;
0a95f563 2288 limit = region + FALCON_NVCONFIG_END;
8c8661e4
BH		 2289 }
2290 for (csum = 0; word < limit; ++word)
2291 csum += le16_to_cpu(*word);
2292
2293 if (~csum & 0xffff) {
2294 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2295 goto out;
2296 }
2297
2298 rc = 0;
2299 if (nvconfig_out)
2300 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2301
2302 out:
2303 kfree(region);
2304 return rc;
2305}
2306
2307/* Registers tested in the falcon register test */
2308static struct {
2309 unsigned address;
2310 efx_oword_t mask;
2311} efx_test_registers[] = {
2312 { ADR_REGION_REG_KER,
2313 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2314 { RX_CFG_REG_KER,
2315 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2316 { TX_CFG_REG_KER,
2317 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2318 { TX_CFG2_REG_KER,
2319 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2320 { MAC0_CTRL_REG_KER,
2321 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2322 { SRM_TX_DC_CFG_REG_KER,
2323 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2324 { RX_DC_CFG_REG_KER,
2325 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2326 { RX_DC_PF_WM_REG_KER,
2327 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2328 { DP_CTRL_REG,
2329 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2330 { XM_GLB_CFG_REG,
2331 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2332 { XM_TX_CFG_REG,
2333 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2334 { XM_RX_CFG_REG,
2335 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2336 { XM_RX_PARAM_REG,
2337 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2338 { XM_FC_REG,
2339 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2340 { XM_ADR_LO_REG,
2341 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2342 { XX_SD_CTL_REG,
2343 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2344};
2345
2346static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2347 const efx_oword_t *mask)
2348{
2349 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2350 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2351}
2352
2353int falcon_test_registers(struct efx_nic *efx)
2354{
2355 unsigned address = 0, i, j;
2356 efx_oword_t mask, imask, original, reg, buf;
2357
2358 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2359 WARN_ON(!LOOPBACK_INTERNAL(efx));
2360
2361 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2362 address = efx_test_registers[i].address;
2363 mask = imask = efx_test_registers[i].mask;
2364 EFX_INVERT_OWORD(imask);
2365
2366 falcon_read(efx, &original, address);
2367
2368 /* bit sweep on and off */
2369 for (j = 0; j < 128; j++) {
2370 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2371 continue;
2372
2373 /* Test this testable bit can be set in isolation */
2374 EFX_AND_OWORD(reg, original, mask);
2375 EFX_SET_OWORD32(reg, j, j, 1);
2376
2377 falcon_write(efx, &reg, address);
2378 falcon_read(efx, &buf, address);
2379
2380 if (efx_masked_compare_oword(&reg, &buf, &mask))
2381 goto fail;
2382
2383 /* Test this testable bit can be cleared in isolation */
2384 EFX_OR_OWORD(reg, original, mask);
2385 EFX_SET_OWORD32(reg, j, j, 0);
2386
2387 falcon_write(efx, &reg, address);
2388 falcon_read(efx, &buf, address);
2389
2390 if (efx_masked_compare_oword(&reg, &buf, &mask))
2391 goto fail;
2392 }
2393
2394 falcon_write(efx, &original, address);
2395 }
2396
2397 return 0;
2398
2399fail:
2400 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2401 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2402 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2403 return -EIO;
2404}
2405
8ceee660
BH		 2406/**************************************************************************
2407 *
2408 * Device reset
2409 *
2410 **************************************************************************
2411 */
2412
2413/* Resets NIC to known state. This routine must be called in process
2414 * context and is allowed to sleep. */
2415int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2416{
2417 struct falcon_nic_data *nic_data = efx->nic_data;
2418 efx_oword_t glb_ctl_reg_ker;
2419 int rc;
2420
2421 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2422
2423 /* Initiate device reset */
2424 if (method == RESET_TYPE_WORLD) {
2425 rc = pci_save_state(efx->pci_dev);
2426 if (rc) {
2427 EFX_ERR(efx, "failed to backup PCI state of primary "
2428 "function prior to hardware reset\n");
2429 goto fail1;
2430 }
2431 if (FALCON_IS_DUAL_FUNC(efx)) {
2432 rc = pci_save_state(nic_data->pci_dev2);
2433 if (rc) {
2434 EFX_ERR(efx, "failed to backup PCI state of "
2435 "secondary function prior to "
2436 "hardware reset\n");
2437 goto fail2;
2438 }
2439 }
2440
2441 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2442 EXT_PHY_RST_DUR, 0x7,
2443 SWRST, 1);
2444 } else {
2445 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2446 EXCLUDE_FROM_RESET : 0);
2447
2448 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2449 EXT_PHY_RST_CTL, reset_phy,
2450 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2451 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2452 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2453 EE_RST_CTL, EXCLUDE_FROM_RESET,
2454 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2455 SWRST, 1);
2456 }
2457 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2458
2459 EFX_LOG(efx, "waiting for hardware reset\n");
2460 schedule_timeout_uninterruptible(HZ / 20);
2461
2462 /* Restore PCI configuration if needed */
2463 if (method == RESET_TYPE_WORLD) {
2464 if (FALCON_IS_DUAL_FUNC(efx)) {
2465 rc = pci_restore_state(nic_data->pci_dev2);
2466 if (rc) {
2467 EFX_ERR(efx, "failed to restore PCI config for "
2468 "the secondary function\n");
2469 goto fail3;
2470 }
2471 }
2472 rc = pci_restore_state(efx->pci_dev);
2473 if (rc) {
2474 EFX_ERR(efx, "failed to restore PCI config for the "
2475 "primary function\n");
2476 goto fail4;
2477 }
2478 EFX_LOG(efx, "successfully restored PCI config\n");
2479 }
2480
2481 /* Assert that reset complete */
2482 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2483 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2484 rc = -ETIMEDOUT;
2485 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2486 goto fail5;
2487 }
2488 EFX_LOG(efx, "hardware reset complete\n");
2489
2490 return 0;
2491
2492 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2493fail2:
2494fail3:
2495 pci_restore_state(efx->pci_dev);
2496fail1:
2497fail4:
2498fail5:
2499 return rc;
2500}
2501
2502/* Zeroes out the SRAM contents. This routine must be called in
2503 * process context and is allowed to sleep.
2504 */
2505static int falcon_reset_sram(struct efx_nic *efx)
2506{
2507 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2508 int count;
2509
2510 /* Set the SRAM wake/sleep GPIO appropriately. */
2511 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2512 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2513 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2514 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2515
2516 /* Initiate SRAM reset */
2517 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2518 SRAM_OOB_BT_INIT_EN, 1,
2519 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2520 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2521
2522 /* Wait for SRAM reset to complete */
2523 count = 0;
2524 do {
2525 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2526
2527 /* SRAM reset is slow; expect around 16ms */
2528 schedule_timeout_uninterruptible(HZ / 50);
2529
2530 /* Check for reset complete */
2531 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2532 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2533 EFX_LOG(efx, "SRAM reset complete\n");
2534
2535 return 0;
2536 }
2537 } while (++count < 20); /* wait upto 0.4 sec */
2538
2539 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2540 return -ETIMEDOUT;
2541}
2542
4a5b504d
BH		 2543static int falcon_spi_device_init(struct efx_nic *efx,
2544 struct efx_spi_device **spi_device_ret,
2545 unsigned int device_id, u32 device_type)
2546{
2547 struct efx_spi_device *spi_device;
2548
2549 if (device_type != 0) {
2550 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2551 if (!spi_device)
2552 return -ENOMEM;
2553 spi_device->device_id = device_id;
2554 spi_device->size =
2555 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2556 spi_device->addr_len =
2557 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2558 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2559 spi_device->addr_len == 1);
f4150724
BH		 2560 spi_device->erase_command =
2561 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
2562 spi_device->erase_size =
2563 1 << SPI_DEV_TYPE_FIELD(device_type,
2564 SPI_DEV_TYPE_ERASE_SIZE);
4a5b504d
BH		 2565 spi_device->block_size =
2566 1 << SPI_DEV_TYPE_FIELD(device_type,
2567 SPI_DEV_TYPE_BLOCK_SIZE);
2568
2569 spi_device->efx = efx;
2570 } else {
2571 spi_device = NULL;
2572 }
2573
2574 kfree(*spi_device_ret);
2575 *spi_device_ret = spi_device;
2576 return 0;
2577}
2578
2579
2580static void falcon_remove_spi_devices(struct efx_nic *efx)
2581{
2582 kfree(efx->spi_eeprom);
2583 efx->spi_eeprom = NULL;
2584 kfree(efx->spi_flash);
2585 efx->spi_flash = NULL;
2586}
2587
8ceee660
BH		 2588/* Extract non-volatile configuration */
2589static int falcon_probe_nvconfig(struct efx_nic *efx)
2590{
2591 struct falcon_nvconfig *nvconfig;
8c8661e4 2592 int board_rev;
8ceee660
BH		 2593 int rc;
2594
8ceee660 2595 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
4a5b504d
BH		 2596 if (!nvconfig)
2597 return -ENOMEM;
8ceee660 2598
8c8661e4
BH		 2599 rc = falcon_read_nvram(efx, nvconfig);
2600 if (rc == -EINVAL) {
2601 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
8ceee660
BH		 2602 efx->phy_type = PHY_TYPE_NONE;
2603 efx->mii.phy_id = PHY_ADDR_INVALID;
2604 board_rev = 0;
8c8661e4
BH		 2605 rc = 0;
2606 } else if (rc) {
2607 goto fail1;
8ceee660
BH		 2608 } else {
2609 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
4a5b504d 2610 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
8ceee660
BH		 2611
2612 efx->phy_type = v2->port0_phy_type;
2613 efx->mii.phy_id = v2->port0_phy_addr;
2614 board_rev = le16_to_cpu(v2->board_revision);
4a5b504d 2615
8c8661e4 2616 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
4a5b504d
BH		 2617 __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2618 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2619 rc = falcon_spi_device_init(efx, &efx->spi_flash,
2620 EE_SPI_FLASH,
2621 le32_to_cpu(fl));
2622 if (rc)
2623 goto fail2;
2624 rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2625 EE_SPI_EEPROM,
2626 le32_to_cpu(ee));
2627 if (rc)
2628 goto fail2;
2629 }
8ceee660
BH		 2630 }
2631
8c8661e4
BH		 2632 /* Read the MAC addresses */
2633 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2634
8ceee660
BH		 2635 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2636
2637 efx_set_board_info(efx, board_rev);
2638
4a5b504d
BH		 2639 kfree(nvconfig);
2640 return 0;
2641
2642 fail2:
2643 falcon_remove_spi_devices(efx);
2644 fail1:
8ceee660
BH		 2645 kfree(nvconfig);
2646 return rc;
2647}
2648
2649/* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2650 * count, port speed). Set workaround and feature flags accordingly.
2651 */
2652static int falcon_probe_nic_variant(struct efx_nic *efx)
2653{
2654 efx_oword_t altera_build;
2655
2656 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2657 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2658 EFX_ERR(efx, "Falcon FPGA not supported\n");
2659 return -ENODEV;
2660 }
2661
55668611 2662 switch (falcon_rev(efx)) {
8ceee660
BH		 2663 case FALCON_REV_A0:
2664 case 0xff:
2665 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2666 return -ENODEV;
2667
2668 case FALCON_REV_A1:{
2669 efx_oword_t nic_stat;
2670
2671 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2672
2673 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2674 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2675 return -ENODEV;
2676 }
2677 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2678 EFX_ERR(efx, "1G mode not supported\n");
2679 return -ENODEV;
2680 }
2681 break;
2682 }
2683
2684 case FALCON_REV_B0:
2685 break;
2686
2687 default:
55668611 2688 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
8ceee660
BH		 2689 return -ENODEV;
2690 }
2691
2692 return 0;
2693}
2694
4a5b504d
BH		 2695/* Probe all SPI devices on the NIC */
2696static void falcon_probe_spi_devices(struct efx_nic *efx)
2697{
2698 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2699 bool has_flash, has_eeprom, boot_is_external;
2700
2701 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2702 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2703 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2704
2705 has_flash = EFX_OWORD_FIELD(nic_stat, SF_PRST);
2706 has_eeprom = EFX_OWORD_FIELD(nic_stat, EE_PRST);
2707 boot_is_external = EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE);
2708
2709 if (has_flash) {
2710 /* Default flash SPI device: Atmel AT25F1024
2711 * 128 KB, 24-bit address, 32 KB erase block,
2712 * 256 B write block
2713 */
2714 u32 flash_device_type =
2715 (17 << SPI_DEV_TYPE_SIZE_LBN)
2716 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2717 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
2718 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
2719 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2720
2721 falcon_spi_device_init(efx, &efx->spi_flash,
2722 EE_SPI_FLASH, flash_device_type);
2723
2724 if (!boot_is_external) {
2725 /* Disable VPD and set clock dividers to safe
2726 * values for initial programming.
2727 */
2728 EFX_LOG(efx, "Booted from internal ASIC settings;"
2729 " setting SPI config\n");
2730 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2731 /* 125 MHz / 7 ~= 20 MHz */
2732 EE_SF_CLOCK_DIV, 7,
2733 /* 125 MHz / 63 ~= 2 MHz */
2734 EE_EE_CLOCK_DIV, 63);
2735 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2736 }
2737 }
2738
2739 if (has_eeprom) {
2740 u32 eeprom_device_type;
2741
2742 /* If it has no flash, it must have a large EEPROM
2743 * for chip config; otherwise check whether 9-bit
2744 * addressing is used for VPD configuration
2745 */
2746 if (has_flash &&
2747 (!boot_is_external ||
2748 EFX_OWORD_FIELD(ee_vpd_cfg, EE_VPD_EN_AD9_MODE))) {
2749 /* Default SPI device: Atmel AT25040 or similar
2750 * 512 B, 9-bit address, 8 B write block
2751 */
2752 eeprom_device_type =
2753 (9 << SPI_DEV_TYPE_SIZE_LBN)
2754 | (1 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2755 | (3 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2756 } else {
2757 /* "Large" SPI device: Atmel AT25640 or similar
2758 * 8 KB, 16-bit address, 32 B write block
2759 */
2760 eeprom_device_type =
2761 (13 << SPI_DEV_TYPE_SIZE_LBN)
2762 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2763 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2764 }
2765
2766 falcon_spi_device_init(efx, &efx->spi_eeprom,
2767 EE_SPI_EEPROM, eeprom_device_type);
2768 }
2769
2770 EFX_LOG(efx, "flash is %s, EEPROM is %s\n",
2771 (has_flash ? "present" : "absent"),
2772 (has_eeprom ? "present" : "absent"));
2773}
2774
8ceee660
BH		 2775int falcon_probe_nic(struct efx_nic *efx)
2776{
2777 struct falcon_nic_data *nic_data;
2778 int rc;
2779
8ceee660
BH		 2780 /* Allocate storage for hardware specific data */
2781 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
88c59425
BH		 2782 if (!nic_data)
2783 return -ENOMEM;
5daab96d 2784 efx->nic_data = nic_data;
8ceee660
BH		 2785
2786 /* Determine number of ports etc. */
2787 rc = falcon_probe_nic_variant(efx);
2788 if (rc)
2789 goto fail1;
2790
2791 /* Probe secondary function if expected */
2792 if (FALCON_IS_DUAL_FUNC(efx)) {
2793 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2794
2795 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2796 dev))) {
2797 if (dev->bus == efx->pci_dev->bus &&
2798 dev->devfn == efx->pci_dev->devfn + 1) {
2799 nic_data->pci_dev2 = dev;
2800 break;
2801 }
2802 }
2803 if (!nic_data->pci_dev2) {
2804 EFX_ERR(efx, "failed to find secondary function\n");
2805 rc = -ENODEV;
2806 goto fail2;
2807 }
2808 }
2809
2810 /* Now we can reset the NIC */
2811 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2812 if (rc) {
2813 EFX_ERR(efx, "failed to reset NIC\n");
2814 goto fail3;
2815 }
2816
2817 /* Allocate memory for INT_KER */
2818 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2819 if (rc)
2820 goto fail4;
2821 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2822
2823 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2824 (unsigned long long)efx->irq_status.dma_addr,
2825 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2826
4a5b504d
BH		 2827 falcon_probe_spi_devices(efx);
2828
8ceee660
BH		 2829 /* Read in the non-volatile configuration */
2830 rc = falcon_probe_nvconfig(efx);
2831 if (rc)
2832 goto fail5;
2833
37b5a603
BH		 2834 /* Initialise I2C adapter */
2835 efx->i2c_adap.owner = THIS_MODULE;
37b5a603
BH		 2836 nic_data->i2c_data = falcon_i2c_bit_operations;
2837 nic_data->i2c_data.data = efx;
2838 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2839 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
9dadae68 2840 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
37b5a603
BH		 2841 rc = i2c_bit_add_bus(&efx->i2c_adap);
2842 if (rc)
2843 goto fail5;
2844
8ceee660
BH		 2845 return 0;
2846
2847 fail5:
4a5b504d 2848 falcon_remove_spi_devices(efx);
8ceee660
BH		 2849 falcon_free_buffer(efx, &efx->irq_status);
2850 fail4:
8ceee660
BH		 2851 fail3:
2852 if (nic_data->pci_dev2) {
2853 pci_dev_put(nic_data->pci_dev2);
2854 nic_data->pci_dev2 = NULL;
2855 }
2856 fail2:
8ceee660
BH		 2857 fail1:
2858 kfree(efx->nic_data);
2859 return rc;
2860}
2861
2862/* This call performs hardware-specific global initialisation, such as
2863 * defining the descriptor cache sizes and number of RSS channels.
2864 * It does not set up any buffers, descriptor rings or event queues.
2865 */
2866int falcon_init_nic(struct efx_nic *efx)
2867{
8ceee660
BH		 2868 efx_oword_t temp;
2869 unsigned thresh;
2870 int rc;
2871
8ceee660
BH		 2872 /* Set up the address region register. This is only needed
2873 * for the B0 FPGA, but since we are just pushing in the
2874 * reset defaults this may as well be unconditional. */
2875 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2876 ADR_REGION1, (1 << 16),
2877 ADR_REGION2, (2 << 16),
2878 ADR_REGION3, (3 << 16));
2879 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2880
2881 /* Use on-chip SRAM */
2882 falcon_read(efx, &temp, NIC_STAT_REG);
2883 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2884 falcon_write(efx, &temp, NIC_STAT_REG);
2885
2886 /* Set buffer table mode */
2887 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2888 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2889
2890 rc = falcon_reset_sram(efx);
2891 if (rc)
2892 return rc;
2893
2894 /* Set positions of descriptor caches in SRAM. */
2895 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2896 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2897 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2898 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2899
2900 /* Set TX descriptor cache size. */
2901 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2902 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2903 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2904
2905 /* Set RX descriptor cache size. Set low watermark to size-8, as
2906 * this allows most efficient prefetching.
2907 */
2908 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2909 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2910 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2911 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2912 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2913
2914 /* Clear the parity enables on the TX data fifos as
2915 * they produce false parity errors because of timing issues
2916 */
2917 if (EFX_WORKAROUND_5129(efx)) {
2918 falcon_read(efx, &temp, SPARE_REG_KER);
2919 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2920 falcon_write(efx, &temp, SPARE_REG_KER);
2921 }
2922
2923 /* Enable all the genuinely fatal interrupts. (They are still
2924 * masked by the overall interrupt mask, controlled by
2925 * falcon_interrupts()).
2926 *
2927 * Note: All other fatal interrupts are enabled
2928 */
2929 EFX_POPULATE_OWORD_3(temp,
2930 ILL_ADR_INT_KER_EN, 1,
2931 RBUF_OWN_INT_KER_EN, 1,
2932 TBUF_OWN_INT_KER_EN, 1);
2933 EFX_INVERT_OWORD(temp);
2934 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2935
8ceee660 2936 if (EFX_WORKAROUND_7244(efx)) {
955f0a74 2937 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
8ceee660
BH		 2938 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2939 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2940 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2941 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
955f0a74 2942 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
8ceee660 2943 }
8ceee660
BH		 2944
2945 falcon_setup_rss_indir_table(efx);
2946
2947 /* Setup RX. Wait for descriptor is broken and must
2948 * be disabled. RXDP recovery shouldn't be needed, but is.
2949 */
2950 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2951 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2952 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2953 if (EFX_WORKAROUND_5583(efx))
2954 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2955 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2956
2957 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2958 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2959 */
2960 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2961 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2962 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2963 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2964 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2965 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2966 /* Enable SW_EV to inherit in char driver - assume harmless here */
2967 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2968 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2969 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2970 /* Squash TX of packets of 16 bytes or less */
55668611 2971 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
8ceee660
BH		 2972 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2973 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2974
2975 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2976 * descriptors (which is bad).
2977 */
2978 falcon_read(efx, &temp, TX_CFG_REG_KER);
2979 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2980 falcon_write(efx, &temp, TX_CFG_REG_KER);
2981
2982 /* RX config */
2983 falcon_read(efx, &temp, RX_CFG_REG_KER);
2984 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2985 if (EFX_WORKAROUND_7575(efx))
2986 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2987 (3 * 4096) / 32);
55668611 2988 if (falcon_rev(efx) >= FALCON_REV_B0)
8ceee660
BH		 2989 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2990
2991 /* RX FIFO flow control thresholds */
2992 thresh = ((rx_xon_thresh_bytes >= 0) ?
2993 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2994 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2995 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2996 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2997 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2998 /* RX control FIFO thresholds [32 entries] */
c84a6f18
BH		 2999 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
3000 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
8ceee660
BH		 3001 falcon_write(efx, &temp, RX_CFG_REG_KER);
3002
3003 /* Set destination of both TX and RX Flush events */
55668611 3004 if (falcon_rev(efx) >= FALCON_REV_B0) {
8ceee660
BH		 3005 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
3006 falcon_write(efx, &temp, DP_CTRL_REG);
3007 }
3008
3009 return 0;
3010}
3011
3012void falcon_remove_nic(struct efx_nic *efx)
3013{
3014 struct falcon_nic_data *nic_data = efx->nic_data;
37b5a603
BH		 3015 int rc;
3016
3017 rc = i2c_del_adapter(&efx->i2c_adap);
3018 BUG_ON(rc);
8ceee660 3019
4a5b504d 3020 falcon_remove_spi_devices(efx);
8ceee660
BH		 3021 falcon_free_buffer(efx, &efx->irq_status);
3022
91ad757c 3023 falcon_reset_hw(efx, RESET_TYPE_ALL);
8ceee660
BH		 3024
3025 /* Release the second function after the reset */
3026 if (nic_data->pci_dev2) {
3027 pci_dev_put(nic_data->pci_dev2);
3028 nic_data->pci_dev2 = NULL;
3029 }
3030
3031 /* Tear down the private nic state */
3032 kfree(efx->nic_data);
3033 efx->nic_data = NULL;
3034}
3035
3036void falcon_update_nic_stats(struct efx_nic *efx)
3037{
3038 efx_oword_t cnt;
3039
3040 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3041 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3042}
3043
3044/**************************************************************************
3045 *
3046 * Revision-dependent attributes used by efx.c
3047 *
3048 **************************************************************************
3049 */
3050
3051struct efx_nic_type falcon_a_nic_type = {
3052 .mem_bar = 2,
3053 .mem_map_size = 0x20000,
3054 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3055 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3056 .buf_tbl_base = BUF_TBL_KER_A1,
3057 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3058 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3059 .txd_ring_mask = FALCON_TXD_RING_MASK,
3060 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3061 .evq_size = FALCON_EVQ_SIZE,
3062 .max_dma_mask = FALCON_DMA_MASK,
3063 .tx_dma_mask = FALCON_TX_DMA_MASK,
3064 .bug5391_mask = 0xf,
3065 .rx_xoff_thresh = 2048,
3066 .rx_xon_thresh = 512,
3067 .rx_buffer_padding = 0x24,
3068 .max_interrupt_mode = EFX_INT_MODE_MSI,
3069 .phys_addr_channels = 4,
3070};
3071
3072struct efx_nic_type falcon_b_nic_type = {
3073 .mem_bar = 2,
3074 /* Map everything up to and including the RSS indirection
3075 * table. Don't map MSI-X table, MSI-X PBA since Linux
3076 * requires that they not be mapped. */
3077 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3078 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3079 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3080 .buf_tbl_base = BUF_TBL_KER_B0,
3081 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3082 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3083 .txd_ring_mask = FALCON_TXD_RING_MASK,
3084 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3085 .evq_size = FALCON_EVQ_SIZE,
3086 .max_dma_mask = FALCON_DMA_MASK,
3087 .tx_dma_mask = FALCON_TX_DMA_MASK,
3088 .bug5391_mask = 0,
3089 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3090 .rx_xon_thresh = 27648, /* ~3*max MTU */
3091 .rx_buffer_padding = 0,
3092 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3093 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3094 * interrupt handler only supports 32
3095 * channels */
3096};
3097
Linux kernel - Deliverables
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