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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/delay.h> | |
12 | #include "net_driver.h" | |
13 | #include "efx.h" | |
14 | #include "falcon.h" | |
15 | #include "falcon_hwdefs.h" | |
16 | #include "falcon_io.h" | |
17 | #include "mac.h" | |
18 | #include "gmii.h" | |
19 | #include "mdio_10g.h" | |
20 | #include "phy.h" | |
21 | #include "boards.h" | |
22 | #include "workarounds.h" | |
23 | ||
8ceee660 BH |
24 | /************************************************************************** |
25 | * | |
26 | * MAC operations | |
27 | * | |
28 | *************************************************************************/ | |
29 | static int falcon_reset_xmac(struct efx_nic *efx) | |
30 | { | |
c1e5fcc9 | 31 | efx_oword_t reg; |
8ceee660 BH |
32 | int count; |
33 | ||
c1e5fcc9 BH |
34 | EFX_POPULATE_OWORD_1(reg, XM_CORE_RST, 1); |
35 | falcon_write(efx, ®, XM_GLB_CFG_REG); | |
8ceee660 BH |
36 | |
37 | for (count = 0; count < 10000; count++) { /* wait upto 100ms */ | |
c1e5fcc9 BH |
38 | falcon_read(efx, ®, XM_GLB_CFG_REG); |
39 | if (EFX_OWORD_FIELD(reg, XM_CORE_RST) == 0) | |
8ceee660 BH |
40 | return 0; |
41 | udelay(10); | |
42 | } | |
43 | ||
44 | EFX_ERR(efx, "timed out waiting for XMAC core reset\n"); | |
45 | return -ETIMEDOUT; | |
46 | } | |
47 | ||
48 | /* Configure the XAUI driver that is an output from Falcon */ | |
49 | static void falcon_setup_xaui(struct efx_nic *efx) | |
50 | { | |
c1e5fcc9 | 51 | efx_oword_t sdctl, txdrv; |
8ceee660 BH |
52 | |
53 | /* Move the XAUI into low power, unless there is no PHY, in | |
54 | * which case the XAUI will have to drive a cable. */ | |
55 | if (efx->phy_type == PHY_TYPE_NONE) | |
56 | return; | |
57 | ||
c1e5fcc9 BH |
58 | falcon_read(efx, &sdctl, XX_SD_CTL_REG); |
59 | EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT); | |
60 | EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT); | |
61 | EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT); | |
62 | EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT); | |
63 | EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT); | |
64 | EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT); | |
65 | EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT); | |
66 | EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT); | |
67 | falcon_write(efx, &sdctl, XX_SD_CTL_REG); | |
68 | ||
69 | EFX_POPULATE_OWORD_8(txdrv, | |
8ceee660 BH |
70 | XX_DEQD, XX_TXDRV_DEQ_DEFAULT, |
71 | XX_DEQC, XX_TXDRV_DEQ_DEFAULT, | |
72 | XX_DEQB, XX_TXDRV_DEQ_DEFAULT, | |
73 | XX_DEQA, XX_TXDRV_DEQ_DEFAULT, | |
74 | XX_DTXD, XX_TXDRV_DTX_DEFAULT, | |
75 | XX_DTXC, XX_TXDRV_DTX_DEFAULT, | |
76 | XX_DTXB, XX_TXDRV_DTX_DEFAULT, | |
77 | XX_DTXA, XX_TXDRV_DTX_DEFAULT); | |
c1e5fcc9 | 78 | falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG); |
8ceee660 BH |
79 | } |
80 | ||
81 | static void falcon_hold_xaui_in_rst(struct efx_nic *efx) | |
82 | { | |
c1e5fcc9 BH |
83 | efx_oword_t reg; |
84 | ||
85 | EFX_ZERO_OWORD(reg); | |
86 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 1); | |
87 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 1); | |
88 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 1); | |
89 | EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 1); | |
90 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 1); | |
91 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 1); | |
92 | EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 1); | |
93 | EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 1); | |
94 | EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 1); | |
95 | EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 1); | |
96 | EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1); | |
97 | EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1); | |
98 | falcon_write(efx, ®, XX_PWR_RST_REG); | |
8ceee660 BH |
99 | udelay(10); |
100 | } | |
101 | ||
102 | static int _falcon_reset_xaui_a(struct efx_nic *efx) | |
103 | { | |
c1e5fcc9 | 104 | efx_oword_t reg; |
8ceee660 BH |
105 | |
106 | falcon_hold_xaui_in_rst(efx); | |
c1e5fcc9 | 107 | falcon_read(efx, ®, XX_PWR_RST_REG); |
8ceee660 BH |
108 | |
109 | /* Follow the RAMBUS XAUI data reset sequencing | |
110 | * Channels A and B first: power down, reset PLL, reset, clear | |
111 | */ | |
c1e5fcc9 BH |
112 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 0); |
113 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 0); | |
114 | falcon_write(efx, ®, XX_PWR_RST_REG); | |
8ceee660 BH |
115 | udelay(10); |
116 | ||
c1e5fcc9 BH |
117 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 0); |
118 | falcon_write(efx, ®, XX_PWR_RST_REG); | |
8ceee660 BH |
119 | udelay(10); |
120 | ||
c1e5fcc9 BH |
121 | EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 0); |
122 | EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 0); | |
123 | falcon_write(efx, ®, XX_PWR_RST_REG); | |
8ceee660 BH |
124 | udelay(10); |
125 | ||
126 | /* Channels C and D: power down, reset PLL, reset, clear */ | |
c1e5fcc9 BH |
127 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 0); |
128 | EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 0); | |
129 | falcon_write(efx, ®, XX_PWR_RST_REG); | |
8ceee660 BH |
130 | udelay(10); |
131 | ||
c1e5fcc9 BH |
132 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 0); |
133 | falcon_write(efx, ®, XX_PWR_RST_REG); | |
8ceee660 BH |
134 | udelay(10); |
135 | ||
c1e5fcc9 BH |
136 | EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 0); |
137 | EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 0); | |
138 | falcon_write(efx, ®, XX_PWR_RST_REG); | |
8ceee660 BH |
139 | udelay(10); |
140 | ||
141 | /* Setup XAUI */ | |
142 | falcon_setup_xaui(efx); | |
143 | udelay(10); | |
144 | ||
145 | /* Take XGXS out of reset */ | |
c1e5fcc9 BH |
146 | EFX_ZERO_OWORD(reg); |
147 | falcon_write(efx, ®, XX_PWR_RST_REG); | |
8ceee660 BH |
148 | udelay(10); |
149 | ||
150 | return 0; | |
151 | } | |
152 | ||
153 | static int _falcon_reset_xaui_b(struct efx_nic *efx) | |
154 | { | |
c1e5fcc9 | 155 | efx_oword_t reg; |
8ceee660 BH |
156 | int count; |
157 | ||
158 | EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1); | |
c1e5fcc9 | 159 | falcon_write(efx, ®, XX_PWR_RST_REG); |
8ceee660 BH |
160 | |
161 | /* Give some time for the link to establish */ | |
162 | for (count = 0; count < 1000; count++) { /* wait upto 10ms */ | |
c1e5fcc9 BH |
163 | falcon_read(efx, ®, XX_PWR_RST_REG); |
164 | if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0) { | |
8ceee660 BH |
165 | falcon_setup_xaui(efx); |
166 | return 0; | |
167 | } | |
168 | udelay(10); | |
169 | } | |
170 | EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n"); | |
171 | return -ETIMEDOUT; | |
172 | } | |
173 | ||
174 | int falcon_reset_xaui(struct efx_nic *efx) | |
175 | { | |
176 | int rc; | |
177 | ||
178 | if (EFX_WORKAROUND_9388(efx)) { | |
179 | falcon_hold_xaui_in_rst(efx); | |
180 | efx->phy_op->reset_xaui(efx); | |
181 | rc = _falcon_reset_xaui_a(efx); | |
182 | } else { | |
183 | rc = _falcon_reset_xaui_b(efx); | |
184 | } | |
185 | return rc; | |
186 | } | |
187 | ||
dc8cfa55 | 188 | static bool falcon_xgmii_status(struct efx_nic *efx) |
8ceee660 | 189 | { |
c1e5fcc9 | 190 | efx_oword_t reg; |
8ceee660 | 191 | |
55668611 | 192 | if (falcon_rev(efx) < FALCON_REV_B0) |
dc8cfa55 | 193 | return true; |
8ceee660 BH |
194 | |
195 | /* The ISR latches, so clear it and re-read */ | |
c1e5fcc9 BH |
196 | falcon_read(efx, ®, XM_MGT_INT_REG_B0); |
197 | falcon_read(efx, ®, XM_MGT_INT_REG_B0); | |
e52eddae | 198 | |
c1e5fcc9 BH |
199 | if (EFX_OWORD_FIELD(reg, XM_LCLFLT) || |
200 | EFX_OWORD_FIELD(reg, XM_RMTFLT)) { | |
8ceee660 | 201 | EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg)); |
dc8cfa55 | 202 | return false; |
8ceee660 BH |
203 | } |
204 | ||
dc8cfa55 | 205 | return true; |
8ceee660 BH |
206 | } |
207 | ||
dc8cfa55 | 208 | static void falcon_mask_status_intr(struct efx_nic *efx, bool enable) |
8ceee660 | 209 | { |
c1e5fcc9 | 210 | efx_oword_t reg; |
8ceee660 | 211 | |
55668611 | 212 | if ((falcon_rev(efx) < FALCON_REV_B0) || LOOPBACK_INTERNAL(efx)) |
8ceee660 BH |
213 | return; |
214 | ||
215 | /* Flush the ISR */ | |
216 | if (enable) | |
c1e5fcc9 | 217 | falcon_read(efx, ®, XM_MGT_INT_REG_B0); |
8ceee660 | 218 | |
c1e5fcc9 | 219 | EFX_POPULATE_OWORD_2(reg, |
8ceee660 BH |
220 | XM_MSK_RMTFLT, !enable, |
221 | XM_MSK_LCLFLT, !enable); | |
c1e5fcc9 | 222 | falcon_write(efx, ®, XM_MGT_INT_MSK_REG_B0); |
8ceee660 BH |
223 | } |
224 | ||
225 | int falcon_init_xmac(struct efx_nic *efx) | |
226 | { | |
227 | int rc; | |
228 | ||
229 | /* Initialize the PHY first so the clock is around */ | |
230 | rc = efx->phy_op->init(efx); | |
231 | if (rc) | |
232 | goto fail1; | |
233 | ||
234 | rc = falcon_reset_xaui(efx); | |
235 | if (rc) | |
236 | goto fail2; | |
237 | ||
238 | /* Wait again. Give the PHY and MAC time to come back */ | |
239 | schedule_timeout_uninterruptible(HZ / 10); | |
240 | ||
241 | rc = falcon_reset_xmac(efx); | |
242 | if (rc) | |
243 | goto fail2; | |
244 | ||
dc8cfa55 | 245 | falcon_mask_status_intr(efx, true); |
8ceee660 BH |
246 | return 0; |
247 | ||
248 | fail2: | |
249 | efx->phy_op->fini(efx); | |
250 | fail1: | |
251 | return rc; | |
252 | } | |
253 | ||
dc8cfa55 | 254 | bool falcon_xaui_link_ok(struct efx_nic *efx) |
8ceee660 | 255 | { |
c1e5fcc9 | 256 | efx_oword_t reg; |
dc8cfa55 BH |
257 | bool align_done, link_ok = false; |
258 | int sync_status; | |
8ceee660 | 259 | |
3273c2e8 | 260 | if (LOOPBACK_INTERNAL(efx)) |
dc8cfa55 | 261 | return true; |
3273c2e8 | 262 | |
8ceee660 | 263 | /* Read link status */ |
c1e5fcc9 | 264 | falcon_read(efx, ®, XX_CORE_STAT_REG); |
8ceee660 | 265 | |
c1e5fcc9 BH |
266 | align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE); |
267 | sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT); | |
8ceee660 | 268 | if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED)) |
dc8cfa55 | 269 | link_ok = true; |
8ceee660 BH |
270 | |
271 | /* Clear link status ready for next read */ | |
c1e5fcc9 BH |
272 | EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET); |
273 | EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET); | |
274 | EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET); | |
275 | falcon_write(efx, ®, XX_CORE_STAT_REG); | |
8ceee660 BH |
276 | |
277 | /* If the link is up, then check the phy side of the xaui link | |
278 | * (error conditions from the wire side propoagate back through | |
279 | * the phy to the xaui side). */ | |
280 | if (efx->link_up && link_ok) { | |
dc8cfa55 | 281 | if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS)) |
8ceee660 BH |
282 | link_ok = mdio_clause45_phyxgxs_lane_sync(efx); |
283 | } | |
284 | ||
285 | /* If the PHY and XAUI links are up, then check the mac's xgmii | |
286 | * fault state */ | |
287 | if (efx->link_up && link_ok) | |
288 | link_ok = falcon_xgmii_status(efx); | |
289 | ||
290 | return link_ok; | |
291 | } | |
292 | ||
293 | static void falcon_reconfigure_xmac_core(struct efx_nic *efx) | |
294 | { | |
295 | unsigned int max_frame_len; | |
c1e5fcc9 | 296 | efx_oword_t reg; |
dc8cfa55 | 297 | bool rx_fc = !!(efx->flow_control & EFX_FC_RX); |
8ceee660 BH |
298 | |
299 | /* Configure MAC - cut-thru mode is hard wired on */ | |
300 | EFX_POPULATE_DWORD_3(reg, | |
301 | XM_RX_JUMBO_MODE, 1, | |
302 | XM_TX_STAT_EN, 1, | |
303 | XM_RX_STAT_EN, 1); | |
c1e5fcc9 | 304 | falcon_write(efx, ®, XM_GLB_CFG_REG); |
8ceee660 BH |
305 | |
306 | /* Configure TX */ | |
307 | EFX_POPULATE_DWORD_6(reg, | |
308 | XM_TXEN, 1, | |
309 | XM_TX_PRMBL, 1, | |
310 | XM_AUTO_PAD, 1, | |
311 | XM_TXCRC, 1, | |
312 | XM_FCNTL, 1, | |
313 | XM_IPG, 0x3); | |
c1e5fcc9 | 314 | falcon_write(efx, ®, XM_TX_CFG_REG); |
8ceee660 BH |
315 | |
316 | /* Configure RX */ | |
317 | EFX_POPULATE_DWORD_5(reg, | |
318 | XM_RXEN, 1, | |
319 | XM_AUTO_DEPAD, 0, | |
320 | XM_ACPT_ALL_MCAST, 1, | |
321 | XM_ACPT_ALL_UCAST, efx->promiscuous, | |
322 | XM_PASS_CRC_ERR, 1); | |
c1e5fcc9 | 323 | falcon_write(efx, ®, XM_RX_CFG_REG); |
8ceee660 BH |
324 | |
325 | /* Set frame length */ | |
326 | max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); | |
327 | EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len); | |
c1e5fcc9 | 328 | falcon_write(efx, ®, XM_RX_PARAM_REG); |
8ceee660 BH |
329 | EFX_POPULATE_DWORD_2(reg, |
330 | XM_MAX_TX_FRM_SIZE, max_frame_len, | |
331 | XM_TX_JUMBO_MODE, 1); | |
c1e5fcc9 | 332 | falcon_write(efx, ®, XM_TX_PARAM_REG); |
8ceee660 BH |
333 | |
334 | EFX_POPULATE_DWORD_2(reg, | |
335 | XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ | |
dc8cfa55 | 336 | XM_DIS_FCNTL, !rx_fc); |
c1e5fcc9 | 337 | falcon_write(efx, ®, XM_FC_REG); |
8ceee660 BH |
338 | |
339 | /* Set MAC address */ | |
340 | EFX_POPULATE_DWORD_4(reg, | |
341 | XM_ADR_0, efx->net_dev->dev_addr[0], | |
342 | XM_ADR_1, efx->net_dev->dev_addr[1], | |
343 | XM_ADR_2, efx->net_dev->dev_addr[2], | |
344 | XM_ADR_3, efx->net_dev->dev_addr[3]); | |
c1e5fcc9 | 345 | falcon_write(efx, ®, XM_ADR_LO_REG); |
8ceee660 BH |
346 | EFX_POPULATE_DWORD_2(reg, |
347 | XM_ADR_4, efx->net_dev->dev_addr[4], | |
348 | XM_ADR_5, efx->net_dev->dev_addr[5]); | |
c1e5fcc9 | 349 | falcon_write(efx, ®, XM_ADR_HI_REG); |
8ceee660 BH |
350 | } |
351 | ||
3273c2e8 BH |
352 | static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) |
353 | { | |
c1e5fcc9 | 354 | efx_oword_t reg; |
dc8cfa55 BH |
355 | bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS); |
356 | bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI); | |
357 | bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII); | |
3273c2e8 BH |
358 | |
359 | /* XGXS block is flaky and will need to be reset if moving | |
360 | * into our out of XGMII, XGXS or XAUI loopbacks. */ | |
361 | if (EFX_WORKAROUND_5147(efx)) { | |
dc8cfa55 BH |
362 | bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; |
363 | bool reset_xgxs; | |
3273c2e8 | 364 | |
c1e5fcc9 BH |
365 | falcon_read(efx, ®, XX_CORE_STAT_REG); |
366 | old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN); | |
367 | old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN); | |
3273c2e8 | 368 | |
c1e5fcc9 BH |
369 | falcon_read(efx, ®, XX_SD_CTL_REG); |
370 | old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA); | |
3273c2e8 BH |
371 | |
372 | /* The PHY driver may have turned XAUI off */ | |
373 | reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) || | |
374 | (xaui_loopback != old_xaui_loopback) || | |
375 | (xgmii_loopback != old_xgmii_loopback)); | |
8c8661e4 BH |
376 | |
377 | if (reset_xgxs) | |
378 | falcon_reset_xaui(efx); | |
3273c2e8 BH |
379 | } |
380 | ||
c1e5fcc9 BH |
381 | falcon_read(efx, ®, XX_CORE_STAT_REG); |
382 | EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG, | |
3273c2e8 BH |
383 | (xgxs_loopback || xaui_loopback) ? |
384 | XX_FORCE_SIG_DECODE_FORCED : 0); | |
c1e5fcc9 BH |
385 | EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback); |
386 | EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback); | |
387 | falcon_write(efx, ®, XX_CORE_STAT_REG); | |
388 | ||
389 | falcon_read(efx, ®, XX_SD_CTL_REG); | |
390 | EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback); | |
391 | EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback); | |
392 | EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback); | |
393 | EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback); | |
394 | falcon_write(efx, ®, XX_SD_CTL_REG); | |
3273c2e8 BH |
395 | } |
396 | ||
397 | ||
8ceee660 BH |
398 | /* Try and bring the Falcon side of the Falcon-Phy XAUI link fails |
399 | * to come back up. Bash it until it comes back up */ | |
dc8cfa55 | 400 | static bool falcon_check_xaui_link_up(struct efx_nic *efx) |
8ceee660 BH |
401 | { |
402 | int max_tries, tries; | |
403 | tries = EFX_WORKAROUND_5147(efx) ? 5 : 1; | |
404 | max_tries = tries; | |
405 | ||
3273c2e8 | 406 | if ((efx->loopback_mode == LOOPBACK_NETWORK) || |
f8b87c17 BH |
407 | (efx->phy_type == PHY_TYPE_NONE) || |
408 | efx_phy_mode_disabled(efx->phy_mode)) | |
dc8cfa55 | 409 | return false; |
8ceee660 BH |
410 | |
411 | while (tries) { | |
412 | if (falcon_xaui_link_ok(efx)) | |
dc8cfa55 | 413 | return true; |
8ceee660 BH |
414 | |
415 | EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n", | |
416 | __func__, tries); | |
91ad757c | 417 | falcon_reset_xaui(efx); |
8ceee660 BH |
418 | udelay(200); |
419 | tries--; | |
420 | } | |
421 | ||
b055629e | 422 | EFX_LOG(efx, "Failed to bring XAUI link back up in %d tries!\n", |
8ceee660 | 423 | max_tries); |
dc8cfa55 | 424 | return false; |
8ceee660 BH |
425 | } |
426 | ||
427 | void falcon_reconfigure_xmac(struct efx_nic *efx) | |
428 | { | |
dc8cfa55 | 429 | bool xaui_link_ok; |
8ceee660 | 430 | |
dc8cfa55 | 431 | falcon_mask_status_intr(efx, false); |
8ceee660 BH |
432 | |
433 | falcon_deconfigure_mac_wrapper(efx); | |
3273c2e8 | 434 | |
f8b87c17 BH |
435 | /* Reconfigure the PHY, disabling transmit in mac level loopback. */ |
436 | if (LOOPBACK_INTERNAL(efx)) | |
437 | efx->phy_mode |= PHY_MODE_TX_DISABLED; | |
438 | else | |
439 | efx->phy_mode &= ~PHY_MODE_TX_DISABLED; | |
8ceee660 | 440 | efx->phy_op->reconfigure(efx); |
3273c2e8 BH |
441 | |
442 | falcon_reconfigure_xgxs_core(efx); | |
8ceee660 | 443 | falcon_reconfigure_xmac_core(efx); |
3273c2e8 | 444 | |
8ceee660 BH |
445 | falcon_reconfigure_mac_wrapper(efx); |
446 | ||
447 | /* Ensure XAUI link is up */ | |
448 | xaui_link_ok = falcon_check_xaui_link_up(efx); | |
449 | ||
450 | if (xaui_link_ok && efx->link_up) | |
dc8cfa55 | 451 | falcon_mask_status_intr(efx, true); |
8ceee660 BH |
452 | } |
453 | ||
454 | void falcon_fini_xmac(struct efx_nic *efx) | |
455 | { | |
456 | /* Isolate the MAC - PHY */ | |
457 | falcon_deconfigure_mac_wrapper(efx); | |
458 | ||
459 | /* Potentially power down the PHY */ | |
460 | efx->phy_op->fini(efx); | |
461 | } | |
462 | ||
463 | void falcon_update_stats_xmac(struct efx_nic *efx) | |
464 | { | |
465 | struct efx_mac_stats *mac_stats = &efx->mac_stats; | |
466 | int rc; | |
467 | ||
468 | rc = falcon_dma_stats(efx, XgDmaDone_offset); | |
469 | if (rc) | |
470 | return; | |
471 | ||
472 | /* Update MAC stats from DMAed values */ | |
473 | FALCON_STAT(efx, XgRxOctets, rx_bytes); | |
474 | FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes); | |
475 | FALCON_STAT(efx, XgRxPkts, rx_packets); | |
476 | FALCON_STAT(efx, XgRxPktsOK, rx_good); | |
477 | FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast); | |
478 | FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast); | |
479 | FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast); | |
480 | FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64); | |
481 | FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo); | |
482 | FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo); | |
483 | FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64); | |
484 | FALCON_STAT(efx, XgRxDropEvents, rx_overflow); | |
485 | FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad); | |
486 | FALCON_STAT(efx, XgRxAlignError, rx_align_error); | |
487 | FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error); | |
488 | FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error); | |
489 | FALCON_STAT(efx, XgRxControlPkts, rx_control); | |
490 | FALCON_STAT(efx, XgRxPausePkts, rx_pause); | |
491 | FALCON_STAT(efx, XgRxPkts64Octets, rx_64); | |
492 | FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127); | |
493 | FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255); | |
494 | FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511); | |
495 | FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023); | |
496 | FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx); | |
497 | FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo); | |
498 | FALCON_STAT(efx, XgRxLengthError, rx_length_error); | |
499 | FALCON_STAT(efx, XgTxPkts, tx_packets); | |
500 | FALCON_STAT(efx, XgTxOctets, tx_bytes); | |
501 | FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast); | |
502 | FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast); | |
503 | FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast); | |
504 | FALCON_STAT(efx, XgTxControlPkts, tx_control); | |
505 | FALCON_STAT(efx, XgTxPausePkts, tx_pause); | |
506 | FALCON_STAT(efx, XgTxPkts64Octets, tx_64); | |
507 | FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127); | |
508 | FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255); | |
509 | FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511); | |
510 | FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023); | |
511 | FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx); | |
512 | FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo); | |
513 | FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64); | |
514 | FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo); | |
515 | FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp); | |
516 | FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error); | |
517 | FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error); | |
518 | ||
519 | /* Update derived statistics */ | |
520 | mac_stats->tx_good_bytes = | |
c264361d BH |
521 | (mac_stats->tx_bytes - mac_stats->tx_bad_bytes - |
522 | mac_stats->tx_control * 64); | |
8ceee660 | 523 | mac_stats->rx_bad_bytes = |
c264361d BH |
524 | (mac_stats->rx_bytes - mac_stats->rx_good_bytes - |
525 | mac_stats->rx_control * 64); | |
8ceee660 BH |
526 | } |
527 | ||
8ceee660 BH |
528 | int falcon_check_xmac(struct efx_nic *efx) |
529 | { | |
dc8cfa55 | 530 | bool xaui_link_ok; |
8ceee660 BH |
531 | int rc; |
532 | ||
3273c2e8 | 533 | if ((efx->loopback_mode == LOOPBACK_NETWORK) || |
f8b87c17 | 534 | efx_phy_mode_disabled(efx->phy_mode)) |
3273c2e8 BH |
535 | return 0; |
536 | ||
dc8cfa55 | 537 | falcon_mask_status_intr(efx, false); |
8ceee660 BH |
538 | xaui_link_ok = falcon_xaui_link_ok(efx); |
539 | ||
540 | if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok) | |
91ad757c | 541 | falcon_reset_xaui(efx); |
8ceee660 BH |
542 | |
543 | /* Call the PHY check_hw routine */ | |
544 | rc = efx->phy_op->check_hw(efx); | |
545 | ||
546 | /* Unmask interrupt if everything was (and still is) ok */ | |
547 | if (xaui_link_ok && efx->link_up) | |
dc8cfa55 | 548 | falcon_mask_status_intr(efx, true); |
8ceee660 BH |
549 | |
550 | return rc; | |
551 | } | |
552 | ||
553 | /* Simulate a PHY event */ | |
554 | void falcon_xmac_sim_phy_event(struct efx_nic *efx) | |
555 | { | |
556 | efx_qword_t phy_event; | |
557 | ||
558 | EFX_POPULATE_QWORD_2(phy_event, | |
559 | EV_CODE, GLOBAL_EV_DECODE, | |
560 | XG_PHY_INTR, 1); | |
561 | falcon_generate_event(&efx->channel[0], &phy_event); | |
562 | } | |
563 | ||
564 | int falcon_xmac_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
565 | { | |
566 | mdio_clause45_get_settings(efx, ecmd); | |
567 | ecmd->transceiver = XCVR_INTERNAL; | |
568 | ecmd->phy_address = efx->mii.phy_id; | |
569 | ecmd->autoneg = AUTONEG_DISABLE; | |
570 | ecmd->duplex = DUPLEX_FULL; | |
571 | return 0; | |
572 | } | |
573 | ||
574 | int falcon_xmac_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
575 | { | |
576 | if (ecmd->transceiver != XCVR_INTERNAL) | |
577 | return -EINVAL; | |
578 | if (ecmd->autoneg != AUTONEG_DISABLE) | |
579 | return -EINVAL; | |
580 | if (ecmd->duplex != DUPLEX_FULL) | |
581 | return -EINVAL; | |
582 | ||
583 | return mdio_clause45_set_settings(efx, ecmd); | |
584 | } | |
585 | ||
586 | ||
587 | int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control) | |
588 | { | |
dc8cfa55 | 589 | bool reset; |
8ceee660 BH |
590 | |
591 | if (flow_control & EFX_FC_AUTO) { | |
592 | EFX_LOG(efx, "10G does not support flow control " | |
593 | "autonegotiation\n"); | |
594 | return -EINVAL; | |
595 | } | |
596 | ||
597 | if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX)) | |
598 | return -EINVAL; | |
599 | ||
600 | /* TX flow control may automatically turn itself off if the | |
601 | * link partner (intermittently) stops responding to pause | |
602 | * frames. There isn't any indication that this has happened, | |
603 | * so the best we do is leave it up to the user to spot this | |
604 | * and fix it be cycling transmit flow control on this end. */ | |
605 | reset = ((flow_control & EFX_FC_TX) && | |
606 | !(efx->flow_control & EFX_FC_TX)); | |
607 | if (EFX_WORKAROUND_11482(efx) && reset) { | |
55668611 | 608 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
8ceee660 BH |
609 | /* Recover by resetting the EM block */ |
610 | if (efx->link_up) | |
611 | falcon_drain_tx_fifo(efx); | |
612 | } else { | |
613 | /* Schedule a reset to recover */ | |
614 | efx_schedule_reset(efx, RESET_TYPE_INVISIBLE); | |
615 | } | |
616 | } | |
617 | ||
618 | efx->flow_control = flow_control; | |
619 | ||
620 | return 0; | |
621 | } |