[deliverable/linux.git] / drivers / net / sfc / tenxpress.c

/****************************************************************************
 * Driver for Solarflare 802.3an compliant PHY
 * Copyright 2007 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#include <linux/delay.h>
#include <linux/seq_file.h>
#include "efx.h"
#include "gmii.h"
#include "mdio_10g.h"
#include "falcon.h"
#include "phy.h"
#include "falcon_hwdefs.h"
#include "boards.h"
#include "mac.h"

/* We expect these MMDs to be in the package */
/* AN not here as mdio_check_mmds() requires STAT2 support */
#define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD | \
				 MDIO_MMDREG_DEVS0_PCS    | \
				 MDIO_MMDREG_DEVS0_PHYXS)

#define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) |	\
			     (1 << LOOPBACK_PCS) |	\
			     (1 << LOOPBACK_PMAPMD) |	\
			     (1 << LOOPBACK_NETWORK))

/* We complain if we fail to see the link partner as 10G capable this many
 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
 */
#define MAX_BAD_LP_TRIES	(5)

/* Extended control register */
#define	PMA_PMD_XCONTROL_REG 0xc000
#define	PMA_PMD_LNPGA_POWERDOWN_LBN 8
#define	PMA_PMD_LNPGA_POWERDOWN_WIDTH 1

/* extended status register */
#define PMA_PMD_XSTATUS_REG 0xc001
#define PMA_PMD_XSTAT_FLP_LBN   (12)

/* LED control register */
#define PMA_PMD_LED_CTRL_REG	(0xc007)
#define PMA_PMA_LED_ACTIVITY_LBN	(3)

/* LED function override register */
#define PMA_PMD_LED_OVERR_REG	(0xc009)
/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
#define PMA_PMD_LED_LINK_LBN	(0)
#define PMA_PMD_LED_SPEED_LBN	(2)
#define PMA_PMD_LED_TX_LBN	(4)
#define PMA_PMD_LED_RX_LBN	(6)
/* Override settings */
#define	PMA_PMD_LED_AUTO	(0)	/* H/W control */
#define	PMA_PMD_LED_ON		(1)
#define	PMA_PMD_LED_OFF		(2)
#define PMA_PMD_LED_FLASH	(3)
/* All LEDs under hardware control */
#define PMA_PMD_LED_FULL_AUTO	(0)
/* Green and Amber under hardware control, Red off */
#define PMA_PMD_LED_DEFAULT	(PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)


/* Special Software reset register */
#define PMA_PMD_EXT_CTRL_REG 49152
#define PMA_PMD_EXT_SSR_LBN 15

/* Misc register defines */
#define PCS_CLOCK_CTRL_REG 0xd801
#define PLL312_RST_N_LBN 2

#define PCS_SOFT_RST2_REG 0xd806
#define SERDES_RST_N_LBN 13
#define XGXS_RST_N_LBN 12

#define	PCS_TEST_SELECT_REG 0xd807	/* PRM 10.5.8 */
#define	CLK312_EN_LBN 3

/* PHYXS registers */
#define PHYXS_TEST1         (49162)
#define LOOPBACK_NEAR_LBN   (8)
#define LOOPBACK_NEAR_WIDTH (1)

/* Boot status register */
#define PCS_BOOT_STATUS_REG	(0xd000)
#define PCS_BOOT_FATAL_ERR_LBN	(0)
#define PCS_BOOT_PROGRESS_LBN	(1)
#define PCS_BOOT_PROGRESS_WIDTH	(2)
#define PCS_BOOT_COMPLETE_LBN	(3)
#define PCS_BOOT_MAX_DELAY	(100)
#define PCS_BOOT_POLL_DELAY	(10)

/* Time to wait between powering down the LNPGA and turning off the power
 * rails */
#define LNPGA_PDOWN_WAIT	(HZ / 5)

static int crc_error_reset_threshold = 100;
module_param(crc_error_reset_threshold, int, 0644);
MODULE_PARM_DESC(crc_error_reset_threshold,
		 "Max number of CRC errors before XAUI reset");

struct tenxpress_phy_data {
	enum efx_loopback_mode loopback_mode;
	atomic_t bad_crc_count;
	enum efx_phy_mode phy_mode;
	int bad_lp_tries;
};

void tenxpress_crc_err(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data = efx->phy_data;
	if (phy_data != NULL)
		atomic_inc(&phy_data->bad_crc_count);
}

/* Check that the C166 has booted successfully */
static int tenxpress_phy_check(struct efx_nic *efx)
{
	int phy_id = efx->mii.phy_id;
	int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
	int boot_stat;

	/* Wait for the boot to complete (or not) */
	while (count) {
		boot_stat = mdio_clause45_read(efx, phy_id,
					       MDIO_MMD_PCS,
					       PCS_BOOT_STATUS_REG);
		if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
			break;
		count--;
		udelay(PCS_BOOT_POLL_DELAY);
	}

	if (!count) {
		EFX_ERR(efx, "%s: PHY boot timed out. Last status "
			"%x\n", __func__,
			(boot_stat >> PCS_BOOT_PROGRESS_LBN) &
			((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
		return -ETIMEDOUT;
	}

	return 0;
}

static int tenxpress_init(struct efx_nic *efx)
{
	int rc, reg;

	/* Turn on the clock  */
	reg = (1 << CLK312_EN_LBN);
	mdio_clause45_write(efx, efx->mii.phy_id,
			    MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);

	rc = tenxpress_phy_check(efx);
	if (rc < 0)
		return rc;

	/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
	reg = mdio_clause45_read(efx, efx->mii.phy_id,
				 MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG);
	reg |= (1 << PMA_PMA_LED_ACTIVITY_LBN);
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_LED_CTRL_REG, reg);

	reg = PMA_PMD_LED_DEFAULT;
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_LED_OVERR_REG, reg);

	return rc;
}

static int tenxpress_phy_init(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data;
	int rc = 0;

	phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
	if (!phy_data)
		return -ENOMEM;
	efx->phy_data = phy_data;
	phy_data->phy_mode = efx->phy_mode;

	rc = mdio_clause45_wait_reset_mmds(efx,
					   TENXPRESS_REQUIRED_DEVS);
	if (rc < 0)
		goto fail;

	rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
	if (rc < 0)
		goto fail;

	rc = tenxpress_init(efx);
	if (rc < 0)
		goto fail;

	schedule_timeout_uninterruptible(HZ / 5); /* 200ms */

	/* Let XGXS and SerDes out of reset and resets 10XPress */
	falcon_reset_xaui(efx);

	return 0;

 fail:
	kfree(efx->phy_data);
	efx->phy_data = NULL;
	return rc;
}

static int tenxpress_special_reset(struct efx_nic *efx)
{
	int rc, reg;

	EFX_TRACE(efx, "%s\n", __func__);

	/* Initiate reset */
	reg = mdio_clause45_read(efx, efx->mii.phy_id,
				 MDIO_MMD_PMAPMD, PMA_PMD_EXT_CTRL_REG);
	reg |= (1 << PMA_PMD_EXT_SSR_LBN);
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_EXT_CTRL_REG, reg);

	msleep(200);

	/* Wait for the blocks to come out of reset */
	rc = mdio_clause45_wait_reset_mmds(efx,
					   TENXPRESS_REQUIRED_DEVS);
	if (rc < 0)
		return rc;

	/* Try and reconfigure the device */
	rc = tenxpress_init(efx);
	if (rc < 0)
		return rc;

	return 0;
}

static void tenxpress_set_bad_lp(struct efx_nic *efx, bool bad_lp)
{
	struct tenxpress_phy_data *pd = efx->phy_data;
	int reg;

	/* Nothing to do if all is well and was previously so. */
	if (!(bad_lp || pd->bad_lp_tries))
		return;

	reg = mdio_clause45_read(efx, efx->mii.phy_id,
				 MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG);

	if (bad_lp)
		pd->bad_lp_tries++;
	else
		pd->bad_lp_tries = 0;

	if (pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
		pd->bad_lp_tries = 0;	/* Restart count */
		reg &= ~(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
		reg |= (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
		EFX_ERR(efx, "This NIC appears to be plugged into"
			" a port that is not 10GBASE-T capable.\n"
			" This PHY is 10GBASE-T ONLY, so no link can"
			" be established.\n");
	} else {
		reg |= (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN);
	}
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_LED_OVERR_REG, reg);
}

/* Check link status and return a boolean OK value. If the link is NOT
 * OK we have a quick rummage round to see if we appear to be plugged
 * into a non-10GBT port and if so warn the user that they won't get
 * link any time soon as we are 10GBT only, unless caller specified
 * not to do this check (it isn't useful in loopback) */
static bool tenxpress_link_ok(struct efx_nic *efx, bool check_lp)
{
	bool ok = mdio_clause45_links_ok(efx, TENXPRESS_REQUIRED_DEVS);

	if (ok) {
		tenxpress_set_bad_lp(efx, false);
	} else if (check_lp) {
		/* Are we plugged into the wrong sort of link? */
		bool bad_lp = false;
		int phy_id = efx->mii.phy_id;
		int an_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
						 MDIO_AN_STATUS);
		int xphy_stat = mdio_clause45_read(efx, phy_id,
						   MDIO_MMD_PMAPMD,
						   PMA_PMD_XSTATUS_REG);
		/* Are we plugged into anything that sends FLPs? If
		 * not we can't distinguish between not being plugged
		 * in and being plugged into a non-AN antique. The FLP
		 * bit has the advantage of not clearing when autoneg
		 * restarts. */
		if (!(xphy_stat & (1 << PMA_PMD_XSTAT_FLP_LBN))) {
			tenxpress_set_bad_lp(efx, false);
			return ok;
		}

		/* If it can do 10GBT it must be XNP capable */
		bad_lp = !(an_stat & (1 << MDIO_AN_STATUS_XNP_LBN));
		if (!bad_lp && (an_stat & (1 << MDIO_AN_STATUS_PAGE_LBN))) {
			bad_lp = !(mdio_clause45_read(efx, phy_id,
					MDIO_MMD_AN, MDIO_AN_10GBT_STATUS) &
					(1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN));
		}
		tenxpress_set_bad_lp(efx, bad_lp);
	}
	return ok;
}

static void tenxpress_phyxs_loopback(struct efx_nic *efx)
{
	int phy_id = efx->mii.phy_id;
	int ctrl1, ctrl2;

	ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
					   PHYXS_TEST1);
	if (efx->loopback_mode == LOOPBACK_PHYXS)
		ctrl2 |= (1 << LOOPBACK_NEAR_LBN);
	else
		ctrl2 &= ~(1 << LOOPBACK_NEAR_LBN);
	if (ctrl1 != ctrl2)
		mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS,
				    PHYXS_TEST1, ctrl2);
}

static void tenxpress_phy_reconfigure(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data = efx->phy_data;
	bool loop_change = LOOPBACK_OUT_OF(phy_data, efx,
					   TENXPRESS_LOOPBACKS);

	if (efx->phy_mode & PHY_MODE_SPECIAL) {
		phy_data->phy_mode = efx->phy_mode;
		return;
	}

	/* When coming out of transmit disable, coming out of low power
	 * mode, or moving out of any PHY internal loopback mode,
	 * perform a special software reset */
	if ((efx->phy_mode == PHY_MODE_NORMAL &&
	     phy_data->phy_mode != PHY_MODE_NORMAL) ||
	    loop_change) {
		tenxpress_special_reset(efx);
		falcon_reset_xaui(efx);
	}

	mdio_clause45_transmit_disable(efx);
	mdio_clause45_phy_reconfigure(efx);
	tenxpress_phyxs_loopback(efx);

	phy_data->loopback_mode = efx->loopback_mode;
	phy_data->phy_mode = efx->phy_mode;
	efx->link_up = tenxpress_link_ok(efx, false);
	efx->link_options = GM_LPA_10000FULL;
}

static void tenxpress_phy_clear_interrupt(struct efx_nic *efx)
{
	/* Nothing done here - LASI interrupts aren't reliable so poll  */
}


/* Poll PHY for interrupt */
static int tenxpress_phy_check_hw(struct efx_nic *efx)
{
	struct tenxpress_phy_data *phy_data = efx->phy_data;
	bool link_ok;

	link_ok = (phy_data->phy_mode == PHY_MODE_NORMAL &&
		   tenxpress_link_ok(efx, true));

	if (link_ok != efx->link_up)
		falcon_xmac_sim_phy_event(efx);

	if (phy_data->phy_mode != PHY_MODE_NORMAL)
		return 0;

	if (atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
		EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
		falcon_reset_xaui(efx);
		atomic_set(&phy_data->bad_crc_count, 0);
	}

	return 0;
}

static void tenxpress_phy_fini(struct efx_nic *efx)
{
	int reg;

	/* Power down the LNPGA */
	reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_XCONTROL_REG, reg);

	/* Waiting here ensures that the board fini, which can turn off the
	 * power to the PHY, won't get run until the LNPGA powerdown has been
	 * given long enough to complete. */
	schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */

	kfree(efx->phy_data);
	efx->phy_data = NULL;
}


/* Set the RX and TX LEDs and Link LED flashing. The other LEDs
 * (which probably aren't wired anyway) are left in AUTO mode */
void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
{
	int reg;

	if (blink)
		reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
			(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
			(PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
	else
		reg = PMA_PMD_LED_DEFAULT;

	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
			    PMA_PMD_LED_OVERR_REG, reg);
}

static int tenxpress_phy_test(struct efx_nic *efx)
{
	/* BIST is automatically run after a special software reset */
	return tenxpress_special_reset(efx);
}

struct efx_phy_operations falcon_tenxpress_phy_ops = {
	.init             = tenxpress_phy_init,
	.reconfigure      = tenxpress_phy_reconfigure,
	.check_hw         = tenxpress_phy_check_hw,
	.fini             = tenxpress_phy_fini,
	.clear_interrupt  = tenxpress_phy_clear_interrupt,
	.test             = tenxpress_phy_test,
	.mmds             = TENXPRESS_REQUIRED_DEVS,
	.loopbacks        = TENXPRESS_LOOPBACKS,
};
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
	2	* Driver for Solarflare 802.3an compliant PHY
	3	* Copyright 2007 Solarflare Communications Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published
	7	* by the Free Software Foundation, incorporated herein by reference.
	8	*/
	9
	10	#include <linux/delay.h>
	11	#include <linux/seq_file.h>
	12	#include "efx.h"
	13	#include "gmii.h"
	14	#include "mdio_10g.h"
	15	#include "falcon.h"
	16	#include "phy.h"
	17	#include "falcon_hwdefs.h"
	18	#include "boards.h"
	19	#include "mac.h"
	20
	21	/* We expect these MMDs to be in the package */
	22	/* AN not here as mdio_check_mmds() requires STAT2 support */
	23	#define TENXPRESS_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_PMAPMD \| \
	24	MDIO_MMDREG_DEVS0_PCS \| \
	25	MDIO_MMDREG_DEVS0_PHYXS)
	26
3273c2e8 BH	27	#define TENXPRESS_LOOPBACKS ((1 << LOOPBACK_PHYXS) \| \
	28	(1 << LOOPBACK_PCS) \| \
	29	(1 << LOOPBACK_PMAPMD) \| \
	30	(1 << LOOPBACK_NETWORK))
	31
8ceee660 BH	32	/* We complain if we fail to see the link partner as 10G capable this many
	33	* times in a row (must be > 1 as sampling the autoneg. registers is racy)
	34	*/
	35	#define MAX_BAD_LP_TRIES (5)
	36
	37	/* Extended control register */
	38	#define PMA_PMD_XCONTROL_REG 0xc000
	39	#define PMA_PMD_LNPGA_POWERDOWN_LBN 8
	40	#define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
	41
	42	/* extended status register */
	43	#define PMA_PMD_XSTATUS_REG 0xc001
	44	#define PMA_PMD_XSTAT_FLP_LBN (12)
	45
	46	/* LED control register */
	47	#define PMA_PMD_LED_CTRL_REG (0xc007)
	48	#define PMA_PMA_LED_ACTIVITY_LBN (3)
	49
	50	/* LED function override register */
	51	#define PMA_PMD_LED_OVERR_REG (0xc009)
	52	/* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
	53	#define PMA_PMD_LED_LINK_LBN (0)
	54	#define PMA_PMD_LED_SPEED_LBN (2)
	55	#define PMA_PMD_LED_TX_LBN (4)
	56	#define PMA_PMD_LED_RX_LBN (6)
	57	/* Override settings */
	58	#define PMA_PMD_LED_AUTO (0) /* H/W control */
	59	#define PMA_PMD_LED_ON (1)
	60	#define PMA_PMD_LED_OFF (2)
	61	#define PMA_PMD_LED_FLASH (3)
	62	/* All LEDs under hardware control */
	63	#define PMA_PMD_LED_FULL_AUTO (0)
	64	/* Green and Amber under hardware control, Red off */
	65	#define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
	66
	67
3273c2e8 BH	68	/* Special Software reset register */
	69	#define PMA_PMD_EXT_CTRL_REG 49152
	70	#define PMA_PMD_EXT_SSR_LBN 15
	71
8ceee660 BH	72	/* Misc register defines */
	73	#define PCS_CLOCK_CTRL_REG 0xd801
	74	#define PLL312_RST_N_LBN 2
	75
	76	#define PCS_SOFT_RST2_REG 0xd806
	77	#define SERDES_RST_N_LBN 13
	78	#define XGXS_RST_N_LBN 12
	79
	80	#define PCS_TEST_SELECT_REG 0xd807 /* PRM 10.5.8 */
	81	#define CLK312_EN_LBN 3
	82
3273c2e8 BH	83	/* PHYXS registers */
	84	#define PHYXS_TEST1 (49162)
	85	#define LOOPBACK_NEAR_LBN (8)
	86	#define LOOPBACK_NEAR_WIDTH (1)
	87
8ceee660 BH	88	/* Boot status register */
	89	#define PCS_BOOT_STATUS_REG (0xd000)
	90	#define PCS_BOOT_FATAL_ERR_LBN (0)
	91	#define PCS_BOOT_PROGRESS_LBN (1)
	92	#define PCS_BOOT_PROGRESS_WIDTH (2)
	93	#define PCS_BOOT_COMPLETE_LBN (3)
	94	#define PCS_BOOT_MAX_DELAY (100)
	95	#define PCS_BOOT_POLL_DELAY (10)
	96
	97	/* Time to wait between powering down the LNPGA and turning off the power
	98	* rails */
	99	#define LNPGA_PDOWN_WAIT (HZ / 5)
	100
	101	static int crc_error_reset_threshold = 100;
	102	module_param(crc_error_reset_threshold, int, 0644);
	103	MODULE_PARM_DESC(crc_error_reset_threshold,
	104	"Max number of CRC errors before XAUI reset");
	105
	106	struct tenxpress_phy_data {
3273c2e8	107	enum efx_loopback_mode loopback_mode;
8ceee660	108	atomic_t bad_crc_count;
f8b87c17	109	enum efx_phy_mode phy_mode;
8ceee660 BH	110	int bad_lp_tries;
	111	};
	112
8ceee660 BH	113	void tenxpress_crc_err(struct efx_nic *efx)
	114	{
	115	struct tenxpress_phy_data *phy_data = efx->phy_data;
	116	if (phy_data != NULL)
	117	atomic_inc(&phy_data->bad_crc_count);
	118	}
	119
	120	/* Check that the C166 has booted successfully */
	121	static int tenxpress_phy_check(struct efx_nic *efx)
	122	{
	123	int phy_id = efx->mii.phy_id;
	124	int count = PCS_BOOT_MAX_DELAY / PCS_BOOT_POLL_DELAY;
	125	int boot_stat;
	126
	127	/* Wait for the boot to complete (or not) */
	128	while (count) {
	129	boot_stat = mdio_clause45_read(efx, phy_id,
	130	MDIO_MMD_PCS,
	131	PCS_BOOT_STATUS_REG);
	132	if (boot_stat & (1 << PCS_BOOT_COMPLETE_LBN))
	133	break;
	134	count--;
	135	udelay(PCS_BOOT_POLL_DELAY);
	136	}
	137
	138	if (!count) {
	139	EFX_ERR(efx, "%s: PHY boot timed out. Last status "
	140	"%x\n", __func__,
	141	(boot_stat >> PCS_BOOT_PROGRESS_LBN) &
	142	((1 << PCS_BOOT_PROGRESS_WIDTH) - 1));
	143	return -ETIMEDOUT;
	144	}
	145
	146	return 0;
	147	}
	148
8ceee660 BH	149	static int tenxpress_init(struct efx_nic *efx)
	150	{
	151	int rc, reg;
	152
	153	/* Turn on the clock */
	154	reg = (1 << CLK312_EN_LBN);
	155	mdio_clause45_write(efx, efx->mii.phy_id,
	156	MDIO_MMD_PCS, PCS_TEST_SELECT_REG, reg);
	157
	158	rc = tenxpress_phy_check(efx);
	159	if (rc < 0)
	160	return rc;
	161
	162	/* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
	163	reg = mdio_clause45_read(efx, efx->mii.phy_id,
	164	MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG);
	165	reg \|= (1 << PMA_PMA_LED_ACTIVITY_LBN);
	166	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	167	PMA_PMD_LED_CTRL_REG, reg);
	168
	169	reg = PMA_PMD_LED_DEFAULT;
	170	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	171	PMA_PMD_LED_OVERR_REG, reg);
	172
	173	return rc;
	174	}
	175
	176	static int tenxpress_phy_init(struct efx_nic *efx)
	177	{
	178	struct tenxpress_phy_data *phy_data;
	179	int rc = 0;
	180
	181	phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
9b7bfc4c BH	182	if (!phy_data)
9b7bfc4c BH	183	return -ENOMEM;
8ceee660	184	efx->phy_data = phy_data;
f8b87c17	185	phy_data->phy_mode = efx->phy_mode;
8ceee660	186
f8b87c17 BH	187	rc = mdio_clause45_wait_reset_mmds(efx,
	188	TENXPRESS_REQUIRED_DEVS);
	189	if (rc < 0)
	190	goto fail;
8ceee660 BH	191
	192	rc = mdio_clause45_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
	193	if (rc < 0)
	194	goto fail;
	195
	196	rc = tenxpress_init(efx);
	197	if (rc < 0)
	198	goto fail;
	199
	200	schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
	201
	202	/* Let XGXS and SerDes out of reset and resets 10XPress */
	203	falcon_reset_xaui(efx);
	204
	205	return 0;
	206
	207	fail:
	208	kfree(efx->phy_data);
	209	efx->phy_data = NULL;
	210	return rc;
	211	}
	212
3273c2e8 BH	213	static int tenxpress_special_reset(struct efx_nic *efx)
	214	{
	215	int rc, reg;
	216
	217	EFX_TRACE(efx, "%s\n", __func__);
	218
	219	/* Initiate reset */
	220	reg = mdio_clause45_read(efx, efx->mii.phy_id,
	221	MDIO_MMD_PMAPMD, PMA_PMD_EXT_CTRL_REG);
	222	reg \|= (1 << PMA_PMD_EXT_SSR_LBN);
	223	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	224	PMA_PMD_EXT_CTRL_REG, reg);
	225
	226	msleep(200);
	227
	228	/* Wait for the blocks to come out of reset */
	229	rc = mdio_clause45_wait_reset_mmds(efx,
	230	TENXPRESS_REQUIRED_DEVS);
	231	if (rc < 0)
	232	return rc;
	233
	234	/* Try and reconfigure the device */
	235	rc = tenxpress_init(efx);
	236	if (rc < 0)
	237	return rc;
	238
	239	return 0;
	240	}
	241
dc8cfa55	242	static void tenxpress_set_bad_lp(struct efx_nic *efx, bool bad_lp)
8ceee660 BH	243	{
	244	struct tenxpress_phy_data *pd = efx->phy_data;
	245	int reg;
	246
	247	/* Nothing to do if all is well and was previously so. */
	248	if (!(bad_lp \|\| pd->bad_lp_tries))
	249	return;
	250
	251	reg = mdio_clause45_read(efx, efx->mii.phy_id,
	252	MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG);
	253
	254	if (bad_lp)
	255	pd->bad_lp_tries++;
	256	else
	257	pd->bad_lp_tries = 0;
	258
	259	if (pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
	260	pd->bad_lp_tries = 0; /* Restart count */
	261	reg &= ~(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
	262	reg \|= (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN);
	263	EFX_ERR(efx, "This NIC appears to be plugged into"
	264	" a port that is not 10GBASE-T capable.\n"
	265	" This PHY is 10GBASE-T ONLY, so no link can"
	266	" be established.\n");
	267	} else {
	268	reg \|= (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN);
	269	}
	270	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	271	PMA_PMD_LED_OVERR_REG, reg);
	272	}
	273
	274	/* Check link status and return a boolean OK value. If the link is NOT
	275	* OK we have a quick rummage round to see if we appear to be plugged
	276	* into a non-10GBT port and if so warn the user that they won't get
	277	* link any time soon as we are 10GBT only, unless caller specified
	278	* not to do this check (it isn't useful in loopback) */
dc8cfa55	279	static bool tenxpress_link_ok(struct efx_nic *efx, bool check_lp)
8ceee660	280	{
dc8cfa55	281	bool ok = mdio_clause45_links_ok(efx, TENXPRESS_REQUIRED_DEVS);
8ceee660 BH	282
8ceee660 BH	283	if (ok) {
dc8cfa55	284	tenxpress_set_bad_lp(efx, false);
8ceee660 BH	285	} else if (check_lp) {
8ceee660 BH	286	/* Are we plugged into the wrong sort of link? */
dc8cfa55	287	bool bad_lp = false;
8ceee660 BH	288	int phy_id = efx->mii.phy_id;
	289	int an_stat = mdio_clause45_read(efx, phy_id, MDIO_MMD_AN,
	290	MDIO_AN_STATUS);
	291	int xphy_stat = mdio_clause45_read(efx, phy_id,
	292	MDIO_MMD_PMAPMD,
	293	PMA_PMD_XSTATUS_REG);
	294	/* Are we plugged into anything that sends FLPs? If
	295	* not we can't distinguish between not being plugged
	296	* in and being plugged into a non-AN antique. The FLP
	297	* bit has the advantage of not clearing when autoneg
	298	* restarts. */
	299	if (!(xphy_stat & (1 << PMA_PMD_XSTAT_FLP_LBN))) {
dc8cfa55	300	tenxpress_set_bad_lp(efx, false);
8ceee660 BH	301	return ok;
	302	}
	303
	304	/* If it can do 10GBT it must be XNP capable */
	305	bad_lp = !(an_stat & (1 << MDIO_AN_STATUS_XNP_LBN));
	306	if (!bad_lp && (an_stat & (1 << MDIO_AN_STATUS_PAGE_LBN))) {
	307	bad_lp = !(mdio_clause45_read(efx, phy_id,
	308	MDIO_MMD_AN, MDIO_AN_10GBT_STATUS) &
	309	(1 << MDIO_AN_10GBT_STATUS_LP_10G_LBN));
	310	}
	311	tenxpress_set_bad_lp(efx, bad_lp);
	312	}
	313	return ok;
	314	}
	315
3273c2e8 BH	316	static void tenxpress_phyxs_loopback(struct efx_nic *efx)
	317	{
	318	int phy_id = efx->mii.phy_id;
	319	int ctrl1, ctrl2;
	320
	321	ctrl1 = ctrl2 = mdio_clause45_read(efx, phy_id, MDIO_MMD_PHYXS,
	322	PHYXS_TEST1);
	323	if (efx->loopback_mode == LOOPBACK_PHYXS)
	324	ctrl2 \|= (1 << LOOPBACK_NEAR_LBN);
	325	else
	326	ctrl2 &= ~(1 << LOOPBACK_NEAR_LBN);
	327	if (ctrl1 != ctrl2)
	328	mdio_clause45_write(efx, phy_id, MDIO_MMD_PHYXS,
	329	PHYXS_TEST1, ctrl2);
	330	}
	331
8ceee660 BH	332	static void tenxpress_phy_reconfigure(struct efx_nic *efx)
8ceee660 BH	333	{
3273c2e8	334	struct tenxpress_phy_data *phy_data = efx->phy_data;
dc8cfa55 BH	335	bool loop_change = LOOPBACK_OUT_OF(phy_data, efx,
dc8cfa55 BH	336	TENXPRESS_LOOPBACKS);
3273c2e8	337
f8b87c17 BH	338	if (efx->phy_mode & PHY_MODE_SPECIAL) {
f8b87c17 BH	339	phy_data->phy_mode = efx->phy_mode;
8ceee660	340	return;
f8b87c17	341	}
8ceee660	342
3273c2e8 BH	343	/* When coming out of transmit disable, coming out of low power
	344	* mode, or moving out of any PHY internal loopback mode,
	345	* perform a special software reset */
f8b87c17 BH	346	if ((efx->phy_mode == PHY_MODE_NORMAL &&
f8b87c17 BH	347	phy_data->phy_mode != PHY_MODE_NORMAL) \|\|
3273c2e8	348	loop_change) {
91ad757c	349	tenxpress_special_reset(efx);
3273c2e8 BH	350	falcon_reset_xaui(efx);
	351	}
	352
	353	mdio_clause45_transmit_disable(efx);
	354	mdio_clause45_phy_reconfigure(efx);
	355	tenxpress_phyxs_loopback(efx);
	356
3273c2e8	357	phy_data->loopback_mode = efx->loopback_mode;
f8b87c17	358	phy_data->phy_mode = efx->phy_mode;
dc8cfa55	359	efx->link_up = tenxpress_link_ok(efx, false);
8ceee660 BH	360	efx->link_options = GM_LPA_10000FULL;
	361	}
	362
	363	static void tenxpress_phy_clear_interrupt(struct efx_nic *efx)
	364	{
	365	/* Nothing done here - LASI interrupts aren't reliable so poll */
	366	}
	367
	368
	369	/* Poll PHY for interrupt */
	370	static int tenxpress_phy_check_hw(struct efx_nic *efx)
	371	{
	372	struct tenxpress_phy_data *phy_data = efx->phy_data;
dc8cfa55	373	bool link_ok;
8ceee660	374
f8b87c17 BH	375	link_ok = (phy_data->phy_mode == PHY_MODE_NORMAL &&
f8b87c17 BH	376	tenxpress_link_ok(efx, true));
8ceee660 BH	377
	378	if (link_ok != efx->link_up)
	379	falcon_xmac_sim_phy_event(efx);
	380
f8b87c17	381	if (phy_data->phy_mode != PHY_MODE_NORMAL)
8ceee660 BH	382	return 0;
	383
	384	if (atomic_read(&phy_data->bad_crc_count) > crc_error_reset_threshold) {
	385	EFX_ERR(efx, "Resetting XAUI due to too many CRC errors\n");
	386	falcon_reset_xaui(efx);
	387	atomic_set(&phy_data->bad_crc_count, 0);
	388	}
	389
	390	return 0;
	391	}
	392
	393	static void tenxpress_phy_fini(struct efx_nic *efx)
	394	{
	395	int reg;
	396
	397	/* Power down the LNPGA */
	398	reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
	399	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	400	PMA_PMD_XCONTROL_REG, reg);
	401
	402	/* Waiting here ensures that the board fini, which can turn off the
	403	* power to the PHY, won't get run until the LNPGA powerdown has been
	404	* given long enough to complete. */
	405	schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
	406
	407	kfree(efx->phy_data);
	408	efx->phy_data = NULL;
	409	}
	410
	411
	412	/* Set the RX and TX LEDs and Link LED flashing. The other LEDs
	413	* (which probably aren't wired anyway) are left in AUTO mode */
dc8cfa55	414	void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
8ceee660 BH	415	{
	416	int reg;
	417
	418	if (blink)
	419	reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) \|
	420	(PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) \|
	421	(PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
	422	else
	423	reg = PMA_PMD_LED_DEFAULT;
	424
	425	mdio_clause45_write(efx, efx->mii.phy_id, MDIO_MMD_PMAPMD,
	426	PMA_PMD_LED_OVERR_REG, reg);
	427	}
	428
8c8661e4 BH	429	static int tenxpress_phy_test(struct efx_nic *efx)
	430	{
	431	/* BIST is automatically run after a special software reset */
	432	return tenxpress_special_reset(efx);
	433	}
	434
8ceee660 BH	435	struct efx_phy_operations falcon_tenxpress_phy_ops = {
	436	.init = tenxpress_phy_init,
	437	.reconfigure = tenxpress_phy_reconfigure,
	438	.check_hw = tenxpress_phy_check_hw,
	439	.fini = tenxpress_phy_fini,
	440	.clear_interrupt = tenxpress_phy_clear_interrupt,
8c8661e4	441	.test = tenxpress_phy_test,
8ceee660	442	.mmds = TENXPRESS_REQUIRED_DEVS,
3273c2e8	443	.loopbacks = TENXPRESS_LOOPBACKS,
8ceee660	444	};