Commit | Line | Data |
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86a74ff2 NI |
1 | /* |
2 | * SuperH Ethernet device driver | |
3 | * | |
b0ca2a21 | 4 | * Copyright (C) 2006-2008 Nobuhiro Iwamatsu |
380af9e3 | 5 | * Copyright (C) 2008-2009 Renesas Solutions Corp. |
86a74ff2 NI |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms and conditions of the GNU General Public License, | |
9 | * version 2, as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program; if not, write to the Free Software Foundation, Inc., | |
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | * | |
19 | * The full GNU General Public License is included in this distribution in | |
20 | * the file called "COPYING". | |
21 | */ | |
22 | ||
86a74ff2 NI |
23 | #include <linux/init.h> |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/etherdevice.h> | |
26 | #include <linux/delay.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/mdio-bitbang.h> | |
29 | #include <linux/netdevice.h> | |
30 | #include <linux/phy.h> | |
31 | #include <linux/cache.h> | |
32 | #include <linux/io.h> | |
bcd5149d | 33 | #include <linux/pm_runtime.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
f568a926 | 35 | #include <asm/cacheflush.h> |
86a74ff2 NI |
36 | |
37 | #include "sh_eth.h" | |
38 | ||
380af9e3 | 39 | /* There is CPU dependent code */ |
65ac8851 YS |
40 | #if defined(CONFIG_CPU_SUBTYPE_SH7724) |
41 | #define SH_ETH_RESET_DEFAULT 1 | |
42 | static void sh_eth_set_duplex(struct net_device *ndev) | |
43 | { | |
44 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
45 | u32 ioaddr = ndev->base_addr; | |
46 | ||
47 | if (mdp->duplex) /* Full */ | |
48 | ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR); | |
49 | else /* Half */ | |
50 | ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR); | |
51 | } | |
52 | ||
53 | static void sh_eth_set_rate(struct net_device *ndev) | |
54 | { | |
55 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
56 | u32 ioaddr = ndev->base_addr; | |
57 | ||
58 | switch (mdp->speed) { | |
59 | case 10: /* 10BASE */ | |
60 | ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR); | |
61 | break; | |
62 | case 100:/* 100BASE */ | |
63 | ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR); | |
64 | break; | |
65 | default: | |
66 | break; | |
67 | } | |
68 | } | |
69 | ||
70 | /* SH7724 */ | |
71 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |
72 | .set_duplex = sh_eth_set_duplex, | |
73 | .set_rate = sh_eth_set_rate, | |
74 | ||
75 | .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, | |
76 | .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, | |
77 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f, | |
78 | ||
79 | .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, | |
80 | .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE | | |
81 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI, | |
82 | .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE, | |
83 | ||
84 | .apr = 1, | |
85 | .mpr = 1, | |
86 | .tpauser = 1, | |
87 | .hw_swap = 1, | |
503914cf MD |
88 | .rpadir = 1, |
89 | .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ | |
65ac8851 YS |
90 | }; |
91 | ||
92 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | |
380af9e3 YS |
93 | #define SH_ETH_HAS_TSU 1 |
94 | static void sh_eth_chip_reset(struct net_device *ndev) | |
95 | { | |
96 | /* reset device */ | |
97 | ctrl_outl(ARSTR_ARSTR, ARSTR); | |
98 | mdelay(1); | |
99 | } | |
100 | ||
101 | static void sh_eth_reset(struct net_device *ndev) | |
102 | { | |
103 | u32 ioaddr = ndev->base_addr; | |
104 | int cnt = 100; | |
105 | ||
106 | ctrl_outl(EDSR_ENALL, ioaddr + EDSR); | |
107 | ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR); | |
108 | while (cnt > 0) { | |
109 | if (!(ctrl_inl(ioaddr + EDMR) & 0x3)) | |
110 | break; | |
111 | mdelay(1); | |
112 | cnt--; | |
113 | } | |
890c8c18 | 114 | if (cnt == 0) |
380af9e3 YS |
115 | printk(KERN_ERR "Device reset fail\n"); |
116 | ||
117 | /* Table Init */ | |
118 | ctrl_outl(0x0, ioaddr + TDLAR); | |
119 | ctrl_outl(0x0, ioaddr + TDFAR); | |
120 | ctrl_outl(0x0, ioaddr + TDFXR); | |
121 | ctrl_outl(0x0, ioaddr + TDFFR); | |
122 | ctrl_outl(0x0, ioaddr + RDLAR); | |
123 | ctrl_outl(0x0, ioaddr + RDFAR); | |
124 | ctrl_outl(0x0, ioaddr + RDFXR); | |
125 | ctrl_outl(0x0, ioaddr + RDFFR); | |
126 | } | |
127 | ||
128 | static void sh_eth_set_duplex(struct net_device *ndev) | |
129 | { | |
130 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
131 | u32 ioaddr = ndev->base_addr; | |
132 | ||
133 | if (mdp->duplex) /* Full */ | |
134 | ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR); | |
135 | else /* Half */ | |
136 | ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR); | |
137 | } | |
138 | ||
139 | static void sh_eth_set_rate(struct net_device *ndev) | |
140 | { | |
141 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
142 | u32 ioaddr = ndev->base_addr; | |
143 | ||
144 | switch (mdp->speed) { | |
145 | case 10: /* 10BASE */ | |
146 | ctrl_outl(GECMR_10, ioaddr + GECMR); | |
147 | break; | |
148 | case 100:/* 100BASE */ | |
149 | ctrl_outl(GECMR_100, ioaddr + GECMR); | |
150 | break; | |
151 | case 1000: /* 1000BASE */ | |
152 | ctrl_outl(GECMR_1000, ioaddr + GECMR); | |
153 | break; | |
154 | default: | |
155 | break; | |
156 | } | |
157 | } | |
158 | ||
159 | /* sh7763 */ | |
160 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |
161 | .chip_reset = sh_eth_chip_reset, | |
162 | .set_duplex = sh_eth_set_duplex, | |
163 | .set_rate = sh_eth_set_rate, | |
164 | ||
165 | .ecsr_value = ECSR_ICD | ECSR_MPD, | |
166 | .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, | |
167 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, | |
168 | ||
169 | .tx_check = EESR_TC1 | EESR_FTC, | |
170 | .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ | |
171 | EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ | |
172 | EESR_ECI, | |
173 | .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \ | |
174 | EESR_TFE, | |
175 | ||
176 | .apr = 1, | |
177 | .mpr = 1, | |
178 | .tpauser = 1, | |
179 | .bculr = 1, | |
180 | .hw_swap = 1, | |
380af9e3 YS |
181 | .no_trimd = 1, |
182 | .no_ade = 1, | |
183 | }; | |
184 | ||
185 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | |
186 | #define SH_ETH_RESET_DEFAULT 1 | |
187 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |
188 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, | |
189 | ||
190 | .apr = 1, | |
191 | .mpr = 1, | |
192 | .tpauser = 1, | |
193 | .hw_swap = 1, | |
194 | }; | |
195 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | |
196 | #define SH_ETH_RESET_DEFAULT 1 | |
197 | #define SH_ETH_HAS_TSU 1 | |
198 | static struct sh_eth_cpu_data sh_eth_my_cpu_data = { | |
199 | .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, | |
200 | }; | |
201 | #endif | |
202 | ||
203 | static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) | |
204 | { | |
205 | if (!cd->ecsr_value) | |
206 | cd->ecsr_value = DEFAULT_ECSR_INIT; | |
207 | ||
208 | if (!cd->ecsipr_value) | |
209 | cd->ecsipr_value = DEFAULT_ECSIPR_INIT; | |
210 | ||
211 | if (!cd->fcftr_value) | |
212 | cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \ | |
213 | DEFAULT_FIFO_F_D_RFD; | |
214 | ||
215 | if (!cd->fdr_value) | |
216 | cd->fdr_value = DEFAULT_FDR_INIT; | |
217 | ||
218 | if (!cd->rmcr_value) | |
219 | cd->rmcr_value = DEFAULT_RMCR_VALUE; | |
220 | ||
221 | if (!cd->tx_check) | |
222 | cd->tx_check = DEFAULT_TX_CHECK; | |
223 | ||
224 | if (!cd->eesr_err_check) | |
225 | cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; | |
226 | ||
227 | if (!cd->tx_error_check) | |
228 | cd->tx_error_check = DEFAULT_TX_ERROR_CHECK; | |
229 | } | |
230 | ||
231 | #if defined(SH_ETH_RESET_DEFAULT) | |
232 | /* Chip Reset */ | |
233 | static void sh_eth_reset(struct net_device *ndev) | |
234 | { | |
235 | u32 ioaddr = ndev->base_addr; | |
236 | ||
237 | ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR); | |
238 | mdelay(3); | |
239 | ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR); | |
240 | } | |
241 | #endif | |
242 | ||
243 | #if defined(CONFIG_CPU_SH4) | |
244 | static void sh_eth_set_receive_align(struct sk_buff *skb) | |
245 | { | |
246 | int reserve; | |
247 | ||
248 | reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); | |
249 | if (reserve) | |
250 | skb_reserve(skb, reserve); | |
251 | } | |
252 | #else | |
253 | static void sh_eth_set_receive_align(struct sk_buff *skb) | |
254 | { | |
255 | skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); | |
256 | } | |
257 | #endif | |
258 | ||
259 | ||
71557a37 YS |
260 | /* CPU <-> EDMAC endian convert */ |
261 | static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) | |
262 | { | |
263 | switch (mdp->edmac_endian) { | |
264 | case EDMAC_LITTLE_ENDIAN: | |
265 | return cpu_to_le32(x); | |
266 | case EDMAC_BIG_ENDIAN: | |
267 | return cpu_to_be32(x); | |
268 | } | |
269 | return x; | |
270 | } | |
271 | ||
272 | static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) | |
273 | { | |
274 | switch (mdp->edmac_endian) { | |
275 | case EDMAC_LITTLE_ENDIAN: | |
276 | return le32_to_cpu(x); | |
277 | case EDMAC_BIG_ENDIAN: | |
278 | return be32_to_cpu(x); | |
279 | } | |
280 | return x; | |
281 | } | |
282 | ||
86a74ff2 NI |
283 | /* |
284 | * Program the hardware MAC address from dev->dev_addr. | |
285 | */ | |
286 | static void update_mac_address(struct net_device *ndev) | |
287 | { | |
288 | u32 ioaddr = ndev->base_addr; | |
289 | ||
290 | ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | | |
291 | (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), | |
292 | ioaddr + MAHR); | |
293 | ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), | |
294 | ioaddr + MALR); | |
295 | } | |
296 | ||
297 | /* | |
298 | * Get MAC address from SuperH MAC address register | |
299 | * | |
300 | * SuperH's Ethernet device doesn't have 'ROM' to MAC address. | |
301 | * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). | |
302 | * When you want use this device, you must set MAC address in bootloader. | |
303 | * | |
304 | */ | |
748031f9 | 305 | static void read_mac_address(struct net_device *ndev, unsigned char *mac) |
86a74ff2 NI |
306 | { |
307 | u32 ioaddr = ndev->base_addr; | |
308 | ||
748031f9 MD |
309 | if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { |
310 | memcpy(ndev->dev_addr, mac, 6); | |
311 | } else { | |
312 | ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24); | |
313 | ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF; | |
314 | ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF; | |
315 | ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF); | |
316 | ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF; | |
317 | ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF); | |
318 | } | |
86a74ff2 NI |
319 | } |
320 | ||
321 | struct bb_info { | |
322 | struct mdiobb_ctrl ctrl; | |
323 | u32 addr; | |
324 | u32 mmd_msk;/* MMD */ | |
325 | u32 mdo_msk; | |
326 | u32 mdi_msk; | |
327 | u32 mdc_msk; | |
328 | }; | |
329 | ||
330 | /* PHY bit set */ | |
331 | static void bb_set(u32 addr, u32 msk) | |
332 | { | |
333 | ctrl_outl(ctrl_inl(addr) | msk, addr); | |
334 | } | |
335 | ||
336 | /* PHY bit clear */ | |
337 | static void bb_clr(u32 addr, u32 msk) | |
338 | { | |
339 | ctrl_outl((ctrl_inl(addr) & ~msk), addr); | |
340 | } | |
341 | ||
342 | /* PHY bit read */ | |
343 | static int bb_read(u32 addr, u32 msk) | |
344 | { | |
345 | return (ctrl_inl(addr) & msk) != 0; | |
346 | } | |
347 | ||
348 | /* Data I/O pin control */ | |
349 | static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) | |
350 | { | |
351 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
352 | if (bit) | |
353 | bb_set(bitbang->addr, bitbang->mmd_msk); | |
354 | else | |
355 | bb_clr(bitbang->addr, bitbang->mmd_msk); | |
356 | } | |
357 | ||
358 | /* Set bit data*/ | |
359 | static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) | |
360 | { | |
361 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
362 | ||
363 | if (bit) | |
364 | bb_set(bitbang->addr, bitbang->mdo_msk); | |
365 | else | |
366 | bb_clr(bitbang->addr, bitbang->mdo_msk); | |
367 | } | |
368 | ||
369 | /* Get bit data*/ | |
370 | static int sh_get_mdio(struct mdiobb_ctrl *ctrl) | |
371 | { | |
372 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
373 | return bb_read(bitbang->addr, bitbang->mdi_msk); | |
374 | } | |
375 | ||
376 | /* MDC pin control */ | |
377 | static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) | |
378 | { | |
379 | struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); | |
380 | ||
381 | if (bit) | |
382 | bb_set(bitbang->addr, bitbang->mdc_msk); | |
383 | else | |
384 | bb_clr(bitbang->addr, bitbang->mdc_msk); | |
385 | } | |
386 | ||
387 | /* mdio bus control struct */ | |
388 | static struct mdiobb_ops bb_ops = { | |
389 | .owner = THIS_MODULE, | |
390 | .set_mdc = sh_mdc_ctrl, | |
391 | .set_mdio_dir = sh_mmd_ctrl, | |
392 | .set_mdio_data = sh_set_mdio, | |
393 | .get_mdio_data = sh_get_mdio, | |
394 | }; | |
395 | ||
86a74ff2 NI |
396 | /* free skb and descriptor buffer */ |
397 | static void sh_eth_ring_free(struct net_device *ndev) | |
398 | { | |
399 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
400 | int i; | |
401 | ||
402 | /* Free Rx skb ringbuffer */ | |
403 | if (mdp->rx_skbuff) { | |
404 | for (i = 0; i < RX_RING_SIZE; i++) { | |
405 | if (mdp->rx_skbuff[i]) | |
406 | dev_kfree_skb(mdp->rx_skbuff[i]); | |
407 | } | |
408 | } | |
409 | kfree(mdp->rx_skbuff); | |
410 | ||
411 | /* Free Tx skb ringbuffer */ | |
412 | if (mdp->tx_skbuff) { | |
413 | for (i = 0; i < TX_RING_SIZE; i++) { | |
414 | if (mdp->tx_skbuff[i]) | |
415 | dev_kfree_skb(mdp->tx_skbuff[i]); | |
416 | } | |
417 | } | |
418 | kfree(mdp->tx_skbuff); | |
419 | } | |
420 | ||
421 | /* format skb and descriptor buffer */ | |
422 | static void sh_eth_ring_format(struct net_device *ndev) | |
423 | { | |
380af9e3 | 424 | u32 ioaddr = ndev->base_addr; |
86a74ff2 NI |
425 | struct sh_eth_private *mdp = netdev_priv(ndev); |
426 | int i; | |
427 | struct sk_buff *skb; | |
428 | struct sh_eth_rxdesc *rxdesc = NULL; | |
429 | struct sh_eth_txdesc *txdesc = NULL; | |
430 | int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE; | |
431 | int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE; | |
432 | ||
433 | mdp->cur_rx = mdp->cur_tx = 0; | |
434 | mdp->dirty_rx = mdp->dirty_tx = 0; | |
435 | ||
436 | memset(mdp->rx_ring, 0, rx_ringsize); | |
437 | ||
438 | /* build Rx ring buffer */ | |
439 | for (i = 0; i < RX_RING_SIZE; i++) { | |
440 | /* skb */ | |
441 | mdp->rx_skbuff[i] = NULL; | |
442 | skb = dev_alloc_skb(mdp->rx_buf_sz); | |
443 | mdp->rx_skbuff[i] = skb; | |
444 | if (skb == NULL) | |
445 | break; | |
e88aae7b YS |
446 | dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz, |
447 | DMA_FROM_DEVICE); | |
b0ca2a21 | 448 | skb->dev = ndev; /* Mark as being used by this device. */ |
380af9e3 YS |
449 | sh_eth_set_receive_align(skb); |
450 | ||
86a74ff2 NI |
451 | /* RX descriptor */ |
452 | rxdesc = &mdp->rx_ring[i]; | |
0029d64a | 453 | rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); |
71557a37 | 454 | rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); |
86a74ff2 NI |
455 | |
456 | /* The size of the buffer is 16 byte boundary. */ | |
0029d64a | 457 | rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); |
b0ca2a21 NI |
458 | /* Rx descriptor address set */ |
459 | if (i == 0) { | |
0029d64a | 460 | ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR); |
b0ca2a21 | 461 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
0029d64a | 462 | ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR); |
b0ca2a21 NI |
463 | #endif |
464 | } | |
86a74ff2 NI |
465 | } |
466 | ||
467 | mdp->dirty_rx = (u32) (i - RX_RING_SIZE); | |
468 | ||
469 | /* Mark the last entry as wrapping the ring. */ | |
71557a37 | 470 | rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); |
86a74ff2 NI |
471 | |
472 | memset(mdp->tx_ring, 0, tx_ringsize); | |
473 | ||
474 | /* build Tx ring buffer */ | |
475 | for (i = 0; i < TX_RING_SIZE; i++) { | |
476 | mdp->tx_skbuff[i] = NULL; | |
477 | txdesc = &mdp->tx_ring[i]; | |
71557a37 | 478 | txdesc->status = cpu_to_edmac(mdp, TD_TFP); |
86a74ff2 | 479 | txdesc->buffer_length = 0; |
b0ca2a21 | 480 | if (i == 0) { |
71557a37 | 481 | /* Tx descriptor address set */ |
0029d64a | 482 | ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR); |
b0ca2a21 | 483 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
0029d64a | 484 | ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR); |
b0ca2a21 NI |
485 | #endif |
486 | } | |
86a74ff2 NI |
487 | } |
488 | ||
71557a37 | 489 | txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); |
86a74ff2 NI |
490 | } |
491 | ||
492 | /* Get skb and descriptor buffer */ | |
493 | static int sh_eth_ring_init(struct net_device *ndev) | |
494 | { | |
495 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
496 | int rx_ringsize, tx_ringsize, ret = 0; | |
497 | ||
498 | /* | |
499 | * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the | |
500 | * card needs room to do 8 byte alignment, +2 so we can reserve | |
501 | * the first 2 bytes, and +16 gets room for the status word from the | |
502 | * card. | |
503 | */ | |
504 | mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : | |
505 | (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); | |
503914cf MD |
506 | if (mdp->cd->rpadir) |
507 | mdp->rx_buf_sz += NET_IP_ALIGN; | |
86a74ff2 NI |
508 | |
509 | /* Allocate RX and TX skb rings */ | |
510 | mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE, | |
511 | GFP_KERNEL); | |
512 | if (!mdp->rx_skbuff) { | |
380af9e3 | 513 | dev_err(&ndev->dev, "Cannot allocate Rx skb\n"); |
86a74ff2 NI |
514 | ret = -ENOMEM; |
515 | return ret; | |
516 | } | |
517 | ||
518 | mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE, | |
519 | GFP_KERNEL); | |
520 | if (!mdp->tx_skbuff) { | |
380af9e3 | 521 | dev_err(&ndev->dev, "Cannot allocate Tx skb\n"); |
86a74ff2 NI |
522 | ret = -ENOMEM; |
523 | goto skb_ring_free; | |
524 | } | |
525 | ||
526 | /* Allocate all Rx descriptors. */ | |
527 | rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE; | |
528 | mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, | |
529 | GFP_KERNEL); | |
530 | ||
531 | if (!mdp->rx_ring) { | |
380af9e3 YS |
532 | dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n", |
533 | rx_ringsize); | |
86a74ff2 NI |
534 | ret = -ENOMEM; |
535 | goto desc_ring_free; | |
536 | } | |
537 | ||
538 | mdp->dirty_rx = 0; | |
539 | ||
540 | /* Allocate all Tx descriptors. */ | |
541 | tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE; | |
542 | mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, | |
543 | GFP_KERNEL); | |
544 | if (!mdp->tx_ring) { | |
380af9e3 YS |
545 | dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n", |
546 | tx_ringsize); | |
86a74ff2 NI |
547 | ret = -ENOMEM; |
548 | goto desc_ring_free; | |
549 | } | |
550 | return ret; | |
551 | ||
552 | desc_ring_free: | |
553 | /* free DMA buffer */ | |
554 | dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); | |
555 | ||
556 | skb_ring_free: | |
557 | /* Free Rx and Tx skb ring buffer */ | |
558 | sh_eth_ring_free(ndev); | |
559 | ||
560 | return ret; | |
561 | } | |
562 | ||
563 | static int sh_eth_dev_init(struct net_device *ndev) | |
564 | { | |
565 | int ret = 0; | |
566 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
567 | u32 ioaddr = ndev->base_addr; | |
568 | u_int32_t rx_int_var, tx_int_var; | |
569 | u32 val; | |
570 | ||
571 | /* Soft Reset */ | |
572 | sh_eth_reset(ndev); | |
573 | ||
b0ca2a21 NI |
574 | /* Descriptor format */ |
575 | sh_eth_ring_format(ndev); | |
380af9e3 YS |
576 | if (mdp->cd->rpadir) |
577 | ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR); | |
86a74ff2 NI |
578 | |
579 | /* all sh_eth int mask */ | |
580 | ctrl_outl(0, ioaddr + EESIPR); | |
581 | ||
380af9e3 YS |
582 | #if defined(__LITTLE_ENDIAN__) |
583 | if (mdp->cd->hw_swap) | |
584 | ctrl_outl(EDMR_EL, ioaddr + EDMR); | |
585 | else | |
b0ca2a21 | 586 | #endif |
380af9e3 | 587 | ctrl_outl(0, ioaddr + EDMR); |
86a74ff2 | 588 | |
b0ca2a21 | 589 | /* FIFO size set */ |
380af9e3 | 590 | ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR); |
86a74ff2 NI |
591 | ctrl_outl(0, ioaddr + TFTR); |
592 | ||
b0ca2a21 | 593 | /* Frame recv control */ |
380af9e3 | 594 | ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR); |
86a74ff2 NI |
595 | |
596 | rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; | |
597 | tx_int_var = mdp->tx_int_var = DESC_I_TINT2; | |
598 | ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER); | |
599 | ||
380af9e3 YS |
600 | if (mdp->cd->bculr) |
601 | ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */ | |
b0ca2a21 | 602 | |
380af9e3 | 603 | ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR); |
86a74ff2 | 604 | |
380af9e3 YS |
605 | if (!mdp->cd->no_trimd) |
606 | ctrl_outl(0, ioaddr + TRIMD); | |
86a74ff2 | 607 | |
b0ca2a21 NI |
608 | /* Recv frame limit set register */ |
609 | ctrl_outl(RFLR_VALUE, ioaddr + RFLR); | |
86a74ff2 NI |
610 | |
611 | ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR); | |
380af9e3 | 612 | ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR); |
86a74ff2 NI |
613 | |
614 | /* PAUSE Prohibition */ | |
615 | val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) | | |
616 | ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; | |
617 | ||
618 | ctrl_outl(val, ioaddr + ECMR); | |
b0ca2a21 | 619 | |
380af9e3 YS |
620 | if (mdp->cd->set_rate) |
621 | mdp->cd->set_rate(ndev); | |
622 | ||
b0ca2a21 | 623 | /* E-MAC Status Register clear */ |
380af9e3 | 624 | ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR); |
b0ca2a21 NI |
625 | |
626 | /* E-MAC Interrupt Enable register */ | |
380af9e3 | 627 | ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR); |
86a74ff2 NI |
628 | |
629 | /* Set MAC address */ | |
630 | update_mac_address(ndev); | |
631 | ||
632 | /* mask reset */ | |
380af9e3 YS |
633 | if (mdp->cd->apr) |
634 | ctrl_outl(APR_AP, ioaddr + APR); | |
635 | if (mdp->cd->mpr) | |
636 | ctrl_outl(MPR_MP, ioaddr + MPR); | |
637 | if (mdp->cd->tpauser) | |
638 | ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER); | |
b0ca2a21 | 639 | |
86a74ff2 NI |
640 | /* Setting the Rx mode will start the Rx process. */ |
641 | ctrl_outl(EDRRR_R, ioaddr + EDRRR); | |
642 | ||
643 | netif_start_queue(ndev); | |
644 | ||
645 | return ret; | |
646 | } | |
647 | ||
648 | /* free Tx skb function */ | |
649 | static int sh_eth_txfree(struct net_device *ndev) | |
650 | { | |
651 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
652 | struct sh_eth_txdesc *txdesc; | |
653 | int freeNum = 0; | |
654 | int entry = 0; | |
655 | ||
656 | for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { | |
657 | entry = mdp->dirty_tx % TX_RING_SIZE; | |
658 | txdesc = &mdp->tx_ring[entry]; | |
71557a37 | 659 | if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) |
86a74ff2 NI |
660 | break; |
661 | /* Free the original skb. */ | |
662 | if (mdp->tx_skbuff[entry]) { | |
663 | dev_kfree_skb_irq(mdp->tx_skbuff[entry]); | |
664 | mdp->tx_skbuff[entry] = NULL; | |
665 | freeNum++; | |
666 | } | |
71557a37 | 667 | txdesc->status = cpu_to_edmac(mdp, TD_TFP); |
86a74ff2 | 668 | if (entry >= TX_RING_SIZE - 1) |
71557a37 | 669 | txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); |
86a74ff2 NI |
670 | |
671 | mdp->stats.tx_packets++; | |
672 | mdp->stats.tx_bytes += txdesc->buffer_length; | |
673 | } | |
674 | return freeNum; | |
675 | } | |
676 | ||
677 | /* Packet receive function */ | |
678 | static int sh_eth_rx(struct net_device *ndev) | |
679 | { | |
680 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
681 | struct sh_eth_rxdesc *rxdesc; | |
682 | ||
683 | int entry = mdp->cur_rx % RX_RING_SIZE; | |
684 | int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx; | |
685 | struct sk_buff *skb; | |
686 | u16 pkt_len = 0; | |
380af9e3 | 687 | u32 desc_status; |
86a74ff2 NI |
688 | |
689 | rxdesc = &mdp->rx_ring[entry]; | |
71557a37 YS |
690 | while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { |
691 | desc_status = edmac_to_cpu(mdp, rxdesc->status); | |
86a74ff2 NI |
692 | pkt_len = rxdesc->frame_length; |
693 | ||
694 | if (--boguscnt < 0) | |
695 | break; | |
696 | ||
697 | if (!(desc_status & RDFEND)) | |
698 | mdp->stats.rx_length_errors++; | |
699 | ||
700 | if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | | |
701 | RD_RFS5 | RD_RFS6 | RD_RFS10)) { | |
702 | mdp->stats.rx_errors++; | |
703 | if (desc_status & RD_RFS1) | |
704 | mdp->stats.rx_crc_errors++; | |
705 | if (desc_status & RD_RFS2) | |
706 | mdp->stats.rx_frame_errors++; | |
707 | if (desc_status & RD_RFS3) | |
708 | mdp->stats.rx_length_errors++; | |
709 | if (desc_status & RD_RFS4) | |
710 | mdp->stats.rx_length_errors++; | |
711 | if (desc_status & RD_RFS6) | |
712 | mdp->stats.rx_missed_errors++; | |
713 | if (desc_status & RD_RFS10) | |
714 | mdp->stats.rx_over_errors++; | |
715 | } else { | |
380af9e3 YS |
716 | if (!mdp->cd->hw_swap) |
717 | sh_eth_soft_swap( | |
718 | phys_to_virt(ALIGN(rxdesc->addr, 4)), | |
719 | pkt_len + 2); | |
86a74ff2 NI |
720 | skb = mdp->rx_skbuff[entry]; |
721 | mdp->rx_skbuff[entry] = NULL; | |
503914cf MD |
722 | if (mdp->cd->rpadir) |
723 | skb_reserve(skb, NET_IP_ALIGN); | |
86a74ff2 NI |
724 | skb_put(skb, pkt_len); |
725 | skb->protocol = eth_type_trans(skb, ndev); | |
726 | netif_rx(skb); | |
86a74ff2 NI |
727 | mdp->stats.rx_packets++; |
728 | mdp->stats.rx_bytes += pkt_len; | |
729 | } | |
71557a37 | 730 | rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); |
86a74ff2 | 731 | entry = (++mdp->cur_rx) % RX_RING_SIZE; |
862df497 | 732 | rxdesc = &mdp->rx_ring[entry]; |
86a74ff2 NI |
733 | } |
734 | ||
735 | /* Refill the Rx ring buffers. */ | |
736 | for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { | |
737 | entry = mdp->dirty_rx % RX_RING_SIZE; | |
738 | rxdesc = &mdp->rx_ring[entry]; | |
b0ca2a21 | 739 | /* The size of the buffer is 16 byte boundary. */ |
0029d64a | 740 | rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); |
b0ca2a21 | 741 | |
86a74ff2 NI |
742 | if (mdp->rx_skbuff[entry] == NULL) { |
743 | skb = dev_alloc_skb(mdp->rx_buf_sz); | |
744 | mdp->rx_skbuff[entry] = skb; | |
745 | if (skb == NULL) | |
746 | break; /* Better luck next round. */ | |
e88aae7b YS |
747 | dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz, |
748 | DMA_FROM_DEVICE); | |
86a74ff2 | 749 | skb->dev = ndev; |
380af9e3 YS |
750 | sh_eth_set_receive_align(skb); |
751 | ||
b0ca2a21 | 752 | skb->ip_summed = CHECKSUM_NONE; |
0029d64a | 753 | rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); |
86a74ff2 | 754 | } |
86a74ff2 NI |
755 | if (entry >= RX_RING_SIZE - 1) |
756 | rxdesc->status |= | |
71557a37 | 757 | cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); |
86a74ff2 NI |
758 | else |
759 | rxdesc->status |= | |
71557a37 | 760 | cpu_to_edmac(mdp, RD_RACT | RD_RFP); |
86a74ff2 NI |
761 | } |
762 | ||
763 | /* Restart Rx engine if stopped. */ | |
764 | /* If we don't need to check status, don't. -KDU */ | |
b0ca2a21 NI |
765 | if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R)) |
766 | ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR); | |
86a74ff2 NI |
767 | |
768 | return 0; | |
769 | } | |
770 | ||
771 | /* error control function */ | |
772 | static void sh_eth_error(struct net_device *ndev, int intr_status) | |
773 | { | |
774 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
775 | u32 ioaddr = ndev->base_addr; | |
776 | u32 felic_stat; | |
380af9e3 YS |
777 | u32 link_stat; |
778 | u32 mask; | |
86a74ff2 NI |
779 | |
780 | if (intr_status & EESR_ECI) { | |
781 | felic_stat = ctrl_inl(ioaddr + ECSR); | |
782 | ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */ | |
783 | if (felic_stat & ECSR_ICD) | |
784 | mdp->stats.tx_carrier_errors++; | |
785 | if (felic_stat & ECSR_LCHNG) { | |
786 | /* Link Changed */ | |
4923576b | 787 | if (mdp->cd->no_psr || mdp->no_ether_link) { |
380af9e3 YS |
788 | if (mdp->link == PHY_DOWN) |
789 | link_stat = 0; | |
790 | else | |
791 | link_stat = PHY_ST_LINK; | |
792 | } else { | |
793 | link_stat = (ctrl_inl(ioaddr + PSR)); | |
4923576b YS |
794 | if (mdp->ether_link_active_low) |
795 | link_stat = ~link_stat; | |
380af9e3 | 796 | } |
86a74ff2 NI |
797 | if (!(link_stat & PHY_ST_LINK)) { |
798 | /* Link Down : disable tx and rx */ | |
799 | ctrl_outl(ctrl_inl(ioaddr + ECMR) & | |
800 | ~(ECMR_RE | ECMR_TE), ioaddr + ECMR); | |
801 | } else { | |
802 | /* Link Up */ | |
803 | ctrl_outl(ctrl_inl(ioaddr + EESIPR) & | |
804 | ~DMAC_M_ECI, ioaddr + EESIPR); | |
805 | /*clear int */ | |
806 | ctrl_outl(ctrl_inl(ioaddr + ECSR), | |
807 | ioaddr + ECSR); | |
808 | ctrl_outl(ctrl_inl(ioaddr + EESIPR) | | |
809 | DMAC_M_ECI, ioaddr + EESIPR); | |
810 | /* enable tx and rx */ | |
811 | ctrl_outl(ctrl_inl(ioaddr + ECMR) | | |
812 | (ECMR_RE | ECMR_TE), ioaddr + ECMR); | |
813 | } | |
814 | } | |
815 | } | |
816 | ||
817 | if (intr_status & EESR_TWB) { | |
818 | /* Write buck end. unused write back interrupt */ | |
819 | if (intr_status & EESR_TABT) /* Transmit Abort int */ | |
820 | mdp->stats.tx_aborted_errors++; | |
821 | } | |
822 | ||
823 | if (intr_status & EESR_RABT) { | |
824 | /* Receive Abort int */ | |
825 | if (intr_status & EESR_RFRMER) { | |
826 | /* Receive Frame Overflow int */ | |
827 | mdp->stats.rx_frame_errors++; | |
380af9e3 | 828 | dev_err(&ndev->dev, "Receive Frame Overflow\n"); |
86a74ff2 NI |
829 | } |
830 | } | |
380af9e3 YS |
831 | |
832 | if (!mdp->cd->no_ade) { | |
833 | if (intr_status & EESR_ADE && intr_status & EESR_TDE && | |
834 | intr_status & EESR_TFE) | |
835 | mdp->stats.tx_fifo_errors++; | |
86a74ff2 NI |
836 | } |
837 | ||
838 | if (intr_status & EESR_RDE) { | |
839 | /* Receive Descriptor Empty int */ | |
840 | mdp->stats.rx_over_errors++; | |
841 | ||
842 | if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R) | |
843 | ctrl_outl(EDRRR_R, ioaddr + EDRRR); | |
380af9e3 | 844 | dev_err(&ndev->dev, "Receive Descriptor Empty\n"); |
86a74ff2 NI |
845 | } |
846 | if (intr_status & EESR_RFE) { | |
847 | /* Receive FIFO Overflow int */ | |
848 | mdp->stats.rx_fifo_errors++; | |
380af9e3 | 849 | dev_err(&ndev->dev, "Receive FIFO Overflow\n"); |
86a74ff2 | 850 | } |
380af9e3 YS |
851 | |
852 | mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; | |
853 | if (mdp->cd->no_ade) | |
854 | mask &= ~EESR_ADE; | |
855 | if (intr_status & mask) { | |
86a74ff2 NI |
856 | /* Tx error */ |
857 | u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR); | |
858 | /* dmesg */ | |
380af9e3 YS |
859 | dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", |
860 | intr_status, mdp->cur_tx); | |
861 | dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", | |
86a74ff2 NI |
862 | mdp->dirty_tx, (u32) ndev->state, edtrr); |
863 | /* dirty buffer free */ | |
864 | sh_eth_txfree(ndev); | |
865 | ||
866 | /* SH7712 BUG */ | |
867 | if (edtrr ^ EDTRR_TRNS) { | |
868 | /* tx dma start */ | |
869 | ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR); | |
870 | } | |
871 | /* wakeup */ | |
872 | netif_wake_queue(ndev); | |
873 | } | |
874 | } | |
875 | ||
876 | static irqreturn_t sh_eth_interrupt(int irq, void *netdev) | |
877 | { | |
878 | struct net_device *ndev = netdev; | |
879 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
380af9e3 | 880 | struct sh_eth_cpu_data *cd = mdp->cd; |
0e0fde3c | 881 | irqreturn_t ret = IRQ_NONE; |
37c8ae3a | 882 | u32 ioaddr, intr_status = 0; |
86a74ff2 NI |
883 | |
884 | ioaddr = ndev->base_addr; | |
885 | spin_lock(&mdp->lock); | |
886 | ||
b0ca2a21 | 887 | /* Get interrpt stat */ |
86a74ff2 NI |
888 | intr_status = ctrl_inl(ioaddr + EESR); |
889 | /* Clear interrupt */ | |
0e0fde3c NI |
890 | if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | |
891 | EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | | |
380af9e3 | 892 | cd->tx_check | cd->eesr_err_check)) { |
0e0fde3c NI |
893 | ctrl_outl(intr_status, ioaddr + EESR); |
894 | ret = IRQ_HANDLED; | |
895 | } else | |
896 | goto other_irq; | |
86a74ff2 | 897 | |
b0ca2a21 NI |
898 | if (intr_status & (EESR_FRC | /* Frame recv*/ |
899 | EESR_RMAF | /* Multi cast address recv*/ | |
900 | EESR_RRF | /* Bit frame recv */ | |
901 | EESR_RTLF | /* Long frame recv*/ | |
902 | EESR_RTSF | /* short frame recv */ | |
903 | EESR_PRE | /* PHY-LSI recv error */ | |
904 | EESR_CERF)){ /* recv frame CRC error */ | |
86a74ff2 | 905 | sh_eth_rx(ndev); |
b0ca2a21 | 906 | } |
86a74ff2 | 907 | |
b0ca2a21 | 908 | /* Tx Check */ |
380af9e3 | 909 | if (intr_status & cd->tx_check) { |
86a74ff2 NI |
910 | sh_eth_txfree(ndev); |
911 | netif_wake_queue(ndev); | |
912 | } | |
913 | ||
380af9e3 | 914 | if (intr_status & cd->eesr_err_check) |
86a74ff2 NI |
915 | sh_eth_error(ndev, intr_status); |
916 | ||
0e0fde3c | 917 | other_irq: |
86a74ff2 NI |
918 | spin_unlock(&mdp->lock); |
919 | ||
0e0fde3c | 920 | return ret; |
86a74ff2 NI |
921 | } |
922 | ||
923 | static void sh_eth_timer(unsigned long data) | |
924 | { | |
925 | struct net_device *ndev = (struct net_device *)data; | |
926 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
927 | ||
928 | mod_timer(&mdp->timer, jiffies + (10 * HZ)); | |
929 | } | |
930 | ||
931 | /* PHY state control function */ | |
932 | static void sh_eth_adjust_link(struct net_device *ndev) | |
933 | { | |
934 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
935 | struct phy_device *phydev = mdp->phydev; | |
936 | u32 ioaddr = ndev->base_addr; | |
937 | int new_state = 0; | |
938 | ||
939 | if (phydev->link != PHY_DOWN) { | |
940 | if (phydev->duplex != mdp->duplex) { | |
941 | new_state = 1; | |
942 | mdp->duplex = phydev->duplex; | |
380af9e3 YS |
943 | if (mdp->cd->set_duplex) |
944 | mdp->cd->set_duplex(ndev); | |
86a74ff2 NI |
945 | } |
946 | ||
947 | if (phydev->speed != mdp->speed) { | |
948 | new_state = 1; | |
949 | mdp->speed = phydev->speed; | |
380af9e3 YS |
950 | if (mdp->cd->set_rate) |
951 | mdp->cd->set_rate(ndev); | |
86a74ff2 NI |
952 | } |
953 | if (mdp->link == PHY_DOWN) { | |
954 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF) | |
955 | | ECMR_DM, ioaddr + ECMR); | |
956 | new_state = 1; | |
957 | mdp->link = phydev->link; | |
86a74ff2 NI |
958 | } |
959 | } else if (mdp->link) { | |
960 | new_state = 1; | |
961 | mdp->link = PHY_DOWN; | |
962 | mdp->speed = 0; | |
963 | mdp->duplex = -1; | |
86a74ff2 NI |
964 | } |
965 | ||
966 | if (new_state) | |
967 | phy_print_status(phydev); | |
968 | } | |
969 | ||
970 | /* PHY init function */ | |
971 | static int sh_eth_phy_init(struct net_device *ndev) | |
972 | { | |
973 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
0a372eb9 | 974 | char phy_id[MII_BUS_ID_SIZE + 3]; |
86a74ff2 NI |
975 | struct phy_device *phydev = NULL; |
976 | ||
fb28ad35 | 977 | snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, |
86a74ff2 NI |
978 | mdp->mii_bus->id , mdp->phy_id); |
979 | ||
980 | mdp->link = PHY_DOWN; | |
981 | mdp->speed = 0; | |
982 | mdp->duplex = -1; | |
983 | ||
984 | /* Try connect to PHY */ | |
985 | phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link, | |
986 | 0, PHY_INTERFACE_MODE_MII); | |
987 | if (IS_ERR(phydev)) { | |
988 | dev_err(&ndev->dev, "phy_connect failed\n"); | |
989 | return PTR_ERR(phydev); | |
990 | } | |
380af9e3 | 991 | |
86a74ff2 | 992 | dev_info(&ndev->dev, "attached phy %i to driver %s\n", |
380af9e3 | 993 | phydev->addr, phydev->drv->name); |
86a74ff2 NI |
994 | |
995 | mdp->phydev = phydev; | |
996 | ||
997 | return 0; | |
998 | } | |
999 | ||
1000 | /* PHY control start function */ | |
1001 | static int sh_eth_phy_start(struct net_device *ndev) | |
1002 | { | |
1003 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1004 | int ret; | |
1005 | ||
1006 | ret = sh_eth_phy_init(ndev); | |
1007 | if (ret) | |
1008 | return ret; | |
1009 | ||
1010 | /* reset phy - this also wakes it from PDOWN */ | |
1011 | phy_write(mdp->phydev, MII_BMCR, BMCR_RESET); | |
1012 | phy_start(mdp->phydev); | |
1013 | ||
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | /* network device open function */ | |
1018 | static int sh_eth_open(struct net_device *ndev) | |
1019 | { | |
1020 | int ret = 0; | |
1021 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1022 | ||
bcd5149d MD |
1023 | pm_runtime_get_sync(&mdp->pdev->dev); |
1024 | ||
a0607fd3 | 1025 | ret = request_irq(ndev->irq, sh_eth_interrupt, |
0e0fde3c NI |
1026 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764) |
1027 | IRQF_SHARED, | |
1028 | #else | |
1029 | 0, | |
1030 | #endif | |
1031 | ndev->name, ndev); | |
86a74ff2 | 1032 | if (ret) { |
380af9e3 | 1033 | dev_err(&ndev->dev, "Can not assign IRQ number\n"); |
86a74ff2 NI |
1034 | return ret; |
1035 | } | |
1036 | ||
1037 | /* Descriptor set */ | |
1038 | ret = sh_eth_ring_init(ndev); | |
1039 | if (ret) | |
1040 | goto out_free_irq; | |
1041 | ||
1042 | /* device init */ | |
1043 | ret = sh_eth_dev_init(ndev); | |
1044 | if (ret) | |
1045 | goto out_free_irq; | |
1046 | ||
1047 | /* PHY control start*/ | |
1048 | ret = sh_eth_phy_start(ndev); | |
1049 | if (ret) | |
1050 | goto out_free_irq; | |
1051 | ||
1052 | /* Set the timer to check for link beat. */ | |
1053 | init_timer(&mdp->timer); | |
1054 | mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ | |
b0ca2a21 | 1055 | setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev); |
86a74ff2 NI |
1056 | |
1057 | return ret; | |
1058 | ||
1059 | out_free_irq: | |
1060 | free_irq(ndev->irq, ndev); | |
bcd5149d | 1061 | pm_runtime_put_sync(&mdp->pdev->dev); |
86a74ff2 NI |
1062 | return ret; |
1063 | } | |
1064 | ||
1065 | /* Timeout function */ | |
1066 | static void sh_eth_tx_timeout(struct net_device *ndev) | |
1067 | { | |
1068 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1069 | u32 ioaddr = ndev->base_addr; | |
1070 | struct sh_eth_rxdesc *rxdesc; | |
1071 | int i; | |
1072 | ||
1073 | netif_stop_queue(ndev); | |
1074 | ||
1075 | /* worning message out. */ | |
1076 | printk(KERN_WARNING "%s: transmit timed out, status %8.8x," | |
1077 | " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR)); | |
1078 | ||
1079 | /* tx_errors count up */ | |
1080 | mdp->stats.tx_errors++; | |
1081 | ||
1082 | /* timer off */ | |
1083 | del_timer_sync(&mdp->timer); | |
1084 | ||
1085 | /* Free all the skbuffs in the Rx queue. */ | |
1086 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1087 | rxdesc = &mdp->rx_ring[i]; | |
1088 | rxdesc->status = 0; | |
1089 | rxdesc->addr = 0xBADF00D0; | |
1090 | if (mdp->rx_skbuff[i]) | |
1091 | dev_kfree_skb(mdp->rx_skbuff[i]); | |
1092 | mdp->rx_skbuff[i] = NULL; | |
1093 | } | |
1094 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1095 | if (mdp->tx_skbuff[i]) | |
1096 | dev_kfree_skb(mdp->tx_skbuff[i]); | |
1097 | mdp->tx_skbuff[i] = NULL; | |
1098 | } | |
1099 | ||
1100 | /* device init */ | |
1101 | sh_eth_dev_init(ndev); | |
1102 | ||
1103 | /* timer on */ | |
1104 | mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ | |
1105 | add_timer(&mdp->timer); | |
1106 | } | |
1107 | ||
1108 | /* Packet transmit function */ | |
1109 | static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) | |
1110 | { | |
1111 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1112 | struct sh_eth_txdesc *txdesc; | |
1113 | u32 entry; | |
fb5e2f9b | 1114 | unsigned long flags; |
86a74ff2 NI |
1115 | |
1116 | spin_lock_irqsave(&mdp->lock, flags); | |
1117 | if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) { | |
1118 | if (!sh_eth_txfree(ndev)) { | |
1119 | netif_stop_queue(ndev); | |
1120 | spin_unlock_irqrestore(&mdp->lock, flags); | |
5b548140 | 1121 | return NETDEV_TX_BUSY; |
86a74ff2 NI |
1122 | } |
1123 | } | |
1124 | spin_unlock_irqrestore(&mdp->lock, flags); | |
1125 | ||
1126 | entry = mdp->cur_tx % TX_RING_SIZE; | |
1127 | mdp->tx_skbuff[entry] = skb; | |
1128 | txdesc = &mdp->tx_ring[entry]; | |
0029d64a | 1129 | txdesc->addr = virt_to_phys(skb->data); |
86a74ff2 | 1130 | /* soft swap. */ |
380af9e3 YS |
1131 | if (!mdp->cd->hw_swap) |
1132 | sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), | |
1133 | skb->len + 2); | |
86a74ff2 NI |
1134 | /* write back */ |
1135 | __flush_purge_region(skb->data, skb->len); | |
1136 | if (skb->len < ETHERSMALL) | |
1137 | txdesc->buffer_length = ETHERSMALL; | |
1138 | else | |
1139 | txdesc->buffer_length = skb->len; | |
1140 | ||
1141 | if (entry >= TX_RING_SIZE - 1) | |
71557a37 | 1142 | txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); |
86a74ff2 | 1143 | else |
71557a37 | 1144 | txdesc->status |= cpu_to_edmac(mdp, TD_TACT); |
86a74ff2 NI |
1145 | |
1146 | mdp->cur_tx++; | |
1147 | ||
b0ca2a21 NI |
1148 | if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS)) |
1149 | ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR); | |
1150 | ||
6ed10654 | 1151 | return NETDEV_TX_OK; |
86a74ff2 NI |
1152 | } |
1153 | ||
1154 | /* device close function */ | |
1155 | static int sh_eth_close(struct net_device *ndev) | |
1156 | { | |
1157 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1158 | u32 ioaddr = ndev->base_addr; | |
1159 | int ringsize; | |
1160 | ||
1161 | netif_stop_queue(ndev); | |
1162 | ||
1163 | /* Disable interrupts by clearing the interrupt mask. */ | |
1164 | ctrl_outl(0x0000, ioaddr + EESIPR); | |
1165 | ||
1166 | /* Stop the chip's Tx and Rx processes. */ | |
1167 | ctrl_outl(0, ioaddr + EDTRR); | |
1168 | ctrl_outl(0, ioaddr + EDRRR); | |
1169 | ||
1170 | /* PHY Disconnect */ | |
1171 | if (mdp->phydev) { | |
1172 | phy_stop(mdp->phydev); | |
1173 | phy_disconnect(mdp->phydev); | |
1174 | } | |
1175 | ||
1176 | free_irq(ndev->irq, ndev); | |
1177 | ||
1178 | del_timer_sync(&mdp->timer); | |
1179 | ||
1180 | /* Free all the skbuffs in the Rx queue. */ | |
1181 | sh_eth_ring_free(ndev); | |
1182 | ||
1183 | /* free DMA buffer */ | |
1184 | ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE; | |
1185 | dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma); | |
1186 | ||
1187 | /* free DMA buffer */ | |
1188 | ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE; | |
1189 | dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma); | |
1190 | ||
bcd5149d MD |
1191 | pm_runtime_put_sync(&mdp->pdev->dev); |
1192 | ||
86a74ff2 NI |
1193 | return 0; |
1194 | } | |
1195 | ||
1196 | static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) | |
1197 | { | |
1198 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1199 | u32 ioaddr = ndev->base_addr; | |
1200 | ||
bcd5149d MD |
1201 | pm_runtime_get_sync(&mdp->pdev->dev); |
1202 | ||
86a74ff2 NI |
1203 | mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR); |
1204 | ctrl_outl(0, ioaddr + TROCR); /* (write clear) */ | |
1205 | mdp->stats.collisions += ctrl_inl(ioaddr + CDCR); | |
1206 | ctrl_outl(0, ioaddr + CDCR); /* (write clear) */ | |
1207 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR); | |
1208 | ctrl_outl(0, ioaddr + LCCR); /* (write clear) */ | |
b0ca2a21 NI |
1209 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
1210 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */ | |
1211 | ctrl_outl(0, ioaddr + CERCR); /* (write clear) */ | |
1212 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */ | |
1213 | ctrl_outl(0, ioaddr + CEECR); /* (write clear) */ | |
1214 | #else | |
86a74ff2 NI |
1215 | mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR); |
1216 | ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */ | |
b0ca2a21 | 1217 | #endif |
bcd5149d MD |
1218 | pm_runtime_put_sync(&mdp->pdev->dev); |
1219 | ||
86a74ff2 NI |
1220 | return &mdp->stats; |
1221 | } | |
1222 | ||
1223 | /* ioctl to device funciotn*/ | |
1224 | static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, | |
1225 | int cmd) | |
1226 | { | |
1227 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1228 | struct phy_device *phydev = mdp->phydev; | |
1229 | ||
1230 | if (!netif_running(ndev)) | |
1231 | return -EINVAL; | |
1232 | ||
1233 | if (!phydev) | |
1234 | return -ENODEV; | |
1235 | ||
1236 | return phy_mii_ioctl(phydev, if_mii(rq), cmd); | |
1237 | } | |
1238 | ||
380af9e3 | 1239 | #if defined(SH_ETH_HAS_TSU) |
86a74ff2 NI |
1240 | /* Multicast reception directions set */ |
1241 | static void sh_eth_set_multicast_list(struct net_device *ndev) | |
1242 | { | |
1243 | u32 ioaddr = ndev->base_addr; | |
1244 | ||
1245 | if (ndev->flags & IFF_PROMISC) { | |
1246 | /* Set promiscuous. */ | |
1247 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM, | |
1248 | ioaddr + ECMR); | |
1249 | } else { | |
1250 | /* Normal, unicast/broadcast-only mode. */ | |
1251 | ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT, | |
1252 | ioaddr + ECMR); | |
1253 | } | |
1254 | } | |
1255 | ||
1256 | /* SuperH's TSU register init function */ | |
1257 | static void sh_eth_tsu_init(u32 ioaddr) | |
1258 | { | |
1259 | ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */ | |
1260 | ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */ | |
1261 | ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */ | |
1262 | ctrl_outl(0xc, ioaddr + TSU_BSYSL0); | |
1263 | ctrl_outl(0xc, ioaddr + TSU_BSYSL1); | |
1264 | ctrl_outl(0, ioaddr + TSU_PRISL0); | |
1265 | ctrl_outl(0, ioaddr + TSU_PRISL1); | |
1266 | ctrl_outl(0, ioaddr + TSU_FWSL0); | |
1267 | ctrl_outl(0, ioaddr + TSU_FWSL1); | |
1268 | ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC); | |
b0ca2a21 NI |
1269 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) |
1270 | ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */ | |
1271 | ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */ | |
1272 | #else | |
86a74ff2 NI |
1273 | ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */ |
1274 | ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */ | |
b0ca2a21 | 1275 | #endif |
86a74ff2 NI |
1276 | ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */ |
1277 | ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */ | |
1278 | ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */ | |
1279 | ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */ | |
1280 | ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */ | |
1281 | ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */ | |
1282 | ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */ | |
1283 | } | |
380af9e3 | 1284 | #endif /* SH_ETH_HAS_TSU */ |
86a74ff2 NI |
1285 | |
1286 | /* MDIO bus release function */ | |
1287 | static int sh_mdio_release(struct net_device *ndev) | |
1288 | { | |
1289 | struct mii_bus *bus = dev_get_drvdata(&ndev->dev); | |
1290 | ||
1291 | /* unregister mdio bus */ | |
1292 | mdiobus_unregister(bus); | |
1293 | ||
1294 | /* remove mdio bus info from net_device */ | |
1295 | dev_set_drvdata(&ndev->dev, NULL); | |
1296 | ||
0f0b405c DK |
1297 | /* free interrupts memory */ |
1298 | kfree(bus->irq); | |
1299 | ||
86a74ff2 NI |
1300 | /* free bitbang info */ |
1301 | free_mdio_bitbang(bus); | |
1302 | ||
1303 | return 0; | |
1304 | } | |
1305 | ||
1306 | /* MDIO bus init function */ | |
1307 | static int sh_mdio_init(struct net_device *ndev, int id) | |
1308 | { | |
1309 | int ret, i; | |
1310 | struct bb_info *bitbang; | |
1311 | struct sh_eth_private *mdp = netdev_priv(ndev); | |
1312 | ||
1313 | /* create bit control struct for PHY */ | |
1314 | bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL); | |
1315 | if (!bitbang) { | |
1316 | ret = -ENOMEM; | |
1317 | goto out; | |
1318 | } | |
1319 | ||
1320 | /* bitbang init */ | |
1321 | bitbang->addr = ndev->base_addr + PIR; | |
1322 | bitbang->mdi_msk = 0x08; | |
1323 | bitbang->mdo_msk = 0x04; | |
1324 | bitbang->mmd_msk = 0x02;/* MMD */ | |
1325 | bitbang->mdc_msk = 0x01; | |
1326 | bitbang->ctrl.ops = &bb_ops; | |
1327 | ||
1328 | /* MII contorller setting */ | |
1329 | mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); | |
1330 | if (!mdp->mii_bus) { | |
1331 | ret = -ENOMEM; | |
1332 | goto out_free_bitbang; | |
1333 | } | |
1334 | ||
1335 | /* Hook up MII support for ethtool */ | |
1336 | mdp->mii_bus->name = "sh_mii"; | |
18ee49dd | 1337 | mdp->mii_bus->parent = &ndev->dev; |
fb5e2f9b | 1338 | snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id); |
86a74ff2 NI |
1339 | |
1340 | /* PHY IRQ */ | |
1341 | mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
1342 | if (!mdp->mii_bus->irq) { | |
1343 | ret = -ENOMEM; | |
1344 | goto out_free_bus; | |
1345 | } | |
1346 | ||
1347 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
1348 | mdp->mii_bus->irq[i] = PHY_POLL; | |
1349 | ||
1350 | /* regist mdio bus */ | |
1351 | ret = mdiobus_register(mdp->mii_bus); | |
1352 | if (ret) | |
1353 | goto out_free_irq; | |
1354 | ||
1355 | dev_set_drvdata(&ndev->dev, mdp->mii_bus); | |
1356 | ||
1357 | return 0; | |
1358 | ||
1359 | out_free_irq: | |
1360 | kfree(mdp->mii_bus->irq); | |
1361 | ||
1362 | out_free_bus: | |
298cf9be | 1363 | free_mdio_bitbang(mdp->mii_bus); |
86a74ff2 NI |
1364 | |
1365 | out_free_bitbang: | |
1366 | kfree(bitbang); | |
1367 | ||
1368 | out: | |
1369 | return ret; | |
1370 | } | |
1371 | ||
ebf84eaa AB |
1372 | static const struct net_device_ops sh_eth_netdev_ops = { |
1373 | .ndo_open = sh_eth_open, | |
1374 | .ndo_stop = sh_eth_close, | |
1375 | .ndo_start_xmit = sh_eth_start_xmit, | |
1376 | .ndo_get_stats = sh_eth_get_stats, | |
380af9e3 | 1377 | #if defined(SH_ETH_HAS_TSU) |
ebf84eaa | 1378 | .ndo_set_multicast_list = sh_eth_set_multicast_list, |
380af9e3 | 1379 | #endif |
ebf84eaa AB |
1380 | .ndo_tx_timeout = sh_eth_tx_timeout, |
1381 | .ndo_do_ioctl = sh_eth_do_ioctl, | |
1382 | .ndo_validate_addr = eth_validate_addr, | |
1383 | .ndo_set_mac_address = eth_mac_addr, | |
1384 | .ndo_change_mtu = eth_change_mtu, | |
1385 | }; | |
1386 | ||
86a74ff2 NI |
1387 | static int sh_eth_drv_probe(struct platform_device *pdev) |
1388 | { | |
1389 | int ret, i, devno = 0; | |
1390 | struct resource *res; | |
1391 | struct net_device *ndev = NULL; | |
1392 | struct sh_eth_private *mdp; | |
71557a37 | 1393 | struct sh_eth_plat_data *pd; |
86a74ff2 NI |
1394 | |
1395 | /* get base addr */ | |
1396 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1397 | if (unlikely(res == NULL)) { | |
1398 | dev_err(&pdev->dev, "invalid resource\n"); | |
1399 | ret = -EINVAL; | |
1400 | goto out; | |
1401 | } | |
1402 | ||
1403 | ndev = alloc_etherdev(sizeof(struct sh_eth_private)); | |
1404 | if (!ndev) { | |
380af9e3 | 1405 | dev_err(&pdev->dev, "Could not allocate device.\n"); |
86a74ff2 NI |
1406 | ret = -ENOMEM; |
1407 | goto out; | |
1408 | } | |
1409 | ||
1410 | /* The sh Ether-specific entries in the device structure. */ | |
1411 | ndev->base_addr = res->start; | |
1412 | devno = pdev->id; | |
1413 | if (devno < 0) | |
1414 | devno = 0; | |
1415 | ||
1416 | ndev->dma = -1; | |
cc3c080d | 1417 | ret = platform_get_irq(pdev, 0); |
1418 | if (ret < 0) { | |
86a74ff2 NI |
1419 | ret = -ENODEV; |
1420 | goto out_release; | |
1421 | } | |
cc3c080d | 1422 | ndev->irq = ret; |
86a74ff2 NI |
1423 | |
1424 | SET_NETDEV_DEV(ndev, &pdev->dev); | |
1425 | ||
1426 | /* Fill in the fields of the device structure with ethernet values. */ | |
1427 | ether_setup(ndev); | |
1428 | ||
1429 | mdp = netdev_priv(ndev); | |
1430 | spin_lock_init(&mdp->lock); | |
bcd5149d MD |
1431 | mdp->pdev = pdev; |
1432 | pm_runtime_enable(&pdev->dev); | |
1433 | pm_runtime_resume(&pdev->dev); | |
86a74ff2 | 1434 | |
71557a37 | 1435 | pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data); |
86a74ff2 | 1436 | /* get PHY ID */ |
71557a37 YS |
1437 | mdp->phy_id = pd->phy; |
1438 | /* EDMAC endian */ | |
1439 | mdp->edmac_endian = pd->edmac_endian; | |
4923576b YS |
1440 | mdp->no_ether_link = pd->no_ether_link; |
1441 | mdp->ether_link_active_low = pd->ether_link_active_low; | |
86a74ff2 | 1442 | |
380af9e3 YS |
1443 | /* set cpu data */ |
1444 | mdp->cd = &sh_eth_my_cpu_data; | |
1445 | sh_eth_set_default_cpu_data(mdp->cd); | |
1446 | ||
86a74ff2 | 1447 | /* set function */ |
ebf84eaa | 1448 | ndev->netdev_ops = &sh_eth_netdev_ops; |
86a74ff2 NI |
1449 | ndev->watchdog_timeo = TX_TIMEOUT; |
1450 | ||
1451 | mdp->post_rx = POST_RX >> (devno << 1); | |
1452 | mdp->post_fw = POST_FW >> (devno << 1); | |
1453 | ||
1454 | /* read and set MAC address */ | |
748031f9 | 1455 | read_mac_address(ndev, pd->mac_addr); |
86a74ff2 NI |
1456 | |
1457 | /* First device only init */ | |
1458 | if (!devno) { | |
380af9e3 YS |
1459 | if (mdp->cd->chip_reset) |
1460 | mdp->cd->chip_reset(ndev); | |
86a74ff2 | 1461 | |
380af9e3 | 1462 | #if defined(SH_ETH_HAS_TSU) |
86a74ff2 NI |
1463 | /* TSU init (Init only)*/ |
1464 | sh_eth_tsu_init(SH_TSU_ADDR); | |
71557a37 | 1465 | #endif |
86a74ff2 NI |
1466 | } |
1467 | ||
1468 | /* network device register */ | |
1469 | ret = register_netdev(ndev); | |
1470 | if (ret) | |
1471 | goto out_release; | |
1472 | ||
1473 | /* mdio bus init */ | |
1474 | ret = sh_mdio_init(ndev, pdev->id); | |
1475 | if (ret) | |
1476 | goto out_unregister; | |
1477 | ||
6cd9b49d HS |
1478 | /* print device infomation */ |
1479 | pr_info("Base address at 0x%x, %pM, IRQ %d.\n", | |
1480 | (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); | |
86a74ff2 NI |
1481 | |
1482 | platform_set_drvdata(pdev, ndev); | |
1483 | ||
1484 | return ret; | |
1485 | ||
1486 | out_unregister: | |
1487 | unregister_netdev(ndev); | |
1488 | ||
1489 | out_release: | |
1490 | /* net_dev free */ | |
1491 | if (ndev) | |
1492 | free_netdev(ndev); | |
1493 | ||
1494 | out: | |
1495 | return ret; | |
1496 | } | |
1497 | ||
1498 | static int sh_eth_drv_remove(struct platform_device *pdev) | |
1499 | { | |
1500 | struct net_device *ndev = platform_get_drvdata(pdev); | |
1501 | ||
1502 | sh_mdio_release(ndev); | |
1503 | unregister_netdev(ndev); | |
1504 | flush_scheduled_work(); | |
bcd5149d | 1505 | pm_runtime_disable(&pdev->dev); |
86a74ff2 NI |
1506 | free_netdev(ndev); |
1507 | platform_set_drvdata(pdev, NULL); | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
bcd5149d MD |
1512 | static int sh_eth_runtime_nop(struct device *dev) |
1513 | { | |
1514 | /* | |
1515 | * Runtime PM callback shared between ->runtime_suspend() | |
1516 | * and ->runtime_resume(). Simply returns success. | |
1517 | * | |
1518 | * This driver re-initializes all registers after | |
1519 | * pm_runtime_get_sync() anyway so there is no need | |
1520 | * to save and restore registers here. | |
1521 | */ | |
1522 | return 0; | |
1523 | } | |
1524 | ||
1525 | static struct dev_pm_ops sh_eth_dev_pm_ops = { | |
1526 | .runtime_suspend = sh_eth_runtime_nop, | |
1527 | .runtime_resume = sh_eth_runtime_nop, | |
1528 | }; | |
1529 | ||
86a74ff2 NI |
1530 | static struct platform_driver sh_eth_driver = { |
1531 | .probe = sh_eth_drv_probe, | |
1532 | .remove = sh_eth_drv_remove, | |
1533 | .driver = { | |
1534 | .name = CARDNAME, | |
bcd5149d | 1535 | .pm = &sh_eth_dev_pm_ops, |
86a74ff2 NI |
1536 | }, |
1537 | }; | |
1538 | ||
1539 | static int __init sh_eth_init(void) | |
1540 | { | |
1541 | return platform_driver_register(&sh_eth_driver); | |
1542 | } | |
1543 | ||
1544 | static void __exit sh_eth_cleanup(void) | |
1545 | { | |
1546 | platform_driver_unregister(&sh_eth_driver); | |
1547 | } | |
1548 | ||
1549 | module_init(sh_eth_init); | |
1550 | module_exit(sh_eth_cleanup); | |
1551 | ||
1552 | MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); | |
1553 | MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); | |
1554 | MODULE_LICENSE("GPL v2"); |