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net: sh_eth: add support for SH7757's GETHER
[deliverable/linux.git] / drivers / net / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
b0ca2a21 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
380af9e3 5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
86a74ff2
NI		 23#include <linux/init.h>
24#include <linux/dma-mapping.h>
25#include <linux/etherdevice.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mdio-bitbang.h>
29#include <linux/netdevice.h>
30#include <linux/phy.h>
31#include <linux/cache.h>
32#include <linux/io.h>
bcd5149d 33#include <linux/pm_runtime.h>
5a0e3ad6 34#include <linux/slab.h>
dc19e4e5 35#include <linux/ethtool.h>
f568a926 36#include <asm/cacheflush.h>
86a74ff2
NI		 37
38#include "sh_eth.h"
39
dc19e4e5
NI		 40#define SH_ETH_DEF_MSG_ENABLE \
41 (NETIF_MSG_LINK | \
42 NETIF_MSG_TIMER | \
43 NETIF_MSG_RX_ERR| \
44 NETIF_MSG_TX_ERR)
45
380af9e3 46/* There is CPU dependent code */
65ac8851
YS		 47#if defined(CONFIG_CPU_SUBTYPE_SH7724)
48#define SH_ETH_RESET_DEFAULT 1
49static void sh_eth_set_duplex(struct net_device *ndev)
50{
51 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 52
53 if (mdp->duplex) /* Full */
4a55530f 54 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 55 else /* Half */
4a55530f 56 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 57}
58
59static void sh_eth_set_rate(struct net_device *ndev)
60{
61 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 62
63 switch (mdp->speed) {
64 case 10: /* 10BASE */
4a55530f 65 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 66 break;
67 case 100:/* 100BASE */
4a55530f 68 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 69 break;
70 default:
71 break;
72 }
73}
74
75/* SH7724 */
76static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
77 .set_duplex = sh_eth_set_duplex,
78 .set_rate = sh_eth_set_rate,
79
80 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
81 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
82 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
83
84 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
85 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
86 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
87 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
88
89 .apr = 1,
90 .mpr = 1,
91 .tpauser = 1,
92 .hw_swap = 1,
503914cf
MD		 93 .rpadir = 1,
94 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 95};
f29a3d04 96#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
8fcd4961
YS		 97#define SH_ETH_HAS_BOTH_MODULES 1
98#define SH_ETH_HAS_TSU 1
f29a3d04
YS		 99static void sh_eth_set_duplex(struct net_device *ndev)
100{
101 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 102
103 if (mdp->duplex) /* Full */
4a55530f 104 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
f29a3d04 105 else /* Half */
4a55530f 106 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
f29a3d04
YS		 107}
108
109static void sh_eth_set_rate(struct net_device *ndev)
110{
111 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 112
113 switch (mdp->speed) {
114 case 10: /* 10BASE */
4a55530f 115 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 116 break;
117 case 100:/* 100BASE */
4a55530f 118 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 119 break;
120 default:
121 break;
122 }
123}
124
125/* SH7757 */
126static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
127 .set_duplex = sh_eth_set_duplex,
128 .set_rate = sh_eth_set_rate,
129
130 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
131 .rmcr_value = 0x00000001,
132
133 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
134 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
135 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
136 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
137
138 .apr = 1,
139 .mpr = 1,
140 .tpauser = 1,
141 .hw_swap = 1,
142 .no_ade = 1,
143};
65ac8851 144
8fcd4961
YS		 145#define SH_GIGA_ETH_BASE 0xfee00000
146#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
147#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
148static void sh_eth_chip_reset_giga(struct net_device *ndev)
149{
150 int i;
151 unsigned long mahr[2], malr[2];
152
153 /* save MAHR and MALR */
154 for (i = 0; i < 2; i++) {
155 malr[i] = readl(GIGA_MALR(i));
156 mahr[i] = readl(GIGA_MAHR(i));
157 }
158
159 /* reset device */
160 writel(ARSTR_ARSTR, SH_GIGA_ETH_BASE + 0x1800);
161 mdelay(1);
162
163 /* restore MAHR and MALR */
164 for (i = 0; i < 2; i++) {
165 writel(malr[i], GIGA_MALR(i));
166 writel(mahr[i], GIGA_MAHR(i));
167 }
168}
169
170static int sh_eth_is_gether(struct sh_eth_private *mdp);
171static void sh_eth_reset(struct net_device *ndev)
172{
173 struct sh_eth_private *mdp = netdev_priv(ndev);
174 int cnt = 100;
175
176 if (sh_eth_is_gether(mdp)) {
177 sh_eth_write(ndev, 0x03, EDSR);
178 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
179 EDMR);
180 while (cnt > 0) {
181 if (!(sh_eth_read(ndev, EDMR) & 0x3))
182 break;
183 mdelay(1);
184 cnt--;
185 }
186 if (cnt < 0)
187 printk(KERN_ERR "Device reset fail\n");
188
189 /* Table Init */
190 sh_eth_write(ndev, 0x0, TDLAR);
191 sh_eth_write(ndev, 0x0, TDFAR);
192 sh_eth_write(ndev, 0x0, TDFXR);
193 sh_eth_write(ndev, 0x0, TDFFR);
194 sh_eth_write(ndev, 0x0, RDLAR);
195 sh_eth_write(ndev, 0x0, RDFAR);
196 sh_eth_write(ndev, 0x0, RDFXR);
197 sh_eth_write(ndev, 0x0, RDFFR);
198 } else {
199 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
200 EDMR);
201 mdelay(3);
202 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
203 EDMR);
204 }
205}
206
207static void sh_eth_set_duplex_giga(struct net_device *ndev)
208{
209 struct sh_eth_private *mdp = netdev_priv(ndev);
210
211 if (mdp->duplex) /* Full */
212 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
213 else /* Half */
214 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
215}
216
217static void sh_eth_set_rate_giga(struct net_device *ndev)
218{
219 struct sh_eth_private *mdp = netdev_priv(ndev);
220
221 switch (mdp->speed) {
222 case 10: /* 10BASE */
223 sh_eth_write(ndev, 0x00000000, GECMR);
224 break;
225 case 100:/* 100BASE */
226 sh_eth_write(ndev, 0x00000010, GECMR);
227 break;
228 case 1000: /* 1000BASE */
229 sh_eth_write(ndev, 0x00000020, GECMR);
230 break;
231 default:
232 break;
233 }
234}
235
236/* SH7757(GETHERC) */
237static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
238 .chip_reset = sh_eth_chip_reset_giga,
239 .set_duplex = sh_eth_set_duplex_giga,
240 .set_rate = sh_eth_set_rate_giga,
241
242 .ecsr_value = ECSR_ICD | ECSR_MPD,
243 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
244 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
245
246 .tx_check = EESR_TC1 | EESR_FTC,
247 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
248 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
249 EESR_ECI,
250 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
251 EESR_TFE,
252 .fdr_value = 0x0000072f,
253 .rmcr_value = 0x00000001,
254
255 .apr = 1,
256 .mpr = 1,
257 .tpauser = 1,
258 .bculr = 1,
259 .hw_swap = 1,
260 .rpadir = 1,
261 .rpadir_value = 2 << 16,
262 .no_trimd = 1,
263 .no_ade = 1,
264};
265
266static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
267{
268 if (sh_eth_is_gether(mdp))
269 return &sh_eth_my_cpu_data_giga;
270 else
271 return &sh_eth_my_cpu_data;
272}
273
65ac8851 274#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
380af9e3
YS		 275#define SH_ETH_HAS_TSU 1
276static void sh_eth_chip_reset(struct net_device *ndev)
277{
4986b996
YS		 278 struct sh_eth_private *mdp = netdev_priv(ndev);
279
380af9e3 280 /* reset device */
4986b996 281 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 282 mdelay(1);
283}
284
285static void sh_eth_reset(struct net_device *ndev)
286{
380af9e3
YS		 287 int cnt = 100;
288
4a55530f 289 sh_eth_write(ndev, EDSR_ENALL, EDSR);
c5ed5368 290 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
380af9e3 291 while (cnt > 0) {
4a55530f 292 if (!(sh_eth_read(ndev, EDMR) & 0x3))
380af9e3
YS		 293 break;
294 mdelay(1);
295 cnt--;
296 }
890c8c18 297 if (cnt == 0)
380af9e3
YS		 298 printk(KERN_ERR "Device reset fail\n");
299
300 /* Table Init */
4a55530f
YS		 301 sh_eth_write(ndev, 0x0, TDLAR);
302 sh_eth_write(ndev, 0x0, TDFAR);
303 sh_eth_write(ndev, 0x0, TDFXR);
304 sh_eth_write(ndev, 0x0, TDFFR);
305 sh_eth_write(ndev, 0x0, RDLAR);
306 sh_eth_write(ndev, 0x0, RDFAR);
307 sh_eth_write(ndev, 0x0, RDFXR);
308 sh_eth_write(ndev, 0x0, RDFFR);
380af9e3
YS		 309}
310
311static void sh_eth_set_duplex(struct net_device *ndev)
312{
313 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 314
315 if (mdp->duplex) /* Full */
4a55530f 316 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
380af9e3 317 else /* Half */
4a55530f 318 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
380af9e3
YS		 319}
320
321static void sh_eth_set_rate(struct net_device *ndev)
322{
323 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 324
325 switch (mdp->speed) {
326 case 10: /* 10BASE */
4a55530f 327 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 328 break;
329 case 100:/* 100BASE */
4a55530f 330 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 331 break;
332 case 1000: /* 1000BASE */
4a55530f 333 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 334 break;
335 default:
336 break;
337 }
338}
339
340/* sh7763 */
341static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
342 .chip_reset = sh_eth_chip_reset,
343 .set_duplex = sh_eth_set_duplex,
344 .set_rate = sh_eth_set_rate,
345
346 .ecsr_value = ECSR_ICD | ECSR_MPD,
347 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
348 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
349
350 .tx_check = EESR_TC1 | EESR_FTC,
351 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
352 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
353 EESR_ECI,
354 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
355 EESR_TFE,
356
357 .apr = 1,
358 .mpr = 1,
359 .tpauser = 1,
360 .bculr = 1,
361 .hw_swap = 1,
380af9e3
YS		 362 .no_trimd = 1,
363 .no_ade = 1,
4986b996 364 .tsu = 1,
380af9e3
YS		 365};
366
367#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
368#define SH_ETH_RESET_DEFAULT 1
369static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
370 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
371
372 .apr = 1,
373 .mpr = 1,
374 .tpauser = 1,
375 .hw_swap = 1,
376};
377#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
378#define SH_ETH_RESET_DEFAULT 1
379#define SH_ETH_HAS_TSU 1
380static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
381 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 382 .tsu = 1,
380af9e3
YS		 383};
384#endif
385
386static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
387{
388 if (!cd->ecsr_value)
389 cd->ecsr_value = DEFAULT_ECSR_INIT;
390
391 if (!cd->ecsipr_value)
392 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
393
394 if (!cd->fcftr_value)
395 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
396 DEFAULT_FIFO_F_D_RFD;
397
398 if (!cd->fdr_value)
399 cd->fdr_value = DEFAULT_FDR_INIT;
400
401 if (!cd->rmcr_value)
402 cd->rmcr_value = DEFAULT_RMCR_VALUE;
403
404 if (!cd->tx_check)
405 cd->tx_check = DEFAULT_TX_CHECK;
406
407 if (!cd->eesr_err_check)
408 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
409
410 if (!cd->tx_error_check)
411 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
412}
413
414#if defined(SH_ETH_RESET_DEFAULT)
415/* Chip Reset */
416static void sh_eth_reset(struct net_device *ndev)
417{
c5ed5368 418 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
380af9e3 419 mdelay(3);
c5ed5368 420 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
380af9e3
YS		 421}
422#endif
423
424#if defined(CONFIG_CPU_SH4)
425static void sh_eth_set_receive_align(struct sk_buff *skb)
426{
427 int reserve;
428
429 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
430 if (reserve)
431 skb_reserve(skb, reserve);
432}
433#else
434static void sh_eth_set_receive_align(struct sk_buff *skb)
435{
436 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
437}
438#endif
439
440
71557a37
YS		 441/* CPU <-> EDMAC endian convert */
442static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
443{
444 switch (mdp->edmac_endian) {
445 case EDMAC_LITTLE_ENDIAN:
446 return cpu_to_le32(x);
447 case EDMAC_BIG_ENDIAN:
448 return cpu_to_be32(x);
449 }
450 return x;
451}
452
453static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
454{
455 switch (mdp->edmac_endian) {
456 case EDMAC_LITTLE_ENDIAN:
457 return le32_to_cpu(x);
458 case EDMAC_BIG_ENDIAN:
459 return be32_to_cpu(x);
460 }
461 return x;
462}
463
86a74ff2
NI		 464/*
465 * Program the hardware MAC address from dev->dev_addr.
466 */
467static void update_mac_address(struct net_device *ndev)
468{
4a55530f
YS		 469 sh_eth_write(ndev,
470 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
471 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
472 sh_eth_write(ndev,
473 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 474}
475
476/*
477 * Get MAC address from SuperH MAC address register
478 *
479 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
480 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
481 * When you want use this device, you must set MAC address in bootloader.
482 *
483 */
748031f9 484static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 485{
748031f9
MD		 486 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
487 memcpy(ndev->dev_addr, mac, 6);
488 } else {
4a55530f
YS		 489 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
490 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
491 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
492 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
493 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
494 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 495 }
86a74ff2
NI		 496}
497
c5ed5368
YS		 498static int sh_eth_is_gether(struct sh_eth_private *mdp)
499{
500 if (mdp->reg_offset == sh_eth_offset_gigabit)
501 return 1;
502 else
503 return 0;
504}
505
506static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
507{
508 if (sh_eth_is_gether(mdp))
509 return EDTRR_TRNS_GETHER;
510 else
511 return EDTRR_TRNS_ETHER;
512}
513
86a74ff2
NI		 514struct bb_info {
515 struct mdiobb_ctrl ctrl;
516 u32 addr;
517 u32 mmd_msk;/* MMD */
518 u32 mdo_msk;
519 u32 mdi_msk;
520 u32 mdc_msk;
521};
522
523/* PHY bit set */
524static void bb_set(u32 addr, u32 msk)
525{
900fcf09 526 writel(readl(addr) | msk, addr);
86a74ff2
NI		 527}
528
529/* PHY bit clear */
530static void bb_clr(u32 addr, u32 msk)
531{
900fcf09 532 writel((readl(addr) & ~msk), addr);
86a74ff2
NI		 533}
534
535/* PHY bit read */
536static int bb_read(u32 addr, u32 msk)
537{
900fcf09 538 return (readl(addr) & msk) != 0;
86a74ff2
NI		 539}
540
541/* Data I/O pin control */
542static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
543{
544 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
545 if (bit)
546 bb_set(bitbang->addr, bitbang->mmd_msk);
547 else
548 bb_clr(bitbang->addr, bitbang->mmd_msk);
549}
550
551/* Set bit data*/
552static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
553{
554 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
555
556 if (bit)
557 bb_set(bitbang->addr, bitbang->mdo_msk);
558 else
559 bb_clr(bitbang->addr, bitbang->mdo_msk);
560}
561
562/* Get bit data*/
563static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
564{
565 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
566 return bb_read(bitbang->addr, bitbang->mdi_msk);
567}
568
569/* MDC pin control */
570static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
571{
572 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
573
574 if (bit)
575 bb_set(bitbang->addr, bitbang->mdc_msk);
576 else
577 bb_clr(bitbang->addr, bitbang->mdc_msk);
578}
579
580/* mdio bus control struct */
581static struct mdiobb_ops bb_ops = {
582 .owner = THIS_MODULE,
583 .set_mdc = sh_mdc_ctrl,
584 .set_mdio_dir = sh_mmd_ctrl,
585 .set_mdio_data = sh_set_mdio,
586 .get_mdio_data = sh_get_mdio,
587};
588
86a74ff2
NI		 589/* free skb and descriptor buffer */
590static void sh_eth_ring_free(struct net_device *ndev)
591{
592 struct sh_eth_private *mdp = netdev_priv(ndev);
593 int i;
594
595 /* Free Rx skb ringbuffer */
596 if (mdp->rx_skbuff) {
597 for (i = 0; i < RX_RING_SIZE; i++) {
598 if (mdp->rx_skbuff[i])
599 dev_kfree_skb(mdp->rx_skbuff[i]);
600 }
601 }
602 kfree(mdp->rx_skbuff);
603
604 /* Free Tx skb ringbuffer */
605 if (mdp->tx_skbuff) {
606 for (i = 0; i < TX_RING_SIZE; i++) {
607 if (mdp->tx_skbuff[i])
608 dev_kfree_skb(mdp->tx_skbuff[i]);
609 }
610 }
611 kfree(mdp->tx_skbuff);
612}
613
614/* format skb and descriptor buffer */
615static void sh_eth_ring_format(struct net_device *ndev)
616{
617 struct sh_eth_private *mdp = netdev_priv(ndev);
618 int i;
619 struct sk_buff *skb;
620 struct sh_eth_rxdesc *rxdesc = NULL;
621 struct sh_eth_txdesc *txdesc = NULL;
622 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
623 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
624
625 mdp->cur_rx = mdp->cur_tx = 0;
626 mdp->dirty_rx = mdp->dirty_tx = 0;
627
628 memset(mdp->rx_ring, 0, rx_ringsize);
629
630 /* build Rx ring buffer */
631 for (i = 0; i < RX_RING_SIZE; i++) {
632 /* skb */
633 mdp->rx_skbuff[i] = NULL;
634 skb = dev_alloc_skb(mdp->rx_buf_sz);
635 mdp->rx_skbuff[i] = skb;
636 if (skb == NULL)
637 break;
e88aae7b
YS		 638 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
639 DMA_FROM_DEVICE);
b0ca2a21 640 skb->dev = ndev; /* Mark as being used by this device. */
380af9e3
YS		 641 sh_eth_set_receive_align(skb);
642
86a74ff2
NI		 643 /* RX descriptor */
644 rxdesc = &mdp->rx_ring[i];
0029d64a 645 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 646 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 647
648 /* The size of the buffer is 16 byte boundary. */
0029d64a 649 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 650 /* Rx descriptor address set */
651 if (i == 0) {
4a55530f 652 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 653 if (sh_eth_is_gether(mdp))
654 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 655 }
86a74ff2
NI		 656 }
657
658 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
659
660 /* Mark the last entry as wrapping the ring. */
71557a37 661 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 662
663 memset(mdp->tx_ring, 0, tx_ringsize);
664
665 /* build Tx ring buffer */
666 for (i = 0; i < TX_RING_SIZE; i++) {
667 mdp->tx_skbuff[i] = NULL;
668 txdesc = &mdp->tx_ring[i];
71557a37 669 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 670 txdesc->buffer_length = 0;
b0ca2a21 671 if (i == 0) {
71557a37 672 /* Tx descriptor address set */
4a55530f 673 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 674 if (sh_eth_is_gether(mdp))
675 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 676 }
86a74ff2
NI		 677 }
678
71557a37 679 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 680}
681
682/* Get skb and descriptor buffer */
683static int sh_eth_ring_init(struct net_device *ndev)
684{
685 struct sh_eth_private *mdp = netdev_priv(ndev);
686 int rx_ringsize, tx_ringsize, ret = 0;
687
688 /*
689 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
690 * card needs room to do 8 byte alignment, +2 so we can reserve
691 * the first 2 bytes, and +16 gets room for the status word from the
692 * card.
693 */
694 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
695 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 696 if (mdp->cd->rpadir)
697 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 698
699 /* Allocate RX and TX skb rings */
700 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
701 GFP_KERNEL);
702 if (!mdp->rx_skbuff) {
380af9e3 703 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
86a74ff2
NI		 704 ret = -ENOMEM;
705 return ret;
706 }
707
708 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
709 GFP_KERNEL);
710 if (!mdp->tx_skbuff) {
380af9e3 711 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
86a74ff2
NI		 712 ret = -ENOMEM;
713 goto skb_ring_free;
714 }
715
716 /* Allocate all Rx descriptors. */
717 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
718 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
719 GFP_KERNEL);
720
721 if (!mdp->rx_ring) {
380af9e3
YS		 722 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
723 rx_ringsize);
86a74ff2
NI		 724 ret = -ENOMEM;
725 goto desc_ring_free;
726 }
727
728 mdp->dirty_rx = 0;
729
730 /* Allocate all Tx descriptors. */
731 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
732 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
733 GFP_KERNEL);
734 if (!mdp->tx_ring) {
380af9e3
YS		 735 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
736 tx_ringsize);
86a74ff2
NI		 737 ret = -ENOMEM;
738 goto desc_ring_free;
739 }
740 return ret;
741
742desc_ring_free:
743 /* free DMA buffer */
744 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
745
746skb_ring_free:
747 /* Free Rx and Tx skb ring buffer */
748 sh_eth_ring_free(ndev);
749
750 return ret;
751}
752
753static int sh_eth_dev_init(struct net_device *ndev)
754{
755 int ret = 0;
756 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 757 u_int32_t rx_int_var, tx_int_var;
758 u32 val;
759
760 /* Soft Reset */
761 sh_eth_reset(ndev);
762
b0ca2a21
NI		 763 /* Descriptor format */
764 sh_eth_ring_format(ndev);
380af9e3 765 if (mdp->cd->rpadir)
4a55530f 766 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 767
768 /* all sh_eth int mask */
4a55530f 769 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 770
380af9e3
YS		 771#if defined(__LITTLE_ENDIAN__)
772 if (mdp->cd->hw_swap)
4a55530f 773 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 774 else
b0ca2a21 775#endif
4a55530f 776 sh_eth_write(ndev, 0, EDMR);
86a74ff2 777
b0ca2a21 778 /* FIFO size set */
4a55530f
YS		 779 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
780 sh_eth_write(ndev, 0, TFTR);
86a74ff2 781
b0ca2a21 782 /* Frame recv control */
4a55530f 783 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2
NI		 784
785 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
786 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
4a55530f 787 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
86a74ff2 788
380af9e3 789 if (mdp->cd->bculr)
4a55530f 790 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 791
4a55530f 792 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 793
380af9e3 794 if (!mdp->cd->no_trimd)
4a55530f 795 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 796
b0ca2a21 797 /* Recv frame limit set register */
4a55530f 798 sh_eth_write(ndev, RFLR_VALUE, RFLR);
86a74ff2 799
4a55530f
YS		 800 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
801 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 802
803 /* PAUSE Prohibition */
4a55530f 804 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 805 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
806
4a55530f 807 sh_eth_write(ndev, val, ECMR);
b0ca2a21 808
380af9e3
YS		 809 if (mdp->cd->set_rate)
810 mdp->cd->set_rate(ndev);
811
b0ca2a21 812 /* E-MAC Status Register clear */
4a55530f 813 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 814
815 /* E-MAC Interrupt Enable register */
4a55530f 816 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 817
818 /* Set MAC address */
819 update_mac_address(ndev);
820
821 /* mask reset */
380af9e3 822 if (mdp->cd->apr)
4a55530f 823 sh_eth_write(ndev, APR_AP, APR);
380af9e3 824 if (mdp->cd->mpr)
4a55530f 825 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 826 if (mdp->cd->tpauser)
4a55530f 827 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 828
86a74ff2 829 /* Setting the Rx mode will start the Rx process. */
4a55530f 830 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 831
832 netif_start_queue(ndev);
833
834 return ret;
835}
836
837/* free Tx skb function */
838static int sh_eth_txfree(struct net_device *ndev)
839{
840 struct sh_eth_private *mdp = netdev_priv(ndev);
841 struct sh_eth_txdesc *txdesc;
842 int freeNum = 0;
843 int entry = 0;
844
845 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
846 entry = mdp->dirty_tx % TX_RING_SIZE;
847 txdesc = &mdp->tx_ring[entry];
71557a37 848 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 849 break;
850 /* Free the original skb. */
851 if (mdp->tx_skbuff[entry]) {
852 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
853 mdp->tx_skbuff[entry] = NULL;
854 freeNum++;
855 }
71557a37 856 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 857 if (entry >= TX_RING_SIZE - 1)
71557a37 858 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 859
860 mdp->stats.tx_packets++;
861 mdp->stats.tx_bytes += txdesc->buffer_length;
862 }
863 return freeNum;
864}
865
866/* Packet receive function */
867static int sh_eth_rx(struct net_device *ndev)
868{
869 struct sh_eth_private *mdp = netdev_priv(ndev);
870 struct sh_eth_rxdesc *rxdesc;
871
872 int entry = mdp->cur_rx % RX_RING_SIZE;
873 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
874 struct sk_buff *skb;
875 u16 pkt_len = 0;
380af9e3 876 u32 desc_status;
86a74ff2
NI		 877
878 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 879 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
880 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 881 pkt_len = rxdesc->frame_length;
882
883 if (--boguscnt < 0)
884 break;
885
886 if (!(desc_status & RDFEND))
887 mdp->stats.rx_length_errors++;
888
889 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
890 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
891 mdp->stats.rx_errors++;
892 if (desc_status & RD_RFS1)
893 mdp->stats.rx_crc_errors++;
894 if (desc_status & RD_RFS2)
895 mdp->stats.rx_frame_errors++;
896 if (desc_status & RD_RFS3)
897 mdp->stats.rx_length_errors++;
898 if (desc_status & RD_RFS4)
899 mdp->stats.rx_length_errors++;
900 if (desc_status & RD_RFS6)
901 mdp->stats.rx_missed_errors++;
902 if (desc_status & RD_RFS10)
903 mdp->stats.rx_over_errors++;
904 } else {
380af9e3
YS		 905 if (!mdp->cd->hw_swap)
906 sh_eth_soft_swap(
907 phys_to_virt(ALIGN(rxdesc->addr, 4)),
908 pkt_len + 2);
86a74ff2
NI		 909 skb = mdp->rx_skbuff[entry];
910 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 911 if (mdp->cd->rpadir)
912 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 913 skb_put(skb, pkt_len);
914 skb->protocol = eth_type_trans(skb, ndev);
915 netif_rx(skb);
86a74ff2
NI		 916 mdp->stats.rx_packets++;
917 mdp->stats.rx_bytes += pkt_len;
918 }
71557a37 919 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
86a74ff2 920 entry = (++mdp->cur_rx) % RX_RING_SIZE;
862df497 921 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 922 }
923
924 /* Refill the Rx ring buffers. */
925 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
926 entry = mdp->dirty_rx % RX_RING_SIZE;
927 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 928 /* The size of the buffer is 16 byte boundary. */
0029d64a 929 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 930
86a74ff2
NI		 931 if (mdp->rx_skbuff[entry] == NULL) {
932 skb = dev_alloc_skb(mdp->rx_buf_sz);
933 mdp->rx_skbuff[entry] = skb;
934 if (skb == NULL)
935 break; /* Better luck next round. */
e88aae7b
YS		 936 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
937 DMA_FROM_DEVICE);
86a74ff2 938 skb->dev = ndev;
380af9e3
YS		 939 sh_eth_set_receive_align(skb);
940
bc8acf2c 941 skb_checksum_none_assert(skb);
0029d64a 942 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 943 }
86a74ff2
NI		 944 if (entry >= RX_RING_SIZE - 1)
945 rxdesc->status |=
71557a37 946 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 947 else
948 rxdesc->status |=
71557a37 949 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 950 }
951
952 /* Restart Rx engine if stopped. */
953 /* If we don't need to check status, don't. -KDU */
4a55530f
YS		 954 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
955 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 956
957 return 0;
958}
959
4a55530f 960static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 961{
962 /* disable tx and rx */
4a55530f
YS		 963 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
964 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 965}
966
4a55530f 967static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 968{
969 /* enable tx and rx */
4a55530f
YS		 970 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
971 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 972}
973
86a74ff2
NI		 974/* error control function */
975static void sh_eth_error(struct net_device *ndev, int intr_status)
976{
977 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 978 u32 felic_stat;
380af9e3
YS		 979 u32 link_stat;
980 u32 mask;
86a74ff2
NI		 981
982 if (intr_status & EESR_ECI) {
4a55530f
YS		 983 felic_stat = sh_eth_read(ndev, ECSR);
984 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2
NI		 985 if (felic_stat & ECSR_ICD)
986 mdp->stats.tx_carrier_errors++;
987 if (felic_stat & ECSR_LCHNG) {
988 /* Link Changed */
4923576b 989 if (mdp->cd->no_psr || mdp->no_ether_link) {
380af9e3
YS		 990 if (mdp->link == PHY_DOWN)
991 link_stat = 0;
992 else
993 link_stat = PHY_ST_LINK;
994 } else {
4a55530f 995 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 996 if (mdp->ether_link_active_low)
997 link_stat = ~link_stat;
380af9e3 998 }
dc19e4e5 999 if (!(link_stat & PHY_ST_LINK))
4a55530f 1000 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1001 else {
86a74ff2 1002 /* Link Up */
4a55530f
YS		 1003 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1004 ~DMAC_M_ECI, EESIPR);
86a74ff2 1005 /*clear int */
4a55530f
YS		 1006 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1007 ECSR);
1008 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1009 DMAC_M_ECI, EESIPR);
86a74ff2 1010 /* enable tx and rx */
4a55530f 1011 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1012 }
1013 }
1014 }
1015
1016 if (intr_status & EESR_TWB) {
1017 /* Write buck end. unused write back interrupt */
1018 if (intr_status & EESR_TABT) /* Transmit Abort int */
1019 mdp->stats.tx_aborted_errors++;
dc19e4e5
NI		 1020 if (netif_msg_tx_err(mdp))
1021 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 1022 }
1023
1024 if (intr_status & EESR_RABT) {
1025 /* Receive Abort int */
1026 if (intr_status & EESR_RFRMER) {
1027 /* Receive Frame Overflow int */
1028 mdp->stats.rx_frame_errors++;
dc19e4e5
NI		 1029 if (netif_msg_rx_err(mdp))
1030 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1031 }
1032 }
380af9e3 1033
dc19e4e5
NI		 1034 if (intr_status & EESR_TDE) {
1035 /* Transmit Descriptor Empty int */
1036 mdp->stats.tx_fifo_errors++;
1037 if (netif_msg_tx_err(mdp))
1038 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1039 }
1040
1041 if (intr_status & EESR_TFE) {
1042 /* FIFO under flow */
1043 mdp->stats.tx_fifo_errors++;
1044 if (netif_msg_tx_err(mdp))
1045 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1046 }
1047
1048 if (intr_status & EESR_RDE) {
1049 /* Receive Descriptor Empty int */
1050 mdp->stats.rx_over_errors++;
1051
4a55530f
YS		 1052 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
1053 sh_eth_write(ndev, EDRRR_R, EDRRR);
dc19e4e5
NI		 1054 if (netif_msg_rx_err(mdp))
1055 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1056 }
dc19e4e5 1057
86a74ff2
NI		 1058 if (intr_status & EESR_RFE) {
1059 /* Receive FIFO Overflow int */
1060 mdp->stats.rx_fifo_errors++;
dc19e4e5
NI		 1061 if (netif_msg_rx_err(mdp))
1062 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1063 }
1064
1065 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1066 /* Address Error */
1067 mdp->stats.tx_fifo_errors++;
1068 if (netif_msg_tx_err(mdp))
1069 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1070 }
380af9e3
YS		 1071
1072 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1073 if (mdp->cd->no_ade)
1074 mask &= ~EESR_ADE;
1075 if (intr_status & mask) {
86a74ff2 1076 /* Tx error */
4a55530f 1077 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1078 /* dmesg */
380af9e3
YS		 1079 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1080 intr_status, mdp->cur_tx);
1081 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1082 mdp->dirty_tx, (u32) ndev->state, edtrr);
1083 /* dirty buffer free */
1084 sh_eth_txfree(ndev);
1085
1086 /* SH7712 BUG */
c5ed5368 1087 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1088 /* tx dma start */
c5ed5368 1089 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1090 }
1091 /* wakeup */
1092 netif_wake_queue(ndev);
1093 }
1094}
1095
1096static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1097{
1098 struct net_device *ndev = netdev;
1099 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1100 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1101 irqreturn_t ret = IRQ_NONE;
4a55530f 1102 u32 intr_status = 0;
86a74ff2 1103
86a74ff2
NI		 1104 spin_lock(&mdp->lock);
1105
b0ca2a21 1106 /* Get interrpt stat */
4a55530f 1107 intr_status = sh_eth_read(ndev, EESR);
86a74ff2 1108 /* Clear interrupt */
0e0fde3c
NI		 1109 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1110 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 1111 cd->tx_check | cd->eesr_err_check)) {
4a55530f 1112 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 1113 ret = IRQ_HANDLED;
1114 } else
1115 goto other_irq;
86a74ff2 1116
b0ca2a21
NI		 1117 if (intr_status & (EESR_FRC | /* Frame recv*/
1118 EESR_RMAF | /* Multi cast address recv*/
1119 EESR_RRF | /* Bit frame recv */
1120 EESR_RTLF | /* Long frame recv*/
1121 EESR_RTSF | /* short frame recv */
1122 EESR_PRE | /* PHY-LSI recv error */
1123 EESR_CERF)){ /* recv frame CRC error */
86a74ff2 1124 sh_eth_rx(ndev);
b0ca2a21 1125 }
86a74ff2 1126
b0ca2a21 1127 /* Tx Check */
380af9e3 1128 if (intr_status & cd->tx_check) {
86a74ff2
NI		 1129 sh_eth_txfree(ndev);
1130 netif_wake_queue(ndev);
1131 }
1132
380af9e3 1133 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 1134 sh_eth_error(ndev, intr_status);
1135
0e0fde3c 1136other_irq:
86a74ff2
NI		 1137 spin_unlock(&mdp->lock);
1138
0e0fde3c 1139 return ret;
86a74ff2
NI		 1140}
1141
1142static void sh_eth_timer(unsigned long data)
1143{
1144 struct net_device *ndev = (struct net_device *)data;
1145 struct sh_eth_private *mdp = netdev_priv(ndev);
1146
1147 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1148}
1149
1150/* PHY state control function */
1151static void sh_eth_adjust_link(struct net_device *ndev)
1152{
1153 struct sh_eth_private *mdp = netdev_priv(ndev);
1154 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1155 int new_state = 0;
1156
1157 if (phydev->link != PHY_DOWN) {
1158 if (phydev->duplex != mdp->duplex) {
1159 new_state = 1;
1160 mdp->duplex = phydev->duplex;
380af9e3
YS		 1161 if (mdp->cd->set_duplex)
1162 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1163 }
1164
1165 if (phydev->speed != mdp->speed) {
1166 new_state = 1;
1167 mdp->speed = phydev->speed;
380af9e3
YS		 1168 if (mdp->cd->set_rate)
1169 mdp->cd->set_rate(ndev);
86a74ff2
NI		 1170 }
1171 if (mdp->link == PHY_DOWN) {
4a55530f
YS		 1172 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF)
1173 | ECMR_DM, ECMR);
86a74ff2
NI		 1174 new_state = 1;
1175 mdp->link = phydev->link;
86a74ff2
NI		 1176 }
1177 } else if (mdp->link) {
1178 new_state = 1;
1179 mdp->link = PHY_DOWN;
1180 mdp->speed = 0;
1181 mdp->duplex = -1;
86a74ff2
NI		 1182 }
1183
dc19e4e5 1184 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1185 phy_print_status(phydev);
1186}
1187
1188/* PHY init function */
1189static int sh_eth_phy_init(struct net_device *ndev)
1190{
1191 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1192 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1193 struct phy_device *phydev = NULL;
1194
fb28ad35 1195 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1196 mdp->mii_bus->id , mdp->phy_id);
1197
1198 mdp->link = PHY_DOWN;
1199 mdp->speed = 0;
1200 mdp->duplex = -1;
1201
1202 /* Try connect to PHY */
c061b18d 1203 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
e47c9052 1204 0, mdp->phy_interface);
86a74ff2
NI		 1205 if (IS_ERR(phydev)) {
1206 dev_err(&ndev->dev, "phy_connect failed\n");
1207 return PTR_ERR(phydev);
1208 }
380af9e3 1209
86a74ff2 1210 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1211 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1212
1213 mdp->phydev = phydev;
1214
1215 return 0;
1216}
1217
1218/* PHY control start function */
1219static int sh_eth_phy_start(struct net_device *ndev)
1220{
1221 struct sh_eth_private *mdp = netdev_priv(ndev);
1222 int ret;
1223
1224 ret = sh_eth_phy_init(ndev);
1225 if (ret)
1226 return ret;
1227
1228 /* reset phy - this also wakes it from PDOWN */
1229 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1230 phy_start(mdp->phydev);
1231
1232 return 0;
1233}
1234
dc19e4e5
NI		 1235static int sh_eth_get_settings(struct net_device *ndev,
1236 struct ethtool_cmd *ecmd)
1237{
1238 struct sh_eth_private *mdp = netdev_priv(ndev);
1239 unsigned long flags;
1240 int ret;
1241
1242 spin_lock_irqsave(&mdp->lock, flags);
1243 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1244 spin_unlock_irqrestore(&mdp->lock, flags);
1245
1246 return ret;
1247}
1248
1249static int sh_eth_set_settings(struct net_device *ndev,
1250 struct ethtool_cmd *ecmd)
1251{
1252 struct sh_eth_private *mdp = netdev_priv(ndev);
1253 unsigned long flags;
1254 int ret;
dc19e4e5
NI		 1255
1256 spin_lock_irqsave(&mdp->lock, flags);
1257
1258 /* disable tx and rx */
4a55530f 1259 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1260
1261 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1262 if (ret)
1263 goto error_exit;
1264
1265 if (ecmd->duplex == DUPLEX_FULL)
1266 mdp->duplex = 1;
1267 else
1268 mdp->duplex = 0;
1269
1270 if (mdp->cd->set_duplex)
1271 mdp->cd->set_duplex(ndev);
1272
1273error_exit:
1274 mdelay(1);
1275
1276 /* enable tx and rx */
4a55530f 1277 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1278
1279 spin_unlock_irqrestore(&mdp->lock, flags);
1280
1281 return ret;
1282}
1283
1284static int sh_eth_nway_reset(struct net_device *ndev)
1285{
1286 struct sh_eth_private *mdp = netdev_priv(ndev);
1287 unsigned long flags;
1288 int ret;
1289
1290 spin_lock_irqsave(&mdp->lock, flags);
1291 ret = phy_start_aneg(mdp->phydev);
1292 spin_unlock_irqrestore(&mdp->lock, flags);
1293
1294 return ret;
1295}
1296
1297static u32 sh_eth_get_msglevel(struct net_device *ndev)
1298{
1299 struct sh_eth_private *mdp = netdev_priv(ndev);
1300 return mdp->msg_enable;
1301}
1302
1303static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1304{
1305 struct sh_eth_private *mdp = netdev_priv(ndev);
1306 mdp->msg_enable = value;
1307}
1308
1309static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1310 "rx_current", "tx_current",
1311 "rx_dirty", "tx_dirty",
1312};
1313#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1314
1315static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1316{
1317 switch (sset) {
1318 case ETH_SS_STATS:
1319 return SH_ETH_STATS_LEN;
1320 default:
1321 return -EOPNOTSUPP;
1322 }
1323}
1324
1325static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1326 struct ethtool_stats *stats, u64 *data)
1327{
1328 struct sh_eth_private *mdp = netdev_priv(ndev);
1329 int i = 0;
1330
1331 /* device-specific stats */
1332 data[i++] = mdp->cur_rx;
1333 data[i++] = mdp->cur_tx;
1334 data[i++] = mdp->dirty_rx;
1335 data[i++] = mdp->dirty_tx;
1336}
1337
1338static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1339{
1340 switch (stringset) {
1341 case ETH_SS_STATS:
1342 memcpy(data, *sh_eth_gstrings_stats,
1343 sizeof(sh_eth_gstrings_stats));
1344 break;
1345 }
1346}
1347
1348static struct ethtool_ops sh_eth_ethtool_ops = {
1349 .get_settings = sh_eth_get_settings,
1350 .set_settings = sh_eth_set_settings,
1351 .nway_reset = sh_eth_nway_reset,
1352 .get_msglevel = sh_eth_get_msglevel,
1353 .set_msglevel = sh_eth_set_msglevel,
1354 .get_link = ethtool_op_get_link,
1355 .get_strings = sh_eth_get_strings,
1356 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1357 .get_sset_count = sh_eth_get_sset_count,
1358};
1359
86a74ff2
NI		 1360/* network device open function */
1361static int sh_eth_open(struct net_device *ndev)
1362{
1363 int ret = 0;
1364 struct sh_eth_private *mdp = netdev_priv(ndev);
1365
bcd5149d
MD		 1366 pm_runtime_get_sync(&mdp->pdev->dev);
1367
a0607fd3 1368 ret = request_irq(ndev->irq, sh_eth_interrupt,
f29a3d04 1369#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
dc19e4e5
NI		 1370 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1371 defined(CONFIG_CPU_SUBTYPE_SH7757)
0e0fde3c
NI		 1372 IRQF_SHARED,
1373#else
1374 0,
1375#endif
1376 ndev->name, ndev);
86a74ff2 1377 if (ret) {
380af9e3 1378 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1379 return ret;
1380 }
1381
1382 /* Descriptor set */
1383 ret = sh_eth_ring_init(ndev);
1384 if (ret)
1385 goto out_free_irq;
1386
1387 /* device init */
1388 ret = sh_eth_dev_init(ndev);
1389 if (ret)
1390 goto out_free_irq;
1391
1392 /* PHY control start*/
1393 ret = sh_eth_phy_start(ndev);
1394 if (ret)
1395 goto out_free_irq;
1396
1397 /* Set the timer to check for link beat. */
1398 init_timer(&mdp->timer);
1399 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
b0ca2a21 1400 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
86a74ff2
NI		 1401
1402 return ret;
1403
1404out_free_irq:
1405 free_irq(ndev->irq, ndev);
bcd5149d 1406 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1407 return ret;
1408}
1409
1410/* Timeout function */
1411static void sh_eth_tx_timeout(struct net_device *ndev)
1412{
1413 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1414 struct sh_eth_rxdesc *rxdesc;
1415 int i;
1416
1417 netif_stop_queue(ndev);
1418
dc19e4e5
NI		 1419 if (netif_msg_timer(mdp))
1420 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1421 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1422
1423 /* tx_errors count up */
1424 mdp->stats.tx_errors++;
1425
1426 /* timer off */
1427 del_timer_sync(&mdp->timer);
1428
1429 /* Free all the skbuffs in the Rx queue. */
1430 for (i = 0; i < RX_RING_SIZE; i++) {
1431 rxdesc = &mdp->rx_ring[i];
1432 rxdesc->status = 0;
1433 rxdesc->addr = 0xBADF00D0;
1434 if (mdp->rx_skbuff[i])
1435 dev_kfree_skb(mdp->rx_skbuff[i]);
1436 mdp->rx_skbuff[i] = NULL;
1437 }
1438 for (i = 0; i < TX_RING_SIZE; i++) {
1439 if (mdp->tx_skbuff[i])
1440 dev_kfree_skb(mdp->tx_skbuff[i]);
1441 mdp->tx_skbuff[i] = NULL;
1442 }
1443
1444 /* device init */
1445 sh_eth_dev_init(ndev);
1446
1447 /* timer on */
1448 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1449 add_timer(&mdp->timer);
1450}
1451
1452/* Packet transmit function */
1453static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1454{
1455 struct sh_eth_private *mdp = netdev_priv(ndev);
1456 struct sh_eth_txdesc *txdesc;
1457 u32 entry;
fb5e2f9b 1458 unsigned long flags;
86a74ff2
NI		 1459
1460 spin_lock_irqsave(&mdp->lock, flags);
1461 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1462 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1463 if (netif_msg_tx_queued(mdp))
1464 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1465 netif_stop_queue(ndev);
1466 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1467 return NETDEV_TX_BUSY;
86a74ff2
NI		 1468 }
1469 }
1470 spin_unlock_irqrestore(&mdp->lock, flags);
1471
1472 entry = mdp->cur_tx % TX_RING_SIZE;
1473 mdp->tx_skbuff[entry] = skb;
1474 txdesc = &mdp->tx_ring[entry];
0029d64a 1475 txdesc->addr = virt_to_phys(skb->data);
86a74ff2 1476 /* soft swap. */
380af9e3
YS		 1477 if (!mdp->cd->hw_swap)
1478 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1479 skb->len + 2);
86a74ff2
NI		 1480 /* write back */
1481 __flush_purge_region(skb->data, skb->len);
1482 if (skb->len < ETHERSMALL)
1483 txdesc->buffer_length = ETHERSMALL;
1484 else
1485 txdesc->buffer_length = skb->len;
1486
1487 if (entry >= TX_RING_SIZE - 1)
71557a37 1488 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1489 else
71557a37 1490 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1491
1492 mdp->cur_tx++;
1493
c5ed5368
YS		 1494 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1495 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 1496
6ed10654 1497 return NETDEV_TX_OK;
86a74ff2
NI		 1498}
1499
1500/* device close function */
1501static int sh_eth_close(struct net_device *ndev)
1502{
1503 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1504 int ringsize;
1505
1506 netif_stop_queue(ndev);
1507
1508 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 1509 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 1510
1511 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 1512 sh_eth_write(ndev, 0, EDTRR);
1513 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 1514
1515 /* PHY Disconnect */
1516 if (mdp->phydev) {
1517 phy_stop(mdp->phydev);
1518 phy_disconnect(mdp->phydev);
1519 }
1520
1521 free_irq(ndev->irq, ndev);
1522
1523 del_timer_sync(&mdp->timer);
1524
1525 /* Free all the skbuffs in the Rx queue. */
1526 sh_eth_ring_free(ndev);
1527
1528 /* free DMA buffer */
1529 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1530 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1531
1532 /* free DMA buffer */
1533 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1534 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1535
bcd5149d
MD		 1536 pm_runtime_put_sync(&mdp->pdev->dev);
1537
86a74ff2
NI		 1538 return 0;
1539}
1540
1541static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1542{
1543 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1544
bcd5149d
MD		 1545 pm_runtime_get_sync(&mdp->pdev->dev);
1546
4a55530f
YS		 1547 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1548 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1549 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1550 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1551 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1552 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368
YS		 1553 if (sh_eth_is_gether(mdp)) {
1554 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1555 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1556 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1557 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1558 } else {
1559 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1560 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1561 }
bcd5149d
MD		 1562 pm_runtime_put_sync(&mdp->pdev->dev);
1563
86a74ff2
NI		 1564 return &mdp->stats;
1565}
1566
1567/* ioctl to device funciotn*/
1568static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1569 int cmd)
1570{
1571 struct sh_eth_private *mdp = netdev_priv(ndev);
1572 struct phy_device *phydev = mdp->phydev;
1573
1574 if (!netif_running(ndev))
1575 return -EINVAL;
1576
1577 if (!phydev)
1578 return -ENODEV;
1579
28b04113 1580 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 1581}
1582
380af9e3 1583#if defined(SH_ETH_HAS_TSU)
86a74ff2
NI		 1584/* Multicast reception directions set */
1585static void sh_eth_set_multicast_list(struct net_device *ndev)
1586{
86a74ff2
NI		 1587 if (ndev->flags & IFF_PROMISC) {
1588 /* Set promiscuous. */
4a55530f
YS		 1589 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1590 ECMR_PRM, ECMR);
86a74ff2
NI		 1591 } else {
1592 /* Normal, unicast/broadcast-only mode. */
4a55530f
YS		 1593 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1594 ECMR_MCT, ECMR);
86a74ff2
NI		 1595 }
1596}
4986b996 1597#endif /* SH_ETH_HAS_TSU */
86a74ff2
NI		 1598
1599/* SuperH's TSU register init function */
4a55530f 1600static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 1601{
4a55530f
YS		 1602 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1603 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1604 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1605 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1606 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1607 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1608 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1609 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1610 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1611 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 1612 if (sh_eth_is_gether(mdp)) {
1613 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1614 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1615 } else {
1616 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1617 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1618 }
4a55530f
YS		 1619 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1620 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1621 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1622 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1623 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1624 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1625 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 1626}
1627
1628/* MDIO bus release function */
1629static int sh_mdio_release(struct net_device *ndev)
1630{
1631 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1632
1633 /* unregister mdio bus */
1634 mdiobus_unregister(bus);
1635
1636 /* remove mdio bus info from net_device */
1637 dev_set_drvdata(&ndev->dev, NULL);
1638
0f0b405c
DK		 1639 /* free interrupts memory */
1640 kfree(bus->irq);
1641
86a74ff2
NI		 1642 /* free bitbang info */
1643 free_mdio_bitbang(bus);
1644
1645 return 0;
1646}
1647
1648/* MDIO bus init function */
1649static int sh_mdio_init(struct net_device *ndev, int id)
1650{
1651 int ret, i;
1652 struct bb_info *bitbang;
1653 struct sh_eth_private *mdp = netdev_priv(ndev);
1654
1655 /* create bit control struct for PHY */
1656 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1657 if (!bitbang) {
1658 ret = -ENOMEM;
1659 goto out;
1660 }
1661
1662 /* bitbang init */
4a55530f 1663 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
86a74ff2
NI		 1664 bitbang->mdi_msk = 0x08;
1665 bitbang->mdo_msk = 0x04;
1666 bitbang->mmd_msk = 0x02;/* MMD */
1667 bitbang->mdc_msk = 0x01;
1668 bitbang->ctrl.ops = &bb_ops;
1669
c2e07b3a 1670 /* MII controller setting */
86a74ff2
NI		 1671 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1672 if (!mdp->mii_bus) {
1673 ret = -ENOMEM;
1674 goto out_free_bitbang;
1675 }
1676
1677 /* Hook up MII support for ethtool */
1678 mdp->mii_bus->name = "sh_mii";
18ee49dd 1679 mdp->mii_bus->parent = &ndev->dev;
fb5e2f9b 1680 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
86a74ff2
NI		 1681
1682 /* PHY IRQ */
1683 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1684 if (!mdp->mii_bus->irq) {
1685 ret = -ENOMEM;
1686 goto out_free_bus;
1687 }
1688
1689 for (i = 0; i < PHY_MAX_ADDR; i++)
1690 mdp->mii_bus->irq[i] = PHY_POLL;
1691
1692 /* regist mdio bus */
1693 ret = mdiobus_register(mdp->mii_bus);
1694 if (ret)
1695 goto out_free_irq;
1696
1697 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1698
1699 return 0;
1700
1701out_free_irq:
1702 kfree(mdp->mii_bus->irq);
1703
1704out_free_bus:
298cf9be 1705 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 1706
1707out_free_bitbang:
1708 kfree(bitbang);
1709
1710out:
1711 return ret;
1712}
1713
4a55530f
YS		 1714static const u16 *sh_eth_get_register_offset(int register_type)
1715{
1716 const u16 *reg_offset = NULL;
1717
1718 switch (register_type) {
1719 case SH_ETH_REG_GIGABIT:
1720 reg_offset = sh_eth_offset_gigabit;
1721 break;
1722 case SH_ETH_REG_FAST_SH4:
1723 reg_offset = sh_eth_offset_fast_sh4;
1724 break;
1725 case SH_ETH_REG_FAST_SH3_SH2:
1726 reg_offset = sh_eth_offset_fast_sh3_sh2;
1727 break;
1728 default:
1729 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1730 break;
1731 }
1732
1733 return reg_offset;
1734}
1735
ebf84eaa
AB		 1736static const struct net_device_ops sh_eth_netdev_ops = {
1737 .ndo_open = sh_eth_open,
1738 .ndo_stop = sh_eth_close,
1739 .ndo_start_xmit = sh_eth_start_xmit,
1740 .ndo_get_stats = sh_eth_get_stats,
380af9e3 1741#if defined(SH_ETH_HAS_TSU)
ebf84eaa 1742 .ndo_set_multicast_list = sh_eth_set_multicast_list,
380af9e3 1743#endif
ebf84eaa
AB		 1744 .ndo_tx_timeout = sh_eth_tx_timeout,
1745 .ndo_do_ioctl = sh_eth_do_ioctl,
1746 .ndo_validate_addr = eth_validate_addr,
1747 .ndo_set_mac_address = eth_mac_addr,
1748 .ndo_change_mtu = eth_change_mtu,
1749};
1750
86a74ff2
NI		 1751static int sh_eth_drv_probe(struct platform_device *pdev)
1752{
9c38657c 1753 int ret, devno = 0;
86a74ff2
NI		 1754 struct resource *res;
1755 struct net_device *ndev = NULL;
1756 struct sh_eth_private *mdp;
71557a37 1757 struct sh_eth_plat_data *pd;
86a74ff2
NI		 1758
1759 /* get base addr */
1760 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1761 if (unlikely(res == NULL)) {
1762 dev_err(&pdev->dev, "invalid resource\n");
1763 ret = -EINVAL;
1764 goto out;
1765 }
1766
1767 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1768 if (!ndev) {
380af9e3 1769 dev_err(&pdev->dev, "Could not allocate device.\n");
86a74ff2
NI		 1770 ret = -ENOMEM;
1771 goto out;
1772 }
1773
1774 /* The sh Ether-specific entries in the device structure. */
1775 ndev->base_addr = res->start;
1776 devno = pdev->id;
1777 if (devno < 0)
1778 devno = 0;
1779
1780 ndev->dma = -1;
cc3c080d 1781 ret = platform_get_irq(pdev, 0);
1782 if (ret < 0) {
86a74ff2
NI		 1783 ret = -ENODEV;
1784 goto out_release;
1785 }
cc3c080d 1786 ndev->irq = ret;
86a74ff2
NI		 1787
1788 SET_NETDEV_DEV(ndev, &pdev->dev);
1789
1790 /* Fill in the fields of the device structure with ethernet values. */
1791 ether_setup(ndev);
1792
1793 mdp = netdev_priv(ndev);
1794 spin_lock_init(&mdp->lock);
bcd5149d
MD		 1795 mdp->pdev = pdev;
1796 pm_runtime_enable(&pdev->dev);
1797 pm_runtime_resume(&pdev->dev);
86a74ff2 1798
71557a37 1799 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
86a74ff2 1800 /* get PHY ID */
71557a37 1801 mdp->phy_id = pd->phy;
e47c9052 1802 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 1803 /* EDMAC endian */
1804 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 1805 mdp->no_ether_link = pd->no_ether_link;
1806 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 1807 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 1808
380af9e3 1809 /* set cpu data */
8fcd4961
YS		 1810#if defined(SH_ETH_HAS_BOTH_MODULES)
1811 mdp->cd = sh_eth_get_cpu_data(mdp);
1812#else
380af9e3 1813 mdp->cd = &sh_eth_my_cpu_data;
8fcd4961 1814#endif
380af9e3
YS		 1815 sh_eth_set_default_cpu_data(mdp->cd);
1816
86a74ff2 1817 /* set function */
ebf84eaa 1818 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 1819 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 1820 ndev->watchdog_timeo = TX_TIMEOUT;
1821
dc19e4e5
NI		 1822 /* debug message level */
1823 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 1824 mdp->post_rx = POST_RX >> (devno << 1);
1825 mdp->post_fw = POST_FW >> (devno << 1);
1826
1827 /* read and set MAC address */
748031f9 1828 read_mac_address(ndev, pd->mac_addr);
86a74ff2
NI		 1829
1830 /* First device only init */
1831 if (!devno) {
4986b996
YS		 1832 if (mdp->cd->tsu) {
1833 struct resource *rtsu;
1834 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1835 if (!rtsu) {
1836 dev_err(&pdev->dev, "Not found TSU resource\n");
1837 goto out_release;
1838 }
1839 mdp->tsu_addr = ioremap(rtsu->start,
1840 resource_size(rtsu));
1841 }
380af9e3
YS		 1842 if (mdp->cd->chip_reset)
1843 mdp->cd->chip_reset(ndev);
86a74ff2 1844
4986b996
YS		 1845 if (mdp->cd->tsu) {
1846 /* TSU init (Init only)*/
1847 sh_eth_tsu_init(mdp);
1848 }
86a74ff2
NI		 1849 }
1850
1851 /* network device register */
1852 ret = register_netdev(ndev);
1853 if (ret)
1854 goto out_release;
1855
1856 /* mdio bus init */
1857 ret = sh_mdio_init(ndev, pdev->id);
1858 if (ret)
1859 goto out_unregister;
1860
6cd9b49d
HS		 1861 /* print device infomation */
1862 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1863 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 1864
1865 platform_set_drvdata(pdev, ndev);
1866
1867 return ret;
1868
1869out_unregister:
1870 unregister_netdev(ndev);
1871
1872out_release:
1873 /* net_dev free */
4986b996
YS		 1874 if (mdp->tsu_addr)
1875 iounmap(mdp->tsu_addr);
86a74ff2
NI		 1876 if (ndev)
1877 free_netdev(ndev);
1878
1879out:
1880 return ret;
1881}
1882
1883static int sh_eth_drv_remove(struct platform_device *pdev)
1884{
1885 struct net_device *ndev = platform_get_drvdata(pdev);
4986b996 1886 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1887
4986b996 1888 iounmap(mdp->tsu_addr);
86a74ff2
NI		 1889 sh_mdio_release(ndev);
1890 unregister_netdev(ndev);
bcd5149d 1891 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 1892 free_netdev(ndev);
1893 platform_set_drvdata(pdev, NULL);
1894
1895 return 0;
1896}
1897
bcd5149d
MD		 1898static int sh_eth_runtime_nop(struct device *dev)
1899{
1900 /*
1901 * Runtime PM callback shared between ->runtime_suspend()
1902 * and ->runtime_resume(). Simply returns success.
1903 *
1904 * This driver re-initializes all registers after
1905 * pm_runtime_get_sync() anyway so there is no need
1906 * to save and restore registers here.
1907 */
1908 return 0;
1909}
1910
1911static struct dev_pm_ops sh_eth_dev_pm_ops = {
1912 .runtime_suspend = sh_eth_runtime_nop,
1913 .runtime_resume = sh_eth_runtime_nop,
1914};
1915
86a74ff2
NI		 1916static struct platform_driver sh_eth_driver = {
1917 .probe = sh_eth_drv_probe,
1918 .remove = sh_eth_drv_remove,
1919 .driver = {
1920 .name = CARDNAME,
bcd5149d 1921 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 1922 },
1923};
1924
1925static int __init sh_eth_init(void)
1926{
1927 return platform_driver_register(&sh_eth_driver);
1928}
1929
1930static void __exit sh_eth_cleanup(void)
1931{
1932 platform_driver_unregister(&sh_eth_driver);
1933}
1934
1935module_init(sh_eth_init);
1936module_exit(sh_eth_cleanup);
1937
1938MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1939MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1940MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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