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skge: convert to hw_features
[deliverable/linux.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
f15063cd
JP		 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
678aa1f6 41#include <linux/debugfs.h>
d43c36dc 42#include <linux/sched.h>
678aa1f6 43#include <linux/seq_file.h>
2cd8e5d3 44#include <linux/mii.h>
5a0e3ad6 45#include <linux/slab.h>
392bd0cb 46#include <linux/dmi.h>
baef58b1
SH		 47#include <asm/irq.h>
48
49#include "skge.h"
50
51#define DRV_NAME "skge"
bf9f56d5 52#define DRV_VERSION "1.13"
baef58b1
SH		 53
54#define DEFAULT_TX_RING_SIZE 128
55#define DEFAULT_RX_RING_SIZE 512
56#define MAX_TX_RING_SIZE 1024
9db96479 57#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 58#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 59#define RX_COPY_THRESHOLD 128
60#define RX_BUF_SIZE 1536
baef58b1
SH		 61#define PHY_RETRIES 1000
62#define ETH_JUMBO_MTU 9000
63#define TX_WATCHDOG (5 * HZ)
64#define NAPI_WEIGHT 64
6abebb53 65#define BLINK_MS 250
501fb72d 66#define LINK_HZ HZ
baef58b1 67
afa151b9
SH		 68#define SKGE_EEPROM_MAGIC 0x9933aabb
69
70
baef58b1 71MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 72MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 73MODULE_LICENSE("GPL");
74MODULE_VERSION(DRV_VERSION);
75
67777f9b
JP		 76static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
77 NETIF_MSG_LINK | NETIF_MSG_IFUP |
78 NETIF_MSG_IFDOWN);
baef58b1
SH		 79
80static int debug = -1; /* defaults above */
81module_param(debug, int, 0);
82MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
83
a3aa1884 84static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
275834d1
SH		 85 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
87 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
88 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 89 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 90 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 91 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
92 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
93 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 94 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 95 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 96 { 0 }
97};
98MODULE_DEVICE_TABLE(pci, skge_id_table);
99
100static int skge_up(struct net_device *dev);
101static int skge_down(struct net_device *dev);
ee294dcd 102static void skge_phy_reset(struct skge_port *skge);
513f533e 103static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 104static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
105static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 106static void genesis_get_stats(struct skge_port *skge, u64 *data);
107static void yukon_get_stats(struct skge_port *skge, u64 *data);
108static void yukon_init(struct skge_hw *hw, int port);
baef58b1 109static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 110static void genesis_link_up(struct skge_port *skge);
f80d032b 111static void skge_set_multicast(struct net_device *dev);
baef58b1 112
7e676d91 113/* Avoid conditionals by using array */
baef58b1
SH		 114static const int txqaddr[] = { Q_XA1, Q_XA2 };
115static const int rxqaddr[] = { Q_R1, Q_R2 };
116static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
117static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 118static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
119static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 120
baef58b1
SH		 121static int skge_get_regs_len(struct net_device *dev)
122{
c3f8be96 123 return 0x4000;
baef58b1
SH		 124}
125
126/*
c3f8be96
SH		 127 * Returns copy of whole control register region
128 * Note: skip RAM address register because accessing it will
129 * cause bus hangs!
baef58b1
SH		 130 */
131static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
132 void *p)
133{
134 const struct skge_port *skge = netdev_priv(dev);
baef58b1 135 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 136
137 regs->version = 1;
c3f8be96
SH		 138 memset(p, 0, regs->len);
139 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 140
c3f8be96
SH		 141 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
142 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 143}
144
8f3f8193 145/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 146static u32 wol_supported(const struct skge_hw *hw)
baef58b1 147{
d17ecb23 148 if (hw->chip_id == CHIP_ID_GENESIS)
a504e64a 149 return 0;
d17ecb23
SH		 150
151 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
152 return 0;
153
154 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 155}
156
a504e64a
SH		 157static void skge_wol_init(struct skge_port *skge)
158{
159 struct skge_hw *hw = skge->hw;
160 int port = skge->port;
692412b3 161 u16 ctrl;
a504e64a 162
a504e64a
SH		 163 skge_write16(hw, B0_CTST, CS_RST_CLR);
164 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
165
692412b3
SH		 166 /* Turn on Vaux */
167 skge_write8(hw, B0_POWER_CTRL,
168 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 169
692412b3
SH		 170 /* WA code for COMA mode -- clear PHY reset */
171 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
172 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
173 u32 reg = skge_read32(hw, B2_GP_IO);
174 reg |= GP_DIR_9;
175 reg &= ~GP_IO_9;
176 skge_write32(hw, B2_GP_IO, reg);
177 }
a504e64a 178
692412b3
SH		 179 skge_write32(hw, SK_REG(port, GPHY_CTRL),
180 GPC_DIS_SLEEP |
181 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
182 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 183
692412b3
SH		 184 skge_write32(hw, SK_REG(port, GPHY_CTRL),
185 GPC_DIS_SLEEP |
186 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
187 GPC_ANEG_1 | GPC_RST_CLR);
188
189 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
190
191 /* Force to 10/100 skge_reset will re-enable on resume */
192 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
67777f9b
JP		 193 (PHY_AN_100FULL | PHY_AN_100HALF |
194 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
692412b3
SH		 195 /* no 1000 HD/FD */
196 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
197 gm_phy_write(hw, port, PHY_MARV_CTRL,
198 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
199 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 200
a504e64a
SH		 201
202 /* Set GMAC to no flow control and auto update for speed/duplex */
203 gma_write16(hw, port, GM_GP_CTRL,
204 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
205 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
206
207 /* Set WOL address */
208 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
209 skge->netdev->dev_addr, ETH_ALEN);
210
211 /* Turn on appropriate WOL control bits */
212 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
213 ctrl = 0;
214 if (skge->wol & WAKE_PHY)
215 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
216 else
217 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
218
219 if (skge->wol & WAKE_MAGIC)
220 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
221 else
a419aef8 222 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
a504e64a
SH		 223
224 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
226
227 /* block receiver */
228 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 229}
230
231static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
232{
233 struct skge_port *skge = netdev_priv(dev);
234
a504e64a
SH		 235 wol->supported = wol_supported(skge->hw);
236 wol->wolopts = skge->wol;
baef58b1
SH		 237}
238
239static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
240{
241 struct skge_port *skge = netdev_priv(dev);
242 struct skge_hw *hw = skge->hw;
243
8e95a202
JP		 244 if ((wol->wolopts & ~wol_supported(hw)) ||
245 !device_can_wakeup(&hw->pdev->dev))
baef58b1
SH		 246 return -EOPNOTSUPP;
247
a504e64a 248 skge->wol = wol->wolopts;
5177b324
RW		 249
250 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
251
baef58b1
SH		 252 return 0;
253}
254
8f3f8193
SH		 255/* Determine supported/advertised modes based on hardware.
256 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 257 */
258static u32 skge_supported_modes(const struct skge_hw *hw)
259{
260 u32 supported;
261
5e1705dd 262 if (hw->copper) {
67777f9b
JP		 263 supported = (SUPPORTED_10baseT_Half |
264 SUPPORTED_10baseT_Full |
265 SUPPORTED_100baseT_Half |
266 SUPPORTED_100baseT_Full |
267 SUPPORTED_1000baseT_Half |
268 SUPPORTED_1000baseT_Full |
269 SUPPORTED_Autoneg |
270 SUPPORTED_TP);
31b619c5
SH		 271
272 if (hw->chip_id == CHIP_ID_GENESIS)
67777f9b
JP		 273 supported &= ~(SUPPORTED_10baseT_Half |
274 SUPPORTED_10baseT_Full |
275 SUPPORTED_100baseT_Half |
276 SUPPORTED_100baseT_Full);
31b619c5
SH		 277
278 else if (hw->chip_id == CHIP_ID_YUKON)
279 supported &= ~SUPPORTED_1000baseT_Half;
280 } else
67777f9b
JP		 281 supported = (SUPPORTED_1000baseT_Full |
282 SUPPORTED_1000baseT_Half |
283 SUPPORTED_FIBRE |
284 SUPPORTED_Autoneg);
31b619c5
SH		 285
286 return supported;
287}
baef58b1
SH		 288
289static int skge_get_settings(struct net_device *dev,
290 struct ethtool_cmd *ecmd)
291{
292 struct skge_port *skge = netdev_priv(dev);
293 struct skge_hw *hw = skge->hw;
294
295 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 296 ecmd->supported = skge_supported_modes(hw);
baef58b1 297
5e1705dd 298 if (hw->copper) {
baef58b1
SH		 299 ecmd->port = PORT_TP;
300 ecmd->phy_address = hw->phy_addr;
31b619c5 301 } else
baef58b1 302 ecmd->port = PORT_FIBRE;
baef58b1
SH		 303
304 ecmd->advertising = skge->advertising;
305 ecmd->autoneg = skge->autoneg;
306 ecmd->speed = skge->speed;
307 ecmd->duplex = skge->duplex;
308 return 0;
309}
310
baef58b1
SH		 311static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
312{
313 struct skge_port *skge = netdev_priv(dev);
314 const struct skge_hw *hw = skge->hw;
31b619c5 315 u32 supported = skge_supported_modes(hw);
9ac1353f 316 int err = 0;
baef58b1
SH		 317
318 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 319 ecmd->advertising = supported;
320 skge->duplex = -1;
321 skge->speed = -1;
baef58b1 322 } else {
31b619c5
SH		 323 u32 setting;
324
2c668514 325 switch (ecmd->speed) {
baef58b1 326 case SPEED_1000:
31b619c5
SH		 327 if (ecmd->duplex == DUPLEX_FULL)
328 setting = SUPPORTED_1000baseT_Full;
329 else if (ecmd->duplex == DUPLEX_HALF)
330 setting = SUPPORTED_1000baseT_Half;
331 else
332 return -EINVAL;
baef58b1
SH		 333 break;
334 case SPEED_100:
31b619c5
SH		 335 if (ecmd->duplex == DUPLEX_FULL)
336 setting = SUPPORTED_100baseT_Full;
337 else if (ecmd->duplex == DUPLEX_HALF)
338 setting = SUPPORTED_100baseT_Half;
339 else
340 return -EINVAL;
341 break;
342
baef58b1 343 case SPEED_10:
31b619c5
SH		 344 if (ecmd->duplex == DUPLEX_FULL)
345 setting = SUPPORTED_10baseT_Full;
346 else if (ecmd->duplex == DUPLEX_HALF)
347 setting = SUPPORTED_10baseT_Half;
348 else
baef58b1
SH		 349 return -EINVAL;
350 break;
351 default:
352 return -EINVAL;
353 }
31b619c5
SH		 354
355 if ((setting & supported) == 0)
356 return -EINVAL;
357
358 skge->speed = ecmd->speed;
359 skge->duplex = ecmd->duplex;
baef58b1
SH		 360 }
361
362 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 363 skge->advertising = ecmd->advertising;
364
9ac1353f
XZ		 365 if (netif_running(dev)) {
366 skge_down(dev);
367 err = skge_up(dev);
368 if (err) {
369 dev_close(dev);
370 return err;
371 }
372 }
ee294dcd 373
67777f9b 374 return 0;
baef58b1
SH		 375}
376
377static void skge_get_drvinfo(struct net_device *dev,
378 struct ethtool_drvinfo *info)
379{
380 struct skge_port *skge = netdev_priv(dev);
381
382 strcpy(info->driver, DRV_NAME);
383 strcpy(info->version, DRV_VERSION);
384 strcpy(info->fw_version, "N/A");
385 strcpy(info->bus_info, pci_name(skge->hw->pdev));
386}
387
388static const struct skge_stat {
389 char name[ETH_GSTRING_LEN];
390 u16 xmac_offset;
391 u16 gma_offset;
392} skge_stats[] = {
393 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
394 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
395
396 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
397 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
398 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
399 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
400 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
401 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
402 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
403 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
404
405 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
406 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
407 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
408 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
409 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
410 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
411
412 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
413 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
414 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
415 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
416 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
417};
418
b9f2c044 419static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 420{
b9f2c044
JG		 421 switch (sset) {
422 case ETH_SS_STATS:
423 return ARRAY_SIZE(skge_stats);
424 default:
425 return -EOPNOTSUPP;
426 }
baef58b1
SH		 427}
428
429static void skge_get_ethtool_stats(struct net_device *dev,
430 struct ethtool_stats *stats, u64 *data)
431{
432 struct skge_port *skge = netdev_priv(dev);
433
434 if (skge->hw->chip_id == CHIP_ID_GENESIS)
435 genesis_get_stats(skge, data);
436 else
437 yukon_get_stats(skge, data);
438}
439
440/* Use hardware MIB variables for critical path statistics and
441 * transmit feedback not reported at interrupt.
442 * Other errors are accounted for in interrupt handler.
443 */
444static struct net_device_stats *skge_get_stats(struct net_device *dev)
445{
446 struct skge_port *skge = netdev_priv(dev);
447 u64 data[ARRAY_SIZE(skge_stats)];
448
449 if (skge->hw->chip_id == CHIP_ID_GENESIS)
450 genesis_get_stats(skge, data);
451 else
452 yukon_get_stats(skge, data);
453
da00772f
SH		 454 dev->stats.tx_bytes = data[0];
455 dev->stats.rx_bytes = data[1];
456 dev->stats.tx_packets = data[2] + data[4] + data[6];
457 dev->stats.rx_packets = data[3] + data[5] + data[7];
458 dev->stats.multicast = data[3] + data[5];
459 dev->stats.collisions = data[10];
460 dev->stats.tx_aborted_errors = data[12];
baef58b1 461
da00772f 462 return &dev->stats;
baef58b1
SH		 463}
464
465static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
466{
467 int i;
468
95566065 469 switch (stringset) {
baef58b1
SH		 470 case ETH_SS_STATS:
471 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
472 memcpy(data + i * ETH_GSTRING_LEN,
473 skge_stats[i].name, ETH_GSTRING_LEN);
474 break;
475 }
476}
477
478static void skge_get_ring_param(struct net_device *dev,
479 struct ethtool_ringparam *p)
480{
481 struct skge_port *skge = netdev_priv(dev);
482
483 p->rx_max_pending = MAX_RX_RING_SIZE;
484 p->tx_max_pending = MAX_TX_RING_SIZE;
485 p->rx_mini_max_pending = 0;
486 p->rx_jumbo_max_pending = 0;
487
488 p->rx_pending = skge->rx_ring.count;
489 p->tx_pending = skge->tx_ring.count;
490 p->rx_mini_pending = 0;
491 p->rx_jumbo_pending = 0;
492}
493
494static int skge_set_ring_param(struct net_device *dev,
495 struct ethtool_ringparam *p)
496{
497 struct skge_port *skge = netdev_priv(dev);
e824b3eb 498 int err = 0;
baef58b1
SH		 499
500 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 501 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 502 return -EINVAL;
503
504 skge->rx_ring.count = p->rx_pending;
505 skge->tx_ring.count = p->tx_pending;
506
507 if (netif_running(dev)) {
508 skge_down(dev);
3b8bb472
SH		 509 err = skge_up(dev);
510 if (err)
511 dev_close(dev);
baef58b1
SH		 512 }
513
e824b3eb 514 return err;
baef58b1
SH		 515}
516
517static u32 skge_get_msglevel(struct net_device *netdev)
518{
519 struct skge_port *skge = netdev_priv(netdev);
520 return skge->msg_enable;
521}
522
523static void skge_set_msglevel(struct net_device *netdev, u32 value)
524{
525 struct skge_port *skge = netdev_priv(netdev);
526 skge->msg_enable = value;
527}
528
529static int skge_nway_reset(struct net_device *dev)
530{
531 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 532
533 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
534 return -EINVAL;
535
ee294dcd 536 skge_phy_reset(skge);
baef58b1
SH		 537 return 0;
538}
539
baef58b1
SH		 540static void skge_get_pauseparam(struct net_device *dev,
541 struct ethtool_pauseparam *ecmd)
542{
543 struct skge_port *skge = netdev_priv(dev);
544
8e95a202
JP		 545 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
546 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
547 ecmd->tx_pause = (ecmd->rx_pause ||
548 (skge->flow_control == FLOW_MODE_LOC_SEND));
baef58b1 549
5d5c8e03 550 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 551}
552
553static int skge_set_pauseparam(struct net_device *dev,
554 struct ethtool_pauseparam *ecmd)
555{
556 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 557 struct ethtool_pauseparam old;
9ac1353f 558 int err = 0;
baef58b1 559
5d5c8e03
SH		 560 skge_get_pauseparam(dev, &old);
561
562 if (ecmd->autoneg != old.autoneg)
563 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
564 else {
565 if (ecmd->rx_pause && ecmd->tx_pause)
566 skge->flow_control = FLOW_MODE_SYMMETRIC;
567 else if (ecmd->rx_pause && !ecmd->tx_pause)
568 skge->flow_control = FLOW_MODE_SYM_OR_REM;
569 else if (!ecmd->rx_pause && ecmd->tx_pause)
570 skge->flow_control = FLOW_MODE_LOC_SEND;
571 else
572 skge->flow_control = FLOW_MODE_NONE;
573 }
baef58b1 574
9ac1353f
XZ		 575 if (netif_running(dev)) {
576 skge_down(dev);
577 err = skge_up(dev);
578 if (err) {
579 dev_close(dev);
580 return err;
581 }
582 }
5d5c8e03 583
baef58b1
SH		 584 return 0;
585}
586
587/* Chip internal frequency for clock calculations */
588static inline u32 hwkhz(const struct skge_hw *hw)
589{
187ff3b8 590 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 591}
592
8f3f8193 593/* Chip HZ to microseconds */
baef58b1
SH		 594static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
595{
596 return (ticks * 1000) / hwkhz(hw);
597}
598
8f3f8193 599/* Microseconds to chip HZ */
baef58b1
SH		 600static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
601{
602 return hwkhz(hw) * usec / 1000;
603}
604
605static int skge_get_coalesce(struct net_device *dev,
606 struct ethtool_coalesce *ecmd)
607{
608 struct skge_port *skge = netdev_priv(dev);
609 struct skge_hw *hw = skge->hw;
610 int port = skge->port;
611
612 ecmd->rx_coalesce_usecs = 0;
613 ecmd->tx_coalesce_usecs = 0;
614
615 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
616 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
617 u32 msk = skge_read32(hw, B2_IRQM_MSK);
618
619 if (msk & rxirqmask[port])
620 ecmd->rx_coalesce_usecs = delay;
621 if (msk & txirqmask[port])
622 ecmd->tx_coalesce_usecs = delay;
623 }
624
625 return 0;
626}
627
628/* Note: interrupt timer is per board, but can turn on/off per port */
629static int skge_set_coalesce(struct net_device *dev,
630 struct ethtool_coalesce *ecmd)
631{
632 struct skge_port *skge = netdev_priv(dev);
633 struct skge_hw *hw = skge->hw;
634 int port = skge->port;
635 u32 msk = skge_read32(hw, B2_IRQM_MSK);
636 u32 delay = 25;
637
638 if (ecmd->rx_coalesce_usecs == 0)
639 msk &= ~rxirqmask[port];
640 else if (ecmd->rx_coalesce_usecs < 25 ||
641 ecmd->rx_coalesce_usecs > 33333)
642 return -EINVAL;
643 else {
644 msk |= rxirqmask[port];
645 delay = ecmd->rx_coalesce_usecs;
646 }
647
648 if (ecmd->tx_coalesce_usecs == 0)
649 msk &= ~txirqmask[port];
650 else if (ecmd->tx_coalesce_usecs < 25 ||
651 ecmd->tx_coalesce_usecs > 33333)
652 return -EINVAL;
653 else {
654 msk |= txirqmask[port];
655 delay = min(delay, ecmd->rx_coalesce_usecs);
656 }
657
658 skge_write32(hw, B2_IRQM_MSK, msk);
659 if (msk == 0)
660 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
661 else {
662 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
663 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
664 }
665 return 0;
666}
667
6abebb53
SH		 668enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
669static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 670{
6abebb53
SH		 671 struct skge_hw *hw = skge->hw;
672 int port = skge->port;
673
9cbe330f 674 spin_lock_bh(&hw->phy_lock);
baef58b1 675 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 676 switch (mode) {
677 case LED_MODE_OFF:
64f6b64d
SH		 678 if (hw->phy_type == SK_PHY_BCOM)
679 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
680 else {
681 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
682 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
683 }
6abebb53
SH		 684 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
685 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
686 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
687 break;
baef58b1 688
6abebb53
SH		 689 case LED_MODE_ON:
690 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
691 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 692
6abebb53
SH		 693 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
694 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 695
6abebb53 696 break;
baef58b1 697
6abebb53
SH		 698 case LED_MODE_TST:
699 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
700 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
701 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 702
64f6b64d
SH		 703 if (hw->phy_type == SK_PHY_BCOM)
704 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
705 else {
706 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
707 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
708 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
709 }
710
6abebb53 711 }
baef58b1 712 } else {
6abebb53
SH		 713 switch (mode) {
714 case LED_MODE_OFF:
715 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
716 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
717 PHY_M_LED_MO_DUP(MO_LED_OFF) |
718 PHY_M_LED_MO_10(MO_LED_OFF) |
719 PHY_M_LED_MO_100(MO_LED_OFF) |
720 PHY_M_LED_MO_1000(MO_LED_OFF) |
721 PHY_M_LED_MO_RX(MO_LED_OFF));
722 break;
723 case LED_MODE_ON:
724 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
725 PHY_M_LED_PULS_DUR(PULS_170MS) |
726 PHY_M_LED_BLINK_RT(BLINK_84MS) |
727 PHY_M_LEDC_TX_CTRL |
728 PHY_M_LEDC_DP_CTRL);
46a60f2d 729
6abebb53
SH		 730 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
731 PHY_M_LED_MO_RX(MO_LED_OFF) |
732 (skge->speed == SPEED_100 ?
733 PHY_M_LED_MO_100(MO_LED_ON) : 0));
734 break;
735 case LED_MODE_TST:
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
737 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
738 PHY_M_LED_MO_DUP(MO_LED_ON) |
739 PHY_M_LED_MO_10(MO_LED_ON) |
740 PHY_M_LED_MO_100(MO_LED_ON) |
741 PHY_M_LED_MO_1000(MO_LED_ON) |
742 PHY_M_LED_MO_RX(MO_LED_ON));
743 }
baef58b1 744 }
9cbe330f 745 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 746}
747
748/* blink LED's for finding board */
a5b9f41c 749static int skge_set_phys_id(struct net_device *dev,
750 enum ethtool_phys_id_state state)
baef58b1
SH		 751{
752 struct skge_port *skge = netdev_priv(dev);
753
a5b9f41c 754 switch (state) {
755 case ETHTOOL_ID_ACTIVE:
756 return -EINVAL;
baef58b1 757
a5b9f41c 758 case ETHTOOL_ID_ON:
759 skge_led(skge, LED_MODE_TST);
760 break;
baef58b1 761
a5b9f41c 762 case ETHTOOL_ID_OFF:
763 skge_led(skge, LED_MODE_OFF);
764 break;
baef58b1 765
a5b9f41c 766 case ETHTOOL_ID_INACTIVE:
767 /* back to regular LED state */
768 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
769 }
baef58b1
SH		 770
771 return 0;
772}
773
afa151b9
SH		 774static int skge_get_eeprom_len(struct net_device *dev)
775{
776 struct skge_port *skge = netdev_priv(dev);
777 u32 reg2;
778
779 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
67777f9b 780 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
afa151b9
SH		 781}
782
783static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
784{
785 u32 val;
786
787 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
788
789 do {
790 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
791 } while (!(offset & PCI_VPD_ADDR_F));
792
793 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
794 return val;
795}
796
797static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
798{
799 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
800 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
801 offset | PCI_VPD_ADDR_F);
802
803 do {
804 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
805 } while (offset & PCI_VPD_ADDR_F);
806}
807
808static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
809 u8 *data)
810{
811 struct skge_port *skge = netdev_priv(dev);
812 struct pci_dev *pdev = skge->hw->pdev;
813 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
814 int length = eeprom->len;
815 u16 offset = eeprom->offset;
816
817 if (!cap)
818 return -EINVAL;
819
820 eeprom->magic = SKGE_EEPROM_MAGIC;
821
822 while (length > 0) {
823 u32 val = skge_vpd_read(pdev, cap, offset);
824 int n = min_t(int, length, sizeof(val));
825
826 memcpy(data, &val, n);
827 length -= n;
828 data += n;
829 offset += n;
830 }
831 return 0;
832}
833
834static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
835 u8 *data)
836{
837 struct skge_port *skge = netdev_priv(dev);
838 struct pci_dev *pdev = skge->hw->pdev;
839 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
840 int length = eeprom->len;
841 u16 offset = eeprom->offset;
842
843 if (!cap)
844 return -EINVAL;
845
846 if (eeprom->magic != SKGE_EEPROM_MAGIC)
847 return -EINVAL;
848
849 while (length > 0) {
850 u32 val;
851 int n = min_t(int, length, sizeof(val));
852
853 if (n < sizeof(val))
854 val = skge_vpd_read(pdev, cap, offset);
855 memcpy(&val, data, n);
856
857 skge_vpd_write(pdev, cap, offset, val);
858
859 length -= n;
860 data += n;
861 offset += n;
862 }
863 return 0;
864}
865
7282d491 866static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 867 .get_settings = skge_get_settings,
868 .set_settings = skge_set_settings,
869 .get_drvinfo = skge_get_drvinfo,
870 .get_regs_len = skge_get_regs_len,
871 .get_regs = skge_get_regs,
872 .get_wol = skge_get_wol,
873 .set_wol = skge_set_wol,
874 .get_msglevel = skge_get_msglevel,
875 .set_msglevel = skge_set_msglevel,
876 .nway_reset = skge_nway_reset,
877 .get_link = ethtool_op_get_link,
afa151b9
SH		 878 .get_eeprom_len = skge_get_eeprom_len,
879 .get_eeprom = skge_get_eeprom,
880 .set_eeprom = skge_set_eeprom,
baef58b1
SH		 881 .get_ringparam = skge_get_ring_param,
882 .set_ringparam = skge_set_ring_param,
883 .get_pauseparam = skge_get_pauseparam,
884 .set_pauseparam = skge_set_pauseparam,
885 .get_coalesce = skge_get_coalesce,
886 .set_coalesce = skge_set_coalesce,
baef58b1 887 .get_strings = skge_get_strings,
a5b9f41c 888 .set_phys_id = skge_set_phys_id,
b9f2c044 889 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 890 .get_ethtool_stats = skge_get_ethtool_stats,
891};
892
893/*
894 * Allocate ring elements and chain them together
895 * One-to-one association of board descriptors with ring elements
896 */
c3da1447 897static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 898{
899 struct skge_tx_desc *d;
900 struct skge_element *e;
901 int i;
902
cd861280 903 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 904 if (!ring->start)
905 return -ENOMEM;
906
907 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
908 e->desc = d;
909 if (i == ring->count - 1) {
910 e->next = ring->start;
911 d->next_offset = base;
912 } else {
913 e->next = e + 1;
914 d->next_offset = base + (i+1) * sizeof(*d);
915 }
916 }
917 ring->to_use = ring->to_clean = ring->start;
918
919 return 0;
920}
921
19a33d4e
SH		 922/* Allocate and setup a new buffer for receiving */
923static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
924 struct sk_buff *skb, unsigned int bufsize)
925{
926 struct skge_rx_desc *rd = e->desc;
927 u64 map;
baef58b1
SH		 928
929 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
930 PCI_DMA_FROMDEVICE);
931
932 rd->dma_lo = map;
933 rd->dma_hi = map >> 32;
934 e->skb = skb;
935 rd->csum1_start = ETH_HLEN;
936 rd->csum2_start = ETH_HLEN;
937 rd->csum1 = 0;
938 rd->csum2 = 0;
939
940 wmb();
941
942 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
10fc51b9
FT		 943 dma_unmap_addr_set(e, mapaddr, map);
944 dma_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 945}
946
19a33d4e
SH		 947/* Resume receiving using existing skb,
948 * Note: DMA address is not changed by chip.
949 * MTU not changed while receiver active.
950 */
5a011447 951static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 952{
953 struct skge_rx_desc *rd = e->desc;
954
955 rd->csum2 = 0;
956 rd->csum2_start = ETH_HLEN;
957
958 wmb();
959
960 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
961}
962
963
964/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 965static void skge_rx_clean(struct skge_port *skge)
966{
967 struct skge_hw *hw = skge->hw;
968 struct skge_ring *ring = &skge->rx_ring;
969 struct skge_element *e;
970
19a33d4e
SH		 971 e = ring->start;
972 do {
baef58b1
SH		 973 struct skge_rx_desc *rd = e->desc;
974 rd->control = 0;
19a33d4e
SH		 975 if (e->skb) {
976 pci_unmap_single(hw->pdev,
10fc51b9
FT		 977 dma_unmap_addr(e, mapaddr),
978 dma_unmap_len(e, maplen),
19a33d4e
SH		 979 PCI_DMA_FROMDEVICE);
980 dev_kfree_skb(e->skb);
981 e->skb = NULL;
982 }
983 } while ((e = e->next) != ring->start);
baef58b1
SH		 984}
985
19a33d4e 986
baef58b1 987/* Allocate buffers for receive ring
19a33d4e 988 * For receive: to_clean is next received frame.
baef58b1 989 */
c54f9765 990static int skge_rx_fill(struct net_device *dev)
baef58b1 991{
c54f9765 992 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 993 struct skge_ring *ring = &skge->rx_ring;
994 struct skge_element *e;
baef58b1 995
19a33d4e
SH		 996 e = ring->start;
997 do {
383181ac 998 struct sk_buff *skb;
baef58b1 999
c54f9765
SH		 1000 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1001 GFP_KERNEL);
19a33d4e
SH		 1002 if (!skb)
1003 return -ENOMEM;
1004
383181ac
SH		 1005 skb_reserve(skb, NET_IP_ALIGN);
1006 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
67777f9b 1007 } while ((e = e->next) != ring->start);
baef58b1 1008
19a33d4e
SH		 1009 ring->to_clean = ring->start;
1010 return 0;
baef58b1
SH		 1011}
1012
5d5c8e03
SH		 1013static const char *skge_pause(enum pause_status status)
1014{
67777f9b 1015 switch (status) {
5d5c8e03
SH		 1016 case FLOW_STAT_NONE:
1017 return "none";
1018 case FLOW_STAT_REM_SEND:
1019 return "rx only";
1020 case FLOW_STAT_LOC_SEND:
1021 return "tx_only";
1022 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1023 return "both";
1024 default:
1025 return "indeterminated";
1026 }
1027}
1028
1029
baef58b1
SH		 1030static void skge_link_up(struct skge_port *skge)
1031{
46a60f2d 1032 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 1033 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1034
baef58b1 1035 netif_carrier_on(skge->netdev);
29b4e886 1036 netif_wake_queue(skge->netdev);
baef58b1 1037
d707204c
JP		 1038 netif_info(skge, link, skge->netdev,
1039 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1040 skge->speed,
1041 skge->duplex == DUPLEX_FULL ? "full" : "half",
1042 skge_pause(skge->flow_status));
baef58b1
SH		 1043}
1044
1045static void skge_link_down(struct skge_port *skge)
1046{
54cfb5aa 1047 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 1048 netif_carrier_off(skge->netdev);
1049 netif_stop_queue(skge->netdev);
1050
d707204c 1051 netif_info(skge, link, skge->netdev, "Link is down\n");
baef58b1
SH		 1052}
1053
a1bc9b87
SH		 1054
1055static void xm_link_down(struct skge_hw *hw, int port)
1056{
1057 struct net_device *dev = hw->dev[port];
1058 struct skge_port *skge = netdev_priv(dev);
a1bc9b87 1059
501fb72d 1060 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
a1bc9b87 1061
a1bc9b87
SH		 1062 if (netif_carrier_ok(dev))
1063 skge_link_down(skge);
1064}
1065
2cd8e5d3 1066static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1067{
1068 int i;
baef58b1 1069
6b0c1480 1070 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1071 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1072
64f6b64d
SH		 1073 if (hw->phy_type == SK_PHY_XMAC)
1074 goto ready;
1075
89bf5f23 1076 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1077 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1078 goto ready;
0781191c 1079 udelay(1);
baef58b1
SH		 1080 }
1081
2cd8e5d3 1082 return -ETIMEDOUT;
89bf5f23 1083 ready:
2cd8e5d3 1084 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1085
2cd8e5d3
SH		 1086 return 0;
1087}
1088
1089static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1090{
1091 u16 v = 0;
1092 if (__xm_phy_read(hw, port, reg, &v))
f15063cd 1093 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
baef58b1
SH		 1094 return v;
1095}
1096
2cd8e5d3 1097static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1098{
1099 int i;
1100
6b0c1480 1101 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1102 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1103 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1104 goto ready;
89bf5f23 1105 udelay(1);
baef58b1 1106 }
2cd8e5d3 1107 return -EIO;
baef58b1
SH		 1108
1109 ready:
6b0c1480 1110 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1111 for (i = 0; i < PHY_RETRIES; i++) {
1112 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1113 return 0;
1114 udelay(1);
1115 }
1116 return -ETIMEDOUT;
baef58b1
SH		 1117}
1118
1119static void genesis_init(struct skge_hw *hw)
1120{
1121 /* set blink source counter */
1122 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1123 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1124
1125 /* configure mac arbiter */
1126 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1127
1128 /* configure mac arbiter timeout values */
1129 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1130 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1131 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1132 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1133
1134 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1135 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1136 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1137 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1138
1139 /* configure packet arbiter timeout */
1140 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1141 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1142 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1143 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1144 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1145}
1146
1147static void genesis_reset(struct skge_hw *hw, int port)
1148{
b6bc7650 1149 static const u8 zero[8] = { 0 };
21d7f677 1150 u32 reg;
baef58b1 1151
46a60f2d
SH		 1152 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1153
baef58b1 1154 /* reset the statistics module */
6b0c1480 1155 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
501fb72d 1156 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
6b0c1480
SH		 1157 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1158 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1159 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1160
89bf5f23 1161 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1162 if (hw->phy_type == SK_PHY_BCOM)
1163 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1164
45bada65 1165 xm_outhash(hw, port, XM_HSM, zero);
21d7f677
SH		 1166
1167 /* Flush TX and RX fifo */
1168 reg = xm_read32(hw, port, XM_MODE);
1169 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1170 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
baef58b1
SH		 1171}
1172
1173
45bada65
SH		 1174/* Convert mode to MII values */
1175static const u16 phy_pause_map[] = {
1176 [FLOW_MODE_NONE] = 0,
1177 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1178 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1179 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1180};
1181
4b67be99
SH		 1182/* special defines for FIBER (88E1011S only) */
1183static const u16 fiber_pause_map[] = {
1184 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1185 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1186 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1187 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1188};
1189
45bada65
SH		 1190
1191/* Check status of Broadcom phy link */
1192static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1193{
45bada65
SH		 1194 struct net_device *dev = hw->dev[port];
1195 struct skge_port *skge = netdev_priv(dev);
1196 u16 status;
1197
1198 /* read twice because of latch */
501fb72d 1199 xm_phy_read(hw, port, PHY_BCOM_STAT);
45bada65
SH		 1200 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1201
45bada65 1202 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1203 xm_link_down(hw, port);
64f6b64d
SH		 1204 return;
1205 }
45bada65 1206
64f6b64d
SH		 1207 if (skge->autoneg == AUTONEG_ENABLE) {
1208 u16 lpa, aux;
45bada65 1209
64f6b64d
SH		 1210 if (!(status & PHY_ST_AN_OVER))
1211 return;
45bada65 1212
64f6b64d
SH		 1213 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1214 if (lpa & PHY_B_AN_RF) {
f15063cd 1215 netdev_notice(dev, "remote fault\n");
64f6b64d
SH		 1216 return;
1217 }
45bada65 1218
64f6b64d
SH		 1219 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1220
1221 /* Check Duplex mismatch */
1222 switch (aux & PHY_B_AS_AN_RES_MSK) {
1223 case PHY_B_RES_1000FD:
1224 skge->duplex = DUPLEX_FULL;
1225 break;
1226 case PHY_B_RES_1000HD:
1227 skge->duplex = DUPLEX_HALF;
1228 break;
1229 default:
f15063cd 1230 netdev_notice(dev, "duplex mismatch\n");
64f6b64d 1231 return;
45bada65
SH		 1232 }
1233
64f6b64d
SH		 1234 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1235 switch (aux & PHY_B_AS_PAUSE_MSK) {
1236 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1237 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1238 break;
1239 case PHY_B_AS_PRR:
5d5c8e03 1240 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1241 break;
1242 case PHY_B_AS_PRT:
5d5c8e03 1243 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1244 break;
1245 default:
5d5c8e03 1246 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1247 }
1248 skge->speed = SPEED_1000;
45bada65 1249 }
64f6b64d
SH		 1250
1251 if (!netif_carrier_ok(dev))
1252 genesis_link_up(skge);
45bada65
SH		 1253}
1254
1255/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1256 * Phy on for 100 or 10Mbit operation
1257 */
64f6b64d 1258static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1259{
1260 struct skge_hw *hw = skge->hw;
1261 int port = skge->port;
baef58b1 1262 int i;
45bada65 1263 u16 id1, r, ext, ctl;
baef58b1
SH		 1264
1265 /* magic workaround patterns for Broadcom */
1266 static const struct {
1267 u16 reg;
1268 u16 val;
1269 } A1hack[] = {
1270 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1271 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1272 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1273 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1274 }, C0hack[] = {
1275 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1276 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1277 };
1278
45bada65
SH		 1279 /* read Id from external PHY (all have the same address) */
1280 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1281
1282 /* Optimize MDIO transfer by suppressing preamble. */
1283 r = xm_read16(hw, port, XM_MMU_CMD);
1284 r |= XM_MMU_NO_PRE;
67777f9b 1285 xm_write16(hw, port, XM_MMU_CMD, r);
45bada65 1286
2c668514 1287 switch (id1) {
45bada65
SH		 1288 case PHY_BCOM_ID1_C0:
1289 /*
1290 * Workaround BCOM Errata for the C0 type.
1291 * Write magic patterns to reserved registers.
1292 */
1293 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1294 xm_phy_write(hw, port,
1295 C0hack[i].reg, C0hack[i].val);
1296
1297 break;
1298 case PHY_BCOM_ID1_A1:
1299 /*
1300 * Workaround BCOM Errata for the A1 type.
1301 * Write magic patterns to reserved registers.
1302 */
1303 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1304 xm_phy_write(hw, port,
1305 A1hack[i].reg, A1hack[i].val);
1306 break;
1307 }
1308
1309 /*
1310 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1311 * Disable Power Management after reset.
1312 */
1313 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1314 r |= PHY_B_AC_DIS_PM;
1315 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1316
1317 /* Dummy read */
1318 xm_read16(hw, port, XM_ISRC);
1319
1320 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1321 ctl = PHY_CT_SP1000; /* always 1000mbit */
1322
1323 if (skge->autoneg == AUTONEG_ENABLE) {
1324 /*
1325 * Workaround BCOM Errata #1 for the C5 type.
1326 * 1000Base-T Link Acquisition Failure in Slave Mode
1327 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1328 */
1329 u16 adv = PHY_B_1000C_RD;
1330 if (skge->advertising & ADVERTISED_1000baseT_Half)
1331 adv |= PHY_B_1000C_AHD;
1332 if (skge->advertising & ADVERTISED_1000baseT_Full)
1333 adv |= PHY_B_1000C_AFD;
1334 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1335
1336 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1337 } else {
1338 if (skge->duplex == DUPLEX_FULL)
1339 ctl |= PHY_CT_DUP_MD;
1340 /* Force to slave */
1341 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1342 }
1343
1344 /* Set autonegotiation pause parameters */
1345 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1346 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1347
1348 /* Handle Jumbo frames */
64f6b64d 1349 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1350 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1351 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1352
1353 ext |= PHY_B_PEC_HIGH_LA;
1354
1355 }
1356
1357 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1358 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1359
8f3f8193 1360 /* Use link status change interrupt */
45bada65 1361 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1362}
45bada65 1363
64f6b64d
SH		 1364static void xm_phy_init(struct skge_port *skge)
1365{
1366 struct skge_hw *hw = skge->hw;
1367 int port = skge->port;
1368 u16 ctrl = 0;
1369
1370 if (skge->autoneg == AUTONEG_ENABLE) {
1371 if (skge->advertising & ADVERTISED_1000baseT_Half)
1372 ctrl |= PHY_X_AN_HD;
1373 if (skge->advertising & ADVERTISED_1000baseT_Full)
1374 ctrl |= PHY_X_AN_FD;
1375
4b67be99 1376 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1377
1378 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1379
1380 /* Restart Auto-negotiation */
1381 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1382 } else {
1383 /* Set DuplexMode in Config register */
1384 if (skge->duplex == DUPLEX_FULL)
1385 ctrl |= PHY_CT_DUP_MD;
1386 /*
1387 * Do NOT enable Auto-negotiation here. This would hold
1388 * the link down because no IDLEs are transmitted
1389 */
1390 }
1391
1392 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1393
1394 /* Poll PHY for status changes */
9cbe330f 1395 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1396}
1397
501fb72d 1398static int xm_check_link(struct net_device *dev)
64f6b64d
SH		 1399{
1400 struct skge_port *skge = netdev_priv(dev);
1401 struct skge_hw *hw = skge->hw;
1402 int port = skge->port;
1403 u16 status;
1404
1405 /* read twice because of latch */
501fb72d 1406 xm_phy_read(hw, port, PHY_XMAC_STAT);
64f6b64d
SH		 1407 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1408
1409 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1410 xm_link_down(hw, port);
501fb72d 1411 return 0;
64f6b64d
SH		 1412 }
1413
1414 if (skge->autoneg == AUTONEG_ENABLE) {
1415 u16 lpa, res;
1416
1417 if (!(status & PHY_ST_AN_OVER))
501fb72d 1418 return 0;
64f6b64d
SH		 1419
1420 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1421 if (lpa & PHY_B_AN_RF) {
f15063cd 1422 netdev_notice(dev, "remote fault\n");
501fb72d 1423 return 0;
64f6b64d
SH		 1424 }
1425
1426 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1427
1428 /* Check Duplex mismatch */
1429 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1430 case PHY_X_RS_FD:
1431 skge->duplex = DUPLEX_FULL;
1432 break;
1433 case PHY_X_RS_HD:
1434 skge->duplex = DUPLEX_HALF;
1435 break;
1436 default:
f15063cd 1437 netdev_notice(dev, "duplex mismatch\n");
501fb72d 1438 return 0;
64f6b64d
SH		 1439 }
1440
1441 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1442 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1443 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1444 (lpa & PHY_X_P_SYM_MD))
1445 skge->flow_status = FLOW_STAT_SYMMETRIC;
1446 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1447 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1448 /* Enable PAUSE receive, disable PAUSE transmit */
1449 skge->flow_status = FLOW_STAT_REM_SEND;
1450 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1451 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1452 /* Disable PAUSE receive, enable PAUSE transmit */
1453 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1454 else
5d5c8e03 1455 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1456
1457 skge->speed = SPEED_1000;
1458 }
1459
1460 if (!netif_carrier_ok(dev))
1461 genesis_link_up(skge);
501fb72d 1462 return 1;
64f6b64d
SH		 1463}
1464
1465/* Poll to check for link coming up.
501fb72d 1466 *
64f6b64d 1467 * Since internal PHY is wired to a level triggered pin, can't
501fb72d
SH		 1468 * get an interrupt when carrier is detected, need to poll for
1469 * link coming up.
64f6b64d 1470 */
9cbe330f 1471static void xm_link_timer(unsigned long arg)
64f6b64d 1472{
9cbe330f 1473 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1474 struct net_device *dev = skge->netdev;
67777f9b 1475 struct skge_hw *hw = skge->hw;
64f6b64d 1476 int port = skge->port;
501fb72d
SH		 1477 int i;
1478 unsigned long flags;
64f6b64d
SH		 1479
1480 if (!netif_running(dev))
1481 return;
1482
501fb72d
SH		 1483 spin_lock_irqsave(&hw->phy_lock, flags);
1484
1485 /*
1486 * Verify that the link by checking GPIO register three times.
1487 * This pin has the signal from the link_sync pin connected to it.
1488 */
1489 for (i = 0; i < 3; i++) {
1490 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1491 goto link_down;
1492 }
1493
67777f9b 1494 /* Re-enable interrupt to detect link down */
501fb72d
SH		 1495 if (xm_check_link(dev)) {
1496 u16 msk = xm_read16(hw, port, XM_IMSK);
1497 msk &= ~XM_IS_INP_ASS;
1498 xm_write16(hw, port, XM_IMSK, msk);
64f6b64d 1499 xm_read16(hw, port, XM_ISRC);
64f6b64d 1500 } else {
501fb72d
SH		 1501link_down:
1502 mod_timer(&skge->link_timer,
1503 round_jiffies(jiffies + LINK_HZ));
64f6b64d 1504 }
501fb72d 1505 spin_unlock_irqrestore(&hw->phy_lock, flags);
45bada65
SH		 1506}
1507
1508static void genesis_mac_init(struct skge_hw *hw, int port)
1509{
1510 struct net_device *dev = hw->dev[port];
1511 struct skge_port *skge = netdev_priv(dev);
1512 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1513 int i;
1514 u32 r;
b6bc7650 1515 static const u8 zero[6] = { 0 };
45bada65 1516
0781191c
SH		 1517 for (i = 0; i < 10; i++) {
1518 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1519 MFF_SET_MAC_RST);
1520 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1521 goto reset_ok;
1522 udelay(1);
1523 }
baef58b1 1524
f15063cd 1525 netdev_warn(dev, "genesis reset failed\n");
0781191c
SH		 1526
1527 reset_ok:
baef58b1 1528 /* Unreset the XMAC. */
6b0c1480 1529 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1530
1531 /*
1532 * Perform additional initialization for external PHYs,
1533 * namely for the 1000baseTX cards that use the XMAC's
1534 * GMII mode.
1535 */
64f6b64d
SH		 1536 if (hw->phy_type != SK_PHY_XMAC) {
1537 /* Take external Phy out of reset */
1538 r = skge_read32(hw, B2_GP_IO);
1539 if (port == 0)
1540 r |= GP_DIR_0|GP_IO_0;
1541 else
1542 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1543
64f6b64d 1544 skge_write32(hw, B2_GP_IO, r);
0781191c 1545
64f6b64d
SH		 1546 /* Enable GMII interface */
1547 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1548 }
89bf5f23 1549
89bf5f23 1550
67777f9b 1551 switch (hw->phy_type) {
64f6b64d
SH		 1552 case SK_PHY_XMAC:
1553 xm_phy_init(skge);
1554 break;
1555 case SK_PHY_BCOM:
1556 bcom_phy_init(skge);
1557 bcom_check_link(hw, port);
1558 }
89bf5f23 1559
45bada65
SH		 1560 /* Set Station Address */
1561 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1562
45bada65
SH		 1563 /* We don't use match addresses so clear */
1564 for (i = 1; i < 16; i++)
1565 xm_outaddr(hw, port, XM_EXM(i), zero);
1566
0781191c
SH		 1567 /* Clear MIB counters */
1568 xm_write16(hw, port, XM_STAT_CMD,
1569 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1570 /* Clear two times according to Errata #3 */
1571 xm_write16(hw, port, XM_STAT_CMD,
1572 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1573
45bada65
SH		 1574 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1575 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1576
1577 /* We don't need the FCS appended to the packet. */
1578 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1579 if (jumbo)
1580 r |= XM_RX_BIG_PK_OK;
89bf5f23 1581
45bada65 1582 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1583 /*
45bada65
SH		 1584 * If in manual half duplex mode the other side might be in
1585 * full duplex mode, so ignore if a carrier extension is not seen
1586 * on frames received
89bf5f23 1587 */
45bada65 1588 r |= XM_RX_DIS_CEXT;
baef58b1 1589 }
45bada65 1590 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1591
baef58b1 1592 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1593 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1594
485982a9
SH		 1595 /* Increase threshold for jumbo frames on dual port */
1596 if (hw->ports > 1 && jumbo)
1597 xm_write16(hw, port, XM_TX_THR, 1020);
1598 else
1599 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1600
1601 /*
1602 * Enable the reception of all error frames. This is is
1603 * a necessary evil due to the design of the XMAC. The
1604 * XMAC's receive FIFO is only 8K in size, however jumbo
1605 * frames can be up to 9000 bytes in length. When bad
1606 * frame filtering is enabled, the XMAC's RX FIFO operates
1607 * in 'store and forward' mode. For this to work, the
1608 * entire frame has to fit into the FIFO, but that means
1609 * that jumbo frames larger than 8192 bytes will be
1610 * truncated. Disabling all bad frame filtering causes
1611 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1612 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1613 * RX FIFO as soon as the FIFO threshold is reached.
1614 */
45bada65 1615 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1616
baef58b1
SH		 1617
1618 /*
45bada65
SH		 1619 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1620 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1621 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1622 */
45bada65
SH		 1623 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1624
1625 /*
1626 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1627 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1628 * and 'Octets Tx OK Hi Cnt Ov'.
1629 */
1630 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1631
1632 /* Configure MAC arbiter */
1633 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1634
1635 /* configure timeout values */
1636 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1637 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1638 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1639 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1640
1641 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1642 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1643 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1644 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1645
1646 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1647 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1648 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1649 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1650
1651 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1652 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1653 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1654 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1655
45bada65 1656 if (jumbo) {
baef58b1 1657 /* Enable frame flushing if jumbo frames used */
67777f9b 1658 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1659 } else {
1660 /* enable timeout timers if normal frames */
1661 skge_write16(hw, B3_PA_CTRL,
45bada65 1662 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1663 }
baef58b1
SH		 1664}
1665
1666static void genesis_stop(struct skge_port *skge)
1667{
1668 struct skge_hw *hw = skge->hw;
1669 int port = skge->port;
799b21d2 1670 unsigned retries = 1000;
21d7f677
SH		 1671 u16 cmd;
1672
67777f9b 1673 /* Disable Tx and Rx */
21d7f677
SH		 1674 cmd = xm_read16(hw, port, XM_MMU_CMD);
1675 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1676 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1677
46a60f2d
SH		 1678 genesis_reset(hw, port);
1679
baef58b1
SH		 1680 /* Clear Tx packet arbiter timeout IRQ */
1681 skge_write16(hw, B3_PA_CTRL,
1682 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1683
baef58b1 1684 /* Reset the MAC */
799b21d2
SH		 1685 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1686 do {
1687 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1688 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1689 break;
1690 } while (--retries > 0);
baef58b1
SH		 1691
1692 /* For external PHYs there must be special handling */
64f6b64d 1693 if (hw->phy_type != SK_PHY_XMAC) {
799b21d2 1694 u32 reg = skge_read32(hw, B2_GP_IO);
64f6b64d
SH		 1695 if (port == 0) {
1696 reg |= GP_DIR_0;
1697 reg &= ~GP_IO_0;
1698 } else {
1699 reg |= GP_DIR_2;
1700 reg &= ~GP_IO_2;
1701 }
1702 skge_write32(hw, B2_GP_IO, reg);
1703 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1704 }
1705
6b0c1480
SH		 1706 xm_write16(hw, port, XM_MMU_CMD,
1707 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1708 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1709
6b0c1480 1710 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1711}
1712
1713
1714static void genesis_get_stats(struct skge_port *skge, u64 *data)
1715{
1716 struct skge_hw *hw = skge->hw;
1717 int port = skge->port;
1718 int i;
1719 unsigned long timeout = jiffies + HZ;
1720
6b0c1480 1721 xm_write16(hw, port,
baef58b1
SH		 1722 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1723
1724 /* wait for update to complete */
6b0c1480 1725 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1726 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1727 if (time_after(jiffies, timeout))
1728 break;
1729 udelay(10);
1730 }
1731
1732 /* special case for 64 bit octet counter */
6b0c1480
SH		 1733 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1734 | xm_read32(hw, port, XM_TXO_OK_LO);
1735 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1736 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1737
1738 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1739 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1740}
1741
1742static void genesis_mac_intr(struct skge_hw *hw, int port)
1743{
da00772f
SH		 1744 struct net_device *dev = hw->dev[port];
1745 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1746 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1747
d707204c
JP		 1748 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1749 "mac interrupt status 0x%x\n", status);
baef58b1 1750
501fb72d 1751 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
67777f9b 1752 xm_link_down(hw, port);
501fb72d
SH		 1753 mod_timer(&skge->link_timer, jiffies + 1);
1754 }
a1bc9b87 1755
baef58b1 1756 if (status & XM_IS_TXF_UR) {
6b0c1480 1757 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
da00772f 1758 ++dev->stats.tx_fifo_errors;
baef58b1 1759 }
baef58b1
SH		 1760}
1761
baef58b1
SH		 1762static void genesis_link_up(struct skge_port *skge)
1763{
1764 struct skge_hw *hw = skge->hw;
1765 int port = skge->port;
a1bc9b87 1766 u16 cmd, msk;
64f6b64d 1767 u32 mode;
baef58b1 1768
6b0c1480 1769 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1770
1771 /*
1772 * enabling pause frame reception is required for 1000BT
1773 * because the XMAC is not reset if the link is going down
1774 */
5d5c8e03
SH		 1775 if (skge->flow_status == FLOW_STAT_NONE ||
1776 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1777 /* Disable Pause Frame Reception */
baef58b1
SH		 1778 cmd |= XM_MMU_IGN_PF;
1779 else
1780 /* Enable Pause Frame Reception */
1781 cmd &= ~XM_MMU_IGN_PF;
1782
6b0c1480 1783 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1784
6b0c1480 1785 mode = xm_read32(hw, port, XM_MODE);
67777f9b 1786 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
5d5c8e03 1787 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1788 /*
1789 * Configure Pause Frame Generation
1790 * Use internal and external Pause Frame Generation.
1791 * Sending pause frames is edge triggered.
1792 * Send a Pause frame with the maximum pause time if
1793 * internal oder external FIFO full condition occurs.
1794 * Send a zero pause time frame to re-start transmission.
1795 */
1796 /* XM_PAUSE_DA = '010000C28001' (default) */
1797 /* XM_MAC_PTIME = 0xffff (maximum) */
1798 /* remember this value is defined in big endian (!) */
6b0c1480 1799 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1800
1801 mode |= XM_PAUSE_MODE;
6b0c1480 1802 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1803 } else {
1804 /*
1805 * disable pause frame generation is required for 1000BT
1806 * because the XMAC is not reset if the link is going down
1807 */
1808 /* Disable Pause Mode in Mode Register */
1809 mode &= ~XM_PAUSE_MODE;
1810
6b0c1480 1811 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1812 }
1813
6b0c1480 1814 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87 1815
d08b9bdf 1816 /* Turn on detection of Tx underrun */
501fb72d 1817 msk = xm_read16(hw, port, XM_IMSK);
d08b9bdf 1818 msk &= ~XM_IS_TXF_UR;
a1bc9b87 1819 xm_write16(hw, port, XM_IMSK, msk);
501fb72d 1820
6b0c1480 1821 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1822
1823 /* get MMU Command Reg. */
6b0c1480 1824 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1825 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1826 cmd |= XM_MMU_GMII_FD;
1827
89bf5f23
SH		 1828 /*
1829 * Workaround BCOM Errata (#10523) for all BCom Phys
1830 * Enable Power Management after link up
1831 */
64f6b64d
SH		 1832 if (hw->phy_type == SK_PHY_BCOM) {
1833 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1834 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1835 & ~PHY_B_AC_DIS_PM);
1836 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1837 }
baef58b1
SH		 1838
1839 /* enable Rx/Tx */
6b0c1480 1840 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1841 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1842 skge_link_up(skge);
1843}
1844
1845
45bada65 1846static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1847{
1848 struct skge_hw *hw = skge->hw;
1849 int port = skge->port;
45bada65
SH		 1850 u16 isrc;
1851
1852 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
d707204c
JP		 1853 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1854 "phy interrupt status 0x%x\n", isrc);
baef58b1 1855
45bada65 1856 if (isrc & PHY_B_IS_PSE)
f15063cd 1857 pr_err("%s: uncorrectable pair swap error\n",
45bada65 1858 hw->dev[port]->name);
baef58b1
SH		 1859
1860 /* Workaround BCom Errata:
1861 * enable and disable loopback mode if "NO HCD" occurs.
1862 */
45bada65 1863 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1864 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1865 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1866 ctrl | PHY_CT_LOOP);
6b0c1480 1867 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1868 ctrl & ~PHY_CT_LOOP);
1869 }
1870
45bada65
SH		 1871 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1872 bcom_check_link(hw, port);
baef58b1 1873
baef58b1
SH		 1874}
1875
2cd8e5d3
SH		 1876static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1877{
1878 int i;
1879
1880 gma_write16(hw, port, GM_SMI_DATA, val);
1881 gma_write16(hw, port, GM_SMI_CTRL,
1882 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1883 for (i = 0; i < PHY_RETRIES; i++) {
1884 udelay(1);
1885
1886 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1887 return 0;
1888 }
1889
f15063cd 1890 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1891 return -EIO;
1892}
1893
1894static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1895{
1896 int i;
1897
1898 gma_write16(hw, port, GM_SMI_CTRL,
1899 GM_SMI_CT_PHY_AD(hw->phy_addr)
1900 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1901
1902 for (i = 0; i < PHY_RETRIES; i++) {
1903 udelay(1);
1904 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1905 goto ready;
1906 }
1907
1908 return -ETIMEDOUT;
1909 ready:
1910 *val = gma_read16(hw, port, GM_SMI_DATA);
1911 return 0;
1912}
1913
1914static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1915{
1916 u16 v = 0;
1917 if (__gm_phy_read(hw, port, reg, &v))
f15063cd 1918 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1919 return v;
1920}
1921
8f3f8193 1922/* Marvell Phy Initialization */
baef58b1
SH		 1923static void yukon_init(struct skge_hw *hw, int port)
1924{
1925 struct skge_port *skge = netdev_priv(hw->dev[port]);
1926 u16 ctrl, ct1000, adv;
baef58b1 1927
baef58b1 1928 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1929 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1930
1931 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1932 PHY_M_EC_MAC_S_MSK);
1933 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1934
c506a509 1935 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1936
6b0c1480 1937 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1938 }
1939
6b0c1480 1940 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1941 if (skge->autoneg == AUTONEG_DISABLE)
1942 ctrl &= ~PHY_CT_ANE;
1943
1944 ctrl |= PHY_CT_RESET;
6b0c1480 1945 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1946
1947 ctrl = 0;
1948 ct1000 = 0;
b18f2091 1949 adv = PHY_AN_CSMA;
baef58b1
SH		 1950
1951 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1952 if (hw->copper) {
baef58b1
SH		 1953 if (skge->advertising & ADVERTISED_1000baseT_Full)
1954 ct1000 |= PHY_M_1000C_AFD;
1955 if (skge->advertising & ADVERTISED_1000baseT_Half)
1956 ct1000 |= PHY_M_1000C_AHD;
1957 if (skge->advertising & ADVERTISED_100baseT_Full)
1958 adv |= PHY_M_AN_100_FD;
1959 if (skge->advertising & ADVERTISED_100baseT_Half)
1960 adv |= PHY_M_AN_100_HD;
1961 if (skge->advertising & ADVERTISED_10baseT_Full)
1962 adv |= PHY_M_AN_10_FD;
1963 if (skge->advertising & ADVERTISED_10baseT_Half)
1964 adv |= PHY_M_AN_10_HD;
baef58b1 1965
4b67be99
SH		 1966 /* Set Flow-control capabilities */
1967 adv |= phy_pause_map[skge->flow_control];
1968 } else {
1969 if (skge->advertising & ADVERTISED_1000baseT_Full)
1970 adv |= PHY_M_AN_1000X_AFD;
1971 if (skge->advertising & ADVERTISED_1000baseT_Half)
1972 adv |= PHY_M_AN_1000X_AHD;
1973
1974 adv |= fiber_pause_map[skge->flow_control];
1975 }
45bada65 1976
baef58b1
SH		 1977 /* Restart Auto-negotiation */
1978 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1979 } else {
1980 /* forced speed/duplex settings */
1981 ct1000 = PHY_M_1000C_MSE;
1982
1983 if (skge->duplex == DUPLEX_FULL)
1984 ctrl |= PHY_CT_DUP_MD;
1985
1986 switch (skge->speed) {
1987 case SPEED_1000:
1988 ctrl |= PHY_CT_SP1000;
1989 break;
1990 case SPEED_100:
1991 ctrl |= PHY_CT_SP100;
1992 break;
1993 }
1994
1995 ctrl |= PHY_CT_RESET;
1996 }
1997
c506a509 1998 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1999
6b0c1480
SH		 2000 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2001 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 2002
baef58b1
SH		 2003 /* Enable phy interrupt on autonegotiation complete (or link up) */
2004 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 2005 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 2006 else
4cde06ed 2007 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2008}
2009
2010static void yukon_reset(struct skge_hw *hw, int port)
2011{
6b0c1480
SH		 2012 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2013 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2014 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2015 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2016 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 2017
6b0c1480
SH		 2018 gma_write16(hw, port, GM_RX_CTRL,
2019 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 2020 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2021}
2022
c8868611
SH		 2023/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2024static int is_yukon_lite_a0(struct skge_hw *hw)
2025{
2026 u32 reg;
2027 int ret;
2028
2029 if (hw->chip_id != CHIP_ID_YUKON)
2030 return 0;
2031
2032 reg = skge_read32(hw, B2_FAR);
2033 skge_write8(hw, B2_FAR + 3, 0xff);
2034 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2035 skge_write32(hw, B2_FAR, reg);
2036 return ret;
2037}
2038
baef58b1
SH		 2039static void yukon_mac_init(struct skge_hw *hw, int port)
2040{
2041 struct skge_port *skge = netdev_priv(hw->dev[port]);
2042 int i;
2043 u32 reg;
2044 const u8 *addr = hw->dev[port]->dev_addr;
2045
2046 /* WA code for COMA mode -- set PHY reset */
2047 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2048 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2049 reg = skge_read32(hw, B2_GP_IO);
2050 reg |= GP_DIR_9 | GP_IO_9;
2051 skge_write32(hw, B2_GP_IO, reg);
2052 }
baef58b1
SH		 2053
2054 /* hard reset */
6b0c1480
SH		 2055 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2056 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2057
2058 /* WA code for COMA mode -- clear PHY reset */
2059 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2060 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2061 reg = skge_read32(hw, B2_GP_IO);
2062 reg |= GP_DIR_9;
2063 reg &= ~GP_IO_9;
2064 skge_write32(hw, B2_GP_IO, reg);
2065 }
baef58b1
SH		 2066
2067 /* Set hardware config mode */
2068 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2069 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2070 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2071
2072 /* Clear GMC reset */
6b0c1480
SH		 2073 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2074 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2075 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2076
baef58b1
SH		 2077 if (skge->autoneg == AUTONEG_DISABLE) {
2078 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2079 gma_write16(hw, port, GM_GP_CTRL,
2080 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2081
2082 switch (skge->speed) {
2083 case SPEED_1000:
564f9abb 2084 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2085 reg |= GM_GPCR_SPEED_1000;
564f9abb 2086 break;
baef58b1 2087 case SPEED_100:
564f9abb 2088 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2089 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2090 break;
2091 case SPEED_10:
2092 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2093 break;
baef58b1
SH		 2094 }
2095
2096 if (skge->duplex == DUPLEX_FULL)
2097 reg |= GM_GPCR_DUP_FULL;
2098 } else
2099 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2100
baef58b1
SH		 2101 switch (skge->flow_control) {
2102 case FLOW_MODE_NONE:
6b0c1480 2103 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2104 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2105 break;
2106 case FLOW_MODE_LOC_SEND:
2107 /* disable Rx flow-control */
2108 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2109 break;
2110 case FLOW_MODE_SYMMETRIC:
2111 case FLOW_MODE_SYM_OR_REM:
2112 /* enable Tx & Rx flow-control */
2113 break;
baef58b1
SH		 2114 }
2115
6b0c1480 2116 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2117 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2118
baef58b1 2119 yukon_init(hw, port);
baef58b1
SH		 2120
2121 /* MIB clear */
6b0c1480
SH		 2122 reg = gma_read16(hw, port, GM_PHY_ADDR);
2123 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2124
2125 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2126 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2127 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2128
2129 /* transmit control */
6b0c1480 2130 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2131
2132 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2133 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2134 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2135
2136 /* transmit flow control */
6b0c1480 2137 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2138
2139 /* transmit parameter */
6b0c1480 2140 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2141 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2142 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2143 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2144
44c7fcce
SH		 2145 /* configure the Serial Mode Register */
2146 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2147 | GM_SMOD_VLAN_ENA
2148 | IPG_DATA_VAL(IPG_DATA_DEF);
2149
2150 if (hw->dev[port]->mtu > ETH_DATA_LEN)
baef58b1
SH		 2151 reg |= GM_SMOD_JUMBO_ENA;
2152
6b0c1480 2153 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2154
2155 /* physical address: used for pause frames */
6b0c1480 2156 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2157 /* virtual address for data */
6b0c1480 2158 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2159
2160 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2161 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2162 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2163 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2164
2165 /* Initialize Mac Fifo */
2166
2167 /* Configure Rx MAC FIFO */
6b0c1480 2168 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2169 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2170
2171 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2172 if (is_yukon_lite_a0(hw))
baef58b1 2173 reg &= ~GMF_RX_F_FL_ON;
c8868611 2174
6b0c1480
SH		 2175 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2176 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2177 /*
2178 * because Pause Packet Truncation in GMAC is not working
2179 * we have to increase the Flush Threshold to 64 bytes
2180 * in order to flush pause packets in Rx FIFO on Yukon-1
2181 */
2182 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2183
2184 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2185 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2186 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2187}
2188
355ec572
SH		 2189/* Go into power down mode */
2190static void yukon_suspend(struct skge_hw *hw, int port)
2191{
2192 u16 ctrl;
2193
2194 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2195 ctrl |= PHY_M_PC_POL_R_DIS;
2196 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2197
2198 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2199 ctrl |= PHY_CT_RESET;
2200 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2201
2202 /* switch IEEE compatible power down mode on */
2203 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2204 ctrl |= PHY_CT_PDOWN;
2205 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2206}
2207
baef58b1
SH		 2208static void yukon_stop(struct skge_port *skge)
2209{
2210 struct skge_hw *hw = skge->hw;
2211 int port = skge->port;
2212
46a60f2d
SH		 2213 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2214 yukon_reset(hw, port);
baef58b1 2215
6b0c1480
SH		 2216 gma_write16(hw, port, GM_GP_CTRL,
2217 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2218 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2219 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2220
355ec572 2221 yukon_suspend(hw, port);
46a60f2d 2222
baef58b1 2223 /* set GPHY Control reset */
46a60f2d
SH		 2224 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2225 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2226}
2227
2228static void yukon_get_stats(struct skge_port *skge, u64 *data)
2229{
2230 struct skge_hw *hw = skge->hw;
2231 int port = skge->port;
2232 int i;
2233
6b0c1480
SH		 2234 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2235 | gma_read32(hw, port, GM_TXO_OK_LO);
2236 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2237 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2238
2239 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2240 data[i] = gma_read32(hw, port,
baef58b1
SH		 2241 skge_stats[i].gma_offset);
2242}
2243
2244static void yukon_mac_intr(struct skge_hw *hw, int port)
2245{
7e676d91
SH		 2246 struct net_device *dev = hw->dev[port];
2247 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2248 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2249
d707204c
JP		 2250 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2251 "mac interrupt status 0x%x\n", status);
7e676d91 2252
baef58b1 2253 if (status & GM_IS_RX_FF_OR) {
da00772f 2254 ++dev->stats.rx_fifo_errors;
d8a09943 2255 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2256 }
d8a09943 2257
baef58b1 2258 if (status & GM_IS_TX_FF_UR) {
da00772f 2259 ++dev->stats.tx_fifo_errors;
d8a09943 2260 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2261 }
2262
2263}
2264
2265static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2266{
95566065 2267 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2268 case PHY_M_PS_SPEED_1000:
2269 return SPEED_1000;
2270 case PHY_M_PS_SPEED_100:
2271 return SPEED_100;
2272 default:
2273 return SPEED_10;
2274 }
2275}
2276
2277static void yukon_link_up(struct skge_port *skge)
2278{
2279 struct skge_hw *hw = skge->hw;
2280 int port = skge->port;
2281 u16 reg;
2282
baef58b1 2283 /* Enable Transmit FIFO Underrun */
46a60f2d 2284 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2285
6b0c1480 2286 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2287 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2288 reg |= GM_GPCR_DUP_FULL;
2289
2290 /* enable Rx/Tx */
2291 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2292 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2293
4cde06ed 2294 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2295 skge_link_up(skge);
2296}
2297
2298static void yukon_link_down(struct skge_port *skge)
2299{
2300 struct skge_hw *hw = skge->hw;
2301 int port = skge->port;
d8a09943 2302 u16 ctrl;
baef58b1 2303
d8a09943
SH		 2304 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2305 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2306 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2307
5d5c8e03
SH		 2308 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2309 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2310 ctrl |= PHY_M_AN_ASP;
baef58b1 2311 /* restore Asymmetric Pause bit */
5d5c8e03 2312 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2313 }
2314
baef58b1
SH		 2315 skge_link_down(skge);
2316
2317 yukon_init(hw, port);
2318}
2319
2320static void yukon_phy_intr(struct skge_port *skge)
2321{
2322 struct skge_hw *hw = skge->hw;
2323 int port = skge->port;
2324 const char *reason = NULL;
2325 u16 istatus, phystat;
2326
6b0c1480
SH		 2327 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2328 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91 2329
d707204c
JP		 2330 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2331 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
baef58b1
SH		 2332
2333 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2334 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2335 & PHY_M_AN_RF) {
2336 reason = "remote fault";
2337 goto failed;
2338 }
2339
c506a509 2340 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2341 reason = "master/slave fault";
2342 goto failed;
2343 }
2344
2345 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2346 reason = "speed/duplex";
2347 goto failed;
2348 }
2349
2350 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2351 ? DUPLEX_FULL : DUPLEX_HALF;
2352 skge->speed = yukon_speed(hw, phystat);
2353
baef58b1
SH		 2354 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2355 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2356 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2357 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2358 break;
2359 case PHY_M_PS_RX_P_EN:
5d5c8e03 2360 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2361 break;
2362 case PHY_M_PS_TX_P_EN:
5d5c8e03 2363 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2364 break;
2365 default:
5d5c8e03 2366 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2367 }
2368
5d5c8e03 2369 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2370 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2371 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2372 else
6b0c1480 2373 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2374 yukon_link_up(skge);
2375 return;
2376 }
2377
2378 if (istatus & PHY_M_IS_LSP_CHANGE)
2379 skge->speed = yukon_speed(hw, phystat);
2380
2381 if (istatus & PHY_M_IS_DUP_CHANGE)
2382 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2383 if (istatus & PHY_M_IS_LST_CHANGE) {
2384 if (phystat & PHY_M_PS_LINK_UP)
2385 yukon_link_up(skge);
2386 else
2387 yukon_link_down(skge);
2388 }
2389 return;
2390 failed:
f15063cd 2391 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
baef58b1
SH		 2392
2393 /* XXX restart autonegotiation? */
2394}
2395
ee294dcd
SH		 2396static void skge_phy_reset(struct skge_port *skge)
2397{
2398 struct skge_hw *hw = skge->hw;
2399 int port = skge->port;
aae343d4 2400 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2401
2402 netif_stop_queue(skge->netdev);
2403 netif_carrier_off(skge->netdev);
2404
9cbe330f 2405 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2406 if (hw->chip_id == CHIP_ID_GENESIS) {
2407 genesis_reset(hw, port);
2408 genesis_mac_init(hw, port);
2409 } else {
2410 yukon_reset(hw, port);
2411 yukon_init(hw, port);
2412 }
9cbe330f 2413 spin_unlock_bh(&hw->phy_lock);
75814090 2414
f80d032b 2415 skge_set_multicast(dev);
ee294dcd
SH		 2416}
2417
2cd8e5d3
SH		 2418/* Basic MII support */
2419static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2420{
2421 struct mii_ioctl_data *data = if_mii(ifr);
2422 struct skge_port *skge = netdev_priv(dev);
2423 struct skge_hw *hw = skge->hw;
2424 int err = -EOPNOTSUPP;
2425
2426 if (!netif_running(dev))
2427 return -ENODEV; /* Phy still in reset */
2428
67777f9b 2429 switch (cmd) {
2cd8e5d3
SH		 2430 case SIOCGMIIPHY:
2431 data->phy_id = hw->phy_addr;
2432
2433 /* fallthru */
2434 case SIOCGMIIREG: {
2435 u16 val = 0;
9cbe330f 2436 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2437 if (hw->chip_id == CHIP_ID_GENESIS)
2438 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2439 else
2440 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2441 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2442 data->val_out = val;
2443 break;
2444 }
2445
2446 case SIOCSMIIREG:
9cbe330f 2447 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2448 if (hw->chip_id == CHIP_ID_GENESIS)
2449 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2450 data->val_in);
2451 else
2452 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2453 data->val_in);
9cbe330f 2454 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2455 break;
2456 }
2457 return err;
2458}
2459
279e1dab 2460static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
baef58b1
SH		 2461{
2462 u32 end;
2463
279e1dab
LT		 2464 start /= 8;
2465 len /= 8;
2466 end = start + len - 1;
baef58b1
SH		 2467
2468 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2469 skge_write32(hw, RB_ADDR(q, RB_START), start);
2470 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2471 skge_write32(hw, RB_ADDR(q, RB_RP), start);
279e1dab 2472 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2473
2474 if (q == Q_R1 || q == Q_R2) {
2475 /* Set thresholds on receive queue's */
279e1dab
LT		 2476 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2477 start + (2*len)/3);
2478 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2479 start + (len/3));
2480 } else {
2481 /* Enable store & forward on Tx queue's because
2482 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2483 */
baef58b1 2484 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
279e1dab 2485 }
baef58b1
SH		 2486
2487 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2488}
2489
2490/* Setup Bus Memory Interface */
2491static void skge_qset(struct skge_port *skge, u16 q,
2492 const struct skge_element *e)
2493{
2494 struct skge_hw *hw = skge->hw;
2495 u32 watermark = 0x600;
2496 u64 base = skge->dma + (e->desc - skge->mem);
2497
2498 /* optimization to reduce window on 32bit/33mhz */
2499 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2500 watermark /= 2;
2501
2502 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2503 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2504 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2505 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2506}
2507
2508static int skge_up(struct net_device *dev)
2509{
2510 struct skge_port *skge = netdev_priv(dev);
2511 struct skge_hw *hw = skge->hw;
2512 int port = skge->port;
279e1dab 2513 u32 chunk, ram_addr;
baef58b1
SH		 2514 size_t rx_size, tx_size;
2515 int err;
2516
fae87592
SH		 2517 if (!is_valid_ether_addr(dev->dev_addr))
2518 return -EINVAL;
2519
d707204c 2520 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
baef58b1 2521
19a33d4e 2522 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2523 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2524 else
2525 skge->rx_buf_size = RX_BUF_SIZE;
2526
2527
baef58b1
SH		 2528 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2529 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2530 skge->mem_size = tx_size + rx_size;
2531 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2532 if (!skge->mem)
2533 return -ENOMEM;
2534
c3da1447
SH		 2535 BUG_ON(skge->dma & 7);
2536
2537 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2538 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2539 err = -EINVAL;
2540 goto free_pci_mem;
2541 }
2542
baef58b1
SH		 2543 memset(skge->mem, 0, skge->mem_size);
2544
203babb6
SH		 2545 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2546 if (err)
baef58b1
SH		 2547 goto free_pci_mem;
2548
c54f9765 2549 err = skge_rx_fill(dev);
19a33d4e 2550 if (err)
baef58b1
SH		 2551 goto free_rx_ring;
2552
203babb6
SH		 2553 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2554 skge->dma + rx_size);
2555 if (err)
baef58b1
SH		 2556 goto free_rx_ring;
2557
8f3f8193 2558 /* Initialize MAC */
9cbe330f 2559 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2560 if (hw->chip_id == CHIP_ID_GENESIS)
2561 genesis_mac_init(hw, port);
2562 else
2563 yukon_mac_init(hw, port);
9cbe330f 2564 spin_unlock_bh(&hw->phy_lock);
baef58b1 2565
29816d9a
SH		 2566 /* Configure RAMbuffers - equally between ports and tx/rx */
2567 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
279e1dab 2568 ram_addr = hw->ram_offset + 2 * chunk * port;
baef58b1 2569
279e1dab 2570 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
7fb7ac24 2571 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
279e1dab 2572
baef58b1 2573 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
279e1dab 2574 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
baef58b1
SH		 2575 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2576
2577 /* Start receiver BMU */
2578 wmb();
2579 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2580 skge_led(skge, LED_MODE_ON);
baef58b1 2581
4ebabfcb
SH		 2582 spin_lock_irq(&hw->hw_lock);
2583 hw->intr_mask |= portmask[port];
2584 skge_write32(hw, B0_IMSK, hw->intr_mask);
2585 spin_unlock_irq(&hw->hw_lock);
2586
bea3348e 2587 napi_enable(&skge->napi);
baef58b1
SH		 2588 return 0;
2589
2590 free_rx_ring:
2591 skge_rx_clean(skge);
2592 kfree(skge->rx_ring.start);
2593 free_pci_mem:
2594 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2595 skge->mem = NULL;
baef58b1
SH		 2596
2597 return err;
2598}
2599
60b24b51
SH		 2600/* stop receiver */
2601static void skge_rx_stop(struct skge_hw *hw, int port)
2602{
2603 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2604 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2605 RB_RST_SET|RB_DIS_OP_MD);
2606 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2607}
2608
baef58b1
SH		 2609static int skge_down(struct net_device *dev)
2610{
2611 struct skge_port *skge = netdev_priv(dev);
2612 struct skge_hw *hw = skge->hw;
2613 int port = skge->port;
2614
7731a4ea
SH		 2615 if (skge->mem == NULL)
2616 return 0;
2617
d707204c 2618 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
baef58b1 2619
d119b392 2620 netif_tx_disable(dev);
692412b3 2621
64f6b64d 2622 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2623 del_timer_sync(&skge->link_timer);
baef58b1 2624
bea3348e 2625 napi_disable(&skge->napi);
692412b3 2626 netif_carrier_off(dev);
4ebabfcb
SH		 2627
2628 spin_lock_irq(&hw->hw_lock);
2629 hw->intr_mask &= ~portmask[port];
2630 skge_write32(hw, B0_IMSK, hw->intr_mask);
2631 spin_unlock_irq(&hw->hw_lock);
2632
46a60f2d
SH		 2633 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2634 if (hw->chip_id == CHIP_ID_GENESIS)
2635 genesis_stop(skge);
2636 else
2637 yukon_stop(skge);
2638
baef58b1
SH		 2639 /* Stop transmitter */
2640 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2641 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2642 RB_RST_SET|RB_DIS_OP_MD);
2643
baef58b1
SH		 2644
2645 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2646 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2647 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2648
2649 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2650 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2651 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2652
2653 /* Reset PCI FIFO */
2654 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2655 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2656
2657 /* Reset the RAM Buffer async Tx queue */
2658 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2659
2660 skge_rx_stop(hw, port);
baef58b1
SH		 2661
2662 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2663 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2664 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2665 } else {
6b0c1480
SH		 2666 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2667 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2668 }
2669
6abebb53 2670 skge_led(skge, LED_MODE_OFF);
baef58b1 2671
e3a1b99f 2672 netif_tx_lock_bh(dev);
513f533e 2673 skge_tx_clean(dev);
e3a1b99f
SH		 2674 netif_tx_unlock_bh(dev);
2675
baef58b1
SH		 2676 skge_rx_clean(skge);
2677
2678 kfree(skge->rx_ring.start);
2679 kfree(skge->tx_ring.start);
2680 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2681 skge->mem = NULL;
baef58b1
SH		 2682 return 0;
2683}
2684
29b4e886
SH		 2685static inline int skge_avail(const struct skge_ring *ring)
2686{
992c9623 2687 smp_mb();
29b4e886
SH		 2688 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2689 + (ring->to_clean - ring->to_use) - 1;
2690}
2691
61357325
SH		 2692static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2693 struct net_device *dev)
baef58b1
SH		 2694{
2695 struct skge_port *skge = netdev_priv(dev);
2696 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2697 struct skge_element *e;
2698 struct skge_tx_desc *td;
2699 int i;
2700 u32 control, len;
2701 u64 map;
baef58b1 2702
5b057c6b 2703 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2704 return NETDEV_TX_OK;
2705
513f533e 2706 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2707 return NETDEV_TX_BUSY;
baef58b1 2708
7c442fa1 2709 e = skge->tx_ring.to_use;
baef58b1 2710 td = e->desc;
7c442fa1 2711 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2712 e->skb = skb;
2713 len = skb_headlen(skb);
2714 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
10fc51b9
FT		 2715 dma_unmap_addr_set(e, mapaddr, map);
2716 dma_unmap_len_set(e, maplen, len);
baef58b1
SH		 2717
2718 td->dma_lo = map;
2719 td->dma_hi = map >> 32;
2720
84fa7933 2721 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 2722 const int offset = skb_checksum_start_offset(skb);
baef58b1
SH		 2723
2724 /* This seems backwards, but it is what the sk98lin
2725 * does. Looks like hardware is wrong?
2726 */
8e95a202 2727 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
67777f9b 2728 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2729 control = BMU_TCP_CHECK;
2730 else
2731 control = BMU_UDP_CHECK;
2732
2733 td->csum_offs = 0;
2734 td->csum_start = offset;
ff1dcadb 2735 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2736 } else
2737 control = BMU_CHECK;
2738
2739 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
67777f9b 2740 control |= BMU_EOF | BMU_IRQ_EOF;
baef58b1
SH		 2741 else {
2742 struct skge_tx_desc *tf = td;
2743
2744 control |= BMU_STFWD;
2745 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2746 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2747
2748 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2749 frag->size, PCI_DMA_TODEVICE);
2750
2751 e = e->next;
7c442fa1 2752 e->skb = skb;
baef58b1 2753 tf = e->desc;
7c442fa1
SH		 2754 BUG_ON(tf->control & BMU_OWN);
2755
baef58b1
SH		 2756 tf->dma_lo = map;
2757 tf->dma_hi = (u64) map >> 32;
10fc51b9
FT		 2758 dma_unmap_addr_set(e, mapaddr, map);
2759 dma_unmap_len_set(e, maplen, frag->size);
baef58b1
SH		 2760
2761 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2762 }
2763 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2764 }
2765 /* Make sure all the descriptors written */
2766 wmb();
2767 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2768 wmb();
2769
2770 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2771
d707204c
JP		 2772 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2773 "tx queued, slot %td, len %d\n",
2774 e - skge->tx_ring.start, skb->len);
baef58b1 2775
7c442fa1 2776 skge->tx_ring.to_use = e->next;
992c9623
SH		 2777 smp_wmb();
2778
9db96479 2779 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
f15063cd 2780 netdev_dbg(dev, "transmit queue full\n");
baef58b1
SH		 2781 netif_stop_queue(dev);
2782 }
2783
baef58b1
SH		 2784 return NETDEV_TX_OK;
2785}
2786
7c442fa1
SH		 2787
2788/* Free resources associated with this reing element */
2789static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2790 u32 control)
866b4f3e
SH		 2791{
2792 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2793
7c442fa1
SH		 2794 /* skb header vs. fragment */
2795 if (control & BMU_STF)
10fc51b9
FT		 2796 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2797 dma_unmap_len(e, maplen),
7c442fa1
SH		 2798 PCI_DMA_TODEVICE);
2799 else
10fc51b9
FT		 2800 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2801 dma_unmap_len(e, maplen),
7c442fa1 2802 PCI_DMA_TODEVICE);
866b4f3e 2803
7c442fa1 2804 if (control & BMU_EOF) {
d707204c
JP		 2805 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2806 "tx done slot %td\n", e - skge->tx_ring.start);
866b4f3e 2807
513f533e 2808 dev_kfree_skb(e->skb);
baef58b1
SH		 2809 }
2810}
2811
7c442fa1 2812/* Free all buffers in transmit ring */
513f533e 2813static void skge_tx_clean(struct net_device *dev)
baef58b1 2814{
513f533e 2815 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2816 struct skge_element *e;
baef58b1 2817
7c442fa1
SH		 2818 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2819 struct skge_tx_desc *td = e->desc;
2820 skge_tx_free(skge, e, td->control);
2821 td->control = 0;
2822 }
2823
2824 skge->tx_ring.to_clean = e;
baef58b1
SH		 2825}
2826
2827static void skge_tx_timeout(struct net_device *dev)
2828{
2829 struct skge_port *skge = netdev_priv(dev);
2830
d707204c 2831 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
baef58b1
SH		 2832
2833 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2834 skge_tx_clean(dev);
d119b392 2835 netif_wake_queue(dev);
baef58b1
SH		 2836}
2837
2838static int skge_change_mtu(struct net_device *dev, int new_mtu)
2839{
7731a4ea 2840 int err;
baef58b1 2841
95566065 2842 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2843 return -EINVAL;
2844
7731a4ea
SH		 2845 if (!netif_running(dev)) {
2846 dev->mtu = new_mtu;
2847 return 0;
2848 }
2849
1a8098be 2850 skge_down(dev);
baef58b1 2851
19a33d4e 2852 dev->mtu = new_mtu;
7731a4ea 2853
1a8098be 2854 err = skge_up(dev);
7731a4ea
SH		 2855 if (err)
2856 dev_close(dev);
baef58b1
SH		 2857
2858 return err;
2859}
2860
c4cd29d2
SH		 2861static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2862
2863static void genesis_add_filter(u8 filter[8], const u8 *addr)
2864{
2865 u32 crc, bit;
2866
2867 crc = ether_crc_le(ETH_ALEN, addr);
2868 bit = ~crc & 0x3f;
2869 filter[bit/8] |= 1 << (bit%8);
2870}
2871
baef58b1
SH		 2872static void genesis_set_multicast(struct net_device *dev)
2873{
2874 struct skge_port *skge = netdev_priv(dev);
2875 struct skge_hw *hw = skge->hw;
2876 int port = skge->port;
22bedad3 2877 struct netdev_hw_addr *ha;
baef58b1
SH		 2878 u32 mode;
2879 u8 filter[8];
2880
6b0c1480 2881 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2882 mode |= XM_MD_ENA_HASH;
2883 if (dev->flags & IFF_PROMISC)
2884 mode |= XM_MD_ENA_PROM;
2885 else
2886 mode &= ~XM_MD_ENA_PROM;
2887
2888 if (dev->flags & IFF_ALLMULTI)
2889 memset(filter, 0xff, sizeof(filter));
2890 else {
2891 memset(filter, 0, sizeof(filter));
c4cd29d2 2892
8e95a202
JP		 2893 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2894 skge->flow_status == FLOW_STAT_SYMMETRIC)
c4cd29d2
SH		 2895 genesis_add_filter(filter, pause_mc_addr);
2896
22bedad3
JP		 2897 netdev_for_each_mc_addr(ha, dev)
2898 genesis_add_filter(filter, ha->addr);
baef58b1
SH		 2899 }
2900
6b0c1480 2901 xm_write32(hw, port, XM_MODE, mode);
45bada65 2902 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2903}
2904
c4cd29d2
SH		 2905static void yukon_add_filter(u8 filter[8], const u8 *addr)
2906{
2907 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2908 filter[bit/8] |= 1 << (bit%8);
2909}
2910
baef58b1
SH		 2911static void yukon_set_multicast(struct net_device *dev)
2912{
2913 struct skge_port *skge = netdev_priv(dev);
2914 struct skge_hw *hw = skge->hw;
2915 int port = skge->port;
22bedad3 2916 struct netdev_hw_addr *ha;
8e95a202
JP		 2917 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2918 skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2919 u16 reg;
2920 u8 filter[8];
2921
2922 memset(filter, 0, sizeof(filter));
2923
6b0c1480 2924 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2925 reg |= GM_RXCR_UCF_ENA;
2926
8f3f8193 2927 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2928 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2929 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2930 memset(filter, 0xff, sizeof(filter));
4cd24eaf 2931 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
baef58b1
SH		 2932 reg &= ~GM_RXCR_MCF_ENA;
2933 else {
baef58b1
SH		 2934 reg |= GM_RXCR_MCF_ENA;
2935
c4cd29d2
SH		 2936 if (rx_pause)
2937 yukon_add_filter(filter, pause_mc_addr);
2938
22bedad3
JP		 2939 netdev_for_each_mc_addr(ha, dev)
2940 yukon_add_filter(filter, ha->addr);
baef58b1
SH		 2941 }
2942
2943
6b0c1480 2944 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2945 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2946 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2947 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2948 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2949 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2950 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2951 (u16)filter[6] | ((u16)filter[7] << 8));
2952
6b0c1480 2953 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2954}
2955
383181ac
SH		 2956static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2957{
2958 if (hw->chip_id == CHIP_ID_GENESIS)
2959 return status >> XMR_FS_LEN_SHIFT;
2960 else
2961 return status >> GMR_FS_LEN_SHIFT;
2962}
2963
baef58b1
SH		 2964static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2965{
2966 if (hw->chip_id == CHIP_ID_GENESIS)
2967 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2968 else
2969 return (status & GMR_FS_ANY_ERR) ||
2970 (status & GMR_FS_RX_OK) == 0;
2971}
2972
f80d032b
SH		 2973static void skge_set_multicast(struct net_device *dev)
2974{
2975 struct skge_port *skge = netdev_priv(dev);
2976 struct skge_hw *hw = skge->hw;
2977
2978 if (hw->chip_id == CHIP_ID_GENESIS)
2979 genesis_set_multicast(dev);
2980 else
2981 yukon_set_multicast(dev);
2982
2983}
2984
19a33d4e
SH		 2985
2986/* Get receive buffer from descriptor.
2987 * Handles copy of small buffers and reallocation failures
2988 */
c54f9765
SH		 2989static struct sk_buff *skge_rx_get(struct net_device *dev,
2990 struct skge_element *e,
2991 u32 control, u32 status, u16 csum)
19a33d4e 2992{
c54f9765 2993 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 2994 struct sk_buff *skb;
2995 u16 len = control & BMU_BBC;
2996
d707204c
JP		 2997 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
2998 "rx slot %td status 0x%x len %d\n",
2999 e - skge->rx_ring.start, status, len);
383181ac
SH		 3000
3001 if (len > skge->rx_buf_size)
3002 goto error;
3003
3004 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3005 goto error;
3006
3007 if (bad_phy_status(skge->hw, status))
3008 goto error;
3009
3010 if (phy_length(skge->hw, status) != len)
3011 goto error;
19a33d4e
SH		 3012
3013 if (len < RX_COPY_THRESHOLD) {
89d71a66 3014 skb = netdev_alloc_skb_ip_align(dev, len);
383181ac
SH		 3015 if (!skb)
3016 goto resubmit;
19a33d4e
SH		 3017
3018 pci_dma_sync_single_for_cpu(skge->hw->pdev,
10fc51b9 3019 dma_unmap_addr(e, mapaddr),
19a33d4e 3020 len, PCI_DMA_FROMDEVICE);
d626f62b 3021 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e 3022 pci_dma_sync_single_for_device(skge->hw->pdev,
10fc51b9 3023 dma_unmap_addr(e, mapaddr),
19a33d4e 3024 len, PCI_DMA_FROMDEVICE);
19a33d4e 3025 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3026 } else {
383181ac 3027 struct sk_buff *nskb;
89d71a66
ED		 3028
3029 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
383181ac
SH		 3030 if (!nskb)
3031 goto resubmit;
19a33d4e
SH		 3032
3033 pci_unmap_single(skge->hw->pdev,
10fc51b9
FT		 3034 dma_unmap_addr(e, mapaddr),
3035 dma_unmap_len(e, maplen),
19a33d4e
SH		 3036 PCI_DMA_FROMDEVICE);
3037 skb = e->skb;
67777f9b 3038 prefetch(skb->data);
19a33d4e 3039 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3040 }
383181ac
SH		 3041
3042 skb_put(skb, len);
e92702b1
MM		 3043
3044 if (dev->features & NETIF_F_RXCSUM) {
383181ac 3045 skb->csum = csum;
84fa7933 3046 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3047 }
3048
c54f9765 3049 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3050
3051 return skb;
3052error:
3053
d707204c
JP		 3054 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3055 "rx err, slot %td control 0x%x status 0x%x\n",
3056 e - skge->rx_ring.start, control, status);
383181ac
SH		 3057
3058 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3059 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
da00772f 3060 dev->stats.rx_length_errors++;
383181ac 3061 if (status & XMR_FS_FRA_ERR)
da00772f 3062 dev->stats.rx_frame_errors++;
383181ac 3063 if (status & XMR_FS_FCS_ERR)
da00772f 3064 dev->stats.rx_crc_errors++;
383181ac
SH		 3065 } else {
3066 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
da00772f 3067 dev->stats.rx_length_errors++;
383181ac 3068 if (status & GMR_FS_FRAGMENT)
da00772f 3069 dev->stats.rx_frame_errors++;
383181ac 3070 if (status & GMR_FS_CRC_ERR)
da00772f 3071 dev->stats.rx_crc_errors++;
383181ac
SH		 3072 }
3073
3074resubmit:
3075 skge_rx_reuse(e, skge->rx_buf_size);
3076 return NULL;
baef58b1
SH		 3077}
3078
7c442fa1 3079/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3080static void skge_tx_done(struct net_device *dev)
00a6cae2 3081{
7c442fa1 3082 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3083 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3084 struct skge_element *e;
3085
513f533e 3086 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3087
866b4f3e 3088 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3089 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3090
992c9623 3091 if (control & BMU_OWN)
00a6cae2
SH		 3092 break;
3093
992c9623 3094 skge_tx_free(skge, e, control);
00a6cae2 3095 }
7c442fa1 3096 skge->tx_ring.to_clean = e;
866b4f3e 3097
992c9623
SH		 3098 /* Can run lockless until we need to synchronize to restart queue. */
3099 smp_mb();
3100
3101 if (unlikely(netif_queue_stopped(dev) &&
3102 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3103 netif_tx_lock(dev);
3104 if (unlikely(netif_queue_stopped(dev) &&
3105 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3106 netif_wake_queue(dev);
00a6cae2 3107
992c9623
SH		 3108 }
3109 netif_tx_unlock(dev);
3110 }
00a6cae2 3111}
19a33d4e 3112
bea3348e 3113static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3114{
bea3348e
SH		 3115 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3116 struct net_device *dev = skge->netdev;
baef58b1
SH		 3117 struct skge_hw *hw = skge->hw;
3118 struct skge_ring *ring = &skge->rx_ring;
3119 struct skge_element *e;
00a6cae2
SH		 3120 int work_done = 0;
3121
513f533e
SH		 3122 skge_tx_done(dev);
3123
3124 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3125
1631aef1 3126 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3127 struct skge_rx_desc *rd = e->desc;
19a33d4e 3128 struct sk_buff *skb;
383181ac 3129 u32 control;
baef58b1
SH		 3130
3131 rmb();
3132 control = rd->control;
3133 if (control & BMU_OWN)
3134 break;
3135
c54f9765 3136 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3137 if (likely(skb)) {
86cac58b 3138 napi_gro_receive(napi, skb);
19a33d4e 3139 ++work_done;
5a011447 3140 }
baef58b1
SH		 3141 }
3142 ring->to_clean = e;
3143
baef58b1
SH		 3144 /* restart receiver */
3145 wmb();
a9cdab86 3146 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3147
bea3348e 3148 if (work_done < to_do) {
6ef2977d 3149 unsigned long flags;
f0c88f9c 3150
86cac58b 3151 napi_gro_flush(napi);
6ef2977d 3152 spin_lock_irqsave(&hw->hw_lock, flags);
288379f0 3153 __napi_complete(napi);
bea3348e
SH		 3154 hw->intr_mask |= napimask[skge->port];
3155 skge_write32(hw, B0_IMSK, hw->intr_mask);
3156 skge_read32(hw, B0_IMSK);
6ef2977d 3157 spin_unlock_irqrestore(&hw->hw_lock, flags);
bea3348e 3158 }
1631aef1 3159
bea3348e 3160 return work_done;
baef58b1
SH		 3161}
3162
f6620cab
SH		 3163/* Parity errors seem to happen when Genesis is connected to a switch
3164 * with no other ports present. Heartbeat error??
3165 */
baef58b1
SH		 3166static void skge_mac_parity(struct skge_hw *hw, int port)
3167{
f6620cab
SH		 3168 struct net_device *dev = hw->dev[port];
3169
da00772f 3170 ++dev->stats.tx_heartbeat_errors;
baef58b1
SH		 3171
3172 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3173 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3174 MFF_CLR_PERR);
3175 else
3176 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3177 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3178 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3179 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3180}
3181
baef58b1
SH		 3182static void skge_mac_intr(struct skge_hw *hw, int port)
3183{
95566065 3184 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3185 genesis_mac_intr(hw, port);
3186 else
3187 yukon_mac_intr(hw, port);
3188}
3189
3190/* Handle device specific framing and timeout interrupts */
3191static void skge_error_irq(struct skge_hw *hw)
3192{
1479d13c 3193 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3194 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3195
3196 if (hw->chip_id == CHIP_ID_GENESIS) {
3197 /* clear xmac errors */
3198 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3199 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3200 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3201 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3202 } else {
3203 /* Timestamp (unused) overflow */
3204 if (hwstatus & IS_IRQ_TIST_OV)
3205 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3206 }
3207
3208 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3209 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3210 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3211 }
3212
3213 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3214 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3215 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3216 }
3217
3218 if (hwstatus & IS_M1_PAR_ERR)
3219 skge_mac_parity(hw, 0);
3220
3221 if (hwstatus & IS_M2_PAR_ERR)
3222 skge_mac_parity(hw, 1);
3223
b9d64acc 3224 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3225 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3226 hw->dev[0]->name);
baef58b1 3227 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3228 }
baef58b1 3229
b9d64acc 3230 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3231 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3232 hw->dev[1]->name);
baef58b1 3233 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3234 }
baef58b1
SH		 3235
3236 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3237 u16 pci_status, pci_cmd;
3238
1479d13c
SH		 3239 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3240 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3241
1479d13c
SH		 3242 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3243 pci_cmd, pci_status);
b9d64acc
SH		 3244
3245 /* Write the error bits back to clear them. */
3246 pci_status &= PCI_STATUS_ERROR_BITS;
3247 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3248 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3249 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3250 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3251 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3252
050ec18a 3253 /* if error still set then just ignore it */
baef58b1
SH		 3254 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3255 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3256 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3257 hw->intr_mask &= ~IS_HW_ERR;
3258 }
3259 }
3260}
3261
3262/*
9cbe330f 3263 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3264 * because accessing phy registers requires spin wait which might
3265 * cause excess interrupt latency.
3266 */
9cbe330f 3267static void skge_extirq(unsigned long arg)
baef58b1 3268{
9cbe330f 3269 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3270 int port;
3271
cfc3ed79 3272 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3273 struct net_device *dev = hw->dev[port];
3274
cfc3ed79 3275 if (netif_running(dev)) {
9cbe330f
SH		 3276 struct skge_port *skge = netdev_priv(dev);
3277
3278 spin_lock(&hw->phy_lock);
baef58b1
SH		 3279 if (hw->chip_id != CHIP_ID_GENESIS)
3280 yukon_phy_intr(skge);
64f6b64d 3281 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3282 bcom_phy_intr(skge);
9cbe330f 3283 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3284 }
3285 }
baef58b1 3286
7c442fa1 3287 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3288 hw->intr_mask |= IS_EXT_REG;
3289 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3290 skge_read32(hw, B0_IMSK);
7c442fa1 3291 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3292}
3293
7d12e780 3294static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3295{
3296 struct skge_hw *hw = dev_id;
cfc3ed79 3297 u32 status;
29365c90 3298 int handled = 0;
baef58b1 3299
29365c90 3300 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3301 /* Reading this register masks IRQ */
3302 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3303 if (status == 0 || status == ~0)
29365c90 3304 goto out;
baef58b1 3305
29365c90 3306 handled = 1;
7c442fa1 3307 status &= hw->intr_mask;
cfc3ed79
SH		 3308 if (status & IS_EXT_REG) {
3309 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3310 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3311 }
3312
513f533e 3313 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3314 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3315 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
288379f0 3316 napi_schedule(&skge->napi);
baef58b1
SH		 3317 }
3318
7c442fa1
SH		 3319 if (status & IS_PA_TO_TX1)
3320 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3321
d25f5a67 3322 if (status & IS_PA_TO_RX1) {
da00772f 3323 ++hw->dev[0]->stats.rx_over_errors;
7c442fa1 3324 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3325 }
3326
d25f5a67 3327
baef58b1
SH		 3328 if (status & IS_MAC1)
3329 skge_mac_intr(hw, 0);
95566065 3330
7c442fa1 3331 if (hw->dev[1]) {
bea3348e
SH		 3332 struct skge_port *skge = netdev_priv(hw->dev[1]);
3333
513f533e
SH		 3334 if (status & (IS_XA2_F|IS_R2_F)) {
3335 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
288379f0 3336 napi_schedule(&skge->napi);
7c442fa1
SH		 3337 }
3338
3339 if (status & IS_PA_TO_RX2) {
da00772f 3340 ++hw->dev[1]->stats.rx_over_errors;
7c442fa1
SH		 3341 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3342 }
3343
3344 if (status & IS_PA_TO_TX2)
3345 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3346
3347 if (status & IS_MAC2)
3348 skge_mac_intr(hw, 1);
3349 }
baef58b1
SH		 3350
3351 if (status & IS_HW_ERR)
3352 skge_error_irq(hw);
3353
7e676d91 3354 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3355 skge_read32(hw, B0_IMSK);
29365c90 3356out:
7c442fa1 3357 spin_unlock(&hw->hw_lock);
baef58b1 3358
29365c90 3359 return IRQ_RETVAL(handled);
baef58b1
SH		 3360}
3361
3362#ifdef CONFIG_NET_POLL_CONTROLLER
3363static void skge_netpoll(struct net_device *dev)
3364{
3365 struct skge_port *skge = netdev_priv(dev);
3366
3367 disable_irq(dev->irq);
7d12e780 3368 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3369 enable_irq(dev->irq);
3370}
3371#endif
3372
3373static int skge_set_mac_address(struct net_device *dev, void *p)
3374{
3375 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3376 struct skge_hw *hw = skge->hw;
3377 unsigned port = skge->port;
3378 const struct sockaddr *addr = p;
2eb3e621 3379 u16 ctrl;
baef58b1
SH		 3380
3381 if (!is_valid_ether_addr(addr->sa_data))
3382 return -EADDRNOTAVAIL;
3383
baef58b1 3384 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3385
9cbe330f
SH		 3386 if (!netif_running(dev)) {
3387 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3388 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3389 } else {
3390 /* disable Rx */
3391 spin_lock_bh(&hw->phy_lock);
3392 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3393 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3394
9cbe330f
SH		 3395 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3396 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3397
2eb3e621
SH		 3398 if (hw->chip_id == CHIP_ID_GENESIS)
3399 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3400 else {
3401 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3402 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3403 }
2eb3e621 3404
9cbe330f
SH		 3405 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3406 spin_unlock_bh(&hw->phy_lock);
3407 }
c2681dd8
SH		 3408
3409 return 0;
baef58b1
SH		 3410}
3411
3412static const struct {
3413 u8 id;
3414 const char *name;
3415} skge_chips[] = {
3416 { CHIP_ID_GENESIS, "Genesis" },
3417 { CHIP_ID_YUKON, "Yukon" },
3418 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3419 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3420};
3421
3422static const char *skge_board_name(const struct skge_hw *hw)
3423{
3424 int i;
3425 static char buf[16];
3426
3427 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3428 if (skge_chips[i].id == hw->chip_id)
3429 return skge_chips[i].name;
3430
3431 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3432 return buf;
3433}
3434
3435
3436/*
3437 * Setup the board data structure, but don't bring up
3438 * the port(s)
3439 */
3440static int skge_reset(struct skge_hw *hw)
3441{
adba9e23 3442 u32 reg;
b9d64acc 3443 u16 ctst, pci_status;
64f6b64d 3444 u8 t8, mac_cfg, pmd_type;
981d0377 3445 int i;
baef58b1
SH		 3446
3447 ctst = skge_read16(hw, B0_CTST);
3448
3449 /* do a SW reset */
3450 skge_write8(hw, B0_CTST, CS_RST_SET);
3451 skge_write8(hw, B0_CTST, CS_RST_CLR);
3452
3453 /* clear PCI errors, if any */
b9d64acc
SH		 3454 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3455 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3456
b9d64acc
SH		 3457 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3458 pci_write_config_word(hw->pdev, PCI_STATUS,
3459 pci_status | PCI_STATUS_ERROR_BITS);
3460 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3461 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3462
3463 /* restore CLK_RUN bits (for Yukon-Lite) */
3464 skge_write16(hw, B0_CTST,
3465 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3466
3467 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3468 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3469 pmd_type = skge_read8(hw, B2_PMD_TYP);
3470 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3471
95566065 3472 switch (hw->chip_id) {
baef58b1 3473 case CHIP_ID_GENESIS:
64f6b64d
SH		 3474 switch (hw->phy_type) {
3475 case SK_PHY_XMAC:
3476 hw->phy_addr = PHY_ADDR_XMAC;
3477 break;
baef58b1
SH		 3478 case SK_PHY_BCOM:
3479 hw->phy_addr = PHY_ADDR_BCOM;
3480 break;
3481 default:
1479d13c
SH		 3482 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3483 hw->phy_type);
baef58b1
SH		 3484 return -EOPNOTSUPP;
3485 }
3486 break;
3487
3488 case CHIP_ID_YUKON:
3489 case CHIP_ID_YUKON_LITE:
3490 case CHIP_ID_YUKON_LP:
64f6b64d 3491 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3492 hw->copper = 1;
baef58b1
SH		 3493
3494 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3495 break;
3496
3497 default:
1479d13c
SH		 3498 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3499 hw->chip_id);
baef58b1
SH		 3500 return -EOPNOTSUPP;
3501 }
3502
981d0377
SH		 3503 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3504 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3505 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3506
3507 /* read the adapters RAM size */
3508 t8 = skge_read8(hw, B2_E_0);
3509 if (hw->chip_id == CHIP_ID_GENESIS) {
3510 if (t8 == 3) {
3511 /* special case: 4 x 64k x 36, offset = 0x80000 */
279e1dab
LT		 3512 hw->ram_size = 0x100000;
3513 hw->ram_offset = 0x80000;
baef58b1
SH		 3514 } else
3515 hw->ram_size = t8 * 512;
67777f9b 3516 } else if (t8 == 0)
279e1dab
LT		 3517 hw->ram_size = 0x20000;
3518 else
3519 hw->ram_size = t8 * 4096;
baef58b1 3520
4ebabfcb 3521 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3522
4ebabfcb 3523 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3524 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3525 hw->intr_mask |= IS_EXT_REG;
3526
baef58b1
SH		 3527 if (hw->chip_id == CHIP_ID_GENESIS)
3528 genesis_init(hw);
3529 else {
3530 /* switch power to VCC (WA for VAUX problem) */
3531 skge_write8(hw, B0_POWER_CTRL,
3532 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3533
050ec18a
SH		 3534 /* avoid boards with stuck Hardware error bits */
3535 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3536 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3537 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3538 hw->intr_mask &= ~IS_HW_ERR;
3539 }
3540
adba9e23
SH		 3541 /* Clear PHY COMA */
3542 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3543 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3544 reg &= ~PCI_PHY_COMA;
3545 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3546 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3547
3548
981d0377 3549 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3550 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3551 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3552 }
3553 }
3554
3555 /* turn off hardware timer (unused) */
3556 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3557 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3558 skge_write8(hw, B0_LED, LED_STAT_ON);
3559
3560 /* enable the Tx Arbiters */
981d0377 3561 for (i = 0; i < hw->ports; i++)
6b0c1480 3562 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3563
3564 /* Initialize ram interface */
3565 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3566
3567 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3568 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3569 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3570 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3571 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3572 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3573 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3574 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3575 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3576 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3577 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3578 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3579
3580 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3581
3582 /* Set interrupt moderation for Transmit only
3583 * Receive interrupts avoided by NAPI
3584 */
3585 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3586 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3587 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3588
baef58b1
SH		 3589 skge_write32(hw, B0_IMSK, hw->intr_mask);
3590
981d0377 3591 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3592 if (hw->chip_id == CHIP_ID_GENESIS)
3593 genesis_reset(hw, i);
3594 else
3595 yukon_reset(hw, i);
3596 }
baef58b1
SH		 3597
3598 return 0;
3599}
3600
678aa1f6
SH		 3601
3602#ifdef CONFIG_SKGE_DEBUG
3603
3604static struct dentry *skge_debug;
3605
3606static int skge_debug_show(struct seq_file *seq, void *v)
3607{
3608 struct net_device *dev = seq->private;
3609 const struct skge_port *skge = netdev_priv(dev);
3610 const struct skge_hw *hw = skge->hw;
3611 const struct skge_element *e;
3612
3613 if (!netif_running(dev))
3614 return -ENETDOWN;
3615
3616 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3617 skge_read32(hw, B0_IMSK));
3618
3619 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3620 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3621 const struct skge_tx_desc *t = e->desc;
3622 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3623 t->control, t->dma_hi, t->dma_lo, t->status,
3624 t->csum_offs, t->csum_write, t->csum_start);
3625 }
3626
2381a55c 3627 seq_printf(seq, "\nRx Ring:\n");
678aa1f6
SH		 3628 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3629 const struct skge_rx_desc *r = e->desc;
3630
3631 if (r->control & BMU_OWN)
3632 break;
3633
3634 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3635 r->control, r->dma_hi, r->dma_lo, r->status,
3636 r->timestamp, r->csum1, r->csum1_start);
3637 }
3638
3639 return 0;
3640}
3641
3642static int skge_debug_open(struct inode *inode, struct file *file)
3643{
3644 return single_open(file, skge_debug_show, inode->i_private);
3645}
3646
3647static const struct file_operations skge_debug_fops = {
3648 .owner = THIS_MODULE,
3649 .open = skge_debug_open,
3650 .read = seq_read,
3651 .llseek = seq_lseek,
3652 .release = single_release,
3653};
3654
3655/*
3656 * Use network device events to create/remove/rename
3657 * debugfs file entries
3658 */
3659static int skge_device_event(struct notifier_block *unused,
3660 unsigned long event, void *ptr)
3661{
3662 struct net_device *dev = ptr;
3663 struct skge_port *skge;
3664 struct dentry *d;
3665
f80d032b 3666 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
678aa1f6
SH		 3667 goto done;
3668
3669 skge = netdev_priv(dev);
67777f9b 3670 switch (event) {
678aa1f6
SH		 3671 case NETDEV_CHANGENAME:
3672 if (skge->debugfs) {
3673 d = debugfs_rename(skge_debug, skge->debugfs,
3674 skge_debug, dev->name);
3675 if (d)
3676 skge->debugfs = d;
3677 else {
f15063cd 3678 netdev_info(dev, "rename failed\n");
678aa1f6
SH		 3679 debugfs_remove(skge->debugfs);
3680 }
3681 }
3682 break;
3683
3684 case NETDEV_GOING_DOWN:
3685 if (skge->debugfs) {
3686 debugfs_remove(skge->debugfs);
3687 skge->debugfs = NULL;
3688 }
3689 break;
3690
3691 case NETDEV_UP:
3692 d = debugfs_create_file(dev->name, S_IRUGO,
3693 skge_debug, dev,
3694 &skge_debug_fops);
3695 if (!d || IS_ERR(d))
f15063cd 3696 netdev_info(dev, "debugfs create failed\n");
678aa1f6
SH		 3697 else
3698 skge->debugfs = d;
3699 break;
3700 }
3701
3702done:
3703 return NOTIFY_DONE;
3704}
3705
3706static struct notifier_block skge_notifier = {
3707 .notifier_call = skge_device_event,
3708};
3709
3710
3711static __init void skge_debug_init(void)
3712{
3713 struct dentry *ent;
3714
3715 ent = debugfs_create_dir("skge", NULL);
3716 if (!ent || IS_ERR(ent)) {
f15063cd 3717 pr_info("debugfs create directory failed\n");
678aa1f6
SH		 3718 return;
3719 }
3720
3721 skge_debug = ent;
3722 register_netdevice_notifier(&skge_notifier);
3723}
3724
3725static __exit void skge_debug_cleanup(void)
3726{
3727 if (skge_debug) {
3728 unregister_netdevice_notifier(&skge_notifier);
3729 debugfs_remove(skge_debug);
3730 skge_debug = NULL;
3731 }
3732}
3733
3734#else
3735#define skge_debug_init()
3736#define skge_debug_cleanup()
3737#endif
3738
f80d032b
SH		 3739static const struct net_device_ops skge_netdev_ops = {
3740 .ndo_open = skge_up,
3741 .ndo_stop = skge_down,
00829823 3742 .ndo_start_xmit = skge_xmit_frame,
f80d032b
SH		 3743 .ndo_do_ioctl = skge_ioctl,
3744 .ndo_get_stats = skge_get_stats,
3745 .ndo_tx_timeout = skge_tx_timeout,
3746 .ndo_change_mtu = skge_change_mtu,
3747 .ndo_validate_addr = eth_validate_addr,
3748 .ndo_set_multicast_list = skge_set_multicast,
3749 .ndo_set_mac_address = skge_set_mac_address,
3750#ifdef CONFIG_NET_POLL_CONTROLLER
3751 .ndo_poll_controller = skge_netpoll,
3752#endif
3753};
3754
3755
baef58b1 3756/* Initialize network device */
981d0377
SH		 3757static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3758 int highmem)
baef58b1
SH		 3759{
3760 struct skge_port *skge;
3761 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3762
3763 if (!dev) {
1479d13c 3764 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3765 return NULL;
3766 }
3767
baef58b1 3768 SET_NETDEV_DEV(dev, &hw->pdev->dev);
f80d032b
SH		 3769 dev->netdev_ops = &skge_netdev_ops;
3770 dev->ethtool_ops = &skge_ethtool_ops;
baef58b1 3771 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1 3772 dev->irq = hw->pdev->irq;
513f533e 3773
981d0377
SH		 3774 if (highmem)
3775 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3776
3777 skge = netdev_priv(dev);
bea3348e 3778 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3779 skge->netdev = dev;
3780 skge->hw = hw;
3781 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3782
baef58b1
SH		 3783 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3784 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3785
3786 /* Auto speed and flow control */
3787 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3788 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3789 skge->duplex = -1;
3790 skge->speed = -1;
31b619c5 3791 skge->advertising = skge_supported_modes(hw);
5b982c5b 3792
7b55a4a3 3793 if (device_can_wakeup(&hw->pdev->dev)) {
5b982c5b 3794 skge->wol = wol_supported(hw) & WAKE_MAGIC;
7b55a4a3
RW		 3795 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3796 }
baef58b1
SH		 3797
3798 hw->dev[port] = dev;
3799
3800 skge->port = port;
3801
64f6b64d 3802 /* Only used for Genesis XMAC */
9cbe330f 3803 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3804
baef58b1 3805 if (hw->chip_id != CHIP_ID_GENESIS) {
e92702b1
MM		 3806 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3807 NETIF_F_RXCSUM;
3808 dev->features |= dev->hw_features;
baef58b1
SH		 3809 }
3810
3811 /* read the mac address */
3812 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3813 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1 3814
baef58b1
SH		 3815 return dev;
3816}
3817
3818static void __devinit skge_show_addr(struct net_device *dev)
3819{
3820 const struct skge_port *skge = netdev_priv(dev);
3821
d707204c 3822 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
baef58b1
SH		 3823}
3824
392bd0cb
SG		 3825static int only_32bit_dma;
3826
baef58b1
SH		 3827static int __devinit skge_probe(struct pci_dev *pdev,
3828 const struct pci_device_id *ent)
3829{
3830 struct net_device *dev, *dev1;
3831 struct skge_hw *hw;
3832 int err, using_dac = 0;
3833
203babb6
SH		 3834 err = pci_enable_device(pdev);
3835 if (err) {
1479d13c 3836 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3837 goto err_out;
3838 }
3839
203babb6
SH		 3840 err = pci_request_regions(pdev, DRV_NAME);
3841 if (err) {
1479d13c 3842 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3843 goto err_out_disable_pdev;
3844 }
3845
3846 pci_set_master(pdev);
3847
392bd0cb 3848 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
baef58b1 3849 using_dac = 1;
6a35528a 3850 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
284901a9 3851 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
93aea718 3852 using_dac = 0;
284901a9 3853 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
93aea718
SH		 3854 }
3855
3856 if (err) {
1479d13c 3857 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3858 goto err_out_free_regions;
baef58b1
SH		 3859 }
3860
3861#ifdef __BIG_ENDIAN
8f3f8193 3862 /* byte swap descriptors in hardware */
baef58b1
SH		 3863 {
3864 u32 reg;
3865
3866 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3867 reg |= PCI_REV_DESC;
3868 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3869 }
3870#endif
3871
3872 err = -ENOMEM;
415e69e6 3873 /* space for skge@pci:0000:04:00.0 */
67777f9b 3874 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
415e69e6 3875 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
baef58b1 3876 if (!hw) {
1479d13c 3877 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3878 goto err_out_free_regions;
3879 }
415e69e6 3880 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
baef58b1 3881
baef58b1 3882 hw->pdev = pdev;
d38efdd6 3883 spin_lock_init(&hw->hw_lock);
9cbe330f 3884 spin_lock_init(&hw->phy_lock);
164165da 3885 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
baef58b1
SH		 3886
3887 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3888 if (!hw->regs) {
1479d13c 3889 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3890 goto err_out_free_hw;
3891 }
3892
baef58b1
SH		 3893 err = skge_reset(hw);
3894 if (err)
ccdaa2a9 3895 goto err_out_iounmap;
baef58b1 3896
f15063cd
JP		 3897 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3898 DRV_VERSION,
3899 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3900 skge_board_name(hw), hw->chip_rev);
baef58b1 3901
ccdaa2a9
SH		 3902 dev = skge_devinit(hw, 0, using_dac);
3903 if (!dev)
baef58b1
SH		 3904 goto err_out_led_off;
3905
fae87592 3906 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3907 if (!is_valid_ether_addr(dev->dev_addr))
3908 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3909
203babb6
SH		 3910 err = register_netdev(dev);
3911 if (err) {
1479d13c 3912 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3913 goto err_out_free_netdev;
3914 }
3915
415e69e6 3916 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
ccdaa2a9 3917 if (err) {
1479d13c 3918 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3919 dev->name, pdev->irq);
3920 goto err_out_unregister;
3921 }
baef58b1
SH		 3922 skge_show_addr(dev);
3923
f1914226
MM		 3924 if (hw->ports > 1) {
3925 dev1 = skge_devinit(hw, 1, using_dac);
3926 if (dev1 && register_netdev(dev1) == 0)
baef58b1
SH		 3927 skge_show_addr(dev1);
3928 else {
3929 /* Failure to register second port need not be fatal */
1479d13c 3930 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1 3931 hw->dev[1] = NULL;
f1914226
MM		 3932 hw->ports = 1;
3933 if (dev1)
3934 free_netdev(dev1);
baef58b1
SH		 3935 }
3936 }
ccdaa2a9 3937 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3938
3939 return 0;
3940
ccdaa2a9
SH		 3941err_out_unregister:
3942 unregister_netdev(dev);
baef58b1
SH		 3943err_out_free_netdev:
3944 free_netdev(dev);
3945err_out_led_off:
3946 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3947err_out_iounmap:
3948 iounmap(hw->regs);
3949err_out_free_hw:
3950 kfree(hw);
3951err_out_free_regions:
3952 pci_release_regions(pdev);
3953err_out_disable_pdev:
3954 pci_disable_device(pdev);
3955 pci_set_drvdata(pdev, NULL);
3956err_out:
3957 return err;
3958}
3959
3960static void __devexit skge_remove(struct pci_dev *pdev)
3961{
3962 struct skge_hw *hw = pci_get_drvdata(pdev);
3963 struct net_device *dev0, *dev1;
3964
95566065 3965 if (!hw)
baef58b1
SH		 3966 return;
3967
67777f9b
JP		 3968 dev1 = hw->dev[1];
3969 if (dev1)
baef58b1
SH		 3970 unregister_netdev(dev1);
3971 dev0 = hw->dev[0];
3972 unregister_netdev(dev0);
3973
9cbe330f
SH		 3974 tasklet_disable(&hw->phy_task);
3975
7c442fa1
SH		 3976 spin_lock_irq(&hw->hw_lock);
3977 hw->intr_mask = 0;
46a60f2d 3978 skge_write32(hw, B0_IMSK, 0);
78bc2186 3979 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3980 spin_unlock_irq(&hw->hw_lock);
3981
46a60f2d 3982 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3983 skge_write8(hw, B0_CTST, CS_RST_SET);
3984
baef58b1
SH		 3985 free_irq(pdev->irq, hw);
3986 pci_release_regions(pdev);
3987 pci_disable_device(pdev);
3988 if (dev1)
3989 free_netdev(dev1);
3990 free_netdev(dev0);
46a60f2d 3991
baef58b1
SH		 3992 iounmap(hw->regs);
3993 kfree(hw);
3994 pci_set_drvdata(pdev, NULL);
3995}
3996
3997#ifdef CONFIG_PM
7dbf6acd 3998static int skge_suspend(struct device *dev)
baef58b1 3999{
7dbf6acd 4000 struct pci_dev *pdev = to_pci_dev(dev);
baef58b1 4001 struct skge_hw *hw = pci_get_drvdata(pdev);
7dbf6acd 4002 int i;
a504e64a 4003
e3b7df17
SH		 4004 if (!hw)
4005 return 0;
4006
d38efdd6 4007 for (i = 0; i < hw->ports; i++) {
baef58b1 4008 struct net_device *dev = hw->dev[i];
a504e64a 4009 struct skge_port *skge = netdev_priv(dev);
baef58b1 4010
a504e64a
SH		 4011 if (netif_running(dev))
4012 skge_down(dev);
7dbf6acd 4013
a504e64a
SH		 4014 if (skge->wol)
4015 skge_wol_init(skge);
baef58b1
SH		 4016 }
4017
d38efdd6 4018 skge_write32(hw, B0_IMSK, 0);
5177b324 4019
baef58b1
SH		 4020 return 0;
4021}
4022
7dbf6acd 4023static int skge_resume(struct device *dev)
baef58b1 4024{
7dbf6acd 4025 struct pci_dev *pdev = to_pci_dev(dev);
baef58b1 4026 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 4027 int i, err;
baef58b1 4028
e3b7df17
SH		 4029 if (!hw)
4030 return 0;
4031
d38efdd6
SH		 4032 err = skge_reset(hw);
4033 if (err)
4034 goto out;
baef58b1 4035
d38efdd6 4036 for (i = 0; i < hw->ports; i++) {
baef58b1 4037 struct net_device *dev = hw->dev[i];
d38efdd6 4038
d38efdd6
SH		 4039 if (netif_running(dev)) {
4040 err = skge_up(dev);
4041
4042 if (err) {
f15063cd 4043 netdev_err(dev, "could not up: %d\n", err);
edd702e8 4044 dev_close(dev);
d38efdd6
SH		 4045 goto out;
4046 }
baef58b1
SH		 4047 }
4048 }
d38efdd6
SH		 4049out:
4050 return err;
baef58b1 4051}
7dbf6acd 4052
4053static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4054#define SKGE_PM_OPS (&skge_pm_ops)
4055
4056#else
4057
4058#define SKGE_PM_OPS NULL
baef58b1
SH		 4059#endif
4060
692412b3
SH		 4061static void skge_shutdown(struct pci_dev *pdev)
4062{
4063 struct skge_hw *hw = pci_get_drvdata(pdev);
7dbf6acd 4064 int i;
692412b3 4065
e3b7df17
SH		 4066 if (!hw)
4067 return;
4068
692412b3
SH		 4069 for (i = 0; i < hw->ports; i++) {
4070 struct net_device *dev = hw->dev[i];
4071 struct skge_port *skge = netdev_priv(dev);
4072
4073 if (skge->wol)
4074 skge_wol_init(skge);
692412b3
SH		 4075 }
4076
7dbf6acd 4077 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
692412b3 4078 pci_set_power_state(pdev, PCI_D3hot);
692412b3
SH		 4079}
4080
baef58b1
SH		 4081static struct pci_driver skge_driver = {
4082 .name = DRV_NAME,
4083 .id_table = skge_id_table,
4084 .probe = skge_probe,
4085 .remove = __devexit_p(skge_remove),
692412b3 4086 .shutdown = skge_shutdown,
7dbf6acd 4087 .driver.pm = SKGE_PM_OPS,
baef58b1
SH		 4088};
4089
392bd0cb
SG		 4090static struct dmi_system_id skge_32bit_dma_boards[] = {
4091 {
4092 .ident = "Gigabyte nForce boards",
4093 .matches = {
4094 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4095 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4096 },
4097 },
4098 {}
4099};
4100
baef58b1
SH		 4101static int __init skge_init_module(void)
4102{
392bd0cb
SG		 4103 if (dmi_check_system(skge_32bit_dma_boards))
4104 only_32bit_dma = 1;
678aa1f6 4105 skge_debug_init();
29917620 4106 return pci_register_driver(&skge_driver);
baef58b1
SH		 4107}
4108
4109static void __exit skge_cleanup_module(void)
4110{
4111 pci_unregister_driver(&skge_driver);
678aa1f6 4112 skge_debug_cleanup();
baef58b1
SH		 4113}
4114
4115module_init(skge_init_module);
4116module_exit(skge_cleanup_module);
Linux kernel - Deliverables
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