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sky2: fix management of driver LED
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
0c3f450b 53#define DRV_VERSION "1.25"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 66
ee5f68fe
SH		 67/* This is the worst case number of transmit list elements for a single skb:
68 VLAN + TSO + CKSUM + Data + skb_frags * DMA */
69#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
e9c1be80 70#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
ee5f68fe
SH		 71#define TX_MAX_PENDING 4096
72#define TX_DEF_PENDING 127
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 142 { 0 }
143};
793b883e 144
cd28ab6a
SH		 145MODULE_DEVICE_TABLE(pci, sky2_id_table);
146
147/* Avoid conditionals by using array */
148static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
149static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 150static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 151
d1b139c0
SH		 152static void sky2_set_multicast(struct net_device *dev);
153
af043aa5 154/* Access to PHY via serial interconnect */
ef743d33 155static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 156{
157 int i;
158
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
162
163 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 164 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
165 if (ctrl == 0xffff)
166 goto io_error;
167
168 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 169 return 0;
af043aa5
SH		 170
171 udelay(10);
cd28ab6a 172 }
ef743d33 173
af043aa5 174 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 175 return -ETIMEDOUT;
af043aa5
SH		 176
177io_error:
178 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
179 return -EIO;
cd28ab6a
SH		 180}
181
ef743d33 182static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 183{
184 int i;
185
793b883e 186 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 187 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
188
189 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 190 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
191 if (ctrl == 0xffff)
192 goto io_error;
193
194 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 195 *val = gma_read16(hw, port, GM_SMI_DATA);
196 return 0;
197 }
198
af043aa5 199 udelay(10);
cd28ab6a
SH		 200 }
201
af043aa5 202 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 203 return -ETIMEDOUT;
af043aa5
SH		 204io_error:
205 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
206 return -EIO;
ef743d33 207}
208
af043aa5 209static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 210{
211 u16 v;
af043aa5 212 __gm_phy_read(hw, port, reg, &v);
ef743d33 213 return v;
cd28ab6a
SH		 214}
215
5afa0a9c 216
ae306cca
SH		 217static void sky2_power_on(struct sky2_hw *hw)
218{
219 /* switch power to VCC (WA for VAUX problem) */
220 sky2_write8(hw, B0_POWER_CTRL,
221 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 222
ae306cca
SH		 223 /* disable Core Clock Division, */
224 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 225
ae306cca
SH		 226 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
227 /* enable bits are inverted */
228 sky2_write8(hw, B2_Y2_CLK_GATE,
229 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
230 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
231 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
232 else
233 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 234
ea76e635 235 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 236 u32 reg;
5afa0a9c 237
b32f40c4 238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 239
b32f40c4 240 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 241 /* set all bits to 0 except bits 15..12 and 8 */
242 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 243 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 244
b32f40c4 245 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 246 /* set all bits to 0 except bits 28 & 27 */
247 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 248 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 249
b32f40c4 250 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 251
252 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
253 reg = sky2_read32(hw, B2_GP_IO);
254 reg |= GLB_GPIO_STAT_RACE_DIS;
255 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 256
257 sky2_read32(hw, B2_GP_IO);
5afa0a9c 258 }
10547ae2
SH		 259
260 /* Turn on "driver loaded" LED */
261 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 262}
5afa0a9c 263
ae306cca
SH		 264static void sky2_power_aux(struct sky2_hw *hw)
265{
266 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
267 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
268 else
269 /* enable bits are inverted */
270 sky2_write8(hw, B2_Y2_CLK_GATE,
271 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
272 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
273 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
274
275 /* switch power to VAUX */
276 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
277 sky2_write8(hw, B0_POWER_CTRL,
278 (PC_VAUX_ENA | PC_VCC_ENA |
279 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 280
281 /* turn off "driver loaded LED" */
282 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 283}
284
d3bcfbeb 285static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 286{
287 u16 reg;
288
289 /* disable all GMAC IRQ's */
290 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 291
cd28ab6a
SH		 292 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
293 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
294 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
296
297 reg = gma_read16(hw, port, GM_RX_CTRL);
298 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
299 gma_write16(hw, port, GM_RX_CTRL, reg);
300}
301
16ad91e1
SH		 302/* flow control to advertise bits */
303static const u16 copper_fc_adv[] = {
304 [FC_NONE] = 0,
305 [FC_TX] = PHY_M_AN_ASP,
306 [FC_RX] = PHY_M_AN_PC,
307 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
308};
309
310/* flow control to advertise bits when using 1000BaseX */
311static const u16 fiber_fc_adv[] = {
df3fe1f3 312 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 313 [FC_TX] = PHY_M_P_ASYM_MD_X,
314 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 315 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 316};
317
318/* flow control to GMA disable bits */
319static const u16 gm_fc_disable[] = {
320 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
321 [FC_TX] = GM_GPCR_FC_RX_DIS,
322 [FC_RX] = GM_GPCR_FC_TX_DIS,
323 [FC_BOTH] = 0,
324};
325
326
cd28ab6a
SH		 327static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
328{
329 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 330 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 331
0ea065e5 332 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 333 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 334 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
335
336 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 337 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 338 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
339
53419c68 340 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 341 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 342 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 343 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
344 else
53419c68
SH		 345 /* set master & slave downshift counter to 1x */
346 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 347
348 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 352 if (sky2_is_copper(hw)) {
05745c4a 353 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 354 /* enable automatic crossover */
355 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 356
357 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
358 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
359 u16 spec;
360
361 /* Enable Class A driver for FE+ A0 */
362 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
363 spec |= PHY_M_FESC_SEL_CL_A;
364 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
365 }
cd28ab6a
SH		 366 } else {
367 /* disable energy detect */
368 ctrl &= ~PHY_M_PC_EN_DET_MSK;
369
370 /* enable automatic crossover */
371 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
372
53419c68 373 /* downshift on PHY 88E1112 and 88E1149 is changed */
0ea065e5 374 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED)
ea76e635 375 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 376 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 377 ctrl &= ~PHY_M_PC_DSC_MSK;
378 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
379 }
380 }
cd28ab6a
SH		 381 } else {
382 /* workaround for deviation #4.88 (CRC errors) */
383 /* disable Automatic Crossover */
384
385 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 386 }
cd28ab6a 387
b89165f2
SH		 388 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
389
390 /* special setup for PHY 88E1112 Fiber */
ea76e635 391 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 392 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 393
b89165f2
SH		 394 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
396 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
397 ctrl &= ~PHY_M_MAC_MD_MSK;
398 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
399 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400
401 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 402 /* select page 1 to access Fiber registers */
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 404
405 /* for SFP-module set SIGDET polarity to low */
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 408 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 409 }
b89165f2
SH		 410
411 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 412 }
413
7800fddc 414 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 415 ct1000 = 0;
416 adv = PHY_AN_CSMA;
2eaba1a2 417 reg = 0;
cd28ab6a 418
0ea065e5 419 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 420 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 421 if (sky2->advertising & ADVERTISED_1000baseT_Full)
422 ct1000 |= PHY_M_1000C_AFD;
423 if (sky2->advertising & ADVERTISED_1000baseT_Half)
424 ct1000 |= PHY_M_1000C_AHD;
425 if (sky2->advertising & ADVERTISED_100baseT_Full)
426 adv |= PHY_M_AN_100_FD;
427 if (sky2->advertising & ADVERTISED_100baseT_Half)
428 adv |= PHY_M_AN_100_HD;
429 if (sky2->advertising & ADVERTISED_10baseT_Full)
430 adv |= PHY_M_AN_10_FD;
431 if (sky2->advertising & ADVERTISED_10baseT_Half)
432 adv |= PHY_M_AN_10_HD;
709c6e7b 433
b89165f2
SH		 434 } else { /* special defines for FIBER (88E1040S only) */
435 if (sky2->advertising & ADVERTISED_1000baseT_Full)
436 adv |= PHY_M_AN_1000X_AFD;
437 if (sky2->advertising & ADVERTISED_1000baseT_Half)
438 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 439 }
cd28ab6a
SH		 440
441 /* Restart Auto-negotiation */
442 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
443 } else {
444 /* forced speed/duplex settings */
445 ct1000 = PHY_M_1000C_MSE;
446
0ea065e5
SH		 447 /* Disable auto update for duplex flow control and duplex */
448 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 449
450 switch (sky2->speed) {
451 case SPEED_1000:
452 ctrl |= PHY_CT_SP1000;
2eaba1a2 453 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 454 break;
455 case SPEED_100:
456 ctrl |= PHY_CT_SP100;
2eaba1a2 457 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 458 break;
459 }
460
2eaba1a2
SH		 461 if (sky2->duplex == DUPLEX_FULL) {
462 reg |= GM_GPCR_DUP_FULL;
463 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 464 } else if (sky2->speed < SPEED_1000)
465 sky2->flow_mode = FC_NONE;
0ea065e5 466 }
2eaba1a2 467
0ea065e5
SH		 468 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
469 if (sky2_is_copper(hw))
470 adv |= copper_fc_adv[sky2->flow_mode];
471 else
472 adv |= fiber_fc_adv[sky2->flow_mode];
473 } else {
474 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 475 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 476
477 /* Forward pause packets to GMAC? */
16ad91e1 478 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
480 else
481 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 482 }
483
2eaba1a2
SH		 484 gma_write16(hw, port, GM_GP_CTRL, reg);
485
05745c4a 486 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 487 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
488
489 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
490 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
491
492 /* Setup Phy LED's */
493 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
494 ledover = 0;
495
496 switch (hw->chip_id) {
497 case CHIP_ID_YUKON_FE:
498 /* on 88E3082 these bits are at 11..9 (shifted left) */
499 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
500
501 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
502
503 /* delete ACT LED control bits */
504 ctrl &= ~PHY_M_FELP_LED1_MSK;
505 /* change ACT LED control to blink mode */
506 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
507 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 break;
509
05745c4a
SH		 510 case CHIP_ID_YUKON_FE_P:
511 /* Enable Link Partner Next Page */
512 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
513 ctrl |= PHY_M_PC_ENA_LIP_NP;
514
515 /* disable Energy Detect and enable scrambler */
516 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
518
519 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
520 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
521 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
522 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
523
524 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
525 break;
526
cd28ab6a 527 case CHIP_ID_YUKON_XL:
793b883e 528 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 529
530 /* select page 3 to access LED control register */
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
532
533 /* set LED Function Control register */
ed6d32c7
SH		 534 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
535 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
536 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
537 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
538 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 539
540 /* set Polarity Control register */
541 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 542 (PHY_M_POLC_LS1_P_MIX(4) |
543 PHY_M_POLC_IS0_P_MIX(4) |
544 PHY_M_POLC_LOS_CTRL(2) |
545 PHY_M_POLC_INIT_CTRL(2) |
546 PHY_M_POLC_STA1_CTRL(2) |
547 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 548
549 /* restore page register */
793b883e 550 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 551 break;
93745494 552
ed6d32c7 553 case CHIP_ID_YUKON_EC_U:
93745494 554 case CHIP_ID_YUKON_EX:
ed4d4161 555 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 556 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
557
558 /* select page 3 to access LED control register */
559 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
560
561 /* set LED Function Control register */
562 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
563 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
564 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
565 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
566 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
567
568 /* set Blink Rate in LED Timer Control Register */
569 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
570 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
571 /* restore page register */
572 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
573 break;
cd28ab6a
SH		 574
575 default:
576 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
577 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 578
cd28ab6a 579 /* turn off the Rx LED (LED_RX) */
a84d0a3d 580 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 581 }
582
0ce8b98d 583 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 584 /* apply fixes in PHY AFE */
ed6d32c7
SH		 585 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
586
977bdf06 587 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 588 gm_phy_write(hw, port, 0x18, 0xaa99);
589 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 590
0ce8b98d
SH		 591 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
592 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
593 gm_phy_write(hw, port, 0x18, 0xa204);
594 gm_phy_write(hw, port, 0x17, 0x2002);
595 }
977bdf06
SH		 596
597 /* set page register to 0 */
9467a8fc 598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 599 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
600 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
601 /* apply workaround for integrated resistors calibration */
602 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
603 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 604 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
605 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 606 /* no effect on Yukon-XL */
977bdf06 607 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 608
0ea065e5
SH		 609 if ( !(sky2->flags & SKY2_FLAG_AUTO_SPEED)
610 || sky2->speed == SPEED_100) {
977bdf06 611 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 612 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 613 }
cd28ab6a 614
977bdf06
SH		 615 if (ledover)
616 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
617
618 }
2eaba1a2 619
d571b694 620 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 621 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 622 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
623 else
624 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
625}
626
b96936da
SH		 627static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
628static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
629
630static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 631{
632 u32 reg1;
d3bcfbeb 633
82637e80 634 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 635 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 636 reg1 &= ~phy_power[port];
d3bcfbeb 637
b96936da 638 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 639 reg1 |= coma_mode[port];
640
b32f40c4 641 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 642 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
643 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 644
645 if (hw->chip_id == CHIP_ID_YUKON_FE)
646 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
647 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
648 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 649}
167f53d0 650
b96936da
SH		 651static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
652{
653 u32 reg1;
db99b988
SH		 654 u16 ctrl;
655
656 /* release GPHY Control reset */
657 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
658
659 /* release GMAC reset */
660 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
661
662 if (hw->flags & SKY2_HW_NEWER_PHY) {
663 /* select page 2 to access MAC control register */
664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
665
666 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
667 /* allow GMII Power Down */
668 ctrl &= ~PHY_M_MAC_GMIF_PUP;
669 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
670
671 /* set page register back to 0 */
672 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
673 }
674
675 /* setup General Purpose Control Register */
676 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 677 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
678 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
679 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 680
681 if (hw->chip_id != CHIP_ID_YUKON_EC) {
682 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 683 /* select page 2 to access MAC control register */
684 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 685
e484d5f5 686 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 687 /* enable Power Down */
688 ctrl |= PHY_M_PC_POW_D_ENA;
689 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 690
691 /* set page register back to 0 */
692 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 693 }
694
695 /* set IEEE compatible Power Down Mode (dev. #4.99) */
696 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
697 }
b96936da
SH		 698
699 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
700 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 701 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 702 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 704}
705
1b537565
SH		 706/* Force a renegotiation */
707static void sky2_phy_reinit(struct sky2_port *sky2)
708{
e07b1aa8 709 spin_lock_bh(&sky2->phy_lock);
1b537565 710 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 711 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 712}
713
e3173832
SH		 714/* Put device in state to listen for Wake On Lan */
715static void sky2_wol_init(struct sky2_port *sky2)
716{
717 struct sky2_hw *hw = sky2->hw;
718 unsigned port = sky2->port;
719 enum flow_control save_mode;
720 u16 ctrl;
721 u32 reg1;
722
723 /* Bring hardware out of reset */
724 sky2_write16(hw, B0_CTST, CS_RST_CLR);
725 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
726
727 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
728 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
729
730 /* Force to 10/100
731 * sky2_reset will re-enable on resume
732 */
733 save_mode = sky2->flow_mode;
734 ctrl = sky2->advertising;
735
736 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
737 sky2->flow_mode = FC_NONE;
b96936da
SH		 738
739 spin_lock_bh(&sky2->phy_lock);
740 sky2_phy_power_up(hw, port);
741 sky2_phy_init(hw, port);
742 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 743
744 sky2->flow_mode = save_mode;
745 sky2->advertising = ctrl;
746
747 /* Set GMAC to no flow control and auto update for speed/duplex */
748 gma_write16(hw, port, GM_GP_CTRL,
749 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
750 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
751
752 /* Set WOL address */
753 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
754 sky2->netdev->dev_addr, ETH_ALEN);
755
756 /* Turn on appropriate WOL control bits */
757 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
758 ctrl = 0;
759 if (sky2->wol & WAKE_PHY)
760 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
761 else
762 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
763
764 if (sky2->wol & WAKE_MAGIC)
765 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
766 else
767 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
768
769 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
771
772 /* Turn on legacy PCI-Express PME mode */
b32f40c4 773 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 774 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 775 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 776
777 /* block receiver */
778 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
779
780}
781
69161611
SH		 782static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
783{
05745c4a
SH		 784 struct net_device *dev = hw->dev[port];
785
ed4d4161
SH		 786 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
787 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
788 hw->chip_id == CHIP_ID_YUKON_FE_P ||
789 hw->chip_id == CHIP_ID_YUKON_SUPR) {
790 /* Yukon-Extreme B0 and further Extreme devices */
791 /* enable Store & Forward mode for TX */
05745c4a 792
ed4d4161
SH		 793 if (dev->mtu <= ETH_DATA_LEN)
794 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
795 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 796
ed4d4161
SH		 797 else
798 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
799 TX_JUMBO_ENA| TX_STFW_ENA);
800 } else {
801 if (dev->mtu <= ETH_DATA_LEN)
802 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
803 else {
804 /* set Tx GMAC FIFO Almost Empty Threshold */
805 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
806 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 807
ed4d4161
SH		 808 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
809
810 /* Can't do offload because of lack of store/forward */
811 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
812 }
69161611
SH		 813 }
814}
815
cd28ab6a
SH		 816static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
817{
818 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
819 u16 reg;
25cccecc 820 u32 rx_reg;
cd28ab6a
SH		 821 int i;
822 const u8 *addr = hw->dev[port]->dev_addr;
823
f350339c
SH		 824 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
825 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 826
827 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
828
793b883e 829 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 830 /* WA DEV_472 -- looks like crossed wires on port 2 */
831 /* clear GMAC 1 Control reset */
832 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
833 do {
834 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
835 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
836 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
837 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
838 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
839 }
840
793b883e 841 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 842
2eaba1a2
SH		 843 /* Enable Transmit FIFO Underrun */
844 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
845
e07b1aa8 846 spin_lock_bh(&sky2->phy_lock);
b96936da 847 sky2_phy_power_up(hw, port);
cd28ab6a 848 sky2_phy_init(hw, port);
e07b1aa8 849 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 850
851 /* MIB clear */
852 reg = gma_read16(hw, port, GM_PHY_ADDR);
853 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
854
43f2f104
SH		 855 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
856 gma_read16(hw, port, i);
cd28ab6a
SH		 857 gma_write16(hw, port, GM_PHY_ADDR, reg);
858
859 /* transmit control */
860 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
861
862 /* receive control reg: unicast + multicast + no FCS */
863 gma_write16(hw, port, GM_RX_CTRL,
793b883e 864 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 865
866 /* transmit flow control */
867 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
868
869 /* transmit parameter */
870 gma_write16(hw, port, GM_TX_PARAM,
871 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
872 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
873 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
874 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
875
876 /* serial mode register */
877 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 878 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 879
6b1a3aef 880 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 881 reg |= GM_SMOD_JUMBO_ENA;
882
883 gma_write16(hw, port, GM_SERIAL_MODE, reg);
884
cd28ab6a
SH		 885 /* virtual address for data */
886 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
887
793b883e
SH		 888 /* physical address: used for pause frames */
889 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
890
891 /* ignore counter overflows */
cd28ab6a
SH		 892 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
893 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
895
896 /* Configure Rx MAC FIFO */
897 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 898 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 899 if (hw->chip_id == CHIP_ID_YUKON_EX ||
900 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 901 rx_reg |= GMF_RX_OVER_ON;
69161611 902
25cccecc 903 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 904
798fdd07
SH		 905 if (hw->chip_id == CHIP_ID_YUKON_XL) {
906 /* Hardware errata - clear flush mask */
907 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
908 } else {
909 /* Flush Rx MAC FIFO on any flow control or error */
910 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
911 }
cd28ab6a 912
8df9a876 913 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 914 reg = RX_GMF_FL_THR_DEF + 1;
915 /* Another magic mystery workaround from sk98lin */
916 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
917 hw->chip_rev == CHIP_REV_YU_FE2_A0)
918 reg = 0x178;
919 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 920
921 /* Configure Tx MAC FIFO */
922 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
923 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 924
e0c28116 925 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 926 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 927 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 928 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 929
69161611 930 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 931 }
932
e970d1f8
SH		 933 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
934 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
935 /* disable dynamic watermark */
936 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
937 reg &= ~TX_DYN_WM_ENA;
938 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
939 }
cd28ab6a
SH		 940}
941
67712901
SH		 942/* Assign Ram Buffer allocation to queue */
943static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 944{
67712901
SH		 945 u32 end;
946
947 /* convert from K bytes to qwords used for hw register */
948 start *= 1024/8;
949 space *= 1024/8;
950 end = start + space - 1;
793b883e 951
cd28ab6a
SH		 952 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
953 sky2_write32(hw, RB_ADDR(q, RB_START), start);
954 sky2_write32(hw, RB_ADDR(q, RB_END), end);
955 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
956 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
957
958 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 959 u32 tp = space - space/4;
793b883e 960
1c28f6ba
SH		 961 /* On receive queue's set the thresholds
962 * give receiver priority when > 3/4 full
963 * send pause when down to 2K
964 */
965 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
966 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 967
1c28f6ba
SH		 968 tp = space - 2048/8;
969 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
970 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 971 } else {
972 /* Enable store & forward on Tx queue's because
973 * Tx FIFO is only 1K on Yukon
974 */
975 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
976 }
977
978 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 979 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 980}
981
cd28ab6a 982/* Setup Bus Memory Interface */
af4ed7e6 983static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 984{
985 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
986 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
987 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 988 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 989}
990
cd28ab6a
SH		 991/* Setup prefetch unit registers. This is the interface between
992 * hardware and driver list elements
993 */
8cc048e3 994static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 995 dma_addr_t addr, u32 last)
cd28ab6a 996{
cd28ab6a
SH		 997 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
998 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 999 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1000 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1001 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1002 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1003
1004 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1005}
1006
9b289c33 1007static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1008{
9b289c33 1009 struct sky2_tx_le *le = sky2->tx_le + *slot;
6b84daca 1010 struct tx_ring_info *re = sky2->tx_ring + *slot;
793b883e 1011
ee5f68fe 1012 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
6b84daca
SH		 1013 re->flags = 0;
1014 re->skb = NULL;
291ea614 1015 le->ctrl = 0;
793b883e
SH		 1016 return le;
1017}
cd28ab6a 1018
88f5f0ca
SH		 1019static void tx_init(struct sky2_port *sky2)
1020{
1021 struct sky2_tx_le *le;
1022
1023 sky2->tx_prod = sky2->tx_cons = 0;
1024 sky2->tx_tcpsum = 0;
1025 sky2->tx_last_mss = 0;
1026
9b289c33 1027 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1028 le->addr = 0;
1029 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1030 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1031}
1032
290d4de5
SH		 1033/* Update chip's next pointer */
1034static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1035{
50432cb5 1036 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1037 wmb();
50432cb5
SH		 1038 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1039
1040 /* Synchronize I/O on since next processor may write to tail */
1041 mmiowb();
cd28ab6a
SH		 1042}
1043
793b883e 1044
cd28ab6a
SH		 1045static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1046{
1047 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1048 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1049 le->ctrl = 0;
cd28ab6a
SH		 1050 return le;
1051}
1052
14d0263f
SH		 1053/* Build description to hardware for one receive segment */
1054static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1055 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1056{
1057 struct sky2_rx_le *le;
1058
86c6887e 1059 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1060 le = sky2_next_rx(sky2);
86c6887e 1061 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1062 le->opcode = OP_ADDR64 | HW_OWNER;
1063 }
793b883e 1064
cd28ab6a 1065 le = sky2_next_rx(sky2);
d6e74b6b 1066 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1067 le->length = cpu_to_le16(len);
14d0263f 1068 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1069}
1070
14d0263f
SH		 1071/* Build description to hardware for one possibly fragmented skb */
1072static void sky2_rx_submit(struct sky2_port *sky2,
1073 const struct rx_ring_info *re)
1074{
1075 int i;
1076
1077 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1078
1079 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1080 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1081}
1082
1083
454e6cb6 1084static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1085 unsigned size)
1086{
1087 struct sk_buff *skb = re->skb;
1088 int i;
1089
1090 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1091 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1092 return -EIO;
1093
14d0263f
SH		 1094 pci_unmap_len_set(re, data_size, size);
1095
1096 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1097 re->frag_addr[i] = pci_map_page(pdev,
1098 skb_shinfo(skb)->frags[i].page,
1099 skb_shinfo(skb)->frags[i].page_offset,
1100 skb_shinfo(skb)->frags[i].size,
1101 PCI_DMA_FROMDEVICE);
454e6cb6 1102 return 0;
14d0263f
SH		 1103}
1104
1105static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1106{
1107 struct sk_buff *skb = re->skb;
1108 int i;
1109
1110 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1111 PCI_DMA_FROMDEVICE);
1112
1113 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1114 pci_unmap_page(pdev, re->frag_addr[i],
1115 skb_shinfo(skb)->frags[i].size,
1116 PCI_DMA_FROMDEVICE);
1117}
793b883e 1118
cd28ab6a
SH		 1119/* Tell chip where to start receive checksum.
1120 * Actually has two checksums, but set both same to avoid possible byte
1121 * order problems.
1122 */
793b883e 1123static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1124{
ea76e635 1125 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1126
ea76e635
SH		 1127 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1128 le->ctrl = 0;
1129 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1130
ea76e635
SH		 1131 sky2_write32(sky2->hw,
1132 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1133 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1134 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1135}
1136
6b1a3aef 1137/*
1138 * The RX Stop command will not work for Yukon-2 if the BMU does not
1139 * reach the end of packet and since we can't make sure that we have
1140 * incoming data, we must reset the BMU while it is not doing a DMA
1141 * transfer. Since it is possible that the RX path is still active,
1142 * the RX RAM buffer will be stopped first, so any possible incoming
1143 * data will not trigger a DMA. After the RAM buffer is stopped, the
1144 * BMU is polled until any DMA in progress is ended and only then it
1145 * will be reset.
1146 */
1147static void sky2_rx_stop(struct sky2_port *sky2)
1148{
1149 struct sky2_hw *hw = sky2->hw;
1150 unsigned rxq = rxqaddr[sky2->port];
1151 int i;
1152
1153 /* disable the RAM Buffer receive queue */
1154 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1155
1156 for (i = 0; i < 0xffff; i++)
1157 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1158 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1159 goto stopped;
1160
1161 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1162 sky2->netdev->name);
1163stopped:
1164 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1165
1166 /* reset the Rx prefetch unit */
1167 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1168 mmiowb();
6b1a3aef 1169}
793b883e 1170
d571b694 1171/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1172static void sky2_rx_clean(struct sky2_port *sky2)
1173{
1174 unsigned i;
1175
1176 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1177 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1178 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1179
1180 if (re->skb) {
14d0263f 1181 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1182 kfree_skb(re->skb);
1183 re->skb = NULL;
1184 }
1185 }
1186}
1187
ef743d33 1188/* Basic MII support */
1189static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1190{
1191 struct mii_ioctl_data *data = if_mii(ifr);
1192 struct sky2_port *sky2 = netdev_priv(dev);
1193 struct sky2_hw *hw = sky2->hw;
1194 int err = -EOPNOTSUPP;
1195
1196 if (!netif_running(dev))
1197 return -ENODEV; /* Phy still in reset */
1198
d89e1343 1199 switch (cmd) {
ef743d33 1200 case SIOCGMIIPHY:
1201 data->phy_id = PHY_ADDR_MARV;
1202
1203 /* fallthru */
1204 case SIOCGMIIREG: {
1205 u16 val = 0;
91c86df5 1206
e07b1aa8 1207 spin_lock_bh(&sky2->phy_lock);
ef743d33 1208 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1209 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1210
ef743d33 1211 data->val_out = val;
1212 break;
1213 }
1214
1215 case SIOCSMIIREG:
1216 if (!capable(CAP_NET_ADMIN))
1217 return -EPERM;
1218
e07b1aa8 1219 spin_lock_bh(&sky2->phy_lock);
ef743d33 1220 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1221 data->val_in);
e07b1aa8 1222 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1223 break;
1224 }
1225 return err;
1226}
1227
d1f13708 1228#ifdef SKY2_VLAN_TAG_USED
d494eacd 1229static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1230{
d494eacd 1231 if (onoff) {
3d4e66f5
SH		 1232 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1233 RX_VLAN_STRIP_ON);
1234 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1235 TX_VLAN_TAG_ON);
1236 } else {
1237 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1238 RX_VLAN_STRIP_OFF);
1239 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1240 TX_VLAN_TAG_OFF);
1241 }
d494eacd
SH		 1242}
1243
1244static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1245{
1246 struct sky2_port *sky2 = netdev_priv(dev);
1247 struct sky2_hw *hw = sky2->hw;
1248 u16 port = sky2->port;
1249
1250 netif_tx_lock_bh(dev);
1251 napi_disable(&hw->napi);
1252
1253 sky2->vlgrp = grp;
1254 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1255
d1d08d12 1256 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1257 napi_enable(&hw->napi);
2bb8c262 1258 netif_tx_unlock_bh(dev);
d1f13708 1259}
1260#endif
1261
bd1c6869
SH		 1262/* Amount of required worst case padding in rx buffer */
1263static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1264{
1265 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1266}
1267
82788c7a 1268/*
14d0263f
SH		 1269 * Allocate an skb for receiving. If the MTU is large enough
1270 * make the skb non-linear with a fragment list of pages.
82788c7a 1271 */
14d0263f 1272static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1273{
1274 struct sk_buff *skb;
14d0263f 1275 int i;
82788c7a 1276
724b6942
SH		 1277 skb = netdev_alloc_skb(sky2->netdev,
1278 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1279 if (!skb)
1280 goto nomem;
1281
39dbd958 1282 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1283 unsigned char *start;
1284 /*
1285 * Workaround for a bug in FIFO that cause hang
1286 * if the FIFO if the receive buffer is not 64 byte aligned.
1287 * The buffer returned from netdev_alloc_skb is
1288 * aligned except if slab debugging is enabled.
1289 */
f03b8654
SH		 1290 start = PTR_ALIGN(skb->data, 8);
1291 skb_reserve(skb, start - skb->data);
bd1c6869 1292 } else
f03b8654 1293 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1294
1295 for (i = 0; i < sky2->rx_nfrags; i++) {
1296 struct page *page = alloc_page(GFP_ATOMIC);
1297
1298 if (!page)
1299 goto free_partial;
1300 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1301 }
1302
1303 return skb;
14d0263f
SH		 1304free_partial:
1305 kfree_skb(skb);
1306nomem:
1307 return NULL;
82788c7a
SH		 1308}
1309
55c9dd35
SH		 1310static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1311{
1312 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1313}
1314
cd28ab6a
SH		 1315/*
1316 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1317 * Normal case this ends up creating one list element for skb
1318 * in the receive ring. Worst case if using large MTU and each
1319 * allocation falls on a different 64 bit region, that results
1320 * in 6 list elements per ring entry.
1321 * One element is used for checksum enable/disable, and one
1322 * extra to avoid wrap.
cd28ab6a 1323 */
6b1a3aef 1324static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1325{
6b1a3aef 1326 struct sky2_hw *hw = sky2->hw;
14d0263f 1327 struct rx_ring_info *re;
6b1a3aef 1328 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1329 unsigned i, size, thresh;
cd28ab6a 1330
6b1a3aef 1331 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1332 sky2_qset(hw, rxq);
977bdf06 1333
c3905bc4
SH		 1334 /* On PCI express lowering the watermark gives better performance */
1335 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1336 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1337
1338 /* These chips have no ram buffer?
1339 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1340 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1341 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1342 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1343 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1344
6b1a3aef 1345 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1346
ea76e635
SH		 1347 if (!(hw->flags & SKY2_HW_NEW_LE))
1348 rx_set_checksum(sky2);
14d0263f
SH		 1349
1350 /* Space needed for frame data + headers rounded up */
f957da2a 1351 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1352
1353 /* Stopping point for hardware truncation */
1354 thresh = (size - 8) / sizeof(u32);
1355
5f06eba4 1356 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1357 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1358
5f06eba4
SH		 1359 /* Compute residue after pages */
1360 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1361
5f06eba4
SH		 1362 /* Optimize to handle small packets and headers */
1363 if (size < copybreak)
1364 size = copybreak;
1365 if (size < ETH_HLEN)
1366 size = ETH_HLEN;
14d0263f 1367
14d0263f
SH		 1368 sky2->rx_data_size = size;
1369
1370 /* Fill Rx ring */
793b883e 1371 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1372 re = sky2->rx_ring + i;
cd28ab6a 1373
14d0263f 1374 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1375 if (!re->skb)
1376 goto nomem;
1377
454e6cb6
SH		 1378 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1379 dev_kfree_skb(re->skb);
1380 re->skb = NULL;
1381 goto nomem;
1382 }
1383
14d0263f 1384 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1385 }
1386
a1433ac4
SH		 1387 /*
1388 * The receiver hangs if it receives frames larger than the
1389 * packet buffer. As a workaround, truncate oversize frames, but
1390 * the register is limited to 9 bits, so if you do frames > 2052
1391 * you better get the MTU right!
1392 */
a1433ac4
SH		 1393 if (thresh > 0x1ff)
1394 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1395 else {
1396 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1397 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1398 }
1399
6b1a3aef 1400 /* Tell chip about available buffers */
55c9dd35 1401 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1402 return 0;
1403nomem:
1404 sky2_rx_clean(sky2);
1405 return -ENOMEM;
1406}
1407
1408/* Bring up network interface. */
1409static int sky2_up(struct net_device *dev)
1410{
1411 struct sky2_port *sky2 = netdev_priv(dev);
1412 struct sky2_hw *hw = sky2->hw;
1413 unsigned port = sky2->port;
e0c28116 1414 u32 imask, ramsize;
ee7abb04 1415 int cap, err = -ENOMEM;
843a46f4 1416 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1417
ee7abb04
SH		 1418 /*
1419 * On dual port PCI-X card, there is an problem where status
1420 * can be received out of order due to split transactions
843a46f4 1421 */
ee7abb04
SH		 1422 if (otherdev && netif_running(otherdev) &&
1423 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1424 u16 cmd;
1425
b32f40c4 1426 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1427 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1428 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1429
ee7abb04 1430 }
843a46f4 1431
55d7b4e6
SH		 1432 netif_carrier_off(dev);
1433
cd28ab6a
SH		 1434 /* must be power of 2 */
1435 sky2->tx_le = pci_alloc_consistent(hw->pdev,
ee5f68fe 1436 sky2->tx_ring_size *
793b883e 1437 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1438 &sky2->tx_le_map);
1439 if (!sky2->tx_le)
1440 goto err_out;
1441
ee5f68fe 1442 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1443 GFP_KERNEL);
1444 if (!sky2->tx_ring)
1445 goto err_out;
88f5f0ca
SH		 1446
1447 tx_init(sky2);
cd28ab6a
SH		 1448
1449 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1450 &sky2->rx_le_map);
1451 if (!sky2->rx_le)
1452 goto err_out;
1453 memset(sky2->rx_le, 0, RX_LE_BYTES);
1454
291ea614 1455 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1456 GFP_KERNEL);
1457 if (!sky2->rx_ring)
1458 goto err_out;
1459
1460 sky2_mac_init(hw, port);
1461
e0c28116
SH		 1462 /* Register is number of 4K blocks on internal RAM buffer. */
1463 ramsize = sky2_read8(hw, B2_E_0) * 4;
1464 if (ramsize > 0) {
67712901 1465 u32 rxspace;
cd28ab6a 1466
39dbd958 1467 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1468 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1469 if (ramsize < 16)
1470 rxspace = ramsize / 2;
1471 else
1472 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1473
67712901
SH		 1474 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1475 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1476
1477 /* Make sure SyncQ is disabled */
1478 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1479 RB_RST_SET);
1480 }
793b883e 1481
af4ed7e6 1482 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1483
69161611
SH		 1484 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1485 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1486 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1487
977bdf06 1488 /* Set almost empty threshold */
c2716fb4
SH		 1489 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1490 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1491 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1492
6b1a3aef 1493 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1494 sky2->tx_ring_size - 1);
cd28ab6a 1495
d494eacd
SH		 1496#ifdef SKY2_VLAN_TAG_USED
1497 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1498#endif
1499
6b1a3aef 1500 err = sky2_rx_start(sky2);
6de16237 1501 if (err)
cd28ab6a
SH		 1502 goto err_out;
1503
cd28ab6a 1504 /* Enable interrupts from phy/mac for port */
e07b1aa8 1505 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1506 imask |= portirq_msk[port];
e07b1aa8 1507 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1508 sky2_read32(hw, B0_IMSK);
e07b1aa8 1509
a11da890
AD		 1510 if (netif_msg_ifup(sky2))
1511 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
af18d8b8 1512
cd28ab6a
SH		 1513 return 0;
1514
1515err_out:
1b537565 1516 if (sky2->rx_le) {
cd28ab6a
SH		 1517 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1518 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1519 sky2->rx_le = NULL;
1520 }
1521 if (sky2->tx_le) {
cd28ab6a 1522 pci_free_consistent(hw->pdev,
ee5f68fe 1523 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
cd28ab6a 1524 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1525 sky2->tx_le = NULL;
1526 }
1527 kfree(sky2->tx_ring);
1528 kfree(sky2->rx_ring);
cd28ab6a 1529
1b537565
SH		 1530 sky2->tx_ring = NULL;
1531 sky2->rx_ring = NULL;
cd28ab6a
SH		 1532 return err;
1533}
1534
793b883e 1535/* Modular subtraction in ring */
ee5f68fe 1536static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1537{
ee5f68fe 1538 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1539}
cd28ab6a 1540
793b883e
SH		 1541/* Number of list elements available for next tx */
1542static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1543{
ee5f68fe 1544 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1545}
1546
793b883e 1547/* Estimate of number of transmit list elements required */
28bd181a 1548static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1549{
793b883e
SH		 1550 unsigned count;
1551
1552 count = sizeof(dma_addr_t) / sizeof(u32);
1553 count += skb_shinfo(skb)->nr_frags * count;
1554
89114afd 1555 if (skb_is_gso(skb))
793b883e
SH		 1556 ++count;
1557
84fa7933 1558 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1559 ++count;
1560
1561 return count;
cd28ab6a
SH		 1562}
1563
6b84daca
SH		 1564static void sky2_tx_unmap(struct pci_dev *pdev,
1565 const struct tx_ring_info *re)
1566{
1567 if (re->flags & TX_MAP_SINGLE)
1568 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1569 pci_unmap_len(re, maplen),
1570 PCI_DMA_TODEVICE);
1571 else if (re->flags & TX_MAP_PAGE)
1572 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1573 pci_unmap_len(re, maplen),
1574 PCI_DMA_TODEVICE);
1575}
1576
793b883e
SH		 1577/*
1578 * Put one packet in ring for transmit.
1579 * A single packet can generate multiple list elements, and
1580 * the number of ring elements will probably be less than the number
1581 * of list elements used.
1582 */
61357325
SH		 1583static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1584 struct net_device *dev)
cd28ab6a
SH		 1585{
1586 struct sky2_port *sky2 = netdev_priv(dev);
1587 struct sky2_hw *hw = sky2->hw;
d1f13708 1588 struct sky2_tx_le *le = NULL;
6cdbbdf3 1589 struct tx_ring_info *re;
9b289c33 1590 unsigned i, len;
cd28ab6a 1591 dma_addr_t mapping;
5dce95e5
SH		 1592 u32 upper;
1593 u16 slot;
cd28ab6a
SH		 1594 u16 mss;
1595 u8 ctrl;
1596
2bb8c262
SH		 1597 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1598 return NETDEV_TX_BUSY;
cd28ab6a 1599
cd28ab6a
SH		 1600 len = skb_headlen(skb);
1601 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1602
454e6cb6
SH		 1603 if (pci_dma_mapping_error(hw->pdev, mapping))
1604 goto mapping_error;
1605
9b289c33 1606 slot = sky2->tx_prod;
454e6cb6
SH		 1607 if (unlikely(netif_msg_tx_queued(sky2)))
1608 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
9b289c33 1609 dev->name, slot, skb->len);
454e6cb6 1610
86c6887e 1611 /* Send high bits if needed */
5dce95e5
SH		 1612 upper = upper_32_bits(mapping);
1613 if (upper != sky2->tx_last_upper) {
9b289c33 1614 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1615 le->addr = cpu_to_le32(upper);
1616 sky2->tx_last_upper = upper;
793b883e 1617 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1618 }
cd28ab6a
SH		 1619
1620 /* Check for TCP Segmentation Offload */
7967168c 1621 mss = skb_shinfo(skb)->gso_size;
793b883e 1622 if (mss != 0) {
ea76e635
SH		 1623
1624 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1625 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1626
1627 if (mss != sky2->tx_last_mss) {
9b289c33 1628 le = get_tx_le(sky2, &slot);
69161611 1629 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1630
1631 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1632 le->opcode = OP_MSS | HW_OWNER;
1633 else
1634 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1635 sky2->tx_last_mss = mss;
1636 }
cd28ab6a
SH		 1637 }
1638
cd28ab6a 1639 ctrl = 0;
d1f13708 1640#ifdef SKY2_VLAN_TAG_USED
1641 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1642 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1643 if (!le) {
9b289c33 1644 le = get_tx_le(sky2, &slot);
f65b138c 1645 le->addr = 0;
d1f13708 1646 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1647 } else
1648 le->opcode |= OP_VLAN;
1649 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1650 ctrl |= INS_VLAN;
1651 }
1652#endif
1653
1654 /* Handle TCP checksum offload */
84fa7933 1655 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1656 /* On Yukon EX (some versions) encoding change. */
ea76e635 1657 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1658 ctrl |= CALSUM; /* auto checksum */
1659 else {
1660 const unsigned offset = skb_transport_offset(skb);
1661 u32 tcpsum;
1662
1663 tcpsum = offset << 16; /* sum start */
1664 tcpsum |= offset + skb->csum_offset; /* sum write */
1665
1666 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1667 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1668 ctrl |= UDPTCP;
1669
1670 if (tcpsum != sky2->tx_tcpsum) {
1671 sky2->tx_tcpsum = tcpsum;
1672
9b289c33 1673 le = get_tx_le(sky2, &slot);
69161611
SH		 1674 le->addr = cpu_to_le32(tcpsum);
1675 le->length = 0; /* initial checksum value */
1676 le->ctrl = 1; /* one packet */
1677 le->opcode = OP_TCPLISW | HW_OWNER;
1678 }
1d179332 1679 }
cd28ab6a
SH		 1680 }
1681
6b84daca
SH		 1682 re = sky2->tx_ring + slot;
1683 re->flags = TX_MAP_SINGLE;
1684 pci_unmap_addr_set(re, mapaddr, mapping);
1685 pci_unmap_len_set(re, maplen, len);
1686
9b289c33 1687 le = get_tx_le(sky2, &slot);
d6e74b6b 1688 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1689 le->length = cpu_to_le16(len);
1690 le->ctrl = ctrl;
793b883e 1691 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1692
cd28ab6a
SH		 1693
1694 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1695 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1696
1697 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1698 frag->size, PCI_DMA_TODEVICE);
86c6887e 1699
454e6cb6
SH		 1700 if (pci_dma_mapping_error(hw->pdev, mapping))
1701 goto mapping_unwind;
1702
5dce95e5
SH		 1703 upper = upper_32_bits(mapping);
1704 if (upper != sky2->tx_last_upper) {
9b289c33 1705 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1706 le->addr = cpu_to_le32(upper);
1707 sky2->tx_last_upper = upper;
793b883e 1708 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1709 }
1710
6b84daca
SH		 1711 re = sky2->tx_ring + slot;
1712 re->flags = TX_MAP_PAGE;
1713 pci_unmap_addr_set(re, mapaddr, mapping);
1714 pci_unmap_len_set(re, maplen, frag->size);
1715
9b289c33 1716 le = get_tx_le(sky2, &slot);
d6e74b6b 1717 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1718 le->length = cpu_to_le16(frag->size);
1719 le->ctrl = ctrl;
793b883e 1720 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1721 }
6cdbbdf3 1722
6b84daca 1723 re->skb = skb;
cd28ab6a
SH		 1724 le->ctrl |= EOP;
1725
9b289c33
MM		 1726 sky2->tx_prod = slot;
1727
97bda706 1728 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1729 netif_stop_queue(dev);
b19666d9 1730
290d4de5 1731 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1732
cd28ab6a 1733 return NETDEV_TX_OK;
454e6cb6
SH		 1734
1735mapping_unwind:
ee5f68fe 1736 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1737 re = sky2->tx_ring + i;
1738
6b84daca 1739 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1740 }
1741
454e6cb6
SH		 1742mapping_error:
1743 if (net_ratelimit())
1744 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1745 dev_kfree_skb(skb);
1746 return NETDEV_TX_OK;
cd28ab6a
SH		 1747}
1748
cd28ab6a 1749/*
793b883e
SH		 1750 * Free ring elements from starting at tx_cons until "done"
1751 *
481cea4a
SH		 1752 * NB:
1753 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1754 * buffers so make sure not to free skb to early.
481cea4a
SH		 1755 * 2. This may run in parallel start_xmit because the it only
1756 * looks at the tail of the queue of FIFO (tx_cons), not
1757 * the head (tx_prod)
cd28ab6a 1758 */
d11c13e7 1759static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1760{
d11c13e7 1761 struct net_device *dev = sky2->netdev;
291ea614 1762 unsigned idx;
cd28ab6a 1763
ee5f68fe 1764 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1765
291ea614 1766 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1767 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1768 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1769 struct sk_buff *skb = re->skb;
291ea614 1770
6b84daca 1771 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1772
6b84daca 1773 if (skb) {
291ea614
SH		 1774 if (unlikely(netif_msg_tx_done(sky2)))
1775 printk(KERN_DEBUG "%s: tx done %u\n",
1776 dev->name, idx);
3cf26753 1777
7138a0f5 1778 dev->stats.tx_packets++;
bd1c6869
SH		 1779 dev->stats.tx_bytes += skb->len;
1780
724b6942 1781 dev_kfree_skb_any(skb);
2bf56fe2 1782
ee5f68fe 1783 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1784 }
793b883e 1785 }
793b883e 1786
291ea614 1787 sky2->tx_cons = idx;
50432cb5
SH		 1788 smp_mb();
1789
22e11703 1790 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1791 netif_wake_queue(dev);
cd28ab6a
SH		 1792}
1793
264bb4fa 1794static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1795{
a510996b
MM		 1796 /* Disable Force Sync bit and Enable Alloc bit */
1797 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1798 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1799
1800 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1801 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1802 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1803
1804 /* Reset the PCI FIFO of the async Tx queue */
1805 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1806 BMU_RST_SET | BMU_FIFO_RST);
1807
1808 /* Reset the Tx prefetch units */
1809 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1810 PREF_UNIT_RST_SET);
1811
1812 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1813 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1814}
1815
cd28ab6a
SH		 1816/* Network shutdown */
1817static int sky2_down(struct net_device *dev)
1818{
1819 struct sky2_port *sky2 = netdev_priv(dev);
1820 struct sky2_hw *hw = sky2->hw;
1821 unsigned port = sky2->port;
1822 u16 ctrl;
e07b1aa8 1823 u32 imask;
cd28ab6a 1824
1b537565
SH		 1825 /* Never really got started! */
1826 if (!sky2->tx_le)
1827 return 0;
1828
cd28ab6a
SH		 1829 if (netif_msg_ifdown(sky2))
1830 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1831
d104acaf
SH		 1832 /* Force flow control off */
1833 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1834
cd28ab6a
SH		 1835 /* Stop transmitter */
1836 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1837 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1838
1839 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1840 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1841
1842 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1843 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1844 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1845
1846 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1847
1848 /* Workaround shared GMAC reset */
793b883e
SH		 1849 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1850 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1851 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1852
cd28ab6a 1853 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1854
6c83504f
SH		 1855 /* Force any delayed status interrrupt and NAPI */
1856 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1857 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1858 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1859 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1860
a947a39d
MM		 1861 sky2_rx_stop(sky2);
1862
1863 /* Disable port IRQ */
1864 imask = sky2_read32(hw, B0_IMSK);
1865 imask &= ~portirq_msk[port];
1866 sky2_write32(hw, B0_IMSK, imask);
1867 sky2_read32(hw, B0_IMSK);
1868
6c83504f
SH		 1869 synchronize_irq(hw->pdev->irq);
1870 napi_synchronize(&hw->napi);
1871
0da6d7b3 1872 spin_lock_bh(&sky2->phy_lock);
b96936da 1873 sky2_phy_power_down(hw, port);
0da6d7b3 1874 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1875
264bb4fa
MM		 1876 sky2_tx_reset(hw, port);
1877
481cea4a
SH		 1878 /* Free any pending frames stuck in HW queue */
1879 sky2_tx_complete(sky2, sky2->tx_prod);
1880
cd28ab6a
SH		 1881 sky2_rx_clean(sky2);
1882
1883 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1884 sky2->rx_le, sky2->rx_le_map);
1885 kfree(sky2->rx_ring);
1886
1887 pci_free_consistent(hw->pdev,
ee5f68fe 1888 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1889 sky2->tx_le, sky2->tx_le_map);
1890 kfree(sky2->tx_ring);
1891
1b537565
SH		 1892 sky2->tx_le = NULL;
1893 sky2->rx_le = NULL;
1894
1895 sky2->rx_ring = NULL;
1896 sky2->tx_ring = NULL;
1897
cd28ab6a
SH		 1898 return 0;
1899}
1900
1901static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1902{
ea76e635 1903 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1904 return SPEED_1000;
1905
05745c4a
SH		 1906 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1907 if (aux & PHY_M_PS_SPEED_100)
1908 return SPEED_100;
1909 else
1910 return SPEED_10;
1911 }
cd28ab6a
SH		 1912
1913 switch (aux & PHY_M_PS_SPEED_MSK) {
1914 case PHY_M_PS_SPEED_1000:
1915 return SPEED_1000;
1916 case PHY_M_PS_SPEED_100:
1917 return SPEED_100;
1918 default:
1919 return SPEED_10;
1920 }
1921}
1922
1923static void sky2_link_up(struct sky2_port *sky2)
1924{
1925 struct sky2_hw *hw = sky2->hw;
1926 unsigned port = sky2->port;
1927 u16 reg;
16ad91e1
SH		 1928 static const char *fc_name[] = {
1929 [FC_NONE] = "none",
1930 [FC_TX] = "tx",
1931 [FC_RX] = "rx",
1932 [FC_BOTH] = "both",
1933 };
cd28ab6a 1934
cd28ab6a 1935 /* enable Rx/Tx */
2eaba1a2 1936 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1937 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1938 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1939
1940 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1941
1942 netif_carrier_on(sky2->netdev);
cd28ab6a 1943
75e80683 1944 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1945
cd28ab6a 1946 /* Turn on link LED */
793b883e 1947 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1948 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1949
1950 if (netif_msg_link(sky2))
1951 printk(KERN_INFO PFX
d571b694 1952 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1953 sky2->netdev->name, sky2->speed,
1954 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1955 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1956}
1957
1958static void sky2_link_down(struct sky2_port *sky2)
1959{
1960 struct sky2_hw *hw = sky2->hw;
1961 unsigned port = sky2->port;
1962 u16 reg;
1963
1964 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1965
1966 reg = gma_read16(hw, port, GM_GP_CTRL);
1967 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1968 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1969
cd28ab6a 1970 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1971
1972 /* Turn on link LED */
1973 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1974
1975 if (netif_msg_link(sky2))
1976 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1977
cd28ab6a
SH		 1978 sky2_phy_init(hw, port);
1979}
1980
16ad91e1
SH		 1981static enum flow_control sky2_flow(int rx, int tx)
1982{
1983 if (rx)
1984 return tx ? FC_BOTH : FC_RX;
1985 else
1986 return tx ? FC_TX : FC_NONE;
1987}
1988
793b883e
SH		 1989static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1990{
1991 struct sky2_hw *hw = sky2->hw;
1992 unsigned port = sky2->port;
da4c1ff4 1993 u16 advert, lpa;
793b883e 1994
da4c1ff4 1995 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1996 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1997 if (lpa & PHY_M_AN_RF) {
1998 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1999 return -1;
2000 }
2001
793b883e
SH		 2002 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2003 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2004 sky2->netdev->name);
2005 return -1;
2006 }
2007
793b883e 2008 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2009 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2010
da4c1ff4
SH		 2011 /* Since the pause result bits seem to in different positions on
2012 * different chips. look at registers.
2013 */
ea76e635 2014 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2015 /* Shift for bits in fiber PHY */
2016 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2017 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2018
2019 if (advert & ADVERTISE_1000XPAUSE)
2020 advert |= ADVERTISE_PAUSE_CAP;
2021 if (advert & ADVERTISE_1000XPSE_ASYM)
2022 advert |= ADVERTISE_PAUSE_ASYM;
2023 if (lpa & LPA_1000XPAUSE)
2024 lpa |= LPA_PAUSE_CAP;
2025 if (lpa & LPA_1000XPAUSE_ASYM)
2026 lpa |= LPA_PAUSE_ASYM;
2027 }
793b883e 2028
da4c1ff4
SH		 2029 sky2->flow_status = FC_NONE;
2030 if (advert & ADVERTISE_PAUSE_CAP) {
2031 if (lpa & LPA_PAUSE_CAP)
2032 sky2->flow_status = FC_BOTH;
2033 else if (advert & ADVERTISE_PAUSE_ASYM)
2034 sky2->flow_status = FC_RX;
2035 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2036 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2037 sky2->flow_status = FC_TX;
2038 }
793b883e 2039
16ad91e1 2040 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2041 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2042 sky2->flow_status = FC_NONE;
2eaba1a2 2043
da4c1ff4 2044 if (sky2->flow_status & FC_TX)
793b883e
SH		 2045 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2046 else
2047 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2048
2049 return 0;
2050}
cd28ab6a 2051
e07b1aa8
SH		 2052/* Interrupt from PHY */
2053static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2054{
e07b1aa8
SH		 2055 struct net_device *dev = hw->dev[port];
2056 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2057 u16 istatus, phystat;
2058
ebc646f6
SH		 2059 if (!netif_running(dev))
2060 return;
2061
e07b1aa8
SH		 2062 spin_lock(&sky2->phy_lock);
2063 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2064 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2065
cd28ab6a
SH		 2066 if (netif_msg_intr(sky2))
2067 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2068 sky2->netdev->name, istatus, phystat);
2069
0ea065e5 2070 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 2071 if (sky2_autoneg_done(sky2, phystat) == 0)
2072 sky2_link_up(sky2);
2073 goto out;
2074 }
cd28ab6a 2075
793b883e
SH		 2076 if (istatus & PHY_M_IS_LSP_CHANGE)
2077 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2078
793b883e
SH		 2079 if (istatus & PHY_M_IS_DUP_CHANGE)
2080 sky2->duplex =
2081 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2082
793b883e
SH		 2083 if (istatus & PHY_M_IS_LST_CHANGE) {
2084 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2085 sky2_link_up(sky2);
793b883e
SH		 2086 else
2087 sky2_link_down(sky2);
cd28ab6a 2088 }
793b883e 2089out:
e07b1aa8 2090 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2091}
2092
62335ab0 2093/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2094 * and tx queue is full (stopped).
2095 */
cd28ab6a
SH		 2096static void sky2_tx_timeout(struct net_device *dev)
2097{
2098 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2099 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2100
2101 if (netif_msg_timer(sky2))
2102 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2103
8f24664d 2104 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2105 dev->name, sky2->tx_cons, sky2->tx_prod,
2106 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2107 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2108
81906791
SH		 2109 /* can't restart safely under softirq */
2110 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2111}
2112
2113static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2114{
6b1a3aef 2115 struct sky2_port *sky2 = netdev_priv(dev);
2116 struct sky2_hw *hw = sky2->hw;
b628ed98 2117 unsigned port = sky2->port;
6b1a3aef 2118 int err;
2119 u16 ctl, mode;
e07b1aa8 2120 u32 imask;
cd28ab6a
SH		 2121
2122 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2123 return -EINVAL;
2124
05745c4a
SH		 2125 if (new_mtu > ETH_DATA_LEN &&
2126 (hw->chip_id == CHIP_ID_YUKON_FE ||
2127 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2128 return -EINVAL;
2129
6b1a3aef 2130 if (!netif_running(dev)) {
2131 dev->mtu = new_mtu;
2132 return 0;
2133 }
2134
e07b1aa8 2135 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2136 sky2_write32(hw, B0_IMSK, 0);
2137
018d1c66 2138 dev->trans_start = jiffies; /* prevent tx timeout */
2139 netif_stop_queue(dev);
bea3348e 2140 napi_disable(&hw->napi);
018d1c66 2141
e07b1aa8
SH		 2142 synchronize_irq(hw->pdev->irq);
2143
39dbd958 2144 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2145 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2146
2147 ctl = gma_read16(hw, port, GM_GP_CTRL);
2148 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2149 sky2_rx_stop(sky2);
2150 sky2_rx_clean(sky2);
cd28ab6a
SH		 2151
2152 dev->mtu = new_mtu;
14d0263f 2153
6b1a3aef 2154 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2155 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2156
2157 if (dev->mtu > ETH_DATA_LEN)
2158 mode |= GM_SMOD_JUMBO_ENA;
2159
b628ed98 2160 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2161
b628ed98 2162 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2163
6b1a3aef 2164 err = sky2_rx_start(sky2);
e07b1aa8 2165 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2166
d1d08d12 2167 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2168 napi_enable(&hw->napi);
2169
1b537565
SH		 2170 if (err)
2171 dev_close(dev);
2172 else {
b628ed98 2173 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2174
1b537565
SH		 2175 netif_wake_queue(dev);
2176 }
2177
cd28ab6a
SH		 2178 return err;
2179}
2180
14d0263f
SH		 2181/* For small just reuse existing skb for next receive */
2182static struct sk_buff *receive_copy(struct sky2_port *sky2,
2183 const struct rx_ring_info *re,
2184 unsigned length)
2185{
2186 struct sk_buff *skb;
2187
2188 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2189 if (likely(skb)) {
2190 skb_reserve(skb, 2);
2191 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2192 length, PCI_DMA_FROMDEVICE);
d626f62b 2193 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2194 skb->ip_summed = re->skb->ip_summed;
2195 skb->csum = re->skb->csum;
2196 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2197 length, PCI_DMA_FROMDEVICE);
2198 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2199 skb_put(skb, length);
14d0263f
SH		 2200 }
2201 return skb;
2202}
2203
2204/* Adjust length of skb with fragments to match received data */
2205static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2206 unsigned int length)
2207{
2208 int i, num_frags;
2209 unsigned int size;
2210
2211 /* put header into skb */
2212 size = min(length, hdr_space);
2213 skb->tail += size;
2214 skb->len += size;
2215 length -= size;
2216
2217 num_frags = skb_shinfo(skb)->nr_frags;
2218 for (i = 0; i < num_frags; i++) {
2219 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2220
2221 if (length == 0) {
2222 /* don't need this page */
2223 __free_page(frag->page);
2224 --skb_shinfo(skb)->nr_frags;
2225 } else {
2226 size = min(length, (unsigned) PAGE_SIZE);
2227
2228 frag->size = size;
2229 skb->data_len += size;
2230 skb->truesize += size;
2231 skb->len += size;
2232 length -= size;
2233 }
2234 }
2235}
2236
2237/* Normal packet - take skb from ring element and put in a new one */
2238static struct sk_buff *receive_new(struct sky2_port *sky2,
2239 struct rx_ring_info *re,
2240 unsigned int length)
2241{
2242 struct sk_buff *skb, *nskb;
2243 unsigned hdr_space = sky2->rx_data_size;
2244
14d0263f
SH		 2245 /* Don't be tricky about reusing pages (yet) */
2246 nskb = sky2_rx_alloc(sky2);
2247 if (unlikely(!nskb))
2248 return NULL;
2249
2250 skb = re->skb;
2251 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2252
2253 prefetch(skb->data);
2254 re->skb = nskb;
454e6cb6
SH		 2255 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2256 dev_kfree_skb(nskb);
2257 re->skb = skb;
2258 return NULL;
2259 }
14d0263f
SH		 2260
2261 if (skb_shinfo(skb)->nr_frags)
2262 skb_put_frags(skb, hdr_space, length);
2263 else
489b10c1 2264 skb_put(skb, length);
14d0263f
SH		 2265 return skb;
2266}
2267
cd28ab6a
SH		 2268/*
2269 * Receive one packet.
d571b694 2270 * For larger packets, get new buffer.
cd28ab6a 2271 */
497d7c86 2272static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2273 u16 length, u32 status)
2274{
497d7c86 2275 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2276 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2277 struct sk_buff *skb = NULL;
d6532232
SH		 2278 u16 count = (status & GMR_FS_LEN) >> 16;
2279
2280#ifdef SKY2_VLAN_TAG_USED
2281 /* Account for vlan tag */
2282 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2283 count -= VLAN_HLEN;
2284#endif
cd28ab6a
SH		 2285
2286 if (unlikely(netif_msg_rx_status(sky2)))
2287 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2288 dev->name, sky2->rx_next, status, length);
cd28ab6a 2289
793b883e 2290 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2291 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2292
3b12e014
SH		 2293 /* This chip has hardware problems that generates bogus status.
2294 * So do only marginal checking and expect higher level protocols
2295 * to handle crap frames.
2296 */
2297 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2298 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2299 length != count)
2300 goto okay;
2301
42eeea01 2302 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2303 goto error;
2304
42eeea01 2305 if (!(status & GMR_FS_RX_OK))
2306 goto resubmit;
2307
d6532232
SH		 2308 /* if length reported by DMA does not match PHY, packet was truncated */
2309 if (length != count)
3b12e014 2310 goto len_error;
71749531 2311
3b12e014 2312okay:
14d0263f
SH		 2313 if (length < copybreak)
2314 skb = receive_copy(sky2, re, length);
2315 else
2316 skb = receive_new(sky2, re, length);
793b883e 2317resubmit:
14d0263f 2318 sky2_rx_submit(sky2, re);
79e57d32 2319
cd28ab6a
SH		 2320 return skb;
2321
3b12e014 2322len_error:
71749531
SH		 2323 /* Truncation of overlength packets
2324 causes PHY length to not match MAC length */
7138a0f5 2325 ++dev->stats.rx_length_errors;
d6532232 2326 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2327 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2328 dev->name, status, length);
d6532232 2329 goto resubmit;
71749531 2330
cd28ab6a 2331error:
7138a0f5 2332 ++dev->stats.rx_errors;
b6d77734 2333 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2334 dev->stats.rx_over_errors++;
b6d77734
SH		 2335 goto resubmit;
2336 }
6e15b712 2337
3be92a70 2338 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2339 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2340 dev->name, status, length);
793b883e
SH		 2341
2342 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2343 dev->stats.rx_length_errors++;
cd28ab6a 2344 if (status & GMR_FS_FRAGMENT)
7138a0f5 2345 dev->stats.rx_frame_errors++;
cd28ab6a 2346 if (status & GMR_FS_CRC_ERR)
7138a0f5 2347 dev->stats.rx_crc_errors++;
79e57d32 2348
793b883e 2349 goto resubmit;
cd28ab6a
SH		 2350}
2351
e07b1aa8
SH		 2352/* Transmit complete */
2353static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2354{
e07b1aa8 2355 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2356
49d4b8ba 2357 if (netif_running(dev))
e07b1aa8 2358 sky2_tx_complete(sky2, last);
cd28ab6a
SH		 2359}
2360
37e5a243
SH		 2361static inline void sky2_skb_rx(const struct sky2_port *sky2,
2362 u32 status, struct sk_buff *skb)
2363{
2364#ifdef SKY2_VLAN_TAG_USED
2365 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2366 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2367 if (skb->ip_summed == CHECKSUM_NONE)
2368 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2369 else
2370 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2371 vlan_tag, skb);
2372 return;
2373 }
2374#endif
2375 if (skb->ip_summed == CHECKSUM_NONE)
2376 netif_receive_skb(skb);
2377 else
2378 napi_gro_receive(&sky2->hw->napi, skb);
2379}
2380
bf15fe99
SH		 2381static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2382 unsigned packets, unsigned bytes)
2383{
2384 if (packets) {
2385 struct net_device *dev = hw->dev[port];
2386
2387 dev->stats.rx_packets += packets;
2388 dev->stats.rx_bytes += bytes;
2389 dev->last_rx = jiffies;
2390 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2391 }
2392}
2393
e07b1aa8 2394/* Process status response ring */
26691830 2395static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2396{
e07b1aa8 2397 int work_done = 0;
bf15fe99
SH		 2398 unsigned int total_bytes[2] = { 0 };
2399 unsigned int total_packets[2] = { 0 };
a8fd6266 2400
af2a58ac 2401 rmb();
26691830 2402 do {
55c9dd35 2403 struct sky2_port *sky2;
13210ce5 2404 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2405 unsigned port;
13210ce5 2406 struct net_device *dev;
cd28ab6a 2407 struct sk_buff *skb;
cd28ab6a
SH		 2408 u32 status;
2409 u16 length;
ab5adecb
SH		 2410 u8 opcode = le->opcode;
2411
2412 if (!(opcode & HW_OWNER))
2413 break;
cd28ab6a 2414
cb5d9547 2415 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2416
ab5adecb 2417 port = le->css & CSS_LINK_BIT;
69161611 2418 dev = hw->dev[port];
13210ce5 2419 sky2 = netdev_priv(dev);
f65b138c
SH		 2420 length = le16_to_cpu(le->length);
2421 status = le32_to_cpu(le->status);
cd28ab6a 2422
ab5adecb
SH		 2423 le->opcode = 0;
2424 switch (opcode & ~HW_OWNER) {
cd28ab6a 2425 case OP_RXSTAT:
bf15fe99
SH		 2426 total_packets[port]++;
2427 total_bytes[port] += length;
497d7c86 2428 skb = sky2_receive(dev, length, status);
3225b919 2429 if (unlikely(!skb)) {
7138a0f5 2430 dev->stats.rx_dropped++;
55c9dd35 2431 break;
3225b919 2432 }
13210ce5 2433
69161611 2434 /* This chip reports checksum status differently */
05745c4a 2435 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2436 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2437 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2438 (le->css & CSS_TCPUDPCSOK))
2439 skb->ip_summed = CHECKSUM_UNNECESSARY;
2440 else
2441 skb->ip_summed = CHECKSUM_NONE;
2442 }
2443
13210ce5 2444 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2445
37e5a243 2446 sky2_skb_rx(sky2, status, skb);
13210ce5 2447
22e11703 2448 /* Stop after net poll weight */
13210ce5 2449 if (++work_done >= to_do)
2450 goto exit_loop;
cd28ab6a
SH		 2451 break;
2452
d1f13708 2453#ifdef SKY2_VLAN_TAG_USED
2454 case OP_RXVLAN:
2455 sky2->rx_tag = length;
2456 break;
2457
2458 case OP_RXCHKSVLAN:
2459 sky2->rx_tag = length;
2460 /* fall through */
2461#endif
cd28ab6a 2462 case OP_RXCHKS:
0ea065e5 2463 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
87418307
SH		 2464 break;
2465
05745c4a
SH		 2466 /* If this happens then driver assuming wrong format */
2467 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2468 if (net_ratelimit())
2469 printk(KERN_NOTICE "%s: unexpected"
2470 " checksum status\n",
2471 dev->name);
69161611 2472 break;
05745c4a 2473 }
69161611 2474
87418307
SH		 2475 /* Both checksum counters are programmed to start at
2476 * the same offset, so unless there is a problem they
2477 * should match. This failure is an early indication that
2478 * hardware receive checksumming won't work.
2479 */
2480 if (likely(status >> 16 == (status & 0xffff))) {
2481 skb = sky2->rx_ring[sky2->rx_next].skb;
2482 skb->ip_summed = CHECKSUM_COMPLETE;
b9389796 2483 skb->csum = le16_to_cpu(status);
87418307
SH		 2484 } else {
2485 printk(KERN_NOTICE PFX "%s: hardware receive "
2486 "checksum problem (status = %#x)\n",
2487 dev->name, status);
0ea065e5
SH		 2488 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2489
87418307 2490 sky2_write32(sky2->hw,
69161611 2491 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2492 BMU_DIS_RX_CHKSUM);
2493 }
cd28ab6a
SH		 2494 break;
2495
2496 case OP_TXINDEXLE:
13b97b74 2497 /* TX index reports status for both ports */
f55925d7 2498 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2499 if (hw->dev[1])
2500 sky2_tx_done(hw->dev[1],
2501 ((status >> 24) & 0xff)
2502 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2503 break;
2504
cd28ab6a
SH		 2505 default:
2506 if (net_ratelimit())
793b883e 2507 printk(KERN_WARNING PFX
ab5adecb 2508 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2509 }
26691830 2510 } while (hw->st_idx != idx);
cd28ab6a 2511
fe2a24df
SH		 2512 /* Fully processed status ring so clear irq */
2513 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2514
13210ce5 2515exit_loop:
bf15fe99
SH		 2516 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2517 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2518
e07b1aa8 2519 return work_done;
cd28ab6a
SH		 2520}
2521
2522static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2523{
2524 struct net_device *dev = hw->dev[port];
2525
3be92a70
SH		 2526 if (net_ratelimit())
2527 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2528 dev->name, status);
cd28ab6a
SH		 2529
2530 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2531 if (net_ratelimit())
2532 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2533 dev->name);
cd28ab6a
SH		 2534 /* Clear IRQ */
2535 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2536 }
2537
2538 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2539 if (net_ratelimit())
2540 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2541 dev->name);
cd28ab6a
SH		 2542
2543 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2544 }
2545
2546 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2547 if (net_ratelimit())
2548 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2549 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2550 }
2551
2552 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2553 if (net_ratelimit())
2554 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2555 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2556 }
2557
2558 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2559 if (net_ratelimit())
2560 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2561 dev->name);
cd28ab6a
SH		 2562 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2563 }
2564}
2565
2566static void sky2_hw_intr(struct sky2_hw *hw)
2567{
555382cb 2568 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2569 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2570 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2571
2572 status &= hwmsk;
cd28ab6a 2573
793b883e 2574 if (status & Y2_IS_TIST_OV)
cd28ab6a 2575 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2576
2577 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2578 u16 pci_err;
2579
82637e80 2580 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2581 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2582 if (net_ratelimit())
555382cb 2583 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2584 pci_err);
cd28ab6a 2585
b32f40c4 2586 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2587 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2588 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2589 }
2590
2591 if (status & Y2_IS_PCI_EXP) {
d571b694 2592 /* PCI-Express uncorrectable Error occurred */
555382cb 2593 u32 err;
cd28ab6a 2594
82637e80 2595 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2596 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2597 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2598 0xfffffffful);
3be92a70 2599 if (net_ratelimit())
555382cb 2600 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2601
7782c8c4 2602 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2603 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2604 }
2605
2606 if (status & Y2_HWE_L1_MASK)
2607 sky2_hw_error(hw, 0, status);
2608 status >>= 8;
2609 if (status & Y2_HWE_L1_MASK)
2610 sky2_hw_error(hw, 1, status);
2611}
2612
2613static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2614{
2615 struct net_device *dev = hw->dev[port];
2616 struct sky2_port *sky2 = netdev_priv(dev);
2617 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2618
2619 if (netif_msg_intr(sky2))
2620 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2621 dev->name, status);
2622
a3caeada
SH		 2623 if (status & GM_IS_RX_CO_OV)
2624 gma_read16(hw, port, GM_RX_IRQ_SRC);
2625
2626 if (status & GM_IS_TX_CO_OV)
2627 gma_read16(hw, port, GM_TX_IRQ_SRC);
2628
cd28ab6a 2629 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2630 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2631 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2632 }
2633
2634 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2635 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2636 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2637 }
cd28ab6a
SH		 2638}
2639
40b01727 2640/* This should never happen it is a bug. */
c119731d 2641static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2642{
2643 struct net_device *dev = hw->dev[port];
c119731d 2644 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2645
c119731d
SH		 2646 dev_err(&hw->pdev->dev, PFX
2647 "%s: descriptor error q=%#x get=%u put=%u\n",
2648 dev->name, (unsigned) q, (unsigned) idx,
2649 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2650
40b01727 2651 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2652}
cd28ab6a 2653
75e80683
SH		 2654static int sky2_rx_hung(struct net_device *dev)
2655{
2656 struct sky2_port *sky2 = netdev_priv(dev);
2657 struct sky2_hw *hw = sky2->hw;
2658 unsigned port = sky2->port;
2659 unsigned rxq = rxqaddr[port];
2660 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2661 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2662 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2663 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2664
2665 /* If idle and MAC or PCI is stuck */
2666 if (sky2->check.last == dev->last_rx &&
2667 ((mac_rp == sky2->check.mac_rp &&
2668 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2669 /* Check if the PCI RX hang */
2670 (fifo_rp == sky2->check.fifo_rp &&
2671 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2672 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2673 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2674 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2675 return 1;
2676 } else {
2677 sky2->check.last = dev->last_rx;
2678 sky2->check.mac_rp = mac_rp;
2679 sky2->check.mac_lev = mac_lev;
2680 sky2->check.fifo_rp = fifo_rp;
2681 sky2->check.fifo_lev = fifo_lev;
2682 return 0;
2683 }
2684}
2685
32c2c300 2686static void sky2_watchdog(unsigned long arg)
d27ed387 2687{
01bd7564 2688 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2689
75e80683 2690 /* Check for lost IRQ once a second */
32c2c300 2691 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2692 napi_schedule(&hw->napi);
75e80683
SH		 2693 } else {
2694 int i, active = 0;
2695
2696 for (i = 0; i < hw->ports; i++) {
bea3348e 2697 struct net_device *dev = hw->dev[i];
75e80683
SH		 2698 if (!netif_running(dev))
2699 continue;
2700 ++active;
2701
2702 /* For chips with Rx FIFO, check if stuck */
39dbd958 2703 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2704 sky2_rx_hung(dev)) {
2705 pr_info(PFX "%s: receiver hang detected\n",
2706 dev->name);
2707 schedule_work(&hw->restart_work);
2708 return;
2709 }
2710 }
2711
2712 if (active == 0)
2713 return;
32c2c300 2714 }
01bd7564 2715
75e80683 2716 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2717}
2718
40b01727
SH		 2719/* Hardware/software error handling */
2720static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2721{
40b01727
SH		 2722 if (net_ratelimit())
2723 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2724
1e5f1283
SH		 2725 if (status & Y2_IS_HW_ERR)
2726 sky2_hw_intr(hw);
d257924e 2727
1e5f1283
SH		 2728 if (status & Y2_IS_IRQ_MAC1)
2729 sky2_mac_intr(hw, 0);
cd28ab6a 2730
1e5f1283
SH		 2731 if (status & Y2_IS_IRQ_MAC2)
2732 sky2_mac_intr(hw, 1);
cd28ab6a 2733
1e5f1283 2734 if (status & Y2_IS_CHK_RX1)
c119731d 2735 sky2_le_error(hw, 0, Q_R1);
d257924e 2736
1e5f1283 2737 if (status & Y2_IS_CHK_RX2)
c119731d 2738 sky2_le_error(hw, 1, Q_R2);
d257924e 2739
1e5f1283 2740 if (status & Y2_IS_CHK_TXA1)
c119731d 2741 sky2_le_error(hw, 0, Q_XA1);
d257924e 2742
1e5f1283 2743 if (status & Y2_IS_CHK_TXA2)
c119731d 2744 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2745}
2746
bea3348e 2747static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2748{
bea3348e 2749 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2750 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2751 int work_done = 0;
26691830 2752 u16 idx;
40b01727
SH		 2753
2754 if (unlikely(status & Y2_IS_ERROR))
2755 sky2_err_intr(hw, status);
2756
2757 if (status & Y2_IS_IRQ_PHY1)
2758 sky2_phy_intr(hw, 0);
2759
2760 if (status & Y2_IS_IRQ_PHY2)
2761 sky2_phy_intr(hw, 1);
cd28ab6a 2762
26691830
SH		 2763 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2764 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2765
2766 if (work_done >= work_limit)
26691830
SH		 2767 goto done;
2768 }
6f535763 2769
26691830
SH		 2770 napi_complete(napi);
2771 sky2_read32(hw, B0_Y2_SP_LISR);
2772done:
6f535763 2773
bea3348e 2774 return work_done;
e07b1aa8
SH		 2775}
2776
7d12e780 2777static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2778{
2779 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2780 u32 status;
2781
2782 /* Reading this mask interrupts as side effect */
2783 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2784 if (status == 0 || status == ~0)
2785 return IRQ_NONE;
793b883e 2786
e07b1aa8 2787 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2788
2789 napi_schedule(&hw->napi);
793b883e 2790
cd28ab6a
SH		 2791 return IRQ_HANDLED;
2792}
2793
2794#ifdef CONFIG_NET_POLL_CONTROLLER
2795static void sky2_netpoll(struct net_device *dev)
2796{
2797 struct sky2_port *sky2 = netdev_priv(dev);
2798
bea3348e 2799 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2800}
2801#endif
2802
2803/* Chip internal frequency for clock calculations */
05745c4a 2804static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2805{
793b883e 2806 switch (hw->chip_id) {
cd28ab6a 2807 case CHIP_ID_YUKON_EC:
5a5b1ea0 2808 case CHIP_ID_YUKON_EC_U:
93745494 2809 case CHIP_ID_YUKON_EX:
ed4d4161 2810 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2811 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2812 return 125;
2813
cd28ab6a 2814 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2815 return 100;
2816
2817 case CHIP_ID_YUKON_FE_P:
2818 return 50;
2819
2820 case CHIP_ID_YUKON_XL:
2821 return 156;
2822
2823 default:
2824 BUG();
cd28ab6a
SH		 2825 }
2826}
2827
fb17358f 2828static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2829{
fb17358f 2830 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2831}
2832
fb17358f 2833static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2834{
fb17358f 2835 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2836}
2837
fb17358f 2838
e3173832 2839static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2840{
b89165f2 2841 u8 t8;
cd28ab6a 2842
167f53d0 2843 /* Enable all clocks and check for bad PCI access */
b32f40c4 2844 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2845
cd28ab6a 2846 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2847
cd28ab6a 2848 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2849 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2850
2851 switch(hw->chip_id) {
2852 case CHIP_ID_YUKON_XL:
39dbd958 2853 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2854 break;
2855
2856 case CHIP_ID_YUKON_EC_U:
2857 hw->flags = SKY2_HW_GIGABIT
2858 | SKY2_HW_NEWER_PHY
2859 | SKY2_HW_ADV_POWER_CTL;
2860 break;
2861
2862 case CHIP_ID_YUKON_EX:
2863 hw->flags = SKY2_HW_GIGABIT
2864 | SKY2_HW_NEWER_PHY
2865 | SKY2_HW_NEW_LE
2866 | SKY2_HW_ADV_POWER_CTL;
2867
2868 /* New transmit checksum */
2869 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2870 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2871 break;
2872
2873 case CHIP_ID_YUKON_EC:
2874 /* This rev is really old, and requires untested workarounds */
2875 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2876 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2877 return -EOPNOTSUPP;
2878 }
39dbd958 2879 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2880 break;
2881
2882 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2883 break;
2884
05745c4a
SH		 2885 case CHIP_ID_YUKON_FE_P:
2886 hw->flags = SKY2_HW_NEWER_PHY
2887 | SKY2_HW_NEW_LE
2888 | SKY2_HW_AUTO_TX_SUM
2889 | SKY2_HW_ADV_POWER_CTL;
2890 break;
ed4d4161
SH		 2891
2892 case CHIP_ID_YUKON_SUPR:
2893 hw->flags = SKY2_HW_GIGABIT
2894 | SKY2_HW_NEWER_PHY
2895 | SKY2_HW_NEW_LE
2896 | SKY2_HW_AUTO_TX_SUM
2897 | SKY2_HW_ADV_POWER_CTL;
2898 break;
2899
0ce8b98d
SH		 2900 case CHIP_ID_YUKON_UL_2:
2901 hw->flags = SKY2_HW_GIGABIT
2902 | SKY2_HW_ADV_POWER_CTL;
2903 break;
2904
ea76e635 2905 default:
b02a9258
SH		 2906 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2907 hw->chip_id);
cd28ab6a
SH		 2908 return -EOPNOTSUPP;
2909 }
2910
ea76e635
SH		 2911 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2912 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2913 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2914
e3173832
SH		 2915 hw->ports = 1;
2916 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2917 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2918 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2919 ++hw->ports;
2920 }
2921
2922 return 0;
2923}
2924
2925static void sky2_reset(struct sky2_hw *hw)
2926{
555382cb 2927 struct pci_dev *pdev = hw->pdev;
e3173832 2928 u16 status;
555382cb
SH		 2929 int i, cap;
2930 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2931
cd28ab6a 2932 /* disable ASF */
4f44d8ba
SH		 2933 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2934 status = sky2_read16(hw, HCU_CCSR);
2935 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2936 HCU_CCSR_UC_STATE_MSK);
2937 sky2_write16(hw, HCU_CCSR, status);
2938 } else
2939 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2940 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2941
2942 /* do a SW reset */
2943 sky2_write8(hw, B0_CTST, CS_RST_SET);
2944 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2945
ac93a394
SH		 2946 /* allow writes to PCI config */
2947 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2948
cd28ab6a 2949 /* clear PCI errors, if any */
b32f40c4 2950 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2951 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2952 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2953
2954 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2955
555382cb
SH		 2956 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2957 if (cap) {
7782c8c4
SH		 2958 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2959 0xfffffffful);
555382cb
SH		 2960
2961 /* If error bit is stuck on ignore it */
2962 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2963 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2964 else
555382cb
SH		 2965 hwe_mask |= Y2_IS_PCI_EXP;
2966 }
cd28ab6a 2967
ae306cca 2968 sky2_power_on(hw);
82637e80 2969 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2970
2971 for (i = 0; i < hw->ports; i++) {
2972 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2973 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2974
ed4d4161
SH		 2975 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2976 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2977 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2978 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2979 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2980 }
2981
793b883e
SH		 2982 /* Clear I2C IRQ noise */
2983 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2984
2985 /* turn off hardware timer (unused) */
2986 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2987 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2988
69634ee7
SH		 2989 /* Turn off descriptor polling */
2990 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2991
2992 /* Turn off receive timestamp */
2993 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2994 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2995
2996 /* enable the Tx Arbiters */
2997 for (i = 0; i < hw->ports; i++)
2998 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2999
3000 /* Initialize ram interface */
3001 for (i = 0; i < hw->ports; i++) {
793b883e 3002 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3003
3004 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3005 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3006 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3007 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3008 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3009 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3010 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3011 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3012 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3013 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3014 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3015 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3016 }
3017
555382cb 3018 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3019
cd28ab6a 3020 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3021 sky2_gmac_reset(hw, i);
cd28ab6a 3022
cd28ab6a
SH		 3023 memset(hw->st_le, 0, STATUS_LE_BYTES);
3024 hw->st_idx = 0;
3025
3026 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3027 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3028
3029 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3030 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3031
3032 /* Set the list last index */
793b883e 3033 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3034
290d4de5
SH		 3035 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3036 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3037
290d4de5
SH		 3038 /* set Status-FIFO ISR watermark */
3039 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3040 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3041 else
3042 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3043
290d4de5 3044 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3045 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3046 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3047
793b883e 3048 /* enable status unit */
cd28ab6a
SH		 3049 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3050
3051 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3052 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3053 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3054}
3055
af18d8b8
SH		 3056/* Take device down (offline).
3057 * Equivalent to doing dev_stop() but this does not
3058 * inform upper layers of the transistion.
3059 */
3060static void sky2_detach(struct net_device *dev)
3061{
3062 if (netif_running(dev)) {
3063 netif_device_detach(dev); /* stop txq */
3064 sky2_down(dev);
3065 }
3066}
3067
3068/* Bring device back after doing sky2_detach */
3069static int sky2_reattach(struct net_device *dev)
3070{
3071 int err = 0;
3072
3073 if (netif_running(dev)) {
3074 err = sky2_up(dev);
3075 if (err) {
3076 printk(KERN_INFO PFX "%s: could not restart %d\n",
3077 dev->name, err);
3078 dev_close(dev);
3079 } else {
3080 netif_device_attach(dev);
3081 sky2_set_multicast(dev);
3082 }
3083 }
3084
3085 return err;
3086}
3087
81906791
SH		 3088static void sky2_restart(struct work_struct *work)
3089{
3090 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
af18d8b8 3091 int i;
81906791 3092
81906791 3093 rtnl_lock();
af18d8b8
SH		 3094 for (i = 0; i < hw->ports; i++)
3095 sky2_detach(hw->dev[i]);
81906791 3096
8cfcbe99
SH		 3097 napi_disable(&hw->napi);
3098 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3099 sky2_reset(hw);
3100 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3101 napi_enable(&hw->napi);
81906791 3102
af18d8b8
SH		 3103 for (i = 0; i < hw->ports; i++)
3104 sky2_reattach(hw->dev[i]);
81906791 3105
81906791
SH		 3106 rtnl_unlock();
3107}
3108
e3173832
SH		 3109static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3110{
3111 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3112}
3113
3114static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3115{
3116 const struct sky2_port *sky2 = netdev_priv(dev);
3117
3118 wol->supported = sky2_wol_supported(sky2->hw);
3119 wol->wolopts = sky2->wol;
3120}
3121
3122static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3123{
3124 struct sky2_port *sky2 = netdev_priv(dev);
3125 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3126
9d731d77
RW		 3127 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3128 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3129 return -EOPNOTSUPP;
3130
3131 sky2->wol = wol->wolopts;
3132
05745c4a
SH		 3133 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3134 hw->chip_id == CHIP_ID_YUKON_EX ||
3135 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3136 sky2_write32(hw, B0_CTST, sky2->wol
3137 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3138
9d731d77
RW		 3139 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3140
e3173832
SH		 3141 if (!netif_running(dev))
3142 sky2_wol_init(sky2);
cd28ab6a
SH		 3143 return 0;
3144}
3145
28bd181a 3146static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3147{
b89165f2
SH		 3148 if (sky2_is_copper(hw)) {
3149 u32 modes = SUPPORTED_10baseT_Half
3150 | SUPPORTED_10baseT_Full
3151 | SUPPORTED_100baseT_Half
3152 | SUPPORTED_100baseT_Full
3153 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3154
ea76e635 3155 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3156 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3157 | SUPPORTED_1000baseT_Full;
3158 return modes;
cd28ab6a 3159 } else
b89165f2
SH		 3160 return SUPPORTED_1000baseT_Half
3161 | SUPPORTED_1000baseT_Full
3162 | SUPPORTED_Autoneg
3163 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3164}
3165
793b883e 3166static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3167{
3168 struct sky2_port *sky2 = netdev_priv(dev);
3169 struct sky2_hw *hw = sky2->hw;
3170
3171 ecmd->transceiver = XCVR_INTERNAL;
3172 ecmd->supported = sky2_supported_modes(hw);
3173 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3174 if (sky2_is_copper(hw)) {
cd28ab6a 3175 ecmd->port = PORT_TP;
b89165f2
SH		 3176 ecmd->speed = sky2->speed;
3177 } else {
3178 ecmd->speed = SPEED_1000;
cd28ab6a 3179 ecmd->port = PORT_FIBRE;
b89165f2 3180 }
cd28ab6a
SH		 3181
3182 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3183 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3184 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3185 ecmd->duplex = sky2->duplex;
3186 return 0;
3187}
3188
3189static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3190{
3191 struct sky2_port *sky2 = netdev_priv(dev);
3192 const struct sky2_hw *hw = sky2->hw;
3193 u32 supported = sky2_supported_modes(hw);
3194
3195 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3196 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3197 ecmd->advertising = supported;
3198 sky2->duplex = -1;
3199 sky2->speed = -1;
3200 } else {
3201 u32 setting;
3202
793b883e 3203 switch (ecmd->speed) {
cd28ab6a
SH		 3204 case SPEED_1000:
3205 if (ecmd->duplex == DUPLEX_FULL)
3206 setting = SUPPORTED_1000baseT_Full;
3207 else if (ecmd->duplex == DUPLEX_HALF)
3208 setting = SUPPORTED_1000baseT_Half;
3209 else
3210 return -EINVAL;
3211 break;
3212 case SPEED_100:
3213 if (ecmd->duplex == DUPLEX_FULL)
3214 setting = SUPPORTED_100baseT_Full;
3215 else if (ecmd->duplex == DUPLEX_HALF)
3216 setting = SUPPORTED_100baseT_Half;
3217 else
3218 return -EINVAL;
3219 break;
3220
3221 case SPEED_10:
3222 if (ecmd->duplex == DUPLEX_FULL)
3223 setting = SUPPORTED_10baseT_Full;
3224 else if (ecmd->duplex == DUPLEX_HALF)
3225 setting = SUPPORTED_10baseT_Half;
3226 else
3227 return -EINVAL;
3228 break;
3229 default:
3230 return -EINVAL;
3231 }
3232
3233 if ((setting & supported) == 0)
3234 return -EINVAL;
3235
3236 sky2->speed = ecmd->speed;
3237 sky2->duplex = ecmd->duplex;
0ea065e5 3238 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3239 }
3240
cd28ab6a
SH		 3241 sky2->advertising = ecmd->advertising;
3242
d1b139c0 3243 if (netif_running(dev)) {
1b537565 3244 sky2_phy_reinit(sky2);
d1b139c0
SH		 3245 sky2_set_multicast(dev);
3246 }
cd28ab6a
SH		 3247
3248 return 0;
3249}
3250
3251static void sky2_get_drvinfo(struct net_device *dev,
3252 struct ethtool_drvinfo *info)
3253{
3254 struct sky2_port *sky2 = netdev_priv(dev);
3255
3256 strcpy(info->driver, DRV_NAME);
3257 strcpy(info->version, DRV_VERSION);
3258 strcpy(info->fw_version, "N/A");
3259 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3260}
3261
3262static const struct sky2_stat {
793b883e
SH		 3263 char name[ETH_GSTRING_LEN];
3264 u16 offset;
cd28ab6a
SH		 3265} sky2_stats[] = {
3266 { "tx_bytes", GM_TXO_OK_HI },
3267 { "rx_bytes", GM_RXO_OK_HI },
3268 { "tx_broadcast", GM_TXF_BC_OK },
3269 { "rx_broadcast", GM_RXF_BC_OK },
3270 { "tx_multicast", GM_TXF_MC_OK },
3271 { "rx_multicast", GM_RXF_MC_OK },
3272 { "tx_unicast", GM_TXF_UC_OK },
3273 { "rx_unicast", GM_RXF_UC_OK },
3274 { "tx_mac_pause", GM_TXF_MPAUSE },
3275 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3276 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3277 { "late_collision",GM_TXF_LAT_COL },
3278 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3279 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3280 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3281
d2604540 3282 { "rx_short", GM_RXF_SHT },
cd28ab6a 3283 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3284 { "rx_64_byte_packets", GM_RXF_64B },
3285 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3286 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3287 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3288 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3289 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3290 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3291 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3292 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3293 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3294 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3295
3296 { "tx_64_byte_packets", GM_TXF_64B },
3297 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3298 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3299 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3300 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3301 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3302 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3303 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3304};
3305
cd28ab6a
SH		 3306static u32 sky2_get_rx_csum(struct net_device *dev)
3307{
3308 struct sky2_port *sky2 = netdev_priv(dev);
3309
0ea065e5 3310 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3311}
3312
3313static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3314{
3315 struct sky2_port *sky2 = netdev_priv(dev);
3316
0ea065e5
SH		 3317 if (data)
3318 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3319 else
3320 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3321
cd28ab6a
SH		 3322 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3323 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3324
3325 return 0;
3326}
3327
3328static u32 sky2_get_msglevel(struct net_device *netdev)
3329{
3330 struct sky2_port *sky2 = netdev_priv(netdev);
3331 return sky2->msg_enable;
3332}
3333
9a7ae0a9
SH		 3334static int sky2_nway_reset(struct net_device *dev)
3335{
3336 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3337
0ea065e5 3338 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3339 return -EINVAL;
3340
1b537565 3341 sky2_phy_reinit(sky2);
d1b139c0 3342 sky2_set_multicast(dev);
9a7ae0a9
SH		 3343
3344 return 0;
3345}
3346
793b883e 3347static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3348{
3349 struct sky2_hw *hw = sky2->hw;
3350 unsigned port = sky2->port;
3351 int i;
3352
3353 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3354 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3355 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3356 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3357
793b883e 3358 for (i = 2; i < count; i++)
cd28ab6a
SH		 3359 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3360}
3361
cd28ab6a
SH		 3362static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3363{
3364 struct sky2_port *sky2 = netdev_priv(netdev);
3365 sky2->msg_enable = value;
3366}
3367
b9f2c044 3368static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3369{
b9f2c044
JG		 3370 switch (sset) {
3371 case ETH_SS_STATS:
3372 return ARRAY_SIZE(sky2_stats);
3373 default:
3374 return -EOPNOTSUPP;
3375 }
cd28ab6a
SH		 3376}
3377
3378static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3379 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3380{
3381 struct sky2_port *sky2 = netdev_priv(dev);
3382
793b883e 3383 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3384}
3385
793b883e 3386static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3387{
3388 int i;
3389
3390 switch (stringset) {
3391 case ETH_SS_STATS:
3392 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3393 memcpy(data + i * ETH_GSTRING_LEN,
3394 sky2_stats[i].name, ETH_GSTRING_LEN);
3395 break;
3396 }
3397}
3398
cd28ab6a
SH		 3399static int sky2_set_mac_address(struct net_device *dev, void *p)
3400{
3401 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3402 struct sky2_hw *hw = sky2->hw;
3403 unsigned port = sky2->port;
3404 const struct sockaddr *addr = p;
cd28ab6a
SH		 3405
3406 if (!is_valid_ether_addr(addr->sa_data))
3407 return -EADDRNOTAVAIL;
3408
cd28ab6a 3409 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3410 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3411 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3412 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3413 dev->dev_addr, ETH_ALEN);
1b537565 3414
a8ab1ec0
SH		 3415 /* virtual address for data */
3416 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3417
3418 /* physical address: used for pause frames */
3419 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3420
3421 return 0;
cd28ab6a
SH		 3422}
3423
a052b52f
SH		 3424static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3425{
3426 u32 bit;
3427
3428 bit = ether_crc(ETH_ALEN, addr) & 63;
3429 filter[bit >> 3] |= 1 << (bit & 7);
3430}
3431
cd28ab6a
SH		 3432static void sky2_set_multicast(struct net_device *dev)
3433{
3434 struct sky2_port *sky2 = netdev_priv(dev);
3435 struct sky2_hw *hw = sky2->hw;
3436 unsigned port = sky2->port;
3437 struct dev_mc_list *list = dev->mc_list;
3438 u16 reg;
3439 u8 filter[8];
a052b52f
SH		 3440 int rx_pause;
3441 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3442
a052b52f 3443 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3444 memset(filter, 0, sizeof(filter));
3445
3446 reg = gma_read16(hw, port, GM_RX_CTRL);
3447 reg |= GM_RXCR_UCF_ENA;
3448
d571b694 3449 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3450 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3451 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3452 memset(filter, 0xff, sizeof(filter));
a052b52f 3453 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3454 reg &= ~GM_RXCR_MCF_ENA;
3455 else {
3456 int i;
3457 reg |= GM_RXCR_MCF_ENA;
3458
a052b52f
SH		 3459 if (rx_pause)
3460 sky2_add_filter(filter, pause_mc_addr);
3461
3462 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3463 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3464 }
3465
cd28ab6a 3466 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3467 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3468 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3469 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3470 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3471 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3472 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3473 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3474
3475 gma_write16(hw, port, GM_RX_CTRL, reg);
3476}
3477
3478/* Can have one global because blinking is controlled by
3479 * ethtool and that is always under RTNL mutex
3480 */
a84d0a3d 3481static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3482{
a84d0a3d
SH		 3483 struct sky2_hw *hw = sky2->hw;
3484 unsigned port = sky2->port;
793b883e 3485
a84d0a3d
SH		 3486 spin_lock_bh(&sky2->phy_lock);
3487 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3488 hw->chip_id == CHIP_ID_YUKON_EX ||
3489 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3490 u16 pg;
793b883e
SH		 3491 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3492 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3493
a84d0a3d
SH		 3494 switch (mode) {
3495 case MO_LED_OFF:
3496 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3497 PHY_M_LEDC_LOS_CTRL(8) |
3498 PHY_M_LEDC_INIT_CTRL(8) |
3499 PHY_M_LEDC_STA1_CTRL(8) |
3500 PHY_M_LEDC_STA0_CTRL(8));
3501 break;
3502 case MO_LED_ON:
3503 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3504 PHY_M_LEDC_LOS_CTRL(9) |
3505 PHY_M_LEDC_INIT_CTRL(9) |
3506 PHY_M_LEDC_STA1_CTRL(9) |
3507 PHY_M_LEDC_STA0_CTRL(9));
3508 break;
3509 case MO_LED_BLINK:
3510 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3511 PHY_M_LEDC_LOS_CTRL(0xa) |
3512 PHY_M_LEDC_INIT_CTRL(0xa) |
3513 PHY_M_LEDC_STA1_CTRL(0xa) |
3514 PHY_M_LEDC_STA0_CTRL(0xa));
3515 break;
3516 case MO_LED_NORM:
3517 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3518 PHY_M_LEDC_LOS_CTRL(1) |
3519 PHY_M_LEDC_INIT_CTRL(8) |
3520 PHY_M_LEDC_STA1_CTRL(7) |
3521 PHY_M_LEDC_STA0_CTRL(7));
3522 }
793b883e 3523
a84d0a3d
SH		 3524 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3525 } else
7d2e3cb7 3526 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3527 PHY_M_LED_MO_DUP(mode) |
3528 PHY_M_LED_MO_10(mode) |
3529 PHY_M_LED_MO_100(mode) |
3530 PHY_M_LED_MO_1000(mode) |
3531 PHY_M_LED_MO_RX(mode) |
3532 PHY_M_LED_MO_TX(mode));
3533
3534 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3535}
3536
3537/* blink LED's for finding board */
3538static int sky2_phys_id(struct net_device *dev, u32 data)
3539{
3540 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3541 unsigned int i;
cd28ab6a 3542
a84d0a3d
SH		 3543 if (data == 0)
3544 data = UINT_MAX;
cd28ab6a 3545
a84d0a3d
SH		 3546 for (i = 0; i < data; i++) {
3547 sky2_led(sky2, MO_LED_ON);
3548 if (msleep_interruptible(500))
3549 break;
3550 sky2_led(sky2, MO_LED_OFF);
3551 if (msleep_interruptible(500))
3552 break;
793b883e 3553 }
a84d0a3d 3554 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3555
3556 return 0;
3557}
3558
3559static void sky2_get_pauseparam(struct net_device *dev,
3560 struct ethtool_pauseparam *ecmd)
3561{
3562 struct sky2_port *sky2 = netdev_priv(dev);
3563
16ad91e1
SH		 3564 switch (sky2->flow_mode) {
3565 case FC_NONE:
3566 ecmd->tx_pause = ecmd->rx_pause = 0;
3567 break;
3568 case FC_TX:
3569 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3570 break;
3571 case FC_RX:
3572 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3573 break;
3574 case FC_BOTH:
3575 ecmd->tx_pause = ecmd->rx_pause = 1;
3576 }
3577
0ea065e5
SH		 3578 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3579 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3580}
3581
3582static int sky2_set_pauseparam(struct net_device *dev,
3583 struct ethtool_pauseparam *ecmd)
3584{
3585 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3586
0ea065e5
SH		 3587 if (ecmd->autoneg == AUTONEG_ENABLE)
3588 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3589 else
3590 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3591
16ad91e1 3592 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3593
16ad91e1
SH		 3594 if (netif_running(dev))
3595 sky2_phy_reinit(sky2);
cd28ab6a 3596
2eaba1a2 3597 return 0;
cd28ab6a
SH		 3598}
3599
fb17358f
SH		 3600static int sky2_get_coalesce(struct net_device *dev,
3601 struct ethtool_coalesce *ecmd)
3602{
3603 struct sky2_port *sky2 = netdev_priv(dev);
3604 struct sky2_hw *hw = sky2->hw;
3605
3606 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3607 ecmd->tx_coalesce_usecs = 0;
3608 else {
3609 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3610 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3611 }
3612 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3613
3614 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3615 ecmd->rx_coalesce_usecs = 0;
3616 else {
3617 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3618 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3619 }
3620 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3621
3622 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3623 ecmd->rx_coalesce_usecs_irq = 0;
3624 else {
3625 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3626 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3627 }
3628
3629 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3630
3631 return 0;
3632}
3633
3634/* Note: this affect both ports */
3635static int sky2_set_coalesce(struct net_device *dev,
3636 struct ethtool_coalesce *ecmd)
3637{
3638 struct sky2_port *sky2 = netdev_priv(dev);
3639 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3640 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3641
77b3d6a2
SH		 3642 if (ecmd->tx_coalesce_usecs > tmax ||
3643 ecmd->rx_coalesce_usecs > tmax ||
3644 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3645 return -EINVAL;
3646
ee5f68fe 3647 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3648 return -EINVAL;
ff81fbbe 3649 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3650 return -EINVAL;
ff81fbbe 3651 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3652 return -EINVAL;
3653
3654 if (ecmd->tx_coalesce_usecs == 0)
3655 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3656 else {
3657 sky2_write32(hw, STAT_TX_TIMER_INI,
3658 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3659 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3660 }
3661 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3662
3663 if (ecmd->rx_coalesce_usecs == 0)
3664 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3665 else {
3666 sky2_write32(hw, STAT_LEV_TIMER_INI,
3667 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3668 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3669 }
3670 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3671
3672 if (ecmd->rx_coalesce_usecs_irq == 0)
3673 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3674 else {
d28d4870 3675 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3676 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3677 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3678 }
3679 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3680 return 0;
3681}
3682
793b883e
SH		 3683static void sky2_get_ringparam(struct net_device *dev,
3684 struct ethtool_ringparam *ering)
3685{
3686 struct sky2_port *sky2 = netdev_priv(dev);
3687
3688 ering->rx_max_pending = RX_MAX_PENDING;
3689 ering->rx_mini_max_pending = 0;
3690 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3691 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3692
3693 ering->rx_pending = sky2->rx_pending;
3694 ering->rx_mini_pending = 0;
3695 ering->rx_jumbo_pending = 0;
3696 ering->tx_pending = sky2->tx_pending;
3697}
3698
3699static int sky2_set_ringparam(struct net_device *dev,
3700 struct ethtool_ringparam *ering)
3701{
3702 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3703
3704 if (ering->rx_pending > RX_MAX_PENDING ||
3705 ering->rx_pending < 8 ||
ee5f68fe
SH		 3706 ering->tx_pending < TX_MIN_PENDING ||
3707 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3708 return -EINVAL;
3709
af18d8b8 3710 sky2_detach(dev);
793b883e
SH		 3711
3712 sky2->rx_pending = ering->rx_pending;
3713 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3714 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3715
af18d8b8 3716 return sky2_reattach(dev);
793b883e
SH		 3717}
3718
793b883e
SH		 3719static int sky2_get_regs_len(struct net_device *dev)
3720{
6e4cbb34 3721 return 0x4000;
793b883e
SH		 3722}
3723
3724/*
3725 * Returns copy of control register region
3ead5db7 3726 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3727 */
3728static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3729 void *p)
3730{
3731 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3732 const void __iomem *io = sky2->hw->regs;
295b54c4 3733 unsigned int b;
793b883e
SH		 3734
3735 regs->version = 1;
793b883e 3736
295b54c4
SH		 3737 for (b = 0; b < 128; b++) {
3738 /* This complicated switch statement is to make sure and
3739 * only access regions that are unreserved.
3740 * Some blocks are only valid on dual port cards.
3741 * and block 3 has some special diagnostic registers that
3742 * are poison.
3743 */
3744 switch (b) {
3745 case 3:
3746 /* skip diagnostic ram region */
3747 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3748 break;
3ead5db7 3749
295b54c4
SH		 3750 /* dual port cards only */
3751 case 5: /* Tx Arbiter 2 */
3752 case 9: /* RX2 */
3753 case 14 ... 15: /* TX2 */
3754 case 17: case 19: /* Ram Buffer 2 */
3755 case 22 ... 23: /* Tx Ram Buffer 2 */
3756 case 25: /* Rx MAC Fifo 1 */
3757 case 27: /* Tx MAC Fifo 2 */
3758 case 31: /* GPHY 2 */
3759 case 40 ... 47: /* Pattern Ram 2 */
3760 case 52: case 54: /* TCP Segmentation 2 */
3761 case 112 ... 116: /* GMAC 2 */
3762 if (sky2->hw->ports == 1)
3763 goto reserved;
3764 /* fall through */
3765 case 0: /* Control */
3766 case 2: /* Mac address */
3767 case 4: /* Tx Arbiter 1 */
3768 case 7: /* PCI express reg */
3769 case 8: /* RX1 */
3770 case 12 ... 13: /* TX1 */
3771 case 16: case 18:/* Rx Ram Buffer 1 */
3772 case 20 ... 21: /* Tx Ram Buffer 1 */
3773 case 24: /* Rx MAC Fifo 1 */
3774 case 26: /* Tx MAC Fifo 1 */
3775 case 28 ... 29: /* Descriptor and status unit */
3776 case 30: /* GPHY 1*/
3777 case 32 ... 39: /* Pattern Ram 1 */
3778 case 48: case 50: /* TCP Segmentation 1 */
3779 case 56 ... 60: /* PCI space */
3780 case 80 ... 84: /* GMAC 1 */
3781 memcpy_fromio(p, io, 128);
3782 break;
3783 default:
3784reserved:
3785 memset(p, 0, 128);
3786 }
3ead5db7 3787
295b54c4
SH		 3788 p += 128;
3789 io += 128;
3790 }
793b883e 3791}
cd28ab6a 3792
b628ed98
SH		 3793/* In order to do Jumbo packets on these chips, need to turn off the
3794 * transmit store/forward. Therefore checksum offload won't work.
3795 */
3796static int no_tx_offload(struct net_device *dev)
3797{
3798 const struct sky2_port *sky2 = netdev_priv(dev);
3799 const struct sky2_hw *hw = sky2->hw;
3800
69161611 3801 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3802}
3803
3804static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3805{
3806 if (data && no_tx_offload(dev))
3807 return -EINVAL;
3808
3809 return ethtool_op_set_tx_csum(dev, data);
3810}
3811
3812
3813static int sky2_set_tso(struct net_device *dev, u32 data)
3814{
3815 if (data && no_tx_offload(dev))
3816 return -EINVAL;
3817
3818 return ethtool_op_set_tso(dev, data);
3819}
3820
f4331a6d
SH		 3821static int sky2_get_eeprom_len(struct net_device *dev)
3822{
3823 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3824 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3825 u16 reg2;
3826
b32f40c4 3827 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3828 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3829}
3830
1413235c 3831static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3832{
1413235c 3833 unsigned long start = jiffies;
f4331a6d 3834
1413235c
SH		 3835 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3836 /* Can take up to 10.6 ms for write */
3837 if (time_after(jiffies, start + HZ/4)) {
3838 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3839 return -ETIMEDOUT;
3840 }
3841 mdelay(1);
3842 }
167f53d0 3843
1413235c
SH		 3844 return 0;
3845}
167f53d0 3846
1413235c
SH		 3847static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3848 u16 offset, size_t length)
3849{
3850 int rc = 0;
3851
3852 while (length > 0) {
3853 u32 val;
3854
3855 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3856 rc = sky2_vpd_wait(hw, cap, 0);
3857 if (rc)
3858 break;
3859
3860 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3861
3862 memcpy(data, &val, min(sizeof(val), length));
3863 offset += sizeof(u32);
3864 data += sizeof(u32);
3865 length -= sizeof(u32);
3866 }
3867
3868 return rc;
f4331a6d
SH		 3869}
3870
1413235c
SH		 3871static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3872 u16 offset, unsigned int length)
f4331a6d 3873{
1413235c
SH		 3874 unsigned int i;
3875 int rc = 0;
3876
3877 for (i = 0; i < length; i += sizeof(u32)) {
3878 u32 val = *(u32 *)(data + i);
3879
3880 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3881 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3882
3883 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3884 if (rc)
3885 break;
3886 }
3887 return rc;
f4331a6d
SH		 3888}
3889
3890static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3891 u8 *data)
3892{
3893 struct sky2_port *sky2 = netdev_priv(dev);
3894 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3895
3896 if (!cap)
3897 return -EINVAL;
3898
3899 eeprom->magic = SKY2_EEPROM_MAGIC;
3900
1413235c 3901 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3902}
3903
3904static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3905 u8 *data)
3906{
3907 struct sky2_port *sky2 = netdev_priv(dev);
3908 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3909
3910 if (!cap)
3911 return -EINVAL;
3912
3913 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3914 return -EINVAL;
3915
1413235c
SH		 3916 /* Partial writes not supported */
3917 if ((eeprom->offset & 3) || (eeprom->len & 3))
3918 return -EINVAL;
f4331a6d 3919
1413235c 3920 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3921}
3922
3923
7282d491 3924static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3925 .get_settings = sky2_get_settings,
3926 .set_settings = sky2_set_settings,
3927 .get_drvinfo = sky2_get_drvinfo,
3928 .get_wol = sky2_get_wol,
3929 .set_wol = sky2_set_wol,
3930 .get_msglevel = sky2_get_msglevel,
3931 .set_msglevel = sky2_set_msglevel,
3932 .nway_reset = sky2_nway_reset,
3933 .get_regs_len = sky2_get_regs_len,
3934 .get_regs = sky2_get_regs,
3935 .get_link = ethtool_op_get_link,
3936 .get_eeprom_len = sky2_get_eeprom_len,
3937 .get_eeprom = sky2_get_eeprom,
3938 .set_eeprom = sky2_set_eeprom,
f4331a6d 3939 .set_sg = ethtool_op_set_sg,
f4331a6d 3940 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3941 .set_tso = sky2_set_tso,
3942 .get_rx_csum = sky2_get_rx_csum,
3943 .set_rx_csum = sky2_set_rx_csum,
3944 .get_strings = sky2_get_strings,
3945 .get_coalesce = sky2_get_coalesce,
3946 .set_coalesce = sky2_set_coalesce,
3947 .get_ringparam = sky2_get_ringparam,
3948 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3949 .get_pauseparam = sky2_get_pauseparam,
3950 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3951 .phys_id = sky2_phys_id,
b9f2c044 3952 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3953 .get_ethtool_stats = sky2_get_ethtool_stats,
3954};
3955
3cf26753
SH		 3956#ifdef CONFIG_SKY2_DEBUG
3957
3958static struct dentry *sky2_debug;
3959
e4c2abe2
SH		 3960
3961/*
3962 * Read and parse the first part of Vital Product Data
3963 */
3964#define VPD_SIZE 128
3965#define VPD_MAGIC 0x82
3966
3967static const struct vpd_tag {
3968 char tag[2];
3969 char *label;
3970} vpd_tags[] = {
3971 { "PN", "Part Number" },
3972 { "EC", "Engineering Level" },
3973 { "MN", "Manufacturer" },
3974 { "SN", "Serial Number" },
3975 { "YA", "Asset Tag" },
3976 { "VL", "First Error Log Message" },
3977 { "VF", "Second Error Log Message" },
3978 { "VB", "Boot Agent ROM Configuration" },
3979 { "VE", "EFI UNDI Configuration" },
3980};
3981
3982static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3983{
3984 size_t vpd_size;
3985 loff_t offs;
3986 u8 len;
3987 unsigned char *buf;
3988 u16 reg2;
3989
3990 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3991 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3992
3993 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3994 buf = kmalloc(vpd_size, GFP_KERNEL);
3995 if (!buf) {
3996 seq_puts(seq, "no memory!\n");
3997 return;
3998 }
3999
4000 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4001 seq_puts(seq, "VPD read failed\n");
4002 goto out;
4003 }
4004
4005 if (buf[0] != VPD_MAGIC) {
4006 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4007 goto out;
4008 }
4009 len = buf[1];
4010 if (len == 0 || len > vpd_size - 4) {
4011 seq_printf(seq, "Invalid id length: %d\n", len);
4012 goto out;
4013 }
4014
4015 seq_printf(seq, "%.*s\n", len, buf + 3);
4016 offs = len + 3;
4017
4018 while (offs < vpd_size - 4) {
4019 int i;
4020
4021 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4022 break;
4023 len = buf[offs + 2];
4024 if (offs + len + 3 >= vpd_size)
4025 break;
4026
4027 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4028 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4029 seq_printf(seq, " %s: %.*s\n",
4030 vpd_tags[i].label, len, buf + offs + 3);
4031 break;
4032 }
4033 }
4034 offs += len + 3;
4035 }
4036out:
4037 kfree(buf);
4038}
4039
3cf26753
SH		 4040static int sky2_debug_show(struct seq_file *seq, void *v)
4041{
4042 struct net_device *dev = seq->private;
4043 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4044 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4045 unsigned port = sky2->port;
4046 unsigned idx, last;
4047 int sop;
4048
e4c2abe2 4049 sky2_show_vpd(seq, hw);
3cf26753 4050
e4c2abe2 4051 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4052 sky2_read32(hw, B0_ISRC),
4053 sky2_read32(hw, B0_IMSK),
4054 sky2_read32(hw, B0_Y2_SP_ICR));
4055
e4c2abe2
SH		 4056 if (!netif_running(dev)) {
4057 seq_printf(seq, "network not running\n");
4058 return 0;
4059 }
4060
bea3348e 4061 napi_disable(&hw->napi);
3cf26753
SH		 4062 last = sky2_read16(hw, STAT_PUT_IDX);
4063
4064 if (hw->st_idx == last)
4065 seq_puts(seq, "Status ring (empty)\n");
4066 else {
4067 seq_puts(seq, "Status ring\n");
4068 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4069 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4070 const struct sky2_status_le *le = hw->st_le + idx;
4071 seq_printf(seq, "[%d] %#x %d %#x\n",
4072 idx, le->opcode, le->length, le->status);
4073 }
4074 seq_puts(seq, "\n");
4075 }
4076
4077 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4078 sky2->tx_cons, sky2->tx_prod,
4079 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4080 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4081
4082 /* Dump contents of tx ring */
4083 sop = 1;
ee5f68fe
SH		 4084 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4085 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4086 const struct sky2_tx_le *le = sky2->tx_le + idx;
4087 u32 a = le32_to_cpu(le->addr);
4088
4089 if (sop)
4090 seq_printf(seq, "%u:", idx);
4091 sop = 0;
4092
4093 switch(le->opcode & ~HW_OWNER) {
4094 case OP_ADDR64:
4095 seq_printf(seq, " %#x:", a);
4096 break;
4097 case OP_LRGLEN:
4098 seq_printf(seq, " mtu=%d", a);
4099 break;
4100 case OP_VLAN:
4101 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4102 break;
4103 case OP_TCPLISW:
4104 seq_printf(seq, " csum=%#x", a);
4105 break;
4106 case OP_LARGESEND:
4107 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4108 break;
4109 case OP_PACKET:
4110 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4111 break;
4112 case OP_BUFFER:
4113 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4114 break;
4115 default:
4116 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4117 a, le16_to_cpu(le->length));
4118 }
4119
4120 if (le->ctrl & EOP) {
4121 seq_putc(seq, '\n');
4122 sop = 1;
4123 }
4124 }
4125
4126 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4127 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4128 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4129 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4130
d1d08d12 4131 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4132 napi_enable(&hw->napi);
3cf26753
SH		 4133 return 0;
4134}
4135
4136static int sky2_debug_open(struct inode *inode, struct file *file)
4137{
4138 return single_open(file, sky2_debug_show, inode->i_private);
4139}
4140
4141static const struct file_operations sky2_debug_fops = {
4142 .owner = THIS_MODULE,
4143 .open = sky2_debug_open,
4144 .read = seq_read,
4145 .llseek = seq_lseek,
4146 .release = single_release,
4147};
4148
4149/*
4150 * Use network device events to create/remove/rename
4151 * debugfs file entries
4152 */
4153static int sky2_device_event(struct notifier_block *unused,
4154 unsigned long event, void *ptr)
4155{
4156 struct net_device *dev = ptr;
5b296bc9 4157 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4158
1436b301 4159 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4160 return NOTIFY_DONE;
3cf26753 4161
5b296bc9
SH		 4162 switch(event) {
4163 case NETDEV_CHANGENAME:
4164 if (sky2->debugfs) {
4165 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4166 sky2_debug, dev->name);
4167 }
4168 break;
3cf26753 4169
5b296bc9
SH		 4170 case NETDEV_GOING_DOWN:
4171 if (sky2->debugfs) {
4172 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4173 dev->name);
4174 debugfs_remove(sky2->debugfs);
4175 sky2->debugfs = NULL;
3cf26753 4176 }
5b296bc9
SH		 4177 break;
4178
4179 case NETDEV_UP:
4180 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4181 sky2_debug, dev,
4182 &sky2_debug_fops);
4183 if (IS_ERR(sky2->debugfs))
4184 sky2->debugfs = NULL;
3cf26753
SH		 4185 }
4186
4187 return NOTIFY_DONE;
4188}
4189
4190static struct notifier_block sky2_notifier = {
4191 .notifier_call = sky2_device_event,
4192};
4193
4194
4195static __init void sky2_debug_init(void)
4196{
4197 struct dentry *ent;
4198
4199 ent = debugfs_create_dir("sky2", NULL);
4200 if (!ent || IS_ERR(ent))
4201 return;
4202
4203 sky2_debug = ent;
4204 register_netdevice_notifier(&sky2_notifier);
4205}
4206
4207static __exit void sky2_debug_cleanup(void)
4208{
4209 if (sky2_debug) {
4210 unregister_netdevice_notifier(&sky2_notifier);
4211 debugfs_remove(sky2_debug);
4212 sky2_debug = NULL;
4213 }
4214}
4215
4216#else
4217#define sky2_debug_init()
4218#define sky2_debug_cleanup()
4219#endif
4220
1436b301
SH		 4221/* Two copies of network device operations to handle special case of
4222 not allowing netpoll on second port */
4223static const struct net_device_ops sky2_netdev_ops[2] = {
4224 {
4225 .ndo_open = sky2_up,
4226 .ndo_stop = sky2_down,
00829823 4227 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4228 .ndo_do_ioctl = sky2_ioctl,
4229 .ndo_validate_addr = eth_validate_addr,
4230 .ndo_set_mac_address = sky2_set_mac_address,
4231 .ndo_set_multicast_list = sky2_set_multicast,
4232 .ndo_change_mtu = sky2_change_mtu,
4233 .ndo_tx_timeout = sky2_tx_timeout,
4234#ifdef SKY2_VLAN_TAG_USED
4235 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4236#endif
4237#ifdef CONFIG_NET_POLL_CONTROLLER
4238 .ndo_poll_controller = sky2_netpoll,
4239#endif
4240 },
4241 {
4242 .ndo_open = sky2_up,
4243 .ndo_stop = sky2_down,
00829823 4244 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4245 .ndo_do_ioctl = sky2_ioctl,
4246 .ndo_validate_addr = eth_validate_addr,
4247 .ndo_set_mac_address = sky2_set_mac_address,
4248 .ndo_set_multicast_list = sky2_set_multicast,
4249 .ndo_change_mtu = sky2_change_mtu,
4250 .ndo_tx_timeout = sky2_tx_timeout,
4251#ifdef SKY2_VLAN_TAG_USED
4252 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4253#endif
4254 },
4255};
3cf26753 4256
cd28ab6a
SH		 4257/* Initialize network device */
4258static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4259 unsigned port,
be63a21c 4260 int highmem, int wol)
cd28ab6a
SH		 4261{
4262 struct sky2_port *sky2;
4263 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4264
4265 if (!dev) {
898eb71c 4266 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4267 return NULL;
4268 }
4269
cd28ab6a 4270 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4271 dev->irq = hw->pdev->irq;
cd28ab6a 4272 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4273 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4274 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4275
4276 sky2 = netdev_priv(dev);
4277 sky2->netdev = dev;
4278 sky2->hw = hw;
4279 sky2->msg_enable = netif_msg_init(debug, default_msg);
4280
cd28ab6a 4281 /* Auto speed and flow control */
0ea065e5
SH		 4282 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4283 if (hw->chip_id != CHIP_ID_YUKON_XL)
4284 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4285
16ad91e1
SH		 4286 sky2->flow_mode = FC_BOTH;
4287
cd28ab6a
SH		 4288 sky2->duplex = -1;
4289 sky2->speed = -1;
4290 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4291 sky2->wol = wol;
75d070c5 4292
e07b1aa8 4293 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4294
793b883e 4295 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4296 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4297 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4298
4299 hw->dev[port] = dev;
4300
4301 sky2->port = port;
4302
4a50a876 4303 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4304 if (highmem)
4305 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4306
d1f13708 4307#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4308 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4309 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4310 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4311 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4312 }
d1f13708 4313#endif
4314
cd28ab6a 4315 /* read the mac address */
793b883e 4316 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4317 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4318
cd28ab6a
SH		 4319 return dev;
4320}
4321
28bd181a 4322static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4323{
4324 const struct sky2_port *sky2 = netdev_priv(dev);
4325
4326 if (netif_msg_probe(sky2))
e174961c
JB		 4327 printk(KERN_INFO PFX "%s: addr %pM\n",
4328 dev->name, dev->dev_addr);
cd28ab6a
SH		 4329}
4330
fb2690a9 4331/* Handle software interrupt used during MSI test */
7d12e780 4332static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4333{
4334 struct sky2_hw *hw = dev_id;
4335 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4336
4337 if (status == 0)
4338 return IRQ_NONE;
4339
4340 if (status & Y2_IS_IRQ_SW) {
ea76e635 4341 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4342 wake_up(&hw->msi_wait);
4343 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4344 }
4345 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4346
4347 return IRQ_HANDLED;
4348}
4349
4350/* Test interrupt path by forcing a a software IRQ */
4351static int __devinit sky2_test_msi(struct sky2_hw *hw)
4352{
4353 struct pci_dev *pdev = hw->pdev;
4354 int err;
4355
bb507fe1 4356 init_waitqueue_head (&hw->msi_wait);
4357
fb2690a9
SH		 4358 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4359
b0a20ded 4360 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4361 if (err) {
b02a9258 4362 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4363 return err;
4364 }
4365
fb2690a9 4366 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4367 sky2_read8(hw, B0_CTST);
fb2690a9 4368
ea76e635 4369 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4370
ea76e635 4371 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4372 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4373 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4374 "switching to INTx mode.\n");
fb2690a9
SH		 4375
4376 err = -EOPNOTSUPP;
4377 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4378 }
4379
4380 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4381 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4382
4383 free_irq(pdev->irq, hw);
4384
4385 return err;
4386}
4387
c7127a34
SH		 4388/* This driver supports yukon2 chipset only */
4389static const char *sky2_name(u8 chipid, char *buf, int sz)
4390{
4391 const char *name[] = {
4392 "XL", /* 0xb3 */
4393 "EC Ultra", /* 0xb4 */
4394 "Extreme", /* 0xb5 */
4395 "EC", /* 0xb6 */
4396 "FE", /* 0xb7 */
4397 "FE+", /* 0xb8 */
4398 "Supreme", /* 0xb9 */
0ce8b98d 4399 "UL 2", /* 0xba */
c7127a34
SH		 4400 };
4401
0ce8b98d 4402 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4403 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4404 else
4405 snprintf(buf, sz, "(chip %#x)", chipid);
4406 return buf;
4407}
4408
cd28ab6a
SH		 4409static int __devinit sky2_probe(struct pci_dev *pdev,
4410 const struct pci_device_id *ent)
4411{
7f60c64b 4412 struct net_device *dev;
cd28ab6a 4413 struct sky2_hw *hw;
be63a21c 4414 int err, using_dac = 0, wol_default;
3834507d 4415 u32 reg;
c7127a34 4416 char buf1[16];
cd28ab6a 4417
793b883e
SH		 4418 err = pci_enable_device(pdev);
4419 if (err) {
b02a9258 4420 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4421 goto err_out;
4422 }
4423
6cc90a5a
SH		 4424 /* Get configuration information
4425 * Note: only regular PCI config access once to test for HW issues
4426 * other PCI access through shared memory for speed and to
4427 * avoid MMCONFIG problems.
4428 */
4429 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4430 if (err) {
4431 dev_err(&pdev->dev, "PCI read config failed\n");
4432 goto err_out;
4433 }
4434
4435 if (~reg == 0) {
4436 dev_err(&pdev->dev, "PCI configuration read error\n");
4437 goto err_out;
4438 }
4439
793b883e
SH		 4440 err = pci_request_regions(pdev, DRV_NAME);
4441 if (err) {
b02a9258 4442 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4443 goto err_out_disable;
cd28ab6a
SH		 4444 }
4445
4446 pci_set_master(pdev);
4447
d1f3d4dd 4448 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4449 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4450 using_dac = 1;
6a35528a 4451 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4452 if (err < 0) {
b02a9258
SH		 4453 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4454 "for consistent allocations\n");
d1f3d4dd
SH		 4455 goto err_out_free_regions;
4456 }
d1f3d4dd 4457 } else {
284901a9 4458 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4459 if (err) {
b02a9258 4460 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4461 goto err_out_free_regions;
4462 }
4463 }
d1f3d4dd 4464
3834507d
SH		 4465
4466#ifdef __BIG_ENDIAN
4467 /* The sk98lin vendor driver uses hardware byte swapping but
4468 * this driver uses software swapping.
4469 */
4470 reg &= ~PCI_REV_DESC;
4471 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4472 if (err) {
4473 dev_err(&pdev->dev, "PCI write config failed\n");
4474 goto err_out_free_regions;
4475 }
4476#endif
4477
9d731d77 4478 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4479
cd28ab6a 4480 err = -ENOMEM;
6aad85d6 4481 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4482 if (!hw) {
b02a9258 4483 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4484 goto err_out_free_regions;
4485 }
4486
cd28ab6a 4487 hw->pdev = pdev;
cd28ab6a
SH		 4488
4489 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4490 if (!hw->regs) {
b02a9258 4491 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4492 goto err_out_free_hw;
4493 }
4494
08c06d8a 4495 /* ring for status responses */
167f53d0 4496 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4497 if (!hw->st_le)
4498 goto err_out_iounmap;
4499
e3173832 4500 err = sky2_init(hw);
cd28ab6a 4501 if (err)
793b883e 4502 goto err_out_iounmap;
cd28ab6a 4503
c844d483
SH		 4504 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4505 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4506
e3173832
SH		 4507 sky2_reset(hw);
4508
be63a21c 4509 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4510 if (!dev) {
4511 err = -ENOMEM;
cd28ab6a 4512 goto err_out_free_pci;
7f60c64b 4513 }
cd28ab6a 4514
9fa1b1f3
SH		 4515 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4516 err = sky2_test_msi(hw);
4517 if (err == -EOPNOTSUPP)
4518 pci_disable_msi(pdev);
4519 else if (err)
4520 goto err_out_free_netdev;
4521 }
4522
793b883e
SH		 4523 err = register_netdev(dev);
4524 if (err) {
b02a9258 4525 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4526 goto err_out_free_netdev;
4527 }
4528
6de16237
SH		 4529 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4530
ea76e635
SH		 4531 err = request_irq(pdev->irq, sky2_intr,
4532 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4533 dev->name, hw);
9fa1b1f3 4534 if (err) {
b02a9258 4535 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4536 goto err_out_unregister;
4537 }
4538 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4539 napi_enable(&hw->napi);
9fa1b1f3 4540
cd28ab6a
SH		 4541 sky2_show_addr(dev);
4542
7f60c64b 4543 if (hw->ports > 1) {
4544 struct net_device *dev1;
4545
be63a21c 4546 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4547 if (!dev1)
4548 dev_warn(&pdev->dev, "allocation for second device failed\n");
4549 else if ((err = register_netdev(dev1))) {
4550 dev_warn(&pdev->dev,
4551 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4552 hw->dev[1] = NULL;
4553 free_netdev(dev1);
b02a9258
SH		 4554 } else
4555 sky2_show_addr(dev1);
cd28ab6a
SH		 4556 }
4557
32c2c300 4558 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4559 INIT_WORK(&hw->restart_work, sky2_restart);
4560
793b883e
SH		 4561 pci_set_drvdata(pdev, hw);
4562
cd28ab6a
SH		 4563 return 0;
4564
793b883e 4565err_out_unregister:
ea76e635 4566 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4567 pci_disable_msi(pdev);
793b883e 4568 unregister_netdev(dev);
cd28ab6a
SH		 4569err_out_free_netdev:
4570 free_netdev(dev);
cd28ab6a 4571err_out_free_pci:
793b883e 4572 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4573 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4574err_out_iounmap:
4575 iounmap(hw->regs);
4576err_out_free_hw:
4577 kfree(hw);
4578err_out_free_regions:
4579 pci_release_regions(pdev);
44a1d2e5 4580err_out_disable:
cd28ab6a 4581 pci_disable_device(pdev);
cd28ab6a 4582err_out:
549a68c3 4583 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4584 return err;
4585}
4586
4587static void __devexit sky2_remove(struct pci_dev *pdev)
4588{
793b883e 4589 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4590 int i;
cd28ab6a 4591
793b883e 4592 if (!hw)
cd28ab6a
SH		 4593 return;
4594
32c2c300 4595 del_timer_sync(&hw->watchdog_timer);
6de16237 4596 cancel_work_sync(&hw->restart_work);
d27ed387 4597
b877fe28 4598 for (i = hw->ports-1; i >= 0; --i)
6de16237 4599 unregister_netdev(hw->dev[i]);
81906791 4600
d27ed387 4601 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4602
ae306cca
SH		 4603 sky2_power_aux(hw);
4604
793b883e 4605 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4606 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4607
4608 free_irq(pdev->irq, hw);
ea76e635 4609 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4610 pci_disable_msi(pdev);
793b883e 4611 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4612 pci_release_regions(pdev);
4613 pci_disable_device(pdev);
793b883e 4614
b877fe28 4615 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4616 free_netdev(hw->dev[i]);
4617
cd28ab6a
SH		 4618 iounmap(hw->regs);
4619 kfree(hw);
5afa0a9c 4620
cd28ab6a
SH		 4621 pci_set_drvdata(pdev, NULL);
4622}
4623
4624#ifdef CONFIG_PM
4625static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4626{
793b883e 4627 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4628 int i, wol = 0;
cd28ab6a 4629
549a68c3
SH		 4630 if (!hw)
4631 return 0;
4632
063a0b38
SH		 4633 del_timer_sync(&hw->watchdog_timer);
4634 cancel_work_sync(&hw->restart_work);
4635
19720737 4636 rtnl_lock();
f05267e7 4637 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4638 struct net_device *dev = hw->dev[i];
e3173832 4639 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4640
af18d8b8 4641 sky2_detach(dev);
e3173832
SH		 4642
4643 if (sky2->wol)
4644 sky2_wol_init(sky2);
4645
4646 wol |= sky2->wol;
cd28ab6a
SH		 4647 }
4648
8ab8fca2 4649 sky2_write32(hw, B0_IMSK, 0);
6de16237 4650 napi_disable(&hw->napi);
ae306cca 4651 sky2_power_aux(hw);
19720737 4652 rtnl_unlock();
e3173832 4653
d374c1c1 4654 pci_save_state(pdev);
e3173832 4655 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4656 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4657
2ccc99b7 4658 return 0;
cd28ab6a
SH		 4659}
4660
4661static int sky2_resume(struct pci_dev *pdev)
4662{
793b883e 4663 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4664 int i, err;
cd28ab6a 4665
549a68c3
SH		 4666 if (!hw)
4667 return 0;
4668
f71eb1a2
SH		 4669 err = pci_set_power_state(pdev, PCI_D0);
4670 if (err)
4671 goto out;
ae306cca
SH		 4672
4673 err = pci_restore_state(pdev);
4674 if (err)
4675 goto out;
4676
cd28ab6a 4677 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4678
4679 /* Re-enable all clocks */
05745c4a
SH		 4680 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4681 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4682 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4683 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4684
e3173832 4685 sky2_reset(hw);
8ab8fca2 4686 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4687 napi_enable(&hw->napi);
8ab8fca2 4688
af18d8b8 4689 rtnl_lock();
f05267e7 4690 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4691 err = sky2_reattach(hw->dev[i]);
4692 if (err)
4693 goto out;
cd28ab6a 4694 }
af18d8b8 4695 rtnl_unlock();
eb35cf60 4696
ae306cca 4697 return 0;
08c06d8a 4698out:
af18d8b8
SH		 4699 rtnl_unlock();
4700
b02a9258 4701 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4702 pci_disable_device(pdev);
08c06d8a 4703 return err;
cd28ab6a
SH		 4704}
4705#endif
4706
e3173832
SH		 4707static void sky2_shutdown(struct pci_dev *pdev)
4708{
4709 struct sky2_hw *hw = pci_get_drvdata(pdev);
4710 int i, wol = 0;
4711
549a68c3
SH		 4712 if (!hw)
4713 return;
4714
19720737 4715 rtnl_lock();
5c0d6b34 4716 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4717
4718 for (i = 0; i < hw->ports; i++) {
4719 struct net_device *dev = hw->dev[i];
4720 struct sky2_port *sky2 = netdev_priv(dev);
4721
4722 if (sky2->wol) {
4723 wol = 1;
4724 sky2_wol_init(sky2);
4725 }
4726 }
4727
4728 if (wol)
4729 sky2_power_aux(hw);
19720737 4730 rtnl_unlock();
e3173832
SH		 4731
4732 pci_enable_wake(pdev, PCI_D3hot, wol);
4733 pci_enable_wake(pdev, PCI_D3cold, wol);
4734
4735 pci_disable_device(pdev);
f71eb1a2 4736 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4737}
4738
cd28ab6a 4739static struct pci_driver sky2_driver = {
793b883e
SH		 4740 .name = DRV_NAME,
4741 .id_table = sky2_id_table,
4742 .probe = sky2_probe,
4743 .remove = __devexit_p(sky2_remove),
cd28ab6a 4744#ifdef CONFIG_PM
793b883e
SH		 4745 .suspend = sky2_suspend,
4746 .resume = sky2_resume,
cd28ab6a 4747#endif
e3173832 4748 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4749};
4750
4751static int __init sky2_init_module(void)
4752{
c844d483
SH		 4753 pr_info(PFX "driver version " DRV_VERSION "\n");
4754
3cf26753 4755 sky2_debug_init();
50241c4c 4756 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4757}
4758
4759static void __exit sky2_cleanup_module(void)
4760{
4761 pci_unregister_driver(&sky2_driver);
3cf26753 4762 sky2_debug_cleanup();
cd28ab6a
SH		 4763}
4764
4765module_init(sky2_init_module);
4766module_exit(sky2_cleanup_module);
4767
4768MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4769MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4770MODULE_LICENSE("GPL");
5f4f9dc1 4771MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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