Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
26 | /* | |
cd28ab6a SH |
27 | * TOTEST |
28 | * - speed setting | |
724bca3c | 29 | * - suspend/resume |
cd28ab6a SH |
30 | */ |
31 | ||
32 | #include <linux/config.h> | |
793b883e | 33 | #include <linux/crc32.h> |
cd28ab6a SH |
34 | #include <linux/kernel.h> |
35 | #include <linux/version.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/netdevice.h> | |
d0bbccfa | 38 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
39 | #include <linux/etherdevice.h> |
40 | #include <linux/ethtool.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/ip.h> | |
43 | #include <linux/tcp.h> | |
44 | #include <linux/in.h> | |
45 | #include <linux/delay.h> | |
91c86df5 | 46 | #include <linux/workqueue.h> |
d1f13708 | 47 | #include <linux/if_vlan.h> |
d70cd51a | 48 | #include <linux/prefetch.h> |
ef743d33 | 49 | #include <linux/mii.h> |
cd28ab6a SH |
50 | |
51 | #include <asm/irq.h> | |
52 | ||
d1f13708 | 53 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
54 | #define SKY2_VLAN_TAG_USED 1 | |
55 | #endif | |
56 | ||
cd28ab6a SH |
57 | #include "sky2.h" |
58 | ||
59 | #define DRV_NAME "sky2" | |
e0c94455 | 60 | #define DRV_VERSION "0.12" |
cd28ab6a SH |
61 | #define PFX DRV_NAME " " |
62 | ||
63 | /* | |
64 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
65 | * that are organized into three (receive, transmit, status) different rings | |
66 | * similar to Tigon3. A transmit can require several elements; | |
67 | * a receive requires one (or two if using 64 bit dma). | |
68 | */ | |
69 | ||
cd28ab6a | 70 | #define is_ec_a1(hw) \ |
21437643 | 71 | unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \ |
72 | (hw)->chip_rev == CHIP_REV_YU_EC_A1) | |
cd28ab6a | 73 | |
13210ce5 | 74 | #define RX_LE_SIZE 512 |
cd28ab6a | 75 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
bea86103 | 76 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) |
13210ce5 | 77 | #define RX_DEF_PENDING RX_MAX_PENDING |
82788c7a | 78 | #define RX_SKB_ALIGN 8 |
793b883e SH |
79 | |
80 | #define TX_RING_SIZE 512 | |
81 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
82 | #define TX_MIN_PENDING 64 | |
83 | #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS) | |
cd28ab6a | 84 | |
793b883e | 85 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
86 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
87 | #define ETH_JUMBO_MTU 9000 | |
88 | #define TX_WATCHDOG (5 * HZ) | |
89 | #define NAPI_WEIGHT 64 | |
90 | #define PHY_RETRIES 1000 | |
91 | ||
92 | static const u32 default_msg = | |
793b883e SH |
93 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
94 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
95 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR; | |
cd28ab6a | 96 | |
793b883e | 97 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
98 | module_param(debug, int, 0); |
99 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
100 | ||
bdb5c58e SH |
101 | static int copybreak __read_mostly = 256; |
102 | module_param(copybreak, int, 0); | |
103 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
104 | ||
cd28ab6a | 105 | static const struct pci_device_id sky2_id_table[] = { |
793b883e | 106 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a SH |
107 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
108 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, | |
109 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
5a5b1ea0 | 120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
cd28ab6a SH |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
5a5b1ea0 | 124 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
cd28ab6a SH |
125 | { 0 } |
126 | }; | |
793b883e | 127 | |
cd28ab6a SH |
128 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
129 | ||
130 | /* Avoid conditionals by using array */ | |
131 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
132 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
133 | ||
92f965e8 SH |
134 | /* This driver supports yukon2 chipset only */ |
135 | static const char *yukon2_name[] = { | |
136 | "XL", /* 0xb3 */ | |
137 | "EC Ultra", /* 0xb4 */ | |
138 | "UNKNOWN", /* 0xb5 */ | |
139 | "EC", /* 0xb6 */ | |
140 | "FE", /* 0xb7 */ | |
793b883e SH |
141 | }; |
142 | ||
793b883e | 143 | /* Access to external PHY */ |
ef743d33 | 144 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
145 | { |
146 | int i; | |
147 | ||
148 | gma_write16(hw, port, GM_SMI_DATA, val); | |
149 | gma_write16(hw, port, GM_SMI_CTRL, | |
150 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
151 | ||
152 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 153 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 154 | return 0; |
793b883e | 155 | udelay(1); |
cd28ab6a | 156 | } |
ef743d33 | 157 | |
793b883e | 158 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 159 | return -ETIMEDOUT; |
cd28ab6a SH |
160 | } |
161 | ||
ef743d33 | 162 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
163 | { |
164 | int i; | |
165 | ||
793b883e | 166 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
167 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
168 | ||
169 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 | 170 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
171 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
172 | return 0; | |
173 | } | |
174 | ||
793b883e | 175 | udelay(1); |
cd28ab6a SH |
176 | } |
177 | ||
ef743d33 | 178 | return -ETIMEDOUT; |
179 | } | |
180 | ||
181 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
182 | { | |
183 | u16 v; | |
184 | ||
185 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
186 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
187 | return v; | |
cd28ab6a SH |
188 | } |
189 | ||
5afa0a9c | 190 | static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
191 | { | |
192 | u16 power_control; | |
193 | u32 reg1; | |
194 | int vaux; | |
195 | int ret = 0; | |
196 | ||
197 | pr_debug("sky2_set_power_state %d\n", state); | |
198 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
199 | ||
200 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control); | |
201 | vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) && | |
202 | (power_control & PCI_PM_CAP_PME_D3cold); | |
203 | ||
204 | pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control); | |
205 | ||
206 | power_control |= PCI_PM_CTRL_PME_STATUS; | |
207 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | |
208 | ||
209 | switch (state) { | |
210 | case PCI_D0: | |
211 | /* switch power to VCC (WA for VAUX problem) */ | |
212 | sky2_write8(hw, B0_POWER_CTRL, | |
213 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
214 | ||
215 | /* disable Core Clock Division, */ | |
216 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
217 | ||
218 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
219 | /* enable bits are inverted */ | |
220 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
221 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
222 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
223 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
224 | else | |
225 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
226 | ||
227 | /* Turn off phy power saving */ | |
228 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
229 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
230 | ||
d571b694 | 231 | /* looks like this XL is back asswards .. */ |
5afa0a9c | 232 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { |
233 | reg1 |= PCI_Y2_PHY1_COMA; | |
234 | if (hw->ports > 1) | |
235 | reg1 |= PCI_Y2_PHY2_COMA; | |
236 | } | |
237 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
238 | break; | |
239 | ||
240 | case PCI_D3hot: | |
241 | case PCI_D3cold: | |
242 | /* Turn on phy power saving */ | |
243 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | |
244 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
245 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
246 | else | |
247 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
248 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | |
249 | ||
250 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
251 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
252 | else | |
253 | /* enable bits are inverted */ | |
254 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
255 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
256 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
257 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
258 | ||
259 | /* switch power to VAUX */ | |
260 | if (vaux && state != PCI_D3cold) | |
261 | sky2_write8(hw, B0_POWER_CTRL, | |
262 | (PC_VAUX_ENA | PC_VCC_ENA | | |
263 | PC_VAUX_ON | PC_VCC_OFF)); | |
264 | break; | |
265 | default: | |
266 | printk(KERN_ERR PFX "Unknown power state %d\n", state); | |
267 | ret = -1; | |
268 | } | |
269 | ||
270 | pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control); | |
271 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
272 | return ret; | |
273 | } | |
274 | ||
cd28ab6a SH |
275 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) |
276 | { | |
277 | u16 reg; | |
278 | ||
279 | /* disable all GMAC IRQ's */ | |
280 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
281 | /* disable PHY IRQs */ | |
282 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 283 | |
cd28ab6a SH |
284 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
285 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
286 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
287 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
288 | ||
289 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
290 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
291 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
292 | } | |
293 | ||
294 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
295 | { | |
296 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 297 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 298 | |
793b883e | 299 | if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) { |
cd28ab6a SH |
300 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
301 | ||
302 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 303 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
304 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
305 | ||
306 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
307 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
308 | else | |
309 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
310 | ||
311 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
312 | } | |
313 | ||
314 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
315 | if (hw->copper) { | |
316 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
317 | /* enable automatic crossover */ | |
318 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
319 | } else { | |
320 | /* disable energy detect */ | |
321 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
322 | ||
323 | /* enable automatic crossover */ | |
324 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
325 | ||
326 | if (sky2->autoneg == AUTONEG_ENABLE && | |
327 | hw->chip_id == CHIP_ID_YUKON_XL) { | |
328 | ctrl &= ~PHY_M_PC_DSC_MSK; | |
329 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
330 | } | |
331 | } | |
332 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
333 | } else { | |
334 | /* workaround for deviation #4.88 (CRC errors) */ | |
335 | /* disable Automatic Crossover */ | |
336 | ||
337 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
338 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
339 | ||
340 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
341 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
342 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
343 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
344 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
345 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
346 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
347 | ||
348 | /* select page 1 to access Fiber registers */ | |
349 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
350 | } | |
cd28ab6a SH |
351 | } |
352 | ||
353 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
354 | if (sky2->autoneg == AUTONEG_DISABLE) | |
355 | ctrl &= ~PHY_CT_ANE; | |
356 | else | |
357 | ctrl |= PHY_CT_ANE; | |
358 | ||
359 | ctrl |= PHY_CT_RESET; | |
360 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
361 | ||
362 | ctrl = 0; | |
363 | ct1000 = 0; | |
364 | adv = PHY_AN_CSMA; | |
365 | ||
366 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
367 | if (hw->copper) { | |
368 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
369 | ct1000 |= PHY_M_1000C_AFD; | |
370 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
371 | ct1000 |= PHY_M_1000C_AHD; | |
372 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
373 | adv |= PHY_M_AN_100_FD; | |
374 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
375 | adv |= PHY_M_AN_100_HD; | |
376 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
377 | adv |= PHY_M_AN_10_FD; | |
378 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
379 | adv |= PHY_M_AN_10_HD; | |
793b883e | 380 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
381 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
382 | ||
383 | /* Set Flow-control capabilities */ | |
384 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 385 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 386 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 387 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
388 | else if (!sky2->rx_pause && sky2->tx_pause) |
389 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
390 | ||
391 | /* Restart Auto-negotiation */ | |
392 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
393 | } else { | |
394 | /* forced speed/duplex settings */ | |
395 | ct1000 = PHY_M_1000C_MSE; | |
396 | ||
397 | if (sky2->duplex == DUPLEX_FULL) | |
398 | ctrl |= PHY_CT_DUP_MD; | |
399 | ||
400 | switch (sky2->speed) { | |
401 | case SPEED_1000: | |
402 | ctrl |= PHY_CT_SP1000; | |
403 | break; | |
404 | case SPEED_100: | |
405 | ctrl |= PHY_CT_SP100; | |
406 | break; | |
407 | } | |
408 | ||
409 | ctrl |= PHY_CT_RESET; | |
410 | } | |
411 | ||
412 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
413 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
414 | ||
415 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
416 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
417 | ||
418 | /* Setup Phy LED's */ | |
419 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
420 | ledover = 0; | |
421 | ||
422 | switch (hw->chip_id) { | |
423 | case CHIP_ID_YUKON_FE: | |
424 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
425 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
426 | ||
427 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
428 | ||
429 | /* delete ACT LED control bits */ | |
430 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
431 | /* change ACT LED control to blink mode */ | |
432 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
433 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
434 | break; | |
435 | ||
436 | case CHIP_ID_YUKON_XL: | |
793b883e | 437 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
438 | |
439 | /* select page 3 to access LED control register */ | |
440 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
441 | ||
442 | /* set LED Function Control register */ | |
793b883e SH |
443 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ |
444 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
445 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
446 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
447 | |
448 | /* set Polarity Control register */ | |
449 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
450 | (PHY_M_POLC_LS1_P_MIX(4) | |
451 | PHY_M_POLC_IS0_P_MIX(4) | | |
452 | PHY_M_POLC_LOS_CTRL(2) | | |
453 | PHY_M_POLC_INIT_CTRL(2) | | |
454 | PHY_M_POLC_STA1_CTRL(2) | | |
455 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
456 | |
457 | /* restore page register */ | |
793b883e | 458 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a SH |
459 | break; |
460 | ||
461 | default: | |
462 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
463 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
464 | /* turn off the Rx LED (LED_RX) */ | |
465 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
466 | } | |
467 | ||
468 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
469 | ||
470 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { | |
471 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
472 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
473 | } | |
474 | ||
475 | if (ledover) | |
476 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
477 | ||
d571b694 | 478 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
479 | if (sky2->autoneg == AUTONEG_ENABLE) |
480 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
481 | else | |
482 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
483 | } | |
484 | ||
1b537565 SH |
485 | /* Force a renegotiation */ |
486 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
487 | { | |
488 | down(&sky2->phy_sema); | |
489 | sky2_phy_init(sky2->hw, sky2->port); | |
490 | up(&sky2->phy_sema); | |
491 | } | |
492 | ||
cd28ab6a SH |
493 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
494 | { | |
495 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
496 | u16 reg; | |
497 | int i; | |
498 | const u8 *addr = hw->dev[port]->dev_addr; | |
499 | ||
42eeea01 | 500 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
501 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); | |
cd28ab6a SH |
502 | |
503 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
504 | ||
793b883e | 505 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
506 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
507 | /* clear GMAC 1 Control reset */ | |
508 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
509 | do { | |
510 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
511 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
512 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
513 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
514 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
515 | } | |
516 | ||
cd28ab6a SH |
517 | if (sky2->autoneg == AUTONEG_DISABLE) { |
518 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
519 | reg |= GM_GPCR_AU_ALL_DIS; | |
520 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
521 | gma_read16(hw, port, GM_GP_CTRL); | |
522 | ||
cd28ab6a SH |
523 | switch (sky2->speed) { |
524 | case SPEED_1000: | |
525 | reg |= GM_GPCR_SPEED_1000; | |
526 | /* fallthru */ | |
527 | case SPEED_100: | |
528 | reg |= GM_GPCR_SPEED_100; | |
529 | } | |
530 | ||
531 | if (sky2->duplex == DUPLEX_FULL) | |
532 | reg |= GM_GPCR_DUP_FULL; | |
533 | } else | |
534 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
535 | ||
536 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
537 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
538 | reg |= |
539 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
540 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
541 | /* disable Rx flow-control */ |
542 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
543 | } | |
544 | ||
545 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
546 | ||
793b883e | 547 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 548 | |
91c86df5 | 549 | down(&sky2->phy_sema); |
cd28ab6a | 550 | sky2_phy_init(hw, port); |
91c86df5 | 551 | up(&sky2->phy_sema); |
cd28ab6a SH |
552 | |
553 | /* MIB clear */ | |
554 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
555 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
556 | ||
557 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
793b883e | 558 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i); |
cd28ab6a SH |
559 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
560 | ||
561 | /* transmit control */ | |
562 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
563 | ||
564 | /* receive control reg: unicast + multicast + no FCS */ | |
565 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 566 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
567 | |
568 | /* transmit flow control */ | |
569 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
570 | ||
571 | /* transmit parameter */ | |
572 | gma_write16(hw, port, GM_TX_PARAM, | |
573 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
574 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
575 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
576 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
577 | ||
578 | /* serial mode register */ | |
579 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 580 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 581 | |
6b1a3aef | 582 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
583 | reg |= GM_SMOD_JUMBO_ENA; |
584 | ||
585 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
586 | ||
cd28ab6a SH |
587 | /* virtual address for data */ |
588 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
589 | ||
793b883e SH |
590 | /* physical address: used for pause frames */ |
591 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
592 | ||
593 | /* ignore counter overflows */ | |
cd28ab6a SH |
594 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
595 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
596 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
597 | ||
598 | /* Configure Rx MAC FIFO */ | |
599 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
793b883e | 600 | sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T), |
d1f13708 | 601 | GMF_RX_CTRL_DEF); |
cd28ab6a | 602 | |
d571b694 | 603 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 604 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 605 | |
793b883e SH |
606 | /* Set threshold to 0xa (64 bytes) |
607 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
608 | */ |
609 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
610 | ||
611 | /* Configure Tx MAC FIFO */ | |
612 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
613 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 | 614 | |
615 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
616 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); | |
617 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | |
618 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
619 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
620 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); | |
621 | /* Disable Store & Forward mode for TX */ | |
622 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); | |
623 | } | |
624 | } | |
625 | ||
cd28ab6a SH |
626 | } |
627 | ||
1c28f6ba SH |
628 | /* Assign Ram Buffer allocation. |
629 | * start and end are in units of 4k bytes | |
630 | * ram registers are in units of 64bit words | |
631 | */ | |
632 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) | |
cd28ab6a | 633 | { |
1c28f6ba | 634 | u32 start, end; |
cd28ab6a | 635 | |
1c28f6ba SH |
636 | start = startk * 4096/8; |
637 | end = (endk * 4096/8) - 1; | |
793b883e | 638 | |
cd28ab6a SH |
639 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
640 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
641 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
642 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
643 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
644 | ||
645 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba SH |
646 | u32 space = (endk - startk) * 4096/8; |
647 | u32 tp = space - space/4; | |
793b883e | 648 | |
1c28f6ba SH |
649 | /* On receive queue's set the thresholds |
650 | * give receiver priority when > 3/4 full | |
651 | * send pause when down to 2K | |
652 | */ | |
653 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
654 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 655 | |
1c28f6ba SH |
656 | tp = space - 2048/8; |
657 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); | |
658 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
659 | } else { |
660 | /* Enable store & forward on Tx queue's because | |
661 | * Tx FIFO is only 1K on Yukon | |
662 | */ | |
663 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
664 | } | |
665 | ||
666 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 667 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
668 | } |
669 | ||
cd28ab6a | 670 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 671 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
672 | { |
673 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
674 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
675 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 676 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
677 | } |
678 | ||
cd28ab6a SH |
679 | /* Setup prefetch unit registers. This is the interface between |
680 | * hardware and driver list elements | |
681 | */ | |
8cc048e3 | 682 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
cd28ab6a SH |
683 | u64 addr, u32 last) |
684 | { | |
cd28ab6a SH |
685 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
686 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
687 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
688 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
689 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
690 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
691 | |
692 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
693 | } |
694 | ||
793b883e SH |
695 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
696 | { | |
697 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
698 | ||
699 | sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE; | |
700 | return le; | |
701 | } | |
cd28ab6a SH |
702 | |
703 | /* | |
d571b694 | 704 | * This is a workaround code taken from SysKonnect sk98lin driver |
793b883e | 705 | * to deal with chip bug on Yukon EC rev 0 in the wraparound case. |
cd28ab6a SH |
706 | */ |
707 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, | |
708 | u16 idx, u16 *last, u16 size) | |
cd28ab6a | 709 | { |
cd28ab6a SH |
710 | if (is_ec_a1(hw) && idx < *last) { |
711 | u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX)); | |
712 | ||
713 | if (hwget == 0) { | |
714 | /* Start prefetching again */ | |
793b883e | 715 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0); |
cd28ab6a SH |
716 | goto setnew; |
717 | } | |
718 | ||
793b883e | 719 | if (hwget == size - 1) { |
cd28ab6a SH |
720 | /* set watermark to one list element */ |
721 | sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8); | |
722 | ||
723 | /* set put index to first list element */ | |
724 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0); | |
793b883e SH |
725 | } else /* have hardware go to end of list */ |
726 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), | |
727 | size - 1); | |
cd28ab6a | 728 | } else { |
793b883e | 729 | setnew: |
cd28ab6a | 730 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
cd28ab6a | 731 | } |
bea86103 | 732 | *last = idx; |
cd28ab6a SH |
733 | } |
734 | ||
793b883e | 735 | |
cd28ab6a SH |
736 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
737 | { | |
738 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
739 | sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE; | |
740 | return le; | |
741 | } | |
742 | ||
a018e330 | 743 | /* Return high part of DMA address (could be 32 or 64 bit) */ |
744 | static inline u32 high32(dma_addr_t a) | |
745 | { | |
746 | return (a >> 16) >> 16; | |
747 | } | |
748 | ||
793b883e | 749 | /* Build description to hardware about buffer */ |
734d1868 | 750 | static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) |
cd28ab6a SH |
751 | { |
752 | struct sky2_rx_le *le; | |
734d1868 SH |
753 | u32 hi = high32(map); |
754 | u16 len = sky2->rx_bufsize; | |
cd28ab6a | 755 | |
793b883e | 756 | if (sky2->rx_addr64 != hi) { |
cd28ab6a | 757 | le = sky2_next_rx(sky2); |
793b883e | 758 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
759 | le->ctrl = 0; |
760 | le->opcode = OP_ADDR64 | HW_OWNER; | |
734d1868 | 761 | sky2->rx_addr64 = high32(map + len); |
cd28ab6a | 762 | } |
793b883e | 763 | |
cd28ab6a | 764 | le = sky2_next_rx(sky2); |
734d1868 SH |
765 | le->addr = cpu_to_le32((u32) map); |
766 | le->length = cpu_to_le16(len); | |
cd28ab6a SH |
767 | le->ctrl = 0; |
768 | le->opcode = OP_PACKET | HW_OWNER; | |
769 | } | |
770 | ||
793b883e | 771 | |
cd28ab6a SH |
772 | /* Tell chip where to start receive checksum. |
773 | * Actually has two checksums, but set both same to avoid possible byte | |
774 | * order problems. | |
775 | */ | |
793b883e | 776 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
777 | { |
778 | struct sky2_rx_le *le; | |
779 | ||
cd28ab6a | 780 | le = sky2_next_rx(sky2); |
793b883e | 781 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
782 | le->ctrl = 0; |
783 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 784 | |
793b883e SH |
785 | sky2_write32(sky2->hw, |
786 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
787 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
788 | |
789 | } | |
790 | ||
6b1a3aef | 791 | /* |
792 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
793 | * reach the end of packet and since we can't make sure that we have | |
794 | * incoming data, we must reset the BMU while it is not doing a DMA | |
795 | * transfer. Since it is possible that the RX path is still active, | |
796 | * the RX RAM buffer will be stopped first, so any possible incoming | |
797 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
798 | * BMU is polled until any DMA in progress is ended and only then it | |
799 | * will be reset. | |
800 | */ | |
801 | static void sky2_rx_stop(struct sky2_port *sky2) | |
802 | { | |
803 | struct sky2_hw *hw = sky2->hw; | |
804 | unsigned rxq = rxqaddr[sky2->port]; | |
805 | int i; | |
806 | ||
807 | /* disable the RAM Buffer receive queue */ | |
808 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
809 | ||
810 | for (i = 0; i < 0xffff; i++) | |
811 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
812 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
813 | goto stopped; | |
814 | ||
815 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
816 | sky2->netdev->name); | |
817 | stopped: | |
818 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
819 | ||
820 | /* reset the Rx prefetch unit */ | |
821 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
822 | } | |
793b883e | 823 | |
d571b694 | 824 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
825 | static void sky2_rx_clean(struct sky2_port *sky2) |
826 | { | |
827 | unsigned i; | |
828 | ||
829 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 830 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
831 | struct ring_info *re = sky2->rx_ring + i; |
832 | ||
833 | if (re->skb) { | |
793b883e | 834 | pci_unmap_single(sky2->hw->pdev, |
734d1868 | 835 | re->mapaddr, sky2->rx_bufsize, |
cd28ab6a SH |
836 | PCI_DMA_FROMDEVICE); |
837 | kfree_skb(re->skb); | |
838 | re->skb = NULL; | |
839 | } | |
840 | } | |
841 | } | |
842 | ||
ef743d33 | 843 | /* Basic MII support */ |
844 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
845 | { | |
846 | struct mii_ioctl_data *data = if_mii(ifr); | |
847 | struct sky2_port *sky2 = netdev_priv(dev); | |
848 | struct sky2_hw *hw = sky2->hw; | |
849 | int err = -EOPNOTSUPP; | |
850 | ||
851 | if (!netif_running(dev)) | |
852 | return -ENODEV; /* Phy still in reset */ | |
853 | ||
854 | switch(cmd) { | |
855 | case SIOCGMIIPHY: | |
856 | data->phy_id = PHY_ADDR_MARV; | |
857 | ||
858 | /* fallthru */ | |
859 | case SIOCGMIIREG: { | |
860 | u16 val = 0; | |
91c86df5 SH |
861 | |
862 | down(&sky2->phy_sema); | |
ef743d33 | 863 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
91c86df5 SH |
864 | up(&sky2->phy_sema); |
865 | ||
ef743d33 | 866 | data->val_out = val; |
867 | break; | |
868 | } | |
869 | ||
870 | case SIOCSMIIREG: | |
871 | if (!capable(CAP_NET_ADMIN)) | |
872 | return -EPERM; | |
873 | ||
91c86df5 | 874 | down(&sky2->phy_sema); |
ef743d33 | 875 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
876 | data->val_in); | |
91c86df5 | 877 | up(&sky2->phy_sema); |
ef743d33 | 878 | break; |
879 | } | |
880 | return err; | |
881 | } | |
882 | ||
d1f13708 | 883 | #ifdef SKY2_VLAN_TAG_USED |
884 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
885 | { | |
886 | struct sky2_port *sky2 = netdev_priv(dev); | |
887 | struct sky2_hw *hw = sky2->hw; | |
888 | u16 port = sky2->port; | |
d1f13708 | 889 | |
f2e46561 | 890 | spin_lock(&sky2->tx_lock); |
d1f13708 | 891 | |
892 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); | |
893 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); | |
894 | sky2->vlgrp = grp; | |
895 | ||
f2e46561 | 896 | spin_unlock(&sky2->tx_lock); |
d1f13708 | 897 | } |
898 | ||
899 | static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
900 | { | |
901 | struct sky2_port *sky2 = netdev_priv(dev); | |
902 | struct sky2_hw *hw = sky2->hw; | |
903 | u16 port = sky2->port; | |
d1f13708 | 904 | |
f2e46561 | 905 | spin_lock(&sky2->tx_lock); |
d1f13708 | 906 | |
907 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); | |
908 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); | |
909 | if (sky2->vlgrp) | |
910 | sky2->vlgrp->vlan_devices[vid] = NULL; | |
911 | ||
f2e46561 | 912 | spin_unlock(&sky2->tx_lock); |
d1f13708 | 913 | } |
914 | #endif | |
915 | ||
82788c7a SH |
916 | /* |
917 | * It appears the hardware has a bug in the FIFO logic that | |
918 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
919 | * is not aligned. ALso alloc_skb() won't align properly if slab | |
920 | * debugging is enabled. | |
921 | */ | |
922 | static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) | |
923 | { | |
924 | struct sk_buff *skb; | |
925 | ||
926 | skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); | |
927 | if (likely(skb)) { | |
928 | unsigned long p = (unsigned long) skb->data; | |
929 | skb_reserve(skb, | |
930 | ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p); | |
931 | } | |
932 | ||
933 | return skb; | |
934 | } | |
935 | ||
cd28ab6a SH |
936 | /* |
937 | * Allocate and setup receiver buffer pool. | |
938 | * In case of 64 bit dma, there are 2X as many list elements | |
939 | * available as ring entries | |
940 | * and need to reserve one list element so we don't wrap around. | |
941 | */ | |
6b1a3aef | 942 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 943 | { |
6b1a3aef | 944 | struct sky2_hw *hw = sky2->hw; |
6b1a3aef | 945 | unsigned rxq = rxqaddr[sky2->port]; |
946 | int i; | |
cd28ab6a | 947 | |
6b1a3aef | 948 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 949 | sky2_qset(hw, rxq); |
6b1a3aef | 950 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
951 | ||
952 | rx_set_checksum(sky2); | |
793b883e | 953 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 954 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 955 | |
82788c7a | 956 | re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); |
cd28ab6a SH |
957 | if (!re->skb) |
958 | goto nomem; | |
959 | ||
6b1a3aef | 960 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
734d1868 SH |
961 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
962 | sky2_rx_add(sky2, re->mapaddr); | |
cd28ab6a SH |
963 | } |
964 | ||
6b1a3aef | 965 | /* Tell chip about available buffers */ |
966 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
967 | sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX)); | |
cd28ab6a SH |
968 | return 0; |
969 | nomem: | |
970 | sky2_rx_clean(sky2); | |
971 | return -ENOMEM; | |
972 | } | |
973 | ||
974 | /* Bring up network interface. */ | |
975 | static int sky2_up(struct net_device *dev) | |
976 | { | |
977 | struct sky2_port *sky2 = netdev_priv(dev); | |
978 | struct sky2_hw *hw = sky2->hw; | |
979 | unsigned port = sky2->port; | |
980 | u32 ramsize, rxspace; | |
981 | int err = -ENOMEM; | |
982 | ||
983 | if (netif_msg_ifup(sky2)) | |
984 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
985 | ||
986 | /* must be power of 2 */ | |
987 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
988 | TX_RING_SIZE * |
989 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
990 | &sky2->tx_le_map); |
991 | if (!sky2->tx_le) | |
992 | goto err_out; | |
993 | ||
6cdbbdf3 | 994 | sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), |
cd28ab6a SH |
995 | GFP_KERNEL); |
996 | if (!sky2->tx_ring) | |
997 | goto err_out; | |
998 | sky2->tx_prod = sky2->tx_cons = 0; | |
cd28ab6a SH |
999 | |
1000 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1001 | &sky2->rx_le_map); | |
1002 | if (!sky2->rx_le) | |
1003 | goto err_out; | |
1004 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1005 | ||
6cdbbdf3 | 1006 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), |
cd28ab6a SH |
1007 | GFP_KERNEL); |
1008 | if (!sky2->rx_ring) | |
1009 | goto err_out; | |
1010 | ||
1011 | sky2_mac_init(hw, port); | |
1012 | ||
1c28f6ba SH |
1013 | /* Determine available ram buffer space (in 4K blocks). |
1014 | * Note: not sure about the FE setting below yet | |
1015 | */ | |
1016 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
1017 | ramsize = 4; | |
1018 | else | |
1019 | ramsize = sky2_read8(hw, B2_E_0); | |
1020 | ||
1021 | /* Give transmitter one third (rounded up) */ | |
1022 | rxspace = ramsize - (ramsize + 2) / 3; | |
cd28ab6a | 1023 | |
cd28ab6a | 1024 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1c28f6ba | 1025 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize); |
cd28ab6a | 1026 | |
793b883e SH |
1027 | /* Make sure SyncQ is disabled */ |
1028 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1029 | RB_RST_SET); | |
1030 | ||
af4ed7e6 | 1031 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1032 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) |
1033 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | |
1034 | ||
1035 | ||
6b1a3aef | 1036 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1037 | TX_RING_SIZE - 1); | |
cd28ab6a | 1038 | |
6b1a3aef | 1039 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
1040 | if (err) |
1041 | goto err_out; | |
1042 | ||
cd28ab6a SH |
1043 | /* Enable interrupts from phy/mac for port */ |
1044 | hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2; | |
1045 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1046 | return 0; | |
1047 | ||
1048 | err_out: | |
1b537565 | 1049 | if (sky2->rx_le) { |
cd28ab6a SH |
1050 | pci_free_consistent(hw->pdev, RX_LE_BYTES, |
1051 | sky2->rx_le, sky2->rx_le_map); | |
1b537565 SH |
1052 | sky2->rx_le = NULL; |
1053 | } | |
1054 | if (sky2->tx_le) { | |
cd28ab6a SH |
1055 | pci_free_consistent(hw->pdev, |
1056 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1057 | sky2->tx_le, sky2->tx_le_map); | |
1b537565 SH |
1058 | sky2->tx_le = NULL; |
1059 | } | |
1060 | kfree(sky2->tx_ring); | |
1061 | kfree(sky2->rx_ring); | |
cd28ab6a | 1062 | |
1b537565 SH |
1063 | sky2->tx_ring = NULL; |
1064 | sky2->rx_ring = NULL; | |
cd28ab6a SH |
1065 | return err; |
1066 | } | |
1067 | ||
793b883e SH |
1068 | /* Modular subtraction in ring */ |
1069 | static inline int tx_dist(unsigned tail, unsigned head) | |
1070 | { | |
129372d0 | 1071 | return (head - tail) % TX_RING_SIZE; |
793b883e | 1072 | } |
cd28ab6a | 1073 | |
793b883e SH |
1074 | /* Number of list elements available for next tx */ |
1075 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1076 | { |
793b883e | 1077 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1078 | } |
1079 | ||
793b883e SH |
1080 | /* Estimate of number of transmit list elements required */ |
1081 | static inline unsigned tx_le_req(const struct sk_buff *skb) | |
cd28ab6a | 1082 | { |
793b883e SH |
1083 | unsigned count; |
1084 | ||
1085 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1086 | count += skb_shinfo(skb)->nr_frags * count; | |
1087 | ||
1088 | if (skb_shinfo(skb)->tso_size) | |
1089 | ++count; | |
1090 | ||
0e3ff6aa | 1091 | if (skb->ip_summed == CHECKSUM_HW) |
793b883e SH |
1092 | ++count; |
1093 | ||
1094 | return count; | |
cd28ab6a SH |
1095 | } |
1096 | ||
793b883e SH |
1097 | /* |
1098 | * Put one packet in ring for transmit. | |
1099 | * A single packet can generate multiple list elements, and | |
1100 | * the number of ring elements will probably be less than the number | |
1101 | * of list elements used. | |
f2e46561 SH |
1102 | * |
1103 | * No BH disabling for tx_lock here (like tg3) | |
793b883e | 1104 | */ |
cd28ab6a SH |
1105 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1106 | { | |
1107 | struct sky2_port *sky2 = netdev_priv(dev); | |
1108 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1109 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1110 | struct tx_ring_info *re; |
cd28ab6a SH |
1111 | unsigned i, len; |
1112 | dma_addr_t mapping; | |
1113 | u32 addr64; | |
1114 | u16 mss; | |
1115 | u8 ctrl; | |
1116 | ||
f2e46561 | 1117 | if (!spin_trylock(&sky2->tx_lock)) |
cd28ab6a SH |
1118 | return NETDEV_TX_LOCKED; |
1119 | ||
793b883e | 1120 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
8c463ef7 SH |
1121 | /* There is a known but harmless race with lockless tx |
1122 | * and netif_stop_queue. | |
1123 | */ | |
1124 | if (!netif_queue_stopped(dev)) { | |
1125 | netif_stop_queue(dev); | |
1126 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
1127 | dev->name); | |
1128 | } | |
f2e46561 | 1129 | spin_unlock(&sky2->tx_lock); |
cd28ab6a | 1130 | |
cd28ab6a SH |
1131 | return NETDEV_TX_BUSY; |
1132 | } | |
1133 | ||
793b883e | 1134 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1135 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1136 | dev->name, sky2->tx_prod, skb->len); | |
1137 | ||
cd28ab6a SH |
1138 | len = skb_headlen(skb); |
1139 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
a018e330 | 1140 | addr64 = high32(mapping); |
793b883e SH |
1141 | |
1142 | re = sky2->tx_ring + sky2->tx_prod; | |
1143 | ||
a018e330 | 1144 | /* Send high bits if changed or crosses boundary */ |
1145 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | |
793b883e SH |
1146 | le = get_tx_le(sky2); |
1147 | le->tx.addr = cpu_to_le32(addr64); | |
1148 | le->ctrl = 0; | |
1149 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 1150 | sky2->tx_addr64 = high32(mapping + len); |
793b883e | 1151 | } |
cd28ab6a SH |
1152 | |
1153 | /* Check for TCP Segmentation Offload */ | |
1154 | mss = skb_shinfo(skb)->tso_size; | |
793b883e | 1155 | if (mss != 0) { |
cd28ab6a SH |
1156 | /* just drop the packet if non-linear expansion fails */ |
1157 | if (skb_header_cloned(skb) && | |
1158 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
793b883e SH |
1159 | dev_kfree_skb_any(skb); |
1160 | goto out_unlock; | |
cd28ab6a SH |
1161 | } |
1162 | ||
1163 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | |
1164 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
1165 | mss += ETH_HLEN; | |
793b883e | 1166 | } |
cd28ab6a | 1167 | |
793b883e | 1168 | if (mss != sky2->tx_last_mss) { |
cd28ab6a SH |
1169 | le = get_tx_le(sky2); |
1170 | le->tx.tso.size = cpu_to_le16(mss); | |
793b883e | 1171 | le->tx.tso.rsvd = 0; |
cd28ab6a | 1172 | le->opcode = OP_LRGLEN | HW_OWNER; |
cd28ab6a | 1173 | le->ctrl = 0; |
793b883e | 1174 | sky2->tx_last_mss = mss; |
cd28ab6a SH |
1175 | } |
1176 | ||
cd28ab6a | 1177 | ctrl = 0; |
d1f13708 | 1178 | #ifdef SKY2_VLAN_TAG_USED |
1179 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1180 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1181 | if (!le) { | |
1182 | le = get_tx_le(sky2); | |
1183 | le->tx.addr = 0; | |
1184 | le->opcode = OP_VLAN|HW_OWNER; | |
1185 | le->ctrl = 0; | |
1186 | } else | |
1187 | le->opcode |= OP_VLAN; | |
1188 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1189 | ctrl |= INS_VLAN; | |
1190 | } | |
1191 | #endif | |
1192 | ||
1193 | /* Handle TCP checksum offload */ | |
cd28ab6a | 1194 | if (skb->ip_summed == CHECKSUM_HW) { |
793b883e SH |
1195 | u16 hdr = skb->h.raw - skb->data; |
1196 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
1197 | |
1198 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1199 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
1200 | ctrl |= UDPTCP; | |
1201 | ||
1202 | le = get_tx_le(sky2); | |
1203 | le->tx.csum.start = cpu_to_le16(hdr); | |
793b883e SH |
1204 | le->tx.csum.offset = cpu_to_le16(offset); |
1205 | le->length = 0; /* initial checksum value */ | |
cd28ab6a | 1206 | le->ctrl = 1; /* one packet */ |
793b883e | 1207 | le->opcode = OP_TCPLISW | HW_OWNER; |
cd28ab6a SH |
1208 | } |
1209 | ||
1210 | le = get_tx_le(sky2); | |
1211 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1212 | le->length = cpu_to_le16(len); | |
1213 | le->ctrl = ctrl; | |
793b883e | 1214 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1215 | |
793b883e | 1216 | /* Record the transmit mapping info */ |
cd28ab6a | 1217 | re->skb = skb; |
6cdbbdf3 | 1218 | pci_unmap_addr_set(re, mapaddr, mapping); |
cd28ab6a SH |
1219 | |
1220 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1221 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6cdbbdf3 | 1222 | struct tx_ring_info *fre; |
cd28ab6a SH |
1223 | |
1224 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1225 | frag->size, PCI_DMA_TODEVICE); | |
793b883e SH |
1226 | addr64 = (mapping >> 16) >> 16; |
1227 | if (addr64 != sky2->tx_addr64) { | |
1228 | le = get_tx_le(sky2); | |
1229 | le->tx.addr = cpu_to_le32(addr64); | |
1230 | le->ctrl = 0; | |
1231 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1232 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1233 | } |
1234 | ||
1235 | le = get_tx_le(sky2); | |
1236 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1237 | le->length = cpu_to_le16(frag->size); | |
1238 | le->ctrl = ctrl; | |
793b883e | 1239 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1240 | |
793b883e SH |
1241 | fre = sky2->tx_ring |
1242 | + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE; | |
6cdbbdf3 | 1243 | pci_unmap_addr_set(fre, mapaddr, mapping); |
cd28ab6a | 1244 | } |
6cdbbdf3 | 1245 | |
793b883e | 1246 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1247 | le->ctrl |= EOP; |
1248 | ||
724bca3c | 1249 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod, |
cd28ab6a SH |
1250 | &sky2->tx_last_put, TX_RING_SIZE); |
1251 | ||
0e3ff6aa | 1252 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
cd28ab6a | 1253 | netif_stop_queue(dev); |
793b883e SH |
1254 | |
1255 | out_unlock: | |
1256 | mmiowb(); | |
f2e46561 | 1257 | spin_unlock(&sky2->tx_lock); |
cd28ab6a SH |
1258 | |
1259 | dev->trans_start = jiffies; | |
1260 | return NETDEV_TX_OK; | |
1261 | } | |
1262 | ||
cd28ab6a | 1263 | /* |
793b883e SH |
1264 | * Free ring elements from starting at tx_cons until "done" |
1265 | * | |
1266 | * NB: the hardware will tell us about partial completion of multi-part | |
d571b694 | 1267 | * buffers; these are deferred until completion. |
cd28ab6a | 1268 | */ |
d11c13e7 | 1269 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1270 | { |
d11c13e7 | 1271 | struct net_device *dev = sky2->netdev; |
af2a58ac SH |
1272 | struct pci_dev *pdev = sky2->hw->pdev; |
1273 | u16 nxt, put; | |
793b883e | 1274 | unsigned i; |
cd28ab6a | 1275 | |
0e3ff6aa | 1276 | BUG_ON(done >= TX_RING_SIZE); |
2224795d | 1277 | |
d11c13e7 | 1278 | if (unlikely(netif_msg_tx_done(sky2))) |
d571b694 | 1279 | printk(KERN_DEBUG "%s: tx done, up to %u\n", |
d11c13e7 | 1280 | dev->name, done); |
cd28ab6a | 1281 | |
af2a58ac SH |
1282 | for (put = sky2->tx_cons; put != done; put = nxt) { |
1283 | struct tx_ring_info *re = sky2->tx_ring + put; | |
1284 | struct sk_buff *skb = re->skb; | |
cd28ab6a | 1285 | |
af2a58ac SH |
1286 | nxt = re->idx; |
1287 | BUG_ON(nxt >= TX_RING_SIZE); | |
d70cd51a | 1288 | prefetch(sky2->tx_ring + nxt); |
cd28ab6a | 1289 | |
793b883e | 1290 | /* Check for partial status */ |
af2a58ac SH |
1291 | if (tx_dist(put, done) < tx_dist(put, nxt)) |
1292 | break; | |
793b883e SH |
1293 | |
1294 | skb = re->skb; | |
af2a58ac | 1295 | pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), |
734d1868 | 1296 | skb_headlen(skb), PCI_DMA_TODEVICE); |
793b883e SH |
1297 | |
1298 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6cdbbdf3 | 1299 | struct tx_ring_info *fre; |
af2a58ac SH |
1300 | fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE; |
1301 | pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), | |
1302 | skb_shinfo(skb)->frags[i].size, | |
734d1868 | 1303 | PCI_DMA_TODEVICE); |
cd28ab6a SH |
1304 | } |
1305 | ||
cd28ab6a | 1306 | dev_kfree_skb_any(skb); |
793b883e | 1307 | } |
793b883e | 1308 | |
af2a58ac SH |
1309 | spin_lock(&sky2->tx_lock); |
1310 | sky2->tx_cons = put; | |
793b883e | 1311 | if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE) |
cd28ab6a SH |
1312 | netif_wake_queue(dev); |
1313 | spin_unlock(&sky2->tx_lock); | |
1314 | } | |
1315 | ||
1316 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
13b97b74 | 1317 | static void sky2_tx_clean(struct sky2_port *sky2) |
cd28ab6a | 1318 | { |
d11c13e7 | 1319 | sky2_tx_complete(sky2, sky2->tx_prod); |
cd28ab6a SH |
1320 | } |
1321 | ||
1322 | /* Network shutdown */ | |
1323 | static int sky2_down(struct net_device *dev) | |
1324 | { | |
1325 | struct sky2_port *sky2 = netdev_priv(dev); | |
1326 | struct sky2_hw *hw = sky2->hw; | |
1327 | unsigned port = sky2->port; | |
1328 | u16 ctrl; | |
cd28ab6a | 1329 | |
1b537565 SH |
1330 | /* Never really got started! */ |
1331 | if (!sky2->tx_le) | |
1332 | return 0; | |
1333 | ||
cd28ab6a SH |
1334 | if (netif_msg_ifdown(sky2)) |
1335 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1336 | ||
018d1c66 | 1337 | /* Stop more packets from being queued */ |
cd28ab6a SH |
1338 | netif_stop_queue(dev); |
1339 | ||
018d1c66 | 1340 | /* Disable port IRQ */ |
1341 | local_irq_disable(); | |
1342 | hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
1343 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
1344 | local_irq_enable(); | |
1345 | ||
91c86df5 | 1346 | flush_scheduled_work(); |
018d1c66 | 1347 | |
793b883e SH |
1348 | sky2_phy_reset(hw, port); |
1349 | ||
cd28ab6a SH |
1350 | /* Stop transmitter */ |
1351 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1352 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1353 | ||
1354 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1355 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1356 | |
1357 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1358 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1359 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1360 | ||
1361 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1362 | ||
1363 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1364 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1365 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1366 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1367 | ||
1368 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1369 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1370 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1371 | ||
1372 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1373 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1374 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1375 | ||
1376 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1377 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1378 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1379 | |
1380 | /* Reset the Tx prefetch units */ | |
1381 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1382 | PREF_UNIT_RST_SET); | |
1383 | ||
1384 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1385 | ||
6b1a3aef | 1386 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1387 | |
1388 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1389 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1390 | ||
d571b694 | 1391 | /* turn off LED's */ |
cd28ab6a SH |
1392 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1393 | ||
018d1c66 | 1394 | synchronize_irq(hw->pdev->irq); |
1395 | ||
cd28ab6a SH |
1396 | sky2_tx_clean(sky2); |
1397 | sky2_rx_clean(sky2); | |
1398 | ||
1399 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1400 | sky2->rx_le, sky2->rx_le_map); | |
1401 | kfree(sky2->rx_ring); | |
1402 | ||
1403 | pci_free_consistent(hw->pdev, | |
1404 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1405 | sky2->tx_le, sky2->tx_le_map); | |
1406 | kfree(sky2->tx_ring); | |
1407 | ||
1b537565 SH |
1408 | sky2->tx_le = NULL; |
1409 | sky2->rx_le = NULL; | |
1410 | ||
1411 | sky2->rx_ring = NULL; | |
1412 | sky2->tx_ring = NULL; | |
1413 | ||
cd28ab6a SH |
1414 | return 0; |
1415 | } | |
1416 | ||
1417 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1418 | { | |
793b883e SH |
1419 | if (!hw->copper) |
1420 | return SPEED_1000; | |
1421 | ||
cd28ab6a SH |
1422 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1423 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1424 | ||
1425 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1426 | case PHY_M_PS_SPEED_1000: | |
1427 | return SPEED_1000; | |
1428 | case PHY_M_PS_SPEED_100: | |
1429 | return SPEED_100; | |
1430 | default: | |
1431 | return SPEED_10; | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | static void sky2_link_up(struct sky2_port *sky2) | |
1436 | { | |
1437 | struct sky2_hw *hw = sky2->hw; | |
1438 | unsigned port = sky2->port; | |
1439 | u16 reg; | |
1440 | ||
1441 | /* Enable Transmit FIFO Underrun */ | |
793b883e | 1442 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1443 | |
1444 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1445 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) | |
1446 | reg |= GM_GPCR_DUP_FULL; | |
1447 | ||
cd28ab6a SH |
1448 | /* enable Rx/Tx */ |
1449 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1450 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1451 | gma_read16(hw, port, GM_GP_CTRL); | |
1452 | ||
1453 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1454 | ||
1455 | netif_carrier_on(sky2->netdev); | |
1456 | netif_wake_queue(sky2->netdev); | |
1457 | ||
1458 | /* Turn on link LED */ | |
793b883e | 1459 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1460 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1461 | ||
793b883e SH |
1462 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
1463 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
1464 | ||
1465 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
1466 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
1467 | PHY_M_LEDC_INIT_CTRL(sky2->speed == | |
1468 | SPEED_10 ? 7 : 0) | | |
1469 | PHY_M_LEDC_STA1_CTRL(sky2->speed == | |
1470 | SPEED_100 ? 7 : 0) | | |
1471 | PHY_M_LEDC_STA0_CTRL(sky2->speed == | |
1472 | SPEED_1000 ? 7 : 0)); | |
1473 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
1474 | } | |
1475 | ||
cd28ab6a SH |
1476 | if (netif_msg_link(sky2)) |
1477 | printk(KERN_INFO PFX | |
d571b694 | 1478 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1479 | sky2->netdev->name, sky2->speed, |
1480 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1481 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1482 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1483 | } |
1484 | ||
1485 | static void sky2_link_down(struct sky2_port *sky2) | |
1486 | { | |
1487 | struct sky2_hw *hw = sky2->hw; | |
1488 | unsigned port = sky2->port; | |
1489 | u16 reg; | |
1490 | ||
1491 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1492 | ||
1493 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1494 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1495 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1496 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1497 | ||
1498 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1499 | /* restore Asymmetric Pause bit */ | |
1500 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1501 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1502 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1503 | } |
1504 | ||
cd28ab6a SH |
1505 | netif_carrier_off(sky2->netdev); |
1506 | netif_stop_queue(sky2->netdev); | |
1507 | ||
1508 | /* Turn on link LED */ | |
1509 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1510 | ||
1511 | if (netif_msg_link(sky2)) | |
1512 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1513 | sky2_phy_init(hw, port); | |
1514 | } | |
1515 | ||
793b883e SH |
1516 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1517 | { | |
1518 | struct sky2_hw *hw = sky2->hw; | |
1519 | unsigned port = sky2->port; | |
1520 | u16 lpa; | |
1521 | ||
1522 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1523 | ||
1524 | if (lpa & PHY_M_AN_RF) { | |
1525 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1526 | return -1; | |
1527 | } | |
1528 | ||
1529 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1530 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1531 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1532 | sky2->netdev->name); | |
1533 | return -1; | |
1534 | } | |
1535 | ||
1536 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1537 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1538 | sky2->netdev->name); | |
1539 | return -1; | |
1540 | } | |
1541 | ||
1542 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1543 | ||
1544 | sky2->speed = sky2_phy_speed(hw, aux); | |
1545 | ||
1546 | /* Pause bits are offset (9..8) */ | |
1547 | if (hw->chip_id == CHIP_ID_YUKON_XL) | |
1548 | aux >>= 6; | |
1549 | ||
1550 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1551 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1552 | ||
1553 | if ((sky2->tx_pause || sky2->rx_pause) | |
1554 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1555 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1556 | else | |
1557 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1558 | ||
1559 | return 0; | |
1560 | } | |
cd28ab6a SH |
1561 | |
1562 | /* | |
91c86df5 | 1563 | * Interrupt from PHY are handled outside of interrupt context |
cd28ab6a SH |
1564 | * because accessing phy registers requires spin wait which might |
1565 | * cause excess interrupt latency. | |
1566 | */ | |
91c86df5 | 1567 | static void sky2_phy_task(void *arg) |
cd28ab6a | 1568 | { |
91c86df5 | 1569 | struct sky2_port *sky2 = arg; |
cd28ab6a | 1570 | struct sky2_hw *hw = sky2->hw; |
cd28ab6a SH |
1571 | u16 istatus, phystat; |
1572 | ||
91c86df5 | 1573 | down(&sky2->phy_sema); |
793b883e SH |
1574 | istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT); |
1575 | phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT); | |
cd28ab6a SH |
1576 | |
1577 | if (netif_msg_intr(sky2)) | |
1578 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1579 | sky2->netdev->name, istatus, phystat); | |
1580 | ||
1581 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1582 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1583 | sky2_link_up(sky2); | |
1584 | goto out; | |
1585 | } | |
cd28ab6a | 1586 | |
793b883e SH |
1587 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1588 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1589 | |
793b883e SH |
1590 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1591 | sky2->duplex = | |
1592 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1593 | |
793b883e SH |
1594 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1595 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1596 | sky2_link_up(sky2); |
793b883e SH |
1597 | else |
1598 | sky2_link_down(sky2); | |
cd28ab6a | 1599 | } |
793b883e | 1600 | out: |
91c86df5 | 1601 | up(&sky2->phy_sema); |
cd28ab6a SH |
1602 | |
1603 | local_irq_disable(); | |
793b883e | 1604 | hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2; |
cd28ab6a SH |
1605 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
1606 | local_irq_enable(); | |
1607 | } | |
1608 | ||
1609 | static void sky2_tx_timeout(struct net_device *dev) | |
1610 | { | |
1611 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 SH |
1612 | struct sky2_hw *hw = sky2->hw; |
1613 | unsigned txq = txqaddr[sky2->port]; | |
cd28ab6a SH |
1614 | |
1615 | if (netif_msg_timer(sky2)) | |
1616 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1617 | ||
8cc048e3 SH |
1618 | netif_stop_queue(dev); |
1619 | ||
1620 | sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); | |
1621 | sky2_read32(hw, Q_ADDR(txq, Q_CSR)); | |
1622 | ||
1623 | sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
cd28ab6a SH |
1624 | |
1625 | sky2_tx_clean(sky2); | |
8cc048e3 SH |
1626 | |
1627 | sky2_qset(hw, txq); | |
1628 | sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); | |
1629 | ||
1630 | netif_wake_queue(dev); | |
cd28ab6a SH |
1631 | } |
1632 | ||
734d1868 SH |
1633 | |
1634 | #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) | |
1635 | /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */ | |
1636 | static inline unsigned sky2_buf_size(int mtu) | |
1637 | { | |
1638 | return roundup(mtu + ETH_HLEN + 4, 8); | |
1639 | } | |
1640 | ||
cd28ab6a SH |
1641 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) |
1642 | { | |
6b1a3aef | 1643 | struct sky2_port *sky2 = netdev_priv(dev); |
1644 | struct sky2_hw *hw = sky2->hw; | |
1645 | int err; | |
1646 | u16 ctl, mode; | |
cd28ab6a SH |
1647 | |
1648 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1649 | return -EINVAL; | |
1650 | ||
5a5b1ea0 | 1651 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) |
1652 | return -EINVAL; | |
1653 | ||
6b1a3aef | 1654 | if (!netif_running(dev)) { |
1655 | dev->mtu = new_mtu; | |
1656 | return 0; | |
1657 | } | |
1658 | ||
6b1a3aef | 1659 | sky2_write32(hw, B0_IMSK, 0); |
1660 | ||
018d1c66 | 1661 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1662 | netif_stop_queue(dev); | |
1663 | netif_poll_disable(hw->dev[0]); | |
1664 | ||
6b1a3aef | 1665 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); |
1666 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1667 | sky2_rx_stop(sky2); | |
1668 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1669 | |
1670 | dev->mtu = new_mtu; | |
734d1868 | 1671 | sky2->rx_bufsize = sky2_buf_size(new_mtu); |
6b1a3aef | 1672 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1673 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1674 | ||
1675 | if (dev->mtu > ETH_DATA_LEN) | |
1676 | mode |= GM_SMOD_JUMBO_ENA; | |
1677 | ||
1678 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1679 | |
6b1a3aef | 1680 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1681 | |
6b1a3aef | 1682 | err = sky2_rx_start(sky2); |
6b1a3aef | 1683 | sky2_write32(hw, B0_IMSK, hw->intr_mask); |
018d1c66 | 1684 | |
1b537565 SH |
1685 | if (err) |
1686 | dev_close(dev); | |
1687 | else { | |
1688 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1689 | ||
1690 | netif_poll_enable(hw->dev[0]); | |
1691 | netif_wake_queue(dev); | |
1692 | } | |
1693 | ||
cd28ab6a SH |
1694 | return err; |
1695 | } | |
1696 | ||
1697 | /* | |
1698 | * Receive one packet. | |
1699 | * For small packets or errors, just reuse existing skb. | |
d571b694 | 1700 | * For larger packets, get new buffer. |
cd28ab6a | 1701 | */ |
d11c13e7 | 1702 | static struct sk_buff *sky2_receive(struct sky2_port *sky2, |
cd28ab6a SH |
1703 | u16 length, u32 status) |
1704 | { | |
cd28ab6a | 1705 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 1706 | struct sk_buff *skb = NULL; |
cd28ab6a SH |
1707 | |
1708 | if (unlikely(netif_msg_rx_status(sky2))) | |
1709 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
d11c13e7 | 1710 | sky2->netdev->name, sky2->rx_next, status, length); |
cd28ab6a | 1711 | |
793b883e | 1712 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 1713 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 1714 | |
42eeea01 | 1715 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
1716 | goto error; |
1717 | ||
42eeea01 | 1718 | if (!(status & GMR_FS_RX_OK)) |
1719 | goto resubmit; | |
1720 | ||
6e15b712 SH |
1721 | if ((status >> 16) != length || length > sky2->rx_bufsize) |
1722 | goto oversize; | |
1723 | ||
bdb5c58e | 1724 | if (length < copybreak) { |
79e57d32 SH |
1725 | skb = alloc_skb(length + 2, GFP_ATOMIC); |
1726 | if (!skb) | |
793b883e SH |
1727 | goto resubmit; |
1728 | ||
79e57d32 | 1729 | skb_reserve(skb, 2); |
793b883e SH |
1730 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1731 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1732 | memcpy(skb->data, re->skb->data, length); |
d11c13e7 | 1733 | skb->ip_summed = re->skb->ip_summed; |
1734 | skb->csum = re->skb->csum; | |
793b883e SH |
1735 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1736 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1737 | } else { |
79e57d32 SH |
1738 | struct sk_buff *nskb; |
1739 | ||
82788c7a | 1740 | nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); |
793b883e SH |
1741 | if (!nskb) |
1742 | goto resubmit; | |
cd28ab6a | 1743 | |
793b883e | 1744 | skb = re->skb; |
79e57d32 | 1745 | re->skb = nskb; |
793b883e | 1746 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
734d1868 | 1747 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1748 | prefetch(skb->data); |
cd28ab6a | 1749 | |
793b883e | 1750 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
734d1868 | 1751 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1752 | } |
cd28ab6a | 1753 | |
79e57d32 | 1754 | skb_put(skb, length); |
793b883e | 1755 | resubmit: |
d11c13e7 | 1756 | re->skb->ip_summed = CHECKSUM_NONE; |
734d1868 | 1757 | sky2_rx_add(sky2, re->mapaddr); |
79e57d32 | 1758 | |
bea86103 | 1759 | /* Tell receiver about new buffers. */ |
1760 | sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put, | |
1761 | &sky2->rx_last_put, RX_LE_SIZE); | |
1762 | ||
cd28ab6a SH |
1763 | return skb; |
1764 | ||
6e15b712 SH |
1765 | oversize: |
1766 | ++sky2->net_stats.rx_over_errors; | |
1767 | goto resubmit; | |
1768 | ||
cd28ab6a | 1769 | error: |
6e15b712 SH |
1770 | ++sky2->net_stats.rx_errors; |
1771 | ||
cd28ab6a SH |
1772 | if (netif_msg_rx_err(sky2)) |
1773 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", | |
1774 | sky2->netdev->name, status, length); | |
793b883e SH |
1775 | |
1776 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1777 | sky2->net_stats.rx_length_errors++; |
1778 | if (status & GMR_FS_FRAGMENT) | |
1779 | sky2->net_stats.rx_frame_errors++; | |
1780 | if (status & GMR_FS_CRC_ERR) | |
1781 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1782 | if (status & GMR_FS_RX_FF_OV) |
1783 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1784 | |
793b883e | 1785 | goto resubmit; |
cd28ab6a SH |
1786 | } |
1787 | ||
2224795d | 1788 | /* |
1789 | * Check for transmit complete | |
793b883e | 1790 | */ |
13b97b74 | 1791 | #define TX_NO_STATUS 0xffff |
2224795d | 1792 | |
13b97b74 SH |
1793 | static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last) |
1794 | { | |
1795 | if (last != TX_NO_STATUS) { | |
1796 | struct net_device *dev = hw->dev[port]; | |
1797 | if (dev && netif_running(dev)) { | |
1798 | struct sky2_port *sky2 = netdev_priv(dev); | |
1799 | sky2_tx_complete(sky2, last); | |
1800 | } | |
2224795d | 1801 | } |
cd28ab6a SH |
1802 | } |
1803 | ||
1804 | /* | |
cd28ab6a SH |
1805 | * Both ports share the same status interrupt, therefore there is only |
1806 | * one poll routine. | |
cd28ab6a | 1807 | */ |
d11c13e7 | 1808 | static int sky2_poll(struct net_device *dev0, int *budget) |
cd28ab6a | 1809 | { |
d11c13e7 | 1810 | struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; |
1811 | unsigned int to_do = min(dev0->quota, *budget); | |
cd28ab6a | 1812 | unsigned int work_done = 0; |
793b883e | 1813 | u16 hwidx; |
13b97b74 | 1814 | u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS }; |
cd28ab6a | 1815 | |
793b883e | 1816 | hwidx = sky2_read16(hw, STAT_PUT_IDX); |
79e57d32 | 1817 | BUG_ON(hwidx >= STATUS_RING_SIZE); |
af2a58ac | 1818 | rmb(); |
bea86103 | 1819 | |
13210ce5 | 1820 | while (hwidx != hw->st_idx) { |
1821 | struct sky2_status_le *le = hw->st_le + hw->st_idx; | |
1822 | struct net_device *dev; | |
d11c13e7 | 1823 | struct sky2_port *sky2; |
cd28ab6a | 1824 | struct sk_buff *skb; |
cd28ab6a SH |
1825 | u32 status; |
1826 | u16 length; | |
13210ce5 | 1827 | u8 op; |
cd28ab6a | 1828 | |
13210ce5 | 1829 | le = hw->st_le + hw->st_idx; |
bea86103 | 1830 | hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE; |
13210ce5 | 1831 | prefetch(hw->st_le + hw->st_idx); |
bea86103 | 1832 | |
13210ce5 | 1833 | BUG_ON(le->link >= 2); |
1834 | dev = hw->dev[le->link]; | |
1835 | if (dev == NULL || !netif_running(dev)) | |
1836 | continue; | |
1837 | ||
1838 | sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1839 | status = le32_to_cpu(le->status); |
1840 | length = le16_to_cpu(le->length); | |
13210ce5 | 1841 | op = le->opcode & ~HW_OWNER; |
1842 | le->opcode = 0; | |
cd28ab6a | 1843 | |
13210ce5 | 1844 | switch (op) { |
cd28ab6a | 1845 | case OP_RXSTAT: |
d11c13e7 | 1846 | skb = sky2_receive(sky2, length, status); |
d1f13708 | 1847 | if (!skb) |
1848 | break; | |
13210ce5 | 1849 | |
1850 | skb->dev = dev; | |
1851 | skb->protocol = eth_type_trans(skb, dev); | |
1852 | dev->last_rx = jiffies; | |
1853 | ||
d1f13708 | 1854 | #ifdef SKY2_VLAN_TAG_USED |
1855 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
1856 | vlan_hwaccel_receive_skb(skb, | |
1857 | sky2->vlgrp, | |
1858 | be16_to_cpu(sky2->rx_tag)); | |
1859 | } else | |
1860 | #endif | |
cd28ab6a | 1861 | netif_receive_skb(skb); |
13210ce5 | 1862 | |
1863 | if (++work_done >= to_do) | |
1864 | goto exit_loop; | |
cd28ab6a SH |
1865 | break; |
1866 | ||
d1f13708 | 1867 | #ifdef SKY2_VLAN_TAG_USED |
1868 | case OP_RXVLAN: | |
1869 | sky2->rx_tag = length; | |
1870 | break; | |
1871 | ||
1872 | case OP_RXCHKSVLAN: | |
1873 | sky2->rx_tag = length; | |
1874 | /* fall through */ | |
1875 | #endif | |
cd28ab6a | 1876 | case OP_RXCHKS: |
d11c13e7 | 1877 | skb = sky2->rx_ring[sky2->rx_next].skb; |
1878 | skb->ip_summed = CHECKSUM_HW; | |
1879 | skb->csum = le16_to_cpu(status); | |
cd28ab6a SH |
1880 | break; |
1881 | ||
1882 | case OP_TXINDEXLE: | |
13b97b74 SH |
1883 | /* TX index reports status for both ports */ |
1884 | tx_done[0] = status & 0xffff; | |
1885 | tx_done[1] = ((status >> 24) & 0xff) | |
1886 | | (u16)(length & 0xf) << 8; | |
cd28ab6a SH |
1887 | break; |
1888 | ||
cd28ab6a SH |
1889 | default: |
1890 | if (net_ratelimit()) | |
793b883e | 1891 | printk(KERN_WARNING PFX |
13210ce5 | 1892 | "unknown status opcode 0x%x\n", op); |
cd28ab6a SH |
1893 | break; |
1894 | } | |
13210ce5 | 1895 | } |
cd28ab6a | 1896 | |
13210ce5 | 1897 | exit_loop: |
3e4b32e1 | 1898 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); |
793b883e SH |
1899 | mmiowb(); |
1900 | ||
13b97b74 SH |
1901 | sky2_tx_check(hw, 0, tx_done[0]); |
1902 | sky2_tx_check(hw, 1, tx_done[1]); | |
1903 | ||
3e4b32e1 | 1904 | if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) { |
13b97b74 | 1905 | /* need to restart TX timer */ |
cd28ab6a SH |
1906 | if (is_ec_a1(hw)) { |
1907 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1908 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1909 | } | |
1910 | ||
bea86103 | 1911 | netif_rx_complete(dev0); |
cd28ab6a SH |
1912 | hw->intr_mask |= Y2_IS_STAT_BMU; |
1913 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
13210ce5 | 1914 | mmiowb(); |
1915 | return 0; | |
1916 | } else { | |
1917 | *budget -= work_done; | |
1918 | dev0->quota -= work_done; | |
1919 | return 1; | |
cd28ab6a | 1920 | } |
cd28ab6a SH |
1921 | } |
1922 | ||
1923 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
1924 | { | |
1925 | struct net_device *dev = hw->dev[port]; | |
1926 | ||
1927 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
1928 | dev->name, status); | |
1929 | ||
1930 | if (status & Y2_IS_PAR_RD1) { | |
1931 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
1932 | dev->name); | |
1933 | /* Clear IRQ */ | |
1934 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
1935 | } | |
1936 | ||
1937 | if (status & Y2_IS_PAR_WR1) { | |
1938 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
1939 | dev->name); | |
1940 | ||
1941 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
1942 | } | |
1943 | ||
1944 | if (status & Y2_IS_PAR_MAC1) { | |
1945 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
1946 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); | |
1947 | } | |
1948 | ||
1949 | if (status & Y2_IS_PAR_RX1) { | |
1950 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
1951 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); | |
1952 | } | |
1953 | ||
1954 | if (status & Y2_IS_TCP_TXA1) { | |
1955 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name); | |
1956 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); | |
1957 | } | |
1958 | } | |
1959 | ||
1960 | static void sky2_hw_intr(struct sky2_hw *hw) | |
1961 | { | |
1962 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
1963 | ||
793b883e | 1964 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 1965 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
1966 | |
1967 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
1968 | u16 pci_err; |
1969 | ||
1970 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err); | |
cd28ab6a SH |
1971 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", |
1972 | pci_name(hw->pdev), pci_err); | |
1973 | ||
1974 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
1975 | pci_write_config_word(hw->pdev, PCI_STATUS, |
1976 | pci_err | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
1977 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1978 | } | |
1979 | ||
1980 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 1981 | /* PCI-Express uncorrectable Error occurred */ |
793b883e SH |
1982 | u32 pex_err; |
1983 | ||
1984 | pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err); | |
cd28ab6a | 1985 | |
cd28ab6a SH |
1986 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", |
1987 | pci_name(hw->pdev), pex_err); | |
1988 | ||
1989 | /* clear the interrupt */ | |
1990 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
793b883e SH |
1991 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, |
1992 | 0xffffffffUL); | |
cd28ab6a SH |
1993 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
1994 | ||
1995 | if (pex_err & PEX_FATAL_ERRORS) { | |
1996 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
1997 | hwmsk &= ~Y2_IS_PCI_EXP; | |
1998 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
1999 | } | |
2000 | } | |
2001 | ||
2002 | if (status & Y2_HWE_L1_MASK) | |
2003 | sky2_hw_error(hw, 0, status); | |
2004 | status >>= 8; | |
2005 | if (status & Y2_HWE_L1_MASK) | |
2006 | sky2_hw_error(hw, 1, status); | |
2007 | } | |
2008 | ||
2009 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2010 | { | |
2011 | struct net_device *dev = hw->dev[port]; | |
2012 | struct sky2_port *sky2 = netdev_priv(dev); | |
2013 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2014 | ||
2015 | if (netif_msg_intr(sky2)) | |
2016 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
2017 | dev->name, status); | |
2018 | ||
2019 | if (status & GM_IS_RX_FF_OR) { | |
2020 | ++sky2->net_stats.rx_fifo_errors; | |
2021 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
2022 | } | |
2023 | ||
2024 | if (status & GM_IS_TX_FF_UR) { | |
2025 | ++sky2->net_stats.tx_fifo_errors; | |
2026 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
2027 | } | |
cd28ab6a SH |
2028 | } |
2029 | ||
2030 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
2031 | { | |
2032 | struct net_device *dev = hw->dev[port]; | |
2033 | struct sky2_port *sky2 = netdev_priv(dev); | |
2034 | ||
2035 | hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2); | |
2036 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
91c86df5 | 2037 | schedule_work(&sky2->phy_task); |
cd28ab6a SH |
2038 | } |
2039 | ||
2040 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
2041 | { | |
2042 | struct sky2_hw *hw = dev_id; | |
bea86103 | 2043 | struct net_device *dev0 = hw->dev[0]; |
cd28ab6a SH |
2044 | u32 status; |
2045 | ||
2046 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
793b883e | 2047 | if (status == 0 || status == ~0) |
cd28ab6a SH |
2048 | return IRQ_NONE; |
2049 | ||
2050 | if (status & Y2_IS_HW_ERR) | |
2051 | sky2_hw_intr(hw); | |
2052 | ||
793b883e | 2053 | /* Do NAPI for Rx and Tx status */ |
bea86103 | 2054 | if (status & Y2_IS_STAT_BMU) { |
cd28ab6a SH |
2055 | hw->intr_mask &= ~Y2_IS_STAT_BMU; |
2056 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
bea86103 | 2057 | |
0a122576 | 2058 | if (likely(__netif_rx_schedule_prep(dev0))) { |
2059 | prefetch(&hw->st_le[hw->st_idx]); | |
bea86103 | 2060 | __netif_rx_schedule(dev0); |
0a122576 | 2061 | } |
cd28ab6a SH |
2062 | } |
2063 | ||
793b883e | 2064 | if (status & Y2_IS_IRQ_PHY1) |
cd28ab6a SH |
2065 | sky2_phy_intr(hw, 0); |
2066 | ||
2067 | if (status & Y2_IS_IRQ_PHY2) | |
2068 | sky2_phy_intr(hw, 1); | |
2069 | ||
2070 | if (status & Y2_IS_IRQ_MAC1) | |
2071 | sky2_mac_intr(hw, 0); | |
2072 | ||
2073 | if (status & Y2_IS_IRQ_MAC2) | |
2074 | sky2_mac_intr(hw, 1); | |
2075 | ||
cd28ab6a | 2076 | sky2_write32(hw, B0_Y2_SP_ICR, 2); |
793b883e SH |
2077 | |
2078 | sky2_read32(hw, B0_IMSK); | |
2079 | ||
cd28ab6a SH |
2080 | return IRQ_HANDLED; |
2081 | } | |
2082 | ||
2083 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2084 | static void sky2_netpoll(struct net_device *dev) | |
2085 | { | |
2086 | struct sky2_port *sky2 = netdev_priv(dev); | |
2087 | ||
793b883e | 2088 | sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); |
cd28ab6a SH |
2089 | } |
2090 | #endif | |
2091 | ||
2092 | /* Chip internal frequency for clock calculations */ | |
fb17358f | 2093 | static inline u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2094 | { |
793b883e | 2095 | switch (hw->chip_id) { |
cd28ab6a | 2096 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2097 | case CHIP_ID_YUKON_EC_U: |
fb17358f | 2098 | return 125; /* 125 Mhz */ |
cd28ab6a | 2099 | case CHIP_ID_YUKON_FE: |
fb17358f | 2100 | return 100; /* 100 Mhz */ |
793b883e | 2101 | default: /* YUKON_XL */ |
fb17358f | 2102 | return 156; /* 156 Mhz */ |
cd28ab6a SH |
2103 | } |
2104 | } | |
2105 | ||
fb17358f | 2106 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2107 | { |
fb17358f | 2108 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2109 | } |
2110 | ||
fb17358f | 2111 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2112 | { |
fb17358f | 2113 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2114 | } |
2115 | ||
fb17358f | 2116 | |
cd28ab6a SH |
2117 | static int sky2_reset(struct sky2_hw *hw) |
2118 | { | |
5afa0a9c | 2119 | u32 ctst; |
cd28ab6a SH |
2120 | u16 status; |
2121 | u8 t8, pmd_type; | |
2122 | int i; | |
2123 | ||
2124 | ctst = sky2_read32(hw, B0_CTST); | |
2125 | ||
2126 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2127 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); | |
2128 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
2129 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2130 | pci_name(hw->pdev), hw->chip_id); | |
2131 | return -EOPNOTSUPP; | |
2132 | } | |
2133 | ||
793b883e SH |
2134 | /* ring for status responses */ |
2135 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
2136 | &hw->st_dma); | |
2137 | if (!hw->st_le) | |
2138 | return -ENOMEM; | |
2139 | ||
cd28ab6a SH |
2140 | /* disable ASF */ |
2141 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
2142 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2143 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
2144 | } | |
2145 | ||
2146 | /* do a SW reset */ | |
2147 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2148 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2149 | ||
2150 | /* clear PCI errors, if any */ | |
793b883e | 2151 | pci_read_config_word(hw->pdev, PCI_STATUS, &status); |
cd28ab6a | 2152 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
793b883e SH |
2153 | pci_write_config_word(hw->pdev, PCI_STATUS, |
2154 | status | PCI_STATUS_ERROR_BITS); | |
cd28ab6a SH |
2155 | |
2156 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2157 | ||
2158 | /* clear any PEX errors */ | |
2159 | if (is_pciex(hw)) { | |
793b883e SH |
2160 | u16 lstat; |
2161 | pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT, | |
2162 | 0xffffffffUL); | |
2163 | pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat); | |
cd28ab6a SH |
2164 | } |
2165 | ||
2166 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
2167 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
2168 | ||
2169 | hw->ports = 1; | |
2170 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2171 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2172 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2173 | ++hw->ports; | |
2174 | } | |
2175 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; | |
2176 | ||
5afa0a9c | 2177 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
2178 | |
2179 | for (i = 0; i < hw->ports; i++) { | |
2180 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2181 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
2182 | } | |
2183 | ||
2184 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2185 | ||
793b883e SH |
2186 | /* Clear I2C IRQ noise */ |
2187 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2188 | |
2189 | /* turn off hardware timer (unused) */ | |
2190 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2191 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2192 | |
cd28ab6a SH |
2193 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2194 | ||
69634ee7 SH |
2195 | /* Turn off descriptor polling */ |
2196 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
2197 | |
2198 | /* Turn off receive timestamp */ | |
2199 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2200 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2201 | |
2202 | /* enable the Tx Arbiters */ | |
2203 | for (i = 0; i < hw->ports; i++) | |
2204 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2205 | ||
2206 | /* Initialize ram interface */ | |
2207 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2208 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2209 | |
2210 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2211 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2212 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2213 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2214 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2215 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2216 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2217 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2218 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2219 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2220 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2221 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2222 | } | |
2223 | ||
cd28ab6a SH |
2224 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); |
2225 | ||
cd28ab6a SH |
2226 | for (i = 0; i < hw->ports; i++) |
2227 | sky2_phy_reset(hw, i); | |
cd28ab6a | 2228 | |
cd28ab6a SH |
2229 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2230 | hw->st_idx = 0; | |
2231 | ||
2232 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2233 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2234 | ||
2235 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2236 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2237 | |
2238 | /* Set the list last index */ | |
793b883e | 2239 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2240 | |
793b883e | 2241 | /* These status setup values are copied from SysKonnect's driver */ |
cd28ab6a SH |
2242 | if (is_ec_a1(hw)) { |
2243 | /* WA for dev. #4.3 */ | |
793b883e | 2244 | sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */ |
cd28ab6a SH |
2245 | |
2246 | /* set Status-FIFO watermark */ | |
2247 | sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */ | |
2248 | ||
2249 | /* set Status-FIFO ISR watermark */ | |
793b883e | 2250 | sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */ |
69634ee7 | 2251 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000)); |
cd28ab6a | 2252 | } else { |
69634ee7 SH |
2253 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
2254 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a SH |
2255 | |
2256 | /* set Status-FIFO ISR watermark */ | |
2257 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
69634ee7 SH |
2258 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); |
2259 | else | |
2260 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 2261 | |
69634ee7 SH |
2262 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
2263 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
2264 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); | |
cd28ab6a SH |
2265 | } |
2266 | ||
793b883e | 2267 | /* enable status unit */ |
cd28ab6a SH |
2268 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2269 | ||
2270 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2271 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2272 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2273 | ||
2274 | return 0; | |
2275 | } | |
2276 | ||
2277 | static inline u32 sky2_supported_modes(const struct sky2_hw *hw) | |
2278 | { | |
2279 | u32 modes; | |
2280 | if (hw->copper) { | |
793b883e SH |
2281 | modes = SUPPORTED_10baseT_Half |
2282 | | SUPPORTED_10baseT_Full | |
2283 | | SUPPORTED_100baseT_Half | |
2284 | | SUPPORTED_100baseT_Full | |
2285 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2286 | |
2287 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2288 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2289 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2290 | } else |
2291 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2292 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2293 | return modes; |
2294 | } | |
2295 | ||
793b883e | 2296 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2297 | { |
2298 | struct sky2_port *sky2 = netdev_priv(dev); | |
2299 | struct sky2_hw *hw = sky2->hw; | |
2300 | ||
2301 | ecmd->transceiver = XCVR_INTERNAL; | |
2302 | ecmd->supported = sky2_supported_modes(hw); | |
2303 | ecmd->phy_address = PHY_ADDR_MARV; | |
2304 | if (hw->copper) { | |
2305 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2306 | | SUPPORTED_10baseT_Full |
2307 | | SUPPORTED_100baseT_Half | |
2308 | | SUPPORTED_100baseT_Full | |
2309 | | SUPPORTED_1000baseT_Half | |
2310 | | SUPPORTED_1000baseT_Full | |
2311 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2312 | ecmd->port = PORT_TP; |
2313 | } else | |
2314 | ecmd->port = PORT_FIBRE; | |
2315 | ||
2316 | ecmd->advertising = sky2->advertising; | |
2317 | ecmd->autoneg = sky2->autoneg; | |
2318 | ecmd->speed = sky2->speed; | |
2319 | ecmd->duplex = sky2->duplex; | |
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2324 | { | |
2325 | struct sky2_port *sky2 = netdev_priv(dev); | |
2326 | const struct sky2_hw *hw = sky2->hw; | |
2327 | u32 supported = sky2_supported_modes(hw); | |
2328 | ||
2329 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2330 | ecmd->advertising = supported; | |
2331 | sky2->duplex = -1; | |
2332 | sky2->speed = -1; | |
2333 | } else { | |
2334 | u32 setting; | |
2335 | ||
793b883e | 2336 | switch (ecmd->speed) { |
cd28ab6a SH |
2337 | case SPEED_1000: |
2338 | if (ecmd->duplex == DUPLEX_FULL) | |
2339 | setting = SUPPORTED_1000baseT_Full; | |
2340 | else if (ecmd->duplex == DUPLEX_HALF) | |
2341 | setting = SUPPORTED_1000baseT_Half; | |
2342 | else | |
2343 | return -EINVAL; | |
2344 | break; | |
2345 | case SPEED_100: | |
2346 | if (ecmd->duplex == DUPLEX_FULL) | |
2347 | setting = SUPPORTED_100baseT_Full; | |
2348 | else if (ecmd->duplex == DUPLEX_HALF) | |
2349 | setting = SUPPORTED_100baseT_Half; | |
2350 | else | |
2351 | return -EINVAL; | |
2352 | break; | |
2353 | ||
2354 | case SPEED_10: | |
2355 | if (ecmd->duplex == DUPLEX_FULL) | |
2356 | setting = SUPPORTED_10baseT_Full; | |
2357 | else if (ecmd->duplex == DUPLEX_HALF) | |
2358 | setting = SUPPORTED_10baseT_Half; | |
2359 | else | |
2360 | return -EINVAL; | |
2361 | break; | |
2362 | default: | |
2363 | return -EINVAL; | |
2364 | } | |
2365 | ||
2366 | if ((setting & supported) == 0) | |
2367 | return -EINVAL; | |
2368 | ||
2369 | sky2->speed = ecmd->speed; | |
2370 | sky2->duplex = ecmd->duplex; | |
2371 | } | |
2372 | ||
2373 | sky2->autoneg = ecmd->autoneg; | |
2374 | sky2->advertising = ecmd->advertising; | |
2375 | ||
1b537565 SH |
2376 | if (netif_running(dev)) |
2377 | sky2_phy_reinit(sky2); | |
cd28ab6a SH |
2378 | |
2379 | return 0; | |
2380 | } | |
2381 | ||
2382 | static void sky2_get_drvinfo(struct net_device *dev, | |
2383 | struct ethtool_drvinfo *info) | |
2384 | { | |
2385 | struct sky2_port *sky2 = netdev_priv(dev); | |
2386 | ||
2387 | strcpy(info->driver, DRV_NAME); | |
2388 | strcpy(info->version, DRV_VERSION); | |
2389 | strcpy(info->fw_version, "N/A"); | |
2390 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2391 | } | |
2392 | ||
2393 | static const struct sky2_stat { | |
793b883e SH |
2394 | char name[ETH_GSTRING_LEN]; |
2395 | u16 offset; | |
cd28ab6a SH |
2396 | } sky2_stats[] = { |
2397 | { "tx_bytes", GM_TXO_OK_HI }, | |
2398 | { "rx_bytes", GM_RXO_OK_HI }, | |
2399 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2400 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2401 | { "tx_multicast", GM_TXF_MC_OK }, | |
2402 | { "rx_multicast", GM_RXF_MC_OK }, | |
2403 | { "tx_unicast", GM_TXF_UC_OK }, | |
2404 | { "rx_unicast", GM_RXF_UC_OK }, | |
2405 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2406 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
2407 | { "collisions", GM_TXF_SNG_COL }, | |
2408 | { "late_collision",GM_TXF_LAT_COL }, | |
2409 | { "aborted", GM_TXF_ABO_COL }, | |
2410 | { "multi_collisions", GM_TXF_MUL_COL }, | |
2411 | { "fifo_underrun", GM_TXE_FIFO_UR }, | |
2412 | { "fifo_overflow", GM_RXE_FIFO_OV }, | |
2413 | { "rx_toolong", GM_RXF_LNG_ERR }, | |
2414 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
2415 | { "rx_runt", GM_RXE_FRAG }, | |
2416 | { "rx_too_long", GM_RXF_LNG_ERR }, | |
2417 | { "rx_fcs_error", GM_RXF_FCS_ERR }, | |
2418 | }; | |
2419 | ||
cd28ab6a SH |
2420 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2421 | { | |
2422 | struct sky2_port *sky2 = netdev_priv(dev); | |
2423 | ||
2424 | return sky2->rx_csum; | |
2425 | } | |
2426 | ||
2427 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2428 | { | |
2429 | struct sky2_port *sky2 = netdev_priv(dev); | |
2430 | ||
2431 | sky2->rx_csum = data; | |
793b883e | 2432 | |
cd28ab6a SH |
2433 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2434 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2435 | ||
2436 | return 0; | |
2437 | } | |
2438 | ||
2439 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2440 | { | |
2441 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2442 | return sky2->msg_enable; | |
2443 | } | |
2444 | ||
9a7ae0a9 SH |
2445 | static int sky2_nway_reset(struct net_device *dev) |
2446 | { | |
2447 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 SH |
2448 | |
2449 | if (sky2->autoneg != AUTONEG_ENABLE) | |
2450 | return -EINVAL; | |
2451 | ||
1b537565 | 2452 | sky2_phy_reinit(sky2); |
9a7ae0a9 SH |
2453 | |
2454 | return 0; | |
2455 | } | |
2456 | ||
793b883e | 2457 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2458 | { |
2459 | struct sky2_hw *hw = sky2->hw; | |
2460 | unsigned port = sky2->port; | |
2461 | int i; | |
2462 | ||
2463 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2464 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2465 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2466 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2467 | |
793b883e | 2468 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2469 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2470 | } | |
2471 | ||
cd28ab6a SH |
2472 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2473 | { | |
2474 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2475 | sky2->msg_enable = value; | |
2476 | } | |
2477 | ||
2478 | static int sky2_get_stats_count(struct net_device *dev) | |
2479 | { | |
2480 | return ARRAY_SIZE(sky2_stats); | |
2481 | } | |
2482 | ||
2483 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2484 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2485 | { |
2486 | struct sky2_port *sky2 = netdev_priv(dev); | |
2487 | ||
793b883e | 2488 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2489 | } |
2490 | ||
793b883e | 2491 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2492 | { |
2493 | int i; | |
2494 | ||
2495 | switch (stringset) { | |
2496 | case ETH_SS_STATS: | |
2497 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2498 | memcpy(data + i * ETH_GSTRING_LEN, | |
2499 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2500 | break; | |
2501 | } | |
2502 | } | |
2503 | ||
2504 | /* Use hardware MIB variables for critical path statistics and | |
2505 | * transmit feedback not reported at interrupt. | |
2506 | * Other errors are accounted for in interrupt handler. | |
2507 | */ | |
2508 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2509 | { | |
2510 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2511 | u64 data[13]; |
cd28ab6a | 2512 | |
793b883e | 2513 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2514 | |
2515 | sky2->net_stats.tx_bytes = data[0]; | |
2516 | sky2->net_stats.rx_bytes = data[1]; | |
2517 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2518 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
2519 | sky2->net_stats.multicast = data[5] + data[7]; | |
2520 | sky2->net_stats.collisions = data[10]; | |
2521 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2522 | ||
2523 | return &sky2->net_stats; | |
2524 | } | |
2525 | ||
2526 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2527 | { | |
2528 | struct sky2_port *sky2 = netdev_priv(dev); | |
2529 | struct sockaddr *addr = p; | |
cd28ab6a SH |
2530 | |
2531 | if (!is_valid_ether_addr(addr->sa_data)) | |
2532 | return -EADDRNOTAVAIL; | |
2533 | ||
cd28ab6a | 2534 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
793b883e | 2535 | memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8, |
cd28ab6a | 2536 | dev->dev_addr, ETH_ALEN); |
793b883e | 2537 | memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8, |
cd28ab6a | 2538 | dev->dev_addr, ETH_ALEN); |
1b537565 SH |
2539 | |
2540 | if (netif_running(dev)) | |
2541 | sky2_phy_reinit(sky2); | |
2542 | ||
2543 | return 0; | |
cd28ab6a SH |
2544 | } |
2545 | ||
2546 | static void sky2_set_multicast(struct net_device *dev) | |
2547 | { | |
2548 | struct sky2_port *sky2 = netdev_priv(dev); | |
2549 | struct sky2_hw *hw = sky2->hw; | |
2550 | unsigned port = sky2->port; | |
2551 | struct dev_mc_list *list = dev->mc_list; | |
2552 | u16 reg; | |
2553 | u8 filter[8]; | |
2554 | ||
2555 | memset(filter, 0, sizeof(filter)); | |
2556 | ||
2557 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2558 | reg |= GM_RXCR_UCF_ENA; | |
2559 | ||
d571b694 | 2560 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 2561 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2562 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2563 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2564 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2565 | reg &= ~GM_RXCR_MCF_ENA; |
2566 | else { | |
2567 | int i; | |
2568 | reg |= GM_RXCR_MCF_ENA; | |
2569 | ||
2570 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2571 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2572 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2573 | } |
2574 | } | |
2575 | ||
cd28ab6a | 2576 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2577 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2578 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2579 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2580 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2581 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2582 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2583 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2584 | |
2585 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2586 | } | |
2587 | ||
2588 | /* Can have one global because blinking is controlled by | |
2589 | * ethtool and that is always under RTNL mutex | |
2590 | */ | |
91c86df5 | 2591 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) |
cd28ab6a | 2592 | { |
793b883e SH |
2593 | u16 pg; |
2594 | ||
793b883e SH |
2595 | switch (hw->chip_id) { |
2596 | case CHIP_ID_YUKON_XL: | |
2597 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2598 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2599 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2600 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2601 | PHY_M_LEDC_INIT_CTRL(7) | | |
2602 | PHY_M_LEDC_STA1_CTRL(7) | | |
2603 | PHY_M_LEDC_STA0_CTRL(7)) | |
2604 | : 0); | |
2605 | ||
2606 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2607 | break; | |
2608 | ||
2609 | default: | |
2610 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2611 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2612 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2613 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2614 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2615 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2616 | PHY_M_LED_MO_RX(MO_LED_ON) |
2617 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2618 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2619 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2620 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2621 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2622 | ||
793b883e | 2623 | } |
cd28ab6a SH |
2624 | } |
2625 | ||
2626 | /* blink LED's for finding board */ | |
2627 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2628 | { | |
2629 | struct sky2_port *sky2 = netdev_priv(dev); | |
2630 | struct sky2_hw *hw = sky2->hw; | |
2631 | unsigned port = sky2->port; | |
793b883e | 2632 | u16 ledctrl, ledover = 0; |
cd28ab6a | 2633 | long ms; |
91c86df5 | 2634 | int interrupted; |
cd28ab6a SH |
2635 | int onoff = 1; |
2636 | ||
793b883e | 2637 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2638 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2639 | else | |
2640 | ms = data * 1000; | |
2641 | ||
2642 | /* save initial values */ | |
91c86df5 | 2643 | down(&sky2->phy_sema); |
793b883e SH |
2644 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2645 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2646 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2647 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2648 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2649 | } else { | |
2650 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2651 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2652 | } | |
cd28ab6a | 2653 | |
91c86df5 SH |
2654 | interrupted = 0; |
2655 | while (!interrupted && ms > 0) { | |
cd28ab6a SH |
2656 | sky2_led(hw, port, onoff); |
2657 | onoff = !onoff; | |
2658 | ||
91c86df5 SH |
2659 | up(&sky2->phy_sema); |
2660 | interrupted = msleep_interruptible(250); | |
2661 | down(&sky2->phy_sema); | |
2662 | ||
cd28ab6a SH |
2663 | ms -= 250; |
2664 | } | |
2665 | ||
2666 | /* resume regularly scheduled programming */ | |
793b883e SH |
2667 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2668 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2669 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2670 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2671 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2672 | } else { | |
2673 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2674 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2675 | } | |
91c86df5 | 2676 | up(&sky2->phy_sema); |
cd28ab6a SH |
2677 | |
2678 | return 0; | |
2679 | } | |
2680 | ||
2681 | static void sky2_get_pauseparam(struct net_device *dev, | |
2682 | struct ethtool_pauseparam *ecmd) | |
2683 | { | |
2684 | struct sky2_port *sky2 = netdev_priv(dev); | |
2685 | ||
2686 | ecmd->tx_pause = sky2->tx_pause; | |
2687 | ecmd->rx_pause = sky2->rx_pause; | |
2688 | ecmd->autoneg = sky2->autoneg; | |
2689 | } | |
2690 | ||
2691 | static int sky2_set_pauseparam(struct net_device *dev, | |
2692 | struct ethtool_pauseparam *ecmd) | |
2693 | { | |
2694 | struct sky2_port *sky2 = netdev_priv(dev); | |
2695 | int err = 0; | |
2696 | ||
2697 | sky2->autoneg = ecmd->autoneg; | |
2698 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2699 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2700 | ||
1b537565 | 2701 | sky2_phy_reinit(sky2); |
cd28ab6a SH |
2702 | |
2703 | return err; | |
2704 | } | |
2705 | ||
2706 | #ifdef CONFIG_PM | |
2707 | static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2708 | { | |
2709 | struct sky2_port *sky2 = netdev_priv(dev); | |
2710 | ||
2711 | wol->supported = WAKE_MAGIC; | |
2712 | wol->wolopts = sky2->wol ? WAKE_MAGIC : 0; | |
2713 | } | |
2714 | ||
2715 | static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2716 | { | |
2717 | struct sky2_port *sky2 = netdev_priv(dev); | |
2718 | struct sky2_hw *hw = sky2->hw; | |
2719 | ||
2720 | if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) | |
2721 | return -EOPNOTSUPP; | |
2722 | ||
2723 | sky2->wol = wol->wolopts == WAKE_MAGIC; | |
2724 | ||
2725 | if (sky2->wol) { | |
2726 | memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN); | |
2727 | ||
2728 | sky2_write16(hw, WOL_CTRL_STAT, | |
2729 | WOL_CTL_ENA_PME_ON_MAGIC_PKT | | |
2730 | WOL_CTL_ENA_MAGIC_PKT_UNIT); | |
2731 | } else | |
2732 | sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT); | |
2733 | ||
2734 | return 0; | |
2735 | } | |
2736 | #endif | |
2737 | ||
fb17358f SH |
2738 | static int sky2_get_coalesce(struct net_device *dev, |
2739 | struct ethtool_coalesce *ecmd) | |
2740 | { | |
2741 | struct sky2_port *sky2 = netdev_priv(dev); | |
2742 | struct sky2_hw *hw = sky2->hw; | |
2743 | ||
2744 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
2745 | ecmd->tx_coalesce_usecs = 0; | |
2746 | else { | |
2747 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
2748 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2749 | } | |
2750 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
2751 | ||
2752 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
2753 | ecmd->rx_coalesce_usecs = 0; | |
2754 | else { | |
2755 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
2756 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2757 | } | |
2758 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
2759 | ||
2760 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
2761 | ecmd->rx_coalesce_usecs_irq = 0; | |
2762 | else { | |
2763 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
2764 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
2765 | } | |
2766 | ||
2767 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
2768 | ||
2769 | return 0; | |
2770 | } | |
2771 | ||
2772 | /* Note: this affect both ports */ | |
2773 | static int sky2_set_coalesce(struct net_device *dev, | |
2774 | struct ethtool_coalesce *ecmd) | |
2775 | { | |
2776 | struct sky2_port *sky2 = netdev_priv(dev); | |
2777 | struct sky2_hw *hw = sky2->hw; | |
2778 | const u32 tmin = sky2_clk2us(hw, 1); | |
2779 | const u32 tmax = 5000; | |
2780 | ||
2781 | if (ecmd->tx_coalesce_usecs != 0 && | |
2782 | (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax)) | |
2783 | return -EINVAL; | |
2784 | ||
2785 | if (ecmd->rx_coalesce_usecs != 0 && | |
2786 | (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax)) | |
2787 | return -EINVAL; | |
2788 | ||
2789 | if (ecmd->rx_coalesce_usecs_irq != 0 && | |
2790 | (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax)) | |
2791 | return -EINVAL; | |
2792 | ||
2793 | if (ecmd->tx_max_coalesced_frames > 0xffff) | |
2794 | return -EINVAL; | |
2795 | if (ecmd->rx_max_coalesced_frames > 0xff) | |
2796 | return -EINVAL; | |
2797 | if (ecmd->rx_max_coalesced_frames_irq > 0xff) | |
2798 | return -EINVAL; | |
2799 | ||
2800 | if (ecmd->tx_coalesce_usecs == 0) | |
2801 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
2802 | else { | |
2803 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2804 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
2805 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2806 | } | |
2807 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
2808 | ||
2809 | if (ecmd->rx_coalesce_usecs == 0) | |
2810 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
2811 | else { | |
2812 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
2813 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
2814 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2815 | } | |
2816 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
2817 | ||
2818 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
2819 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
2820 | else { | |
2821 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2822 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); | |
2823 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2824 | } | |
2825 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
2826 | return 0; | |
2827 | } | |
2828 | ||
793b883e SH |
2829 | static void sky2_get_ringparam(struct net_device *dev, |
2830 | struct ethtool_ringparam *ering) | |
2831 | { | |
2832 | struct sky2_port *sky2 = netdev_priv(dev); | |
2833 | ||
2834 | ering->rx_max_pending = RX_MAX_PENDING; | |
2835 | ering->rx_mini_max_pending = 0; | |
2836 | ering->rx_jumbo_max_pending = 0; | |
2837 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2838 | ||
2839 | ering->rx_pending = sky2->rx_pending; | |
2840 | ering->rx_mini_pending = 0; | |
2841 | ering->rx_jumbo_pending = 0; | |
2842 | ering->tx_pending = sky2->tx_pending; | |
2843 | } | |
2844 | ||
2845 | static int sky2_set_ringparam(struct net_device *dev, | |
2846 | struct ethtool_ringparam *ering) | |
2847 | { | |
2848 | struct sky2_port *sky2 = netdev_priv(dev); | |
2849 | int err = 0; | |
2850 | ||
2851 | if (ering->rx_pending > RX_MAX_PENDING || | |
2852 | ering->rx_pending < 8 || | |
2853 | ering->tx_pending < MAX_SKB_TX_LE || | |
2854 | ering->tx_pending > TX_RING_SIZE - 1) | |
2855 | return -EINVAL; | |
2856 | ||
2857 | if (netif_running(dev)) | |
2858 | sky2_down(dev); | |
2859 | ||
2860 | sky2->rx_pending = ering->rx_pending; | |
2861 | sky2->tx_pending = ering->tx_pending; | |
2862 | ||
1b537565 | 2863 | if (netif_running(dev)) { |
793b883e | 2864 | err = sky2_up(dev); |
1b537565 SH |
2865 | if (err) |
2866 | dev_close(dev); | |
6ed995bb SH |
2867 | else |
2868 | sky2_set_multicast(dev); | |
1b537565 | 2869 | } |
793b883e SH |
2870 | |
2871 | return err; | |
2872 | } | |
2873 | ||
793b883e SH |
2874 | static int sky2_get_regs_len(struct net_device *dev) |
2875 | { | |
6e4cbb34 | 2876 | return 0x4000; |
793b883e SH |
2877 | } |
2878 | ||
2879 | /* | |
2880 | * Returns copy of control register region | |
6e4cbb34 | 2881 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
2882 | */ |
2883 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2884 | void *p) | |
2885 | { | |
2886 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2887 | const void __iomem *io = sky2->hw->regs; |
793b883e | 2888 | |
6e4cbb34 | 2889 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 2890 | regs->version = 1; |
6e4cbb34 | 2891 | memset(p, 0, regs->len); |
793b883e | 2892 | |
6e4cbb34 SH |
2893 | memcpy_fromio(p, io, B3_RAM_ADDR); |
2894 | ||
2895 | memcpy_fromio(p + B3_RI_WTO_R1, | |
2896 | io + B3_RI_WTO_R1, | |
2897 | regs->len - B3_RI_WTO_R1); | |
793b883e | 2898 | } |
cd28ab6a SH |
2899 | |
2900 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
2901 | .get_settings = sky2_get_settings, |
2902 | .set_settings = sky2_set_settings, | |
2903 | .get_drvinfo = sky2_get_drvinfo, | |
2904 | .get_msglevel = sky2_get_msglevel, | |
2905 | .set_msglevel = sky2_set_msglevel, | |
9a7ae0a9 | 2906 | .nway_reset = sky2_nway_reset, |
793b883e SH |
2907 | .get_regs_len = sky2_get_regs_len, |
2908 | .get_regs = sky2_get_regs, | |
2909 | .get_link = ethtool_op_get_link, | |
2910 | .get_sg = ethtool_op_get_sg, | |
2911 | .set_sg = ethtool_op_set_sg, | |
2912 | .get_tx_csum = ethtool_op_get_tx_csum, | |
2913 | .set_tx_csum = ethtool_op_set_tx_csum, | |
2914 | .get_tso = ethtool_op_get_tso, | |
2915 | .set_tso = ethtool_op_set_tso, | |
2916 | .get_rx_csum = sky2_get_rx_csum, | |
2917 | .set_rx_csum = sky2_set_rx_csum, | |
2918 | .get_strings = sky2_get_strings, | |
fb17358f SH |
2919 | .get_coalesce = sky2_get_coalesce, |
2920 | .set_coalesce = sky2_set_coalesce, | |
793b883e SH |
2921 | .get_ringparam = sky2_get_ringparam, |
2922 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
2923 | .get_pauseparam = sky2_get_pauseparam, |
2924 | .set_pauseparam = sky2_set_pauseparam, | |
2925 | #ifdef CONFIG_PM | |
793b883e SH |
2926 | .get_wol = sky2_get_wol, |
2927 | .set_wol = sky2_set_wol, | |
cd28ab6a | 2928 | #endif |
793b883e | 2929 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
2930 | .get_stats_count = sky2_get_stats_count, |
2931 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2995bfb7 | 2932 | .get_perm_addr = ethtool_op_get_perm_addr, |
cd28ab6a SH |
2933 | }; |
2934 | ||
2935 | /* Initialize network device */ | |
2936 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
2937 | unsigned port, int highmem) | |
2938 | { | |
2939 | struct sky2_port *sky2; | |
2940 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
2941 | ||
2942 | if (!dev) { | |
2943 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
2944 | return NULL; | |
2945 | } | |
2946 | ||
2947 | SET_MODULE_OWNER(dev); | |
2948 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
ef743d33 | 2949 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
2950 | dev->open = sky2_up; |
2951 | dev->stop = sky2_down; | |
ef743d33 | 2952 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a SH |
2953 | dev->hard_start_xmit = sky2_xmit_frame; |
2954 | dev->get_stats = sky2_get_stats; | |
2955 | dev->set_multicast_list = sky2_set_multicast; | |
2956 | dev->set_mac_address = sky2_set_mac_address; | |
2957 | dev->change_mtu = sky2_change_mtu; | |
2958 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
2959 | dev->tx_timeout = sky2_tx_timeout; | |
2960 | dev->watchdog_timeo = TX_WATCHDOG; | |
2961 | if (port == 0) | |
2962 | dev->poll = sky2_poll; | |
2963 | dev->weight = NAPI_WEIGHT; | |
2964 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2965 | dev->poll_controller = sky2_netpoll; | |
2966 | #endif | |
cd28ab6a SH |
2967 | |
2968 | sky2 = netdev_priv(dev); | |
2969 | sky2->netdev = dev; | |
2970 | sky2->hw = hw; | |
2971 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
2972 | ||
2973 | spin_lock_init(&sky2->tx_lock); | |
2974 | /* Auto speed and flow control */ | |
2975 | sky2->autoneg = AUTONEG_ENABLE; | |
585b5601 | 2976 | sky2->tx_pause = 1; |
cd28ab6a SH |
2977 | sky2->rx_pause = 1; |
2978 | sky2->duplex = -1; | |
2979 | sky2->speed = -1; | |
2980 | sky2->advertising = sky2_supported_modes(hw); | |
75d070c5 SH |
2981 | |
2982 | /* Receive checksum disabled for Yukon XL | |
2983 | * because of observed problems with incorrect | |
2984 | * values when multiple packets are received in one interrupt | |
2985 | */ | |
2986 | sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL); | |
2987 | ||
91c86df5 SH |
2988 | INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2); |
2989 | init_MUTEX(&sky2->phy_sema); | |
793b883e SH |
2990 | sky2->tx_pending = TX_DEF_PENDING; |
2991 | sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING; | |
734d1868 | 2992 | sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); |
cd28ab6a SH |
2993 | |
2994 | hw->dev[port] = dev; | |
2995 | ||
2996 | sky2->port = port; | |
2997 | ||
5a5b1ea0 | 2998 | dev->features |= NETIF_F_LLTX; |
2999 | if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
3000 | dev->features |= NETIF_F_TSO; | |
cd28ab6a SH |
3001 | if (highmem) |
3002 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 3003 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a | 3004 | |
d1f13708 | 3005 | #ifdef SKY2_VLAN_TAG_USED |
3006 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
3007 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
3008 | dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; | |
3009 | #endif | |
3010 | ||
cd28ab6a | 3011 | /* read the mac address */ |
793b883e | 3012 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 3013 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a SH |
3014 | |
3015 | /* device is off until link detection */ | |
3016 | netif_carrier_off(dev); | |
3017 | netif_stop_queue(dev); | |
3018 | ||
3019 | return dev; | |
3020 | } | |
3021 | ||
3022 | static inline void sky2_show_addr(struct net_device *dev) | |
3023 | { | |
3024 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3025 | ||
3026 | if (netif_msg_probe(sky2)) | |
3027 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3028 | dev->name, | |
3029 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3030 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3031 | } | |
3032 | ||
3033 | static int __devinit sky2_probe(struct pci_dev *pdev, | |
3034 | const struct pci_device_id *ent) | |
3035 | { | |
793b883e | 3036 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a | 3037 | struct sky2_hw *hw; |
5afa0a9c | 3038 | int err, pm_cap, using_dac = 0; |
cd28ab6a | 3039 | |
793b883e SH |
3040 | err = pci_enable_device(pdev); |
3041 | if (err) { | |
cd28ab6a SH |
3042 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
3043 | pci_name(pdev)); | |
3044 | goto err_out; | |
3045 | } | |
3046 | ||
793b883e SH |
3047 | err = pci_request_regions(pdev, DRV_NAME); |
3048 | if (err) { | |
cd28ab6a SH |
3049 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
3050 | pci_name(pdev)); | |
793b883e | 3051 | goto err_out; |
cd28ab6a SH |
3052 | } |
3053 | ||
3054 | pci_set_master(pdev); | |
3055 | ||
5afa0a9c | 3056 | /* Find power-management capability. */ |
3057 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
3058 | if (pm_cap == 0) { | |
3059 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
3060 | "aborting.\n"); | |
3061 | err = -EIO; | |
3062 | goto err_out_free_regions; | |
3063 | } | |
3064 | ||
d1f3d4dd SH |
3065 | if (sizeof(dma_addr_t) > sizeof(u32) && |
3066 | !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { | |
3067 | using_dac = 1; | |
3068 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
3069 | if (err < 0) { | |
3070 | printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " | |
3071 | "for consistent allocations\n", pci_name(pdev)); | |
3072 | goto err_out_free_regions; | |
3073 | } | |
cd28ab6a | 3074 | |
d1f3d4dd | 3075 | } else { |
cd28ab6a SH |
3076 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
3077 | if (err) { | |
3078 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3079 | pci_name(pdev)); | |
3080 | goto err_out_free_regions; | |
3081 | } | |
3082 | } | |
d1f3d4dd | 3083 | |
cd28ab6a | 3084 | #ifdef __BIG_ENDIAN |
d571b694 | 3085 | /* byte swap descriptors in hardware */ |
cd28ab6a SH |
3086 | { |
3087 | u32 reg; | |
3088 | ||
3089 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3090 | reg |= PCI_REV_DESC; | |
3091 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3092 | } | |
3093 | #endif | |
3094 | ||
3095 | err = -ENOMEM; | |
3096 | hw = kmalloc(sizeof(*hw), GFP_KERNEL); | |
3097 | if (!hw) { | |
3098 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3099 | pci_name(pdev)); | |
3100 | goto err_out_free_regions; | |
3101 | } | |
3102 | ||
3103 | memset(hw, 0, sizeof(*hw)); | |
3104 | hw->pdev = pdev; | |
cd28ab6a SH |
3105 | |
3106 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3107 | if (!hw->regs) { | |
3108 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3109 | pci_name(pdev)); | |
3110 | goto err_out_free_hw; | |
3111 | } | |
5afa0a9c | 3112 | hw->pm_cap = pm_cap; |
cd28ab6a | 3113 | |
cd28ab6a SH |
3114 | err = sky2_reset(hw); |
3115 | if (err) | |
793b883e | 3116 | goto err_out_iounmap; |
cd28ab6a | 3117 | |
5f4f9dc1 | 3118 | printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", |
3119 | DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq, | |
92f965e8 | 3120 | yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], |
793b883e | 3121 | hw->chip_id, hw->chip_rev); |
cd28ab6a | 3122 | |
793b883e SH |
3123 | dev = sky2_init_netdev(hw, 0, using_dac); |
3124 | if (!dev) | |
cd28ab6a SH |
3125 | goto err_out_free_pci; |
3126 | ||
793b883e SH |
3127 | err = register_netdev(dev); |
3128 | if (err) { | |
cd28ab6a SH |
3129 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
3130 | pci_name(pdev)); | |
3131 | goto err_out_free_netdev; | |
3132 | } | |
3133 | ||
3134 | sky2_show_addr(dev); | |
3135 | ||
3136 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
3137 | if (register_netdev(dev1) == 0) | |
3138 | sky2_show_addr(dev1); | |
3139 | else { | |
3140 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
3141 | printk(KERN_WARNING PFX |
3142 | "register of second port failed\n"); | |
cd28ab6a SH |
3143 | hw->dev[1] = NULL; |
3144 | free_netdev(dev1); | |
3145 | } | |
3146 | } | |
3147 | ||
793b883e SH |
3148 | err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw); |
3149 | if (err) { | |
3150 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3151 | pci_name(pdev), pdev->irq); | |
3152 | goto err_out_unregister; | |
3153 | } | |
3154 | ||
3155 | hw->intr_mask = Y2_IS_BASE; | |
3156 | sky2_write32(hw, B0_IMSK, hw->intr_mask); | |
3157 | ||
3158 | pci_set_drvdata(pdev, hw); | |
3159 | ||
cd28ab6a SH |
3160 | return 0; |
3161 | ||
793b883e SH |
3162 | err_out_unregister: |
3163 | if (dev1) { | |
3164 | unregister_netdev(dev1); | |
3165 | free_netdev(dev1); | |
3166 | } | |
3167 | unregister_netdev(dev); | |
cd28ab6a SH |
3168 | err_out_free_netdev: |
3169 | free_netdev(dev); | |
cd28ab6a | 3170 | err_out_free_pci: |
793b883e | 3171 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
3172 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
3173 | err_out_iounmap: | |
3174 | iounmap(hw->regs); | |
3175 | err_out_free_hw: | |
3176 | kfree(hw); | |
3177 | err_out_free_regions: | |
3178 | pci_release_regions(pdev); | |
cd28ab6a | 3179 | pci_disable_device(pdev); |
cd28ab6a SH |
3180 | err_out: |
3181 | return err; | |
3182 | } | |
3183 | ||
3184 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
3185 | { | |
793b883e | 3186 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3187 | struct net_device *dev0, *dev1; |
3188 | ||
793b883e | 3189 | if (!hw) |
cd28ab6a SH |
3190 | return; |
3191 | ||
cd28ab6a | 3192 | dev0 = hw->dev[0]; |
793b883e SH |
3193 | dev1 = hw->dev[1]; |
3194 | if (dev1) | |
3195 | unregister_netdev(dev1); | |
cd28ab6a SH |
3196 | unregister_netdev(dev0); |
3197 | ||
793b883e | 3198 | sky2_write32(hw, B0_IMSK, 0); |
5afa0a9c | 3199 | sky2_set_power_state(hw, PCI_D3hot); |
cd28ab6a | 3200 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 3201 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 3202 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
3203 | |
3204 | free_irq(pdev->irq, hw); | |
793b883e | 3205 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
3206 | pci_release_regions(pdev); |
3207 | pci_disable_device(pdev); | |
793b883e | 3208 | |
cd28ab6a SH |
3209 | if (dev1) |
3210 | free_netdev(dev1); | |
3211 | free_netdev(dev0); | |
3212 | iounmap(hw->regs); | |
3213 | kfree(hw); | |
5afa0a9c | 3214 | |
cd28ab6a SH |
3215 | pci_set_drvdata(pdev, NULL); |
3216 | } | |
3217 | ||
3218 | #ifdef CONFIG_PM | |
3219 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
3220 | { | |
793b883e | 3221 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5afa0a9c | 3222 | int i; |
cd28ab6a SH |
3223 | |
3224 | for (i = 0; i < 2; i++) { | |
3225 | struct net_device *dev = hw->dev[i]; | |
3226 | ||
3227 | if (dev) { | |
5afa0a9c | 3228 | if (!netif_running(dev)) |
3229 | continue; | |
3230 | ||
3231 | sky2_down(dev); | |
cd28ab6a | 3232 | netif_device_detach(dev); |
cd28ab6a SH |
3233 | } |
3234 | } | |
3235 | ||
5afa0a9c | 3236 | return sky2_set_power_state(hw, pci_choose_state(pdev, state)); |
cd28ab6a SH |
3237 | } |
3238 | ||
3239 | static int sky2_resume(struct pci_dev *pdev) | |
3240 | { | |
793b883e | 3241 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3242 | int i; |
3243 | ||
cd28ab6a SH |
3244 | pci_restore_state(pdev); |
3245 | pci_enable_wake(pdev, PCI_D0, 0); | |
5afa0a9c | 3246 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
3247 | |
3248 | sky2_reset(hw); | |
3249 | ||
3250 | for (i = 0; i < 2; i++) { | |
3251 | struct net_device *dev = hw->dev[i]; | |
3252 | if (dev) { | |
5afa0a9c | 3253 | if (netif_running(dev)) { |
3254 | netif_device_attach(dev); | |
1b537565 SH |
3255 | if (sky2_up(dev)) |
3256 | dev_close(dev); | |
5afa0a9c | 3257 | } |
cd28ab6a SH |
3258 | } |
3259 | } | |
3260 | return 0; | |
3261 | } | |
3262 | #endif | |
3263 | ||
3264 | static struct pci_driver sky2_driver = { | |
793b883e SH |
3265 | .name = DRV_NAME, |
3266 | .id_table = sky2_id_table, | |
3267 | .probe = sky2_probe, | |
3268 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 3269 | #ifdef CONFIG_PM |
793b883e SH |
3270 | .suspend = sky2_suspend, |
3271 | .resume = sky2_resume, | |
cd28ab6a SH |
3272 | #endif |
3273 | }; | |
3274 | ||
3275 | static int __init sky2_init_module(void) | |
3276 | { | |
50241c4c | 3277 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
3278 | } |
3279 | ||
3280 | static void __exit sky2_cleanup_module(void) | |
3281 | { | |
3282 | pci_unregister_driver(&sky2_driver); | |
3283 | } | |
3284 | ||
3285 | module_init(sky2_init_module); | |
3286 | module_exit(sky2_cleanup_module); | |
3287 | ||
3288 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
3289 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
3290 | MODULE_LICENSE("GPL"); | |
5f4f9dc1 | 3291 | MODULE_VERSION(DRV_VERSION); |