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[PATCH] sky2: use netif_tx_lock instead of LLTX
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
e981d47b 53#define DRV_VERSION "1.7"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
13210ce5 63#define RX_LE_SIZE 512
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
22e11703 68#define RX_BUF_WRITE 16
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
cd28ab6a
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
2f4a66ad 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
cd28ab6a
SH		 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
2f4a66ad 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
cd28ab6a
SH		 132 { 0 }
133};
793b883e 134
cd28ab6a
SH		 135MODULE_DEVICE_TABLE(pci, sky2_id_table);
136
137/* Avoid conditionals by using array */
138static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
139static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 140static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 141
92f965e8
SH		 142/* This driver supports yukon2 chipset only */
143static const char *yukon2_name[] = {
144 "XL", /* 0xb3 */
145 "EC Ultra", /* 0xb4 */
146 "UNKNOWN", /* 0xb5 */
147 "EC", /* 0xb6 */
148 "FE", /* 0xb7 */
793b883e
SH		 149};
150
793b883e 151/* Access to external PHY */
ef743d33 152static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 153{
154 int i;
155
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159
160 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 161 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 162 return 0;
793b883e 163 udelay(1);
cd28ab6a 164 }
ef743d33 165
793b883e 166 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 167 return -ETIMEDOUT;
cd28ab6a
SH		 168}
169
ef743d33 170static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 171{
172 int i;
173
793b883e 174 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 175 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
176
177 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 178 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
179 *val = gma_read16(hw, port, GM_SMI_DATA);
180 return 0;
181 }
182
793b883e 183 udelay(1);
cd28ab6a
SH		 184 }
185
ef743d33 186 return -ETIMEDOUT;
187}
188
189static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
190{
191 u16 v;
192
193 if (__gm_phy_read(hw, port, reg, &v) != 0)
194 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
195 return v;
cd28ab6a
SH		 196}
197
2ccc99b7 198static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c 199{
200 u16 power_control;
5afa0a9c 201 int vaux;
5afa0a9c 202
203 pr_debug("sky2_set_power_state %d\n", state);
204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
205
56a645cc 206 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 207 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 208 (power_control & PCI_PM_CAP_PME_D3cold);
209
56a645cc 210 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 211
212 power_control |= PCI_PM_CTRL_PME_STATUS;
213 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
214
215 switch (state) {
216 case PCI_D0:
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
977bdf06 233 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb 234 u32 reg1;
235
56a645cc
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 238 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 239 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
240 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 241 }
242
5afa0a9c 243 break;
244
245 case PCI_D3hot:
246 case PCI_D3cold:
5afa0a9c 247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
248 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
249 else
250 /* enable bits are inverted */
251 sky2_write8(hw, B2_Y2_CLK_GATE,
252 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
253 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
254 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
255
256 /* switch power to VAUX */
257 if (vaux && state != PCI_D3cold)
258 sky2_write8(hw, B0_POWER_CTRL,
259 (PC_VAUX_ENA | PC_VCC_ENA |
260 PC_VAUX_ON | PC_VCC_OFF));
261 break;
262 default:
263 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c 264 }
265
56a645cc 266 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 267 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c 268}
269
d3bcfbeb 270static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 271{
272 u16 reg;
273
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 278
cd28ab6a
SH		 279 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
280 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
283
284 reg = gma_read16(hw, port, GM_RX_CTRL);
285 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
286 gma_write16(hw, port, GM_RX_CTRL, reg);
287}
288
289static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
290{
291 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 292 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 293
ed6d32c7 294 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 295 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 296 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
297
298 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 299 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 300 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
301
302 if (hw->chip_id == CHIP_ID_YUKON_EC)
303 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
304 else
305 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
306
307 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
308 }
309
310 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 311 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 312 if (hw->chip_id == CHIP_ID_YUKON_FE) {
313 /* enable automatic crossover */
314 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
315 } else {
316 /* disable energy detect */
317 ctrl &= ~PHY_M_PC_EN_DET_MSK;
318
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
321
322 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 323 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 324 ctrl &= ~PHY_M_PC_DSC_MSK;
325 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
326 }
327 }
cd28ab6a
SH		 328 } else {
329 /* workaround for deviation #4.88 (CRC errors) */
330 /* disable Automatic Crossover */
331
332 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 333 }
cd28ab6a 334
b89165f2
SH		 335 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
336
337 /* special setup for PHY 88E1112 Fiber */
338 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
339 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 340
b89165f2
SH		 341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 349 /* select page 1 to access Fiber registers */
350 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 351
352 /* for SFP-module set SIGDET polarity to low */
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl |= PHY_M_FIB_SIGD_POL;
355 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 356 }
b89165f2
SH		 357
358 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 359 }
360
361 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
362 if (sky2->autoneg == AUTONEG_DISABLE)
363 ctrl &= ~PHY_CT_ANE;
364 else
365 ctrl |= PHY_CT_ANE;
366
367 ctrl |= PHY_CT_RESET;
368 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
369
370 ctrl = 0;
371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
2eaba1a2 373 reg = 0;
cd28ab6a
SH		 374
375 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 376 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
b89165f2
SH		 389 } else { /* special defines for FIBER (88E1040S only) */
390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 adv |= PHY_M_AN_1000X_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 adv |= PHY_M_AN_1000X_AHD;
394 }
cd28ab6a
SH		 395
396 /* Set Flow-control capabilities */
397 if (sky2->tx_pause && sky2->rx_pause)
793b883e 398 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 399 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 400 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 401 else if (!sky2->rx_pause && sky2->tx_pause)
402 adv |= PHY_AN_PAUSE_ASYM; /* local */
403
404 /* Restart Auto-negotiation */
405 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
406 } else {
407 /* forced speed/duplex settings */
408 ct1000 = PHY_M_1000C_MSE;
409
2eaba1a2
SH		 410 /* Disable auto update for duplex flow control and speed */
411 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 412
413 switch (sky2->speed) {
414 case SPEED_1000:
415 ctrl |= PHY_CT_SP1000;
2eaba1a2 416 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 417 break;
418 case SPEED_100:
419 ctrl |= PHY_CT_SP100;
2eaba1a2 420 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 421 break;
422 }
423
2eaba1a2
SH		 424 if (sky2->duplex == DUPLEX_FULL) {
425 reg |= GM_GPCR_DUP_FULL;
426 ctrl |= PHY_CT_DUP_MD;
427 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
428 /* Turn off flow control for 10/100mbps */
429 sky2->rx_pause = 0;
430 sky2->tx_pause = 0;
431 }
432
433 if (!sky2->rx_pause)
434 reg |= GM_GPCR_FC_RX_DIS;
435
436 if (!sky2->tx_pause)
437 reg |= GM_GPCR_FC_TX_DIS;
438
439 /* Forward pause packets to GMAC? */
440 if (sky2->tx_pause || sky2->rx_pause)
441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
442 else
443 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
444
cd28ab6a
SH		 445 ctrl |= PHY_CT_RESET;
446 }
447
2eaba1a2
SH		 448 gma_write16(hw, port, GM_GP_CTRL, reg);
449
cd28ab6a
SH		 450 if (hw->chip_id != CHIP_ID_YUKON_FE)
451 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
452
453 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
454 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
455
456 /* Setup Phy LED's */
457 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
458 ledover = 0;
459
460 switch (hw->chip_id) {
461 case CHIP_ID_YUKON_FE:
462 /* on 88E3082 these bits are at 11..9 (shifted left) */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
464
465 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
466
467 /* delete ACT LED control bits */
468 ctrl &= ~PHY_M_FELP_LED1_MSK;
469 /* change ACT LED control to blink mode */
470 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
471 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
472 break;
473
474 case CHIP_ID_YUKON_XL:
793b883e 475 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 476
477 /* select page 3 to access LED control register */
478 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
479
480 /* set LED Function Control register */
ed6d32c7
SH		 481 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
482 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
483 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
484 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
485 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 486
487 /* set Polarity Control register */
488 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 489 (PHY_M_POLC_LS1_P_MIX(4) |
490 PHY_M_POLC_IS0_P_MIX(4) |
491 PHY_M_POLC_LOS_CTRL(2) |
492 PHY_M_POLC_INIT_CTRL(2) |
493 PHY_M_POLC_STA1_CTRL(2) |
494 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 495
496 /* restore page register */
793b883e 497 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 498 break;
ed6d32c7
SH		 499 case CHIP_ID_YUKON_EC_U:
500 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
501
502 /* select page 3 to access LED control register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
504
505 /* set LED Function Control register */
506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
507 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
508 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
509 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
510 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
511
512 /* set Blink Rate in LED Timer Control Register */
513 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
514 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
515 /* restore page register */
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
517 break;
cd28ab6a
SH		 518
519 default:
520 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
521 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
522 /* turn off the Rx LED (LED_RX) */
523 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
524 }
525
ed6d32c7 526 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 527 /* apply fixes in PHY AFE */
ed6d32c7
SH		 528 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
530
977bdf06 531 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 532 gm_phy_write(hw, port, 0x18, 0xaa99);
533 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 534
977bdf06 535 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 536 gm_phy_write(hw, port, 0x18, 0xa204);
537 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 538
539 /* set page register to 0 */
ed6d32c7 540 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 541 } else {
542 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 543
977bdf06
SH		 544 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
545 /* turn on 100 Mbps LED (LED_LINK100) */
546 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
547 }
cd28ab6a 548
977bdf06
SH		 549 if (ledover)
550 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
551
552 }
2eaba1a2 553
d571b694 554 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 555 if (sky2->autoneg == AUTONEG_ENABLE)
556 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
557 else
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
559}
560
d3bcfbeb 561static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
562{
563 u32 reg1;
564 static const u32 phy_power[]
565 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
566
567 /* looks like this XL is back asswards .. */
568 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
569 onoff = !onoff;
570
571 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
572
573 if (onoff)
574 /* Turn off phy power saving */
575 reg1 &= ~phy_power[port];
576 else
577 reg1 |= phy_power[port];
578
579 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 580 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 581 udelay(100);
582}
583
1b537565
SH		 584/* Force a renegotiation */
585static void sky2_phy_reinit(struct sky2_port *sky2)
586{
e07b1aa8 587 spin_lock_bh(&sky2->phy_lock);
1b537565 588 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 589 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 590}
591
cd28ab6a
SH		 592static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
593{
594 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
595 u16 reg;
596 int i;
597 const u8 *addr = hw->dev[port]->dev_addr;
598
42eeea01 599 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
600 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 601
602 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
603
793b883e 604 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 605 /* WA DEV_472 -- looks like crossed wires on port 2 */
606 /* clear GMAC 1 Control reset */
607 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
608 do {
609 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
610 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
611 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
612 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
613 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
614 }
615
793b883e 616 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 617
2eaba1a2
SH		 618 /* Enable Transmit FIFO Underrun */
619 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
620
e07b1aa8 621 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 622 sky2_phy_init(hw, port);
e07b1aa8 623 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 624
625 /* MIB clear */
626 reg = gma_read16(hw, port, GM_PHY_ADDR);
627 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
628
43f2f104
SH		 629 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
630 gma_read16(hw, port, i);
cd28ab6a
SH		 631 gma_write16(hw, port, GM_PHY_ADDR, reg);
632
633 /* transmit control */
634 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
635
636 /* receive control reg: unicast + multicast + no FCS */
637 gma_write16(hw, port, GM_RX_CTRL,
793b883e 638 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 639
640 /* transmit flow control */
641 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
642
643 /* transmit parameter */
644 gma_write16(hw, port, GM_TX_PARAM,
645 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
646 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
647 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
648 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
649
650 /* serial mode register */
651 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 652 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 653
6b1a3aef 654 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 655 reg |= GM_SMOD_JUMBO_ENA;
656
657 gma_write16(hw, port, GM_SERIAL_MODE, reg);
658
cd28ab6a
SH		 659 /* virtual address for data */
660 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
661
793b883e
SH		 662 /* physical address: used for pause frames */
663 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
664
665 /* ignore counter overflows */
cd28ab6a
SH		 666 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
667 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
668 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
669
670 /* Configure Rx MAC FIFO */
671 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 672 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
673 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 674
d571b694 675 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 676 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 677
793b883e
SH		 678 /* Set threshold to 0xa (64 bytes)
679 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 680 */
681 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
682
683 /* Configure Tx MAC FIFO */
684 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
685 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 686
687 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
688 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
689 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
690 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
691 /* set Tx GMAC FIFO Almost Empty Threshold */
692 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
693 /* Disable Store & Forward mode for TX */
694 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
695 }
696 }
697
cd28ab6a
SH		 698}
699
1c28f6ba
SH		 700/* Assign Ram Buffer allocation.
701 * start and end are in units of 4k bytes
702 * ram registers are in units of 64bit words
703 */
704static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 705{
1c28f6ba 706 u32 start, end;
cd28ab6a 707
1c28f6ba
SH		 708 start = startk * 4096/8;
709 end = (endk * 4096/8) - 1;
793b883e 710
cd28ab6a
SH		 711 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
712 sky2_write32(hw, RB_ADDR(q, RB_START), start);
713 sky2_write32(hw, RB_ADDR(q, RB_END), end);
714 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
715 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
716
717 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 718 u32 space = (endk - startk) * 4096/8;
719 u32 tp = space - space/4;
793b883e 720
1c28f6ba
SH		 721 /* On receive queue's set the thresholds
722 * give receiver priority when > 3/4 full
723 * send pause when down to 2K
724 */
725 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
726 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 727
1c28f6ba
SH		 728 tp = space - 2048/8;
729 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
730 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 731 } else {
732 /* Enable store & forward on Tx queue's because
733 * Tx FIFO is only 1K on Yukon
734 */
735 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
736 }
737
738 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 739 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 740}
741
cd28ab6a 742/* Setup Bus Memory Interface */
af4ed7e6 743static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 744{
745 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
746 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
747 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 748 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 749}
750
cd28ab6a
SH		 751/* Setup prefetch unit registers. This is the interface between
752 * hardware and driver list elements
753 */
8cc048e3 754static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 755 u64 addr, u32 last)
756{
cd28ab6a
SH		 757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
759 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
761 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
762 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 763
764 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 765}
766
793b883e
SH		 767static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
768{
769 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
770
cb5d9547 771 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 772 le->ctrl = 0;
793b883e
SH		 773 return le;
774}
cd28ab6a 775
291ea614
SH		 776static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
777 struct sky2_tx_le *le)
778{
779 return sky2->tx_ring + (le - sky2->tx_le);
780}
781
290d4de5
SH		 782/* Update chip's next pointer */
783static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 784{
98232f85 785 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 786 wmb();
98232f85 787 sky2_write16(hw, q, idx);
788 sky2_read16(hw, q);
cd28ab6a
SH		 789}
790
793b883e 791
cd28ab6a
SH		 792static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
793{
794 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 795 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 796 le->ctrl = 0;
cd28ab6a
SH		 797 return le;
798}
799
a018e330 800/* Return high part of DMA address (could be 32 or 64 bit) */
801static inline u32 high32(dma_addr_t a)
802{
a036119f 803 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 804}
805
793b883e 806/* Build description to hardware about buffer */
28bd181a 807static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 808{
809 struct sky2_rx_le *le;
734d1868
SH		 810 u32 hi = high32(map);
811 u16 len = sky2->rx_bufsize;
cd28ab6a 812
793b883e 813 if (sky2->rx_addr64 != hi) {
cd28ab6a 814 le = sky2_next_rx(sky2);
793b883e 815 le->addr = cpu_to_le32(hi);
cd28ab6a 816 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 817 sky2->rx_addr64 = high32(map + len);
cd28ab6a 818 }
793b883e 819
cd28ab6a 820 le = sky2_next_rx(sky2);
734d1868
SH		 821 le->addr = cpu_to_le32((u32) map);
822 le->length = cpu_to_le16(len);
cd28ab6a
SH		 823 le->opcode = OP_PACKET | HW_OWNER;
824}
825
793b883e 826
cd28ab6a
SH		 827/* Tell chip where to start receive checksum.
828 * Actually has two checksums, but set both same to avoid possible byte
829 * order problems.
830 */
793b883e 831static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 832{
833 struct sky2_rx_le *le;
834
cd28ab6a 835 le = sky2_next_rx(sky2);
f65b138c 836 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 837 le->ctrl = 0;
838 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 839
793b883e
SH		 840 sky2_write32(sky2->hw,
841 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
842 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 843
844}
845
6b1a3aef 846/*
847 * The RX Stop command will not work for Yukon-2 if the BMU does not
848 * reach the end of packet and since we can't make sure that we have
849 * incoming data, we must reset the BMU while it is not doing a DMA
850 * transfer. Since it is possible that the RX path is still active,
851 * the RX RAM buffer will be stopped first, so any possible incoming
852 * data will not trigger a DMA. After the RAM buffer is stopped, the
853 * BMU is polled until any DMA in progress is ended and only then it
854 * will be reset.
855 */
856static void sky2_rx_stop(struct sky2_port *sky2)
857{
858 struct sky2_hw *hw = sky2->hw;
859 unsigned rxq = rxqaddr[sky2->port];
860 int i;
861
862 /* disable the RAM Buffer receive queue */
863 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
864
865 for (i = 0; i < 0xffff; i++)
866 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
867 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
868 goto stopped;
869
870 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
871 sky2->netdev->name);
872stopped:
873 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
874
875 /* reset the Rx prefetch unit */
876 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
877}
793b883e 878
d571b694 879/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 880static void sky2_rx_clean(struct sky2_port *sky2)
881{
882 unsigned i;
883
884 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 885 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 886 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 887
888 if (re->skb) {
793b883e 889 pci_unmap_single(sky2->hw->pdev,
734d1868 890 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 891 PCI_DMA_FROMDEVICE);
892 kfree_skb(re->skb);
893 re->skb = NULL;
894 }
895 }
896}
897
ef743d33 898/* Basic MII support */
899static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
900{
901 struct mii_ioctl_data *data = if_mii(ifr);
902 struct sky2_port *sky2 = netdev_priv(dev);
903 struct sky2_hw *hw = sky2->hw;
904 int err = -EOPNOTSUPP;
905
906 if (!netif_running(dev))
907 return -ENODEV; /* Phy still in reset */
908
d89e1343 909 switch (cmd) {
ef743d33 910 case SIOCGMIIPHY:
911 data->phy_id = PHY_ADDR_MARV;
912
913 /* fallthru */
914 case SIOCGMIIREG: {
915 u16 val = 0;
91c86df5 916
e07b1aa8 917 spin_lock_bh(&sky2->phy_lock);
ef743d33 918 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 919 spin_unlock_bh(&sky2->phy_lock);
91c86df5 920
ef743d33 921 data->val_out = val;
922 break;
923 }
924
925 case SIOCSMIIREG:
926 if (!capable(CAP_NET_ADMIN))
927 return -EPERM;
928
e07b1aa8 929 spin_lock_bh(&sky2->phy_lock);
ef743d33 930 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
931 data->val_in);
e07b1aa8 932 spin_unlock_bh(&sky2->phy_lock);
ef743d33 933 break;
934 }
935 return err;
936}
937
d1f13708 938#ifdef SKY2_VLAN_TAG_USED
939static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
940{
941 struct sky2_port *sky2 = netdev_priv(dev);
942 struct sky2_hw *hw = sky2->hw;
943 u16 port = sky2->port;
d1f13708 944
2bb8c262 945 netif_tx_lock_bh(dev);
d1f13708 946
947 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
948 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
949 sky2->vlgrp = grp;
950
2bb8c262 951 netif_tx_unlock_bh(dev);
d1f13708 952}
953
954static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
955{
956 struct sky2_port *sky2 = netdev_priv(dev);
957 struct sky2_hw *hw = sky2->hw;
958 u16 port = sky2->port;
d1f13708 959
2bb8c262 960 netif_tx_lock_bh(dev);
d1f13708 961
962 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
963 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
964 if (sky2->vlgrp)
965 sky2->vlgrp->vlan_devices[vid] = NULL;
966
2bb8c262 967 netif_tx_unlock_bh(dev);
d1f13708 968}
969#endif
970
82788c7a
SH		 971/*
972 * It appears the hardware has a bug in the FIFO logic that
973 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 974 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
975 * aligned except if slab debugging is enabled.
82788c7a 976 */
497d7c86 977static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
978 unsigned int length,
979 gfp_t gfp_mask)
82788c7a
SH		 980{
981 struct sk_buff *skb;
982
497d7c86 983 skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
82788c7a
SH		 984 if (likely(skb)) {
985 unsigned long p = (unsigned long) skb->data;
4a15d56f 986 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 987 }
988
989 return skb;
990}
991
cd28ab6a
SH		 992/*
993 * Allocate and setup receiver buffer pool.
994 * In case of 64 bit dma, there are 2X as many list elements
995 * available as ring entries
996 * and need to reserve one list element so we don't wrap around.
997 */
6b1a3aef 998static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 999{
6b1a3aef 1000 struct sky2_hw *hw = sky2->hw;
6b1a3aef 1001 unsigned rxq = rxqaddr[sky2->port];
1002 int i;
a1433ac4 1003 unsigned thresh;
cd28ab6a 1004
6b1a3aef 1005 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1006 sky2_qset(hw, rxq);
977bdf06
SH		 1007
1008 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1009 /* MAC Rx RAM Read is controlled by hardware */
1010 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1011 }
1012
6b1a3aef 1013 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1014
1015 rx_set_checksum(sky2);
793b883e 1016 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1017 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a 1018
497d7c86 1019 re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
1020 GFP_KERNEL);
cd28ab6a
SH		 1021 if (!re->skb)
1022 goto nomem;
1023
6b1a3aef 1024 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1025 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1026 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1027 }
1028
a1433ac4
SH		 1029
1030 /*
1031 * The receiver hangs if it receives frames larger than the
1032 * packet buffer. As a workaround, truncate oversize frames, but
1033 * the register is limited to 9 bits, so if you do frames > 2052
1034 * you better get the MTU right!
1035 */
1036 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1037 if (thresh > 0x1ff)
1038 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1039 else {
1040 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1041 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1042 }
1043
70f1be48 1044
6b1a3aef 1045 /* Tell chip about available buffers */
1046 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1047 return 0;
1048nomem:
1049 sky2_rx_clean(sky2);
1050 return -ENOMEM;
1051}
1052
1053/* Bring up network interface. */
1054static int sky2_up(struct net_device *dev)
1055{
1056 struct sky2_port *sky2 = netdev_priv(dev);
1057 struct sky2_hw *hw = sky2->hw;
1058 unsigned port = sky2->port;
e07b1aa8 1059 u32 ramsize, rxspace, imask;
ee7abb04 1060 int cap, err = -ENOMEM;
843a46f4 1061 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1062
ee7abb04
SH		 1063 /*
1064 * On dual port PCI-X card, there is an problem where status
1065 * can be received out of order due to split transactions
843a46f4 1066 */
ee7abb04
SH		 1067 if (otherdev && netif_running(otherdev) &&
1068 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1069 struct sky2_port *osky2 = netdev_priv(otherdev);
1070 u16 cmd;
1071
1072 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1073 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1074 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1075
1076 sky2->rx_csum = 0;
1077 osky2->rx_csum = 0;
1078 }
843a46f4 1079
cd28ab6a
SH		 1080 if (netif_msg_ifup(sky2))
1081 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1082
1083 /* must be power of 2 */
1084 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1085 TX_RING_SIZE *
1086 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1087 &sky2->tx_le_map);
1088 if (!sky2->tx_le)
1089 goto err_out;
1090
6cdbbdf3 1091 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1092 GFP_KERNEL);
1093 if (!sky2->tx_ring)
1094 goto err_out;
1095 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1096
1097 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1098 &sky2->rx_le_map);
1099 if (!sky2->rx_le)
1100 goto err_out;
1101 memset(sky2->rx_le, 0, RX_LE_BYTES);
1102
291ea614 1103 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1104 GFP_KERNEL);
1105 if (!sky2->rx_ring)
1106 goto err_out;
1107
d3bcfbeb 1108 sky2_phy_power(hw, port, 1);
1109
cd28ab6a
SH		 1110 sky2_mac_init(hw, port);
1111
1c28f6ba
SH		 1112 /* Determine available ram buffer space (in 4K blocks).
1113 * Note: not sure about the FE setting below yet
1114 */
1115 if (hw->chip_id == CHIP_ID_YUKON_FE)
1116 ramsize = 4;
1117 else
1118 ramsize = sky2_read8(hw, B2_E_0);
1119
1120 /* Give transmitter one third (rounded up) */
1121 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1122
cd28ab6a 1123 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1124 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1125
793b883e
SH		 1126 /* Make sure SyncQ is disabled */
1127 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1128 RB_RST_SET);
1129
af4ed7e6 1130 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1131
977bdf06 1132 /* Set almost empty threshold */
c2716fb4
SH		 1133 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1134 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1135 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1136
6b1a3aef 1137 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1138 TX_RING_SIZE - 1);
cd28ab6a 1139
6b1a3aef 1140 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1141 if (err)
1142 goto err_out;
1143
cd28ab6a 1144 /* Enable interrupts from phy/mac for port */
e07b1aa8 1145 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1146 imask |= portirq_msk[port];
e07b1aa8
SH		 1147 sky2_write32(hw, B0_IMSK, imask);
1148
cd28ab6a
SH		 1149 return 0;
1150
1151err_out:
1b537565 1152 if (sky2->rx_le) {
cd28ab6a
SH		 1153 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1154 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1155 sky2->rx_le = NULL;
1156 }
1157 if (sky2->tx_le) {
cd28ab6a
SH		 1158 pci_free_consistent(hw->pdev,
1159 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1160 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1161 sky2->tx_le = NULL;
1162 }
1163 kfree(sky2->tx_ring);
1164 kfree(sky2->rx_ring);
cd28ab6a 1165
1b537565
SH		 1166 sky2->tx_ring = NULL;
1167 sky2->rx_ring = NULL;
cd28ab6a
SH		 1168 return err;
1169}
1170
793b883e
SH		 1171/* Modular subtraction in ring */
1172static inline int tx_dist(unsigned tail, unsigned head)
1173{
cb5d9547 1174 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1175}
cd28ab6a 1176
793b883e
SH		 1177/* Number of list elements available for next tx */
1178static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1179{
793b883e 1180 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1181}
1182
793b883e 1183/* Estimate of number of transmit list elements required */
28bd181a 1184static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1185{
793b883e
SH		 1186 unsigned count;
1187
1188 count = sizeof(dma_addr_t) / sizeof(u32);
1189 count += skb_shinfo(skb)->nr_frags * count;
1190
89114afd 1191 if (skb_is_gso(skb))
793b883e
SH		 1192 ++count;
1193
84fa7933 1194 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1195 ++count;
1196
1197 return count;
cd28ab6a
SH		 1198}
1199
793b883e
SH		 1200/*
1201 * Put one packet in ring for transmit.
1202 * A single packet can generate multiple list elements, and
1203 * the number of ring elements will probably be less than the number
1204 * of list elements used.
1205 */
cd28ab6a
SH		 1206static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1207{
1208 struct sky2_port *sky2 = netdev_priv(dev);
1209 struct sky2_hw *hw = sky2->hw;
d1f13708 1210 struct sky2_tx_le *le = NULL;
6cdbbdf3 1211 struct tx_ring_info *re;
cd28ab6a
SH		 1212 unsigned i, len;
1213 dma_addr_t mapping;
1214 u32 addr64;
1215 u16 mss;
1216 u8 ctrl;
1217
2bb8c262
SH		 1218 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1219 return NETDEV_TX_BUSY;
cd28ab6a 1220
793b883e 1221 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1222 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1223 dev->name, sky2->tx_prod, skb->len);
1224
cd28ab6a
SH		 1225 len = skb_headlen(skb);
1226 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1227 addr64 = high32(mapping);
793b883e 1228
a018e330 1229 /* Send high bits if changed or crosses boundary */
1230 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1231 le = get_tx_le(sky2);
f65b138c 1232 le->addr = cpu_to_le32(addr64);
793b883e 1233 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1234 sky2->tx_addr64 = high32(mapping + len);
793b883e 1235 }
cd28ab6a
SH		 1236
1237 /* Check for TCP Segmentation Offload */
7967168c 1238 mss = skb_shinfo(skb)->gso_size;
793b883e 1239 if (mss != 0) {
cd28ab6a
SH		 1240 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1241 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1242 mss += ETH_HLEN;
1243
e07560cd 1244 if (mss != sky2->tx_last_mss) {
1245 le = get_tx_le(sky2);
f65b138c 1246 le->addr = cpu_to_le32(mss);
e07560cd 1247 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1248 sky2->tx_last_mss = mss;
1249 }
cd28ab6a
SH		 1250 }
1251
cd28ab6a 1252 ctrl = 0;
d1f13708 1253#ifdef SKY2_VLAN_TAG_USED
1254 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1255 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1256 if (!le) {
1257 le = get_tx_le(sky2);
f65b138c 1258 le->addr = 0;
d1f13708 1259 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1260 } else
1261 le->opcode |= OP_VLAN;
1262 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1263 ctrl |= INS_VLAN;
1264 }
1265#endif
1266
1267 /* Handle TCP checksum offload */
84fa7933 1268 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1269 unsigned offset = skb->h.raw - skb->data;
1270 u32 tcpsum;
1271
1272 tcpsum = offset << 16; /* sum start */
1273 tcpsum |= offset + skb->csum; /* sum write */
cd28ab6a
SH		 1274
1275 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1276 if (skb->nh.iph->protocol == IPPROTO_UDP)
1277 ctrl |= UDPTCP;
1278
f65b138c
SH		 1279 if (tcpsum != sky2->tx_tcpsum) {
1280 sky2->tx_tcpsum = tcpsum;
1d179332 1281
1282 le = get_tx_le(sky2);
f65b138c 1283 le->addr = cpu_to_le32(tcpsum);
1d179332 1284 le->length = 0; /* initial checksum value */
1285 le->ctrl = 1; /* one packet */
1286 le->opcode = OP_TCPLISW | HW_OWNER;
1287 }
cd28ab6a
SH		 1288 }
1289
1290 le = get_tx_le(sky2);
f65b138c 1291 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1292 le->length = cpu_to_le16(len);
1293 le->ctrl = ctrl;
793b883e 1294 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1295
291ea614 1296 re = tx_le_re(sky2, le);
cd28ab6a 1297 re->skb = skb;
6cdbbdf3 1298 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1299 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1300
1301 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1302 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1303
1304 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1305 frag->size, PCI_DMA_TODEVICE);
a036119f 1306 addr64 = high32(mapping);
793b883e
SH		 1307 if (addr64 != sky2->tx_addr64) {
1308 le = get_tx_le(sky2);
f65b138c 1309 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1310 le->ctrl = 0;
1311 le->opcode = OP_ADDR64 | HW_OWNER;
1312 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1313 }
1314
1315 le = get_tx_le(sky2);
f65b138c 1316 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1317 le->length = cpu_to_le16(frag->size);
1318 le->ctrl = ctrl;
793b883e 1319 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1320
291ea614
SH		 1321 re = tx_le_re(sky2, le);
1322 re->skb = skb;
1323 pci_unmap_addr_set(re, mapaddr, mapping);
1324 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1325 }
6cdbbdf3 1326
cd28ab6a
SH		 1327 le->ctrl |= EOP;
1328
97bda706 1329 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1330 netif_stop_queue(dev);
b19666d9 1331
290d4de5 1332 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1333
cd28ab6a
SH		 1334 dev->trans_start = jiffies;
1335 return NETDEV_TX_OK;
1336}
1337
cd28ab6a 1338/*
793b883e
SH		 1339 * Free ring elements from starting at tx_cons until "done"
1340 *
1341 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1342 * buffers so make sure not to free skb to early.
cd28ab6a 1343 */
d11c13e7 1344static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1345{
d11c13e7 1346 struct net_device *dev = sky2->netdev;
af2a58ac 1347 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1348 unsigned idx;
cd28ab6a 1349
0e3ff6aa 1350 BUG_ON(done >= TX_RING_SIZE);
2224795d 1351
291ea614
SH		 1352 for (idx = sky2->tx_cons; idx != done;
1353 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1354 struct sky2_tx_le *le = sky2->tx_le + idx;
1355 struct tx_ring_info *re = sky2->tx_ring + idx;
1356
1357 switch(le->opcode & ~HW_OWNER) {
1358 case OP_LARGESEND:
1359 case OP_PACKET:
1360 pci_unmap_single(pdev,
1361 pci_unmap_addr(re, mapaddr),
1362 pci_unmap_len(re, maplen),
1363 PCI_DMA_TODEVICE);
af2a58ac 1364 break;
291ea614
SH		 1365 case OP_BUFFER:
1366 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1367 pci_unmap_len(re, maplen),
734d1868 1368 PCI_DMA_TODEVICE);
291ea614
SH		 1369 break;
1370 }
1371
1372 if (le->ctrl & EOP) {
1373 if (unlikely(netif_msg_tx_done(sky2)))
1374 printk(KERN_DEBUG "%s: tx done %u\n",
1375 dev->name, idx);
1376 dev_kfree_skb(re->skb);
cd28ab6a
SH		 1377 }
1378
291ea614 1379 le->opcode = 0; /* paranoia */
793b883e 1380 }
793b883e 1381
291ea614 1382 sky2->tx_cons = idx;
22e11703 1383 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1384 netif_wake_queue(dev);
cd28ab6a
SH		 1385}
1386
1387/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1388static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1389{
2bb8c262
SH		 1390 struct sky2_port *sky2 = netdev_priv(dev);
1391
1392 netif_tx_lock_bh(dev);
d11c13e7 1393 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1394 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1395}
1396
1397/* Network shutdown */
1398static int sky2_down(struct net_device *dev)
1399{
1400 struct sky2_port *sky2 = netdev_priv(dev);
1401 struct sky2_hw *hw = sky2->hw;
1402 unsigned port = sky2->port;
1403 u16 ctrl;
e07b1aa8 1404 u32 imask;
cd28ab6a 1405
1b537565
SH		 1406 /* Never really got started! */
1407 if (!sky2->tx_le)
1408 return 0;
1409
cd28ab6a
SH		 1410 if (netif_msg_ifdown(sky2))
1411 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1412
018d1c66 1413 /* Stop more packets from being queued */
cd28ab6a
SH		 1414 netif_stop_queue(dev);
1415
d3bcfbeb 1416 sky2_gmac_reset(hw, port);
793b883e 1417
cd28ab6a
SH		 1418 /* Stop transmitter */
1419 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1420 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1421
1422 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1423 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1424
c2716fb4
SH		 1425 /* WA for dev. #4.209 */
1426 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1427 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1428 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1429 sky2->speed != SPEED_1000 ?
1430 TX_STFW_ENA : TX_STFW_DIS);
1431
cd28ab6a 1432 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1433 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1434 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1435
1436 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1437
1438 /* Workaround shared GMAC reset */
793b883e
SH		 1439 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1440 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1441 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1442
1443 /* Disable Force Sync bit and Enable Alloc bit */
1444 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1445 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1446
1447 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1448 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1449 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1450
1451 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1452 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1453 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1454
1455 /* Reset the Tx prefetch units */
1456 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1457 PREF_UNIT_RST_SET);
1458
1459 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1460
6b1a3aef 1461 sky2_rx_stop(sky2);
cd28ab6a
SH		 1462
1463 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1464 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1465
e07b1aa8
SH		 1466 /* Disable port IRQ */
1467 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1468 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1469 sky2_write32(hw, B0_IMSK, imask);
1470
d3bcfbeb 1471 sky2_phy_power(hw, port, 0);
1472
d571b694 1473 /* turn off LED's */
cd28ab6a
SH		 1474 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1475
018d1c66 1476 synchronize_irq(hw->pdev->irq);
1477
2bb8c262 1478 sky2_tx_clean(dev);
cd28ab6a
SH		 1479 sky2_rx_clean(sky2);
1480
1481 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1482 sky2->rx_le, sky2->rx_le_map);
1483 kfree(sky2->rx_ring);
1484
1485 pci_free_consistent(hw->pdev,
1486 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1487 sky2->tx_le, sky2->tx_le_map);
1488 kfree(sky2->tx_ring);
1489
1b537565
SH		 1490 sky2->tx_le = NULL;
1491 sky2->rx_le = NULL;
1492
1493 sky2->rx_ring = NULL;
1494 sky2->tx_ring = NULL;
1495
cd28ab6a
SH		 1496 return 0;
1497}
1498
1499static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1500{
b89165f2 1501 if (!sky2_is_copper(hw))
793b883e
SH		 1502 return SPEED_1000;
1503
cd28ab6a
SH		 1504 if (hw->chip_id == CHIP_ID_YUKON_FE)
1505 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1506
1507 switch (aux & PHY_M_PS_SPEED_MSK) {
1508 case PHY_M_PS_SPEED_1000:
1509 return SPEED_1000;
1510 case PHY_M_PS_SPEED_100:
1511 return SPEED_100;
1512 default:
1513 return SPEED_10;
1514 }
1515}
1516
1517static void sky2_link_up(struct sky2_port *sky2)
1518{
1519 struct sky2_hw *hw = sky2->hw;
1520 unsigned port = sky2->port;
1521 u16 reg;
1522
cd28ab6a 1523 /* enable Rx/Tx */
2eaba1a2 1524 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1525 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1526 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1527
1528 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1529
1530 netif_carrier_on(sky2->netdev);
1531 netif_wake_queue(sky2->netdev);
1532
1533 /* Turn on link LED */
793b883e 1534 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1535 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1536
ed6d32c7 1537 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1538 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1539 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1540
1541 switch(sky2->speed) {
1542 case SPEED_10:
1543 led |= PHY_M_LEDC_INIT_CTRL(7);
1544 break;
1545
1546 case SPEED_100:
1547 led |= PHY_M_LEDC_STA1_CTRL(7);
1548 break;
1549
1550 case SPEED_1000:
1551 led |= PHY_M_LEDC_STA0_CTRL(7);
1552 break;
1553 }
793b883e
SH		 1554
1555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1556 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1558 }
1559
cd28ab6a
SH		 1560 if (netif_msg_link(sky2))
1561 printk(KERN_INFO PFX
d571b694 1562 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1563 sky2->netdev->name, sky2->speed,
1564 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1565 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1566 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1567}
1568
1569static void sky2_link_down(struct sky2_port *sky2)
1570{
1571 struct sky2_hw *hw = sky2->hw;
1572 unsigned port = sky2->port;
1573 u16 reg;
1574
1575 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1576
1577 reg = gma_read16(hw, port, GM_GP_CTRL);
1578 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1579 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1580
1581 if (sky2->rx_pause && !sky2->tx_pause) {
1582 /* restore Asymmetric Pause bit */
1583 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1584 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1585 | PHY_M_AN_ASP);
cd28ab6a
SH		 1586 }
1587
cd28ab6a
SH		 1588 netif_carrier_off(sky2->netdev);
1589 netif_stop_queue(sky2->netdev);
1590
1591 /* Turn on link LED */
1592 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1593
1594 if (netif_msg_link(sky2))
1595 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1596
cd28ab6a
SH		 1597 sky2_phy_init(hw, port);
1598}
1599
793b883e
SH		 1600static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1601{
1602 struct sky2_hw *hw = sky2->hw;
1603 unsigned port = sky2->port;
1604 u16 lpa;
1605
1606 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1607
1608 if (lpa & PHY_M_AN_RF) {
1609 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1610 return -1;
1611 }
1612
793b883e
SH		 1613 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1614 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1615 sky2->netdev->name);
1616 return -1;
1617 }
1618
793b883e 1619 sky2->speed = sky2_phy_speed(hw, aux);
e0ed5459
SH		 1620 if (sky2->speed == SPEED_1000) {
1621 u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
1622 u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
1623 if (lpa2 & PHY_B_1000S_MSF) {
1624 printk(KERN_ERR PFX "%s: master/slave fault",
1625 sky2->netdev->name);
1626 return -1;
1627 }
1628
1629 if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
1630 sky2->duplex = DUPLEX_FULL;
1631 else
1632 sky2->duplex = DUPLEX_HALF;
1633 } else {
1634 u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1635 if ((aux & adv) & PHY_AN_FULL)
1636 sky2->duplex = DUPLEX_FULL;
1637 else
1638 sky2->duplex = DUPLEX_HALF;
1639 }
793b883e
SH		 1640
1641 /* Pause bits are offset (9..8) */
ed6d32c7 1642 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1643 aux >>= 6;
1644
1645 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1646 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1647
2eaba1a2
SH		 1648 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1649 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1650 sky2->rx_pause = sky2->tx_pause = 0;
1651
1652 if (sky2->rx_pause || sky2->tx_pause)
793b883e
SH		 1653 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1654 else
1655 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1656
1657 return 0;
1658}
cd28ab6a 1659
e07b1aa8
SH		 1660/* Interrupt from PHY */
1661static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1662{
e07b1aa8
SH		 1663 struct net_device *dev = hw->dev[port];
1664 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1665 u16 istatus, phystat;
1666
e07b1aa8
SH		 1667 spin_lock(&sky2->phy_lock);
1668 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1669 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1670
1671 if (!netif_running(dev))
1672 goto out;
cd28ab6a
SH		 1673
1674 if (netif_msg_intr(sky2))
1675 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1676 sky2->netdev->name, istatus, phystat);
1677
2eaba1a2 1678 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1679 if (sky2_autoneg_done(sky2, phystat) == 0)
1680 sky2_link_up(sky2);
1681 goto out;
1682 }
cd28ab6a 1683
793b883e
SH		 1684 if (istatus & PHY_M_IS_LSP_CHANGE)
1685 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1686
793b883e
SH		 1687 if (istatus & PHY_M_IS_DUP_CHANGE)
1688 sky2->duplex =
1689 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1690
793b883e
SH		 1691 if (istatus & PHY_M_IS_LST_CHANGE) {
1692 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1693 sky2_link_up(sky2);
793b883e
SH		 1694 else
1695 sky2_link_down(sky2);
cd28ab6a 1696 }
793b883e 1697out:
e07b1aa8 1698 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1699}
1700
302d1252
SH		 1701
1702/* Transmit timeout is only called if we are running, carries is up
1703 * and tx queue is full (stopped).
1704 */
cd28ab6a
SH		 1705static void sky2_tx_timeout(struct net_device *dev)
1706{
1707 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1708 struct sky2_hw *hw = sky2->hw;
1709 unsigned txq = txqaddr[sky2->port];
8f24664d 1710 u16 report, done;
cd28ab6a
SH		 1711
1712 if (netif_msg_timer(sky2))
1713 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1714
8f24664d
SH		 1715 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1716 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1717
8f24664d
SH		 1718 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1719 dev->name,
1720 sky2->tx_cons, sky2->tx_prod, report, done);
1721
1722 if (report != done) {
1723 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1724
1725 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1726 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1727 } else if (report != sky2->tx_cons) {
1728 printk(KERN_INFO PFX "status report lost?\n");
1729
2bb8c262 1730 netif_tx_lock_bh(dev);
8f24664d 1731 sky2_tx_complete(sky2, report);
2bb8c262 1732 netif_tx_unlock_bh(dev);
8f24664d
SH		 1733 } else {
1734 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1735
8f24664d
SH		 1736 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1737 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1738
2bb8c262 1739 sky2_tx_clean(dev);
8f24664d
SH		 1740
1741 sky2_qset(hw, txq);
1742 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1743 }
cd28ab6a
SH		 1744}
1745
734d1868 1746
70f1be48
SH		 1747/* Want receive buffer size to be multiple of 64 bits
1748 * and incl room for vlan and truncation
1749 */
734d1868
SH		 1750static inline unsigned sky2_buf_size(int mtu)
1751{
4a15d56f 1752 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1753}
1754
cd28ab6a
SH		 1755static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1756{
6b1a3aef 1757 struct sky2_port *sky2 = netdev_priv(dev);
1758 struct sky2_hw *hw = sky2->hw;
1759 int err;
1760 u16 ctl, mode;
e07b1aa8 1761 u32 imask;
cd28ab6a
SH		 1762
1763 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1764 return -EINVAL;
1765
5a5b1ea0 1766 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1767 return -EINVAL;
1768
6b1a3aef 1769 if (!netif_running(dev)) {
1770 dev->mtu = new_mtu;
1771 return 0;
1772 }
1773
e07b1aa8 1774 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1775 sky2_write32(hw, B0_IMSK, 0);
1776
018d1c66 1777 dev->trans_start = jiffies; /* prevent tx timeout */
1778 netif_stop_queue(dev);
1779 netif_poll_disable(hw->dev[0]);
1780
e07b1aa8
SH		 1781 synchronize_irq(hw->pdev->irq);
1782
6b1a3aef 1783 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1784 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1785 sky2_rx_stop(sky2);
1786 sky2_rx_clean(sky2);
cd28ab6a
SH		 1787
1788 dev->mtu = new_mtu;
734d1868 1789 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef 1790 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1791 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1792
1793 if (dev->mtu > ETH_DATA_LEN)
1794 mode |= GM_SMOD_JUMBO_ENA;
1795
1796 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1797
6b1a3aef 1798 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1799
6b1a3aef 1800 err = sky2_rx_start(sky2);
e07b1aa8 1801 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1802
1b537565
SH		 1803 if (err)
1804 dev_close(dev);
1805 else {
1806 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1807
1808 netif_poll_enable(hw->dev[0]);
1809 netif_wake_queue(dev);
1810 }
1811
cd28ab6a
SH		 1812 return err;
1813}
1814
1815/*
1816 * Receive one packet.
1817 * For small packets or errors, just reuse existing skb.
d571b694 1818 * For larger packets, get new buffer.
cd28ab6a 1819 */
497d7c86 1820static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1821 u16 length, u32 status)
1822{
497d7c86 1823 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1824 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1825 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1826
1827 if (unlikely(netif_msg_rx_status(sky2)))
1828 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1829 dev->name, sky2->rx_next, status, length);
cd28ab6a 1830
793b883e 1831 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1832 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1833
42eeea01 1834 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1835 goto error;
1836
42eeea01 1837 if (!(status & GMR_FS_RX_OK))
1838 goto resubmit;
1839
497d7c86 1840 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1841 goto oversize;
1842
bdb5c58e 1843 if (length < copybreak) {
497d7c86 1844 skb = netdev_alloc_skb(dev, length + 2);
79e57d32 1845 if (!skb)
793b883e
SH		 1846 goto resubmit;
1847
79e57d32 1848 skb_reserve(skb, 2);
793b883e
SH		 1849 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1850 length, PCI_DMA_FROMDEVICE);
79e57d32 1851 memcpy(skb->data, re->skb->data, length);
d11c13e7 1852 skb->ip_summed = re->skb->ip_summed;
1853 skb->csum = re->skb->csum;
793b883e
SH		 1854 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1855 length, PCI_DMA_FROMDEVICE);
793b883e 1856 } else {
79e57d32
SH		 1857 struct sk_buff *nskb;
1858
497d7c86 1859 nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1860 if (!nskb)
1861 goto resubmit;
cd28ab6a 1862
793b883e 1863 skb = re->skb;
79e57d32 1864 re->skb = nskb;
793b883e 1865 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1866 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1867 prefetch(skb->data);
cd28ab6a 1868
793b883e 1869 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
291ea614 1870 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1871 }
cd28ab6a 1872
79e57d32 1873 skb_put(skb, length);
793b883e 1874resubmit:
d11c13e7 1875 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1876 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1877
cd28ab6a
SH		 1878 return skb;
1879
6e15b712
SH		 1880oversize:
1881 ++sky2->net_stats.rx_over_errors;
1882 goto resubmit;
1883
cd28ab6a 1884error:
6e15b712
SH		 1885 ++sky2->net_stats.rx_errors;
1886
3be92a70 1887 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 1888 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 1889 dev->name, status, length);
793b883e
SH		 1890
1891 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1892 sky2->net_stats.rx_length_errors++;
1893 if (status & GMR_FS_FRAGMENT)
1894 sky2->net_stats.rx_frame_errors++;
1895 if (status & GMR_FS_CRC_ERR)
1896 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1897 if (status & GMR_FS_RX_FF_OV)
1898 sky2->net_stats.rx_fifo_errors++;
79e57d32 1899
793b883e 1900 goto resubmit;
cd28ab6a
SH		 1901}
1902
e07b1aa8
SH		 1903/* Transmit complete */
1904static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1905{
e07b1aa8 1906 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1907
e07b1aa8 1908 if (netif_running(dev)) {
2bb8c262 1909 netif_tx_lock(dev);
e07b1aa8 1910 sky2_tx_complete(sky2, last);
2bb8c262 1911 netif_tx_unlock(dev);
2224795d 1912 }
cd28ab6a
SH		 1913}
1914
e07b1aa8
SH		 1915/* Process status response ring */
1916static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1917{
22e11703 1918 struct sky2_port *sky2;
e07b1aa8 1919 int work_done = 0;
22e11703 1920 unsigned buf_write[2] = { 0, 0 };
e71ebd73 1921 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1922
af2a58ac 1923 rmb();
bea86103 1924
e71ebd73 1925 while (hw->st_idx != hwidx) {
13210ce5 1926 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1927 struct net_device *dev;
cd28ab6a 1928 struct sk_buff *skb;
cd28ab6a
SH		 1929 u32 status;
1930 u16 length;
1931
cb5d9547 1932 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1933
e71ebd73
SH		 1934 BUG_ON(le->link >= 2);
1935 dev = hw->dev[le->link];
13210ce5 1936
1937 sky2 = netdev_priv(dev);
f65b138c
SH		 1938 length = le16_to_cpu(le->length);
1939 status = le32_to_cpu(le->status);
cd28ab6a 1940
e71ebd73 1941 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1942 case OP_RXSTAT:
497d7c86 1943 skb = sky2_receive(dev, length, status);
d1f13708 1944 if (!skb)
1945 break;
13210ce5 1946
13210ce5 1947 skb->protocol = eth_type_trans(skb, dev);
1948 dev->last_rx = jiffies;
1949
d1f13708 1950#ifdef SKY2_VLAN_TAG_USED
1951 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1952 vlan_hwaccel_receive_skb(skb,
1953 sky2->vlgrp,
1954 be16_to_cpu(sky2->rx_tag));
1955 } else
1956#endif
cd28ab6a 1957 netif_receive_skb(skb);
13210ce5 1958
22e11703
SH		 1959 /* Update receiver after 16 frames */
1960 if (++buf_write[le->link] == RX_BUF_WRITE) {
1961 sky2_put_idx(hw, rxqaddr[le->link],
1962 sky2->rx_put);
1963 buf_write[le->link] = 0;
1964 }
1965
1966 /* Stop after net poll weight */
13210ce5 1967 if (++work_done >= to_do)
1968 goto exit_loop;
cd28ab6a
SH		 1969 break;
1970
d1f13708 1971#ifdef SKY2_VLAN_TAG_USED
1972 case OP_RXVLAN:
1973 sky2->rx_tag = length;
1974 break;
1975
1976 case OP_RXCHKSVLAN:
1977 sky2->rx_tag = length;
1978 /* fall through */
1979#endif
cd28ab6a 1980 case OP_RXCHKS:
d11c13e7 1981 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 1982 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 1983 skb->csum = status & 0xffff;
cd28ab6a
SH		 1984 break;
1985
1986 case OP_TXINDEXLE:
13b97b74 1987 /* TX index reports status for both ports */
f55925d7
SH		 1988 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1989 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 1990 if (hw->dev[1])
1991 sky2_tx_done(hw->dev[1],
1992 ((status >> 24) & 0xff)
1993 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1994 break;
1995
cd28ab6a
SH		 1996 default:
1997 if (net_ratelimit())
793b883e 1998 printk(KERN_WARNING PFX
e71ebd73
SH		 1999 "unknown status opcode 0x%x\n", le->opcode);
2000 goto exit_loop;
cd28ab6a 2001 }
13210ce5 2002 }
cd28ab6a 2003
fe2a24df
SH		 2004 /* Fully processed status ring so clear irq */
2005 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2006
13210ce5 2007exit_loop:
22e11703
SH		 2008 if (buf_write[0]) {
2009 sky2 = netdev_priv(hw->dev[0]);
2010 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2011 }
2012
2013 if (buf_write[1]) {
2014 sky2 = netdev_priv(hw->dev[1]);
2015 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2016 }
2017
e07b1aa8 2018 return work_done;
cd28ab6a
SH		 2019}
2020
2021static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2022{
2023 struct net_device *dev = hw->dev[port];
2024
3be92a70
SH		 2025 if (net_ratelimit())
2026 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2027 dev->name, status);
cd28ab6a
SH		 2028
2029 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2030 if (net_ratelimit())
2031 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2032 dev->name);
cd28ab6a
SH		 2033 /* Clear IRQ */
2034 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2035 }
2036
2037 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2038 if (net_ratelimit())
2039 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2040 dev->name);
cd28ab6a
SH		 2041
2042 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2043 }
2044
2045 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2046 if (net_ratelimit())
2047 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2048 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2049 }
2050
2051 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2052 if (net_ratelimit())
2053 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2054 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2055 }
2056
2057 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2058 if (net_ratelimit())
2059 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2060 dev->name);
cd28ab6a
SH		 2061 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2062 }
2063}
2064
2065static void sky2_hw_intr(struct sky2_hw *hw)
2066{
2067 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2068
793b883e 2069 if (status & Y2_IS_TIST_OV)
cd28ab6a 2070 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2071
2072 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2073 u16 pci_err;
2074
56a645cc 2075 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2076 if (net_ratelimit())
2077 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2078 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2079
2080 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2081 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2082 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2083 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2084 }
2085
2086 if (status & Y2_IS_PCI_EXP) {
d571b694 2087 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2088 u32 pex_err;
2089
91aeb3ed
SH		 2090 pex_err = sky2_pci_read32(hw,
2091 hw->err_cap + PCI_ERR_UNCOR_STATUS);
cd28ab6a 2092
3be92a70
SH		 2093 if (net_ratelimit())
2094 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2095 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2096
2097 /* clear the interrupt */
2098 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
91aeb3ed
SH		 2099 sky2_pci_write32(hw,
2100 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2101 0xffffffffUL);
cd28ab6a
SH		 2102 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2103
91aeb3ed
SH		 2104
2105 /* In case of fatal error mask off to keep from getting stuck */
2106 if (pex_err & (PCI_ERR_UNC_POISON_TLP | PCI_ERR_UNC_FCP
2107 | PCI_ERR_UNC_DLP)) {
cd28ab6a
SH		 2108 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2109 hwmsk &= ~Y2_IS_PCI_EXP;
2110 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2111 }
91aeb3ed 2112
cd28ab6a
SH		 2113 }
2114
2115 if (status & Y2_HWE_L1_MASK)
2116 sky2_hw_error(hw, 0, status);
2117 status >>= 8;
2118 if (status & Y2_HWE_L1_MASK)
2119 sky2_hw_error(hw, 1, status);
2120}
2121
2122static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2123{
2124 struct net_device *dev = hw->dev[port];
2125 struct sky2_port *sky2 = netdev_priv(dev);
2126 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2127
2128 if (netif_msg_intr(sky2))
2129 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2130 dev->name, status);
2131
2132 if (status & GM_IS_RX_FF_OR) {
2133 ++sky2->net_stats.rx_fifo_errors;
2134 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2135 }
2136
2137 if (status & GM_IS_TX_FF_UR) {
2138 ++sky2->net_stats.tx_fifo_errors;
2139 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2140 }
cd28ab6a
SH		 2141}
2142
d257924e
SH		 2143/* This should never happen it is a fatal situation */
2144static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2145 const char *rxtx, u32 mask)
2146{
2147 struct net_device *dev = hw->dev[port];
2148 struct sky2_port *sky2 = netdev_priv(dev);
2149 u32 imask;
2150
2151 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2152 dev ? dev->name : "<not registered>", rxtx);
2153
2154 imask = sky2_read32(hw, B0_IMSK);
2155 imask &= ~mask;
2156 sky2_write32(hw, B0_IMSK, imask);
2157
2158 if (dev) {
2159 spin_lock(&sky2->phy_lock);
2160 sky2_link_down(sky2);
2161 spin_unlock(&sky2->phy_lock);
2162 }
2163}
cd28ab6a 2164
d27ed387
SH		 2165/* If idle then force a fake soft NAPI poll once a second
2166 * to work around cases where sharing an edge triggered interrupt.
2167 */
eb35cf60
SH		 2168static inline void sky2_idle_start(struct sky2_hw *hw)
2169{
2170 if (idle_timeout > 0)
2171 mod_timer(&hw->idle_timer,
2172 jiffies + msecs_to_jiffies(idle_timeout));
2173}
2174
d27ed387
SH		 2175static void sky2_idle(unsigned long arg)
2176{
01bd7564
SH		 2177 struct sky2_hw *hw = (struct sky2_hw *) arg;
2178 struct net_device *dev = hw->dev[0];
d27ed387 2179
d27ed387
SH		 2180 if (__netif_rx_schedule_prep(dev))
2181 __netif_rx_schedule(dev);
01bd7564
SH		 2182
2183 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2184}
2185
2186
e07b1aa8 2187static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2188{
e07b1aa8
SH		 2189 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2190 int work_limit = min(dev0->quota, *budget);
2191 int work_done = 0;
fb2690a9 2192 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2193
1e5f1283
SH		 2194 if (status & Y2_IS_HW_ERR)
2195 sky2_hw_intr(hw);
d257924e 2196
1e5f1283
SH		 2197 if (status & Y2_IS_IRQ_PHY1)
2198 sky2_phy_intr(hw, 0);
cd28ab6a 2199
1e5f1283
SH		 2200 if (status & Y2_IS_IRQ_PHY2)
2201 sky2_phy_intr(hw, 1);
cd28ab6a 2202
1e5f1283
SH		 2203 if (status & Y2_IS_IRQ_MAC1)
2204 sky2_mac_intr(hw, 0);
cd28ab6a 2205
1e5f1283
SH		 2206 if (status & Y2_IS_IRQ_MAC2)
2207 sky2_mac_intr(hw, 1);
cd28ab6a 2208
1e5f1283
SH		 2209 if (status & Y2_IS_CHK_RX1)
2210 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2211
1e5f1283
SH		 2212 if (status & Y2_IS_CHK_RX2)
2213 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2214
1e5f1283
SH		 2215 if (status & Y2_IS_CHK_TXA1)
2216 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2217
1e5f1283
SH		 2218 if (status & Y2_IS_CHK_TXA2)
2219 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2220
1e5f1283 2221 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2222 if (work_done < work_limit) {
2223 netif_rx_complete(dev0);
86fba634 2224
fe2a24df
SH		 2225 sky2_read32(hw, B0_Y2_SP_LISR);
2226 return 0;
2227 } else {
2228 *budget -= work_done;
2229 dev0->quota -= work_done;
1e5f1283 2230 return 1;
fe2a24df 2231 }
e07b1aa8
SH		 2232}
2233
2234static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2235{
2236 struct sky2_hw *hw = dev_id;
2237 struct net_device *dev0 = hw->dev[0];
2238 u32 status;
2239
2240 /* Reading this mask interrupts as side effect */
2241 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2242 if (status == 0 || status == ~0)
2243 return IRQ_NONE;
793b883e 2244
e07b1aa8
SH		 2245 prefetch(&hw->st_le[hw->st_idx]);
2246 if (likely(__netif_rx_schedule_prep(dev0)))
2247 __netif_rx_schedule(dev0);
793b883e 2248
cd28ab6a
SH		 2249 return IRQ_HANDLED;
2250}
2251
2252#ifdef CONFIG_NET_POLL_CONTROLLER
2253static void sky2_netpoll(struct net_device *dev)
2254{
2255 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2256 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2257
88d11360
SH		 2258 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2259 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2260}
2261#endif
2262
2263/* Chip internal frequency for clock calculations */
fb17358f 2264static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2265{
793b883e 2266 switch (hw->chip_id) {
cd28ab6a 2267 case CHIP_ID_YUKON_EC:
5a5b1ea0 2268 case CHIP_ID_YUKON_EC_U:
fb17358f 2269 return 125; /* 125 Mhz */
cd28ab6a 2270 case CHIP_ID_YUKON_FE:
fb17358f 2271 return 100; /* 100 Mhz */
793b883e 2272 default: /* YUKON_XL */
fb17358f 2273 return 156; /* 156 Mhz */
cd28ab6a
SH		 2274 }
2275}
2276
fb17358f 2277static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2278{
fb17358f 2279 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2280}
2281
fb17358f 2282static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2283{
fb17358f 2284 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2285}
2286
fb17358f 2287
59139528 2288static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2289{
cd28ab6a 2290 u16 status;
b89165f2 2291 u8 t8;
56a645cc 2292 int i;
91aeb3ed 2293 u32 msk;
cd28ab6a 2294
cd28ab6a 2295 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2296
cd28ab6a
SH		 2297 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2298 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2299 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2300 pci_name(hw->pdev), hw->chip_id);
2301 return -EOPNOTSUPP;
2302 }
2303
290d4de5
SH		 2304 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2305
2306 /* This rev is really old, and requires untested workarounds */
2307 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2308 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2309 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2310 hw->chip_id, hw->chip_rev);
2311 return -EOPNOTSUPP;
2312 }
2313
cd28ab6a
SH		 2314 /* disable ASF */
2315 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2316 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2317 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2318 }
2319
2320 /* do a SW reset */
2321 sky2_write8(hw, B0_CTST, CS_RST_SET);
2322 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2323
2324 /* clear PCI errors, if any */
56a645cc 2325 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2326
cd28ab6a 2327 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2328 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2329
cd28ab6a
SH		 2330
2331 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2332
2333 /* clear any PEX errors */
91aeb3ed
SH		 2334 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2335 hw->err_cap = pci_find_ext_capability(hw->pdev, PCI_EXT_CAP_ID_ERR);
2336 if (hw->err_cap)
2337 sky2_pci_write32(hw,
2338 hw->err_cap + PCI_ERR_UNCOR_STATUS,
2339 0xffffffffUL);
2340 }
cd28ab6a 2341
b89165f2 2342 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2343 hw->ports = 1;
2344 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2345 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2346 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2347 ++hw->ports;
2348 }
cd28ab6a 2349
5afa0a9c 2350 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2351
2352 for (i = 0; i < hw->ports; i++) {
2353 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2354 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2355 }
2356
2357 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2358
793b883e
SH		 2359 /* Clear I2C IRQ noise */
2360 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2361
2362 /* turn off hardware timer (unused) */
2363 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2364 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2365
cd28ab6a
SH		 2366 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2367
69634ee7
SH		 2368 /* Turn off descriptor polling */
2369 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2370
2371 /* Turn off receive timestamp */
2372 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2373 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2374
2375 /* enable the Tx Arbiters */
2376 for (i = 0; i < hw->ports; i++)
2377 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2378
2379 /* Initialize ram interface */
2380 for (i = 0; i < hw->ports; i++) {
793b883e 2381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2382
2383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2385 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2395 }
2396
91aeb3ed
SH		 2397 msk = Y2_HWE_ALL_MASK;
2398 if (!hw->err_cap)
2399 msk &= ~Y2_IS_PCI_EXP;
2400 sky2_write32(hw, B0_HWE_IMSK, msk);
cd28ab6a 2401
cd28ab6a 2402 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2403 sky2_gmac_reset(hw, i);
cd28ab6a 2404
cd28ab6a
SH		 2405 memset(hw->st_le, 0, STATUS_LE_BYTES);
2406 hw->st_idx = 0;
2407
2408 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2409 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2410
2411 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2412 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2413
2414 /* Set the list last index */
793b883e 2415 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2416
290d4de5
SH		 2417 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2418 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2419
290d4de5
SH		 2420 /* set Status-FIFO ISR watermark */
2421 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2422 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2423 else
2424 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2425
290d4de5 2426 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2427 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2428 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2429
793b883e 2430 /* enable status unit */
cd28ab6a
SH		 2431 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2432
2433 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2434 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2435 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2436
2437 return 0;
2438}
2439
28bd181a 2440static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2441{
b89165f2
SH		 2442 if (sky2_is_copper(hw)) {
2443 u32 modes = SUPPORTED_10baseT_Half
2444 | SUPPORTED_10baseT_Full
2445 | SUPPORTED_100baseT_Half
2446 | SUPPORTED_100baseT_Full
2447 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2448
2449 if (hw->chip_id != CHIP_ID_YUKON_FE)
2450 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2451 | SUPPORTED_1000baseT_Full;
2452 return modes;
cd28ab6a 2453 } else
b89165f2
SH		 2454 return SUPPORTED_1000baseT_Half
2455 | SUPPORTED_1000baseT_Full
2456 | SUPPORTED_Autoneg
2457 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2458}
2459
793b883e 2460static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2461{
2462 struct sky2_port *sky2 = netdev_priv(dev);
2463 struct sky2_hw *hw = sky2->hw;
2464
2465 ecmd->transceiver = XCVR_INTERNAL;
2466 ecmd->supported = sky2_supported_modes(hw);
2467 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2468 if (sky2_is_copper(hw)) {
cd28ab6a 2469 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2470 | SUPPORTED_10baseT_Full
2471 | SUPPORTED_100baseT_Half
2472 | SUPPORTED_100baseT_Full
2473 | SUPPORTED_1000baseT_Half
2474 | SUPPORTED_1000baseT_Full
2475 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2476 ecmd->port = PORT_TP;
b89165f2
SH		 2477 ecmd->speed = sky2->speed;
2478 } else {
2479 ecmd->speed = SPEED_1000;
cd28ab6a 2480 ecmd->port = PORT_FIBRE;
b89165f2 2481 }
cd28ab6a
SH		 2482
2483 ecmd->advertising = sky2->advertising;
2484 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2485 ecmd->duplex = sky2->duplex;
2486 return 0;
2487}
2488
2489static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2490{
2491 struct sky2_port *sky2 = netdev_priv(dev);
2492 const struct sky2_hw *hw = sky2->hw;
2493 u32 supported = sky2_supported_modes(hw);
2494
2495 if (ecmd->autoneg == AUTONEG_ENABLE) {
2496 ecmd->advertising = supported;
2497 sky2->duplex = -1;
2498 sky2->speed = -1;
2499 } else {
2500 u32 setting;
2501
793b883e 2502 switch (ecmd->speed) {
cd28ab6a
SH		 2503 case SPEED_1000:
2504 if (ecmd->duplex == DUPLEX_FULL)
2505 setting = SUPPORTED_1000baseT_Full;
2506 else if (ecmd->duplex == DUPLEX_HALF)
2507 setting = SUPPORTED_1000baseT_Half;
2508 else
2509 return -EINVAL;
2510 break;
2511 case SPEED_100:
2512 if (ecmd->duplex == DUPLEX_FULL)
2513 setting = SUPPORTED_100baseT_Full;
2514 else if (ecmd->duplex == DUPLEX_HALF)
2515 setting = SUPPORTED_100baseT_Half;
2516 else
2517 return -EINVAL;
2518 break;
2519
2520 case SPEED_10:
2521 if (ecmd->duplex == DUPLEX_FULL)
2522 setting = SUPPORTED_10baseT_Full;
2523 else if (ecmd->duplex == DUPLEX_HALF)
2524 setting = SUPPORTED_10baseT_Half;
2525 else
2526 return -EINVAL;
2527 break;
2528 default:
2529 return -EINVAL;
2530 }
2531
2532 if ((setting & supported) == 0)
2533 return -EINVAL;
2534
2535 sky2->speed = ecmd->speed;
2536 sky2->duplex = ecmd->duplex;
2537 }
2538
2539 sky2->autoneg = ecmd->autoneg;
2540 sky2->advertising = ecmd->advertising;
2541
1b537565
SH		 2542 if (netif_running(dev))
2543 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2544
2545 return 0;
2546}
2547
2548static void sky2_get_drvinfo(struct net_device *dev,
2549 struct ethtool_drvinfo *info)
2550{
2551 struct sky2_port *sky2 = netdev_priv(dev);
2552
2553 strcpy(info->driver, DRV_NAME);
2554 strcpy(info->version, DRV_VERSION);
2555 strcpy(info->fw_version, "N/A");
2556 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2557}
2558
2559static const struct sky2_stat {
793b883e
SH		 2560 char name[ETH_GSTRING_LEN];
2561 u16 offset;
cd28ab6a
SH		 2562} sky2_stats[] = {
2563 { "tx_bytes", GM_TXO_OK_HI },
2564 { "rx_bytes", GM_RXO_OK_HI },
2565 { "tx_broadcast", GM_TXF_BC_OK },
2566 { "rx_broadcast", GM_RXF_BC_OK },
2567 { "tx_multicast", GM_TXF_MC_OK },
2568 { "rx_multicast", GM_RXF_MC_OK },
2569 { "tx_unicast", GM_TXF_UC_OK },
2570 { "rx_unicast", GM_RXF_UC_OK },
2571 { "tx_mac_pause", GM_TXF_MPAUSE },
2572 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2573 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2574 { "late_collision",GM_TXF_LAT_COL },
2575 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2576 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2577 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2578
d2604540 2579 { "rx_short", GM_RXF_SHT },
cd28ab6a 2580 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2581 { "rx_64_byte_packets", GM_RXF_64B },
2582 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2583 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2584 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2585 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2586 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2587 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2588 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2589 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2590 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2591 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2592
2593 { "tx_64_byte_packets", GM_TXF_64B },
2594 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2595 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2596 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2597 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2598 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2599 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2600 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2601};
2602
cd28ab6a
SH		 2603static u32 sky2_get_rx_csum(struct net_device *dev)
2604{
2605 struct sky2_port *sky2 = netdev_priv(dev);
2606
2607 return sky2->rx_csum;
2608}
2609
2610static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2611{
2612 struct sky2_port *sky2 = netdev_priv(dev);
2613
2614 sky2->rx_csum = data;
793b883e 2615
cd28ab6a
SH		 2616 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2617 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2618
2619 return 0;
2620}
2621
2622static u32 sky2_get_msglevel(struct net_device *netdev)
2623{
2624 struct sky2_port *sky2 = netdev_priv(netdev);
2625 return sky2->msg_enable;
2626}
2627
9a7ae0a9
SH		 2628static int sky2_nway_reset(struct net_device *dev)
2629{
2630 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2631
2632 if (sky2->autoneg != AUTONEG_ENABLE)
2633 return -EINVAL;
2634
1b537565 2635 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2636
2637 return 0;
2638}
2639
793b883e 2640static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2641{
2642 struct sky2_hw *hw = sky2->hw;
2643 unsigned port = sky2->port;
2644 int i;
2645
2646 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2647 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2648 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2649 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2650
793b883e 2651 for (i = 2; i < count; i++)
cd28ab6a
SH		 2652 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2653}
2654
cd28ab6a
SH		 2655static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2656{
2657 struct sky2_port *sky2 = netdev_priv(netdev);
2658 sky2->msg_enable = value;
2659}
2660
2661static int sky2_get_stats_count(struct net_device *dev)
2662{
2663 return ARRAY_SIZE(sky2_stats);
2664}
2665
2666static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2667 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2668{
2669 struct sky2_port *sky2 = netdev_priv(dev);
2670
793b883e 2671 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2672}
2673
793b883e 2674static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2675{
2676 int i;
2677
2678 switch (stringset) {
2679 case ETH_SS_STATS:
2680 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2681 memcpy(data + i * ETH_GSTRING_LEN,
2682 sky2_stats[i].name, ETH_GSTRING_LEN);
2683 break;
2684 }
2685}
2686
2687/* Use hardware MIB variables for critical path statistics and
2688 * transmit feedback not reported at interrupt.
2689 * Other errors are accounted for in interrupt handler.
2690 */
2691static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2692{
2693 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2694 u64 data[13];
cd28ab6a 2695
793b883e 2696 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2697
2698 sky2->net_stats.tx_bytes = data[0];
2699 sky2->net_stats.rx_bytes = data[1];
2700 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2701 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2702 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2703 sky2->net_stats.collisions = data[10];
2704 sky2->net_stats.tx_aborted_errors = data[12];
2705
2706 return &sky2->net_stats;
2707}
2708
2709static int sky2_set_mac_address(struct net_device *dev, void *p)
2710{
2711 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2712 struct sky2_hw *hw = sky2->hw;
2713 unsigned port = sky2->port;
2714 const struct sockaddr *addr = p;
cd28ab6a
SH		 2715
2716 if (!is_valid_ether_addr(addr->sa_data))
2717 return -EADDRNOTAVAIL;
2718
cd28ab6a 2719 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2720 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2721 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2722 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2723 dev->dev_addr, ETH_ALEN);
1b537565 2724
a8ab1ec0
SH		 2725 /* virtual address for data */
2726 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2727
2728 /* physical address: used for pause frames */
2729 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2730
2731 return 0;
cd28ab6a
SH		 2732}
2733
2734static void sky2_set_multicast(struct net_device *dev)
2735{
2736 struct sky2_port *sky2 = netdev_priv(dev);
2737 struct sky2_hw *hw = sky2->hw;
2738 unsigned port = sky2->port;
2739 struct dev_mc_list *list = dev->mc_list;
2740 u16 reg;
2741 u8 filter[8];
2742
2743 memset(filter, 0, sizeof(filter));
2744
2745 reg = gma_read16(hw, port, GM_RX_CTRL);
2746 reg |= GM_RXCR_UCF_ENA;
2747
d571b694 2748 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2749 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2750 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2751 memset(filter, 0xff, sizeof(filter));
793b883e 2752 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2753 reg &= ~GM_RXCR_MCF_ENA;
2754 else {
2755 int i;
2756 reg |= GM_RXCR_MCF_ENA;
2757
2758 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2759 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2760 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2761 }
2762 }
2763
cd28ab6a 2764 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2765 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2766 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2767 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2768 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2769 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2770 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2771 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2772
2773 gma_write16(hw, port, GM_RX_CTRL, reg);
2774}
2775
2776/* Can have one global because blinking is controlled by
2777 * ethtool and that is always under RTNL mutex
2778 */
91c86df5 2779static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2780{
793b883e
SH		 2781 u16 pg;
2782
793b883e
SH		 2783 switch (hw->chip_id) {
2784 case CHIP_ID_YUKON_XL:
2785 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2786 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2787 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2788 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2789 PHY_M_LEDC_INIT_CTRL(7) |
2790 PHY_M_LEDC_STA1_CTRL(7) |
2791 PHY_M_LEDC_STA0_CTRL(7))
2792 : 0);
2793
2794 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2795 break;
2796
2797 default:
2798 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2799 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2800 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2801 PHY_M_LED_MO_10(MO_LED_ON) |
2802 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2803 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2804 PHY_M_LED_MO_RX(MO_LED_ON)
2805 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2806 PHY_M_LED_MO_10(MO_LED_OFF) |
2807 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2808 PHY_M_LED_MO_1000(MO_LED_OFF) |
2809 PHY_M_LED_MO_RX(MO_LED_OFF));
2810
793b883e 2811 }
cd28ab6a
SH		 2812}
2813
2814/* blink LED's for finding board */
2815static int sky2_phys_id(struct net_device *dev, u32 data)
2816{
2817 struct sky2_port *sky2 = netdev_priv(dev);
2818 struct sky2_hw *hw = sky2->hw;
2819 unsigned port = sky2->port;
793b883e 2820 u16 ledctrl, ledover = 0;
cd28ab6a 2821 long ms;
91c86df5 2822 int interrupted;
cd28ab6a
SH		 2823 int onoff = 1;
2824
793b883e 2825 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2826 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2827 else
2828 ms = data * 1000;
2829
2830 /* save initial values */
e07b1aa8 2831 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2832 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2833 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2834 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2835 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2836 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2837 } else {
2838 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2839 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2840 }
cd28ab6a 2841
91c86df5
SH		 2842 interrupted = 0;
2843 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2844 sky2_led(hw, port, onoff);
2845 onoff = !onoff;
2846
e07b1aa8 2847 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2848 interrupted = msleep_interruptible(250);
e07b1aa8 2849 spin_lock_bh(&sky2->phy_lock);
91c86df5 2850
cd28ab6a
SH		 2851 ms -= 250;
2852 }
2853
2854 /* resume regularly scheduled programming */
793b883e
SH		 2855 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2856 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2857 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2858 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2859 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2860 } else {
2861 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2862 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2863 }
e07b1aa8 2864 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2865
2866 return 0;
2867}
2868
2869static void sky2_get_pauseparam(struct net_device *dev,
2870 struct ethtool_pauseparam *ecmd)
2871{
2872 struct sky2_port *sky2 = netdev_priv(dev);
2873
2874 ecmd->tx_pause = sky2->tx_pause;
2875 ecmd->rx_pause = sky2->rx_pause;
2876 ecmd->autoneg = sky2->autoneg;
2877}
2878
2879static int sky2_set_pauseparam(struct net_device *dev,
2880 struct ethtool_pauseparam *ecmd)
2881{
2882 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2883
2884 sky2->autoneg = ecmd->autoneg;
2885 sky2->tx_pause = ecmd->tx_pause != 0;
2886 sky2->rx_pause = ecmd->rx_pause != 0;
2887
1b537565 2888 sky2_phy_reinit(sky2);
cd28ab6a 2889
2eaba1a2 2890 return 0;
cd28ab6a
SH		 2891}
2892
fb17358f
SH		 2893static int sky2_get_coalesce(struct net_device *dev,
2894 struct ethtool_coalesce *ecmd)
2895{
2896 struct sky2_port *sky2 = netdev_priv(dev);
2897 struct sky2_hw *hw = sky2->hw;
2898
2899 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2900 ecmd->tx_coalesce_usecs = 0;
2901 else {
2902 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2903 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2904 }
2905 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2906
2907 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2908 ecmd->rx_coalesce_usecs = 0;
2909 else {
2910 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2911 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2912 }
2913 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2914
2915 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2916 ecmd->rx_coalesce_usecs_irq = 0;
2917 else {
2918 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2919 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2920 }
2921
2922 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2923
2924 return 0;
2925}
2926
2927/* Note: this affect both ports */
2928static int sky2_set_coalesce(struct net_device *dev,
2929 struct ethtool_coalesce *ecmd)
2930{
2931 struct sky2_port *sky2 = netdev_priv(dev);
2932 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2933 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2934
77b3d6a2
SH		 2935 if (ecmd->tx_coalesce_usecs > tmax ||
2936 ecmd->rx_coalesce_usecs > tmax ||
2937 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2938 return -EINVAL;
2939
ff81fbbe 2940 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2941 return -EINVAL;
ff81fbbe 2942 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2943 return -EINVAL;
ff81fbbe 2944 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2945 return -EINVAL;
2946
2947 if (ecmd->tx_coalesce_usecs == 0)
2948 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2949 else {
2950 sky2_write32(hw, STAT_TX_TIMER_INI,
2951 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2952 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2953 }
2954 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2955
2956 if (ecmd->rx_coalesce_usecs == 0)
2957 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2958 else {
2959 sky2_write32(hw, STAT_LEV_TIMER_INI,
2960 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2961 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2962 }
2963 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2964
2965 if (ecmd->rx_coalesce_usecs_irq == 0)
2966 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2967 else {
d28d4870 2968 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2969 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2970 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2971 }
2972 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2973 return 0;
2974}
2975
793b883e
SH		 2976static void sky2_get_ringparam(struct net_device *dev,
2977 struct ethtool_ringparam *ering)
2978{
2979 struct sky2_port *sky2 = netdev_priv(dev);
2980
2981 ering->rx_max_pending = RX_MAX_PENDING;
2982 ering->rx_mini_max_pending = 0;
2983 ering->rx_jumbo_max_pending = 0;
2984 ering->tx_max_pending = TX_RING_SIZE - 1;
2985
2986 ering->rx_pending = sky2->rx_pending;
2987 ering->rx_mini_pending = 0;
2988 ering->rx_jumbo_pending = 0;
2989 ering->tx_pending = sky2->tx_pending;
2990}
2991
2992static int sky2_set_ringparam(struct net_device *dev,
2993 struct ethtool_ringparam *ering)
2994{
2995 struct sky2_port *sky2 = netdev_priv(dev);
2996 int err = 0;
2997
2998 if (ering->rx_pending > RX_MAX_PENDING ||
2999 ering->rx_pending < 8 ||
3000 ering->tx_pending < MAX_SKB_TX_LE ||
3001 ering->tx_pending > TX_RING_SIZE - 1)
3002 return -EINVAL;
3003
3004 if (netif_running(dev))
3005 sky2_down(dev);
3006
3007 sky2->rx_pending = ering->rx_pending;
3008 sky2->tx_pending = ering->tx_pending;
3009
1b537565 3010 if (netif_running(dev)) {
793b883e 3011 err = sky2_up(dev);
1b537565
SH		 3012 if (err)
3013 dev_close(dev);
6ed995bb
SH		 3014 else
3015 sky2_set_multicast(dev);
1b537565 3016 }
793b883e
SH		 3017
3018 return err;
3019}
3020
793b883e
SH		 3021static int sky2_get_regs_len(struct net_device *dev)
3022{
6e4cbb34 3023 return 0x4000;
793b883e
SH		 3024}
3025
3026/*
3027 * Returns copy of control register region
6e4cbb34 3028 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3029 */
3030static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3031 void *p)
3032{
3033 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3034 const void __iomem *io = sky2->hw->regs;
793b883e 3035
6e4cbb34 3036 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3037 regs->version = 1;
6e4cbb34 3038 memset(p, 0, regs->len);
793b883e 3039
6e4cbb34
SH		 3040 memcpy_fromio(p, io, B3_RAM_ADDR);
3041
3042 memcpy_fromio(p + B3_RI_WTO_R1,
3043 io + B3_RI_WTO_R1,
3044 regs->len - B3_RI_WTO_R1);
793b883e 3045}
cd28ab6a 3046
7282d491 3047static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3048 .get_settings = sky2_get_settings,
3049 .set_settings = sky2_set_settings,
3050 .get_drvinfo = sky2_get_drvinfo,
3051 .get_msglevel = sky2_get_msglevel,
3052 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3053 .nway_reset = sky2_nway_reset,
793b883e
SH		 3054 .get_regs_len = sky2_get_regs_len,
3055 .get_regs = sky2_get_regs,
3056 .get_link = ethtool_op_get_link,
3057 .get_sg = ethtool_op_get_sg,
3058 .set_sg = ethtool_op_set_sg,
3059 .get_tx_csum = ethtool_op_get_tx_csum,
3060 .set_tx_csum = ethtool_op_set_tx_csum,
3061 .get_tso = ethtool_op_get_tso,
3062 .set_tso = ethtool_op_set_tso,
3063 .get_rx_csum = sky2_get_rx_csum,
3064 .set_rx_csum = sky2_set_rx_csum,
3065 .get_strings = sky2_get_strings,
fb17358f
SH		 3066 .get_coalesce = sky2_get_coalesce,
3067 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3068 .get_ringparam = sky2_get_ringparam,
3069 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3070 .get_pauseparam = sky2_get_pauseparam,
3071 .set_pauseparam = sky2_set_pauseparam,
793b883e 3072 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3073 .get_stats_count = sky2_get_stats_count,
3074 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3075 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3076};
3077
3078/* Initialize network device */
3079static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3080 unsigned port, int highmem)
3081{
3082 struct sky2_port *sky2;
3083 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3084
3085 if (!dev) {
3086 printk(KERN_ERR "sky2 etherdev alloc failed");
3087 return NULL;
3088 }
3089
3090 SET_MODULE_OWNER(dev);
3091 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3092 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3093 dev->open = sky2_up;
3094 dev->stop = sky2_down;
ef743d33 3095 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3096 dev->hard_start_xmit = sky2_xmit_frame;
3097 dev->get_stats = sky2_get_stats;
3098 dev->set_multicast_list = sky2_set_multicast;
3099 dev->set_mac_address = sky2_set_mac_address;
3100 dev->change_mtu = sky2_change_mtu;
3101 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3102 dev->tx_timeout = sky2_tx_timeout;
3103 dev->watchdog_timeo = TX_WATCHDOG;
3104 if (port == 0)
3105 dev->poll = sky2_poll;
3106 dev->weight = NAPI_WEIGHT;
3107#ifdef CONFIG_NET_POLL_CONTROLLER
3108 dev->poll_controller = sky2_netpoll;
3109#endif
cd28ab6a
SH		 3110
3111 sky2 = netdev_priv(dev);
3112 sky2->netdev = dev;
3113 sky2->hw = hw;
3114 sky2->msg_enable = netif_msg_init(debug, default_msg);
3115
cd28ab6a
SH		 3116 /* Auto speed and flow control */
3117 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3118 sky2->tx_pause = 1;
cd28ab6a
SH		 3119 sky2->rx_pause = 1;
3120 sky2->duplex = -1;
3121 sky2->speed = -1;
3122 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3123 sky2->rx_csum = 1;
75d070c5 3124
e07b1aa8 3125 spin_lock_init(&sky2->phy_lock);
793b883e 3126 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3127 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3128 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3129
3130 hw->dev[port] = dev;
3131
3132 sky2->port = port;
3133
5a5b1ea0 3134 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3135 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3136 if (highmem)
3137 dev->features |= NETIF_F_HIGHDMA;
793b883e 3138 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3139
d1f13708 3140#ifdef SKY2_VLAN_TAG_USED
3141 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3142 dev->vlan_rx_register = sky2_vlan_rx_register;
3143 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3144#endif
3145
cd28ab6a 3146 /* read the mac address */
793b883e 3147 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3148 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3149
3150 /* device is off until link detection */
3151 netif_carrier_off(dev);
3152 netif_stop_queue(dev);
3153
3154 return dev;
3155}
3156
28bd181a 3157static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3158{
3159 const struct sky2_port *sky2 = netdev_priv(dev);
3160
3161 if (netif_msg_probe(sky2))
3162 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3163 dev->name,
3164 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3165 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3166}
3167
fb2690a9
SH		 3168/* Handle software interrupt used during MSI test */
3169static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3170 struct pt_regs *regs)
3171{
3172 struct sky2_hw *hw = dev_id;
3173 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3174
3175 if (status == 0)
3176 return IRQ_NONE;
3177
3178 if (status & Y2_IS_IRQ_SW) {
3179 hw->msi_detected = 1;
3180 wake_up(&hw->msi_wait);
3181 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3182 }
3183 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3184
3185 return IRQ_HANDLED;
3186}
3187
3188/* Test interrupt path by forcing a a software IRQ */
3189static int __devinit sky2_test_msi(struct sky2_hw *hw)
3190{
3191 struct pci_dev *pdev = hw->pdev;
3192 int err;
3193
bb507fe1 3194 init_waitqueue_head (&hw->msi_wait);
3195
fb2690a9
SH		 3196 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3197
1fb9df5d 3198 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3199 if (err) {
3200 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3201 pci_name(pdev), pdev->irq);
3202 return err;
3203 }
3204
fb2690a9 3205 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3206 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3207
3208 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3209
3210 if (!hw->msi_detected) {
3211 /* MSI test failed, go back to INTx mode */
3212 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3213 "switching to INTx mode. Please report this failure to "
3214 "the PCI maintainer and include system chipset information.\n",
3215 pci_name(pdev));
3216
3217 err = -EOPNOTSUPP;
3218 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3219 }
3220
3221 sky2_write32(hw, B0_IMSK, 0);
3222
3223 free_irq(pdev->irq, hw);
3224
3225 return err;
3226}
3227
cd28ab6a
SH		 3228static int __devinit sky2_probe(struct pci_dev *pdev,
3229 const struct pci_device_id *ent)
3230{
793b883e 3231 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3232 struct sky2_hw *hw;
5afa0a9c 3233 int err, pm_cap, using_dac = 0;
cd28ab6a 3234
793b883e
SH		 3235 err = pci_enable_device(pdev);
3236 if (err) {
cd28ab6a
SH		 3237 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3238 pci_name(pdev));
3239 goto err_out;
3240 }
3241
793b883e
SH		 3242 err = pci_request_regions(pdev, DRV_NAME);
3243 if (err) {
cd28ab6a
SH		 3244 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3245 pci_name(pdev));
793b883e 3246 goto err_out;
cd28ab6a
SH		 3247 }
3248
3249 pci_set_master(pdev);
3250
5afa0a9c 3251 /* Find power-management capability. */
3252 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3253 if (pm_cap == 0) {
3254 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3255 "aborting.\n");
3256 err = -EIO;
3257 goto err_out_free_regions;
3258 }
3259
d1f3d4dd
SH		 3260 if (sizeof(dma_addr_t) > sizeof(u32) &&
3261 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3262 using_dac = 1;
3263 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3264 if (err < 0) {
3265 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3266 "for consistent allocations\n", pci_name(pdev));
3267 goto err_out_free_regions;
3268 }
cd28ab6a 3269
d1f3d4dd 3270 } else {
cd28ab6a
SH		 3271 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3272 if (err) {
3273 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3274 pci_name(pdev));
3275 goto err_out_free_regions;
3276 }
3277 }
d1f3d4dd 3278
cd28ab6a 3279 err = -ENOMEM;
6aad85d6 3280 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3281 if (!hw) {
3282 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3283 pci_name(pdev));
3284 goto err_out_free_regions;
3285 }
3286
cd28ab6a 3287 hw->pdev = pdev;
cd28ab6a
SH		 3288
3289 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3290 if (!hw->regs) {
3291 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3292 pci_name(pdev));
3293 goto err_out_free_hw;
3294 }
5afa0a9c 3295 hw->pm_cap = pm_cap;
cd28ab6a 3296
56a645cc 3297#ifdef __BIG_ENDIAN
f65b138c
SH		 3298 /* The sk98lin vendor driver uses hardware byte swapping but
3299 * this driver uses software swapping.
3300 */
56a645cc
SH		 3301 {
3302 u32 reg;
56a645cc 3303 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3304 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3305 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3306 }
3307#endif
3308
08c06d8a
SH		 3309 /* ring for status responses */
3310 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3311 &hw->st_dma);
3312 if (!hw->st_le)
3313 goto err_out_iounmap;
3314
cd28ab6a
SH		 3315 err = sky2_reset(hw);
3316 if (err)
793b883e 3317 goto err_out_iounmap;
cd28ab6a 3318
7c7459d1
GKH		 3319 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3320 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3321 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3322 hw->chip_id, hw->chip_rev);
cd28ab6a 3323
793b883e
SH		 3324 dev = sky2_init_netdev(hw, 0, using_dac);
3325 if (!dev)
cd28ab6a
SH		 3326 goto err_out_free_pci;
3327
9fa1b1f3
SH		 3328 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3329 err = sky2_test_msi(hw);
3330 if (err == -EOPNOTSUPP)
3331 pci_disable_msi(pdev);
3332 else if (err)
3333 goto err_out_free_netdev;
3334 }
3335
793b883e
SH		 3336 err = register_netdev(dev);
3337 if (err) {
cd28ab6a
SH		 3338 printk(KERN_ERR PFX "%s: cannot register net device\n",
3339 pci_name(pdev));
3340 goto err_out_free_netdev;
3341 }
3342
9fa1b1f3
SH		 3343 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
3344 if (err) {
3345 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3346 pci_name(pdev), pdev->irq);
3347 goto err_out_unregister;
3348 }
3349 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3350
cd28ab6a
SH		 3351 sky2_show_addr(dev);
3352
3353 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3354 if (register_netdev(dev1) == 0)
3355 sky2_show_addr(dev1);
3356 else {
3357 /* Failure to register second port need not be fatal */
793b883e
SH		 3358 printk(KERN_WARNING PFX
3359 "register of second port failed\n");
cd28ab6a
SH		 3360 hw->dev[1] = NULL;
3361 free_netdev(dev1);
3362 }
3363 }
3364
01bd7564 3365 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3366 sky2_idle_start(hw);
d27ed387 3367
793b883e
SH		 3368 pci_set_drvdata(pdev, hw);
3369
cd28ab6a
SH		 3370 return 0;
3371
793b883e 3372err_out_unregister:
fb2690a9 3373 pci_disable_msi(pdev);
793b883e 3374 unregister_netdev(dev);
cd28ab6a
SH		 3375err_out_free_netdev:
3376 free_netdev(dev);
cd28ab6a 3377err_out_free_pci:
793b883e 3378 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3379 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3380err_out_iounmap:
3381 iounmap(hw->regs);
3382err_out_free_hw:
3383 kfree(hw);
3384err_out_free_regions:
3385 pci_release_regions(pdev);
cd28ab6a 3386 pci_disable_device(pdev);
cd28ab6a
SH		 3387err_out:
3388 return err;
3389}
3390
3391static void __devexit sky2_remove(struct pci_dev *pdev)
3392{
793b883e 3393 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3394 struct net_device *dev0, *dev1;
3395
793b883e 3396 if (!hw)
cd28ab6a
SH		 3397 return;
3398
d27ed387
SH		 3399 del_timer_sync(&hw->idle_timer);
3400
3401 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3402 synchronize_irq(hw->pdev->irq);
3403
cd28ab6a 3404 dev0 = hw->dev[0];
793b883e
SH		 3405 dev1 = hw->dev[1];
3406 if (dev1)
3407 unregister_netdev(dev1);
cd28ab6a
SH		 3408 unregister_netdev(dev0);
3409
5afa0a9c 3410 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3411 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3412 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3413 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3414
3415 free_irq(pdev->irq, hw);
fb2690a9 3416 pci_disable_msi(pdev);
793b883e 3417 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3418 pci_release_regions(pdev);
3419 pci_disable_device(pdev);
793b883e 3420
cd28ab6a
SH		 3421 if (dev1)
3422 free_netdev(dev1);
3423 free_netdev(dev0);
3424 iounmap(hw->regs);
3425 kfree(hw);
5afa0a9c 3426
cd28ab6a
SH		 3427 pci_set_drvdata(pdev, NULL);
3428}
3429
3430#ifdef CONFIG_PM
3431static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3432{
793b883e 3433 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3434 int i;
2ccc99b7
SH		 3435 pci_power_t pstate = pci_choose_state(pdev, state);
3436
3437 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3438 return -EINVAL;
cd28ab6a 3439
eb35cf60 3440 del_timer_sync(&hw->idle_timer);
6a5706b9 3441 netif_poll_disable(hw->dev[0]);
eb35cf60 3442
f05267e7 3443 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3444 struct net_device *dev = hw->dev[i];
3445
6a5706b9 3446 if (netif_running(dev)) {
5afa0a9c 3447 sky2_down(dev);
cd28ab6a 3448 netif_device_detach(dev);
cd28ab6a
SH		 3449 }
3450 }
3451
8ab8fca2 3452 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3453 pci_save_state(pdev);
2ccc99b7
SH		 3454 sky2_set_power_state(hw, pstate);
3455 return 0;
cd28ab6a
SH		 3456}
3457
3458static int sky2_resume(struct pci_dev *pdev)
3459{
793b883e 3460 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3461 int i, err;
cd28ab6a 3462
cd28ab6a
SH		 3463 pci_restore_state(pdev);
3464 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3465 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3466
08c06d8a
SH		 3467 err = sky2_reset(hw);
3468 if (err)
3469 goto out;
cd28ab6a 3470
8ab8fca2
SH		 3471 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3472
f05267e7 3473 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3474 struct net_device *dev = hw->dev[i];
6a5706b9 3475 if (netif_running(dev)) {
08c06d8a 3476 netif_device_attach(dev);
88d11360 3477
08c06d8a
SH		 3478 err = sky2_up(dev);
3479 if (err) {
3480 printk(KERN_ERR PFX "%s: could not up: %d\n",
3481 dev->name, err);
3482 dev_close(dev);
eb35cf60 3483 goto out;
5afa0a9c 3484 }
cd28ab6a
SH		 3485 }
3486 }
eb35cf60 3487
6a5706b9 3488 netif_poll_enable(hw->dev[0]);
eb35cf60 3489 sky2_idle_start(hw);
08c06d8a
SH		 3490out:
3491 return err;
cd28ab6a
SH		 3492}
3493#endif
3494
3495static struct pci_driver sky2_driver = {
793b883e
SH		 3496 .name = DRV_NAME,
3497 .id_table = sky2_id_table,
3498 .probe = sky2_probe,
3499 .remove = __devexit_p(sky2_remove),
cd28ab6a 3500#ifdef CONFIG_PM
793b883e
SH		 3501 .suspend = sky2_suspend,
3502 .resume = sky2_resume,
cd28ab6a
SH		 3503#endif
3504};
3505
3506static int __init sky2_init_module(void)
3507{
50241c4c 3508 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3509}
3510
3511static void __exit sky2_cleanup_module(void)
3512{
3513 pci_unregister_driver(&sky2_driver);
3514}
3515
3516module_init(sky2_init_module);
3517module_exit(sky2_cleanup_module);
3518
3519MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3520MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3521MODULE_LICENSE("GPL");
5f4f9dc1 3522MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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