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[PATCH] sky2: tx pause bug fix
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
e981d47b 53#define DRV_VERSION "1.7"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
13210ce5 63#define RX_LE_SIZE 512
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
22e11703 68#define RX_BUF_WRITE 16
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
cd28ab6a
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
2f4a66ad 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
cd28ab6a
SH		 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
2f4a66ad 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
cd28ab6a
SH		 132 { 0 }
133};
793b883e 134
cd28ab6a
SH		 135MODULE_DEVICE_TABLE(pci, sky2_id_table);
136
137/* Avoid conditionals by using array */
138static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
139static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 140static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 141
92f965e8
SH		 142/* This driver supports yukon2 chipset only */
143static const char *yukon2_name[] = {
144 "XL", /* 0xb3 */
145 "EC Ultra", /* 0xb4 */
146 "UNKNOWN", /* 0xb5 */
147 "EC", /* 0xb6 */
148 "FE", /* 0xb7 */
793b883e
SH		 149};
150
793b883e 151/* Access to external PHY */
ef743d33 152static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 153{
154 int i;
155
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159
160 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 161 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 162 return 0;
793b883e 163 udelay(1);
cd28ab6a 164 }
ef743d33 165
793b883e 166 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 167 return -ETIMEDOUT;
cd28ab6a
SH		 168}
169
ef743d33 170static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 171{
172 int i;
173
793b883e 174 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 175 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
176
177 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 178 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
179 *val = gma_read16(hw, port, GM_SMI_DATA);
180 return 0;
181 }
182
793b883e 183 udelay(1);
cd28ab6a
SH		 184 }
185
ef743d33 186 return -ETIMEDOUT;
187}
188
189static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
190{
191 u16 v;
192
193 if (__gm_phy_read(hw, port, reg, &v) != 0)
194 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
195 return v;
cd28ab6a
SH		 196}
197
2ccc99b7 198static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c 199{
200 u16 power_control;
5afa0a9c 201 int vaux;
5afa0a9c 202
203 pr_debug("sky2_set_power_state %d\n", state);
204 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
205
56a645cc 206 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 207 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c 208 (power_control & PCI_PM_CAP_PME_D3cold);
209
56a645cc 210 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c 211
212 power_control |= PCI_PM_CTRL_PME_STATUS;
213 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
214
215 switch (state) {
216 case PCI_D0:
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
220
221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
223
224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
232
977bdf06 233 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb 234 u32 reg1;
235
56a645cc
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
237 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 238 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 239 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
240 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 241 }
242
5afa0a9c 243 break;
244
245 case PCI_D3hot:
246 case PCI_D3cold:
5afa0a9c 247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
248 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
249 else
250 /* enable bits are inverted */
251 sky2_write8(hw, B2_Y2_CLK_GATE,
252 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
253 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
254 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
255
256 /* switch power to VAUX */
257 if (vaux && state != PCI_D3cold)
258 sky2_write8(hw, B0_POWER_CTRL,
259 (PC_VAUX_ENA | PC_VCC_ENA |
260 PC_VAUX_ON | PC_VCC_OFF));
261 break;
262 default:
263 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c 264 }
265
56a645cc 266 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 267 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c 268}
269
d3bcfbeb 270static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 271{
272 u16 reg;
273
274 /* disable all GMAC IRQ's */
275 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
276 /* disable PHY IRQs */
277 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 278
cd28ab6a
SH		 279 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
280 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
281 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
282 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
283
284 reg = gma_read16(hw, port, GM_RX_CTRL);
285 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
286 gma_write16(hw, port, GM_RX_CTRL, reg);
287}
288
289static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
290{
291 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 292 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 293
ed6d32c7 294 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 295 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 296 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
297
298 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 299 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 300 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
301
302 if (hw->chip_id == CHIP_ID_YUKON_EC)
303 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
304 else
305 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
306
307 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
308 }
309
310 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
311 if (hw->copper) {
312 if (hw->chip_id == CHIP_ID_YUKON_FE) {
313 /* enable automatic crossover */
314 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
315 } else {
316 /* disable energy detect */
317 ctrl &= ~PHY_M_PC_EN_DET_MSK;
318
319 /* enable automatic crossover */
320 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
321
322 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 323 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 324 ctrl &= ~PHY_M_PC_DSC_MSK;
325 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
326 }
327 }
328 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
329 } else {
330 /* workaround for deviation #4.88 (CRC errors) */
331 /* disable Automatic Crossover */
332
333 ctrl &= ~PHY_M_PC_MDIX_MSK;
334 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
335
336 if (hw->chip_id == CHIP_ID_YUKON_XL) {
337 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
338 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
339 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
340 ctrl &= ~PHY_M_MAC_MD_MSK;
341 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
343
344 /* select page 1 to access Fiber registers */
345 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
346 }
cd28ab6a
SH		 347 }
348
349 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
350 if (sky2->autoneg == AUTONEG_DISABLE)
351 ctrl &= ~PHY_CT_ANE;
352 else
353 ctrl |= PHY_CT_ANE;
354
355 ctrl |= PHY_CT_RESET;
356 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
357
358 ctrl = 0;
359 ct1000 = 0;
360 adv = PHY_AN_CSMA;
2eaba1a2 361 reg = 0;
cd28ab6a
SH		 362
363 if (sky2->autoneg == AUTONEG_ENABLE) {
364 if (hw->copper) {
365 if (sky2->advertising & ADVERTISED_1000baseT_Full)
366 ct1000 |= PHY_M_1000C_AFD;
367 if (sky2->advertising & ADVERTISED_1000baseT_Half)
368 ct1000 |= PHY_M_1000C_AHD;
369 if (sky2->advertising & ADVERTISED_100baseT_Full)
370 adv |= PHY_M_AN_100_FD;
371 if (sky2->advertising & ADVERTISED_100baseT_Half)
372 adv |= PHY_M_AN_100_HD;
373 if (sky2->advertising & ADVERTISED_10baseT_Full)
374 adv |= PHY_M_AN_10_FD;
375 if (sky2->advertising & ADVERTISED_10baseT_Half)
376 adv |= PHY_M_AN_10_HD;
793b883e 377 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 378 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
379
380 /* Set Flow-control capabilities */
381 if (sky2->tx_pause && sky2->rx_pause)
793b883e 382 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 383 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 384 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 385 else if (!sky2->rx_pause && sky2->tx_pause)
386 adv |= PHY_AN_PAUSE_ASYM; /* local */
387
388 /* Restart Auto-negotiation */
389 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
390 } else {
391 /* forced speed/duplex settings */
392 ct1000 = PHY_M_1000C_MSE;
393
2eaba1a2
SH		 394 /* Disable auto update for duplex flow control and speed */
395 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 396
397 switch (sky2->speed) {
398 case SPEED_1000:
399 ctrl |= PHY_CT_SP1000;
2eaba1a2 400 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 401 break;
402 case SPEED_100:
403 ctrl |= PHY_CT_SP100;
2eaba1a2 404 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 405 break;
406 }
407
2eaba1a2
SH		 408 if (sky2->duplex == DUPLEX_FULL) {
409 reg |= GM_GPCR_DUP_FULL;
410 ctrl |= PHY_CT_DUP_MD;
411 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
412 /* Turn off flow control for 10/100mbps */
413 sky2->rx_pause = 0;
414 sky2->tx_pause = 0;
415 }
416
417 if (!sky2->rx_pause)
418 reg |= GM_GPCR_FC_RX_DIS;
419
420 if (!sky2->tx_pause)
421 reg |= GM_GPCR_FC_TX_DIS;
422
423 /* Forward pause packets to GMAC? */
424 if (sky2->tx_pause || sky2->rx_pause)
425 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
426 else
427 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
428
cd28ab6a
SH		 429 ctrl |= PHY_CT_RESET;
430 }
431
2eaba1a2
SH		 432 gma_write16(hw, port, GM_GP_CTRL, reg);
433
cd28ab6a
SH		 434 if (hw->chip_id != CHIP_ID_YUKON_FE)
435 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
436
437 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
438 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
439
440 /* Setup Phy LED's */
441 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
442 ledover = 0;
443
444 switch (hw->chip_id) {
445 case CHIP_ID_YUKON_FE:
446 /* on 88E3082 these bits are at 11..9 (shifted left) */
447 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
448
449 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
450
451 /* delete ACT LED control bits */
452 ctrl &= ~PHY_M_FELP_LED1_MSK;
453 /* change ACT LED control to blink mode */
454 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
455 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
456 break;
457
458 case CHIP_ID_YUKON_XL:
793b883e 459 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 460
461 /* select page 3 to access LED control register */
462 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
463
464 /* set LED Function Control register */
ed6d32c7
SH		 465 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
466 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
467 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
468 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
469 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 470
471 /* set Polarity Control register */
472 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 473 (PHY_M_POLC_LS1_P_MIX(4) |
474 PHY_M_POLC_IS0_P_MIX(4) |
475 PHY_M_POLC_LOS_CTRL(2) |
476 PHY_M_POLC_INIT_CTRL(2) |
477 PHY_M_POLC_STA1_CTRL(2) |
478 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 479
480 /* restore page register */
793b883e 481 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 482 break;
ed6d32c7
SH		 483 case CHIP_ID_YUKON_EC_U:
484 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
485
486 /* select page 3 to access LED control register */
487 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
488
489 /* set LED Function Control register */
490 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
491 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
492 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
493 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
494 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
495
496 /* set Blink Rate in LED Timer Control Register */
497 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
498 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
499 /* restore page register */
500 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
501 break;
cd28ab6a
SH		 502
503 default:
504 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
505 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
506 /* turn off the Rx LED (LED_RX) */
507 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
508 }
509
ed6d32c7 510 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 511 /* apply fixes in PHY AFE */
ed6d32c7
SH		 512 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
514
977bdf06 515 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 516 gm_phy_write(hw, port, 0x18, 0xaa99);
517 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 518
977bdf06 519 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 520 gm_phy_write(hw, port, 0x18, 0xa204);
521 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 522
523 /* set page register to 0 */
ed6d32c7 524 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 525 } else {
526 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 527
977bdf06
SH		 528 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
529 /* turn on 100 Mbps LED (LED_LINK100) */
530 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
531 }
cd28ab6a 532
977bdf06
SH		 533 if (ledover)
534 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
535
536 }
2eaba1a2 537
d571b694 538 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 539 if (sky2->autoneg == AUTONEG_ENABLE)
540 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
541 else
542 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
543}
544
d3bcfbeb 545static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
546{
547 u32 reg1;
548 static const u32 phy_power[]
549 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
550
551 /* looks like this XL is back asswards .. */
552 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
553 onoff = !onoff;
554
555 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
556
557 if (onoff)
558 /* Turn off phy power saving */
559 reg1 &= ~phy_power[port];
560 else
561 reg1 |= phy_power[port];
562
563 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 564 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 565 udelay(100);
566}
567
1b537565
SH		 568/* Force a renegotiation */
569static void sky2_phy_reinit(struct sky2_port *sky2)
570{
e07b1aa8 571 spin_lock_bh(&sky2->phy_lock);
1b537565 572 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 573 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 574}
575
cd28ab6a
SH		 576static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
577{
578 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
579 u16 reg;
580 int i;
581 const u8 *addr = hw->dev[port]->dev_addr;
582
42eeea01 583 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
584 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 585
586 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
587
793b883e 588 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 589 /* WA DEV_472 -- looks like crossed wires on port 2 */
590 /* clear GMAC 1 Control reset */
591 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
592 do {
593 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
594 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
595 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
596 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
597 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
598 }
599
793b883e 600 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 601
2eaba1a2
SH		 602 /* Enable Transmit FIFO Underrun */
603 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
604
e07b1aa8 605 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 606 sky2_phy_init(hw, port);
e07b1aa8 607 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 608
609 /* MIB clear */
610 reg = gma_read16(hw, port, GM_PHY_ADDR);
611 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
612
43f2f104
SH		 613 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
614 gma_read16(hw, port, i);
cd28ab6a
SH		 615 gma_write16(hw, port, GM_PHY_ADDR, reg);
616
617 /* transmit control */
618 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
619
620 /* receive control reg: unicast + multicast + no FCS */
621 gma_write16(hw, port, GM_RX_CTRL,
793b883e 622 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 623
624 /* transmit flow control */
625 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
626
627 /* transmit parameter */
628 gma_write16(hw, port, GM_TX_PARAM,
629 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
630 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
631 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
632 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
633
634 /* serial mode register */
635 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 636 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 637
6b1a3aef 638 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 639 reg |= GM_SMOD_JUMBO_ENA;
640
641 gma_write16(hw, port, GM_SERIAL_MODE, reg);
642
cd28ab6a
SH		 643 /* virtual address for data */
644 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
645
793b883e
SH		 646 /* physical address: used for pause frames */
647 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
648
649 /* ignore counter overflows */
cd28ab6a
SH		 650 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
651 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
652 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
653
654 /* Configure Rx MAC FIFO */
655 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 656 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
657 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 658
d571b694 659 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 660 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 661
793b883e
SH		 662 /* Set threshold to 0xa (64 bytes)
663 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 664 */
665 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
666
667 /* Configure Tx MAC FIFO */
668 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
669 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 670
671 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
672 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
673 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
674 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
675 /* set Tx GMAC FIFO Almost Empty Threshold */
676 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
677 /* Disable Store & Forward mode for TX */
678 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
679 }
680 }
681
cd28ab6a
SH		 682}
683
1c28f6ba
SH		 684/* Assign Ram Buffer allocation.
685 * start and end are in units of 4k bytes
686 * ram registers are in units of 64bit words
687 */
688static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 689{
1c28f6ba 690 u32 start, end;
cd28ab6a 691
1c28f6ba
SH		 692 start = startk * 4096/8;
693 end = (endk * 4096/8) - 1;
793b883e 694
cd28ab6a
SH		 695 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
696 sky2_write32(hw, RB_ADDR(q, RB_START), start);
697 sky2_write32(hw, RB_ADDR(q, RB_END), end);
698 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
699 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
700
701 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 702 u32 space = (endk - startk) * 4096/8;
703 u32 tp = space - space/4;
793b883e 704
1c28f6ba
SH		 705 /* On receive queue's set the thresholds
706 * give receiver priority when > 3/4 full
707 * send pause when down to 2K
708 */
709 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
710 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 711
1c28f6ba
SH		 712 tp = space - 2048/8;
713 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
714 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 715 } else {
716 /* Enable store & forward on Tx queue's because
717 * Tx FIFO is only 1K on Yukon
718 */
719 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
720 }
721
722 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 723 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 724}
725
cd28ab6a 726/* Setup Bus Memory Interface */
af4ed7e6 727static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 728{
729 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
730 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
731 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 732 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 733}
734
cd28ab6a
SH		 735/* Setup prefetch unit registers. This is the interface between
736 * hardware and driver list elements
737 */
8cc048e3 738static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 739 u64 addr, u32 last)
740{
cd28ab6a
SH		 741 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
742 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
744 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
745 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
746 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 747
748 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 749}
750
793b883e
SH		 751static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
752{
753 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
754
cb5d9547 755 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 756 return le;
757}
cd28ab6a 758
290d4de5
SH		 759/* Update chip's next pointer */
760static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 761{
98232f85 762 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 763 wmb();
98232f85 764 sky2_write16(hw, q, idx);
765 sky2_read16(hw, q);
cd28ab6a
SH		 766}
767
793b883e 768
cd28ab6a
SH		 769static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
770{
771 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 772 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 773 return le;
774}
775
a018e330 776/* Return high part of DMA address (could be 32 or 64 bit) */
777static inline u32 high32(dma_addr_t a)
778{
a036119f 779 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330 780}
781
793b883e 782/* Build description to hardware about buffer */
28bd181a 783static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 784{
785 struct sky2_rx_le *le;
734d1868
SH		 786 u32 hi = high32(map);
787 u16 len = sky2->rx_bufsize;
cd28ab6a 788
793b883e 789 if (sky2->rx_addr64 != hi) {
cd28ab6a 790 le = sky2_next_rx(sky2);
793b883e 791 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 792 le->ctrl = 0;
793 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 794 sky2->rx_addr64 = high32(map + len);
cd28ab6a 795 }
793b883e 796
cd28ab6a 797 le = sky2_next_rx(sky2);
734d1868
SH		 798 le->addr = cpu_to_le32((u32) map);
799 le->length = cpu_to_le16(len);
cd28ab6a
SH		 800 le->ctrl = 0;
801 le->opcode = OP_PACKET | HW_OWNER;
802}
803
793b883e 804
cd28ab6a
SH		 805/* Tell chip where to start receive checksum.
806 * Actually has two checksums, but set both same to avoid possible byte
807 * order problems.
808 */
793b883e 809static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 810{
811 struct sky2_rx_le *le;
812
cd28ab6a 813 le = sky2_next_rx(sky2);
793b883e 814 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 815 le->ctrl = 0;
816 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 817
793b883e
SH		 818 sky2_write32(sky2->hw,
819 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
820 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 821
822}
823
6b1a3aef 824/*
825 * The RX Stop command will not work for Yukon-2 if the BMU does not
826 * reach the end of packet and since we can't make sure that we have
827 * incoming data, we must reset the BMU while it is not doing a DMA
828 * transfer. Since it is possible that the RX path is still active,
829 * the RX RAM buffer will be stopped first, so any possible incoming
830 * data will not trigger a DMA. After the RAM buffer is stopped, the
831 * BMU is polled until any DMA in progress is ended and only then it
832 * will be reset.
833 */
834static void sky2_rx_stop(struct sky2_port *sky2)
835{
836 struct sky2_hw *hw = sky2->hw;
837 unsigned rxq = rxqaddr[sky2->port];
838 int i;
839
840 /* disable the RAM Buffer receive queue */
841 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
842
843 for (i = 0; i < 0xffff; i++)
844 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
845 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
846 goto stopped;
847
848 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
849 sky2->netdev->name);
850stopped:
851 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
852
853 /* reset the Rx prefetch unit */
854 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
855}
793b883e 856
d571b694 857/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 858static void sky2_rx_clean(struct sky2_port *sky2)
859{
860 unsigned i;
861
862 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 863 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 864 struct ring_info *re = sky2->rx_ring + i;
865
866 if (re->skb) {
793b883e 867 pci_unmap_single(sky2->hw->pdev,
734d1868 868 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 869 PCI_DMA_FROMDEVICE);
870 kfree_skb(re->skb);
871 re->skb = NULL;
872 }
873 }
874}
875
ef743d33 876/* Basic MII support */
877static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
878{
879 struct mii_ioctl_data *data = if_mii(ifr);
880 struct sky2_port *sky2 = netdev_priv(dev);
881 struct sky2_hw *hw = sky2->hw;
882 int err = -EOPNOTSUPP;
883
884 if (!netif_running(dev))
885 return -ENODEV; /* Phy still in reset */
886
d89e1343 887 switch (cmd) {
ef743d33 888 case SIOCGMIIPHY:
889 data->phy_id = PHY_ADDR_MARV;
890
891 /* fallthru */
892 case SIOCGMIIREG: {
893 u16 val = 0;
91c86df5 894
e07b1aa8 895 spin_lock_bh(&sky2->phy_lock);
ef743d33 896 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 897 spin_unlock_bh(&sky2->phy_lock);
91c86df5 898
ef743d33 899 data->val_out = val;
900 break;
901 }
902
903 case SIOCSMIIREG:
904 if (!capable(CAP_NET_ADMIN))
905 return -EPERM;
906
e07b1aa8 907 spin_lock_bh(&sky2->phy_lock);
ef743d33 908 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
909 data->val_in);
e07b1aa8 910 spin_unlock_bh(&sky2->phy_lock);
ef743d33 911 break;
912 }
913 return err;
914}
915
d1f13708 916#ifdef SKY2_VLAN_TAG_USED
917static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
918{
919 struct sky2_port *sky2 = netdev_priv(dev);
920 struct sky2_hw *hw = sky2->hw;
921 u16 port = sky2->port;
d1f13708 922
302d1252 923 spin_lock_bh(&sky2->tx_lock);
d1f13708 924
925 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
926 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
927 sky2->vlgrp = grp;
928
302d1252 929 spin_unlock_bh(&sky2->tx_lock);
d1f13708 930}
931
932static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
933{
934 struct sky2_port *sky2 = netdev_priv(dev);
935 struct sky2_hw *hw = sky2->hw;
936 u16 port = sky2->port;
d1f13708 937
302d1252 938 spin_lock_bh(&sky2->tx_lock);
d1f13708 939
940 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
941 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
942 if (sky2->vlgrp)
943 sky2->vlgrp->vlan_devices[vid] = NULL;
944
302d1252 945 spin_unlock_bh(&sky2->tx_lock);
d1f13708 946}
947#endif
948
82788c7a
SH		 949/*
950 * It appears the hardware has a bug in the FIFO logic that
951 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 952 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
953 * aligned except if slab debugging is enabled.
82788c7a 954 */
497d7c86 955static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
956 unsigned int length,
957 gfp_t gfp_mask)
82788c7a
SH		 958{
959 struct sk_buff *skb;
960
497d7c86 961 skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
82788c7a
SH		 962 if (likely(skb)) {
963 unsigned long p = (unsigned long) skb->data;
4a15d56f 964 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 965 }
966
967 return skb;
968}
969
cd28ab6a
SH		 970/*
971 * Allocate and setup receiver buffer pool.
972 * In case of 64 bit dma, there are 2X as many list elements
973 * available as ring entries
974 * and need to reserve one list element so we don't wrap around.
975 */
6b1a3aef 976static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 977{
6b1a3aef 978 struct sky2_hw *hw = sky2->hw;
6b1a3aef 979 unsigned rxq = rxqaddr[sky2->port];
980 int i;
a1433ac4 981 unsigned thresh;
cd28ab6a 982
6b1a3aef 983 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 984 sky2_qset(hw, rxq);
977bdf06
SH		 985
986 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
987 /* MAC Rx RAM Read is controlled by hardware */
988 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
989 }
990
6b1a3aef 991 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
992
993 rx_set_checksum(sky2);
793b883e 994 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 995 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 996
497d7c86 997 re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
998 GFP_KERNEL);
cd28ab6a
SH		 999 if (!re->skb)
1000 goto nomem;
1001
6b1a3aef 1002 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1003 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1004 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1005 }
1006
a1433ac4
SH		 1007
1008 /*
1009 * The receiver hangs if it receives frames larger than the
1010 * packet buffer. As a workaround, truncate oversize frames, but
1011 * the register is limited to 9 bits, so if you do frames > 2052
1012 * you better get the MTU right!
1013 */
1014 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1015 if (thresh > 0x1ff)
1016 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1017 else {
1018 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1019 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1020 }
1021
70f1be48 1022
6b1a3aef 1023 /* Tell chip about available buffers */
1024 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1025 return 0;
1026nomem:
1027 sky2_rx_clean(sky2);
1028 return -ENOMEM;
1029}
1030
1031/* Bring up network interface. */
1032static int sky2_up(struct net_device *dev)
1033{
1034 struct sky2_port *sky2 = netdev_priv(dev);
1035 struct sky2_hw *hw = sky2->hw;
1036 unsigned port = sky2->port;
e07b1aa8 1037 u32 ramsize, rxspace, imask;
ee7abb04 1038 int cap, err = -ENOMEM;
843a46f4 1039 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1040
ee7abb04
SH		 1041 /*
1042 * On dual port PCI-X card, there is an problem where status
1043 * can be received out of order due to split transactions
843a46f4 1044 */
ee7abb04
SH		 1045 if (otherdev && netif_running(otherdev) &&
1046 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1047 struct sky2_port *osky2 = netdev_priv(otherdev);
1048 u16 cmd;
1049
1050 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1051 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1052 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1053
1054 sky2->rx_csum = 0;
1055 osky2->rx_csum = 0;
1056 }
843a46f4 1057
cd28ab6a
SH		 1058 if (netif_msg_ifup(sky2))
1059 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1060
1061 /* must be power of 2 */
1062 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1063 TX_RING_SIZE *
1064 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1065 &sky2->tx_le_map);
1066 if (!sky2->tx_le)
1067 goto err_out;
1068
6cdbbdf3 1069 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1070 GFP_KERNEL);
1071 if (!sky2->tx_ring)
1072 goto err_out;
1073 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1074
1075 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1076 &sky2->rx_le_map);
1077 if (!sky2->rx_le)
1078 goto err_out;
1079 memset(sky2->rx_le, 0, RX_LE_BYTES);
1080
6cdbbdf3 1081 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1082 GFP_KERNEL);
1083 if (!sky2->rx_ring)
1084 goto err_out;
1085
d3bcfbeb 1086 sky2_phy_power(hw, port, 1);
1087
cd28ab6a
SH		 1088 sky2_mac_init(hw, port);
1089
1c28f6ba
SH		 1090 /* Determine available ram buffer space (in 4K blocks).
1091 * Note: not sure about the FE setting below yet
1092 */
1093 if (hw->chip_id == CHIP_ID_YUKON_FE)
1094 ramsize = 4;
1095 else
1096 ramsize = sky2_read8(hw, B2_E_0);
1097
1098 /* Give transmitter one third (rounded up) */
1099 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1100
cd28ab6a 1101 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1102 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1103
793b883e
SH		 1104 /* Make sure SyncQ is disabled */
1105 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1106 RB_RST_SET);
1107
af4ed7e6 1108 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1109
977bdf06
SH		 1110 /* Set almost empty threshold */
1111 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1112 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1113
6b1a3aef 1114 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1115 TX_RING_SIZE - 1);
cd28ab6a 1116
6b1a3aef 1117 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1118 if (err)
1119 goto err_out;
1120
cd28ab6a 1121 /* Enable interrupts from phy/mac for port */
e07b1aa8 1122 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1123 imask |= portirq_msk[port];
e07b1aa8
SH		 1124 sky2_write32(hw, B0_IMSK, imask);
1125
cd28ab6a
SH		 1126 return 0;
1127
1128err_out:
1b537565 1129 if (sky2->rx_le) {
cd28ab6a
SH		 1130 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1131 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1132 sky2->rx_le = NULL;
1133 }
1134 if (sky2->tx_le) {
cd28ab6a
SH		 1135 pci_free_consistent(hw->pdev,
1136 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1137 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1138 sky2->tx_le = NULL;
1139 }
1140 kfree(sky2->tx_ring);
1141 kfree(sky2->rx_ring);
cd28ab6a 1142
1b537565
SH		 1143 sky2->tx_ring = NULL;
1144 sky2->rx_ring = NULL;
cd28ab6a
SH		 1145 return err;
1146}
1147
793b883e
SH		 1148/* Modular subtraction in ring */
1149static inline int tx_dist(unsigned tail, unsigned head)
1150{
cb5d9547 1151 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1152}
cd28ab6a 1153
793b883e
SH		 1154/* Number of list elements available for next tx */
1155static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1156{
793b883e 1157 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1158}
1159
793b883e 1160/* Estimate of number of transmit list elements required */
28bd181a 1161static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1162{
793b883e
SH		 1163 unsigned count;
1164
1165 count = sizeof(dma_addr_t) / sizeof(u32);
1166 count += skb_shinfo(skb)->nr_frags * count;
1167
89114afd 1168 if (skb_is_gso(skb))
793b883e
SH		 1169 ++count;
1170
0e3ff6aa 1171 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1172 ++count;
1173
1174 return count;
cd28ab6a
SH		 1175}
1176
793b883e
SH		 1177/*
1178 * Put one packet in ring for transmit.
1179 * A single packet can generate multiple list elements, and
1180 * the number of ring elements will probably be less than the number
1181 * of list elements used.
f2e46561
SH		 1182 *
1183 * No BH disabling for tx_lock here (like tg3)
793b883e 1184 */
cd28ab6a
SH		 1185static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1186{
1187 struct sky2_port *sky2 = netdev_priv(dev);
1188 struct sky2_hw *hw = sky2->hw;
d1f13708 1189 struct sky2_tx_le *le = NULL;
6cdbbdf3 1190 struct tx_ring_info *re;
cd28ab6a
SH		 1191 unsigned i, len;
1192 dma_addr_t mapping;
1193 u32 addr64;
1194 u16 mss;
1195 u8 ctrl;
1196
302d1252
SH		 1197 /* No BH disabling for tx_lock here. We are running in BH disabled
1198 * context and TX reclaim runs via poll inside of a software
1199 * interrupt, and no related locks in IRQ processing.
1200 */
f2e46561 1201 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1202 return NETDEV_TX_LOCKED;
1203
793b883e 1204 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1205 /* There is a known but harmless race with lockless tx
1206 * and netif_stop_queue.
1207 */
1208 if (!netif_queue_stopped(dev)) {
1209 netif_stop_queue(dev);
3be92a70
SH		 1210 if (net_ratelimit())
1211 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1212 dev->name);
8c463ef7 1213 }
f2e46561 1214 spin_unlock(&sky2->tx_lock);
cd28ab6a 1215
cd28ab6a
SH		 1216 return NETDEV_TX_BUSY;
1217 }
1218
793b883e 1219 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1220 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1221 dev->name, sky2->tx_prod, skb->len);
1222
cd28ab6a
SH		 1223 len = skb_headlen(skb);
1224 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1225 addr64 = high32(mapping);
793b883e
SH		 1226
1227 re = sky2->tx_ring + sky2->tx_prod;
1228
a018e330 1229 /* Send high bits if changed or crosses boundary */
1230 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1231 le = get_tx_le(sky2);
1232 le->tx.addr = cpu_to_le32(addr64);
1233 le->ctrl = 0;
1234 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1235 sky2->tx_addr64 = high32(mapping + len);
793b883e 1236 }
cd28ab6a
SH		 1237
1238 /* Check for TCP Segmentation Offload */
7967168c 1239 mss = skb_shinfo(skb)->gso_size;
793b883e 1240 if (mss != 0) {
cd28ab6a
SH		 1241 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1242 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1243 mss += ETH_HLEN;
1244
e07560cd 1245 if (mss != sky2->tx_last_mss) {
1246 le = get_tx_le(sky2);
1247 le->tx.tso.size = cpu_to_le16(mss);
1248 le->tx.tso.rsvd = 0;
1249 le->opcode = OP_LRGLEN | HW_OWNER;
1250 le->ctrl = 0;
1251 sky2->tx_last_mss = mss;
1252 }
cd28ab6a
SH		 1253 }
1254
cd28ab6a 1255 ctrl = 0;
d1f13708 1256#ifdef SKY2_VLAN_TAG_USED
1257 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1258 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1259 if (!le) {
1260 le = get_tx_le(sky2);
1261 le->tx.addr = 0;
1262 le->opcode = OP_VLAN|HW_OWNER;
1263 le->ctrl = 0;
1264 } else
1265 le->opcode |= OP_VLAN;
1266 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1267 ctrl |= INS_VLAN;
1268 }
1269#endif
1270
1271 /* Handle TCP checksum offload */
cd28ab6a 1272 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1273 u16 hdr = skb->h.raw - skb->data;
1274 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1275
1276 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1277 if (skb->nh.iph->protocol == IPPROTO_UDP)
1278 ctrl |= UDPTCP;
1279
1d179332 1280 if (hdr != sky2->tx_csum_start || offset != sky2->tx_csum_offset) {
1281 sky2->tx_csum_start = hdr;
1282 sky2->tx_csum_offset = offset;
1283
1284 le = get_tx_le(sky2);
1285 le->tx.csum.start = cpu_to_le16(hdr);
1286 le->tx.csum.offset = cpu_to_le16(offset);
1287 le->length = 0; /* initial checksum value */
1288 le->ctrl = 1; /* one packet */
1289 le->opcode = OP_TCPLISW | HW_OWNER;
1290 }
cd28ab6a
SH		 1291 }
1292
1293 le = get_tx_le(sky2);
1294 le->tx.addr = cpu_to_le32((u32) mapping);
1295 le->length = cpu_to_le16(len);
1296 le->ctrl = ctrl;
793b883e 1297 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1298
793b883e 1299 /* Record the transmit mapping info */
cd28ab6a 1300 re->skb = skb;
6cdbbdf3 1301 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1302
1303 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1304 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1305 struct tx_ring_info *fre;
cd28ab6a
SH		 1306
1307 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1308 frag->size, PCI_DMA_TODEVICE);
a036119f 1309 addr64 = high32(mapping);
793b883e
SH		 1310 if (addr64 != sky2->tx_addr64) {
1311 le = get_tx_le(sky2);
1312 le->tx.addr = cpu_to_le32(addr64);
1313 le->ctrl = 0;
1314 le->opcode = OP_ADDR64 | HW_OWNER;
1315 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1316 }
1317
1318 le = get_tx_le(sky2);
1319 le->tx.addr = cpu_to_le32((u32) mapping);
1320 le->length = cpu_to_le16(frag->size);
1321 le->ctrl = ctrl;
793b883e 1322 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1323
793b883e 1324 fre = sky2->tx_ring
e07560cd 1325 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1326 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1327 }
6cdbbdf3 1328
793b883e 1329 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1330 le->ctrl |= EOP;
1331
97bda706 1332 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1333 netif_stop_queue(dev);
b19666d9 1334
290d4de5 1335 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1336
f2e46561 1337 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1338
1339 dev->trans_start = jiffies;
1340 return NETDEV_TX_OK;
1341}
1342
cd28ab6a 1343/*
793b883e
SH		 1344 * Free ring elements from starting at tx_cons until "done"
1345 *
1346 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1347 * buffers; these are deferred until completion.
cd28ab6a 1348 */
d11c13e7 1349static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1350{
d11c13e7 1351 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1352 struct pci_dev *pdev = sky2->hw->pdev;
1353 u16 nxt, put;
793b883e 1354 unsigned i;
cd28ab6a 1355
0e3ff6aa 1356 BUG_ON(done >= TX_RING_SIZE);
2224795d 1357
d11c13e7 1358 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1359 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1360 dev->name, done);
cd28ab6a 1361
af2a58ac
SH		 1362 for (put = sky2->tx_cons; put != done; put = nxt) {
1363 struct tx_ring_info *re = sky2->tx_ring + put;
1364 struct sk_buff *skb = re->skb;
cd28ab6a 1365
d89e1343 1366 nxt = re->idx;
af2a58ac 1367 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1368 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1369
793b883e 1370 /* Check for partial status */
af2a58ac
SH		 1371 if (tx_dist(put, done) < tx_dist(put, nxt))
1372 break;
793b883e
SH		 1373
1374 skb = re->skb;
af2a58ac 1375 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1376 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1377
1378 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1379 struct tx_ring_info *fre;
cb5d9547 1380 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1381 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1382 skb_shinfo(skb)->frags[i].size,
734d1868 1383 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1384 }
1385
15240072 1386 dev_kfree_skb(skb);
793b883e 1387 }
793b883e 1388
af2a58ac 1389 sky2->tx_cons = put;
22e11703 1390 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1391 netif_wake_queue(dev);
cd28ab6a
SH		 1392}
1393
1394/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1395static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1396{
302d1252 1397 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1398 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1399 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1400}
1401
1402/* Network shutdown */
1403static int sky2_down(struct net_device *dev)
1404{
1405 struct sky2_port *sky2 = netdev_priv(dev);
1406 struct sky2_hw *hw = sky2->hw;
1407 unsigned port = sky2->port;
1408 u16 ctrl;
e07b1aa8 1409 u32 imask;
cd28ab6a 1410
1b537565
SH		 1411 /* Never really got started! */
1412 if (!sky2->tx_le)
1413 return 0;
1414
cd28ab6a
SH		 1415 if (netif_msg_ifdown(sky2))
1416 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1417
018d1c66 1418 /* Stop more packets from being queued */
cd28ab6a
SH		 1419 netif_stop_queue(dev);
1420
d3bcfbeb 1421 sky2_gmac_reset(hw, port);
793b883e 1422
cd28ab6a
SH		 1423 /* Stop transmitter */
1424 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1425 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1426
1427 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1428 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1429
1430 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1431 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1432 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1433
1434 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1435
1436 /* Workaround shared GMAC reset */
793b883e
SH		 1437 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1438 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1439 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1440
1441 /* Disable Force Sync bit and Enable Alloc bit */
1442 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1443 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1444
1445 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1446 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1447 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1448
1449 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1450 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1451 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1452
1453 /* Reset the Tx prefetch units */
1454 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1455 PREF_UNIT_RST_SET);
1456
1457 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1458
6b1a3aef 1459 sky2_rx_stop(sky2);
cd28ab6a
SH		 1460
1461 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1462 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1463
e07b1aa8
SH		 1464 /* Disable port IRQ */
1465 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1466 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1467 sky2_write32(hw, B0_IMSK, imask);
1468
d3bcfbeb 1469 sky2_phy_power(hw, port, 0);
1470
d571b694 1471 /* turn off LED's */
cd28ab6a
SH		 1472 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1473
018d1c66 1474 synchronize_irq(hw->pdev->irq);
1475
cd28ab6a
SH		 1476 sky2_tx_clean(sky2);
1477 sky2_rx_clean(sky2);
1478
1479 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1480 sky2->rx_le, sky2->rx_le_map);
1481 kfree(sky2->rx_ring);
1482
1483 pci_free_consistent(hw->pdev,
1484 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1485 sky2->tx_le, sky2->tx_le_map);
1486 kfree(sky2->tx_ring);
1487
1b537565
SH		 1488 sky2->tx_le = NULL;
1489 sky2->rx_le = NULL;
1490
1491 sky2->rx_ring = NULL;
1492 sky2->tx_ring = NULL;
1493
cd28ab6a
SH		 1494 return 0;
1495}
1496
1497static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1498{
793b883e
SH		 1499 if (!hw->copper)
1500 return SPEED_1000;
1501
cd28ab6a
SH		 1502 if (hw->chip_id == CHIP_ID_YUKON_FE)
1503 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1504
1505 switch (aux & PHY_M_PS_SPEED_MSK) {
1506 case PHY_M_PS_SPEED_1000:
1507 return SPEED_1000;
1508 case PHY_M_PS_SPEED_100:
1509 return SPEED_100;
1510 default:
1511 return SPEED_10;
1512 }
1513}
1514
1515static void sky2_link_up(struct sky2_port *sky2)
1516{
1517 struct sky2_hw *hw = sky2->hw;
1518 unsigned port = sky2->port;
1519 u16 reg;
1520
cd28ab6a 1521 /* enable Rx/Tx */
2eaba1a2 1522 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1523 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1524 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1525
1526 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1527
1528 netif_carrier_on(sky2->netdev);
1529 netif_wake_queue(sky2->netdev);
1530
1531 /* Turn on link LED */
793b883e 1532 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1533 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1534
ed6d32c7 1535 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1536 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1537 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1538
1539 switch(sky2->speed) {
1540 case SPEED_10:
1541 led |= PHY_M_LEDC_INIT_CTRL(7);
1542 break;
1543
1544 case SPEED_100:
1545 led |= PHY_M_LEDC_STA1_CTRL(7);
1546 break;
1547
1548 case SPEED_1000:
1549 led |= PHY_M_LEDC_STA0_CTRL(7);
1550 break;
1551 }
793b883e
SH		 1552
1553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1554 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1556 }
1557
cd28ab6a
SH		 1558 if (netif_msg_link(sky2))
1559 printk(KERN_INFO PFX
d571b694 1560 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1561 sky2->netdev->name, sky2->speed,
1562 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1563 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1564 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1565}
1566
1567static void sky2_link_down(struct sky2_port *sky2)
1568{
1569 struct sky2_hw *hw = sky2->hw;
1570 unsigned port = sky2->port;
1571 u16 reg;
1572
1573 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1574
1575 reg = gma_read16(hw, port, GM_GP_CTRL);
1576 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1577 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1578
1579 if (sky2->rx_pause && !sky2->tx_pause) {
1580 /* restore Asymmetric Pause bit */
1581 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1582 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1583 | PHY_M_AN_ASP);
cd28ab6a
SH		 1584 }
1585
cd28ab6a
SH		 1586 netif_carrier_off(sky2->netdev);
1587 netif_stop_queue(sky2->netdev);
1588
1589 /* Turn on link LED */
1590 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1591
1592 if (netif_msg_link(sky2))
1593 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1594
cd28ab6a
SH		 1595 sky2_phy_init(hw, port);
1596}
1597
793b883e
SH		 1598static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1599{
1600 struct sky2_hw *hw = sky2->hw;
1601 unsigned port = sky2->port;
1602 u16 lpa;
1603
1604 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1605
1606 if (lpa & PHY_M_AN_RF) {
1607 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1608 return -1;
1609 }
1610
1611 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1612 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1613 printk(KERN_ERR PFX "%s: master/slave fault",
1614 sky2->netdev->name);
1615 return -1;
1616 }
1617
1618 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1619 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1620 sky2->netdev->name);
1621 return -1;
1622 }
1623
1624 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1625
1626 sky2->speed = sky2_phy_speed(hw, aux);
1627
1628 /* Pause bits are offset (9..8) */
ed6d32c7 1629 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1630 aux >>= 6;
1631
1632 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1633 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1634
2eaba1a2
SH		 1635 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1636 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1637 sky2->rx_pause = sky2->tx_pause = 0;
1638
1639 if (sky2->rx_pause || sky2->tx_pause)
793b883e
SH		 1640 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1641 else
1642 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1643
1644 return 0;
1645}
cd28ab6a 1646
e07b1aa8
SH		 1647/* Interrupt from PHY */
1648static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1649{
e07b1aa8
SH		 1650 struct net_device *dev = hw->dev[port];
1651 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1652 u16 istatus, phystat;
1653
e07b1aa8
SH		 1654 spin_lock(&sky2->phy_lock);
1655 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1656 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1657
1658 if (!netif_running(dev))
1659 goto out;
cd28ab6a
SH		 1660
1661 if (netif_msg_intr(sky2))
1662 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1663 sky2->netdev->name, istatus, phystat);
1664
2eaba1a2 1665 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1666 if (sky2_autoneg_done(sky2, phystat) == 0)
1667 sky2_link_up(sky2);
1668 goto out;
1669 }
cd28ab6a 1670
793b883e
SH		 1671 if (istatus & PHY_M_IS_LSP_CHANGE)
1672 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1673
793b883e
SH		 1674 if (istatus & PHY_M_IS_DUP_CHANGE)
1675 sky2->duplex =
1676 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1677
793b883e
SH		 1678 if (istatus & PHY_M_IS_LST_CHANGE) {
1679 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1680 sky2_link_up(sky2);
793b883e
SH		 1681 else
1682 sky2_link_down(sky2);
cd28ab6a 1683 }
793b883e 1684out:
e07b1aa8 1685 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1686}
1687
302d1252
SH		 1688
1689/* Transmit timeout is only called if we are running, carries is up
1690 * and tx queue is full (stopped).
1691 */
cd28ab6a
SH		 1692static void sky2_tx_timeout(struct net_device *dev)
1693{
1694 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1695 struct sky2_hw *hw = sky2->hw;
1696 unsigned txq = txqaddr[sky2->port];
8f24664d 1697 u16 report, done;
cd28ab6a
SH		 1698
1699 if (netif_msg_timer(sky2))
1700 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1701
8f24664d
SH		 1702 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1703 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1704
8f24664d
SH		 1705 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1706 dev->name,
1707 sky2->tx_cons, sky2->tx_prod, report, done);
1708
1709 if (report != done) {
1710 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1711
1712 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1713 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1714 } else if (report != sky2->tx_cons) {
1715 printk(KERN_INFO PFX "status report lost?\n");
1716
1717 spin_lock_bh(&sky2->tx_lock);
1718 sky2_tx_complete(sky2, report);
1719 spin_unlock_bh(&sky2->tx_lock);
1720 } else {
1721 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1722
8f24664d
SH		 1723 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1724 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1725
1726 sky2_tx_clean(sky2);
1727
1728 sky2_qset(hw, txq);
1729 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1730 }
cd28ab6a
SH		 1731}
1732
734d1868 1733
70f1be48
SH		 1734/* Want receive buffer size to be multiple of 64 bits
1735 * and incl room for vlan and truncation
1736 */
734d1868
SH		 1737static inline unsigned sky2_buf_size(int mtu)
1738{
4a15d56f 1739 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1740}
1741
cd28ab6a
SH		 1742static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1743{
6b1a3aef 1744 struct sky2_port *sky2 = netdev_priv(dev);
1745 struct sky2_hw *hw = sky2->hw;
1746 int err;
1747 u16 ctl, mode;
e07b1aa8 1748 u32 imask;
cd28ab6a
SH		 1749
1750 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1751 return -EINVAL;
1752
5a5b1ea0 1753 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1754 return -EINVAL;
1755
6b1a3aef 1756 if (!netif_running(dev)) {
1757 dev->mtu = new_mtu;
1758 return 0;
1759 }
1760
e07b1aa8 1761 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1762 sky2_write32(hw, B0_IMSK, 0);
1763
018d1c66 1764 dev->trans_start = jiffies; /* prevent tx timeout */
1765 netif_stop_queue(dev);
1766 netif_poll_disable(hw->dev[0]);
1767
e07b1aa8
SH		 1768 synchronize_irq(hw->pdev->irq);
1769
6b1a3aef 1770 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1771 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1772 sky2_rx_stop(sky2);
1773 sky2_rx_clean(sky2);
cd28ab6a
SH		 1774
1775 dev->mtu = new_mtu;
734d1868 1776 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef 1777 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1778 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1779
1780 if (dev->mtu > ETH_DATA_LEN)
1781 mode |= GM_SMOD_JUMBO_ENA;
1782
1783 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1784
6b1a3aef 1785 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1786
6b1a3aef 1787 err = sky2_rx_start(sky2);
e07b1aa8 1788 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1789
1b537565
SH		 1790 if (err)
1791 dev_close(dev);
1792 else {
1793 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1794
1795 netif_poll_enable(hw->dev[0]);
1796 netif_wake_queue(dev);
1797 }
1798
cd28ab6a
SH		 1799 return err;
1800}
1801
1802/*
1803 * Receive one packet.
1804 * For small packets or errors, just reuse existing skb.
d571b694 1805 * For larger packets, get new buffer.
cd28ab6a 1806 */
497d7c86 1807static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1808 u16 length, u32 status)
1809{
497d7c86 1810 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 1811 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1812 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1813
1814 if (unlikely(netif_msg_rx_status(sky2)))
1815 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1816 dev->name, sky2->rx_next, status, length);
cd28ab6a 1817
793b883e 1818 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1819 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1820
42eeea01 1821 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1822 goto error;
1823
42eeea01 1824 if (!(status & GMR_FS_RX_OK))
1825 goto resubmit;
1826
497d7c86 1827 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1828 goto oversize;
1829
bdb5c58e 1830 if (length < copybreak) {
497d7c86 1831 skb = netdev_alloc_skb(dev, length + 2);
79e57d32 1832 if (!skb)
793b883e
SH		 1833 goto resubmit;
1834
79e57d32 1835 skb_reserve(skb, 2);
793b883e
SH		 1836 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1837 length, PCI_DMA_FROMDEVICE);
79e57d32 1838 memcpy(skb->data, re->skb->data, length);
d11c13e7 1839 skb->ip_summed = re->skb->ip_summed;
1840 skb->csum = re->skb->csum;
793b883e
SH		 1841 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1842 length, PCI_DMA_FROMDEVICE);
793b883e 1843 } else {
79e57d32
SH		 1844 struct sk_buff *nskb;
1845
497d7c86 1846 nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1847 if (!nskb)
1848 goto resubmit;
cd28ab6a 1849
793b883e 1850 skb = re->skb;
79e57d32 1851 re->skb = nskb;
793b883e 1852 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1853 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1854 prefetch(skb->data);
cd28ab6a 1855
793b883e 1856 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1857 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1858 }
cd28ab6a 1859
79e57d32 1860 skb_put(skb, length);
793b883e 1861resubmit:
d11c13e7 1862 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1863 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1864
cd28ab6a
SH		 1865 return skb;
1866
6e15b712
SH		 1867oversize:
1868 ++sky2->net_stats.rx_over_errors;
1869 goto resubmit;
1870
cd28ab6a 1871error:
6e15b712
SH		 1872 ++sky2->net_stats.rx_errors;
1873
3be92a70 1874 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 1875 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 1876 dev->name, status, length);
793b883e
SH		 1877
1878 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1879 sky2->net_stats.rx_length_errors++;
1880 if (status & GMR_FS_FRAGMENT)
1881 sky2->net_stats.rx_frame_errors++;
1882 if (status & GMR_FS_CRC_ERR)
1883 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1884 if (status & GMR_FS_RX_FF_OV)
1885 sky2->net_stats.rx_fifo_errors++;
79e57d32 1886
793b883e 1887 goto resubmit;
cd28ab6a
SH		 1888}
1889
e07b1aa8
SH		 1890/* Transmit complete */
1891static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1892{
e07b1aa8 1893 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1894
e07b1aa8
SH		 1895 if (netif_running(dev)) {
1896 spin_lock(&sky2->tx_lock);
1897 sky2_tx_complete(sky2, last);
1898 spin_unlock(&sky2->tx_lock);
2224795d 1899 }
cd28ab6a
SH		 1900}
1901
e07b1aa8
SH		 1902/* Process status response ring */
1903static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1904{
22e11703 1905 struct sky2_port *sky2;
e07b1aa8 1906 int work_done = 0;
22e11703 1907 unsigned buf_write[2] = { 0, 0 };
e71ebd73 1908 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1909
af2a58ac 1910 rmb();
bea86103 1911
e71ebd73 1912 while (hw->st_idx != hwidx) {
13210ce5 1913 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1914 struct net_device *dev;
cd28ab6a 1915 struct sk_buff *skb;
cd28ab6a
SH		 1916 u32 status;
1917 u16 length;
1918
cb5d9547 1919 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1920
e71ebd73
SH		 1921 BUG_ON(le->link >= 2);
1922 dev = hw->dev[le->link];
13210ce5 1923
1924 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1925 length = le->length;
1926 status = le->status;
cd28ab6a 1927
e71ebd73 1928 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1929 case OP_RXSTAT:
497d7c86 1930 skb = sky2_receive(dev, length, status);
d1f13708 1931 if (!skb)
1932 break;
13210ce5 1933
13210ce5 1934 skb->protocol = eth_type_trans(skb, dev);
1935 dev->last_rx = jiffies;
1936
d1f13708 1937#ifdef SKY2_VLAN_TAG_USED
1938 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1939 vlan_hwaccel_receive_skb(skb,
1940 sky2->vlgrp,
1941 be16_to_cpu(sky2->rx_tag));
1942 } else
1943#endif
cd28ab6a 1944 netif_receive_skb(skb);
13210ce5 1945
22e11703
SH		 1946 /* Update receiver after 16 frames */
1947 if (++buf_write[le->link] == RX_BUF_WRITE) {
1948 sky2_put_idx(hw, rxqaddr[le->link],
1949 sky2->rx_put);
1950 buf_write[le->link] = 0;
1951 }
1952
1953 /* Stop after net poll weight */
13210ce5 1954 if (++work_done >= to_do)
1955 goto exit_loop;
cd28ab6a
SH		 1956 break;
1957
d1f13708 1958#ifdef SKY2_VLAN_TAG_USED
1959 case OP_RXVLAN:
1960 sky2->rx_tag = length;
1961 break;
1962
1963 case OP_RXCHKSVLAN:
1964 sky2->rx_tag = length;
1965 /* fall through */
1966#endif
cd28ab6a 1967 case OP_RXCHKS:
d11c13e7 1968 skb = sky2->rx_ring[sky2->rx_next].skb;
1969 skb->ip_summed = CHECKSUM_HW;
1970 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1971 break;
1972
1973 case OP_TXINDEXLE:
13b97b74 1974 /* TX index reports status for both ports */
f55925d7
SH		 1975 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1976 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 1977 if (hw->dev[1])
1978 sky2_tx_done(hw->dev[1],
1979 ((status >> 24) & 0xff)
1980 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 1981 break;
1982
cd28ab6a
SH		 1983 default:
1984 if (net_ratelimit())
793b883e 1985 printk(KERN_WARNING PFX
e71ebd73
SH		 1986 "unknown status opcode 0x%x\n", le->opcode);
1987 goto exit_loop;
cd28ab6a 1988 }
13210ce5 1989 }
cd28ab6a 1990
fe2a24df
SH		 1991 /* Fully processed status ring so clear irq */
1992 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1993
13210ce5 1994exit_loop:
22e11703
SH		 1995 if (buf_write[0]) {
1996 sky2 = netdev_priv(hw->dev[0]);
1997 sky2_put_idx(hw, Q_R1, sky2->rx_put);
1998 }
1999
2000 if (buf_write[1]) {
2001 sky2 = netdev_priv(hw->dev[1]);
2002 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2003 }
2004
e07b1aa8 2005 return work_done;
cd28ab6a
SH		 2006}
2007
2008static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2009{
2010 struct net_device *dev = hw->dev[port];
2011
3be92a70
SH		 2012 if (net_ratelimit())
2013 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2014 dev->name, status);
cd28ab6a
SH		 2015
2016 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2017 if (net_ratelimit())
2018 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2019 dev->name);
cd28ab6a
SH		 2020 /* Clear IRQ */
2021 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2022 }
2023
2024 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2025 if (net_ratelimit())
2026 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2027 dev->name);
cd28ab6a
SH		 2028
2029 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2030 }
2031
2032 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2033 if (net_ratelimit())
2034 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2035 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2036 }
2037
2038 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2039 if (net_ratelimit())
2040 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2041 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2042 }
2043
2044 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2045 if (net_ratelimit())
2046 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2047 dev->name);
cd28ab6a
SH		 2048 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2049 }
2050}
2051
2052static void sky2_hw_intr(struct sky2_hw *hw)
2053{
2054 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2055
793b883e 2056 if (status & Y2_IS_TIST_OV)
cd28ab6a 2057 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2058
2059 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2060 u16 pci_err;
2061
56a645cc 2062 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2063 if (net_ratelimit())
2064 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2065 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2066
2067 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2068 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2069 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2070 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2071 }
2072
2073 if (status & Y2_IS_PCI_EXP) {
d571b694 2074 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2075 u32 pex_err;
2076
56a645cc 2077 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2078
3be92a70
SH		 2079 if (net_ratelimit())
2080 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2081 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2082
2083 /* clear the interrupt */
2084 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2085 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2086 0xffffffffUL);
cd28ab6a
SH		 2087 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2088
2089 if (pex_err & PEX_FATAL_ERRORS) {
2090 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2091 hwmsk &= ~Y2_IS_PCI_EXP;
2092 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2093 }
2094 }
2095
2096 if (status & Y2_HWE_L1_MASK)
2097 sky2_hw_error(hw, 0, status);
2098 status >>= 8;
2099 if (status & Y2_HWE_L1_MASK)
2100 sky2_hw_error(hw, 1, status);
2101}
2102
2103static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2104{
2105 struct net_device *dev = hw->dev[port];
2106 struct sky2_port *sky2 = netdev_priv(dev);
2107 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2108
2109 if (netif_msg_intr(sky2))
2110 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2111 dev->name, status);
2112
2113 if (status & GM_IS_RX_FF_OR) {
2114 ++sky2->net_stats.rx_fifo_errors;
2115 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2116 }
2117
2118 if (status & GM_IS_TX_FF_UR) {
2119 ++sky2->net_stats.tx_fifo_errors;
2120 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2121 }
cd28ab6a
SH		 2122}
2123
d257924e
SH		 2124/* This should never happen it is a fatal situation */
2125static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2126 const char *rxtx, u32 mask)
2127{
2128 struct net_device *dev = hw->dev[port];
2129 struct sky2_port *sky2 = netdev_priv(dev);
2130 u32 imask;
2131
2132 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2133 dev ? dev->name : "<not registered>", rxtx);
2134
2135 imask = sky2_read32(hw, B0_IMSK);
2136 imask &= ~mask;
2137 sky2_write32(hw, B0_IMSK, imask);
2138
2139 if (dev) {
2140 spin_lock(&sky2->phy_lock);
2141 sky2_link_down(sky2);
2142 spin_unlock(&sky2->phy_lock);
2143 }
2144}
cd28ab6a 2145
d27ed387
SH		 2146/* If idle then force a fake soft NAPI poll once a second
2147 * to work around cases where sharing an edge triggered interrupt.
2148 */
eb35cf60
SH		 2149static inline void sky2_idle_start(struct sky2_hw *hw)
2150{
2151 if (idle_timeout > 0)
2152 mod_timer(&hw->idle_timer,
2153 jiffies + msecs_to_jiffies(idle_timeout));
2154}
2155
d27ed387
SH		 2156static void sky2_idle(unsigned long arg)
2157{
01bd7564
SH		 2158 struct sky2_hw *hw = (struct sky2_hw *) arg;
2159 struct net_device *dev = hw->dev[0];
d27ed387 2160
d27ed387
SH		 2161 if (__netif_rx_schedule_prep(dev))
2162 __netif_rx_schedule(dev);
01bd7564
SH		 2163
2164 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2165}
2166
2167
e07b1aa8 2168static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2169{
e07b1aa8
SH		 2170 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2171 int work_limit = min(dev0->quota, *budget);
2172 int work_done = 0;
fb2690a9 2173 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2174
1e5f1283
SH		 2175 if (status & Y2_IS_HW_ERR)
2176 sky2_hw_intr(hw);
d257924e 2177
1e5f1283
SH		 2178 if (status & Y2_IS_IRQ_PHY1)
2179 sky2_phy_intr(hw, 0);
cd28ab6a 2180
1e5f1283
SH		 2181 if (status & Y2_IS_IRQ_PHY2)
2182 sky2_phy_intr(hw, 1);
cd28ab6a 2183
1e5f1283
SH		 2184 if (status & Y2_IS_IRQ_MAC1)
2185 sky2_mac_intr(hw, 0);
cd28ab6a 2186
1e5f1283
SH		 2187 if (status & Y2_IS_IRQ_MAC2)
2188 sky2_mac_intr(hw, 1);
cd28ab6a 2189
1e5f1283
SH		 2190 if (status & Y2_IS_CHK_RX1)
2191 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2192
1e5f1283
SH		 2193 if (status & Y2_IS_CHK_RX2)
2194 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2195
1e5f1283
SH		 2196 if (status & Y2_IS_CHK_TXA1)
2197 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2198
1e5f1283
SH		 2199 if (status & Y2_IS_CHK_TXA2)
2200 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2201
1e5f1283 2202 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2203 if (work_done < work_limit) {
2204 netif_rx_complete(dev0);
86fba634 2205
fe2a24df
SH		 2206 sky2_read32(hw, B0_Y2_SP_LISR);
2207 return 0;
2208 } else {
2209 *budget -= work_done;
2210 dev0->quota -= work_done;
1e5f1283 2211 return 1;
fe2a24df 2212 }
e07b1aa8
SH		 2213}
2214
2215static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2216{
2217 struct sky2_hw *hw = dev_id;
2218 struct net_device *dev0 = hw->dev[0];
2219 u32 status;
2220
2221 /* Reading this mask interrupts as side effect */
2222 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2223 if (status == 0 || status == ~0)
2224 return IRQ_NONE;
793b883e 2225
e07b1aa8
SH		 2226 prefetch(&hw->st_le[hw->st_idx]);
2227 if (likely(__netif_rx_schedule_prep(dev0)))
2228 __netif_rx_schedule(dev0);
793b883e 2229
cd28ab6a
SH		 2230 return IRQ_HANDLED;
2231}
2232
2233#ifdef CONFIG_NET_POLL_CONTROLLER
2234static void sky2_netpoll(struct net_device *dev)
2235{
2236 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2237 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2238
88d11360
SH		 2239 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2240 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2241}
2242#endif
2243
2244/* Chip internal frequency for clock calculations */
fb17358f 2245static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2246{
793b883e 2247 switch (hw->chip_id) {
cd28ab6a 2248 case CHIP_ID_YUKON_EC:
5a5b1ea0 2249 case CHIP_ID_YUKON_EC_U:
fb17358f 2250 return 125; /* 125 Mhz */
cd28ab6a 2251 case CHIP_ID_YUKON_FE:
fb17358f 2252 return 100; /* 100 Mhz */
793b883e 2253 default: /* YUKON_XL */
fb17358f 2254 return 156; /* 156 Mhz */
cd28ab6a
SH		 2255 }
2256}
2257
fb17358f 2258static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2259{
fb17358f 2260 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2261}
2262
fb17358f 2263static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2264{
fb17358f 2265 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2266}
2267
fb17358f 2268
59139528 2269static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2270{
cd28ab6a
SH		 2271 u16 status;
2272 u8 t8, pmd_type;
56a645cc 2273 int i;
cd28ab6a 2274
cd28ab6a 2275 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2276
cd28ab6a
SH		 2277 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2278 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2279 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2280 pci_name(hw->pdev), hw->chip_id);
2281 return -EOPNOTSUPP;
2282 }
2283
290d4de5
SH		 2284 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2285
2286 /* This rev is really old, and requires untested workarounds */
2287 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2288 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2289 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2290 hw->chip_id, hw->chip_rev);
2291 return -EOPNOTSUPP;
2292 }
2293
cd28ab6a
SH		 2294 /* disable ASF */
2295 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2296 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2297 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2298 }
2299
2300 /* do a SW reset */
2301 sky2_write8(hw, B0_CTST, CS_RST_SET);
2302 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2303
2304 /* clear PCI errors, if any */
56a645cc 2305 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2306
cd28ab6a 2307 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2308 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2309
cd28ab6a
SH		 2310
2311 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2312
2313 /* clear any PEX errors */
d89e1343 2314 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2315 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2316
cd28ab6a
SH		 2317
2318 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2319 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2320
2321 hw->ports = 1;
2322 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2323 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2324 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2325 ++hw->ports;
2326 }
cd28ab6a 2327
5afa0a9c 2328 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2329
2330 for (i = 0; i < hw->ports; i++) {
2331 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2332 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2333 }
2334
2335 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2336
793b883e
SH		 2337 /* Clear I2C IRQ noise */
2338 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2339
2340 /* turn off hardware timer (unused) */
2341 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2342 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2343
cd28ab6a
SH		 2344 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2345
69634ee7
SH		 2346 /* Turn off descriptor polling */
2347 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2348
2349 /* Turn off receive timestamp */
2350 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2351 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2352
2353 /* enable the Tx Arbiters */
2354 for (i = 0; i < hw->ports; i++)
2355 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2356
2357 /* Initialize ram interface */
2358 for (i = 0; i < hw->ports; i++) {
793b883e 2359 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2360
2361 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2362 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2363 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2364 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2365 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2366 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2367 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2368 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2369 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2370 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2371 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2372 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2373 }
2374
cd28ab6a
SH		 2375 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2376
cd28ab6a 2377 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2378 sky2_gmac_reset(hw, i);
cd28ab6a 2379
cd28ab6a
SH		 2380 memset(hw->st_le, 0, STATUS_LE_BYTES);
2381 hw->st_idx = 0;
2382
2383 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2384 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2385
2386 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2387 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2388
2389 /* Set the list last index */
793b883e 2390 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2391
290d4de5
SH		 2392 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2393 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2394
290d4de5
SH		 2395 /* set Status-FIFO ISR watermark */
2396 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2397 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2398 else
2399 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2400
290d4de5 2401 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2402 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2403 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2404
793b883e 2405 /* enable status unit */
cd28ab6a
SH		 2406 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2407
2408 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2409 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2410 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2411
2412 return 0;
2413}
2414
28bd181a 2415static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2416{
2417 u32 modes;
2418 if (hw->copper) {
793b883e
SH		 2419 modes = SUPPORTED_10baseT_Half
2420 | SUPPORTED_10baseT_Full
2421 | SUPPORTED_100baseT_Half
2422 | SUPPORTED_100baseT_Full
2423 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2424
2425 if (hw->chip_id != CHIP_ID_YUKON_FE)
2426 modes |= SUPPORTED_1000baseT_Half
793b883e 2427 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2428 } else
2429 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2430 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2431 return modes;
2432}
2433
793b883e 2434static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2435{
2436 struct sky2_port *sky2 = netdev_priv(dev);
2437 struct sky2_hw *hw = sky2->hw;
2438
2439 ecmd->transceiver = XCVR_INTERNAL;
2440 ecmd->supported = sky2_supported_modes(hw);
2441 ecmd->phy_address = PHY_ADDR_MARV;
2442 if (hw->copper) {
2443 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2444 | SUPPORTED_10baseT_Full
2445 | SUPPORTED_100baseT_Half
2446 | SUPPORTED_100baseT_Full
2447 | SUPPORTED_1000baseT_Half
2448 | SUPPORTED_1000baseT_Full
2449 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2450 ecmd->port = PORT_TP;
2451 } else
2452 ecmd->port = PORT_FIBRE;
2453
2454 ecmd->advertising = sky2->advertising;
2455 ecmd->autoneg = sky2->autoneg;
2456 ecmd->speed = sky2->speed;
2457 ecmd->duplex = sky2->duplex;
2458 return 0;
2459}
2460
2461static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2462{
2463 struct sky2_port *sky2 = netdev_priv(dev);
2464 const struct sky2_hw *hw = sky2->hw;
2465 u32 supported = sky2_supported_modes(hw);
2466
2467 if (ecmd->autoneg == AUTONEG_ENABLE) {
2468 ecmd->advertising = supported;
2469 sky2->duplex = -1;
2470 sky2->speed = -1;
2471 } else {
2472 u32 setting;
2473
793b883e 2474 switch (ecmd->speed) {
cd28ab6a
SH		 2475 case SPEED_1000:
2476 if (ecmd->duplex == DUPLEX_FULL)
2477 setting = SUPPORTED_1000baseT_Full;
2478 else if (ecmd->duplex == DUPLEX_HALF)
2479 setting = SUPPORTED_1000baseT_Half;
2480 else
2481 return -EINVAL;
2482 break;
2483 case SPEED_100:
2484 if (ecmd->duplex == DUPLEX_FULL)
2485 setting = SUPPORTED_100baseT_Full;
2486 else if (ecmd->duplex == DUPLEX_HALF)
2487 setting = SUPPORTED_100baseT_Half;
2488 else
2489 return -EINVAL;
2490 break;
2491
2492 case SPEED_10:
2493 if (ecmd->duplex == DUPLEX_FULL)
2494 setting = SUPPORTED_10baseT_Full;
2495 else if (ecmd->duplex == DUPLEX_HALF)
2496 setting = SUPPORTED_10baseT_Half;
2497 else
2498 return -EINVAL;
2499 break;
2500 default:
2501 return -EINVAL;
2502 }
2503
2504 if ((setting & supported) == 0)
2505 return -EINVAL;
2506
2507 sky2->speed = ecmd->speed;
2508 sky2->duplex = ecmd->duplex;
2509 }
2510
2511 sky2->autoneg = ecmd->autoneg;
2512 sky2->advertising = ecmd->advertising;
2513
1b537565
SH		 2514 if (netif_running(dev))
2515 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2516
2517 return 0;
2518}
2519
2520static void sky2_get_drvinfo(struct net_device *dev,
2521 struct ethtool_drvinfo *info)
2522{
2523 struct sky2_port *sky2 = netdev_priv(dev);
2524
2525 strcpy(info->driver, DRV_NAME);
2526 strcpy(info->version, DRV_VERSION);
2527 strcpy(info->fw_version, "N/A");
2528 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2529}
2530
2531static const struct sky2_stat {
793b883e
SH		 2532 char name[ETH_GSTRING_LEN];
2533 u16 offset;
cd28ab6a
SH		 2534} sky2_stats[] = {
2535 { "tx_bytes", GM_TXO_OK_HI },
2536 { "rx_bytes", GM_RXO_OK_HI },
2537 { "tx_broadcast", GM_TXF_BC_OK },
2538 { "rx_broadcast", GM_RXF_BC_OK },
2539 { "tx_multicast", GM_TXF_MC_OK },
2540 { "rx_multicast", GM_RXF_MC_OK },
2541 { "tx_unicast", GM_TXF_UC_OK },
2542 { "rx_unicast", GM_RXF_UC_OK },
2543 { "tx_mac_pause", GM_TXF_MPAUSE },
2544 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2545 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2546 { "late_collision",GM_TXF_LAT_COL },
2547 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2548 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2549 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2550
d2604540 2551 { "rx_short", GM_RXF_SHT },
cd28ab6a 2552 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2553 { "rx_64_byte_packets", GM_RXF_64B },
2554 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2555 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2556 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2557 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2558 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2559 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2560 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2561 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2562 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2563 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2564
2565 { "tx_64_byte_packets", GM_TXF_64B },
2566 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2567 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2568 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2569 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2570 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2571 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2572 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2573};
2574
cd28ab6a
SH		 2575static u32 sky2_get_rx_csum(struct net_device *dev)
2576{
2577 struct sky2_port *sky2 = netdev_priv(dev);
2578
2579 return sky2->rx_csum;
2580}
2581
2582static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2583{
2584 struct sky2_port *sky2 = netdev_priv(dev);
2585
2586 sky2->rx_csum = data;
793b883e 2587
cd28ab6a
SH		 2588 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2589 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2590
2591 return 0;
2592}
2593
2594static u32 sky2_get_msglevel(struct net_device *netdev)
2595{
2596 struct sky2_port *sky2 = netdev_priv(netdev);
2597 return sky2->msg_enable;
2598}
2599
9a7ae0a9
SH		 2600static int sky2_nway_reset(struct net_device *dev)
2601{
2602 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2603
2604 if (sky2->autoneg != AUTONEG_ENABLE)
2605 return -EINVAL;
2606
1b537565 2607 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2608
2609 return 0;
2610}
2611
793b883e 2612static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2613{
2614 struct sky2_hw *hw = sky2->hw;
2615 unsigned port = sky2->port;
2616 int i;
2617
2618 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2619 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2620 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2621 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2622
793b883e 2623 for (i = 2; i < count; i++)
cd28ab6a
SH		 2624 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2625}
2626
cd28ab6a
SH		 2627static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2628{
2629 struct sky2_port *sky2 = netdev_priv(netdev);
2630 sky2->msg_enable = value;
2631}
2632
2633static int sky2_get_stats_count(struct net_device *dev)
2634{
2635 return ARRAY_SIZE(sky2_stats);
2636}
2637
2638static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2639 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2640{
2641 struct sky2_port *sky2 = netdev_priv(dev);
2642
793b883e 2643 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2644}
2645
793b883e 2646static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2647{
2648 int i;
2649
2650 switch (stringset) {
2651 case ETH_SS_STATS:
2652 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2653 memcpy(data + i * ETH_GSTRING_LEN,
2654 sky2_stats[i].name, ETH_GSTRING_LEN);
2655 break;
2656 }
2657}
2658
2659/* Use hardware MIB variables for critical path statistics and
2660 * transmit feedback not reported at interrupt.
2661 * Other errors are accounted for in interrupt handler.
2662 */
2663static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2664{
2665 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2666 u64 data[13];
cd28ab6a 2667
793b883e 2668 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2669
2670 sky2->net_stats.tx_bytes = data[0];
2671 sky2->net_stats.rx_bytes = data[1];
2672 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2673 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2674 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2675 sky2->net_stats.collisions = data[10];
2676 sky2->net_stats.tx_aborted_errors = data[12];
2677
2678 return &sky2->net_stats;
2679}
2680
2681static int sky2_set_mac_address(struct net_device *dev, void *p)
2682{
2683 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2684 struct sky2_hw *hw = sky2->hw;
2685 unsigned port = sky2->port;
2686 const struct sockaddr *addr = p;
cd28ab6a
SH		 2687
2688 if (!is_valid_ether_addr(addr->sa_data))
2689 return -EADDRNOTAVAIL;
2690
cd28ab6a 2691 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2692 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2693 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2694 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2695 dev->dev_addr, ETH_ALEN);
1b537565 2696
a8ab1ec0
SH		 2697 /* virtual address for data */
2698 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2699
2700 /* physical address: used for pause frames */
2701 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2702
2703 return 0;
cd28ab6a
SH		 2704}
2705
2706static void sky2_set_multicast(struct net_device *dev)
2707{
2708 struct sky2_port *sky2 = netdev_priv(dev);
2709 struct sky2_hw *hw = sky2->hw;
2710 unsigned port = sky2->port;
2711 struct dev_mc_list *list = dev->mc_list;
2712 u16 reg;
2713 u8 filter[8];
2714
2715 memset(filter, 0, sizeof(filter));
2716
2717 reg = gma_read16(hw, port, GM_RX_CTRL);
2718 reg |= GM_RXCR_UCF_ENA;
2719
d571b694 2720 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2721 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2722 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2723 memset(filter, 0xff, sizeof(filter));
793b883e 2724 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2725 reg &= ~GM_RXCR_MCF_ENA;
2726 else {
2727 int i;
2728 reg |= GM_RXCR_MCF_ENA;
2729
2730 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2731 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2732 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2733 }
2734 }
2735
cd28ab6a 2736 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2737 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2738 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2739 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2740 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2741 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2742 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2743 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2744
2745 gma_write16(hw, port, GM_RX_CTRL, reg);
2746}
2747
2748/* Can have one global because blinking is controlled by
2749 * ethtool and that is always under RTNL mutex
2750 */
91c86df5 2751static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2752{
793b883e
SH		 2753 u16 pg;
2754
793b883e
SH		 2755 switch (hw->chip_id) {
2756 case CHIP_ID_YUKON_XL:
2757 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2758 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2759 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2760 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2761 PHY_M_LEDC_INIT_CTRL(7) |
2762 PHY_M_LEDC_STA1_CTRL(7) |
2763 PHY_M_LEDC_STA0_CTRL(7))
2764 : 0);
2765
2766 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2767 break;
2768
2769 default:
2770 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2771 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2772 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2773 PHY_M_LED_MO_10(MO_LED_ON) |
2774 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2775 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2776 PHY_M_LED_MO_RX(MO_LED_ON)
2777 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2778 PHY_M_LED_MO_10(MO_LED_OFF) |
2779 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2780 PHY_M_LED_MO_1000(MO_LED_OFF) |
2781 PHY_M_LED_MO_RX(MO_LED_OFF));
2782
793b883e 2783 }
cd28ab6a
SH		 2784}
2785
2786/* blink LED's for finding board */
2787static int sky2_phys_id(struct net_device *dev, u32 data)
2788{
2789 struct sky2_port *sky2 = netdev_priv(dev);
2790 struct sky2_hw *hw = sky2->hw;
2791 unsigned port = sky2->port;
793b883e 2792 u16 ledctrl, ledover = 0;
cd28ab6a 2793 long ms;
91c86df5 2794 int interrupted;
cd28ab6a
SH		 2795 int onoff = 1;
2796
793b883e 2797 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2798 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2799 else
2800 ms = data * 1000;
2801
2802 /* save initial values */
e07b1aa8 2803 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2804 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2805 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2806 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2807 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2808 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2809 } else {
2810 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2811 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2812 }
cd28ab6a 2813
91c86df5
SH		 2814 interrupted = 0;
2815 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2816 sky2_led(hw, port, onoff);
2817 onoff = !onoff;
2818
e07b1aa8 2819 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2820 interrupted = msleep_interruptible(250);
e07b1aa8 2821 spin_lock_bh(&sky2->phy_lock);
91c86df5 2822
cd28ab6a
SH		 2823 ms -= 250;
2824 }
2825
2826 /* resume regularly scheduled programming */
793b883e
SH		 2827 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2828 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2829 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2830 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2831 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2832 } else {
2833 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2834 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2835 }
e07b1aa8 2836 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2837
2838 return 0;
2839}
2840
2841static void sky2_get_pauseparam(struct net_device *dev,
2842 struct ethtool_pauseparam *ecmd)
2843{
2844 struct sky2_port *sky2 = netdev_priv(dev);
2845
2846 ecmd->tx_pause = sky2->tx_pause;
2847 ecmd->rx_pause = sky2->rx_pause;
2848 ecmd->autoneg = sky2->autoneg;
2849}
2850
2851static int sky2_set_pauseparam(struct net_device *dev,
2852 struct ethtool_pauseparam *ecmd)
2853{
2854 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2855
2856 sky2->autoneg = ecmd->autoneg;
2857 sky2->tx_pause = ecmd->tx_pause != 0;
2858 sky2->rx_pause = ecmd->rx_pause != 0;
2859
1b537565 2860 sky2_phy_reinit(sky2);
cd28ab6a 2861
2eaba1a2 2862 return 0;
cd28ab6a
SH		 2863}
2864
fb17358f
SH		 2865static int sky2_get_coalesce(struct net_device *dev,
2866 struct ethtool_coalesce *ecmd)
2867{
2868 struct sky2_port *sky2 = netdev_priv(dev);
2869 struct sky2_hw *hw = sky2->hw;
2870
2871 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2872 ecmd->tx_coalesce_usecs = 0;
2873 else {
2874 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2875 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2876 }
2877 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2878
2879 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2880 ecmd->rx_coalesce_usecs = 0;
2881 else {
2882 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2883 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2884 }
2885 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2886
2887 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2888 ecmd->rx_coalesce_usecs_irq = 0;
2889 else {
2890 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2891 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2892 }
2893
2894 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2895
2896 return 0;
2897}
2898
2899/* Note: this affect both ports */
2900static int sky2_set_coalesce(struct net_device *dev,
2901 struct ethtool_coalesce *ecmd)
2902{
2903 struct sky2_port *sky2 = netdev_priv(dev);
2904 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2905 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2906
77b3d6a2
SH		 2907 if (ecmd->tx_coalesce_usecs > tmax ||
2908 ecmd->rx_coalesce_usecs > tmax ||
2909 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2910 return -EINVAL;
2911
ff81fbbe 2912 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2913 return -EINVAL;
ff81fbbe 2914 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2915 return -EINVAL;
ff81fbbe 2916 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2917 return -EINVAL;
2918
2919 if (ecmd->tx_coalesce_usecs == 0)
2920 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2921 else {
2922 sky2_write32(hw, STAT_TX_TIMER_INI,
2923 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2924 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2925 }
2926 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2927
2928 if (ecmd->rx_coalesce_usecs == 0)
2929 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2930 else {
2931 sky2_write32(hw, STAT_LEV_TIMER_INI,
2932 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2933 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2934 }
2935 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2936
2937 if (ecmd->rx_coalesce_usecs_irq == 0)
2938 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2939 else {
d28d4870 2940 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2941 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2942 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2943 }
2944 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2945 return 0;
2946}
2947
793b883e
SH		 2948static void sky2_get_ringparam(struct net_device *dev,
2949 struct ethtool_ringparam *ering)
2950{
2951 struct sky2_port *sky2 = netdev_priv(dev);
2952
2953 ering->rx_max_pending = RX_MAX_PENDING;
2954 ering->rx_mini_max_pending = 0;
2955 ering->rx_jumbo_max_pending = 0;
2956 ering->tx_max_pending = TX_RING_SIZE - 1;
2957
2958 ering->rx_pending = sky2->rx_pending;
2959 ering->rx_mini_pending = 0;
2960 ering->rx_jumbo_pending = 0;
2961 ering->tx_pending = sky2->tx_pending;
2962}
2963
2964static int sky2_set_ringparam(struct net_device *dev,
2965 struct ethtool_ringparam *ering)
2966{
2967 struct sky2_port *sky2 = netdev_priv(dev);
2968 int err = 0;
2969
2970 if (ering->rx_pending > RX_MAX_PENDING ||
2971 ering->rx_pending < 8 ||
2972 ering->tx_pending < MAX_SKB_TX_LE ||
2973 ering->tx_pending > TX_RING_SIZE - 1)
2974 return -EINVAL;
2975
2976 if (netif_running(dev))
2977 sky2_down(dev);
2978
2979 sky2->rx_pending = ering->rx_pending;
2980 sky2->tx_pending = ering->tx_pending;
2981
1b537565 2982 if (netif_running(dev)) {
793b883e 2983 err = sky2_up(dev);
1b537565
SH		 2984 if (err)
2985 dev_close(dev);
6ed995bb
SH		 2986 else
2987 sky2_set_multicast(dev);
1b537565 2988 }
793b883e
SH		 2989
2990 return err;
2991}
2992
793b883e
SH		 2993static int sky2_get_regs_len(struct net_device *dev)
2994{
6e4cbb34 2995 return 0x4000;
793b883e
SH		 2996}
2997
2998/*
2999 * Returns copy of control register region
6e4cbb34 3000 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3001 */
3002static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3003 void *p)
3004{
3005 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3006 const void __iomem *io = sky2->hw->regs;
793b883e 3007
6e4cbb34 3008 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3009 regs->version = 1;
6e4cbb34 3010 memset(p, 0, regs->len);
793b883e 3011
6e4cbb34
SH		 3012 memcpy_fromio(p, io, B3_RAM_ADDR);
3013
3014 memcpy_fromio(p + B3_RI_WTO_R1,
3015 io + B3_RI_WTO_R1,
3016 regs->len - B3_RI_WTO_R1);
793b883e 3017}
cd28ab6a
SH		 3018
3019static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3020 .get_settings = sky2_get_settings,
3021 .set_settings = sky2_set_settings,
3022 .get_drvinfo = sky2_get_drvinfo,
3023 .get_msglevel = sky2_get_msglevel,
3024 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3025 .nway_reset = sky2_nway_reset,
793b883e
SH		 3026 .get_regs_len = sky2_get_regs_len,
3027 .get_regs = sky2_get_regs,
3028 .get_link = ethtool_op_get_link,
3029 .get_sg = ethtool_op_get_sg,
3030 .set_sg = ethtool_op_set_sg,
3031 .get_tx_csum = ethtool_op_get_tx_csum,
3032 .set_tx_csum = ethtool_op_set_tx_csum,
3033 .get_tso = ethtool_op_get_tso,
3034 .set_tso = ethtool_op_set_tso,
3035 .get_rx_csum = sky2_get_rx_csum,
3036 .set_rx_csum = sky2_set_rx_csum,
3037 .get_strings = sky2_get_strings,
fb17358f
SH		 3038 .get_coalesce = sky2_get_coalesce,
3039 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3040 .get_ringparam = sky2_get_ringparam,
3041 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3042 .get_pauseparam = sky2_get_pauseparam,
3043 .set_pauseparam = sky2_set_pauseparam,
793b883e 3044 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3045 .get_stats_count = sky2_get_stats_count,
3046 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3047 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3048};
3049
3050/* Initialize network device */
3051static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3052 unsigned port, int highmem)
3053{
3054 struct sky2_port *sky2;
3055 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3056
3057 if (!dev) {
3058 printk(KERN_ERR "sky2 etherdev alloc failed");
3059 return NULL;
3060 }
3061
3062 SET_MODULE_OWNER(dev);
3063 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3064 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3065 dev->open = sky2_up;
3066 dev->stop = sky2_down;
ef743d33 3067 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3068 dev->hard_start_xmit = sky2_xmit_frame;
3069 dev->get_stats = sky2_get_stats;
3070 dev->set_multicast_list = sky2_set_multicast;
3071 dev->set_mac_address = sky2_set_mac_address;
3072 dev->change_mtu = sky2_change_mtu;
3073 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3074 dev->tx_timeout = sky2_tx_timeout;
3075 dev->watchdog_timeo = TX_WATCHDOG;
3076 if (port == 0)
3077 dev->poll = sky2_poll;
3078 dev->weight = NAPI_WEIGHT;
3079#ifdef CONFIG_NET_POLL_CONTROLLER
3080 dev->poll_controller = sky2_netpoll;
3081#endif
cd28ab6a
SH		 3082
3083 sky2 = netdev_priv(dev);
3084 sky2->netdev = dev;
3085 sky2->hw = hw;
3086 sky2->msg_enable = netif_msg_init(debug, default_msg);
3087
3088 spin_lock_init(&sky2->tx_lock);
3089 /* Auto speed and flow control */
3090 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3091 sky2->tx_pause = 1;
cd28ab6a
SH		 3092 sky2->rx_pause = 1;
3093 sky2->duplex = -1;
3094 sky2->speed = -1;
3095 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3096 sky2->rx_csum = 1;
75d070c5 3097
e07b1aa8 3098 spin_lock_init(&sky2->phy_lock);
793b883e 3099 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3100 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3101 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3102
3103 hw->dev[port] = dev;
3104
3105 sky2->port = port;
3106
5a5b1ea0 3107 dev->features |= NETIF_F_LLTX;
3108 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3109 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3110 if (highmem)
3111 dev->features |= NETIF_F_HIGHDMA;
793b883e 3112 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3113
d1f13708 3114#ifdef SKY2_VLAN_TAG_USED
3115 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3116 dev->vlan_rx_register = sky2_vlan_rx_register;
3117 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3118#endif
3119
cd28ab6a 3120 /* read the mac address */
793b883e 3121 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3122 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3123
3124 /* device is off until link detection */
3125 netif_carrier_off(dev);
3126 netif_stop_queue(dev);
3127
3128 return dev;
3129}
3130
28bd181a 3131static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3132{
3133 const struct sky2_port *sky2 = netdev_priv(dev);
3134
3135 if (netif_msg_probe(sky2))
3136 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3137 dev->name,
3138 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3139 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3140}
3141
fb2690a9
SH		 3142/* Handle software interrupt used during MSI test */
3143static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3144 struct pt_regs *regs)
3145{
3146 struct sky2_hw *hw = dev_id;
3147 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3148
3149 if (status == 0)
3150 return IRQ_NONE;
3151
3152 if (status & Y2_IS_IRQ_SW) {
3153 hw->msi_detected = 1;
3154 wake_up(&hw->msi_wait);
3155 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3156 }
3157 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3158
3159 return IRQ_HANDLED;
3160}
3161
3162/* Test interrupt path by forcing a a software IRQ */
3163static int __devinit sky2_test_msi(struct sky2_hw *hw)
3164{
3165 struct pci_dev *pdev = hw->pdev;
3166 int err;
3167
bb507fe1 3168 init_waitqueue_head (&hw->msi_wait);
3169
fb2690a9
SH		 3170 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3171
1fb9df5d 3172 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3173 if (err) {
3174 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3175 pci_name(pdev), pdev->irq);
3176 return err;
3177 }
3178
fb2690a9 3179 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3180 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3181
3182 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3183
3184 if (!hw->msi_detected) {
3185 /* MSI test failed, go back to INTx mode */
3186 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3187 "switching to INTx mode. Please report this failure to "
3188 "the PCI maintainer and include system chipset information.\n",
3189 pci_name(pdev));
3190
3191 err = -EOPNOTSUPP;
3192 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3193 }
3194
3195 sky2_write32(hw, B0_IMSK, 0);
3196
3197 free_irq(pdev->irq, hw);
3198
3199 return err;
3200}
3201
cd28ab6a
SH		 3202static int __devinit sky2_probe(struct pci_dev *pdev,
3203 const struct pci_device_id *ent)
3204{
793b883e 3205 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3206 struct sky2_hw *hw;
5afa0a9c 3207 int err, pm_cap, using_dac = 0;
cd28ab6a 3208
793b883e
SH		 3209 err = pci_enable_device(pdev);
3210 if (err) {
cd28ab6a
SH		 3211 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3212 pci_name(pdev));
3213 goto err_out;
3214 }
3215
793b883e
SH		 3216 err = pci_request_regions(pdev, DRV_NAME);
3217 if (err) {
cd28ab6a
SH		 3218 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3219 pci_name(pdev));
793b883e 3220 goto err_out;
cd28ab6a
SH		 3221 }
3222
3223 pci_set_master(pdev);
3224
5afa0a9c 3225 /* Find power-management capability. */
3226 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3227 if (pm_cap == 0) {
3228 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3229 "aborting.\n");
3230 err = -EIO;
3231 goto err_out_free_regions;
3232 }
3233
d1f3d4dd
SH		 3234 if (sizeof(dma_addr_t) > sizeof(u32) &&
3235 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3236 using_dac = 1;
3237 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3238 if (err < 0) {
3239 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3240 "for consistent allocations\n", pci_name(pdev));
3241 goto err_out_free_regions;
3242 }
cd28ab6a 3243
d1f3d4dd 3244 } else {
cd28ab6a
SH		 3245 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3246 if (err) {
3247 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3248 pci_name(pdev));
3249 goto err_out_free_regions;
3250 }
3251 }
d1f3d4dd 3252
cd28ab6a 3253 err = -ENOMEM;
6aad85d6 3254 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3255 if (!hw) {
3256 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3257 pci_name(pdev));
3258 goto err_out_free_regions;
3259 }
3260
cd28ab6a 3261 hw->pdev = pdev;
cd28ab6a
SH		 3262
3263 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3264 if (!hw->regs) {
3265 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3266 pci_name(pdev));
3267 goto err_out_free_hw;
3268 }
5afa0a9c 3269 hw->pm_cap = pm_cap;
cd28ab6a 3270
56a645cc
SH		 3271#ifdef __BIG_ENDIAN
3272 /* byte swap descriptors in hardware */
3273 {
3274 u32 reg;
3275
3276 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3277 reg |= PCI_REV_DESC;
3278 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3279 }
3280#endif
3281
08c06d8a
SH		 3282 /* ring for status responses */
3283 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3284 &hw->st_dma);
3285 if (!hw->st_le)
3286 goto err_out_iounmap;
3287
cd28ab6a
SH		 3288 err = sky2_reset(hw);
3289 if (err)
793b883e 3290 goto err_out_iounmap;
cd28ab6a 3291
7c7459d1
GKH		 3292 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3293 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3294 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3295 hw->chip_id, hw->chip_rev);
cd28ab6a 3296
793b883e
SH		 3297 dev = sky2_init_netdev(hw, 0, using_dac);
3298 if (!dev)
cd28ab6a
SH		 3299 goto err_out_free_pci;
3300
793b883e
SH		 3301 err = register_netdev(dev);
3302 if (err) {
cd28ab6a
SH		 3303 printk(KERN_ERR PFX "%s: cannot register net device\n",
3304 pci_name(pdev));
3305 goto err_out_free_netdev;
3306 }
3307
3308 sky2_show_addr(dev);
3309
3310 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3311 if (register_netdev(dev1) == 0)
3312 sky2_show_addr(dev1);
3313 else {
3314 /* Failure to register second port need not be fatal */
793b883e
SH		 3315 printk(KERN_WARNING PFX
3316 "register of second port failed\n");
cd28ab6a
SH		 3317 hw->dev[1] = NULL;
3318 free_netdev(dev1);
3319 }
3320 }
3321
fb2690a9
SH		 3322 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3323 err = sky2_test_msi(hw);
3324 if (err == -EOPNOTSUPP)
3325 pci_disable_msi(pdev);
3326 else if (err)
3327 goto err_out_unregister;
3328 }
3329
1fb9df5d 3330 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
793b883e
SH		 3331 if (err) {
3332 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3333 pci_name(pdev), pdev->irq);
3334 goto err_out_unregister;
3335 }
3336
e07b1aa8 3337 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3338
01bd7564 3339 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3340 sky2_idle_start(hw);
d27ed387 3341
793b883e
SH		 3342 pci_set_drvdata(pdev, hw);
3343
cd28ab6a
SH		 3344 return 0;
3345
793b883e 3346err_out_unregister:
fb2690a9 3347 pci_disable_msi(pdev);
793b883e
SH		 3348 if (dev1) {
3349 unregister_netdev(dev1);
3350 free_netdev(dev1);
3351 }
3352 unregister_netdev(dev);
cd28ab6a
SH		 3353err_out_free_netdev:
3354 free_netdev(dev);
cd28ab6a 3355err_out_free_pci:
793b883e 3356 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3357 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3358err_out_iounmap:
3359 iounmap(hw->regs);
3360err_out_free_hw:
3361 kfree(hw);
3362err_out_free_regions:
3363 pci_release_regions(pdev);
cd28ab6a 3364 pci_disable_device(pdev);
cd28ab6a
SH		 3365err_out:
3366 return err;
3367}
3368
3369static void __devexit sky2_remove(struct pci_dev *pdev)
3370{
793b883e 3371 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3372 struct net_device *dev0, *dev1;
3373
793b883e 3374 if (!hw)
cd28ab6a
SH		 3375 return;
3376
d27ed387
SH		 3377 del_timer_sync(&hw->idle_timer);
3378
3379 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3380 synchronize_irq(hw->pdev->irq);
3381
cd28ab6a 3382 dev0 = hw->dev[0];
793b883e
SH		 3383 dev1 = hw->dev[1];
3384 if (dev1)
3385 unregister_netdev(dev1);
cd28ab6a
SH		 3386 unregister_netdev(dev0);
3387
5afa0a9c 3388 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3389 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3390 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3391 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3392
3393 free_irq(pdev->irq, hw);
fb2690a9 3394 pci_disable_msi(pdev);
793b883e 3395 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3396 pci_release_regions(pdev);
3397 pci_disable_device(pdev);
793b883e 3398
cd28ab6a
SH		 3399 if (dev1)
3400 free_netdev(dev1);
3401 free_netdev(dev0);
3402 iounmap(hw->regs);
3403 kfree(hw);
5afa0a9c 3404
cd28ab6a
SH		 3405 pci_set_drvdata(pdev, NULL);
3406}
3407
3408#ifdef CONFIG_PM
3409static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3410{
793b883e 3411 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3412 int i;
2ccc99b7
SH		 3413 pci_power_t pstate = pci_choose_state(pdev, state);
3414
3415 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3416 return -EINVAL;
cd28ab6a 3417
eb35cf60 3418 del_timer_sync(&hw->idle_timer);
6a5706b9 3419 netif_poll_disable(hw->dev[0]);
eb35cf60 3420
f05267e7 3421 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3422 struct net_device *dev = hw->dev[i];
3423
6a5706b9 3424 if (netif_running(dev)) {
5afa0a9c 3425 sky2_down(dev);
cd28ab6a 3426 netif_device_detach(dev);
cd28ab6a
SH		 3427 }
3428 }
3429
8ab8fca2 3430 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3431 pci_save_state(pdev);
2ccc99b7
SH		 3432 sky2_set_power_state(hw, pstate);
3433 return 0;
cd28ab6a
SH		 3434}
3435
3436static int sky2_resume(struct pci_dev *pdev)
3437{
793b883e 3438 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3439 int i, err;
cd28ab6a 3440
cd28ab6a
SH		 3441 pci_restore_state(pdev);
3442 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3443 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3444
08c06d8a
SH		 3445 err = sky2_reset(hw);
3446 if (err)
3447 goto out;
cd28ab6a 3448
8ab8fca2
SH		 3449 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3450
f05267e7 3451 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3452 struct net_device *dev = hw->dev[i];
6a5706b9 3453 if (netif_running(dev)) {
08c06d8a 3454 netif_device_attach(dev);
88d11360 3455
08c06d8a
SH		 3456 err = sky2_up(dev);
3457 if (err) {
3458 printk(KERN_ERR PFX "%s: could not up: %d\n",
3459 dev->name, err);
3460 dev_close(dev);
eb35cf60 3461 goto out;
5afa0a9c 3462 }
cd28ab6a
SH		 3463 }
3464 }
eb35cf60 3465
6a5706b9 3466 netif_poll_enable(hw->dev[0]);
eb35cf60 3467 sky2_idle_start(hw);
08c06d8a
SH		 3468out:
3469 return err;
cd28ab6a
SH		 3470}
3471#endif
3472
3473static struct pci_driver sky2_driver = {
793b883e
SH		 3474 .name = DRV_NAME,
3475 .id_table = sky2_id_table,
3476 .probe = sky2_probe,
3477 .remove = __devexit_p(sky2_remove),
cd28ab6a 3478#ifdef CONFIG_PM
793b883e
SH		 3479 .suspend = sky2_suspend,
3480 .resume = sky2_resume,
cd28ab6a
SH		 3481#endif
3482};
3483
3484static int __init sky2_init_module(void)
3485{
50241c4c 3486 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3487}
3488
3489static void __exit sky2_cleanup_module(void)
3490{
3491 pci_unregister_driver(&sky2_driver);
3492}
3493
3494module_init(sky2_init_module);
3495module_exit(sky2_cleanup_module);
3496
3497MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3498MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3499MODULE_LICENSE("GPL");
5f4f9dc1 3500MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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