projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Linux 2.6.23-rc8
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
faf60e72 54#define DRV_VERSION "1.18"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
e5b74c7d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 136 { 0 }
137};
793b883e 138
cd28ab6a
SH		 139MODULE_DEVICE_TABLE(pci, sky2_id_table);
140
141/* Avoid conditionals by using array */
142static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 144static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 145
92f965e8
SH		 146/* This driver supports yukon2 chipset only */
147static const char *yukon2_name[] = {
148 "XL", /* 0xb3 */
149 "EC Ultra", /* 0xb4 */
93745494 150 "Extreme", /* 0xb5 */
92f965e8
SH		 151 "EC", /* 0xb6 */
152 "FE", /* 0xb7 */
05745c4a 153 "FE+", /* 0xb8 */
793b883e
SH		 154};
155
d1b139c0
SH		 156static void sky2_set_multicast(struct net_device *dev);
157
793b883e 158/* Access to external PHY */
ef743d33 159static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 160{
161 int i;
162
163 gma_write16(hw, port, GM_SMI_DATA, val);
164 gma_write16(hw, port, GM_SMI_CTRL,
165 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
166
167 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 168 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 169 return 0;
793b883e 170 udelay(1);
cd28ab6a 171 }
ef743d33 172
793b883e 173 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 174 return -ETIMEDOUT;
cd28ab6a
SH		 175}
176
ef743d33 177static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 178{
179 int i;
180
793b883e 181 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 182 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
183
184 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 185 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
186 *val = gma_read16(hw, port, GM_SMI_DATA);
187 return 0;
188 }
189
793b883e 190 udelay(1);
cd28ab6a
SH		 191 }
192
ef743d33 193 return -ETIMEDOUT;
194}
195
196static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
197{
198 u16 v;
199
200 if (__gm_phy_read(hw, port, reg, &v) != 0)
201 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
202 return v;
cd28ab6a
SH		 203}
204
5afa0a9c 205
ae306cca
SH		 206static void sky2_power_on(struct sky2_hw *hw)
207{
208 /* switch power to VCC (WA for VAUX problem) */
209 sky2_write8(hw, B0_POWER_CTRL,
210 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 211
ae306cca
SH		 212 /* disable Core Clock Division, */
213 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 214
ae306cca
SH		 215 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
216 /* enable bits are inverted */
217 sky2_write8(hw, B2_Y2_CLK_GATE,
218 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
219 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
220 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
221 else
222 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 223
ea76e635 224 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 225 u32 reg;
5afa0a9c 226
b2345773
SH		 227 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
228
fc99fe06
SH		 229 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
230 /* set all bits to 0 except bits 15..12 and 8 */
231 reg &= P_ASPM_CONTROL_MSK;
232 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
233
234 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
235 /* set all bits to 0 except bits 28 & 27 */
236 reg &= P_CTL_TIM_VMAIN_AV_MSK;
237 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
238
239 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 240
241 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
242 reg = sky2_read32(hw, B2_GP_IO);
243 reg |= GLB_GPIO_STAT_RACE_DIS;
244 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 245
246 sky2_read32(hw, B2_GP_IO);
5afa0a9c 247 }
ae306cca 248}
5afa0a9c 249
ae306cca
SH		 250static void sky2_power_aux(struct sky2_hw *hw)
251{
252 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
253 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
254 else
255 /* enable bits are inverted */
256 sky2_write8(hw, B2_Y2_CLK_GATE,
257 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
258 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
259 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
260
261 /* switch power to VAUX */
262 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
263 sky2_write8(hw, B0_POWER_CTRL,
264 (PC_VAUX_ENA | PC_VCC_ENA |
265 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
16ad91e1
SH		 287/* flow control to advertise bits */
288static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293};
294
295/* flow control to advertise bits when using 1000BaseX */
296static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301};
302
303/* flow control to GMA disable bits */
304static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309};
310
311
cd28ab6a
SH		 312static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
313{
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 316
ea76e635
SH		 317 if (sky2->autoneg == AUTONEG_ENABLE &&
318 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 322 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324
53419c68 325 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 326 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 327 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 328 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
329 else
53419c68
SH		 330 /* set master & slave downshift counter to 1x */
331 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 332
333 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
334 }
335
336 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 337 if (sky2_is_copper(hw)) {
05745c4a 338 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
341 } else {
342 /* disable energy detect */
343 ctrl &= ~PHY_M_PC_EN_DET_MSK;
344
345 /* enable automatic crossover */
346 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
347
53419c68 348 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 349 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 350 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 351 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 352 ctrl &= ~PHY_M_PC_DSC_MSK;
353 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
354 }
355 }
cd28ab6a
SH		 356 } else {
357 /* workaround for deviation #4.88 (CRC errors) */
358 /* disable Automatic Crossover */
359
360 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 361 }
cd28ab6a 362
b89165f2
SH		 363 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
364
365 /* special setup for PHY 88E1112 Fiber */
ea76e635 366 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 367 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 368
b89165f2
SH		 369 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
370 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
371 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
372 ctrl &= ~PHY_M_MAC_MD_MSK;
373 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
374 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
375
376 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 377 /* select page 1 to access Fiber registers */
378 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 379
380 /* for SFP-module set SIGDET polarity to low */
381 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
382 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 383 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 384 }
b89165f2
SH		 385
386 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 387 }
388
7800fddc 389 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 390 ct1000 = 0;
391 adv = PHY_AN_CSMA;
2eaba1a2 392 reg = 0;
cd28ab6a
SH		 393
394 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 395 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 396 if (sky2->advertising & ADVERTISED_1000baseT_Full)
397 ct1000 |= PHY_M_1000C_AFD;
398 if (sky2->advertising & ADVERTISED_1000baseT_Half)
399 ct1000 |= PHY_M_1000C_AHD;
400 if (sky2->advertising & ADVERTISED_100baseT_Full)
401 adv |= PHY_M_AN_100_FD;
402 if (sky2->advertising & ADVERTISED_100baseT_Half)
403 adv |= PHY_M_AN_100_HD;
404 if (sky2->advertising & ADVERTISED_10baseT_Full)
405 adv |= PHY_M_AN_10_FD;
406 if (sky2->advertising & ADVERTISED_10baseT_Half)
407 adv |= PHY_M_AN_10_HD;
709c6e7b 408
16ad91e1 409 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 410 } else { /* special defines for FIBER (88E1040S only) */
411 if (sky2->advertising & ADVERTISED_1000baseT_Full)
412 adv |= PHY_M_AN_1000X_AFD;
413 if (sky2->advertising & ADVERTISED_1000baseT_Half)
414 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 415
16ad91e1 416 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 417 }
cd28ab6a
SH		 418
419 /* Restart Auto-negotiation */
420 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
421 } else {
422 /* forced speed/duplex settings */
423 ct1000 = PHY_M_1000C_MSE;
424
2eaba1a2
SH		 425 /* Disable auto update for duplex flow control and speed */
426 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 427
428 switch (sky2->speed) {
429 case SPEED_1000:
430 ctrl |= PHY_CT_SP1000;
2eaba1a2 431 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 432 break;
433 case SPEED_100:
434 ctrl |= PHY_CT_SP100;
2eaba1a2 435 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 436 break;
437 }
438
2eaba1a2
SH		 439 if (sky2->duplex == DUPLEX_FULL) {
440 reg |= GM_GPCR_DUP_FULL;
441 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 442 } else if (sky2->speed < SPEED_1000)
443 sky2->flow_mode = FC_NONE;
2eaba1a2 444
2eaba1a2 445
16ad91e1 446 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 447
448 /* Forward pause packets to GMAC? */
16ad91e1 449 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 450 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
451 else
452 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 453 }
454
2eaba1a2
SH		 455 gma_write16(hw, port, GM_GP_CTRL, reg);
456
05745c4a 457 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 458 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
459
460 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
461 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
462
463 /* Setup Phy LED's */
464 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
465 ledover = 0;
466
467 switch (hw->chip_id) {
468 case CHIP_ID_YUKON_FE:
469 /* on 88E3082 these bits are at 11..9 (shifted left) */
470 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
471
472 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
473
474 /* delete ACT LED control bits */
475 ctrl &= ~PHY_M_FELP_LED1_MSK;
476 /* change ACT LED control to blink mode */
477 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
478 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
479 break;
480
05745c4a
SH		 481 case CHIP_ID_YUKON_FE_P:
482 /* Enable Link Partner Next Page */
483 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
484 ctrl |= PHY_M_PC_ENA_LIP_NP;
485
486 /* disable Energy Detect and enable scrambler */
487 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
488 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
489
490 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
491 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
492 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
493 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
494
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
cd28ab6a 498 case CHIP_ID_YUKON_XL:
793b883e 499 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 500
501 /* select page 3 to access LED control register */
502 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
503
504 /* set LED Function Control register */
ed6d32c7
SH		 505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
506 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
507 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
508 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
509 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 510
511 /* set Polarity Control register */
512 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 513 (PHY_M_POLC_LS1_P_MIX(4) |
514 PHY_M_POLC_IS0_P_MIX(4) |
515 PHY_M_POLC_LOS_CTRL(2) |
516 PHY_M_POLC_INIT_CTRL(2) |
517 PHY_M_POLC_STA1_CTRL(2) |
518 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 519
520 /* restore page register */
793b883e 521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 522 break;
93745494 523
ed6d32c7 524 case CHIP_ID_YUKON_EC_U:
93745494 525 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
527
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
530
531 /* set LED Function Control register */
532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
537
538 /* set Blink Rate in LED Timer Control Register */
539 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
540 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
541 /* restore page register */
542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
543 break;
cd28ab6a
SH		 544
545 default:
546 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
547 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
548 /* turn off the Rx LED (LED_RX) */
0efdf262 549 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 550 }
551
9467a8fc
SH		 552 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
553 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 554 /* apply fixes in PHY AFE */
ed6d32c7
SH		 555 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
556
977bdf06 557 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 558 gm_phy_write(hw, port, 0x18, 0xaa99);
559 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 560
977bdf06 561 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 562 gm_phy_write(hw, port, 0x18, 0xa204);
563 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 564
565 /* set page register to 0 */
9467a8fc 566 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 567 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
568 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
569 /* apply workaround for integrated resistors calibration */
570 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
571 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
93745494 572 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
05745c4a 573 /* no effect on Yukon-XL */
977bdf06 574 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 575
977bdf06
SH		 576 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
577 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 578 ledover |= PHY_M_LED_MO_100;
977bdf06 579 }
cd28ab6a 580
977bdf06
SH		 581 if (ledover)
582 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
583
584 }
2eaba1a2 585
d571b694 586 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 587 if (sky2->autoneg == AUTONEG_ENABLE)
588 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
589 else
590 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
591}
592
d3bcfbeb 593static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
594{
595 u32 reg1;
596 static const u32 phy_power[]
597 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
598
599 /* looks like this XL is back asswards .. */
600 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
601 onoff = !onoff;
602
aed2cec4 603 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 604 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 605 if (onoff)
606 /* Turn off phy power saving */
607 reg1 &= ~phy_power[port];
608 else
609 reg1 |= phy_power[port];
610
611 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 612 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 613 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 614 udelay(100);
615}
616
1b537565
SH		 617/* Force a renegotiation */
618static void sky2_phy_reinit(struct sky2_port *sky2)
619{
e07b1aa8 620 spin_lock_bh(&sky2->phy_lock);
1b537565 621 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 622 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 623}
624
e3173832
SH		 625/* Put device in state to listen for Wake On Lan */
626static void sky2_wol_init(struct sky2_port *sky2)
627{
628 struct sky2_hw *hw = sky2->hw;
629 unsigned port = sky2->port;
630 enum flow_control save_mode;
631 u16 ctrl;
632 u32 reg1;
633
634 /* Bring hardware out of reset */
635 sky2_write16(hw, B0_CTST, CS_RST_CLR);
636 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
637
638 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
639 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
640
641 /* Force to 10/100
642 * sky2_reset will re-enable on resume
643 */
644 save_mode = sky2->flow_mode;
645 ctrl = sky2->advertising;
646
647 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
648 sky2->flow_mode = FC_NONE;
649 sky2_phy_power(hw, port, 1);
650 sky2_phy_reinit(sky2);
651
652 sky2->flow_mode = save_mode;
653 sky2->advertising = ctrl;
654
655 /* Set GMAC to no flow control and auto update for speed/duplex */
656 gma_write16(hw, port, GM_GP_CTRL,
657 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
658 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
659
660 /* Set WOL address */
661 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
662 sky2->netdev->dev_addr, ETH_ALEN);
663
664 /* Turn on appropriate WOL control bits */
665 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
666 ctrl = 0;
667 if (sky2->wol & WAKE_PHY)
668 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
669 else
670 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
671
672 if (sky2->wol & WAKE_MAGIC)
673 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
674 else
675 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
676
677 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
678 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
679
680 /* Turn on legacy PCI-Express PME mode */
681 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
682 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
683 reg1 |= PCI_Y2_PME_LEGACY;
684 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
685 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
686
687 /* block receiver */
688 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
689
690}
691
69161611
SH		 692static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
693{
05745c4a
SH		 694 struct net_device *dev = hw->dev[port];
695
696 if (dev->mtu <= ETH_DATA_LEN)
69161611 697 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
05745c4a
SH		 698 TX_JUMBO_DIS | TX_STFW_ENA);
699
700 else if (hw->chip_id != CHIP_ID_YUKON_EC_U)
701 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
702 TX_STFW_ENA | TX_JUMBO_ENA);
703 else {
704 /* set Tx GMAC FIFO Almost Empty Threshold */
705 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
706 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 707
05745c4a
SH		 708 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
709 TX_JUMBO_ENA | TX_STFW_DIS);
69161611 710
05745c4a
SH		 711 /* Can't do offload because of lack of store/forward */
712 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
69161611
SH		 713 }
714}
715
cd28ab6a
SH		 716static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
717{
718 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
719 u16 reg;
25cccecc 720 u32 rx_reg;
cd28ab6a
SH		 721 int i;
722 const u8 *addr = hw->dev[port]->dev_addr;
723
f350339c
SH		 724 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
725 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 726
727 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
728
793b883e 729 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 730 /* WA DEV_472 -- looks like crossed wires on port 2 */
731 /* clear GMAC 1 Control reset */
732 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
733 do {
734 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
735 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
736 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
737 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
738 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
739 }
740
793b883e 741 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 742
2eaba1a2
SH		 743 /* Enable Transmit FIFO Underrun */
744 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
745
e07b1aa8 746 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 747 sky2_phy_init(hw, port);
e07b1aa8 748 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 749
750 /* MIB clear */
751 reg = gma_read16(hw, port, GM_PHY_ADDR);
752 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
753
43f2f104
SH		 754 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
755 gma_read16(hw, port, i);
cd28ab6a
SH		 756 gma_write16(hw, port, GM_PHY_ADDR, reg);
757
758 /* transmit control */
759 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
760
761 /* receive control reg: unicast + multicast + no FCS */
762 gma_write16(hw, port, GM_RX_CTRL,
793b883e 763 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 764
765 /* transmit flow control */
766 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
767
768 /* transmit parameter */
769 gma_write16(hw, port, GM_TX_PARAM,
770 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
771 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
772 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
773 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
774
775 /* serial mode register */
776 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 777 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 778
6b1a3aef 779 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 780 reg |= GM_SMOD_JUMBO_ENA;
781
782 gma_write16(hw, port, GM_SERIAL_MODE, reg);
783
cd28ab6a
SH		 784 /* virtual address for data */
785 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
786
793b883e
SH		 787 /* physical address: used for pause frames */
788 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
789
790 /* ignore counter overflows */
cd28ab6a
SH		 791 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
792 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
793 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
794
795 /* Configure Rx MAC FIFO */
796 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 797 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 798 if (hw->chip_id == CHIP_ID_YUKON_EX ||
799 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 800 rx_reg |= GMF_RX_OVER_ON;
69161611 801
25cccecc 802 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 803
d571b694 804 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 805 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 806
8df9a876 807 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 808 reg = RX_GMF_FL_THR_DEF + 1;
809 /* Another magic mystery workaround from sk98lin */
810 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
811 hw->chip_rev == CHIP_REV_YU_FE2_A0)
812 reg = 0x178;
813 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 814
815 /* Configure Tx MAC FIFO */
816 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
817 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 818
ea76e635 819 if (!(hw->flags & SKY2_HW_RAMBUFFER)) {
8df9a876 820 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 821 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 822
69161611 823 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 824 }
825
cd28ab6a
SH		 826}
827
67712901
SH		 828/* Assign Ram Buffer allocation to queue */
829static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 830{
67712901
SH		 831 u32 end;
832
833 /* convert from K bytes to qwords used for hw register */
834 start *= 1024/8;
835 space *= 1024/8;
836 end = start + space - 1;
793b883e 837
cd28ab6a
SH		 838 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
839 sky2_write32(hw, RB_ADDR(q, RB_START), start);
840 sky2_write32(hw, RB_ADDR(q, RB_END), end);
841 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
842 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
843
844 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 845 u32 tp = space - space/4;
793b883e 846
1c28f6ba
SH		 847 /* On receive queue's set the thresholds
848 * give receiver priority when > 3/4 full
849 * send pause when down to 2K
850 */
851 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
852 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 853
1c28f6ba
SH		 854 tp = space - 2048/8;
855 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
856 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 857 } else {
858 /* Enable store & forward on Tx queue's because
859 * Tx FIFO is only 1K on Yukon
860 */
861 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
862 }
863
864 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 865 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 866}
867
cd28ab6a 868/* Setup Bus Memory Interface */
af4ed7e6 869static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 870{
871 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
872 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
873 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 874 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 875}
876
cd28ab6a
SH		 877/* Setup prefetch unit registers. This is the interface between
878 * hardware and driver list elements
879 */
8cc048e3 880static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 881 u64 addr, u32 last)
882{
cd28ab6a
SH		 883 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
884 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
885 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
886 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
887 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
888 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 889
890 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 891}
892
793b883e
SH		 893static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
894{
895 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
896
cb5d9547 897 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 898 le->ctrl = 0;
793b883e
SH		 899 return le;
900}
cd28ab6a 901
291ea614
SH		 902static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
903 struct sky2_tx_le *le)
904{
905 return sky2->tx_ring + (le - sky2->tx_le);
906}
907
290d4de5
SH		 908/* Update chip's next pointer */
909static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 910{
50432cb5 911 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 912 wmb();
50432cb5
SH		 913 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
914
915 /* Synchronize I/O on since next processor may write to tail */
916 mmiowb();
cd28ab6a
SH		 917}
918
793b883e 919
cd28ab6a
SH		 920static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
921{
922 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 923 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 924 le->ctrl = 0;
cd28ab6a
SH		 925 return le;
926}
927
14d0263f
SH		 928/* Build description to hardware for one receive segment */
929static void sky2_rx_add(struct sky2_port *sky2, u8 op,
930 dma_addr_t map, unsigned len)
cd28ab6a
SH		 931{
932 struct sky2_rx_le *le;
36eb0c71 933 u32 hi = upper_32_bits(map);
cd28ab6a 934
793b883e 935 if (sky2->rx_addr64 != hi) {
cd28ab6a 936 le = sky2_next_rx(sky2);
793b883e 937 le->addr = cpu_to_le32(hi);
cd28ab6a 938 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 939 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 940 }
793b883e 941
cd28ab6a 942 le = sky2_next_rx(sky2);
734d1868
SH		 943 le->addr = cpu_to_le32((u32) map);
944 le->length = cpu_to_le16(len);
14d0263f 945 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 946}
947
14d0263f
SH		 948/* Build description to hardware for one possibly fragmented skb */
949static void sky2_rx_submit(struct sky2_port *sky2,
950 const struct rx_ring_info *re)
951{
952 int i;
953
954 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
955
956 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
957 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
958}
959
960
961static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
962 unsigned size)
963{
964 struct sk_buff *skb = re->skb;
965 int i;
966
967 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
968 pci_unmap_len_set(re, data_size, size);
969
970 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
971 re->frag_addr[i] = pci_map_page(pdev,
972 skb_shinfo(skb)->frags[i].page,
973 skb_shinfo(skb)->frags[i].page_offset,
974 skb_shinfo(skb)->frags[i].size,
975 PCI_DMA_FROMDEVICE);
976}
977
978static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
979{
980 struct sk_buff *skb = re->skb;
981 int i;
982
983 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
984 PCI_DMA_FROMDEVICE);
985
986 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
987 pci_unmap_page(pdev, re->frag_addr[i],
988 skb_shinfo(skb)->frags[i].size,
989 PCI_DMA_FROMDEVICE);
990}
793b883e 991
cd28ab6a
SH		 992/* Tell chip where to start receive checksum.
993 * Actually has two checksums, but set both same to avoid possible byte
994 * order problems.
995 */
793b883e 996static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 997{
ea76e635 998 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 999
ea76e635
SH		 1000 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1001 le->ctrl = 0;
1002 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1003
ea76e635
SH		 1004 sky2_write32(sky2->hw,
1005 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1006 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1007}
1008
6b1a3aef 1009/*
1010 * The RX Stop command will not work for Yukon-2 if the BMU does not
1011 * reach the end of packet and since we can't make sure that we have
1012 * incoming data, we must reset the BMU while it is not doing a DMA
1013 * transfer. Since it is possible that the RX path is still active,
1014 * the RX RAM buffer will be stopped first, so any possible incoming
1015 * data will not trigger a DMA. After the RAM buffer is stopped, the
1016 * BMU is polled until any DMA in progress is ended and only then it
1017 * will be reset.
1018 */
1019static void sky2_rx_stop(struct sky2_port *sky2)
1020{
1021 struct sky2_hw *hw = sky2->hw;
1022 unsigned rxq = rxqaddr[sky2->port];
1023 int i;
1024
1025 /* disable the RAM Buffer receive queue */
1026 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1027
1028 for (i = 0; i < 0xffff; i++)
1029 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1030 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1031 goto stopped;
1032
1033 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1034 sky2->netdev->name);
1035stopped:
1036 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1037
1038 /* reset the Rx prefetch unit */
1039 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1040 mmiowb();
6b1a3aef 1041}
793b883e 1042
d571b694 1043/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1044static void sky2_rx_clean(struct sky2_port *sky2)
1045{
1046 unsigned i;
1047
1048 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1049 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1050 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1051
1052 if (re->skb) {
14d0263f 1053 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1054 kfree_skb(re->skb);
1055 re->skb = NULL;
1056 }
1057 }
1058}
1059
ef743d33 1060/* Basic MII support */
1061static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1062{
1063 struct mii_ioctl_data *data = if_mii(ifr);
1064 struct sky2_port *sky2 = netdev_priv(dev);
1065 struct sky2_hw *hw = sky2->hw;
1066 int err = -EOPNOTSUPP;
1067
1068 if (!netif_running(dev))
1069 return -ENODEV; /* Phy still in reset */
1070
d89e1343 1071 switch (cmd) {
ef743d33 1072 case SIOCGMIIPHY:
1073 data->phy_id = PHY_ADDR_MARV;
1074
1075 /* fallthru */
1076 case SIOCGMIIREG: {
1077 u16 val = 0;
91c86df5 1078
e07b1aa8 1079 spin_lock_bh(&sky2->phy_lock);
ef743d33 1080 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1081 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1082
ef743d33 1083 data->val_out = val;
1084 break;
1085 }
1086
1087 case SIOCSMIIREG:
1088 if (!capable(CAP_NET_ADMIN))
1089 return -EPERM;
1090
e07b1aa8 1091 spin_lock_bh(&sky2->phy_lock);
ef743d33 1092 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1093 data->val_in);
e07b1aa8 1094 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1095 break;
1096 }
1097 return err;
1098}
1099
d1f13708 1100#ifdef SKY2_VLAN_TAG_USED
1101static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1102{
1103 struct sky2_port *sky2 = netdev_priv(dev);
1104 struct sky2_hw *hw = sky2->hw;
1105 u16 port = sky2->port;
d1f13708 1106
2bb8c262 1107 netif_tx_lock_bh(dev);
3d4e66f5 1108 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1109
d1f13708 1110 sky2->vlgrp = grp;
3d4e66f5
SH		 1111 if (grp) {
1112 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1113 RX_VLAN_STRIP_ON);
1114 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1115 TX_VLAN_TAG_ON);
1116 } else {
1117 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1118 RX_VLAN_STRIP_OFF);
1119 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1120 TX_VLAN_TAG_OFF);
1121 }
d1f13708 1122
3d4e66f5 1123 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1124 netif_tx_unlock_bh(dev);
d1f13708 1125}
1126#endif
1127
82788c7a 1128/*
14d0263f
SH		 1129 * Allocate an skb for receiving. If the MTU is large enough
1130 * make the skb non-linear with a fragment list of pages.
1131 *
82788c7a
SH		 1132 * It appears the hardware has a bug in the FIFO logic that
1133 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1134 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1135 * aligned except if slab debugging is enabled.
82788c7a 1136 */
14d0263f 1137static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1138{
1139 struct sk_buff *skb;
14d0263f
SH		 1140 unsigned long p;
1141 int i;
82788c7a 1142
14d0263f
SH		 1143 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1144 if (!skb)
1145 goto nomem;
1146
1147 p = (unsigned long) skb->data;
1148 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1149
1150 for (i = 0; i < sky2->rx_nfrags; i++) {
1151 struct page *page = alloc_page(GFP_ATOMIC);
1152
1153 if (!page)
1154 goto free_partial;
1155 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1156 }
1157
1158 return skb;
14d0263f
SH		 1159free_partial:
1160 kfree_skb(skb);
1161nomem:
1162 return NULL;
82788c7a
SH		 1163}
1164
55c9dd35
SH		 1165static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1166{
1167 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1168}
1169
cd28ab6a
SH		 1170/*
1171 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1172 * Normal case this ends up creating one list element for skb
1173 * in the receive ring. Worst case if using large MTU and each
1174 * allocation falls on a different 64 bit region, that results
1175 * in 6 list elements per ring entry.
1176 * One element is used for checksum enable/disable, and one
1177 * extra to avoid wrap.
cd28ab6a 1178 */
6b1a3aef 1179static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1180{
6b1a3aef 1181 struct sky2_hw *hw = sky2->hw;
14d0263f 1182 struct rx_ring_info *re;
6b1a3aef 1183 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1184 unsigned i, size, space, thresh;
cd28ab6a 1185
6b1a3aef 1186 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1187 sky2_qset(hw, rxq);
977bdf06 1188
c3905bc4
SH		 1189 /* On PCI express lowering the watermark gives better performance */
1190 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1191 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1192
1193 /* These chips have no ram buffer?
1194 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1195 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1196 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1197 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1198 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1199
6b1a3aef 1200 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1201
ea76e635
SH		 1202 if (!(hw->flags & SKY2_HW_NEW_LE))
1203 rx_set_checksum(sky2);
14d0263f
SH		 1204
1205 /* Space needed for frame data + headers rounded up */
f957da2a 1206 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1207
1208 /* Stopping point for hardware truncation */
1209 thresh = (size - 8) / sizeof(u32);
1210
1211 /* Account for overhead of skb - to avoid order > 0 allocation */
1212 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1213 + sizeof(struct skb_shared_info);
1214
1215 sky2->rx_nfrags = space >> PAGE_SHIFT;
1216 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1217
1218 if (sky2->rx_nfrags != 0) {
1219 /* Compute residue after pages */
1220 space = sky2->rx_nfrags << PAGE_SHIFT;
1221
1222 if (space < size)
1223 size -= space;
1224 else
1225 size = 0;
1226
1227 /* Optimize to handle small packets and headers */
1228 if (size < copybreak)
1229 size = copybreak;
1230 if (size < ETH_HLEN)
1231 size = ETH_HLEN;
1232 }
1233 sky2->rx_data_size = size;
1234
1235 /* Fill Rx ring */
793b883e 1236 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1237 re = sky2->rx_ring + i;
cd28ab6a 1238
14d0263f 1239 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1240 if (!re->skb)
1241 goto nomem;
1242
14d0263f
SH		 1243 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1244 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1245 }
1246
a1433ac4
SH		 1247 /*
1248 * The receiver hangs if it receives frames larger than the
1249 * packet buffer. As a workaround, truncate oversize frames, but
1250 * the register is limited to 9 bits, so if you do frames > 2052
1251 * you better get the MTU right!
1252 */
a1433ac4
SH		 1253 if (thresh > 0x1ff)
1254 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1255 else {
1256 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1257 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1258 }
1259
6b1a3aef 1260 /* Tell chip about available buffers */
55c9dd35 1261 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1262 return 0;
1263nomem:
1264 sky2_rx_clean(sky2);
1265 return -ENOMEM;
1266}
1267
1268/* Bring up network interface. */
1269static int sky2_up(struct net_device *dev)
1270{
1271 struct sky2_port *sky2 = netdev_priv(dev);
1272 struct sky2_hw *hw = sky2->hw;
1273 unsigned port = sky2->port;
ea76e635 1274 u32 imask;
ee7abb04 1275 int cap, err = -ENOMEM;
843a46f4 1276 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1277
ee7abb04
SH		 1278 /*
1279 * On dual port PCI-X card, there is an problem where status
1280 * can be received out of order due to split transactions
843a46f4 1281 */
ee7abb04
SH		 1282 if (otherdev && netif_running(otherdev) &&
1283 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1284 struct sky2_port *osky2 = netdev_priv(otherdev);
1285 u16 cmd;
1286
1287 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1288 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1289 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1290
1291 sky2->rx_csum = 0;
1292 osky2->rx_csum = 0;
1293 }
843a46f4 1294
cd28ab6a
SH		 1295 if (netif_msg_ifup(sky2))
1296 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1297
55d7b4e6
SH		 1298 netif_carrier_off(dev);
1299
cd28ab6a
SH		 1300 /* must be power of 2 */
1301 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1302 TX_RING_SIZE *
1303 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1304 &sky2->tx_le_map);
1305 if (!sky2->tx_le)
1306 goto err_out;
1307
6cdbbdf3 1308 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1309 GFP_KERNEL);
1310 if (!sky2->tx_ring)
1311 goto err_out;
1312 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1313
1314 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1315 &sky2->rx_le_map);
1316 if (!sky2->rx_le)
1317 goto err_out;
1318 memset(sky2->rx_le, 0, RX_LE_BYTES);
1319
291ea614 1320 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1321 GFP_KERNEL);
1322 if (!sky2->rx_ring)
1323 goto err_out;
1324
d3bcfbeb 1325 sky2_phy_power(hw, port, 1);
1326
cd28ab6a
SH		 1327 sky2_mac_init(hw, port);
1328
ea76e635
SH		 1329 if (hw->flags & SKY2_HW_RAMBUFFER) {
1330 /* Register is number of 4K blocks on internal RAM buffer. */
1331 u32 ramsize = sky2_read8(hw, B2_E_0) * 4;
67712901 1332 u32 rxspace;
cd28ab6a 1333
ea76e635
SH		 1334 printk(KERN_DEBUG PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1335
67712901
SH		 1336 if (ramsize < 16)
1337 rxspace = ramsize / 2;
1338 else
1339 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1340
67712901
SH		 1341 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1342 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1343
1344 /* Make sure SyncQ is disabled */
1345 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1346 RB_RST_SET);
1347 }
793b883e 1348
af4ed7e6 1349 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1350
69161611
SH		 1351 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1352 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1353 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1354
977bdf06 1355 /* Set almost empty threshold */
c2716fb4
SH		 1356 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1357 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1358 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1359
6b1a3aef 1360 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1361 TX_RING_SIZE - 1);
cd28ab6a 1362
6b1a3aef 1363 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1364 if (err)
1365 goto err_out;
1366
cd28ab6a 1367 /* Enable interrupts from phy/mac for port */
e07b1aa8 1368 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1369 imask |= portirq_msk[port];
e07b1aa8
SH		 1370 sky2_write32(hw, B0_IMSK, imask);
1371
cd28ab6a
SH		 1372 return 0;
1373
1374err_out:
1b537565 1375 if (sky2->rx_le) {
cd28ab6a
SH		 1376 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1377 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1378 sky2->rx_le = NULL;
1379 }
1380 if (sky2->tx_le) {
cd28ab6a
SH		 1381 pci_free_consistent(hw->pdev,
1382 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1383 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1384 sky2->tx_le = NULL;
1385 }
1386 kfree(sky2->tx_ring);
1387 kfree(sky2->rx_ring);
cd28ab6a 1388
1b537565
SH		 1389 sky2->tx_ring = NULL;
1390 sky2->rx_ring = NULL;
cd28ab6a
SH		 1391 return err;
1392}
1393
793b883e
SH		 1394/* Modular subtraction in ring */
1395static inline int tx_dist(unsigned tail, unsigned head)
1396{
cb5d9547 1397 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1398}
cd28ab6a 1399
793b883e
SH		 1400/* Number of list elements available for next tx */
1401static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1402{
793b883e 1403 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1404}
1405
793b883e 1406/* Estimate of number of transmit list elements required */
28bd181a 1407static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1408{
793b883e
SH		 1409 unsigned count;
1410
1411 count = sizeof(dma_addr_t) / sizeof(u32);
1412 count += skb_shinfo(skb)->nr_frags * count;
1413
89114afd 1414 if (skb_is_gso(skb))
793b883e
SH		 1415 ++count;
1416
84fa7933 1417 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1418 ++count;
1419
1420 return count;
cd28ab6a
SH		 1421}
1422
793b883e
SH		 1423/*
1424 * Put one packet in ring for transmit.
1425 * A single packet can generate multiple list elements, and
1426 * the number of ring elements will probably be less than the number
1427 * of list elements used.
1428 */
cd28ab6a
SH		 1429static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1430{
1431 struct sky2_port *sky2 = netdev_priv(dev);
1432 struct sky2_hw *hw = sky2->hw;
d1f13708 1433 struct sky2_tx_le *le = NULL;
6cdbbdf3 1434 struct tx_ring_info *re;
cd28ab6a
SH		 1435 unsigned i, len;
1436 dma_addr_t mapping;
1437 u32 addr64;
1438 u16 mss;
1439 u8 ctrl;
1440
2bb8c262
SH		 1441 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1442 return NETDEV_TX_BUSY;
cd28ab6a 1443
793b883e 1444 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1445 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1446 dev->name, sky2->tx_prod, skb->len);
1447
cd28ab6a
SH		 1448 len = skb_headlen(skb);
1449 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1450 addr64 = upper_32_bits(mapping);
793b883e 1451
a018e330 1452 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1453 if (addr64 != sky2->tx_addr64 ||
1454 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1455 le = get_tx_le(sky2);
f65b138c 1456 le->addr = cpu_to_le32(addr64);
793b883e 1457 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1458 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1459 }
cd28ab6a
SH		 1460
1461 /* Check for TCP Segmentation Offload */
7967168c 1462 mss = skb_shinfo(skb)->gso_size;
793b883e 1463 if (mss != 0) {
ea76e635
SH		 1464
1465 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1466 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1467
1468 if (mss != sky2->tx_last_mss) {
1469 le = get_tx_le(sky2);
1470 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1471
1472 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1473 le->opcode = OP_MSS | HW_OWNER;
1474 else
1475 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1476 sky2->tx_last_mss = mss;
1477 }
cd28ab6a
SH		 1478 }
1479
cd28ab6a 1480 ctrl = 0;
d1f13708 1481#ifdef SKY2_VLAN_TAG_USED
1482 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1483 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1484 if (!le) {
1485 le = get_tx_le(sky2);
f65b138c 1486 le->addr = 0;
d1f13708 1487 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1488 } else
1489 le->opcode |= OP_VLAN;
1490 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1491 ctrl |= INS_VLAN;
1492 }
1493#endif
1494
1495 /* Handle TCP checksum offload */
84fa7933 1496 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1497 /* On Yukon EX (some versions) encoding change. */
ea76e635 1498 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1499 ctrl |= CALSUM; /* auto checksum */
1500 else {
1501 const unsigned offset = skb_transport_offset(skb);
1502 u32 tcpsum;
1503
1504 tcpsum = offset << 16; /* sum start */
1505 tcpsum |= offset + skb->csum_offset; /* sum write */
1506
1507 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1508 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1509 ctrl |= UDPTCP;
1510
1511 if (tcpsum != sky2->tx_tcpsum) {
1512 sky2->tx_tcpsum = tcpsum;
1513
1514 le = get_tx_le(sky2);
1515 le->addr = cpu_to_le32(tcpsum);
1516 le->length = 0; /* initial checksum value */
1517 le->ctrl = 1; /* one packet */
1518 le->opcode = OP_TCPLISW | HW_OWNER;
1519 }
1d179332 1520 }
cd28ab6a
SH		 1521 }
1522
1523 le = get_tx_le(sky2);
f65b138c 1524 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1525 le->length = cpu_to_le16(len);
1526 le->ctrl = ctrl;
793b883e 1527 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1528
291ea614 1529 re = tx_le_re(sky2, le);
cd28ab6a 1530 re->skb = skb;
6cdbbdf3 1531 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1532 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1533
1534 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1535 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1536
1537 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1538 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1539 addr64 = upper_32_bits(mapping);
793b883e
SH		 1540 if (addr64 != sky2->tx_addr64) {
1541 le = get_tx_le(sky2);
f65b138c 1542 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1543 le->ctrl = 0;
1544 le->opcode = OP_ADDR64 | HW_OWNER;
1545 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1546 }
1547
1548 le = get_tx_le(sky2);
f65b138c 1549 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1550 le->length = cpu_to_le16(frag->size);
1551 le->ctrl = ctrl;
793b883e 1552 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1553
291ea614
SH		 1554 re = tx_le_re(sky2, le);
1555 re->skb = skb;
1556 pci_unmap_addr_set(re, mapaddr, mapping);
1557 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1558 }
6cdbbdf3 1559
cd28ab6a
SH		 1560 le->ctrl |= EOP;
1561
97bda706 1562 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1563 netif_stop_queue(dev);
b19666d9 1564
290d4de5 1565 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1566
cd28ab6a
SH		 1567 dev->trans_start = jiffies;
1568 return NETDEV_TX_OK;
1569}
1570
cd28ab6a 1571/*
793b883e
SH		 1572 * Free ring elements from starting at tx_cons until "done"
1573 *
1574 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1575 * buffers so make sure not to free skb to early.
cd28ab6a 1576 */
d11c13e7 1577static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1578{
d11c13e7 1579 struct net_device *dev = sky2->netdev;
af2a58ac 1580 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1581 unsigned idx;
cd28ab6a 1582
0e3ff6aa 1583 BUG_ON(done >= TX_RING_SIZE);
2224795d 1584
291ea614
SH		 1585 for (idx = sky2->tx_cons; idx != done;
1586 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1587 struct sky2_tx_le *le = sky2->tx_le + idx;
1588 struct tx_ring_info *re = sky2->tx_ring + idx;
1589
1590 switch(le->opcode & ~HW_OWNER) {
1591 case OP_LARGESEND:
1592 case OP_PACKET:
1593 pci_unmap_single(pdev,
1594 pci_unmap_addr(re, mapaddr),
1595 pci_unmap_len(re, maplen),
1596 PCI_DMA_TODEVICE);
af2a58ac 1597 break;
291ea614
SH		 1598 case OP_BUFFER:
1599 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1600 pci_unmap_len(re, maplen),
734d1868 1601 PCI_DMA_TODEVICE);
291ea614
SH		 1602 break;
1603 }
1604
1605 if (le->ctrl & EOP) {
1606 if (unlikely(netif_msg_tx_done(sky2)))
1607 printk(KERN_DEBUG "%s: tx done %u\n",
1608 dev->name, idx);
3cf26753 1609
2bf56fe2 1610 sky2->net_stats.tx_packets++;
1611 sky2->net_stats.tx_bytes += re->skb->len;
1612
794b2bd2 1613 dev_kfree_skb_any(re->skb);
3cf26753 1614 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1615 }
793b883e 1616 }
793b883e 1617
291ea614 1618 sky2->tx_cons = idx;
50432cb5
SH		 1619 smp_mb();
1620
22e11703 1621 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1622 netif_wake_queue(dev);
cd28ab6a
SH		 1623}
1624
1625/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1626static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1627{
2bb8c262
SH		 1628 struct sky2_port *sky2 = netdev_priv(dev);
1629
1630 netif_tx_lock_bh(dev);
d11c13e7 1631 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1632 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1633}
1634
1635/* Network shutdown */
1636static int sky2_down(struct net_device *dev)
1637{
1638 struct sky2_port *sky2 = netdev_priv(dev);
1639 struct sky2_hw *hw = sky2->hw;
1640 unsigned port = sky2->port;
1641 u16 ctrl;
e07b1aa8 1642 u32 imask;
cd28ab6a 1643
1b537565
SH		 1644 /* Never really got started! */
1645 if (!sky2->tx_le)
1646 return 0;
1647
cd28ab6a
SH		 1648 if (netif_msg_ifdown(sky2))
1649 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1650
018d1c66 1651 /* Stop more packets from being queued */
cd28ab6a
SH		 1652 netif_stop_queue(dev);
1653
ebc646f6
SH		 1654 /* Disable port IRQ */
1655 imask = sky2_read32(hw, B0_IMSK);
1656 imask &= ~portirq_msk[port];
1657 sky2_write32(hw, B0_IMSK, imask);
1658
d3bcfbeb 1659 sky2_gmac_reset(hw, port);
793b883e 1660
cd28ab6a
SH		 1661 /* Stop transmitter */
1662 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1663 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1664
1665 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1666 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1667
1668 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1669 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1670 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1671
1672 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1673
1674 /* Workaround shared GMAC reset */
793b883e
SH		 1675 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1676 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1677 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1678
1679 /* Disable Force Sync bit and Enable Alloc bit */
1680 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1681 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1682
1683 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1684 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1685 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1686
1687 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1688 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1689 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1690
1691 /* Reset the Tx prefetch units */
1692 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1693 PREF_UNIT_RST_SET);
1694
1695 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1696
6b1a3aef 1697 sky2_rx_stop(sky2);
cd28ab6a
SH		 1698
1699 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1700 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1701
d3bcfbeb 1702 sky2_phy_power(hw, port, 0);
1703
55d7b4e6
SH		 1704 netif_carrier_off(dev);
1705
d571b694 1706 /* turn off LED's */
cd28ab6a
SH		 1707 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1708
018d1c66 1709 synchronize_irq(hw->pdev->irq);
1710
2bb8c262 1711 sky2_tx_clean(dev);
cd28ab6a
SH		 1712 sky2_rx_clean(sky2);
1713
1714 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1715 sky2->rx_le, sky2->rx_le_map);
1716 kfree(sky2->rx_ring);
1717
1718 pci_free_consistent(hw->pdev,
1719 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1720 sky2->tx_le, sky2->tx_le_map);
1721 kfree(sky2->tx_ring);
1722
1b537565
SH		 1723 sky2->tx_le = NULL;
1724 sky2->rx_le = NULL;
1725
1726 sky2->rx_ring = NULL;
1727 sky2->tx_ring = NULL;
1728
cd28ab6a
SH		 1729 return 0;
1730}
1731
1732static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1733{
ea76e635 1734 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1735 return SPEED_1000;
1736
05745c4a
SH		 1737 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1738 if (aux & PHY_M_PS_SPEED_100)
1739 return SPEED_100;
1740 else
1741 return SPEED_10;
1742 }
cd28ab6a
SH		 1743
1744 switch (aux & PHY_M_PS_SPEED_MSK) {
1745 case PHY_M_PS_SPEED_1000:
1746 return SPEED_1000;
1747 case PHY_M_PS_SPEED_100:
1748 return SPEED_100;
1749 default:
1750 return SPEED_10;
1751 }
1752}
1753
1754static void sky2_link_up(struct sky2_port *sky2)
1755{
1756 struct sky2_hw *hw = sky2->hw;
1757 unsigned port = sky2->port;
1758 u16 reg;
16ad91e1
SH		 1759 static const char *fc_name[] = {
1760 [FC_NONE] = "none",
1761 [FC_TX] = "tx",
1762 [FC_RX] = "rx",
1763 [FC_BOTH] = "both",
1764 };
cd28ab6a 1765
cd28ab6a 1766 /* enable Rx/Tx */
2eaba1a2 1767 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1768 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1769 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1770
1771 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1772
1773 netif_carrier_on(sky2->netdev);
cd28ab6a 1774
75e80683 1775 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1776
cd28ab6a 1777 /* Turn on link LED */
793b883e 1778 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1779 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1780
ea76e635 1781 if (hw->flags & SKY2_HW_NEWER_PHY) {
793b883e 1782 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1783 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1784
1785 switch(sky2->speed) {
1786 case SPEED_10:
1787 led |= PHY_M_LEDC_INIT_CTRL(7);
1788 break;
1789
1790 case SPEED_100:
1791 led |= PHY_M_LEDC_STA1_CTRL(7);
1792 break;
1793
1794 case SPEED_1000:
1795 led |= PHY_M_LEDC_STA0_CTRL(7);
1796 break;
1797 }
793b883e
SH		 1798
1799 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1800 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1801 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1802 }
1803
cd28ab6a
SH		 1804 if (netif_msg_link(sky2))
1805 printk(KERN_INFO PFX
d571b694 1806 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1807 sky2->netdev->name, sky2->speed,
1808 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1809 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1810}
1811
1812static void sky2_link_down(struct sky2_port *sky2)
1813{
1814 struct sky2_hw *hw = sky2->hw;
1815 unsigned port = sky2->port;
1816 u16 reg;
1817
1818 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1819
1820 reg = gma_read16(hw, port, GM_GP_CTRL);
1821 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1822 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1823
cd28ab6a 1824 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1825
1826 /* Turn on link LED */
1827 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1828
1829 if (netif_msg_link(sky2))
1830 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1831
cd28ab6a
SH		 1832 sky2_phy_init(hw, port);
1833}
1834
16ad91e1
SH		 1835static enum flow_control sky2_flow(int rx, int tx)
1836{
1837 if (rx)
1838 return tx ? FC_BOTH : FC_RX;
1839 else
1840 return tx ? FC_TX : FC_NONE;
1841}
1842
793b883e
SH		 1843static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1844{
1845 struct sky2_hw *hw = sky2->hw;
1846 unsigned port = sky2->port;
da4c1ff4 1847 u16 advert, lpa;
793b883e 1848
da4c1ff4 1849 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1850 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1851 if (lpa & PHY_M_AN_RF) {
1852 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1853 return -1;
1854 }
1855
793b883e
SH		 1856 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1857 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1858 sky2->netdev->name);
1859 return -1;
1860 }
1861
793b883e 1862 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1863 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1864
da4c1ff4
SH		 1865 /* Since the pause result bits seem to in different positions on
1866 * different chips. look at registers.
1867 */
ea76e635 1868 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1869 /* Shift for bits in fiber PHY */
1870 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1871 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1872
1873 if (advert & ADVERTISE_1000XPAUSE)
1874 advert |= ADVERTISE_PAUSE_CAP;
1875 if (advert & ADVERTISE_1000XPSE_ASYM)
1876 advert |= ADVERTISE_PAUSE_ASYM;
1877 if (lpa & LPA_1000XPAUSE)
1878 lpa |= LPA_PAUSE_CAP;
1879 if (lpa & LPA_1000XPAUSE_ASYM)
1880 lpa |= LPA_PAUSE_ASYM;
1881 }
793b883e 1882
da4c1ff4
SH		 1883 sky2->flow_status = FC_NONE;
1884 if (advert & ADVERTISE_PAUSE_CAP) {
1885 if (lpa & LPA_PAUSE_CAP)
1886 sky2->flow_status = FC_BOTH;
1887 else if (advert & ADVERTISE_PAUSE_ASYM)
1888 sky2->flow_status = FC_RX;
1889 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1890 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1891 sky2->flow_status = FC_TX;
1892 }
793b883e 1893
16ad91e1 1894 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1895 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1896 sky2->flow_status = FC_NONE;
2eaba1a2 1897
da4c1ff4 1898 if (sky2->flow_status & FC_TX)
793b883e
SH		 1899 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1900 else
1901 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1902
1903 return 0;
1904}
cd28ab6a 1905
e07b1aa8
SH		 1906/* Interrupt from PHY */
1907static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1908{
e07b1aa8
SH		 1909 struct net_device *dev = hw->dev[port];
1910 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1911 u16 istatus, phystat;
1912
ebc646f6
SH		 1913 if (!netif_running(dev))
1914 return;
1915
e07b1aa8
SH		 1916 spin_lock(&sky2->phy_lock);
1917 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1918 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1919
cd28ab6a
SH		 1920 if (netif_msg_intr(sky2))
1921 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1922 sky2->netdev->name, istatus, phystat);
1923
2eaba1a2 1924 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1925 if (sky2_autoneg_done(sky2, phystat) == 0)
1926 sky2_link_up(sky2);
1927 goto out;
1928 }
cd28ab6a 1929
793b883e
SH		 1930 if (istatus & PHY_M_IS_LSP_CHANGE)
1931 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1932
793b883e
SH		 1933 if (istatus & PHY_M_IS_DUP_CHANGE)
1934 sky2->duplex =
1935 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1936
793b883e
SH		 1937 if (istatus & PHY_M_IS_LST_CHANGE) {
1938 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1939 sky2_link_up(sky2);
793b883e
SH		 1940 else
1941 sky2_link_down(sky2);
cd28ab6a 1942 }
793b883e 1943out:
e07b1aa8 1944 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1945}
1946
62335ab0 1947/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1948 * and tx queue is full (stopped).
1949 */
cd28ab6a
SH		 1950static void sky2_tx_timeout(struct net_device *dev)
1951{
1952 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1953 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1954
1955 if (netif_msg_timer(sky2))
1956 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1957
8f24664d 1958 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1959 dev->name, sky2->tx_cons, sky2->tx_prod,
1960 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1961 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1962
81906791
SH		 1963 /* can't restart safely under softirq */
1964 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1965}
1966
1967static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1968{
6b1a3aef 1969 struct sky2_port *sky2 = netdev_priv(dev);
1970 struct sky2_hw *hw = sky2->hw;
b628ed98 1971 unsigned port = sky2->port;
6b1a3aef 1972 int err;
1973 u16 ctl, mode;
e07b1aa8 1974 u32 imask;
cd28ab6a
SH		 1975
1976 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1977 return -EINVAL;
1978
05745c4a
SH		 1979 if (new_mtu > ETH_DATA_LEN &&
1980 (hw->chip_id == CHIP_ID_YUKON_FE ||
1981 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 1982 return -EINVAL;
1983
6b1a3aef 1984 if (!netif_running(dev)) {
1985 dev->mtu = new_mtu;
1986 return 0;
1987 }
1988
e07b1aa8 1989 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1990 sky2_write32(hw, B0_IMSK, 0);
1991
018d1c66 1992 dev->trans_start = jiffies; /* prevent tx timeout */
1993 netif_stop_queue(dev);
1994 netif_poll_disable(hw->dev[0]);
1995
e07b1aa8
SH		 1996 synchronize_irq(hw->pdev->irq);
1997
05745c4a 1998 if (!(hw->flags & SKY2_HW_RAMBUFFER))
69161611 1999 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2000
2001 ctl = gma_read16(hw, port, GM_GP_CTRL);
2002 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2003 sky2_rx_stop(sky2);
2004 sky2_rx_clean(sky2);
cd28ab6a
SH		 2005
2006 dev->mtu = new_mtu;
14d0263f 2007
6b1a3aef 2008 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2009 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2010
2011 if (dev->mtu > ETH_DATA_LEN)
2012 mode |= GM_SMOD_JUMBO_ENA;
2013
b628ed98 2014 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2015
b628ed98 2016 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2017
6b1a3aef 2018 err = sky2_rx_start(sky2);
e07b1aa8 2019 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2020
1b537565
SH		 2021 if (err)
2022 dev_close(dev);
2023 else {
b628ed98 2024 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 2025
2026 netif_poll_enable(hw->dev[0]);
2027 netif_wake_queue(dev);
2028 }
2029
cd28ab6a
SH		 2030 return err;
2031}
2032
14d0263f
SH		 2033/* For small just reuse existing skb for next receive */
2034static struct sk_buff *receive_copy(struct sky2_port *sky2,
2035 const struct rx_ring_info *re,
2036 unsigned length)
2037{
2038 struct sk_buff *skb;
2039
2040 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2041 if (likely(skb)) {
2042 skb_reserve(skb, 2);
2043 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2044 length, PCI_DMA_FROMDEVICE);
d626f62b 2045 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2046 skb->ip_summed = re->skb->ip_summed;
2047 skb->csum = re->skb->csum;
2048 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2049 length, PCI_DMA_FROMDEVICE);
2050 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2051 skb_put(skb, length);
14d0263f
SH		 2052 }
2053 return skb;
2054}
2055
2056/* Adjust length of skb with fragments to match received data */
2057static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2058 unsigned int length)
2059{
2060 int i, num_frags;
2061 unsigned int size;
2062
2063 /* put header into skb */
2064 size = min(length, hdr_space);
2065 skb->tail += size;
2066 skb->len += size;
2067 length -= size;
2068
2069 num_frags = skb_shinfo(skb)->nr_frags;
2070 for (i = 0; i < num_frags; i++) {
2071 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2072
2073 if (length == 0) {
2074 /* don't need this page */
2075 __free_page(frag->page);
2076 --skb_shinfo(skb)->nr_frags;
2077 } else {
2078 size = min(length, (unsigned) PAGE_SIZE);
2079
2080 frag->size = size;
2081 skb->data_len += size;
2082 skb->truesize += size;
2083 skb->len += size;
2084 length -= size;
2085 }
2086 }
2087}
2088
2089/* Normal packet - take skb from ring element and put in a new one */
2090static struct sk_buff *receive_new(struct sky2_port *sky2,
2091 struct rx_ring_info *re,
2092 unsigned int length)
2093{
2094 struct sk_buff *skb, *nskb;
2095 unsigned hdr_space = sky2->rx_data_size;
2096
14d0263f
SH		 2097 /* Don't be tricky about reusing pages (yet) */
2098 nskb = sky2_rx_alloc(sky2);
2099 if (unlikely(!nskb))
2100 return NULL;
2101
2102 skb = re->skb;
2103 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2104
2105 prefetch(skb->data);
2106 re->skb = nskb;
2107 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2108
2109 if (skb_shinfo(skb)->nr_frags)
2110 skb_put_frags(skb, hdr_space, length);
2111 else
489b10c1 2112 skb_put(skb, length);
14d0263f
SH		 2113 return skb;
2114}
2115
cd28ab6a
SH		 2116/*
2117 * Receive one packet.
d571b694 2118 * For larger packets, get new buffer.
cd28ab6a 2119 */
497d7c86 2120static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2121 u16 length, u32 status)
2122{
497d7c86 2123 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2124 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2125 struct sk_buff *skb = NULL;
d6532232
SH		 2126 u16 count = (status & GMR_FS_LEN) >> 16;
2127
2128#ifdef SKY2_VLAN_TAG_USED
2129 /* Account for vlan tag */
2130 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2131 count -= VLAN_HLEN;
2132#endif
cd28ab6a
SH		 2133
2134 if (unlikely(netif_msg_rx_status(sky2)))
2135 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2136 dev->name, sky2->rx_next, status, length);
cd28ab6a 2137
793b883e 2138 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2139 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2140
42eeea01 2141 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2142 goto error;
2143
42eeea01 2144 if (!(status & GMR_FS_RX_OK))
2145 goto resubmit;
2146
d6532232
SH		 2147 /* if length reported by DMA does not match PHY, packet was truncated */
2148 if (length != count)
71749531
SH		 2149 goto len_mismatch;
2150
14d0263f
SH		 2151 if (length < copybreak)
2152 skb = receive_copy(sky2, re, length);
2153 else
2154 skb = receive_new(sky2, re, length);
793b883e 2155resubmit:
14d0263f 2156 sky2_rx_submit(sky2, re);
79e57d32 2157
cd28ab6a
SH		 2158 return skb;
2159
71749531
SH		 2160len_mismatch:
2161 /* Truncation of overlength packets
2162 causes PHY length to not match MAC length */
2163 ++sky2->net_stats.rx_length_errors;
d6532232
SH		 2164 if (netif_msg_rx_err(sky2) && net_ratelimit())
2165 pr_info(PFX "%s: rx length mismatch: length %d status %#x\n",
2166 dev->name, length, status);
2167 goto resubmit;
71749531 2168
cd28ab6a 2169error:
6e15b712 2170 ++sky2->net_stats.rx_errors;
b6d77734 2171 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2172 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2173 goto resubmit;
2174 }
6e15b712 2175
3be92a70 2176 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2177 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2178 dev->name, status, length);
793b883e
SH		 2179
2180 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2181 sky2->net_stats.rx_length_errors++;
2182 if (status & GMR_FS_FRAGMENT)
2183 sky2->net_stats.rx_frame_errors++;
2184 if (status & GMR_FS_CRC_ERR)
2185 sky2->net_stats.rx_crc_errors++;
79e57d32 2186
793b883e 2187 goto resubmit;
cd28ab6a
SH		 2188}
2189
e07b1aa8
SH		 2190/* Transmit complete */
2191static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2192{
e07b1aa8 2193 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2194
e07b1aa8 2195 if (netif_running(dev)) {
2bb8c262 2196 netif_tx_lock(dev);
e07b1aa8 2197 sky2_tx_complete(sky2, last);
2bb8c262 2198 netif_tx_unlock(dev);
2224795d 2199 }
cd28ab6a
SH		 2200}
2201
e07b1aa8
SH		 2202/* Process status response ring */
2203static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2204{
e07b1aa8 2205 int work_done = 0;
55c9dd35 2206 unsigned rx[2] = { 0, 0 };
e71ebd73 2207 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2208
af2a58ac 2209 rmb();
bea86103 2210
e71ebd73 2211 while (hw->st_idx != hwidx) {
55c9dd35 2212 struct sky2_port *sky2;
13210ce5 2213 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2214 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2215 struct net_device *dev;
cd28ab6a 2216 struct sk_buff *skb;
cd28ab6a
SH		 2217 u32 status;
2218 u16 length;
2219
cb5d9547 2220 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2221
69161611 2222 dev = hw->dev[port];
13210ce5 2223 sky2 = netdev_priv(dev);
f65b138c
SH		 2224 length = le16_to_cpu(le->length);
2225 status = le32_to_cpu(le->status);
cd28ab6a 2226
e71ebd73 2227 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2228 case OP_RXSTAT:
55c9dd35 2229 ++rx[port];
497d7c86 2230 skb = sky2_receive(dev, length, status);
3225b919
SH		 2231 if (unlikely(!skb)) {
2232 sky2->net_stats.rx_dropped++;
55c9dd35 2233 break;
3225b919 2234 }
13210ce5 2235
69161611 2236 /* This chip reports checksum status differently */
05745c4a 2237 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2238 if (sky2->rx_csum &&
2239 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2240 (le->css & CSS_TCPUDPCSOK))
2241 skb->ip_summed = CHECKSUM_UNNECESSARY;
2242 else
2243 skb->ip_summed = CHECKSUM_NONE;
2244 }
2245
13210ce5 2246 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2247 sky2->net_stats.rx_packets++;
2248 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2249 dev->last_rx = jiffies;
2250
d1f13708 2251#ifdef SKY2_VLAN_TAG_USED
2252 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2253 vlan_hwaccel_receive_skb(skb,
2254 sky2->vlgrp,
2255 be16_to_cpu(sky2->rx_tag));
2256 } else
2257#endif
cd28ab6a 2258 netif_receive_skb(skb);
13210ce5 2259
22e11703 2260 /* Stop after net poll weight */
13210ce5 2261 if (++work_done >= to_do)
2262 goto exit_loop;
cd28ab6a
SH		 2263 break;
2264
d1f13708 2265#ifdef SKY2_VLAN_TAG_USED
2266 case OP_RXVLAN:
2267 sky2->rx_tag = length;
2268 break;
2269
2270 case OP_RXCHKSVLAN:
2271 sky2->rx_tag = length;
2272 /* fall through */
2273#endif
cd28ab6a 2274 case OP_RXCHKS:
87418307
SH		 2275 if (!sky2->rx_csum)
2276 break;
2277
05745c4a
SH		 2278 /* If this happens then driver assuming wrong format */
2279 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2280 if (net_ratelimit())
2281 printk(KERN_NOTICE "%s: unexpected"
2282 " checksum status\n",
2283 dev->name);
69161611 2284 break;
05745c4a 2285 }
69161611 2286
87418307
SH		 2287 /* Both checksum counters are programmed to start at
2288 * the same offset, so unless there is a problem they
2289 * should match. This failure is an early indication that
2290 * hardware receive checksumming won't work.
2291 */
2292 if (likely(status >> 16 == (status & 0xffff))) {
2293 skb = sky2->rx_ring[sky2->rx_next].skb;
2294 skb->ip_summed = CHECKSUM_COMPLETE;
2295 skb->csum = status & 0xffff;
2296 } else {
2297 printk(KERN_NOTICE PFX "%s: hardware receive "
2298 "checksum problem (status = %#x)\n",
2299 dev->name, status);
2300 sky2->rx_csum = 0;
2301 sky2_write32(sky2->hw,
69161611 2302 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2303 BMU_DIS_RX_CHKSUM);
2304 }
cd28ab6a
SH		 2305 break;
2306
2307 case OP_TXINDEXLE:
13b97b74 2308 /* TX index reports status for both ports */
f55925d7
SH		 2309 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2310 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2311 if (hw->dev[1])
2312 sky2_tx_done(hw->dev[1],
2313 ((status >> 24) & 0xff)
2314 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2315 break;
2316
cd28ab6a
SH		 2317 default:
2318 if (net_ratelimit())
793b883e 2319 printk(KERN_WARNING PFX
e71ebd73 2320 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2321 }
13210ce5 2322 }
cd28ab6a 2323
fe2a24df
SH		 2324 /* Fully processed status ring so clear irq */
2325 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2326
13210ce5 2327exit_loop:
55c9dd35
SH		 2328 if (rx[0])
2329 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2330
55c9dd35
SH		 2331 if (rx[1])
2332 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2333
e07b1aa8 2334 return work_done;
cd28ab6a
SH		 2335}
2336
2337static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2338{
2339 struct net_device *dev = hw->dev[port];
2340
3be92a70
SH		 2341 if (net_ratelimit())
2342 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2343 dev->name, status);
cd28ab6a
SH		 2344
2345 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2346 if (net_ratelimit())
2347 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2348 dev->name);
cd28ab6a
SH		 2349 /* Clear IRQ */
2350 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2351 }
2352
2353 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2354 if (net_ratelimit())
2355 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2356 dev->name);
cd28ab6a
SH		 2357
2358 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2359 }
2360
2361 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2362 if (net_ratelimit())
2363 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2364 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2365 }
2366
2367 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2368 if (net_ratelimit())
2369 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2370 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2371 }
2372
2373 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2374 if (net_ratelimit())
2375 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2376 dev->name);
cd28ab6a
SH		 2377 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2378 }
2379}
2380
2381static void sky2_hw_intr(struct sky2_hw *hw)
2382{
2383 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2384
793b883e 2385 if (status & Y2_IS_TIST_OV)
cd28ab6a 2386 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2387
2388 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2389 u16 pci_err;
2390
56a645cc 2391 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2392 if (net_ratelimit())
b02a9258
SH		 2393 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2394 pci_err);
cd28ab6a
SH		 2395
2396 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2397 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2398 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2399 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2400 }
2401
2402 if (status & Y2_IS_PCI_EXP) {
d571b694 2403 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2404 u32 pex_err;
2405
7bd656d1 2406 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2407
3be92a70 2408 if (net_ratelimit())
b02a9258
SH		 2409 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2410 pex_err);
cd28ab6a
SH		 2411
2412 /* clear the interrupt */
2413 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2414 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2415 0xffffffffUL);
cd28ab6a
SH		 2416 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2417
7bd656d1 2418 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2419 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2420 hwmsk &= ~Y2_IS_PCI_EXP;
2421 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2422 }
2423 }
2424
2425 if (status & Y2_HWE_L1_MASK)
2426 sky2_hw_error(hw, 0, status);
2427 status >>= 8;
2428 if (status & Y2_HWE_L1_MASK)
2429 sky2_hw_error(hw, 1, status);
2430}
2431
2432static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2433{
2434 struct net_device *dev = hw->dev[port];
2435 struct sky2_port *sky2 = netdev_priv(dev);
2436 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2437
2438 if (netif_msg_intr(sky2))
2439 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2440 dev->name, status);
2441
a3caeada
SH		 2442 if (status & GM_IS_RX_CO_OV)
2443 gma_read16(hw, port, GM_RX_IRQ_SRC);
2444
2445 if (status & GM_IS_TX_CO_OV)
2446 gma_read16(hw, port, GM_TX_IRQ_SRC);
2447
cd28ab6a
SH		 2448 if (status & GM_IS_RX_FF_OR) {
2449 ++sky2->net_stats.rx_fifo_errors;
2450 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2451 }
2452
2453 if (status & GM_IS_TX_FF_UR) {
2454 ++sky2->net_stats.tx_fifo_errors;
2455 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2456 }
cd28ab6a
SH		 2457}
2458
40b01727
SH		 2459/* This should never happen it is a bug. */
2460static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2461 u16 q, unsigned ring_size)
d257924e
SH		 2462{
2463 struct net_device *dev = hw->dev[port];
2464 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2465 unsigned idx;
2466 const u64 *le = (q == Q_R1 || q == Q_R2)
2467 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2468
40b01727
SH		 2469 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2470 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2471 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2472 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2473
40b01727 2474 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2475}
cd28ab6a 2476
75e80683
SH		 2477static int sky2_rx_hung(struct net_device *dev)
2478{
2479 struct sky2_port *sky2 = netdev_priv(dev);
2480 struct sky2_hw *hw = sky2->hw;
2481 unsigned port = sky2->port;
2482 unsigned rxq = rxqaddr[port];
2483 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2484 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2485 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2486 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2487
2488 /* If idle and MAC or PCI is stuck */
2489 if (sky2->check.last == dev->last_rx &&
2490 ((mac_rp == sky2->check.mac_rp &&
2491 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2492 /* Check if the PCI RX hang */
2493 (fifo_rp == sky2->check.fifo_rp &&
2494 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2495 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2496 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2497 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2498 return 1;
2499 } else {
2500 sky2->check.last = dev->last_rx;
2501 sky2->check.mac_rp = mac_rp;
2502 sky2->check.mac_lev = mac_lev;
2503 sky2->check.fifo_rp = fifo_rp;
2504 sky2->check.fifo_lev = fifo_lev;
2505 return 0;
2506 }
2507}
2508
32c2c300 2509static void sky2_watchdog(unsigned long arg)
d27ed387 2510{
01bd7564 2511 struct sky2_hw *hw = (struct sky2_hw *) arg;
75e80683 2512 struct net_device *dev;
d27ed387 2513
75e80683 2514 /* Check for lost IRQ once a second */
32c2c300 2515 if (sky2_read32(hw, B0_ISRC)) {
75e80683 2516 dev = hw->dev[0];
32c2c300
SH		 2517 if (__netif_rx_schedule_prep(dev))
2518 __netif_rx_schedule(dev);
75e80683
SH		 2519 } else {
2520 int i, active = 0;
2521
2522 for (i = 0; i < hw->ports; i++) {
2523 dev = hw->dev[i];
2524 if (!netif_running(dev))
2525 continue;
2526 ++active;
2527
2528 /* For chips with Rx FIFO, check if stuck */
2529 if ((hw->flags & SKY2_HW_RAMBUFFER) &&
2530 sky2_rx_hung(dev)) {
2531 pr_info(PFX "%s: receiver hang detected\n",
2532 dev->name);
2533 schedule_work(&hw->restart_work);
2534 return;
2535 }
2536 }
2537
2538 if (active == 0)
2539 return;
32c2c300 2540 }
01bd7564 2541
75e80683 2542 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2543}
2544
40b01727
SH		 2545/* Hardware/software error handling */
2546static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2547{
40b01727
SH		 2548 if (net_ratelimit())
2549 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2550
1e5f1283
SH		 2551 if (status & Y2_IS_HW_ERR)
2552 sky2_hw_intr(hw);
d257924e 2553
1e5f1283
SH		 2554 if (status & Y2_IS_IRQ_MAC1)
2555 sky2_mac_intr(hw, 0);
cd28ab6a 2556
1e5f1283
SH		 2557 if (status & Y2_IS_IRQ_MAC2)
2558 sky2_mac_intr(hw, 1);
cd28ab6a 2559
1e5f1283 2560 if (status & Y2_IS_CHK_RX1)
40b01727 2561 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2562
1e5f1283 2563 if (status & Y2_IS_CHK_RX2)
40b01727 2564 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2565
1e5f1283 2566 if (status & Y2_IS_CHK_TXA1)
40b01727 2567 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2568
1e5f1283 2569 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2570 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2571}
2572
2573static int sky2_poll(struct net_device *dev0, int *budget)
2574{
2575 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2576 int work_done;
40b01727
SH		 2577 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2578
2579 if (unlikely(status & Y2_IS_ERROR))
2580 sky2_err_intr(hw, status);
2581
2582 if (status & Y2_IS_IRQ_PHY1)
2583 sky2_phy_intr(hw, 0);
2584
2585 if (status & Y2_IS_IRQ_PHY2)
2586 sky2_phy_intr(hw, 1);
cd28ab6a 2587
5c11ce70
SH		 2588 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2589 *budget -= work_done;
2590 dev0->quota -= work_done;
86fba634 2591
5c11ce70
SH		 2592 /* More work? */
2593 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2594 return 1;
5c11ce70
SH		 2595
2596 /* Bug/Errata workaround?
2597 * Need to kick the TX irq moderation timer.
2598 */
2599 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2600 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2601 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2602 }
5c11ce70
SH		 2603 netif_rx_complete(dev0);
2604
2605 sky2_read32(hw, B0_Y2_SP_LISR);
2606 return 0;
e07b1aa8
SH		 2607}
2608
7d12e780 2609static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2610{
2611 struct sky2_hw *hw = dev_id;
2612 struct net_device *dev0 = hw->dev[0];
2613 u32 status;
2614
2615 /* Reading this mask interrupts as side effect */
2616 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2617 if (status == 0 || status == ~0)
2618 return IRQ_NONE;
793b883e 2619
e07b1aa8
SH		 2620 prefetch(&hw->st_le[hw->st_idx]);
2621 if (likely(__netif_rx_schedule_prep(dev0)))
2622 __netif_rx_schedule(dev0);
793b883e 2623
cd28ab6a
SH		 2624 return IRQ_HANDLED;
2625}
2626
2627#ifdef CONFIG_NET_POLL_CONTROLLER
2628static void sky2_netpoll(struct net_device *dev)
2629{
2630 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2631 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2632
88d11360
SH		 2633 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2634 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2635}
2636#endif
2637
2638/* Chip internal frequency for clock calculations */
05745c4a 2639static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2640{
793b883e 2641 switch (hw->chip_id) {
cd28ab6a 2642 case CHIP_ID_YUKON_EC:
5a5b1ea0 2643 case CHIP_ID_YUKON_EC_U:
93745494 2644 case CHIP_ID_YUKON_EX:
05745c4a
SH		 2645 return 125;
2646
cd28ab6a 2647 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2648 return 100;
2649
2650 case CHIP_ID_YUKON_FE_P:
2651 return 50;
2652
2653 case CHIP_ID_YUKON_XL:
2654 return 156;
2655
2656 default:
2657 BUG();
cd28ab6a
SH		 2658 }
2659}
2660
fb17358f 2661static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2662{
fb17358f 2663 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2664}
2665
fb17358f 2666static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2667{
fb17358f 2668 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2669}
2670
fb17358f 2671
e3173832 2672static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2673{
b89165f2 2674 u8 t8;
cd28ab6a 2675
451af335
SH		 2676 /* Enable all clocks */
2677 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2678
cd28ab6a 2679 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2680
cd28ab6a 2681 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2682 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2683
2684 switch(hw->chip_id) {
2685 case CHIP_ID_YUKON_XL:
2686 hw->flags = SKY2_HW_GIGABIT
2687 | SKY2_HW_NEWER_PHY
2688 | SKY2_HW_RAMBUFFER;
2689 break;
2690
2691 case CHIP_ID_YUKON_EC_U:
2692 hw->flags = SKY2_HW_GIGABIT
2693 | SKY2_HW_NEWER_PHY
2694 | SKY2_HW_ADV_POWER_CTL;
2695 break;
2696
2697 case CHIP_ID_YUKON_EX:
2698 hw->flags = SKY2_HW_GIGABIT
2699 | SKY2_HW_NEWER_PHY
2700 | SKY2_HW_NEW_LE
2701 | SKY2_HW_ADV_POWER_CTL;
2702
2703 /* New transmit checksum */
2704 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2705 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2706 break;
2707
2708 case CHIP_ID_YUKON_EC:
2709 /* This rev is really old, and requires untested workarounds */
2710 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2711 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2712 return -EOPNOTSUPP;
2713 }
2714 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RAMBUFFER;
2715 break;
2716
2717 case CHIP_ID_YUKON_FE:
2718 hw->flags = SKY2_HW_RAMBUFFER;
2719 break;
2720
05745c4a
SH		 2721 case CHIP_ID_YUKON_FE_P:
2722 hw->flags = SKY2_HW_NEWER_PHY
2723 | SKY2_HW_NEW_LE
2724 | SKY2_HW_AUTO_TX_SUM
2725 | SKY2_HW_ADV_POWER_CTL;
2726 break;
ea76e635 2727 default:
b02a9258
SH		 2728 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2729 hw->chip_id);
cd28ab6a
SH		 2730 return -EOPNOTSUPP;
2731 }
2732
ea76e635
SH		 2733 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2734 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2735 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2736
290d4de5 2737
e3173832
SH		 2738 hw->ports = 1;
2739 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2740 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2741 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2742 ++hw->ports;
2743 }
2744
2745 return 0;
2746}
2747
2748static void sky2_reset(struct sky2_hw *hw)
2749{
2750 u16 status;
2751 int i;
2752
cd28ab6a 2753 /* disable ASF */
4f44d8ba
SH		 2754 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2755 status = sky2_read16(hw, HCU_CCSR);
2756 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2757 HCU_CCSR_UC_STATE_MSK);
2758 sky2_write16(hw, HCU_CCSR, status);
2759 } else
2760 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2761 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2762
2763 /* do a SW reset */
2764 sky2_write8(hw, B0_CTST, CS_RST_SET);
2765 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2766
2767 /* clear PCI errors, if any */
56a645cc 2768 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2769
cd28ab6a 2770 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2771 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2772
cd28ab6a
SH		 2773
2774 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2775
2776 /* clear any PEX errors */
7bd656d1
SH		 2777 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2778 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2779
cd28ab6a 2780
ae306cca 2781 sky2_power_on(hw);
cd28ab6a
SH		 2782
2783 for (i = 0; i < hw->ports; i++) {
2784 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2785 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2786
2787 if (hw->chip_id == CHIP_ID_YUKON_EX)
2788 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2789 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2790 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2791 }
2792
2793 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2794
793b883e
SH		 2795 /* Clear I2C IRQ noise */
2796 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2797
2798 /* turn off hardware timer (unused) */
2799 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2800 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2801
cd28ab6a
SH		 2802 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2803
69634ee7
SH		 2804 /* Turn off descriptor polling */
2805 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2806
2807 /* Turn off receive timestamp */
2808 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2809 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2810
2811 /* enable the Tx Arbiters */
2812 for (i = 0; i < hw->ports; i++)
2813 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2814
2815 /* Initialize ram interface */
2816 for (i = 0; i < hw->ports; i++) {
793b883e 2817 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2818
2819 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2820 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2821 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2822 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2823 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2824 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2825 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2826 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2827 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2828 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2829 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2830 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2831 }
2832
7bd656d1 2833 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2834
cd28ab6a 2835 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2836 sky2_gmac_reset(hw, i);
cd28ab6a 2837
cd28ab6a
SH		 2838 memset(hw->st_le, 0, STATUS_LE_BYTES);
2839 hw->st_idx = 0;
2840
2841 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2842 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2843
2844 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2845 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2846
2847 /* Set the list last index */
793b883e 2848 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2849
290d4de5
SH		 2850 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2851 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2852
290d4de5
SH		 2853 /* set Status-FIFO ISR watermark */
2854 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2855 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2856 else
2857 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2858
290d4de5 2859 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2860 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2861 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2862
793b883e 2863 /* enable status unit */
cd28ab6a
SH		 2864 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2865
2866 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2867 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2868 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2869}
2870
81906791
SH		 2871static void sky2_restart(struct work_struct *work)
2872{
2873 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2874 struct net_device *dev;
2875 int i, err;
2876
81906791
SH		 2877 rtnl_lock();
2878 sky2_write32(hw, B0_IMSK, 0);
2879 sky2_read32(hw, B0_IMSK);
2880
2881 netif_poll_disable(hw->dev[0]);
2882
2883 for (i = 0; i < hw->ports; i++) {
2884 dev = hw->dev[i];
2885 if (netif_running(dev))
2886 sky2_down(dev);
2887 }
2888
2889 sky2_reset(hw);
2890 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2891 netif_poll_enable(hw->dev[0]);
2892
2893 for (i = 0; i < hw->ports; i++) {
2894 dev = hw->dev[i];
2895 if (netif_running(dev)) {
2896 err = sky2_up(dev);
2897 if (err) {
2898 printk(KERN_INFO PFX "%s: could not restart %d\n",
2899 dev->name, err);
2900 dev_close(dev);
2901 }
2902 }
2903 }
2904
81906791
SH		 2905 rtnl_unlock();
2906}
2907
e3173832
SH		 2908static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2909{
2910 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2911}
2912
2913static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2914{
2915 const struct sky2_port *sky2 = netdev_priv(dev);
2916
2917 wol->supported = sky2_wol_supported(sky2->hw);
2918 wol->wolopts = sky2->wol;
2919}
2920
2921static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2922{
2923 struct sky2_port *sky2 = netdev_priv(dev);
2924 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2925
e3173832
SH		 2926 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2927 return -EOPNOTSUPP;
2928
2929 sky2->wol = wol->wolopts;
2930
05745c4a
SH		 2931 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2932 hw->chip_id == CHIP_ID_YUKON_EX ||
2933 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 2934 sky2_write32(hw, B0_CTST, sky2->wol
2935 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2936
2937 if (!netif_running(dev))
2938 sky2_wol_init(sky2);
cd28ab6a
SH		 2939 return 0;
2940}
2941
28bd181a 2942static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2943{
b89165f2
SH		 2944 if (sky2_is_copper(hw)) {
2945 u32 modes = SUPPORTED_10baseT_Half
2946 | SUPPORTED_10baseT_Full
2947 | SUPPORTED_100baseT_Half
2948 | SUPPORTED_100baseT_Full
2949 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2950
ea76e635 2951 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 2952 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2953 | SUPPORTED_1000baseT_Full;
2954 return modes;
cd28ab6a 2955 } else
b89165f2
SH		 2956 return SUPPORTED_1000baseT_Half
2957 | SUPPORTED_1000baseT_Full
2958 | SUPPORTED_Autoneg
2959 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2960}
2961
793b883e 2962static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2963{
2964 struct sky2_port *sky2 = netdev_priv(dev);
2965 struct sky2_hw *hw = sky2->hw;
2966
2967 ecmd->transceiver = XCVR_INTERNAL;
2968 ecmd->supported = sky2_supported_modes(hw);
2969 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2970 if (sky2_is_copper(hw)) {
cd28ab6a 2971 ecmd->port = PORT_TP;
b89165f2
SH		 2972 ecmd->speed = sky2->speed;
2973 } else {
2974 ecmd->speed = SPEED_1000;
cd28ab6a 2975 ecmd->port = PORT_FIBRE;
b89165f2 2976 }
cd28ab6a
SH		 2977
2978 ecmd->advertising = sky2->advertising;
2979 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2980 ecmd->duplex = sky2->duplex;
2981 return 0;
2982}
2983
2984static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2985{
2986 struct sky2_port *sky2 = netdev_priv(dev);
2987 const struct sky2_hw *hw = sky2->hw;
2988 u32 supported = sky2_supported_modes(hw);
2989
2990 if (ecmd->autoneg == AUTONEG_ENABLE) {
2991 ecmd->advertising = supported;
2992 sky2->duplex = -1;
2993 sky2->speed = -1;
2994 } else {
2995 u32 setting;
2996
793b883e 2997 switch (ecmd->speed) {
cd28ab6a
SH		 2998 case SPEED_1000:
2999 if (ecmd->duplex == DUPLEX_FULL)
3000 setting = SUPPORTED_1000baseT_Full;
3001 else if (ecmd->duplex == DUPLEX_HALF)
3002 setting = SUPPORTED_1000baseT_Half;
3003 else
3004 return -EINVAL;
3005 break;
3006 case SPEED_100:
3007 if (ecmd->duplex == DUPLEX_FULL)
3008 setting = SUPPORTED_100baseT_Full;
3009 else if (ecmd->duplex == DUPLEX_HALF)
3010 setting = SUPPORTED_100baseT_Half;
3011 else
3012 return -EINVAL;
3013 break;
3014
3015 case SPEED_10:
3016 if (ecmd->duplex == DUPLEX_FULL)
3017 setting = SUPPORTED_10baseT_Full;
3018 else if (ecmd->duplex == DUPLEX_HALF)
3019 setting = SUPPORTED_10baseT_Half;
3020 else
3021 return -EINVAL;
3022 break;
3023 default:
3024 return -EINVAL;
3025 }
3026
3027 if ((setting & supported) == 0)
3028 return -EINVAL;
3029
3030 sky2->speed = ecmd->speed;
3031 sky2->duplex = ecmd->duplex;
3032 }
3033
3034 sky2->autoneg = ecmd->autoneg;
3035 sky2->advertising = ecmd->advertising;
3036
d1b139c0 3037 if (netif_running(dev)) {
1b537565 3038 sky2_phy_reinit(sky2);
d1b139c0
SH		 3039 sky2_set_multicast(dev);
3040 }
cd28ab6a
SH		 3041
3042 return 0;
3043}
3044
3045static void sky2_get_drvinfo(struct net_device *dev,
3046 struct ethtool_drvinfo *info)
3047{
3048 struct sky2_port *sky2 = netdev_priv(dev);
3049
3050 strcpy(info->driver, DRV_NAME);
3051 strcpy(info->version, DRV_VERSION);
3052 strcpy(info->fw_version, "N/A");
3053 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3054}
3055
3056static const struct sky2_stat {
793b883e
SH		 3057 char name[ETH_GSTRING_LEN];
3058 u16 offset;
cd28ab6a
SH		 3059} sky2_stats[] = {
3060 { "tx_bytes", GM_TXO_OK_HI },
3061 { "rx_bytes", GM_RXO_OK_HI },
3062 { "tx_broadcast", GM_TXF_BC_OK },
3063 { "rx_broadcast", GM_RXF_BC_OK },
3064 { "tx_multicast", GM_TXF_MC_OK },
3065 { "rx_multicast", GM_RXF_MC_OK },
3066 { "tx_unicast", GM_TXF_UC_OK },
3067 { "rx_unicast", GM_RXF_UC_OK },
3068 { "tx_mac_pause", GM_TXF_MPAUSE },
3069 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3070 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3071 { "late_collision",GM_TXF_LAT_COL },
3072 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3073 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3074 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3075
d2604540 3076 { "rx_short", GM_RXF_SHT },
cd28ab6a 3077 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3078 { "rx_64_byte_packets", GM_RXF_64B },
3079 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3080 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3081 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3082 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3083 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3084 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3085 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3086 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3087 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3088 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3089
3090 { "tx_64_byte_packets", GM_TXF_64B },
3091 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3092 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3093 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3094 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3095 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3096 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3097 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3098};
3099
cd28ab6a
SH		 3100static u32 sky2_get_rx_csum(struct net_device *dev)
3101{
3102 struct sky2_port *sky2 = netdev_priv(dev);
3103
3104 return sky2->rx_csum;
3105}
3106
3107static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3108{
3109 struct sky2_port *sky2 = netdev_priv(dev);
3110
3111 sky2->rx_csum = data;
793b883e 3112
cd28ab6a
SH		 3113 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3114 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3115
3116 return 0;
3117}
3118
3119static u32 sky2_get_msglevel(struct net_device *netdev)
3120{
3121 struct sky2_port *sky2 = netdev_priv(netdev);
3122 return sky2->msg_enable;
3123}
3124
9a7ae0a9
SH		 3125static int sky2_nway_reset(struct net_device *dev)
3126{
3127 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3128
16ad91e1 3129 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3130 return -EINVAL;
3131
1b537565 3132 sky2_phy_reinit(sky2);
d1b139c0 3133 sky2_set_multicast(dev);
9a7ae0a9
SH		 3134
3135 return 0;
3136}
3137
793b883e 3138static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3139{
3140 struct sky2_hw *hw = sky2->hw;
3141 unsigned port = sky2->port;
3142 int i;
3143
3144 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3145 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3146 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3147 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3148
793b883e 3149 for (i = 2; i < count; i++)
cd28ab6a
SH		 3150 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3151}
3152
cd28ab6a
SH		 3153static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3154{
3155 struct sky2_port *sky2 = netdev_priv(netdev);
3156 sky2->msg_enable = value;
3157}
3158
3159static int sky2_get_stats_count(struct net_device *dev)
3160{
3161 return ARRAY_SIZE(sky2_stats);
3162}
3163
3164static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3165 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3166{
3167 struct sky2_port *sky2 = netdev_priv(dev);
3168
793b883e 3169 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3170}
3171
793b883e 3172static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3173{
3174 int i;
3175
3176 switch (stringset) {
3177 case ETH_SS_STATS:
3178 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3179 memcpy(data + i * ETH_GSTRING_LEN,
3180 sky2_stats[i].name, ETH_GSTRING_LEN);
3181 break;
3182 }
3183}
3184
cd28ab6a
SH		 3185static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3186{
3187 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3188 return &sky2->net_stats;
3189}
3190
3191static int sky2_set_mac_address(struct net_device *dev, void *p)
3192{
3193 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3194 struct sky2_hw *hw = sky2->hw;
3195 unsigned port = sky2->port;
3196 const struct sockaddr *addr = p;
cd28ab6a
SH		 3197
3198 if (!is_valid_ether_addr(addr->sa_data))
3199 return -EADDRNOTAVAIL;
3200
cd28ab6a 3201 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3202 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3203 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3204 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3205 dev->dev_addr, ETH_ALEN);
1b537565 3206
a8ab1ec0
SH		 3207 /* virtual address for data */
3208 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3209
3210 /* physical address: used for pause frames */
3211 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3212
3213 return 0;
cd28ab6a
SH		 3214}
3215
a052b52f
SH		 3216static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3217{
3218 u32 bit;
3219
3220 bit = ether_crc(ETH_ALEN, addr) & 63;
3221 filter[bit >> 3] |= 1 << (bit & 7);
3222}
3223
cd28ab6a
SH		 3224static void sky2_set_multicast(struct net_device *dev)
3225{
3226 struct sky2_port *sky2 = netdev_priv(dev);
3227 struct sky2_hw *hw = sky2->hw;
3228 unsigned port = sky2->port;
3229 struct dev_mc_list *list = dev->mc_list;
3230 u16 reg;
3231 u8 filter[8];
a052b52f
SH		 3232 int rx_pause;
3233 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3234
a052b52f 3235 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3236 memset(filter, 0, sizeof(filter));
3237
3238 reg = gma_read16(hw, port, GM_RX_CTRL);
3239 reg |= GM_RXCR_UCF_ENA;
3240
d571b694 3241 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3242 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3243 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3244 memset(filter, 0xff, sizeof(filter));
a052b52f 3245 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3246 reg &= ~GM_RXCR_MCF_ENA;
3247 else {
3248 int i;
3249 reg |= GM_RXCR_MCF_ENA;
3250
a052b52f
SH		 3251 if (rx_pause)
3252 sky2_add_filter(filter, pause_mc_addr);
3253
3254 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3255 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3256 }
3257
cd28ab6a 3258 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3259 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3260 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3261 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3262 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3263 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3264 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3265 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3266
3267 gma_write16(hw, port, GM_RX_CTRL, reg);
3268}
3269
3270/* Can have one global because blinking is controlled by
3271 * ethtool and that is always under RTNL mutex
3272 */
91c86df5 3273static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3274{
793b883e
SH		 3275 u16 pg;
3276
793b883e
SH		 3277 switch (hw->chip_id) {
3278 case CHIP_ID_YUKON_XL:
3279 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3280 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3281 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3282 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3283 PHY_M_LEDC_INIT_CTRL(7) |
3284 PHY_M_LEDC_STA1_CTRL(7) |
3285 PHY_M_LEDC_STA0_CTRL(7))
3286 : 0);
3287
3288 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3289 break;
3290
3291 default:
3292 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3293 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3294 on ? PHY_M_LED_ALL : 0);
793b883e 3295 }
cd28ab6a
SH		 3296}
3297
3298/* blink LED's for finding board */
3299static int sky2_phys_id(struct net_device *dev, u32 data)
3300{
3301 struct sky2_port *sky2 = netdev_priv(dev);
3302 struct sky2_hw *hw = sky2->hw;
3303 unsigned port = sky2->port;
793b883e 3304 u16 ledctrl, ledover = 0;
cd28ab6a 3305 long ms;
91c86df5 3306 int interrupted;
cd28ab6a
SH		 3307 int onoff = 1;
3308
793b883e 3309 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3310 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3311 else
3312 ms = data * 1000;
3313
3314 /* save initial values */
e07b1aa8 3315 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3316 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3317 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3318 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3319 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3320 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3321 } else {
3322 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3323 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3324 }
cd28ab6a 3325
91c86df5
SH		 3326 interrupted = 0;
3327 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3328 sky2_led(hw, port, onoff);
3329 onoff = !onoff;
3330
e07b1aa8 3331 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3332 interrupted = msleep_interruptible(250);
e07b1aa8 3333 spin_lock_bh(&sky2->phy_lock);
91c86df5 3334
cd28ab6a
SH		 3335 ms -= 250;
3336 }
3337
3338 /* resume regularly scheduled programming */
793b883e
SH		 3339 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3340 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3341 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3343 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3344 } else {
3345 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3346 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3347 }
e07b1aa8 3348 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3349
3350 return 0;
3351}
3352
3353static void sky2_get_pauseparam(struct net_device *dev,
3354 struct ethtool_pauseparam *ecmd)
3355{
3356 struct sky2_port *sky2 = netdev_priv(dev);
3357
16ad91e1
SH		 3358 switch (sky2->flow_mode) {
3359 case FC_NONE:
3360 ecmd->tx_pause = ecmd->rx_pause = 0;
3361 break;
3362 case FC_TX:
3363 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3364 break;
3365 case FC_RX:
3366 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3367 break;
3368 case FC_BOTH:
3369 ecmd->tx_pause = ecmd->rx_pause = 1;
3370 }
3371
cd28ab6a
SH		 3372 ecmd->autoneg = sky2->autoneg;
3373}
3374
3375static int sky2_set_pauseparam(struct net_device *dev,
3376 struct ethtool_pauseparam *ecmd)
3377{
3378 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3379
3380 sky2->autoneg = ecmd->autoneg;
16ad91e1 3381 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3382
16ad91e1
SH		 3383 if (netif_running(dev))
3384 sky2_phy_reinit(sky2);
cd28ab6a 3385
2eaba1a2 3386 return 0;
cd28ab6a
SH		 3387}
3388
fb17358f
SH		 3389static int sky2_get_coalesce(struct net_device *dev,
3390 struct ethtool_coalesce *ecmd)
3391{
3392 struct sky2_port *sky2 = netdev_priv(dev);
3393 struct sky2_hw *hw = sky2->hw;
3394
3395 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3396 ecmd->tx_coalesce_usecs = 0;
3397 else {
3398 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3399 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3400 }
3401 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3402
3403 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3404 ecmd->rx_coalesce_usecs = 0;
3405 else {
3406 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3407 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3408 }
3409 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3410
3411 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3412 ecmd->rx_coalesce_usecs_irq = 0;
3413 else {
3414 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3415 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3416 }
3417
3418 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3419
3420 return 0;
3421}
3422
3423/* Note: this affect both ports */
3424static int sky2_set_coalesce(struct net_device *dev,
3425 struct ethtool_coalesce *ecmd)
3426{
3427 struct sky2_port *sky2 = netdev_priv(dev);
3428 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3429 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3430
77b3d6a2
SH		 3431 if (ecmd->tx_coalesce_usecs > tmax ||
3432 ecmd->rx_coalesce_usecs > tmax ||
3433 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3434 return -EINVAL;
3435
ff81fbbe 3436 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3437 return -EINVAL;
ff81fbbe 3438 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3439 return -EINVAL;
ff81fbbe 3440 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3441 return -EINVAL;
3442
3443 if (ecmd->tx_coalesce_usecs == 0)
3444 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3445 else {
3446 sky2_write32(hw, STAT_TX_TIMER_INI,
3447 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3448 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3449 }
3450 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3451
3452 if (ecmd->rx_coalesce_usecs == 0)
3453 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3454 else {
3455 sky2_write32(hw, STAT_LEV_TIMER_INI,
3456 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3457 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3458 }
3459 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3460
3461 if (ecmd->rx_coalesce_usecs_irq == 0)
3462 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3463 else {
d28d4870 3464 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3465 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3466 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3467 }
3468 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3469 return 0;
3470}
3471
793b883e
SH		 3472static void sky2_get_ringparam(struct net_device *dev,
3473 struct ethtool_ringparam *ering)
3474{
3475 struct sky2_port *sky2 = netdev_priv(dev);
3476
3477 ering->rx_max_pending = RX_MAX_PENDING;
3478 ering->rx_mini_max_pending = 0;
3479 ering->rx_jumbo_max_pending = 0;
3480 ering->tx_max_pending = TX_RING_SIZE - 1;
3481
3482 ering->rx_pending = sky2->rx_pending;
3483 ering->rx_mini_pending = 0;
3484 ering->rx_jumbo_pending = 0;
3485 ering->tx_pending = sky2->tx_pending;
3486}
3487
3488static int sky2_set_ringparam(struct net_device *dev,
3489 struct ethtool_ringparam *ering)
3490{
3491 struct sky2_port *sky2 = netdev_priv(dev);
3492 int err = 0;
3493
3494 if (ering->rx_pending > RX_MAX_PENDING ||
3495 ering->rx_pending < 8 ||
3496 ering->tx_pending < MAX_SKB_TX_LE ||
3497 ering->tx_pending > TX_RING_SIZE - 1)
3498 return -EINVAL;
3499
3500 if (netif_running(dev))
3501 sky2_down(dev);
3502
3503 sky2->rx_pending = ering->rx_pending;
3504 sky2->tx_pending = ering->tx_pending;
3505
1b537565 3506 if (netif_running(dev)) {
793b883e 3507 err = sky2_up(dev);
1b537565
SH		 3508 if (err)
3509 dev_close(dev);
6ed995bb
SH		 3510 else
3511 sky2_set_multicast(dev);
1b537565 3512 }
793b883e
SH		 3513
3514 return err;
3515}
3516
793b883e
SH		 3517static int sky2_get_regs_len(struct net_device *dev)
3518{
6e4cbb34 3519 return 0x4000;
793b883e
SH		 3520}
3521
3522/*
3523 * Returns copy of control register region
3ead5db7 3524 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3525 */
3526static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3527 void *p)
3528{
3529 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3530 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3531
3532 regs->version = 1;
6e4cbb34 3533 memset(p, 0, regs->len);
793b883e 3534
6e4cbb34
SH		 3535 memcpy_fromio(p, io, B3_RAM_ADDR);
3536
3ead5db7
SH		 3537 /* skip diagnostic ram region */
3538 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3539
3540 /* copy GMAC registers */
3541 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3542 if (sky2->hw->ports > 1)
3543 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3544
793b883e 3545}
cd28ab6a 3546
b628ed98
SH		 3547/* In order to do Jumbo packets on these chips, need to turn off the
3548 * transmit store/forward. Therefore checksum offload won't work.
3549 */
3550static int no_tx_offload(struct net_device *dev)
3551{
3552 const struct sky2_port *sky2 = netdev_priv(dev);
3553 const struct sky2_hw *hw = sky2->hw;
3554
69161611 3555 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3556}
3557
3558static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3559{
3560 if (data && no_tx_offload(dev))
3561 return -EINVAL;
3562
3563 return ethtool_op_set_tx_csum(dev, data);
3564}
3565
3566
3567static int sky2_set_tso(struct net_device *dev, u32 data)
3568{
3569 if (data && no_tx_offload(dev))
3570 return -EINVAL;
3571
3572 return ethtool_op_set_tso(dev, data);
3573}
3574
f4331a6d
SH		 3575static int sky2_get_eeprom_len(struct net_device *dev)
3576{
3577 struct sky2_port *sky2 = netdev_priv(dev);
3578 u16 reg2;
3579
3580 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3581 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3582}
3583
3584static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3585{
3586 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3587
3588 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3589 cpu_relax();
3590 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3591}
3592
3593static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3594{
3595 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3596 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3597 do {
3598 cpu_relax();
3599 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3600}
3601
3602static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3603 u8 *data)
3604{
3605 struct sky2_port *sky2 = netdev_priv(dev);
3606 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3607 int length = eeprom->len;
3608 u16 offset = eeprom->offset;
3609
3610 if (!cap)
3611 return -EINVAL;
3612
3613 eeprom->magic = SKY2_EEPROM_MAGIC;
3614
3615 while (length > 0) {
3616 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3617 int n = min_t(int, length, sizeof(val));
3618
3619 memcpy(data, &val, n);
3620 length -= n;
3621 data += n;
3622 offset += n;
3623 }
3624 return 0;
3625}
3626
3627static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3628 u8 *data)
3629{
3630 struct sky2_port *sky2 = netdev_priv(dev);
3631 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3632 int length = eeprom->len;
3633 u16 offset = eeprom->offset;
3634
3635 if (!cap)
3636 return -EINVAL;
3637
3638 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3639 return -EINVAL;
3640
3641 while (length > 0) {
3642 u32 val;
3643 int n = min_t(int, length, sizeof(val));
3644
3645 if (n < sizeof(val))
3646 val = sky2_vpd_read(sky2->hw, cap, offset);
3647 memcpy(&val, data, n);
3648
3649 sky2_vpd_write(sky2->hw, cap, offset, val);
3650
3651 length -= n;
3652 data += n;
3653 offset += n;
3654 }
3655 return 0;
3656}
3657
3658
7282d491 3659static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3660 .get_settings = sky2_get_settings,
3661 .set_settings = sky2_set_settings,
3662 .get_drvinfo = sky2_get_drvinfo,
3663 .get_wol = sky2_get_wol,
3664 .set_wol = sky2_set_wol,
3665 .get_msglevel = sky2_get_msglevel,
3666 .set_msglevel = sky2_set_msglevel,
3667 .nway_reset = sky2_nway_reset,
3668 .get_regs_len = sky2_get_regs_len,
3669 .get_regs = sky2_get_regs,
3670 .get_link = ethtool_op_get_link,
3671 .get_eeprom_len = sky2_get_eeprom_len,
3672 .get_eeprom = sky2_get_eeprom,
3673 .set_eeprom = sky2_set_eeprom,
3674 .get_sg = ethtool_op_get_sg,
3675 .set_sg = ethtool_op_set_sg,
3676 .get_tx_csum = ethtool_op_get_tx_csum,
3677 .set_tx_csum = sky2_set_tx_csum,
3678 .get_tso = ethtool_op_get_tso,
3679 .set_tso = sky2_set_tso,
3680 .get_rx_csum = sky2_get_rx_csum,
3681 .set_rx_csum = sky2_set_rx_csum,
3682 .get_strings = sky2_get_strings,
3683 .get_coalesce = sky2_get_coalesce,
3684 .set_coalesce = sky2_set_coalesce,
3685 .get_ringparam = sky2_get_ringparam,
3686 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3687 .get_pauseparam = sky2_get_pauseparam,
3688 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3689 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3690 .get_stats_count = sky2_get_stats_count,
3691 .get_ethtool_stats = sky2_get_ethtool_stats,
3692};
3693
3cf26753
SH		 3694#ifdef CONFIG_SKY2_DEBUG
3695
3696static struct dentry *sky2_debug;
3697
3698static int sky2_debug_show(struct seq_file *seq, void *v)
3699{
3700 struct net_device *dev = seq->private;
3701 const struct sky2_port *sky2 = netdev_priv(dev);
3702 const struct sky2_hw *hw = sky2->hw;
3703 unsigned port = sky2->port;
3704 unsigned idx, last;
3705 int sop;
3706
3707 if (!netif_running(dev))
3708 return -ENETDOWN;
3709
3710 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3711 sky2_read32(hw, B0_ISRC),
3712 sky2_read32(hw, B0_IMSK),
3713 sky2_read32(hw, B0_Y2_SP_ICR));
3714
3715 netif_poll_disable(hw->dev[0]);
3716 last = sky2_read16(hw, STAT_PUT_IDX);
3717
3718 if (hw->st_idx == last)
3719 seq_puts(seq, "Status ring (empty)\n");
3720 else {
3721 seq_puts(seq, "Status ring\n");
3722 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3723 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3724 const struct sky2_status_le *le = hw->st_le + idx;
3725 seq_printf(seq, "[%d] %#x %d %#x\n",
3726 idx, le->opcode, le->length, le->status);
3727 }
3728 seq_puts(seq, "\n");
3729 }
3730
3731 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3732 sky2->tx_cons, sky2->tx_prod,
3733 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3734 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3735
3736 /* Dump contents of tx ring */
3737 sop = 1;
3738 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3739 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3740 const struct sky2_tx_le *le = sky2->tx_le + idx;
3741 u32 a = le32_to_cpu(le->addr);
3742
3743 if (sop)
3744 seq_printf(seq, "%u:", idx);
3745 sop = 0;
3746
3747 switch(le->opcode & ~HW_OWNER) {
3748 case OP_ADDR64:
3749 seq_printf(seq, " %#x:", a);
3750 break;
3751 case OP_LRGLEN:
3752 seq_printf(seq, " mtu=%d", a);
3753 break;
3754 case OP_VLAN:
3755 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3756 break;
3757 case OP_TCPLISW:
3758 seq_printf(seq, " csum=%#x", a);
3759 break;
3760 case OP_LARGESEND:
3761 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3762 break;
3763 case OP_PACKET:
3764 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3765 break;
3766 case OP_BUFFER:
3767 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3768 break;
3769 default:
3770 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3771 a, le16_to_cpu(le->length));
3772 }
3773
3774 if (le->ctrl & EOP) {
3775 seq_putc(seq, '\n');
3776 sop = 1;
3777 }
3778 }
3779
3780 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3781 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3782 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3783 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3784
3785 netif_poll_enable(hw->dev[0]);
3786 return 0;
3787}
3788
3789static int sky2_debug_open(struct inode *inode, struct file *file)
3790{
3791 return single_open(file, sky2_debug_show, inode->i_private);
3792}
3793
3794static const struct file_operations sky2_debug_fops = {
3795 .owner = THIS_MODULE,
3796 .open = sky2_debug_open,
3797 .read = seq_read,
3798 .llseek = seq_lseek,
3799 .release = single_release,
3800};
3801
3802/*
3803 * Use network device events to create/remove/rename
3804 * debugfs file entries
3805 */
3806static int sky2_device_event(struct notifier_block *unused,
3807 unsigned long event, void *ptr)
3808{
3809 struct net_device *dev = ptr;
3810
3811 if (dev->open == sky2_up) {
3812 struct sky2_port *sky2 = netdev_priv(dev);
3813
3814 switch(event) {
3815 case NETDEV_CHANGENAME:
3816 if (!netif_running(dev))
3817 break;
3818 /* fallthrough */
3819 case NETDEV_DOWN:
3820 case NETDEV_GOING_DOWN:
3821 if (sky2->debugfs) {
3822 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3823 dev->name);
3824 debugfs_remove(sky2->debugfs);
3825 sky2->debugfs = NULL;
3826 }
3827
3828 if (event != NETDEV_CHANGENAME)
3829 break;
3830 /* fallthrough for changename */
3831 case NETDEV_UP:
3832 if (sky2_debug) {
3833 struct dentry *d;
3834 d = debugfs_create_file(dev->name, S_IRUGO,
3835 sky2_debug, dev,
3836 &sky2_debug_fops);
3837 if (d == NULL || IS_ERR(d))
3838 printk(KERN_INFO PFX
3839 "%s: debugfs create failed\n",
3840 dev->name);
3841 else
3842 sky2->debugfs = d;
3843 }
3844 break;
3845 }
3846 }
3847
3848 return NOTIFY_DONE;
3849}
3850
3851static struct notifier_block sky2_notifier = {
3852 .notifier_call = sky2_device_event,
3853};
3854
3855
3856static __init void sky2_debug_init(void)
3857{
3858 struct dentry *ent;
3859
3860 ent = debugfs_create_dir("sky2", NULL);
3861 if (!ent || IS_ERR(ent))
3862 return;
3863
3864 sky2_debug = ent;
3865 register_netdevice_notifier(&sky2_notifier);
3866}
3867
3868static __exit void sky2_debug_cleanup(void)
3869{
3870 if (sky2_debug) {
3871 unregister_netdevice_notifier(&sky2_notifier);
3872 debugfs_remove(sky2_debug);
3873 sky2_debug = NULL;
3874 }
3875}
3876
3877#else
3878#define sky2_debug_init()
3879#define sky2_debug_cleanup()
3880#endif
3881
3882
cd28ab6a
SH		 3883/* Initialize network device */
3884static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3885 unsigned port,
3886 int highmem, int wol)
cd28ab6a
SH		 3887{
3888 struct sky2_port *sky2;
3889 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3890
3891 if (!dev) {
b02a9258 3892 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3893 return NULL;
3894 }
3895
3896 SET_MODULE_OWNER(dev);
3897 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3898 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3899 dev->open = sky2_up;
3900 dev->stop = sky2_down;
ef743d33 3901 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3902 dev->hard_start_xmit = sky2_xmit_frame;
3903 dev->get_stats = sky2_get_stats;
3904 dev->set_multicast_list = sky2_set_multicast;
3905 dev->set_mac_address = sky2_set_mac_address;
3906 dev->change_mtu = sky2_change_mtu;
3907 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3908 dev->tx_timeout = sky2_tx_timeout;
3909 dev->watchdog_timeo = TX_WATCHDOG;
3910 if (port == 0)
3911 dev->poll = sky2_poll;
3912 dev->weight = NAPI_WEIGHT;
3913#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3914 /* Network console (only works on port 0)
3915 * because netpoll makes assumptions about NAPI
3916 */
3917 if (port == 0)
3918 dev->poll_controller = sky2_netpoll;
cd28ab6a 3919#endif
cd28ab6a
SH		 3920
3921 sky2 = netdev_priv(dev);
3922 sky2->netdev = dev;
3923 sky2->hw = hw;
3924 sky2->msg_enable = netif_msg_init(debug, default_msg);
3925
05745c4a
SH		 3926 /* This chip has hardware problems that generates
3927 * bogus PHY receive status so by default shut up the message.
3928 */
3929 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
3930 hw->chip_rev == CHIP_REV_YU_FE2_A0)
3931 sky2->msg_enable &= ~NETIF_MSG_RX_ERR;
3932
cd28ab6a
SH		 3933 /* Auto speed and flow control */
3934 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3935 sky2->flow_mode = FC_BOTH;
3936
cd28ab6a
SH		 3937 sky2->duplex = -1;
3938 sky2->speed = -1;
3939 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3940 sky2->rx_csum = 1;
e3173832 3941 sky2->wol = wol;
75d070c5 3942
e07b1aa8 3943 spin_lock_init(&sky2->phy_lock);
793b883e 3944 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3945 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3946
3947 hw->dev[port] = dev;
3948
3949 sky2->port = port;
3950
4a50a876 3951 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3952 if (highmem)
3953 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3954
d1f13708 3955#ifdef SKY2_VLAN_TAG_USED
3956 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3957 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708 3958#endif
3959
cd28ab6a 3960 /* read the mac address */
793b883e 3961 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3962 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3963
cd28ab6a
SH		 3964 return dev;
3965}
3966
28bd181a 3967static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3968{
3969 const struct sky2_port *sky2 = netdev_priv(dev);
3970
3971 if (netif_msg_probe(sky2))
3972 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3973 dev->name,
3974 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3975 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3976}
3977
fb2690a9 3978/* Handle software interrupt used during MSI test */
7d12e780 3979static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3980{
3981 struct sky2_hw *hw = dev_id;
3982 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3983
3984 if (status == 0)
3985 return IRQ_NONE;
3986
3987 if (status & Y2_IS_IRQ_SW) {
ea76e635 3988 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 3989 wake_up(&hw->msi_wait);
3990 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3991 }
3992 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3993
3994 return IRQ_HANDLED;
3995}
3996
3997/* Test interrupt path by forcing a a software IRQ */
3998static int __devinit sky2_test_msi(struct sky2_hw *hw)
3999{
4000 struct pci_dev *pdev = hw->pdev;
4001 int err;
4002
bb507fe1 4003 init_waitqueue_head (&hw->msi_wait);
4004
fb2690a9
SH		 4005 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4006
b0a20ded 4007 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4008 if (err) {
b02a9258 4009 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4010 return err;
4011 }
4012
fb2690a9 4013 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4014 sky2_read8(hw, B0_CTST);
fb2690a9 4015
ea76e635 4016 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4017
ea76e635 4018 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4019 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4020 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4021 "switching to INTx mode.\n");
fb2690a9
SH		 4022
4023 err = -EOPNOTSUPP;
4024 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4025 }
4026
4027 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4028 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4029
4030 free_irq(pdev->irq, hw);
4031
4032 return err;
4033}
4034
e3173832
SH		 4035static int __devinit pci_wake_enabled(struct pci_dev *dev)
4036{
4037 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4038 u16 value;
4039
4040 if (!pm)
4041 return 0;
4042 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4043 return 0;
4044 return value & PCI_PM_CTRL_PME_ENABLE;
4045}
4046
cd28ab6a
SH		 4047static int __devinit sky2_probe(struct pci_dev *pdev,
4048 const struct pci_device_id *ent)
4049{
7f60c64b 4050 struct net_device *dev;
cd28ab6a 4051 struct sky2_hw *hw;
e3173832 4052 int err, using_dac = 0, wol_default;
cd28ab6a 4053
793b883e
SH		 4054 err = pci_enable_device(pdev);
4055 if (err) {
b02a9258 4056 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4057 goto err_out;
4058 }
4059
793b883e
SH		 4060 err = pci_request_regions(pdev, DRV_NAME);
4061 if (err) {
b02a9258 4062 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4063 goto err_out_disable;
cd28ab6a
SH		 4064 }
4065
4066 pci_set_master(pdev);
4067
d1f3d4dd
SH		 4068 if (sizeof(dma_addr_t) > sizeof(u32) &&
4069 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4070 using_dac = 1;
4071 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4072 if (err < 0) {
b02a9258
SH		 4073 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4074 "for consistent allocations\n");
d1f3d4dd
SH		 4075 goto err_out_free_regions;
4076 }
d1f3d4dd 4077 } else {
cd28ab6a
SH		 4078 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4079 if (err) {
b02a9258 4080 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4081 goto err_out_free_regions;
4082 }
4083 }
d1f3d4dd 4084
e3173832
SH		 4085 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4086
cd28ab6a 4087 err = -ENOMEM;
6aad85d6 4088 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4089 if (!hw) {
b02a9258 4090 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4091 goto err_out_free_regions;
4092 }
4093
cd28ab6a 4094 hw->pdev = pdev;
cd28ab6a
SH		 4095
4096 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4097 if (!hw->regs) {
b02a9258 4098 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4099 goto err_out_free_hw;
4100 }
4101
56a645cc 4102#ifdef __BIG_ENDIAN
f65b138c
SH		 4103 /* The sk98lin vendor driver uses hardware byte swapping but
4104 * this driver uses software swapping.
4105 */
56a645cc
SH		 4106 {
4107 u32 reg;
56a645cc 4108 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 4109 reg &= ~PCI_REV_DESC;
56a645cc
SH		 4110 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4111 }
4112#endif
4113
08c06d8a
SH		 4114 /* ring for status responses */
4115 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
4116 &hw->st_dma);
4117 if (!hw->st_le)
4118 goto err_out_iounmap;
4119
e3173832 4120 err = sky2_init(hw);
cd28ab6a 4121 if (err)
793b883e 4122 goto err_out_iounmap;
cd28ab6a 4123
b02a9258 4124 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 4125 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4126 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 4127 hw->chip_id, hw->chip_rev);
cd28ab6a 4128
e3173832
SH		 4129 sky2_reset(hw);
4130
4131 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4132 if (!dev) {
4133 err = -ENOMEM;
cd28ab6a 4134 goto err_out_free_pci;
7f60c64b 4135 }
cd28ab6a 4136
9fa1b1f3
SH		 4137 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4138 err = sky2_test_msi(hw);
4139 if (err == -EOPNOTSUPP)
4140 pci_disable_msi(pdev);
4141 else if (err)
4142 goto err_out_free_netdev;
4143 }
4144
793b883e
SH		 4145 err = register_netdev(dev);
4146 if (err) {
b02a9258 4147 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4148 goto err_out_free_netdev;
4149 }
4150
ea76e635
SH		 4151 err = request_irq(pdev->irq, sky2_intr,
4152 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4153 dev->name, hw);
9fa1b1f3 4154 if (err) {
b02a9258 4155 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4156 goto err_out_unregister;
4157 }
4158 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4159
cd28ab6a
SH		 4160 sky2_show_addr(dev);
4161
7f60c64b 4162 if (hw->ports > 1) {
4163 struct net_device *dev1;
4164
e3173832 4165 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4166 if (!dev1)
4167 dev_warn(&pdev->dev, "allocation for second device failed\n");
4168 else if ((err = register_netdev(dev1))) {
4169 dev_warn(&pdev->dev,
4170 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4171 hw->dev[1] = NULL;
4172 free_netdev(dev1);
b02a9258
SH		 4173 } else
4174 sky2_show_addr(dev1);
cd28ab6a
SH		 4175 }
4176
32c2c300 4177 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4178 INIT_WORK(&hw->restart_work, sky2_restart);
4179
793b883e
SH		 4180 pci_set_drvdata(pdev, hw);
4181
cd28ab6a
SH		 4182 return 0;
4183
793b883e 4184err_out_unregister:
ea76e635 4185 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4186 pci_disable_msi(pdev);
793b883e 4187 unregister_netdev(dev);
cd28ab6a
SH		 4188err_out_free_netdev:
4189 free_netdev(dev);
cd28ab6a 4190err_out_free_pci:
793b883e 4191 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4192 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4193err_out_iounmap:
4194 iounmap(hw->regs);
4195err_out_free_hw:
4196 kfree(hw);
4197err_out_free_regions:
4198 pci_release_regions(pdev);
44a1d2e5 4199err_out_disable:
cd28ab6a 4200 pci_disable_device(pdev);
cd28ab6a 4201err_out:
549a68c3 4202 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4203 return err;
4204}
4205
4206static void __devexit sky2_remove(struct pci_dev *pdev)
4207{
793b883e 4208 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4209 struct net_device *dev0, *dev1;
4210
793b883e 4211 if (!hw)
cd28ab6a
SH		 4212 return;
4213
32c2c300 4214 del_timer_sync(&hw->watchdog_timer);
d27ed387 4215
81906791
SH		 4216 flush_scheduled_work();
4217
d27ed387 4218 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4219 synchronize_irq(hw->pdev->irq);
4220
cd28ab6a 4221 dev0 = hw->dev[0];
793b883e
SH		 4222 dev1 = hw->dev[1];
4223 if (dev1)
4224 unregister_netdev(dev1);
cd28ab6a
SH		 4225 unregister_netdev(dev0);
4226
ae306cca
SH		 4227 sky2_power_aux(hw);
4228
cd28ab6a 4229 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4230 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4231 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4232
4233 free_irq(pdev->irq, hw);
ea76e635 4234 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4235 pci_disable_msi(pdev);
793b883e 4236 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4237 pci_release_regions(pdev);
4238 pci_disable_device(pdev);
793b883e 4239
cd28ab6a
SH		 4240 if (dev1)
4241 free_netdev(dev1);
4242 free_netdev(dev0);
4243 iounmap(hw->regs);
4244 kfree(hw);
5afa0a9c 4245
cd28ab6a
SH		 4246 pci_set_drvdata(pdev, NULL);
4247}
4248
4249#ifdef CONFIG_PM
4250static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4251{
793b883e 4252 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4253 int i, wol = 0;
cd28ab6a 4254
549a68c3
SH		 4255 if (!hw)
4256 return 0;
4257
6a5706b9 4258 netif_poll_disable(hw->dev[0]);
eb35cf60 4259
f05267e7 4260 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4261 struct net_device *dev = hw->dev[i];
e3173832 4262 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4263
e3173832 4264 if (netif_running(dev))
5afa0a9c 4265 sky2_down(dev);
e3173832
SH		 4266
4267 if (sky2->wol)
4268 sky2_wol_init(sky2);
4269
4270 wol |= sky2->wol;
cd28ab6a
SH		 4271 }
4272
8ab8fca2 4273 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4274 sky2_power_aux(hw);
e3173832 4275
d374c1c1 4276 pci_save_state(pdev);
e3173832 4277 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4278 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4279
2ccc99b7 4280 return 0;
cd28ab6a
SH		 4281}
4282
4283static int sky2_resume(struct pci_dev *pdev)
4284{
793b883e 4285 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4286 int i, err;
cd28ab6a 4287
549a68c3
SH		 4288 if (!hw)
4289 return 0;
4290
ae306cca
SH		 4291 err = pci_set_power_state(pdev, PCI_D0);
4292 if (err)
4293 goto out;
4294
4295 err = pci_restore_state(pdev);
4296 if (err)
4297 goto out;
4298
cd28ab6a 4299 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4300
4301 /* Re-enable all clocks */
05745c4a
SH		 4302 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4303 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4304 hw->chip_id == CHIP_ID_YUKON_FE_P)
1ad5b4a5
SH		 4305 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4306
e3173832 4307 sky2_reset(hw);
cd28ab6a 4308
8ab8fca2
SH		 4309 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4310
f05267e7 4311 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4312 struct net_device *dev = hw->dev[i];
6a5706b9 4313 if (netif_running(dev)) {
08c06d8a
SH		 4314 err = sky2_up(dev);
4315 if (err) {
4316 printk(KERN_ERR PFX "%s: could not up: %d\n",
4317 dev->name, err);
4318 dev_close(dev);
eb35cf60 4319 goto out;
5afa0a9c 4320 }
d1b139c0
SH		 4321
4322 sky2_set_multicast(dev);
cd28ab6a
SH		 4323 }
4324 }
eb35cf60 4325
6a5706b9 4326 netif_poll_enable(hw->dev[0]);
32c2c300 4327
ae306cca 4328 return 0;
08c06d8a 4329out:
b02a9258 4330 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4331 pci_disable_device(pdev);
08c06d8a 4332 return err;
cd28ab6a
SH		 4333}
4334#endif
4335
e3173832
SH		 4336static void sky2_shutdown(struct pci_dev *pdev)
4337{
4338 struct sky2_hw *hw = pci_get_drvdata(pdev);
4339 int i, wol = 0;
4340
549a68c3
SH		 4341 if (!hw)
4342 return;
4343
e3173832
SH		 4344 netif_poll_disable(hw->dev[0]);
4345
4346 for (i = 0; i < hw->ports; i++) {
4347 struct net_device *dev = hw->dev[i];
4348 struct sky2_port *sky2 = netdev_priv(dev);
4349
4350 if (sky2->wol) {
4351 wol = 1;
4352 sky2_wol_init(sky2);
4353 }
4354 }
4355
4356 if (wol)
4357 sky2_power_aux(hw);
4358
4359 pci_enable_wake(pdev, PCI_D3hot, wol);
4360 pci_enable_wake(pdev, PCI_D3cold, wol);
4361
4362 pci_disable_device(pdev);
4363 pci_set_power_state(pdev, PCI_D3hot);
4364
4365}
4366
cd28ab6a 4367static struct pci_driver sky2_driver = {
793b883e
SH		 4368 .name = DRV_NAME,
4369 .id_table = sky2_id_table,
4370 .probe = sky2_probe,
4371 .remove = __devexit_p(sky2_remove),
cd28ab6a 4372#ifdef CONFIG_PM
793b883e
SH		 4373 .suspend = sky2_suspend,
4374 .resume = sky2_resume,
cd28ab6a 4375#endif
e3173832 4376 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4377};
4378
4379static int __init sky2_init_module(void)
4380{
3cf26753 4381 sky2_debug_init();
50241c4c 4382 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4383}
4384
4385static void __exit sky2_cleanup_module(void)
4386{
4387 pci_unregister_driver(&sky2_driver);
3cf26753 4388 sky2_debug_cleanup();
cd28ab6a
SH		 4389}
4390
4391module_init(sky2_init_module);
4392module_exit(sky2_cleanup_module);
4393
4394MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4395MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4396MODULE_LICENSE("GPL");
5f4f9dc1 4397MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
This page took 0.565752 seconds and 5 git commands to generate.