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sky2: clear PCI power control reg at startup
[deliverable/linux.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
0640b8dc 54#define DRV_VERSION "1.16"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
cb5d9547
SH		 83#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
cd28ab6a 85static const u32 default_msg =
793b883e
SH		 86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 89
793b883e 90static int debug = -1; /* defaults above */
cd28ab6a
SH		 91module_param(debug, int, 0);
92MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
14d0263f 94static int copybreak __read_mostly = 128;
bdb5c58e
SH		 95module_param(copybreak, int, 0);
96MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
fb2690a9
SH		 98static int disable_msi = 0;
99module_param(disable_msi, int, 0);
100MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
c59697e0 102static int idle_timeout = 100;
01bd7564 103module_param(idle_timeout, int, 0);
e561a83b 104MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 105
cd28ab6a 106static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 137 { 0 }
138};
793b883e 139
cd28ab6a
SH		 140MODULE_DEVICE_TABLE(pci, sky2_id_table);
141
142/* Avoid conditionals by using array */
143static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
144static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 145static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 146
92f965e8
SH		 147/* This driver supports yukon2 chipset only */
148static const char *yukon2_name[] = {
149 "XL", /* 0xb3 */
150 "EC Ultra", /* 0xb4 */
93745494 151 "Extreme", /* 0xb5 */
92f965e8
SH		 152 "EC", /* 0xb6 */
153 "FE", /* 0xb7 */
793b883e
SH		 154};
155
793b883e 156/* Access to external PHY */
ef743d33 157static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 158{
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 166 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
793b883e 168 udelay(1);
cd28ab6a 169 }
ef743d33 170
793b883e 171 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 172 return -ETIMEDOUT;
cd28ab6a
SH		 173}
174
ef743d33 175static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 176{
177 int i;
178
793b883e 179 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 180 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
181
182 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33 183 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
184 *val = gma_read16(hw, port, GM_SMI_DATA);
185 return 0;
186 }
187
793b883e 188 udelay(1);
cd28ab6a
SH		 189 }
190
ef743d33 191 return -ETIMEDOUT;
192}
193
194static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
195{
196 u16 v;
197
198 if (__gm_phy_read(hw, port, reg, &v) != 0)
199 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
200 return v;
cd28ab6a
SH		 201}
202
5afa0a9c 203
ae306cca
SH		 204static void sky2_power_on(struct sky2_hw *hw)
205{
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw, B0_POWER_CTRL,
208 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 209
ae306cca
SH		 210 /* disable Core Clock Division, */
211 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 212
ae306cca
SH		 213 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
214 /* enable bits are inverted */
215 sky2_write8(hw, B2_Y2_CLK_GATE,
216 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
217 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
218 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
219 else
220 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 221
b2345773
SH		 222 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
223 hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 224 u32 reg;
5afa0a9c 225
b2345773
SH		 226 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
227
fc99fe06
SH		 228 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
229 /* set all bits to 0 except bits 15..12 and 8 */
230 reg &= P_ASPM_CONTROL_MSK;
231 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
232
233 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
234 /* set all bits to 0 except bits 28 & 27 */
235 reg &= P_CTL_TIM_VMAIN_AV_MSK;
236 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
237
238 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 239
240 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
241 reg = sky2_read32(hw, B2_GP_IO);
242 reg |= GLB_GPIO_STAT_RACE_DIS;
243 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 244
245 sky2_read32(hw, B2_GP_IO);
5afa0a9c 246 }
ae306cca 247}
5afa0a9c 248
ae306cca
SH		 249static void sky2_power_aux(struct sky2_hw *hw)
250{
251 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
252 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
253 else
254 /* enable bits are inverted */
255 sky2_write8(hw, B2_Y2_CLK_GATE,
256 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
257 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
258 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
259
260 /* switch power to VAUX */
261 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
262 sky2_write8(hw, B0_POWER_CTRL,
263 (PC_VAUX_ENA | PC_VCC_ENA |
264 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c 265}
266
d3bcfbeb 267static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 268{
269 u16 reg;
270
271 /* disable all GMAC IRQ's */
272 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
273 /* disable PHY IRQs */
274 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 275
cd28ab6a
SH		 276 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
277 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
278 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
280
281 reg = gma_read16(hw, port, GM_RX_CTRL);
282 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
283 gma_write16(hw, port, GM_RX_CTRL, reg);
284}
285
16ad91e1
SH		 286/* flow control to advertise bits */
287static const u16 copper_fc_adv[] = {
288 [FC_NONE] = 0,
289 [FC_TX] = PHY_M_AN_ASP,
290 [FC_RX] = PHY_M_AN_PC,
291 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
292};
293
294/* flow control to advertise bits when using 1000BaseX */
295static const u16 fiber_fc_adv[] = {
296 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
297 [FC_TX] = PHY_M_P_ASYM_MD_X,
298 [FC_RX] = PHY_M_P_SYM_MD_X,
299 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
300};
301
302/* flow control to GMA disable bits */
303static const u16 gm_fc_disable[] = {
304 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
305 [FC_TX] = GM_GPCR_FC_RX_DIS,
306 [FC_RX] = GM_GPCR_FC_TX_DIS,
307 [FC_BOTH] = 0,
308};
309
310
cd28ab6a
SH		 311static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
312{
313 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 314 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 315
93745494
SH		 316 if (sky2->autoneg == AUTONEG_ENABLE
317 && !(hw->chip_id == CHIP_ID_YUKON_XL
318 || hw->chip_id == CHIP_ID_YUKON_EC_U
319 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 320 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
321
322 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 323 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 324 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
325
53419c68 326 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 327 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 328 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 329 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
330 else
53419c68
SH		 331 /* set master & slave downshift counter to 1x */
332 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 333
334 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
335 }
336
337 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 338 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 339 if (hw->chip_id == CHIP_ID_YUKON_FE) {
340 /* enable automatic crossover */
341 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
342 } else {
343 /* disable energy detect */
344 ctrl &= ~PHY_M_PC_EN_DET_MSK;
345
346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
348
53419c68 349 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 350 if (sky2->autoneg == AUTONEG_ENABLE
351 && (hw->chip_id == CHIP_ID_YUKON_XL
352 || hw->chip_id == CHIP_ID_YUKON_EC_U
353 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 354 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 355 ctrl &= ~PHY_M_PC_DSC_MSK;
356 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
357 }
358 }
cd28ab6a
SH		 359 } else {
360 /* workaround for deviation #4.88 (CRC errors) */
361 /* disable Automatic Crossover */
362
363 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 364 }
cd28ab6a 365
b89165f2
SH		 366 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
367
368 /* special setup for PHY 88E1112 Fiber */
369 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
370 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 371
b89165f2
SH		 372 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
374 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
375 ctrl &= ~PHY_M_MAC_MD_MSK;
376 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
377 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
378
379 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 380 /* select page 1 to access Fiber registers */
381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 382
383 /* for SFP-module set SIGDET polarity to low */
384 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
385 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 386 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 387 }
b89165f2
SH		 388
389 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 390 }
391
7800fddc 392 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 393 ct1000 = 0;
394 adv = PHY_AN_CSMA;
2eaba1a2 395 reg = 0;
cd28ab6a
SH		 396
397 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 398 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 399 if (sky2->advertising & ADVERTISED_1000baseT_Full)
400 ct1000 |= PHY_M_1000C_AFD;
401 if (sky2->advertising & ADVERTISED_1000baseT_Half)
402 ct1000 |= PHY_M_1000C_AHD;
403 if (sky2->advertising & ADVERTISED_100baseT_Full)
404 adv |= PHY_M_AN_100_FD;
405 if (sky2->advertising & ADVERTISED_100baseT_Half)
406 adv |= PHY_M_AN_100_HD;
407 if (sky2->advertising & ADVERTISED_10baseT_Full)
408 adv |= PHY_M_AN_10_FD;
409 if (sky2->advertising & ADVERTISED_10baseT_Half)
410 adv |= PHY_M_AN_10_HD;
709c6e7b 411
16ad91e1 412 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 413 } else { /* special defines for FIBER (88E1040S only) */
414 if (sky2->advertising & ADVERTISED_1000baseT_Full)
415 adv |= PHY_M_AN_1000X_AFD;
416 if (sky2->advertising & ADVERTISED_1000baseT_Half)
417 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 418
16ad91e1 419 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 420 }
cd28ab6a
SH		 421
422 /* Restart Auto-negotiation */
423 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
424 } else {
425 /* forced speed/duplex settings */
426 ct1000 = PHY_M_1000C_MSE;
427
2eaba1a2
SH		 428 /* Disable auto update for duplex flow control and speed */
429 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 430
431 switch (sky2->speed) {
432 case SPEED_1000:
433 ctrl |= PHY_CT_SP1000;
2eaba1a2 434 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 435 break;
436 case SPEED_100:
437 ctrl |= PHY_CT_SP100;
2eaba1a2 438 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 439 break;
440 }
441
2eaba1a2
SH		 442 if (sky2->duplex == DUPLEX_FULL) {
443 reg |= GM_GPCR_DUP_FULL;
444 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 445 } else if (sky2->speed < SPEED_1000)
446 sky2->flow_mode = FC_NONE;
2eaba1a2 447
2eaba1a2 448
16ad91e1 449 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 450
451 /* Forward pause packets to GMAC? */
16ad91e1 452 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 453 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
454 else
455 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 456 }
457
2eaba1a2
SH		 458 gma_write16(hw, port, GM_GP_CTRL, reg);
459
cd28ab6a
SH		 460 if (hw->chip_id != CHIP_ID_YUKON_FE)
461 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
462
463 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
464 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
465
466 /* Setup Phy LED's */
467 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
468 ledover = 0;
469
470 switch (hw->chip_id) {
471 case CHIP_ID_YUKON_FE:
472 /* on 88E3082 these bits are at 11..9 (shifted left) */
473 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
474
475 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
476
477 /* delete ACT LED control bits */
478 ctrl &= ~PHY_M_FELP_LED1_MSK;
479 /* change ACT LED control to blink mode */
480 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
481 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
482 break;
483
484 case CHIP_ID_YUKON_XL:
793b883e 485 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 486
487 /* select page 3 to access LED control register */
488 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
489
490 /* set LED Function Control register */
ed6d32c7
SH		 491 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
492 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
493 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
494 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
495 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 496
497 /* set Polarity Control register */
498 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 499 (PHY_M_POLC_LS1_P_MIX(4) |
500 PHY_M_POLC_IS0_P_MIX(4) |
501 PHY_M_POLC_LOS_CTRL(2) |
502 PHY_M_POLC_INIT_CTRL(2) |
503 PHY_M_POLC_STA1_CTRL(2) |
504 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 505
506 /* restore page register */
793b883e 507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 508 break;
93745494 509
ed6d32c7 510 case CHIP_ID_YUKON_EC_U:
93745494 511 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 512 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
513
514 /* select page 3 to access LED control register */
515 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
516
517 /* set LED Function Control register */
518 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
519 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
520 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
521 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
522 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
523
524 /* set Blink Rate in LED Timer Control Register */
525 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
526 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
527 /* restore page register */
528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
529 break;
cd28ab6a
SH		 530
531 default:
532 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
533 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
534 /* turn off the Rx LED (LED_RX) */
0efdf262 535 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 536 }
537
9467a8fc
SH		 538 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
539 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 540 /* apply fixes in PHY AFE */
ed6d32c7
SH		 541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
542
977bdf06 543 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 544 gm_phy_write(hw, port, 0x18, 0xaa99);
545 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 546
977bdf06 547 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 548 gm_phy_write(hw, port, 0x18, 0xa204);
549 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 550
551 /* set page register to 0 */
9467a8fc 552 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 553 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 554 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 555
977bdf06
SH		 556 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
557 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 558 ledover |= PHY_M_LED_MO_100;
977bdf06 559 }
cd28ab6a 560
977bdf06
SH		 561 if (ledover)
562 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
563
564 }
2eaba1a2 565
d571b694 566 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 567 if (sky2->autoneg == AUTONEG_ENABLE)
568 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
569 else
570 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
571}
572
d3bcfbeb 573static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
574{
575 u32 reg1;
576 static const u32 phy_power[]
577 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
578
579 /* looks like this XL is back asswards .. */
580 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
581 onoff = !onoff;
582
aed2cec4 583 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 584 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb 585 if (onoff)
586 /* Turn off phy power saving */
587 reg1 &= ~phy_power[port];
588 else
589 reg1 |= phy_power[port];
590
591 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 592 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 593 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 594 udelay(100);
595}
596
1b537565
SH		 597/* Force a renegotiation */
598static void sky2_phy_reinit(struct sky2_port *sky2)
599{
e07b1aa8 600 spin_lock_bh(&sky2->phy_lock);
1b537565 601 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 602 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 603}
604
e3173832
SH		 605/* Put device in state to listen for Wake On Lan */
606static void sky2_wol_init(struct sky2_port *sky2)
607{
608 struct sky2_hw *hw = sky2->hw;
609 unsigned port = sky2->port;
610 enum flow_control save_mode;
611 u16 ctrl;
612 u32 reg1;
613
614 /* Bring hardware out of reset */
615 sky2_write16(hw, B0_CTST, CS_RST_CLR);
616 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
617
618 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
619 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
620
621 /* Force to 10/100
622 * sky2_reset will re-enable on resume
623 */
624 save_mode = sky2->flow_mode;
625 ctrl = sky2->advertising;
626
627 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
628 sky2->flow_mode = FC_NONE;
629 sky2_phy_power(hw, port, 1);
630 sky2_phy_reinit(sky2);
631
632 sky2->flow_mode = save_mode;
633 sky2->advertising = ctrl;
634
635 /* Set GMAC to no flow control and auto update for speed/duplex */
636 gma_write16(hw, port, GM_GP_CTRL,
637 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
638 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
639
640 /* Set WOL address */
641 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
642 sky2->netdev->dev_addr, ETH_ALEN);
643
644 /* Turn on appropriate WOL control bits */
645 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
646 ctrl = 0;
647 if (sky2->wol & WAKE_PHY)
648 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
649 else
650 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
651
652 if (sky2->wol & WAKE_MAGIC)
653 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
654 else
655 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
656
657 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
658 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
659
660 /* Turn on legacy PCI-Express PME mode */
661 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
662 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
663 reg1 |= PCI_Y2_PME_LEGACY;
664 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
665 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
666
667 /* block receiver */
668 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
669
670}
671
69161611
SH		 672static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
673{
674 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
675 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
676 TX_STFW_ENA |
677 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
678 } else {
679 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
680 /* set Tx GMAC FIFO Almost Empty Threshold */
681 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
682 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
683
684 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
685 TX_JUMBO_ENA | TX_STFW_DIS);
686
687 /* Can't do offload because of lack of store/forward */
688 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
689 | NETIF_F_ALL_CSUM);
690 } else
691 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
692 TX_JUMBO_DIS | TX_STFW_ENA);
693 }
694}
695
cd28ab6a
SH		 696static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
697{
698 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
699 u16 reg;
25cccecc 700 u32 rx_reg;
cd28ab6a
SH		 701 int i;
702 const u8 *addr = hw->dev[port]->dev_addr;
703
f350339c
SH		 704 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
705 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 706
707 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
708
793b883e 709 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 710 /* WA DEV_472 -- looks like crossed wires on port 2 */
711 /* clear GMAC 1 Control reset */
712 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
713 do {
714 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
715 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
716 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
717 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
718 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
719 }
720
793b883e 721 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 722
2eaba1a2
SH		 723 /* Enable Transmit FIFO Underrun */
724 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
725
e07b1aa8 726 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 727 sky2_phy_init(hw, port);
e07b1aa8 728 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 729
730 /* MIB clear */
731 reg = gma_read16(hw, port, GM_PHY_ADDR);
732 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
733
43f2f104
SH		 734 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
735 gma_read16(hw, port, i);
cd28ab6a
SH		 736 gma_write16(hw, port, GM_PHY_ADDR, reg);
737
738 /* transmit control */
739 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
740
741 /* receive control reg: unicast + multicast + no FCS */
742 gma_write16(hw, port, GM_RX_CTRL,
793b883e 743 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 744
745 /* transmit flow control */
746 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
747
748 /* transmit parameter */
749 gma_write16(hw, port, GM_TX_PARAM,
750 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
751 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
752 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
753 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
754
755 /* serial mode register */
756 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 757 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 758
6b1a3aef 759 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 760 reg |= GM_SMOD_JUMBO_ENA;
761
762 gma_write16(hw, port, GM_SERIAL_MODE, reg);
763
cd28ab6a
SH		 764 /* virtual address for data */
765 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
766
793b883e
SH		 767 /* physical address: used for pause frames */
768 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
769
770 /* ignore counter overflows */
cd28ab6a
SH		 771 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
772 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
773 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
774
775 /* Configure Rx MAC FIFO */
776 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 777 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
69161611 778 if (hw->chip_id == CHIP_ID_YUKON_EX)
25cccecc 779 rx_reg |= GMF_RX_OVER_ON;
69161611 780
25cccecc 781 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 782
d571b694 783 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 784 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 785
8df9a876
SH		 786 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
787 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 788
789 /* Configure Tx MAC FIFO */
790 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
791 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 792
93745494 793 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 794 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 795 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 796
69161611 797 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 798 }
799
cd28ab6a
SH		 800}
801
67712901
SH		 802/* Assign Ram Buffer allocation to queue */
803static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 804{
67712901
SH		 805 u32 end;
806
807 /* convert from K bytes to qwords used for hw register */
808 start *= 1024/8;
809 space *= 1024/8;
810 end = start + space - 1;
793b883e 811
cd28ab6a
SH		 812 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
813 sky2_write32(hw, RB_ADDR(q, RB_START), start);
814 sky2_write32(hw, RB_ADDR(q, RB_END), end);
815 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
816 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
817
818 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 819 u32 tp = space - space/4;
793b883e 820
1c28f6ba
SH		 821 /* On receive queue's set the thresholds
822 * give receiver priority when > 3/4 full
823 * send pause when down to 2K
824 */
825 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
826 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 827
1c28f6ba
SH		 828 tp = space - 2048/8;
829 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
830 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 831 } else {
832 /* Enable store & forward on Tx queue's because
833 * Tx FIFO is only 1K on Yukon
834 */
835 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
836 }
837
838 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 839 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 840}
841
cd28ab6a 842/* Setup Bus Memory Interface */
af4ed7e6 843static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 844{
845 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
846 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
847 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 848 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 849}
850
cd28ab6a
SH		 851/* Setup prefetch unit registers. This is the interface between
852 * hardware and driver list elements
853 */
8cc048e3 854static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 855 u64 addr, u32 last)
856{
cd28ab6a
SH		 857 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
858 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
859 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
860 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
861 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
862 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 863
864 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 865}
866
793b883e
SH		 867static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
868{
869 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
870
cb5d9547 871 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 872 le->ctrl = 0;
793b883e
SH		 873 return le;
874}
cd28ab6a 875
291ea614
SH		 876static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
877 struct sky2_tx_le *le)
878{
879 return sky2->tx_ring + (le - sky2->tx_le);
880}
881
290d4de5
SH		 882/* Update chip's next pointer */
883static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 884{
50432cb5 885 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 886 wmb();
50432cb5
SH		 887 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
888
889 /* Synchronize I/O on since next processor may write to tail */
890 mmiowb();
cd28ab6a
SH		 891}
892
793b883e 893
cd28ab6a
SH		 894static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
895{
896 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 897 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 898 le->ctrl = 0;
cd28ab6a
SH		 899 return le;
900}
901
14d0263f
SH		 902/* Build description to hardware for one receive segment */
903static void sky2_rx_add(struct sky2_port *sky2, u8 op,
904 dma_addr_t map, unsigned len)
cd28ab6a
SH		 905{
906 struct sky2_rx_le *le;
36eb0c71 907 u32 hi = upper_32_bits(map);
cd28ab6a 908
793b883e 909 if (sky2->rx_addr64 != hi) {
cd28ab6a 910 le = sky2_next_rx(sky2);
793b883e 911 le->addr = cpu_to_le32(hi);
cd28ab6a 912 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 913 sky2->rx_addr64 = upper_32_bits(map + len);
cd28ab6a 914 }
793b883e 915
cd28ab6a 916 le = sky2_next_rx(sky2);
734d1868
SH		 917 le->addr = cpu_to_le32((u32) map);
918 le->length = cpu_to_le16(len);
14d0263f 919 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 920}
921
14d0263f
SH		 922/* Build description to hardware for one possibly fragmented skb */
923static void sky2_rx_submit(struct sky2_port *sky2,
924 const struct rx_ring_info *re)
925{
926 int i;
927
928 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
929
930 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
931 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
932}
933
934
935static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
936 unsigned size)
937{
938 struct sk_buff *skb = re->skb;
939 int i;
940
941 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
942 pci_unmap_len_set(re, data_size, size);
943
944 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
945 re->frag_addr[i] = pci_map_page(pdev,
946 skb_shinfo(skb)->frags[i].page,
947 skb_shinfo(skb)->frags[i].page_offset,
948 skb_shinfo(skb)->frags[i].size,
949 PCI_DMA_FROMDEVICE);
950}
951
952static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
953{
954 struct sk_buff *skb = re->skb;
955 int i;
956
957 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
958 PCI_DMA_FROMDEVICE);
959
960 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
961 pci_unmap_page(pdev, re->frag_addr[i],
962 skb_shinfo(skb)->frags[i].size,
963 PCI_DMA_FROMDEVICE);
964}
793b883e 965
cd28ab6a
SH		 966/* Tell chip where to start receive checksum.
967 * Actually has two checksums, but set both same to avoid possible byte
968 * order problems.
969 */
793b883e 970static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 971{
972 struct sky2_rx_le *le;
973
69161611
SH		 974 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
975 le = sky2_next_rx(sky2);
976 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
977 le->ctrl = 0;
978 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 979
69161611
SH		 980 sky2_write32(sky2->hw,
981 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
982 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
983 }
cd28ab6a
SH		 984
985}
986
6b1a3aef 987/*
988 * The RX Stop command will not work for Yukon-2 if the BMU does not
989 * reach the end of packet and since we can't make sure that we have
990 * incoming data, we must reset the BMU while it is not doing a DMA
991 * transfer. Since it is possible that the RX path is still active,
992 * the RX RAM buffer will be stopped first, so any possible incoming
993 * data will not trigger a DMA. After the RAM buffer is stopped, the
994 * BMU is polled until any DMA in progress is ended and only then it
995 * will be reset.
996 */
997static void sky2_rx_stop(struct sky2_port *sky2)
998{
999 struct sky2_hw *hw = sky2->hw;
1000 unsigned rxq = rxqaddr[sky2->port];
1001 int i;
1002
1003 /* disable the RAM Buffer receive queue */
1004 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1005
1006 for (i = 0; i < 0xffff; i++)
1007 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1008 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1009 goto stopped;
1010
1011 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1012 sky2->netdev->name);
1013stopped:
1014 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1015
1016 /* reset the Rx prefetch unit */
1017 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1018 mmiowb();
6b1a3aef 1019}
793b883e 1020
d571b694 1021/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1022static void sky2_rx_clean(struct sky2_port *sky2)
1023{
1024 unsigned i;
1025
1026 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1027 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1028 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1029
1030 if (re->skb) {
14d0263f 1031 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1032 kfree_skb(re->skb);
1033 re->skb = NULL;
1034 }
1035 }
1036}
1037
ef743d33 1038/* Basic MII support */
1039static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1040{
1041 struct mii_ioctl_data *data = if_mii(ifr);
1042 struct sky2_port *sky2 = netdev_priv(dev);
1043 struct sky2_hw *hw = sky2->hw;
1044 int err = -EOPNOTSUPP;
1045
1046 if (!netif_running(dev))
1047 return -ENODEV; /* Phy still in reset */
1048
d89e1343 1049 switch (cmd) {
ef743d33 1050 case SIOCGMIIPHY:
1051 data->phy_id = PHY_ADDR_MARV;
1052
1053 /* fallthru */
1054 case SIOCGMIIREG: {
1055 u16 val = 0;
91c86df5 1056
e07b1aa8 1057 spin_lock_bh(&sky2->phy_lock);
ef743d33 1058 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1059 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1060
ef743d33 1061 data->val_out = val;
1062 break;
1063 }
1064
1065 case SIOCSMIIREG:
1066 if (!capable(CAP_NET_ADMIN))
1067 return -EPERM;
1068
e07b1aa8 1069 spin_lock_bh(&sky2->phy_lock);
ef743d33 1070 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1071 data->val_in);
e07b1aa8 1072 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1073 break;
1074 }
1075 return err;
1076}
1077
d1f13708 1078#ifdef SKY2_VLAN_TAG_USED
1079static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1080{
1081 struct sky2_port *sky2 = netdev_priv(dev);
1082 struct sky2_hw *hw = sky2->hw;
1083 u16 port = sky2->port;
d1f13708 1084
2bb8c262 1085 netif_tx_lock_bh(dev);
3d4e66f5 1086 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1087
d1f13708 1088 sky2->vlgrp = grp;
3d4e66f5
SH		 1089 if (grp) {
1090 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1091 RX_VLAN_STRIP_ON);
1092 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1093 TX_VLAN_TAG_ON);
1094 } else {
1095 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1096 RX_VLAN_STRIP_OFF);
1097 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1098 TX_VLAN_TAG_OFF);
1099 }
d1f13708 1100
3d4e66f5 1101 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1102 netif_tx_unlock_bh(dev);
d1f13708 1103}
1104#endif
1105
82788c7a 1106/*
14d0263f
SH		 1107 * Allocate an skb for receiving. If the MTU is large enough
1108 * make the skb non-linear with a fragment list of pages.
1109 *
82788c7a
SH		 1110 * It appears the hardware has a bug in the FIFO logic that
1111 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86 1112 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1113 * aligned except if slab debugging is enabled.
82788c7a 1114 */
14d0263f 1115static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1116{
1117 struct sk_buff *skb;
14d0263f
SH		 1118 unsigned long p;
1119 int i;
82788c7a 1120
14d0263f
SH		 1121 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1122 if (!skb)
1123 goto nomem;
1124
1125 p = (unsigned long) skb->data;
1126 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1127
1128 for (i = 0; i < sky2->rx_nfrags; i++) {
1129 struct page *page = alloc_page(GFP_ATOMIC);
1130
1131 if (!page)
1132 goto free_partial;
1133 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1134 }
1135
1136 return skb;
14d0263f
SH		 1137free_partial:
1138 kfree_skb(skb);
1139nomem:
1140 return NULL;
82788c7a
SH		 1141}
1142
55c9dd35
SH		 1143static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1144{
1145 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1146}
1147
cd28ab6a
SH		 1148/*
1149 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1150 * Normal case this ends up creating one list element for skb
1151 * in the receive ring. Worst case if using large MTU and each
1152 * allocation falls on a different 64 bit region, that results
1153 * in 6 list elements per ring entry.
1154 * One element is used for checksum enable/disable, and one
1155 * extra to avoid wrap.
cd28ab6a 1156 */
6b1a3aef 1157static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1158{
6b1a3aef 1159 struct sky2_hw *hw = sky2->hw;
14d0263f 1160 struct rx_ring_info *re;
6b1a3aef 1161 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1162 unsigned i, size, space, thresh;
cd28ab6a 1163
6b1a3aef 1164 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1165 sky2_qset(hw, rxq);
977bdf06 1166
c3905bc4
SH		 1167 /* On PCI express lowering the watermark gives better performance */
1168 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1169 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1170
1171 /* These chips have no ram buffer?
1172 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1173 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1174 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1175 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1176 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1177
6b1a3aef 1178 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1179
1180 rx_set_checksum(sky2);
14d0263f
SH		 1181
1182 /* Space needed for frame data + headers rounded up */
f957da2a 1183 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1184
1185 /* Stopping point for hardware truncation */
1186 thresh = (size - 8) / sizeof(u32);
1187
1188 /* Account for overhead of skb - to avoid order > 0 allocation */
1189 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1190 + sizeof(struct skb_shared_info);
1191
1192 sky2->rx_nfrags = space >> PAGE_SHIFT;
1193 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1194
1195 if (sky2->rx_nfrags != 0) {
1196 /* Compute residue after pages */
1197 space = sky2->rx_nfrags << PAGE_SHIFT;
1198
1199 if (space < size)
1200 size -= space;
1201 else
1202 size = 0;
1203
1204 /* Optimize to handle small packets and headers */
1205 if (size < copybreak)
1206 size = copybreak;
1207 if (size < ETH_HLEN)
1208 size = ETH_HLEN;
1209 }
1210 sky2->rx_data_size = size;
1211
1212 /* Fill Rx ring */
793b883e 1213 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1214 re = sky2->rx_ring + i;
cd28ab6a 1215
14d0263f 1216 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1217 if (!re->skb)
1218 goto nomem;
1219
14d0263f
SH		 1220 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1221 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1222 }
1223
a1433ac4
SH		 1224 /*
1225 * The receiver hangs if it receives frames larger than the
1226 * packet buffer. As a workaround, truncate oversize frames, but
1227 * the register is limited to 9 bits, so if you do frames > 2052
1228 * you better get the MTU right!
1229 */
a1433ac4
SH		 1230 if (thresh > 0x1ff)
1231 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1232 else {
1233 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1234 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1235 }
1236
6b1a3aef 1237 /* Tell chip about available buffers */
55c9dd35 1238 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1239 return 0;
1240nomem:
1241 sky2_rx_clean(sky2);
1242 return -ENOMEM;
1243}
1244
1245/* Bring up network interface. */
1246static int sky2_up(struct net_device *dev)
1247{
1248 struct sky2_port *sky2 = netdev_priv(dev);
1249 struct sky2_hw *hw = sky2->hw;
1250 unsigned port = sky2->port;
67712901 1251 u32 ramsize, imask;
ee7abb04 1252 int cap, err = -ENOMEM;
843a46f4 1253 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1254
ee7abb04
SH		 1255 /*
1256 * On dual port PCI-X card, there is an problem where status
1257 * can be received out of order due to split transactions
843a46f4 1258 */
ee7abb04
SH		 1259 if (otherdev && netif_running(otherdev) &&
1260 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1261 struct sky2_port *osky2 = netdev_priv(otherdev);
1262 u16 cmd;
1263
1264 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1265 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1266 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1267
1268 sky2->rx_csum = 0;
1269 osky2->rx_csum = 0;
1270 }
843a46f4 1271
cd28ab6a
SH		 1272 if (netif_msg_ifup(sky2))
1273 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1274
55d7b4e6
SH		 1275 netif_carrier_off(dev);
1276
cd28ab6a
SH		 1277 /* must be power of 2 */
1278 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1279 TX_RING_SIZE *
1280 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1281 &sky2->tx_le_map);
1282 if (!sky2->tx_le)
1283 goto err_out;
1284
6cdbbdf3 1285 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1286 GFP_KERNEL);
1287 if (!sky2->tx_ring)
1288 goto err_out;
1289 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1290
1291 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1292 &sky2->rx_le_map);
1293 if (!sky2->rx_le)
1294 goto err_out;
1295 memset(sky2->rx_le, 0, RX_LE_BYTES);
1296
291ea614 1297 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1298 GFP_KERNEL);
1299 if (!sky2->rx_ring)
1300 goto err_out;
1301
d3bcfbeb 1302 sky2_phy_power(hw, port, 1);
1303
cd28ab6a
SH		 1304 sky2_mac_init(hw, port);
1305
67712901
SH		 1306 /* Register is number of 4K blocks on internal RAM buffer. */
1307 ramsize = sky2_read8(hw, B2_E_0) * 4;
1308 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1309
67712901
SH		 1310 if (ramsize > 0) {
1311 u32 rxspace;
cd28ab6a 1312
67712901
SH		 1313 if (ramsize < 16)
1314 rxspace = ramsize / 2;
1315 else
1316 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1317
67712901
SH		 1318 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1319 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1320
1321 /* Make sure SyncQ is disabled */
1322 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1323 RB_RST_SET);
1324 }
793b883e 1325
af4ed7e6 1326 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1327
69161611
SH		 1328 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1329 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1330 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1331
977bdf06 1332 /* Set almost empty threshold */
c2716fb4
SH		 1333 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1334 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1335 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1336
6b1a3aef 1337 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1338 TX_RING_SIZE - 1);
cd28ab6a 1339
6b1a3aef 1340 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1341 if (err)
1342 goto err_out;
1343
cd28ab6a 1344 /* Enable interrupts from phy/mac for port */
e07b1aa8 1345 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1346 imask |= portirq_msk[port];
e07b1aa8
SH		 1347 sky2_write32(hw, B0_IMSK, imask);
1348
cd28ab6a
SH		 1349 return 0;
1350
1351err_out:
1b537565 1352 if (sky2->rx_le) {
cd28ab6a
SH		 1353 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1354 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1355 sky2->rx_le = NULL;
1356 }
1357 if (sky2->tx_le) {
cd28ab6a
SH		 1358 pci_free_consistent(hw->pdev,
1359 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1360 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1361 sky2->tx_le = NULL;
1362 }
1363 kfree(sky2->tx_ring);
1364 kfree(sky2->rx_ring);
cd28ab6a 1365
1b537565
SH		 1366 sky2->tx_ring = NULL;
1367 sky2->rx_ring = NULL;
cd28ab6a
SH		 1368 return err;
1369}
1370
793b883e
SH		 1371/* Modular subtraction in ring */
1372static inline int tx_dist(unsigned tail, unsigned head)
1373{
cb5d9547 1374 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1375}
cd28ab6a 1376
793b883e
SH		 1377/* Number of list elements available for next tx */
1378static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1379{
793b883e 1380 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1381}
1382
793b883e 1383/* Estimate of number of transmit list elements required */
28bd181a 1384static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1385{
793b883e
SH		 1386 unsigned count;
1387
1388 count = sizeof(dma_addr_t) / sizeof(u32);
1389 count += skb_shinfo(skb)->nr_frags * count;
1390
89114afd 1391 if (skb_is_gso(skb))
793b883e
SH		 1392 ++count;
1393
84fa7933 1394 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1395 ++count;
1396
1397 return count;
cd28ab6a
SH		 1398}
1399
793b883e
SH		 1400/*
1401 * Put one packet in ring for transmit.
1402 * A single packet can generate multiple list elements, and
1403 * the number of ring elements will probably be less than the number
1404 * of list elements used.
1405 */
cd28ab6a
SH		 1406static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1407{
1408 struct sky2_port *sky2 = netdev_priv(dev);
1409 struct sky2_hw *hw = sky2->hw;
d1f13708 1410 struct sky2_tx_le *le = NULL;
6cdbbdf3 1411 struct tx_ring_info *re;
cd28ab6a
SH		 1412 unsigned i, len;
1413 dma_addr_t mapping;
1414 u32 addr64;
1415 u16 mss;
1416 u8 ctrl;
1417
2bb8c262
SH		 1418 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1419 return NETDEV_TX_BUSY;
cd28ab6a 1420
793b883e 1421 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1422 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1423 dev->name, sky2->tx_prod, skb->len);
1424
cd28ab6a
SH		 1425 len = skb_headlen(skb);
1426 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
36eb0c71 1427 addr64 = upper_32_bits(mapping);
793b883e 1428
a018e330 1429 /* Send high bits if changed or crosses boundary */
36eb0c71
SH		 1430 if (addr64 != sky2->tx_addr64 ||
1431 upper_32_bits(mapping + len) != sky2->tx_addr64) {
793b883e 1432 le = get_tx_le(sky2);
f65b138c 1433 le->addr = cpu_to_le32(addr64);
793b883e 1434 le->opcode = OP_ADDR64 | HW_OWNER;
36eb0c71 1435 sky2->tx_addr64 = upper_32_bits(mapping + len);
793b883e 1436 }
cd28ab6a
SH		 1437
1438 /* Check for TCP Segmentation Offload */
7967168c 1439 mss = skb_shinfo(skb)->gso_size;
793b883e 1440 if (mss != 0) {
69161611
SH		 1441 if (hw->chip_id != CHIP_ID_YUKON_EX)
1442 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1443
1444 if (mss != sky2->tx_last_mss) {
1445 le = get_tx_le(sky2);
1446 le->addr = cpu_to_le32(mss);
1447 if (hw->chip_id == CHIP_ID_YUKON_EX)
1448 le->opcode = OP_MSS | HW_OWNER;
1449 else
1450 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1451 sky2->tx_last_mss = mss;
1452 }
cd28ab6a
SH		 1453 }
1454
cd28ab6a 1455 ctrl = 0;
d1f13708 1456#ifdef SKY2_VLAN_TAG_USED
1457 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1458 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1459 if (!le) {
1460 le = get_tx_le(sky2);
f65b138c 1461 le->addr = 0;
d1f13708 1462 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1463 } else
1464 le->opcode |= OP_VLAN;
1465 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1466 ctrl |= INS_VLAN;
1467 }
1468#endif
1469
1470 /* Handle TCP checksum offload */
84fa7933 1471 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611
SH		 1472 /* On Yukon EX (some versions) encoding change. */
1473 if (hw->chip_id == CHIP_ID_YUKON_EX
1474 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1475 ctrl |= CALSUM; /* auto checksum */
1476 else {
1477 const unsigned offset = skb_transport_offset(skb);
1478 u32 tcpsum;
1479
1480 tcpsum = offset << 16; /* sum start */
1481 tcpsum |= offset + skb->csum_offset; /* sum write */
1482
1483 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1484 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1485 ctrl |= UDPTCP;
1486
1487 if (tcpsum != sky2->tx_tcpsum) {
1488 sky2->tx_tcpsum = tcpsum;
1489
1490 le = get_tx_le(sky2);
1491 le->addr = cpu_to_le32(tcpsum);
1492 le->length = 0; /* initial checksum value */
1493 le->ctrl = 1; /* one packet */
1494 le->opcode = OP_TCPLISW | HW_OWNER;
1495 }
1d179332 1496 }
cd28ab6a
SH		 1497 }
1498
1499 le = get_tx_le(sky2);
f65b138c 1500 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1501 le->length = cpu_to_le16(len);
1502 le->ctrl = ctrl;
793b883e 1503 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1504
291ea614 1505 re = tx_le_re(sky2, le);
cd28ab6a 1506 re->skb = skb;
6cdbbdf3 1507 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1508 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1509
1510 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1511 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1512
1513 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1514 frag->size, PCI_DMA_TODEVICE);
36eb0c71 1515 addr64 = upper_32_bits(mapping);
793b883e
SH		 1516 if (addr64 != sky2->tx_addr64) {
1517 le = get_tx_le(sky2);
f65b138c 1518 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1519 le->ctrl = 0;
1520 le->opcode = OP_ADDR64 | HW_OWNER;
1521 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1522 }
1523
1524 le = get_tx_le(sky2);
f65b138c 1525 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1526 le->length = cpu_to_le16(frag->size);
1527 le->ctrl = ctrl;
793b883e 1528 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1529
291ea614
SH		 1530 re = tx_le_re(sky2, le);
1531 re->skb = skb;
1532 pci_unmap_addr_set(re, mapaddr, mapping);
1533 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1534 }
6cdbbdf3 1535
cd28ab6a
SH		 1536 le->ctrl |= EOP;
1537
97bda706 1538 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1539 netif_stop_queue(dev);
b19666d9 1540
290d4de5 1541 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1542
cd28ab6a
SH		 1543 dev->trans_start = jiffies;
1544 return NETDEV_TX_OK;
1545}
1546
cd28ab6a 1547/*
793b883e
SH		 1548 * Free ring elements from starting at tx_cons until "done"
1549 *
1550 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1551 * buffers so make sure not to free skb to early.
cd28ab6a 1552 */
d11c13e7 1553static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1554{
d11c13e7 1555 struct net_device *dev = sky2->netdev;
af2a58ac 1556 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1557 unsigned idx;
cd28ab6a 1558
0e3ff6aa 1559 BUG_ON(done >= TX_RING_SIZE);
2224795d 1560
291ea614
SH		 1561 for (idx = sky2->tx_cons; idx != done;
1562 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1563 struct sky2_tx_le *le = sky2->tx_le + idx;
1564 struct tx_ring_info *re = sky2->tx_ring + idx;
1565
1566 switch(le->opcode & ~HW_OWNER) {
1567 case OP_LARGESEND:
1568 case OP_PACKET:
1569 pci_unmap_single(pdev,
1570 pci_unmap_addr(re, mapaddr),
1571 pci_unmap_len(re, maplen),
1572 PCI_DMA_TODEVICE);
af2a58ac 1573 break;
291ea614
SH		 1574 case OP_BUFFER:
1575 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1576 pci_unmap_len(re, maplen),
734d1868 1577 PCI_DMA_TODEVICE);
291ea614
SH		 1578 break;
1579 }
1580
1581 if (le->ctrl & EOP) {
1582 if (unlikely(netif_msg_tx_done(sky2)))
1583 printk(KERN_DEBUG "%s: tx done %u\n",
1584 dev->name, idx);
3cf26753 1585
2bf56fe2 1586 sky2->net_stats.tx_packets++;
1587 sky2->net_stats.tx_bytes += re->skb->len;
1588
794b2bd2 1589 dev_kfree_skb_any(re->skb);
3cf26753 1590 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1591 }
793b883e 1592 }
793b883e 1593
291ea614 1594 sky2->tx_cons = idx;
50432cb5
SH		 1595 smp_mb();
1596
22e11703 1597 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1598 netif_wake_queue(dev);
cd28ab6a
SH		 1599}
1600
1601/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1602static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1603{
2bb8c262
SH		 1604 struct sky2_port *sky2 = netdev_priv(dev);
1605
1606 netif_tx_lock_bh(dev);
d11c13e7 1607 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1608 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1609}
1610
1611/* Network shutdown */
1612static int sky2_down(struct net_device *dev)
1613{
1614 struct sky2_port *sky2 = netdev_priv(dev);
1615 struct sky2_hw *hw = sky2->hw;
1616 unsigned port = sky2->port;
1617 u16 ctrl;
e07b1aa8 1618 u32 imask;
cd28ab6a 1619
1b537565
SH		 1620 /* Never really got started! */
1621 if (!sky2->tx_le)
1622 return 0;
1623
cd28ab6a
SH		 1624 if (netif_msg_ifdown(sky2))
1625 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1626
018d1c66 1627 /* Stop more packets from being queued */
cd28ab6a
SH		 1628 netif_stop_queue(dev);
1629
ebc646f6
SH		 1630 /* Disable port IRQ */
1631 imask = sky2_read32(hw, B0_IMSK);
1632 imask &= ~portirq_msk[port];
1633 sky2_write32(hw, B0_IMSK, imask);
1634
d3bcfbeb 1635 sky2_gmac_reset(hw, port);
793b883e 1636
cd28ab6a
SH		 1637 /* Stop transmitter */
1638 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1639 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1640
1641 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1642 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1643
1644 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1645 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1646 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1647
1648 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1649
1650 /* Workaround shared GMAC reset */
793b883e
SH		 1651 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1652 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1653 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1654
1655 /* Disable Force Sync bit and Enable Alloc bit */
1656 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1657 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1658
1659 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1660 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1661 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1662
1663 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1664 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1665 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1666
1667 /* Reset the Tx prefetch units */
1668 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1669 PREF_UNIT_RST_SET);
1670
1671 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1672
6b1a3aef 1673 sky2_rx_stop(sky2);
cd28ab6a
SH		 1674
1675 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1676 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1677
d3bcfbeb 1678 sky2_phy_power(hw, port, 0);
1679
55d7b4e6
SH		 1680 netif_carrier_off(dev);
1681
d571b694 1682 /* turn off LED's */
cd28ab6a
SH		 1683 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1684
018d1c66 1685 synchronize_irq(hw->pdev->irq);
1686
2bb8c262 1687 sky2_tx_clean(dev);
cd28ab6a
SH		 1688 sky2_rx_clean(sky2);
1689
1690 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1691 sky2->rx_le, sky2->rx_le_map);
1692 kfree(sky2->rx_ring);
1693
1694 pci_free_consistent(hw->pdev,
1695 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1696 sky2->tx_le, sky2->tx_le_map);
1697 kfree(sky2->tx_ring);
1698
1b537565
SH		 1699 sky2->tx_le = NULL;
1700 sky2->rx_le = NULL;
1701
1702 sky2->rx_ring = NULL;
1703 sky2->tx_ring = NULL;
1704
cd28ab6a
SH		 1705 return 0;
1706}
1707
1708static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1709{
b89165f2 1710 if (!sky2_is_copper(hw))
793b883e
SH		 1711 return SPEED_1000;
1712
cd28ab6a
SH		 1713 if (hw->chip_id == CHIP_ID_YUKON_FE)
1714 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1715
1716 switch (aux & PHY_M_PS_SPEED_MSK) {
1717 case PHY_M_PS_SPEED_1000:
1718 return SPEED_1000;
1719 case PHY_M_PS_SPEED_100:
1720 return SPEED_100;
1721 default:
1722 return SPEED_10;
1723 }
1724}
1725
1726static void sky2_link_up(struct sky2_port *sky2)
1727{
1728 struct sky2_hw *hw = sky2->hw;
1729 unsigned port = sky2->port;
1730 u16 reg;
16ad91e1
SH		 1731 static const char *fc_name[] = {
1732 [FC_NONE] = "none",
1733 [FC_TX] = "tx",
1734 [FC_RX] = "rx",
1735 [FC_BOTH] = "both",
1736 };
cd28ab6a 1737
cd28ab6a 1738 /* enable Rx/Tx */
2eaba1a2 1739 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1740 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1741 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1742
1743 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1744
1745 netif_carrier_on(sky2->netdev);
cd28ab6a
SH		 1746
1747 /* Turn on link LED */
793b883e 1748 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1749 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1750
93745494
SH		 1751 if (hw->chip_id == CHIP_ID_YUKON_XL
1752 || hw->chip_id == CHIP_ID_YUKON_EC_U
1753 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1754 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1755 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1756
1757 switch(sky2->speed) {
1758 case SPEED_10:
1759 led |= PHY_M_LEDC_INIT_CTRL(7);
1760 break;
1761
1762 case SPEED_100:
1763 led |= PHY_M_LEDC_STA1_CTRL(7);
1764 break;
1765
1766 case SPEED_1000:
1767 led |= PHY_M_LEDC_STA0_CTRL(7);
1768 break;
1769 }
793b883e
SH		 1770
1771 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1772 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1773 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1774 }
1775
cd28ab6a
SH		 1776 if (netif_msg_link(sky2))
1777 printk(KERN_INFO PFX
d571b694 1778 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1779 sky2->netdev->name, sky2->speed,
1780 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1781 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1782}
1783
1784static void sky2_link_down(struct sky2_port *sky2)
1785{
1786 struct sky2_hw *hw = sky2->hw;
1787 unsigned port = sky2->port;
1788 u16 reg;
1789
1790 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1791
1792 reg = gma_read16(hw, port, GM_GP_CTRL);
1793 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1794 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1795
cd28ab6a 1796 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1797
1798 /* Turn on link LED */
1799 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1800
1801 if (netif_msg_link(sky2))
1802 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1803
cd28ab6a
SH		 1804 sky2_phy_init(hw, port);
1805}
1806
16ad91e1
SH		 1807static enum flow_control sky2_flow(int rx, int tx)
1808{
1809 if (rx)
1810 return tx ? FC_BOTH : FC_RX;
1811 else
1812 return tx ? FC_TX : FC_NONE;
1813}
1814
793b883e
SH		 1815static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1816{
1817 struct sky2_hw *hw = sky2->hw;
1818 unsigned port = sky2->port;
da4c1ff4 1819 u16 advert, lpa;
793b883e 1820
da4c1ff4 1821 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1822 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1823 if (lpa & PHY_M_AN_RF) {
1824 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1825 return -1;
1826 }
1827
793b883e
SH		 1828 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1829 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1830 sky2->netdev->name);
1831 return -1;
1832 }
1833
793b883e 1834 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1835 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1836
da4c1ff4
SH		 1837 /* Since the pause result bits seem to in different positions on
1838 * different chips. look at registers.
1839 */
1840 if (!sky2_is_copper(hw)) {
1841 /* Shift for bits in fiber PHY */
1842 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1843 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1844
1845 if (advert & ADVERTISE_1000XPAUSE)
1846 advert |= ADVERTISE_PAUSE_CAP;
1847 if (advert & ADVERTISE_1000XPSE_ASYM)
1848 advert |= ADVERTISE_PAUSE_ASYM;
1849 if (lpa & LPA_1000XPAUSE)
1850 lpa |= LPA_PAUSE_CAP;
1851 if (lpa & LPA_1000XPAUSE_ASYM)
1852 lpa |= LPA_PAUSE_ASYM;
1853 }
793b883e 1854
da4c1ff4
SH		 1855 sky2->flow_status = FC_NONE;
1856 if (advert & ADVERTISE_PAUSE_CAP) {
1857 if (lpa & LPA_PAUSE_CAP)
1858 sky2->flow_status = FC_BOTH;
1859 else if (advert & ADVERTISE_PAUSE_ASYM)
1860 sky2->flow_status = FC_RX;
1861 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1862 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1863 sky2->flow_status = FC_TX;
1864 }
793b883e 1865
16ad91e1 1866 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1867 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1868 sky2->flow_status = FC_NONE;
2eaba1a2 1869
da4c1ff4 1870 if (sky2->flow_status & FC_TX)
793b883e
SH		 1871 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1872 else
1873 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1874
1875 return 0;
1876}
cd28ab6a 1877
e07b1aa8
SH		 1878/* Interrupt from PHY */
1879static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1880{
e07b1aa8
SH		 1881 struct net_device *dev = hw->dev[port];
1882 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1883 u16 istatus, phystat;
1884
ebc646f6
SH		 1885 if (!netif_running(dev))
1886 return;
1887
e07b1aa8
SH		 1888 spin_lock(&sky2->phy_lock);
1889 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1890 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1891
cd28ab6a
SH		 1892 if (netif_msg_intr(sky2))
1893 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1894 sky2->netdev->name, istatus, phystat);
1895
2eaba1a2 1896 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1897 if (sky2_autoneg_done(sky2, phystat) == 0)
1898 sky2_link_up(sky2);
1899 goto out;
1900 }
cd28ab6a 1901
793b883e
SH		 1902 if (istatus & PHY_M_IS_LSP_CHANGE)
1903 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1904
793b883e
SH		 1905 if (istatus & PHY_M_IS_DUP_CHANGE)
1906 sky2->duplex =
1907 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1908
793b883e
SH		 1909 if (istatus & PHY_M_IS_LST_CHANGE) {
1910 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1911 sky2_link_up(sky2);
793b883e
SH		 1912 else
1913 sky2_link_down(sky2);
cd28ab6a 1914 }
793b883e 1915out:
e07b1aa8 1916 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1917}
1918
62335ab0 1919/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1920 * and tx queue is full (stopped).
1921 */
cd28ab6a
SH		 1922static void sky2_tx_timeout(struct net_device *dev)
1923{
1924 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1925 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1926
1927 if (netif_msg_timer(sky2))
1928 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1929
8f24664d 1930 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1931 dev->name, sky2->tx_cons, sky2->tx_prod,
1932 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1933 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1934
81906791
SH		 1935 /* can't restart safely under softirq */
1936 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1937}
1938
1939static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1940{
6b1a3aef 1941 struct sky2_port *sky2 = netdev_priv(dev);
1942 struct sky2_hw *hw = sky2->hw;
b628ed98 1943 unsigned port = sky2->port;
6b1a3aef 1944 int err;
1945 u16 ctl, mode;
e07b1aa8 1946 u32 imask;
cd28ab6a
SH		 1947
1948 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1949 return -EINVAL;
1950
d2adf4f6
SH		 1951 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1952 return -EINVAL;
1953
6b1a3aef 1954 if (!netif_running(dev)) {
1955 dev->mtu = new_mtu;
1956 return 0;
1957 }
1958
e07b1aa8 1959 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 1960 sky2_write32(hw, B0_IMSK, 0);
1961
018d1c66 1962 dev->trans_start = jiffies; /* prevent tx timeout */
1963 netif_stop_queue(dev);
1964 netif_poll_disable(hw->dev[0]);
1965
e07b1aa8
SH		 1966 synchronize_irq(hw->pdev->irq);
1967
69161611
SH		 1968 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1969 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 1970
1971 ctl = gma_read16(hw, port, GM_GP_CTRL);
1972 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 1973 sky2_rx_stop(sky2);
1974 sky2_rx_clean(sky2);
cd28ab6a
SH		 1975
1976 dev->mtu = new_mtu;
14d0263f 1977
6b1a3aef 1978 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1979 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1980
1981 if (dev->mtu > ETH_DATA_LEN)
1982 mode |= GM_SMOD_JUMBO_ENA;
1983
b628ed98 1984 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1985
b628ed98 1986 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1987
6b1a3aef 1988 err = sky2_rx_start(sky2);
e07b1aa8 1989 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1990
1b537565
SH		 1991 if (err)
1992 dev_close(dev);
1993 else {
b628ed98 1994 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1995
1996 netif_poll_enable(hw->dev[0]);
1997 netif_wake_queue(dev);
1998 }
1999
cd28ab6a
SH		 2000 return err;
2001}
2002
14d0263f
SH		 2003/* For small just reuse existing skb for next receive */
2004static struct sk_buff *receive_copy(struct sky2_port *sky2,
2005 const struct rx_ring_info *re,
2006 unsigned length)
2007{
2008 struct sk_buff *skb;
2009
2010 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2011 if (likely(skb)) {
2012 skb_reserve(skb, 2);
2013 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2014 length, PCI_DMA_FROMDEVICE);
d626f62b 2015 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2016 skb->ip_summed = re->skb->ip_summed;
2017 skb->csum = re->skb->csum;
2018 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2019 length, PCI_DMA_FROMDEVICE);
2020 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2021 skb_put(skb, length);
14d0263f
SH		 2022 }
2023 return skb;
2024}
2025
2026/* Adjust length of skb with fragments to match received data */
2027static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2028 unsigned int length)
2029{
2030 int i, num_frags;
2031 unsigned int size;
2032
2033 /* put header into skb */
2034 size = min(length, hdr_space);
2035 skb->tail += size;
2036 skb->len += size;
2037 length -= size;
2038
2039 num_frags = skb_shinfo(skb)->nr_frags;
2040 for (i = 0; i < num_frags; i++) {
2041 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2042
2043 if (length == 0) {
2044 /* don't need this page */
2045 __free_page(frag->page);
2046 --skb_shinfo(skb)->nr_frags;
2047 } else {
2048 size = min(length, (unsigned) PAGE_SIZE);
2049
2050 frag->size = size;
2051 skb->data_len += size;
2052 skb->truesize += size;
2053 skb->len += size;
2054 length -= size;
2055 }
2056 }
2057}
2058
2059/* Normal packet - take skb from ring element and put in a new one */
2060static struct sk_buff *receive_new(struct sky2_port *sky2,
2061 struct rx_ring_info *re,
2062 unsigned int length)
2063{
2064 struct sk_buff *skb, *nskb;
2065 unsigned hdr_space = sky2->rx_data_size;
2066
14d0263f
SH		 2067 /* Don't be tricky about reusing pages (yet) */
2068 nskb = sky2_rx_alloc(sky2);
2069 if (unlikely(!nskb))
2070 return NULL;
2071
2072 skb = re->skb;
2073 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2074
2075 prefetch(skb->data);
2076 re->skb = nskb;
2077 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2078
2079 if (skb_shinfo(skb)->nr_frags)
2080 skb_put_frags(skb, hdr_space, length);
2081 else
489b10c1 2082 skb_put(skb, length);
14d0263f
SH		 2083 return skb;
2084}
2085
cd28ab6a
SH		 2086/*
2087 * Receive one packet.
d571b694 2088 * For larger packets, get new buffer.
cd28ab6a 2089 */
497d7c86 2090static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2091 u16 length, u32 status)
2092{
497d7c86 2093 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2094 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2095 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2096
2097 if (unlikely(netif_msg_rx_status(sky2)))
2098 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2099 dev->name, sky2->rx_next, status, length);
cd28ab6a 2100
793b883e 2101 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2102 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2103
42eeea01 2104 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2105 goto error;
2106
42eeea01 2107 if (!(status & GMR_FS_RX_OK))
2108 goto resubmit;
2109
71749531
SH		 2110 if (status >> 16 != length)
2111 goto len_mismatch;
2112
14d0263f
SH		 2113 if (length < copybreak)
2114 skb = receive_copy(sky2, re, length);
2115 else
2116 skb = receive_new(sky2, re, length);
793b883e 2117resubmit:
14d0263f 2118 sky2_rx_submit(sky2, re);
79e57d32 2119
cd28ab6a
SH		 2120 return skb;
2121
71749531
SH		 2122len_mismatch:
2123 /* Truncation of overlength packets
2124 causes PHY length to not match MAC length */
2125 ++sky2->net_stats.rx_length_errors;
2126
cd28ab6a 2127error:
6e15b712 2128 ++sky2->net_stats.rx_errors;
b6d77734 2129 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2130 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2131 goto resubmit;
2132 }
6e15b712 2133
3be92a70 2134 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2135 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2136 dev->name, status, length);
793b883e
SH		 2137
2138 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2139 sky2->net_stats.rx_length_errors++;
2140 if (status & GMR_FS_FRAGMENT)
2141 sky2->net_stats.rx_frame_errors++;
2142 if (status & GMR_FS_CRC_ERR)
2143 sky2->net_stats.rx_crc_errors++;
79e57d32 2144
793b883e 2145 goto resubmit;
cd28ab6a
SH		 2146}
2147
e07b1aa8
SH		 2148/* Transmit complete */
2149static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2150{
e07b1aa8 2151 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2152
e07b1aa8 2153 if (netif_running(dev)) {
2bb8c262 2154 netif_tx_lock(dev);
e07b1aa8 2155 sky2_tx_complete(sky2, last);
2bb8c262 2156 netif_tx_unlock(dev);
2224795d 2157 }
cd28ab6a
SH		 2158}
2159
e07b1aa8
SH		 2160/* Process status response ring */
2161static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2162{
e07b1aa8 2163 int work_done = 0;
55c9dd35 2164 unsigned rx[2] = { 0, 0 };
e71ebd73 2165 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2166
af2a58ac 2167 rmb();
bea86103 2168
e71ebd73 2169 while (hw->st_idx != hwidx) {
55c9dd35 2170 struct sky2_port *sky2;
13210ce5 2171 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2172 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2173 struct net_device *dev;
cd28ab6a 2174 struct sk_buff *skb;
cd28ab6a
SH		 2175 u32 status;
2176 u16 length;
2177
cb5d9547 2178 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2179
69161611 2180 dev = hw->dev[port];
13210ce5 2181 sky2 = netdev_priv(dev);
f65b138c
SH		 2182 length = le16_to_cpu(le->length);
2183 status = le32_to_cpu(le->status);
cd28ab6a 2184
e71ebd73 2185 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2186 case OP_RXSTAT:
55c9dd35 2187 ++rx[port];
497d7c86 2188 skb = sky2_receive(dev, length, status);
3225b919
SH		 2189 if (unlikely(!skb)) {
2190 sky2->net_stats.rx_dropped++;
55c9dd35 2191 break;
3225b919 2192 }
13210ce5 2193
69161611
SH		 2194 /* This chip reports checksum status differently */
2195 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2196 if (sky2->rx_csum &&
2197 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2198 (le->css & CSS_TCPUDPCSOK))
2199 skb->ip_summed = CHECKSUM_UNNECESSARY;
2200 else
2201 skb->ip_summed = CHECKSUM_NONE;
2202 }
2203
13210ce5 2204 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2205 sky2->net_stats.rx_packets++;
2206 sky2->net_stats.rx_bytes += skb->len;
13210ce5 2207 dev->last_rx = jiffies;
2208
d1f13708 2209#ifdef SKY2_VLAN_TAG_USED
2210 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2211 vlan_hwaccel_receive_skb(skb,
2212 sky2->vlgrp,
2213 be16_to_cpu(sky2->rx_tag));
2214 } else
2215#endif
cd28ab6a 2216 netif_receive_skb(skb);
13210ce5 2217
22e11703 2218 /* Stop after net poll weight */
13210ce5 2219 if (++work_done >= to_do)
2220 goto exit_loop;
cd28ab6a
SH		 2221 break;
2222
d1f13708 2223#ifdef SKY2_VLAN_TAG_USED
2224 case OP_RXVLAN:
2225 sky2->rx_tag = length;
2226 break;
2227
2228 case OP_RXCHKSVLAN:
2229 sky2->rx_tag = length;
2230 /* fall through */
2231#endif
cd28ab6a 2232 case OP_RXCHKS:
87418307
SH		 2233 if (!sky2->rx_csum)
2234 break;
2235
69161611
SH		 2236 if (hw->chip_id == CHIP_ID_YUKON_EX)
2237 break;
2238
87418307
SH		 2239 /* Both checksum counters are programmed to start at
2240 * the same offset, so unless there is a problem they
2241 * should match. This failure is an early indication that
2242 * hardware receive checksumming won't work.
2243 */
2244 if (likely(status >> 16 == (status & 0xffff))) {
2245 skb = sky2->rx_ring[sky2->rx_next].skb;
2246 skb->ip_summed = CHECKSUM_COMPLETE;
2247 skb->csum = status & 0xffff;
2248 } else {
2249 printk(KERN_NOTICE PFX "%s: hardware receive "
2250 "checksum problem (status = %#x)\n",
2251 dev->name, status);
2252 sky2->rx_csum = 0;
2253 sky2_write32(sky2->hw,
69161611 2254 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2255 BMU_DIS_RX_CHKSUM);
2256 }
cd28ab6a
SH		 2257 break;
2258
2259 case OP_TXINDEXLE:
13b97b74 2260 /* TX index reports status for both ports */
f55925d7
SH		 2261 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2262 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2263 if (hw->dev[1])
2264 sky2_tx_done(hw->dev[1],
2265 ((status >> 24) & 0xff)
2266 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2267 break;
2268
cd28ab6a
SH		 2269 default:
2270 if (net_ratelimit())
793b883e 2271 printk(KERN_WARNING PFX
e71ebd73 2272 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a 2273 }
13210ce5 2274 }
cd28ab6a 2275
fe2a24df
SH		 2276 /* Fully processed status ring so clear irq */
2277 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2278
13210ce5 2279exit_loop:
55c9dd35
SH		 2280 if (rx[0])
2281 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2282
55c9dd35
SH		 2283 if (rx[1])
2284 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2285
e07b1aa8 2286 return work_done;
cd28ab6a
SH		 2287}
2288
2289static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2290{
2291 struct net_device *dev = hw->dev[port];
2292
3be92a70
SH		 2293 if (net_ratelimit())
2294 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2295 dev->name, status);
cd28ab6a
SH		 2296
2297 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2298 if (net_ratelimit())
2299 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2300 dev->name);
cd28ab6a
SH		 2301 /* Clear IRQ */
2302 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2303 }
2304
2305 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2306 if (net_ratelimit())
2307 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2308 dev->name);
cd28ab6a
SH		 2309
2310 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2311 }
2312
2313 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2314 if (net_ratelimit())
2315 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2316 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2317 }
2318
2319 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2320 if (net_ratelimit())
2321 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2322 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2323 }
2324
2325 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2326 if (net_ratelimit())
2327 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2328 dev->name);
cd28ab6a
SH		 2329 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2330 }
2331}
2332
2333static void sky2_hw_intr(struct sky2_hw *hw)
2334{
2335 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2336
793b883e 2337 if (status & Y2_IS_TIST_OV)
cd28ab6a 2338 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2339
2340 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2341 u16 pci_err;
2342
56a645cc 2343 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2344 if (net_ratelimit())
b02a9258
SH		 2345 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2346 pci_err);
cd28ab6a
SH		 2347
2348 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2349 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2350 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2351 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2352 }
2353
2354 if (status & Y2_IS_PCI_EXP) {
d571b694 2355 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2356 u32 pex_err;
2357
7bd656d1 2358 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2359
3be92a70 2360 if (net_ratelimit())
b02a9258
SH		 2361 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2362 pex_err);
cd28ab6a
SH		 2363
2364 /* clear the interrupt */
2365 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2366 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2367 0xffffffffUL);
cd28ab6a
SH		 2368 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2369
7bd656d1 2370 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2371 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2372 hwmsk &= ~Y2_IS_PCI_EXP;
2373 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2374 }
2375 }
2376
2377 if (status & Y2_HWE_L1_MASK)
2378 sky2_hw_error(hw, 0, status);
2379 status >>= 8;
2380 if (status & Y2_HWE_L1_MASK)
2381 sky2_hw_error(hw, 1, status);
2382}
2383
2384static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2385{
2386 struct net_device *dev = hw->dev[port];
2387 struct sky2_port *sky2 = netdev_priv(dev);
2388 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2389
2390 if (netif_msg_intr(sky2))
2391 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2392 dev->name, status);
2393
a3caeada
SH		 2394 if (status & GM_IS_RX_CO_OV)
2395 gma_read16(hw, port, GM_RX_IRQ_SRC);
2396
2397 if (status & GM_IS_TX_CO_OV)
2398 gma_read16(hw, port, GM_TX_IRQ_SRC);
2399
cd28ab6a
SH		 2400 if (status & GM_IS_RX_FF_OR) {
2401 ++sky2->net_stats.rx_fifo_errors;
2402 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2403 }
2404
2405 if (status & GM_IS_TX_FF_UR) {
2406 ++sky2->net_stats.tx_fifo_errors;
2407 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2408 }
cd28ab6a
SH		 2409}
2410
40b01727
SH		 2411/* This should never happen it is a bug. */
2412static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2413 u16 q, unsigned ring_size)
d257924e
SH		 2414{
2415 struct net_device *dev = hw->dev[port];
2416 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2417 unsigned idx;
2418 const u64 *le = (q == Q_R1 || q == Q_R2)
2419 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2420
40b01727
SH		 2421 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2422 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2423 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2424 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2425
40b01727 2426 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2427}
cd28ab6a 2428
d27ed387
SH		 2429/* If idle then force a fake soft NAPI poll once a second
2430 * to work around cases where sharing an edge triggered interrupt.
2431 */
eb35cf60
SH		 2432static inline void sky2_idle_start(struct sky2_hw *hw)
2433{
2434 if (idle_timeout > 0)
2435 mod_timer(&hw->idle_timer,
2436 jiffies + msecs_to_jiffies(idle_timeout));
2437}
2438
d27ed387
SH		 2439static void sky2_idle(unsigned long arg)
2440{
01bd7564
SH		 2441 struct sky2_hw *hw = (struct sky2_hw *) arg;
2442 struct net_device *dev = hw->dev[0];
d27ed387 2443
d27ed387
SH		 2444 if (__netif_rx_schedule_prep(dev))
2445 __netif_rx_schedule(dev);
01bd7564
SH		 2446
2447 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2448}
2449
40b01727
SH		 2450/* Hardware/software error handling */
2451static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2452{
40b01727
SH		 2453 if (net_ratelimit())
2454 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2455
1e5f1283
SH		 2456 if (status & Y2_IS_HW_ERR)
2457 sky2_hw_intr(hw);
d257924e 2458
1e5f1283
SH		 2459 if (status & Y2_IS_IRQ_MAC1)
2460 sky2_mac_intr(hw, 0);
cd28ab6a 2461
1e5f1283
SH		 2462 if (status & Y2_IS_IRQ_MAC2)
2463 sky2_mac_intr(hw, 1);
cd28ab6a 2464
1e5f1283 2465 if (status & Y2_IS_CHK_RX1)
40b01727 2466 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2467
1e5f1283 2468 if (status & Y2_IS_CHK_RX2)
40b01727 2469 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2470
1e5f1283 2471 if (status & Y2_IS_CHK_TXA1)
40b01727 2472 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2473
1e5f1283 2474 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2475 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2476}
2477
2478static int sky2_poll(struct net_device *dev0, int *budget)
2479{
2480 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2481 int work_done;
40b01727
SH		 2482 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2483
2484 if (unlikely(status & Y2_IS_ERROR))
2485 sky2_err_intr(hw, status);
2486
2487 if (status & Y2_IS_IRQ_PHY1)
2488 sky2_phy_intr(hw, 0);
2489
2490 if (status & Y2_IS_IRQ_PHY2)
2491 sky2_phy_intr(hw, 1);
cd28ab6a 2492
5c11ce70
SH		 2493 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2494 *budget -= work_done;
2495 dev0->quota -= work_done;
86fba634 2496
5c11ce70
SH		 2497 /* More work? */
2498 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2499 return 1;
5c11ce70
SH		 2500
2501 /* Bug/Errata workaround?
2502 * Need to kick the TX irq moderation timer.
2503 */
2504 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2505 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2506 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2507 }
5c11ce70
SH		 2508 netif_rx_complete(dev0);
2509
2510 sky2_read32(hw, B0_Y2_SP_LISR);
2511 return 0;
e07b1aa8
SH		 2512}
2513
7d12e780 2514static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2515{
2516 struct sky2_hw *hw = dev_id;
2517 struct net_device *dev0 = hw->dev[0];
2518 u32 status;
2519
2520 /* Reading this mask interrupts as side effect */
2521 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2522 if (status == 0 || status == ~0)
2523 return IRQ_NONE;
793b883e 2524
e07b1aa8
SH		 2525 prefetch(&hw->st_le[hw->st_idx]);
2526 if (likely(__netif_rx_schedule_prep(dev0)))
2527 __netif_rx_schedule(dev0);
793b883e 2528
cd28ab6a
SH		 2529 return IRQ_HANDLED;
2530}
2531
2532#ifdef CONFIG_NET_POLL_CONTROLLER
2533static void sky2_netpoll(struct net_device *dev)
2534{
2535 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2536 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2537
88d11360
SH		 2538 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2539 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2540}
2541#endif
2542
2543/* Chip internal frequency for clock calculations */
fb17358f 2544static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2545{
793b883e 2546 switch (hw->chip_id) {
cd28ab6a 2547 case CHIP_ID_YUKON_EC:
5a5b1ea0 2548 case CHIP_ID_YUKON_EC_U:
93745494 2549 case CHIP_ID_YUKON_EX:
fb17358f 2550 return 125; /* 125 Mhz */
cd28ab6a 2551 case CHIP_ID_YUKON_FE:
fb17358f 2552 return 100; /* 100 Mhz */
793b883e 2553 default: /* YUKON_XL */
fb17358f 2554 return 156; /* 156 Mhz */
cd28ab6a
SH		 2555 }
2556}
2557
fb17358f 2558static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2559{
fb17358f 2560 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2561}
2562
fb17358f 2563static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2564{
fb17358f 2565 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2566}
2567
fb17358f 2568
e3173832 2569static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2570{
b89165f2 2571 u8 t8;
cd28ab6a 2572
451af335
SH		 2573 /* Enable all clocks */
2574 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2575
cd28ab6a 2576 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2577
cd28ab6a
SH		 2578 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2579 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2580 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2581 hw->chip_id);
cd28ab6a
SH		 2582 return -EOPNOTSUPP;
2583 }
2584
290d4de5
SH		 2585 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2586
2587 /* This rev is really old, and requires untested workarounds */
2588 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2589 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2590 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2591 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2592 return -EOPNOTSUPP;
2593 }
2594
e3173832
SH		 2595 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2596 hw->ports = 1;
2597 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2598 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2599 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2600 ++hw->ports;
2601 }
2602
2603 return 0;
2604}
2605
2606static void sky2_reset(struct sky2_hw *hw)
2607{
2608 u16 status;
2609 int i;
2610
cd28ab6a 2611 /* disable ASF */
4f44d8ba
SH		 2612 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2613 status = sky2_read16(hw, HCU_CCSR);
2614 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2615 HCU_CCSR_UC_STATE_MSK);
2616 sky2_write16(hw, HCU_CCSR, status);
2617 } else
2618 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2619 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2620
2621 /* do a SW reset */
2622 sky2_write8(hw, B0_CTST, CS_RST_SET);
2623 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2624
2625 /* clear PCI errors, if any */
56a645cc 2626 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2627
cd28ab6a 2628 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2629 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2630
cd28ab6a
SH		 2631
2632 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2633
2634 /* clear any PEX errors */
7bd656d1
SH		 2635 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2636 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2637
cd28ab6a 2638
ae306cca 2639 sky2_power_on(hw);
cd28ab6a
SH		 2640
2641 for (i = 0; i < hw->ports; i++) {
2642 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2643 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2644
2645 if (hw->chip_id == CHIP_ID_YUKON_EX)
2646 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2647 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2648 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2649 }
2650
2651 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2652
793b883e
SH		 2653 /* Clear I2C IRQ noise */
2654 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2655
2656 /* turn off hardware timer (unused) */
2657 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2658 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2659
cd28ab6a
SH		 2660 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2661
69634ee7
SH		 2662 /* Turn off descriptor polling */
2663 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2664
2665 /* Turn off receive timestamp */
2666 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2667 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2668
2669 /* enable the Tx Arbiters */
2670 for (i = 0; i < hw->ports; i++)
2671 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2672
2673 /* Initialize ram interface */
2674 for (i = 0; i < hw->ports; i++) {
793b883e 2675 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2676
2677 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2678 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2679 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2681 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2683 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2684 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2685 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2686 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2687 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2688 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2689 }
2690
7bd656d1 2691 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2692
cd28ab6a 2693 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2694 sky2_gmac_reset(hw, i);
cd28ab6a 2695
cd28ab6a
SH		 2696 memset(hw->st_le, 0, STATUS_LE_BYTES);
2697 hw->st_idx = 0;
2698
2699 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2700 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2701
2702 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2703 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2704
2705 /* Set the list last index */
793b883e 2706 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2707
290d4de5
SH		 2708 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2709 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2710
290d4de5
SH		 2711 /* set Status-FIFO ISR watermark */
2712 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2713 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2714 else
2715 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2716
290d4de5 2717 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2718 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2719 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2720
793b883e 2721 /* enable status unit */
cd28ab6a
SH		 2722 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2723
2724 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2725 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2726 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2727}
2728
81906791
SH		 2729static void sky2_restart(struct work_struct *work)
2730{
2731 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2732 struct net_device *dev;
2733 int i, err;
2734
81906791
SH		 2735 del_timer_sync(&hw->idle_timer);
2736
2737 rtnl_lock();
2738 sky2_write32(hw, B0_IMSK, 0);
2739 sky2_read32(hw, B0_IMSK);
2740
2741 netif_poll_disable(hw->dev[0]);
2742
2743 for (i = 0; i < hw->ports; i++) {
2744 dev = hw->dev[i];
2745 if (netif_running(dev))
2746 sky2_down(dev);
2747 }
2748
2749 sky2_reset(hw);
2750 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2751 netif_poll_enable(hw->dev[0]);
2752
2753 for (i = 0; i < hw->ports; i++) {
2754 dev = hw->dev[i];
2755 if (netif_running(dev)) {
2756 err = sky2_up(dev);
2757 if (err) {
2758 printk(KERN_INFO PFX "%s: could not restart %d\n",
2759 dev->name, err);
2760 dev_close(dev);
2761 }
2762 }
2763 }
2764
2765 sky2_idle_start(hw);
2766
2767 rtnl_unlock();
2768}
2769
e3173832
SH		 2770static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2771{
2772 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2773}
2774
2775static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2776{
2777 const struct sky2_port *sky2 = netdev_priv(dev);
2778
2779 wol->supported = sky2_wol_supported(sky2->hw);
2780 wol->wolopts = sky2->wol;
2781}
2782
2783static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2784{
2785 struct sky2_port *sky2 = netdev_priv(dev);
2786 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2787
e3173832
SH		 2788 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2789 return -EOPNOTSUPP;
2790
2791 sky2->wol = wol->wolopts;
2792
69161611 2793 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
e3173832
SH		 2794 sky2_write32(hw, B0_CTST, sky2->wol
2795 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2796
2797 if (!netif_running(dev))
2798 sky2_wol_init(sky2);
cd28ab6a
SH		 2799 return 0;
2800}
2801
28bd181a 2802static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2803{
b89165f2
SH		 2804 if (sky2_is_copper(hw)) {
2805 u32 modes = SUPPORTED_10baseT_Half
2806 | SUPPORTED_10baseT_Full
2807 | SUPPORTED_100baseT_Half
2808 | SUPPORTED_100baseT_Full
2809 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2810
2811 if (hw->chip_id != CHIP_ID_YUKON_FE)
2812 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2813 | SUPPORTED_1000baseT_Full;
2814 return modes;
cd28ab6a 2815 } else
b89165f2
SH		 2816 return SUPPORTED_1000baseT_Half
2817 | SUPPORTED_1000baseT_Full
2818 | SUPPORTED_Autoneg
2819 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2820}
2821
793b883e 2822static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2823{
2824 struct sky2_port *sky2 = netdev_priv(dev);
2825 struct sky2_hw *hw = sky2->hw;
2826
2827 ecmd->transceiver = XCVR_INTERNAL;
2828 ecmd->supported = sky2_supported_modes(hw);
2829 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2830 if (sky2_is_copper(hw)) {
cd28ab6a 2831 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2832 | SUPPORTED_10baseT_Full
2833 | SUPPORTED_100baseT_Half
2834 | SUPPORTED_100baseT_Full
2835 | SUPPORTED_1000baseT_Half
2836 | SUPPORTED_1000baseT_Full
2837 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2838 ecmd->port = PORT_TP;
b89165f2
SH		 2839 ecmd->speed = sky2->speed;
2840 } else {
2841 ecmd->speed = SPEED_1000;
cd28ab6a 2842 ecmd->port = PORT_FIBRE;
b89165f2 2843 }
cd28ab6a
SH		 2844
2845 ecmd->advertising = sky2->advertising;
2846 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2847 ecmd->duplex = sky2->duplex;
2848 return 0;
2849}
2850
2851static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2852{
2853 struct sky2_port *sky2 = netdev_priv(dev);
2854 const struct sky2_hw *hw = sky2->hw;
2855 u32 supported = sky2_supported_modes(hw);
2856
2857 if (ecmd->autoneg == AUTONEG_ENABLE) {
2858 ecmd->advertising = supported;
2859 sky2->duplex = -1;
2860 sky2->speed = -1;
2861 } else {
2862 u32 setting;
2863
793b883e 2864 switch (ecmd->speed) {
cd28ab6a
SH		 2865 case SPEED_1000:
2866 if (ecmd->duplex == DUPLEX_FULL)
2867 setting = SUPPORTED_1000baseT_Full;
2868 else if (ecmd->duplex == DUPLEX_HALF)
2869 setting = SUPPORTED_1000baseT_Half;
2870 else
2871 return -EINVAL;
2872 break;
2873 case SPEED_100:
2874 if (ecmd->duplex == DUPLEX_FULL)
2875 setting = SUPPORTED_100baseT_Full;
2876 else if (ecmd->duplex == DUPLEX_HALF)
2877 setting = SUPPORTED_100baseT_Half;
2878 else
2879 return -EINVAL;
2880 break;
2881
2882 case SPEED_10:
2883 if (ecmd->duplex == DUPLEX_FULL)
2884 setting = SUPPORTED_10baseT_Full;
2885 else if (ecmd->duplex == DUPLEX_HALF)
2886 setting = SUPPORTED_10baseT_Half;
2887 else
2888 return -EINVAL;
2889 break;
2890 default:
2891 return -EINVAL;
2892 }
2893
2894 if ((setting & supported) == 0)
2895 return -EINVAL;
2896
2897 sky2->speed = ecmd->speed;
2898 sky2->duplex = ecmd->duplex;
2899 }
2900
2901 sky2->autoneg = ecmd->autoneg;
2902 sky2->advertising = ecmd->advertising;
2903
1b537565
SH		 2904 if (netif_running(dev))
2905 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2906
2907 return 0;
2908}
2909
2910static void sky2_get_drvinfo(struct net_device *dev,
2911 struct ethtool_drvinfo *info)
2912{
2913 struct sky2_port *sky2 = netdev_priv(dev);
2914
2915 strcpy(info->driver, DRV_NAME);
2916 strcpy(info->version, DRV_VERSION);
2917 strcpy(info->fw_version, "N/A");
2918 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2919}
2920
2921static const struct sky2_stat {
793b883e
SH		 2922 char name[ETH_GSTRING_LEN];
2923 u16 offset;
cd28ab6a
SH		 2924} sky2_stats[] = {
2925 { "tx_bytes", GM_TXO_OK_HI },
2926 { "rx_bytes", GM_RXO_OK_HI },
2927 { "tx_broadcast", GM_TXF_BC_OK },
2928 { "rx_broadcast", GM_RXF_BC_OK },
2929 { "tx_multicast", GM_TXF_MC_OK },
2930 { "rx_multicast", GM_RXF_MC_OK },
2931 { "tx_unicast", GM_TXF_UC_OK },
2932 { "rx_unicast", GM_RXF_UC_OK },
2933 { "tx_mac_pause", GM_TXF_MPAUSE },
2934 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2935 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2936 { "late_collision",GM_TXF_LAT_COL },
2937 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2938 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2939 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2940
d2604540 2941 { "rx_short", GM_RXF_SHT },
cd28ab6a 2942 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2943 { "rx_64_byte_packets", GM_RXF_64B },
2944 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2945 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2946 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2947 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2948 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2949 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2950 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2951 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2952 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2953 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2954
2955 { "tx_64_byte_packets", GM_TXF_64B },
2956 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2957 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2958 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2959 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2960 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2961 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2962 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2963};
2964
cd28ab6a
SH		 2965static u32 sky2_get_rx_csum(struct net_device *dev)
2966{
2967 struct sky2_port *sky2 = netdev_priv(dev);
2968
2969 return sky2->rx_csum;
2970}
2971
2972static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2973{
2974 struct sky2_port *sky2 = netdev_priv(dev);
2975
2976 sky2->rx_csum = data;
793b883e 2977
cd28ab6a
SH		 2978 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2979 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2980
2981 return 0;
2982}
2983
2984static u32 sky2_get_msglevel(struct net_device *netdev)
2985{
2986 struct sky2_port *sky2 = netdev_priv(netdev);
2987 return sky2->msg_enable;
2988}
2989
9a7ae0a9
SH		 2990static int sky2_nway_reset(struct net_device *dev)
2991{
2992 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2993
16ad91e1 2994 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2995 return -EINVAL;
2996
1b537565 2997 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2998
2999 return 0;
3000}
3001
793b883e 3002static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3003{
3004 struct sky2_hw *hw = sky2->hw;
3005 unsigned port = sky2->port;
3006 int i;
3007
3008 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3009 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3010 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3011 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3012
793b883e 3013 for (i = 2; i < count; i++)
cd28ab6a
SH		 3014 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3015}
3016
cd28ab6a
SH		 3017static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3018{
3019 struct sky2_port *sky2 = netdev_priv(netdev);
3020 sky2->msg_enable = value;
3021}
3022
3023static int sky2_get_stats_count(struct net_device *dev)
3024{
3025 return ARRAY_SIZE(sky2_stats);
3026}
3027
3028static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3029 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3030{
3031 struct sky2_port *sky2 = netdev_priv(dev);
3032
793b883e 3033 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3034}
3035
793b883e 3036static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3037{
3038 int i;
3039
3040 switch (stringset) {
3041 case ETH_SS_STATS:
3042 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3043 memcpy(data + i * ETH_GSTRING_LEN,
3044 sky2_stats[i].name, ETH_GSTRING_LEN);
3045 break;
3046 }
3047}
3048
cd28ab6a
SH		 3049static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3050{
3051 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3052 return &sky2->net_stats;
3053}
3054
3055static int sky2_set_mac_address(struct net_device *dev, void *p)
3056{
3057 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3058 struct sky2_hw *hw = sky2->hw;
3059 unsigned port = sky2->port;
3060 const struct sockaddr *addr = p;
cd28ab6a
SH		 3061
3062 if (!is_valid_ether_addr(addr->sa_data))
3063 return -EADDRNOTAVAIL;
3064
cd28ab6a 3065 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3066 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3067 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3068 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3069 dev->dev_addr, ETH_ALEN);
1b537565 3070
a8ab1ec0
SH		 3071 /* virtual address for data */
3072 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3073
3074 /* physical address: used for pause frames */
3075 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3076
3077 return 0;
cd28ab6a
SH		 3078}
3079
a052b52f
SH		 3080static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3081{
3082 u32 bit;
3083
3084 bit = ether_crc(ETH_ALEN, addr) & 63;
3085 filter[bit >> 3] |= 1 << (bit & 7);
3086}
3087
cd28ab6a
SH		 3088static void sky2_set_multicast(struct net_device *dev)
3089{
3090 struct sky2_port *sky2 = netdev_priv(dev);
3091 struct sky2_hw *hw = sky2->hw;
3092 unsigned port = sky2->port;
3093 struct dev_mc_list *list = dev->mc_list;
3094 u16 reg;
3095 u8 filter[8];
a052b52f
SH		 3096 int rx_pause;
3097 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3098
a052b52f 3099 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3100 memset(filter, 0, sizeof(filter));
3101
3102 reg = gma_read16(hw, port, GM_RX_CTRL);
3103 reg |= GM_RXCR_UCF_ENA;
3104
d571b694 3105 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3106 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3107 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3108 memset(filter, 0xff, sizeof(filter));
a052b52f 3109 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3110 reg &= ~GM_RXCR_MCF_ENA;
3111 else {
3112 int i;
3113 reg |= GM_RXCR_MCF_ENA;
3114
a052b52f
SH		 3115 if (rx_pause)
3116 sky2_add_filter(filter, pause_mc_addr);
3117
3118 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3119 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3120 }
3121
cd28ab6a 3122 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3123 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3124 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3125 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3126 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3127 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3128 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3129 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3130
3131 gma_write16(hw, port, GM_RX_CTRL, reg);
3132}
3133
3134/* Can have one global because blinking is controlled by
3135 * ethtool and that is always under RTNL mutex
3136 */
91c86df5 3137static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3138{
793b883e
SH		 3139 u16 pg;
3140
793b883e
SH		 3141 switch (hw->chip_id) {
3142 case CHIP_ID_YUKON_XL:
3143 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3144 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3145 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3146 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3147 PHY_M_LEDC_INIT_CTRL(7) |
3148 PHY_M_LEDC_STA1_CTRL(7) |
3149 PHY_M_LEDC_STA0_CTRL(7))
3150 : 0);
3151
3152 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3153 break;
3154
3155 default:
3156 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3157 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3158 on ? PHY_M_LED_ALL : 0);
793b883e 3159 }
cd28ab6a
SH		 3160}
3161
3162/* blink LED's for finding board */
3163static int sky2_phys_id(struct net_device *dev, u32 data)
3164{
3165 struct sky2_port *sky2 = netdev_priv(dev);
3166 struct sky2_hw *hw = sky2->hw;
3167 unsigned port = sky2->port;
793b883e 3168 u16 ledctrl, ledover = 0;
cd28ab6a 3169 long ms;
91c86df5 3170 int interrupted;
cd28ab6a
SH		 3171 int onoff = 1;
3172
793b883e 3173 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3174 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3175 else
3176 ms = data * 1000;
3177
3178 /* save initial values */
e07b1aa8 3179 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3180 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3181 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3182 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3183 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3184 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3185 } else {
3186 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3187 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3188 }
cd28ab6a 3189
91c86df5
SH		 3190 interrupted = 0;
3191 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3192 sky2_led(hw, port, onoff);
3193 onoff = !onoff;
3194
e07b1aa8 3195 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3196 interrupted = msleep_interruptible(250);
e07b1aa8 3197 spin_lock_bh(&sky2->phy_lock);
91c86df5 3198
cd28ab6a
SH		 3199 ms -= 250;
3200 }
3201
3202 /* resume regularly scheduled programming */
793b883e
SH		 3203 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3204 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3205 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3206 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3207 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3208 } else {
3209 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3210 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3211 }
e07b1aa8 3212 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3213
3214 return 0;
3215}
3216
3217static void sky2_get_pauseparam(struct net_device *dev,
3218 struct ethtool_pauseparam *ecmd)
3219{
3220 struct sky2_port *sky2 = netdev_priv(dev);
3221
16ad91e1
SH		 3222 switch (sky2->flow_mode) {
3223 case FC_NONE:
3224 ecmd->tx_pause = ecmd->rx_pause = 0;
3225 break;
3226 case FC_TX:
3227 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3228 break;
3229 case FC_RX:
3230 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3231 break;
3232 case FC_BOTH:
3233 ecmd->tx_pause = ecmd->rx_pause = 1;
3234 }
3235
cd28ab6a
SH		 3236 ecmd->autoneg = sky2->autoneg;
3237}
3238
3239static int sky2_set_pauseparam(struct net_device *dev,
3240 struct ethtool_pauseparam *ecmd)
3241{
3242 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3243
3244 sky2->autoneg = ecmd->autoneg;
16ad91e1 3245 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3246
16ad91e1
SH		 3247 if (netif_running(dev))
3248 sky2_phy_reinit(sky2);
cd28ab6a 3249
2eaba1a2 3250 return 0;
cd28ab6a
SH		 3251}
3252
fb17358f
SH		 3253static int sky2_get_coalesce(struct net_device *dev,
3254 struct ethtool_coalesce *ecmd)
3255{
3256 struct sky2_port *sky2 = netdev_priv(dev);
3257 struct sky2_hw *hw = sky2->hw;
3258
3259 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3260 ecmd->tx_coalesce_usecs = 0;
3261 else {
3262 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3263 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3264 }
3265 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3266
3267 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3268 ecmd->rx_coalesce_usecs = 0;
3269 else {
3270 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3271 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3272 }
3273 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3274
3275 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3276 ecmd->rx_coalesce_usecs_irq = 0;
3277 else {
3278 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3279 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3280 }
3281
3282 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3283
3284 return 0;
3285}
3286
3287/* Note: this affect both ports */
3288static int sky2_set_coalesce(struct net_device *dev,
3289 struct ethtool_coalesce *ecmd)
3290{
3291 struct sky2_port *sky2 = netdev_priv(dev);
3292 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3293 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3294
77b3d6a2
SH		 3295 if (ecmd->tx_coalesce_usecs > tmax ||
3296 ecmd->rx_coalesce_usecs > tmax ||
3297 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3298 return -EINVAL;
3299
ff81fbbe 3300 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3301 return -EINVAL;
ff81fbbe 3302 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3303 return -EINVAL;
ff81fbbe 3304 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3305 return -EINVAL;
3306
3307 if (ecmd->tx_coalesce_usecs == 0)
3308 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3309 else {
3310 sky2_write32(hw, STAT_TX_TIMER_INI,
3311 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3312 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3313 }
3314 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3315
3316 if (ecmd->rx_coalesce_usecs == 0)
3317 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3318 else {
3319 sky2_write32(hw, STAT_LEV_TIMER_INI,
3320 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3321 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3322 }
3323 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3324
3325 if (ecmd->rx_coalesce_usecs_irq == 0)
3326 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3327 else {
d28d4870 3328 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3329 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3330 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3331 }
3332 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3333 return 0;
3334}
3335
793b883e
SH		 3336static void sky2_get_ringparam(struct net_device *dev,
3337 struct ethtool_ringparam *ering)
3338{
3339 struct sky2_port *sky2 = netdev_priv(dev);
3340
3341 ering->rx_max_pending = RX_MAX_PENDING;
3342 ering->rx_mini_max_pending = 0;
3343 ering->rx_jumbo_max_pending = 0;
3344 ering->tx_max_pending = TX_RING_SIZE - 1;
3345
3346 ering->rx_pending = sky2->rx_pending;
3347 ering->rx_mini_pending = 0;
3348 ering->rx_jumbo_pending = 0;
3349 ering->tx_pending = sky2->tx_pending;
3350}
3351
3352static int sky2_set_ringparam(struct net_device *dev,
3353 struct ethtool_ringparam *ering)
3354{
3355 struct sky2_port *sky2 = netdev_priv(dev);
3356 int err = 0;
3357
3358 if (ering->rx_pending > RX_MAX_PENDING ||
3359 ering->rx_pending < 8 ||
3360 ering->tx_pending < MAX_SKB_TX_LE ||
3361 ering->tx_pending > TX_RING_SIZE - 1)
3362 return -EINVAL;
3363
3364 if (netif_running(dev))
3365 sky2_down(dev);
3366
3367 sky2->rx_pending = ering->rx_pending;
3368 sky2->tx_pending = ering->tx_pending;
3369
1b537565 3370 if (netif_running(dev)) {
793b883e 3371 err = sky2_up(dev);
1b537565
SH		 3372 if (err)
3373 dev_close(dev);
6ed995bb
SH		 3374 else
3375 sky2_set_multicast(dev);
1b537565 3376 }
793b883e
SH		 3377
3378 return err;
3379}
3380
793b883e
SH		 3381static int sky2_get_regs_len(struct net_device *dev)
3382{
6e4cbb34 3383 return 0x4000;
793b883e
SH		 3384}
3385
3386/*
3387 * Returns copy of control register region
3ead5db7 3388 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3389 */
3390static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3391 void *p)
3392{
3393 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3394 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3395
3396 regs->version = 1;
6e4cbb34 3397 memset(p, 0, regs->len);
793b883e 3398
6e4cbb34
SH		 3399 memcpy_fromio(p, io, B3_RAM_ADDR);
3400
3ead5db7
SH		 3401 /* skip diagnostic ram region */
3402 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3403
3404 /* copy GMAC registers */
3405 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3406 if (sky2->hw->ports > 1)
3407 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3408
793b883e 3409}
cd28ab6a 3410
b628ed98
SH		 3411/* In order to do Jumbo packets on these chips, need to turn off the
3412 * transmit store/forward. Therefore checksum offload won't work.
3413 */
3414static int no_tx_offload(struct net_device *dev)
3415{
3416 const struct sky2_port *sky2 = netdev_priv(dev);
3417 const struct sky2_hw *hw = sky2->hw;
3418
69161611 3419 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3420}
3421
3422static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3423{
3424 if (data && no_tx_offload(dev))
3425 return -EINVAL;
3426
3427 return ethtool_op_set_tx_csum(dev, data);
3428}
3429
3430
3431static int sky2_set_tso(struct net_device *dev, u32 data)
3432{
3433 if (data && no_tx_offload(dev))
3434 return -EINVAL;
3435
3436 return ethtool_op_set_tso(dev, data);
3437}
3438
f4331a6d
SH		 3439static int sky2_get_eeprom_len(struct net_device *dev)
3440{
3441 struct sky2_port *sky2 = netdev_priv(dev);
3442 u16 reg2;
3443
3444 reg2 = sky2_pci_read32(sky2->hw, PCI_DEV_REG2);
3445 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3446}
3447
3448static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3449{
3450 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3451
3452 while (!(sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F))
3453 cpu_relax();
3454 return sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3455}
3456
3457static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3458{
3459 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3460 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3461 do {
3462 cpu_relax();
3463 } while (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F);
3464}
3465
3466static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3467 u8 *data)
3468{
3469 struct sky2_port *sky2 = netdev_priv(dev);
3470 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3471 int length = eeprom->len;
3472 u16 offset = eeprom->offset;
3473
3474 if (!cap)
3475 return -EINVAL;
3476
3477 eeprom->magic = SKY2_EEPROM_MAGIC;
3478
3479 while (length > 0) {
3480 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3481 int n = min_t(int, length, sizeof(val));
3482
3483 memcpy(data, &val, n);
3484 length -= n;
3485 data += n;
3486 offset += n;
3487 }
3488 return 0;
3489}
3490
3491static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3492 u8 *data)
3493{
3494 struct sky2_port *sky2 = netdev_priv(dev);
3495 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3496 int length = eeprom->len;
3497 u16 offset = eeprom->offset;
3498
3499 if (!cap)
3500 return -EINVAL;
3501
3502 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3503 return -EINVAL;
3504
3505 while (length > 0) {
3506 u32 val;
3507 int n = min_t(int, length, sizeof(val));
3508
3509 if (n < sizeof(val))
3510 val = sky2_vpd_read(sky2->hw, cap, offset);
3511 memcpy(&val, data, n);
3512
3513 sky2_vpd_write(sky2->hw, cap, offset, val);
3514
3515 length -= n;
3516 data += n;
3517 offset += n;
3518 }
3519 return 0;
3520}
3521
3522
7282d491 3523static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3524 .get_settings = sky2_get_settings,
3525 .set_settings = sky2_set_settings,
3526 .get_drvinfo = sky2_get_drvinfo,
3527 .get_wol = sky2_get_wol,
3528 .set_wol = sky2_set_wol,
3529 .get_msglevel = sky2_get_msglevel,
3530 .set_msglevel = sky2_set_msglevel,
3531 .nway_reset = sky2_nway_reset,
3532 .get_regs_len = sky2_get_regs_len,
3533 .get_regs = sky2_get_regs,
3534 .get_link = ethtool_op_get_link,
3535 .get_eeprom_len = sky2_get_eeprom_len,
3536 .get_eeprom = sky2_get_eeprom,
3537 .set_eeprom = sky2_set_eeprom,
3538 .get_sg = ethtool_op_get_sg,
3539 .set_sg = ethtool_op_set_sg,
3540 .get_tx_csum = ethtool_op_get_tx_csum,
3541 .set_tx_csum = sky2_set_tx_csum,
3542 .get_tso = ethtool_op_get_tso,
3543 .set_tso = sky2_set_tso,
3544 .get_rx_csum = sky2_get_rx_csum,
3545 .set_rx_csum = sky2_set_rx_csum,
3546 .get_strings = sky2_get_strings,
3547 .get_coalesce = sky2_get_coalesce,
3548 .set_coalesce = sky2_set_coalesce,
3549 .get_ringparam = sky2_get_ringparam,
3550 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3551 .get_pauseparam = sky2_get_pauseparam,
3552 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3553 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3554 .get_stats_count = sky2_get_stats_count,
3555 .get_ethtool_stats = sky2_get_ethtool_stats,
3556};
3557
3cf26753
SH		 3558#ifdef CONFIG_SKY2_DEBUG
3559
3560static struct dentry *sky2_debug;
3561
3562static int sky2_debug_show(struct seq_file *seq, void *v)
3563{
3564 struct net_device *dev = seq->private;
3565 const struct sky2_port *sky2 = netdev_priv(dev);
3566 const struct sky2_hw *hw = sky2->hw;
3567 unsigned port = sky2->port;
3568 unsigned idx, last;
3569 int sop;
3570
3571 if (!netif_running(dev))
3572 return -ENETDOWN;
3573
3574 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3575 sky2_read32(hw, B0_ISRC),
3576 sky2_read32(hw, B0_IMSK),
3577 sky2_read32(hw, B0_Y2_SP_ICR));
3578
3579 netif_poll_disable(hw->dev[0]);
3580 last = sky2_read16(hw, STAT_PUT_IDX);
3581
3582 if (hw->st_idx == last)
3583 seq_puts(seq, "Status ring (empty)\n");
3584 else {
3585 seq_puts(seq, "Status ring\n");
3586 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3587 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3588 const struct sky2_status_le *le = hw->st_le + idx;
3589 seq_printf(seq, "[%d] %#x %d %#x\n",
3590 idx, le->opcode, le->length, le->status);
3591 }
3592 seq_puts(seq, "\n");
3593 }
3594
3595 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3596 sky2->tx_cons, sky2->tx_prod,
3597 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3598 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3599
3600 /* Dump contents of tx ring */
3601 sop = 1;
3602 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3603 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3604 const struct sky2_tx_le *le = sky2->tx_le + idx;
3605 u32 a = le32_to_cpu(le->addr);
3606
3607 if (sop)
3608 seq_printf(seq, "%u:", idx);
3609 sop = 0;
3610
3611 switch(le->opcode & ~HW_OWNER) {
3612 case OP_ADDR64:
3613 seq_printf(seq, " %#x:", a);
3614 break;
3615 case OP_LRGLEN:
3616 seq_printf(seq, " mtu=%d", a);
3617 break;
3618 case OP_VLAN:
3619 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3620 break;
3621 case OP_TCPLISW:
3622 seq_printf(seq, " csum=%#x", a);
3623 break;
3624 case OP_LARGESEND:
3625 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3626 break;
3627 case OP_PACKET:
3628 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3629 break;
3630 case OP_BUFFER:
3631 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3632 break;
3633 default:
3634 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3635 a, le16_to_cpu(le->length));
3636 }
3637
3638 if (le->ctrl & EOP) {
3639 seq_putc(seq, '\n');
3640 sop = 1;
3641 }
3642 }
3643
3644 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3645 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3646 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3647 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3648
3649 netif_poll_enable(hw->dev[0]);
3650 return 0;
3651}
3652
3653static int sky2_debug_open(struct inode *inode, struct file *file)
3654{
3655 return single_open(file, sky2_debug_show, inode->i_private);
3656}
3657
3658static const struct file_operations sky2_debug_fops = {
3659 .owner = THIS_MODULE,
3660 .open = sky2_debug_open,
3661 .read = seq_read,
3662 .llseek = seq_lseek,
3663 .release = single_release,
3664};
3665
3666/*
3667 * Use network device events to create/remove/rename
3668 * debugfs file entries
3669 */
3670static int sky2_device_event(struct notifier_block *unused,
3671 unsigned long event, void *ptr)
3672{
3673 struct net_device *dev = ptr;
3674
3675 if (dev->open == sky2_up) {
3676 struct sky2_port *sky2 = netdev_priv(dev);
3677
3678 switch(event) {
3679 case NETDEV_CHANGENAME:
3680 if (!netif_running(dev))
3681 break;
3682 /* fallthrough */
3683 case NETDEV_DOWN:
3684 case NETDEV_GOING_DOWN:
3685 if (sky2->debugfs) {
3686 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3687 dev->name);
3688 debugfs_remove(sky2->debugfs);
3689 sky2->debugfs = NULL;
3690 }
3691
3692 if (event != NETDEV_CHANGENAME)
3693 break;
3694 /* fallthrough for changename */
3695 case NETDEV_UP:
3696 if (sky2_debug) {
3697 struct dentry *d;
3698 d = debugfs_create_file(dev->name, S_IRUGO,
3699 sky2_debug, dev,
3700 &sky2_debug_fops);
3701 if (d == NULL || IS_ERR(d))
3702 printk(KERN_INFO PFX
3703 "%s: debugfs create failed\n",
3704 dev->name);
3705 else
3706 sky2->debugfs = d;
3707 }
3708 break;
3709 }
3710 }
3711
3712 return NOTIFY_DONE;
3713}
3714
3715static struct notifier_block sky2_notifier = {
3716 .notifier_call = sky2_device_event,
3717};
3718
3719
3720static __init void sky2_debug_init(void)
3721{
3722 struct dentry *ent;
3723
3724 ent = debugfs_create_dir("sky2", NULL);
3725 if (!ent || IS_ERR(ent))
3726 return;
3727
3728 sky2_debug = ent;
3729 register_netdevice_notifier(&sky2_notifier);
3730}
3731
3732static __exit void sky2_debug_cleanup(void)
3733{
3734 if (sky2_debug) {
3735 unregister_netdevice_notifier(&sky2_notifier);
3736 debugfs_remove(sky2_debug);
3737 sky2_debug = NULL;
3738 }
3739}
3740
3741#else
3742#define sky2_debug_init()
3743#define sky2_debug_cleanup()
3744#endif
3745
3746
cd28ab6a
SH		 3747/* Initialize network device */
3748static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3749 unsigned port,
3750 int highmem, int wol)
cd28ab6a
SH		 3751{
3752 struct sky2_port *sky2;
3753 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3754
3755 if (!dev) {
b02a9258 3756 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3757 return NULL;
3758 }
3759
3760 SET_MODULE_OWNER(dev);
3761 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3762 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3763 dev->open = sky2_up;
3764 dev->stop = sky2_down;
ef743d33 3765 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3766 dev->hard_start_xmit = sky2_xmit_frame;
3767 dev->get_stats = sky2_get_stats;
3768 dev->set_multicast_list = sky2_set_multicast;
3769 dev->set_mac_address = sky2_set_mac_address;
3770 dev->change_mtu = sky2_change_mtu;
3771 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3772 dev->tx_timeout = sky2_tx_timeout;
3773 dev->watchdog_timeo = TX_WATCHDOG;
3774 if (port == 0)
3775 dev->poll = sky2_poll;
3776 dev->weight = NAPI_WEIGHT;
3777#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3778 /* Network console (only works on port 0)
3779 * because netpoll makes assumptions about NAPI
3780 */
3781 if (port == 0)
3782 dev->poll_controller = sky2_netpoll;
cd28ab6a 3783#endif
cd28ab6a
SH		 3784
3785 sky2 = netdev_priv(dev);
3786 sky2->netdev = dev;
3787 sky2->hw = hw;
3788 sky2->msg_enable = netif_msg_init(debug, default_msg);
3789
cd28ab6a
SH		 3790 /* Auto speed and flow control */
3791 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3792 sky2->flow_mode = FC_BOTH;
3793
cd28ab6a
SH		 3794 sky2->duplex = -1;
3795 sky2->speed = -1;
3796 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3797 sky2->rx_csum = 1;
e3173832 3798 sky2->wol = wol;
75d070c5 3799
e07b1aa8 3800 spin_lock_init(&sky2->phy_lock);
793b883e 3801 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3802 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3803
3804 hw->dev[port] = dev;
3805
3806 sky2->port = port;
3807
4a50a876 3808 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3809 if (highmem)
3810 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3811
d1f13708 3812#ifdef SKY2_VLAN_TAG_USED
3813 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3814 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708 3815#endif
3816
cd28ab6a 3817 /* read the mac address */
793b883e 3818 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3819 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3820
cd28ab6a
SH		 3821 return dev;
3822}
3823
28bd181a 3824static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3825{
3826 const struct sky2_port *sky2 = netdev_priv(dev);
3827
3828 if (netif_msg_probe(sky2))
3829 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3830 dev->name,
3831 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3832 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3833}
3834
fb2690a9 3835/* Handle software interrupt used during MSI test */
7d12e780 3836static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3837{
3838 struct sky2_hw *hw = dev_id;
3839 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3840
3841 if (status == 0)
3842 return IRQ_NONE;
3843
3844 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3845 hw->msi = 1;
fb2690a9
SH		 3846 wake_up(&hw->msi_wait);
3847 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3848 }
3849 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3850
3851 return IRQ_HANDLED;
3852}
3853
3854/* Test interrupt path by forcing a a software IRQ */
3855static int __devinit sky2_test_msi(struct sky2_hw *hw)
3856{
3857 struct pci_dev *pdev = hw->pdev;
3858 int err;
3859
bb507fe1 3860 init_waitqueue_head (&hw->msi_wait);
3861
fb2690a9
SH		 3862 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3863
b0a20ded 3864 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3865 if (err) {
b02a9258 3866 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3867 return err;
3868 }
3869
fb2690a9 3870 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3871 sky2_read8(hw, B0_CTST);
fb2690a9 3872
b0a20ded 3873 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3874
b0a20ded 3875 if (!hw->msi) {
fb2690a9 3876 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3877 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3878 "switching to INTx mode.\n");
fb2690a9
SH		 3879
3880 err = -EOPNOTSUPP;
3881 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3882 }
3883
3884 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3885 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3886
3887 free_irq(pdev->irq, hw);
3888
3889 return err;
3890}
3891
e3173832
SH		 3892static int __devinit pci_wake_enabled(struct pci_dev *dev)
3893{
3894 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3895 u16 value;
3896
3897 if (!pm)
3898 return 0;
3899 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3900 return 0;
3901 return value & PCI_PM_CTRL_PME_ENABLE;
3902}
3903
cd28ab6a
SH		 3904static int __devinit sky2_probe(struct pci_dev *pdev,
3905 const struct pci_device_id *ent)
3906{
7f60c64b 3907 struct net_device *dev;
cd28ab6a 3908 struct sky2_hw *hw;
e3173832 3909 int err, using_dac = 0, wol_default;
cd28ab6a 3910
793b883e
SH		 3911 err = pci_enable_device(pdev);
3912 if (err) {
b02a9258 3913 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3914 goto err_out;
3915 }
3916
793b883e
SH		 3917 err = pci_request_regions(pdev, DRV_NAME);
3918 if (err) {
b02a9258 3919 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3920 goto err_out_disable;
cd28ab6a
SH		 3921 }
3922
3923 pci_set_master(pdev);
3924
d1f3d4dd
SH		 3925 if (sizeof(dma_addr_t) > sizeof(u32) &&
3926 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3927 using_dac = 1;
3928 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3929 if (err < 0) {
b02a9258
SH		 3930 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3931 "for consistent allocations\n");
d1f3d4dd
SH		 3932 goto err_out_free_regions;
3933 }
d1f3d4dd 3934 } else {
cd28ab6a
SH		 3935 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3936 if (err) {
b02a9258 3937 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3938 goto err_out_free_regions;
3939 }
3940 }
d1f3d4dd 3941
e3173832
SH		 3942 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3943
cd28ab6a 3944 err = -ENOMEM;
6aad85d6 3945 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3946 if (!hw) {
b02a9258 3947 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3948 goto err_out_free_regions;
3949 }
3950
cd28ab6a 3951 hw->pdev = pdev;
cd28ab6a
SH		 3952
3953 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3954 if (!hw->regs) {
b02a9258 3955 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3956 goto err_out_free_hw;
3957 }
3958
56a645cc 3959#ifdef __BIG_ENDIAN
f65b138c
SH		 3960 /* The sk98lin vendor driver uses hardware byte swapping but
3961 * this driver uses software swapping.
3962 */
56a645cc
SH		 3963 {
3964 u32 reg;
56a645cc 3965 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3966 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3967 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3968 }
3969#endif
3970
08c06d8a
SH		 3971 /* ring for status responses */
3972 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3973 &hw->st_dma);
3974 if (!hw->st_le)
3975 goto err_out_iounmap;
3976
e3173832 3977 err = sky2_init(hw);
cd28ab6a 3978 if (err)
793b883e 3979 goto err_out_iounmap;
cd28ab6a 3980
b02a9258 3981 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3982 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3983 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3984 hw->chip_id, hw->chip_rev);
cd28ab6a 3985
e3173832
SH		 3986 sky2_reset(hw);
3987
3988 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3989 if (!dev) {
3990 err = -ENOMEM;
cd28ab6a 3991 goto err_out_free_pci;
7f60c64b 3992 }
cd28ab6a 3993
9fa1b1f3
SH		 3994 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3995 err = sky2_test_msi(hw);
3996 if (err == -EOPNOTSUPP)
3997 pci_disable_msi(pdev);
3998 else if (err)
3999 goto err_out_free_netdev;
4000 }
4001
793b883e
SH		 4002 err = register_netdev(dev);
4003 if (err) {
b02a9258 4004 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4005 goto err_out_free_netdev;
4006 }
4007
b0a20ded
SH		 4008 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
4009 dev->name, hw);
9fa1b1f3 4010 if (err) {
b02a9258 4011 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4012 goto err_out_unregister;
4013 }
4014 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4015
cd28ab6a
SH		 4016 sky2_show_addr(dev);
4017
7f60c64b 4018 if (hw->ports > 1) {
4019 struct net_device *dev1;
4020
e3173832 4021 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4022 if (!dev1)
4023 dev_warn(&pdev->dev, "allocation for second device failed\n");
4024 else if ((err = register_netdev(dev1))) {
4025 dev_warn(&pdev->dev,
4026 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4027 hw->dev[1] = NULL;
4028 free_netdev(dev1);
b02a9258
SH		 4029 } else
4030 sky2_show_addr(dev1);
cd28ab6a
SH		 4031 }
4032
01bd7564 4033 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 4034 INIT_WORK(&hw->restart_work, sky2_restart);
4035
eb35cf60 4036 sky2_idle_start(hw);
d27ed387 4037
793b883e
SH		 4038 pci_set_drvdata(pdev, hw);
4039
cd28ab6a
SH		 4040 return 0;
4041
793b883e 4042err_out_unregister:
b0a20ded
SH		 4043 if (hw->msi)
4044 pci_disable_msi(pdev);
793b883e 4045 unregister_netdev(dev);
cd28ab6a
SH		 4046err_out_free_netdev:
4047 free_netdev(dev);
cd28ab6a 4048err_out_free_pci:
793b883e 4049 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4050 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4051err_out_iounmap:
4052 iounmap(hw->regs);
4053err_out_free_hw:
4054 kfree(hw);
4055err_out_free_regions:
4056 pci_release_regions(pdev);
44a1d2e5 4057err_out_disable:
cd28ab6a 4058 pci_disable_device(pdev);
cd28ab6a 4059err_out:
549a68c3 4060 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4061 return err;
4062}
4063
4064static void __devexit sky2_remove(struct pci_dev *pdev)
4065{
793b883e 4066 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 4067 struct net_device *dev0, *dev1;
4068
793b883e 4069 if (!hw)
cd28ab6a
SH		 4070 return;
4071
d27ed387
SH		 4072 del_timer_sync(&hw->idle_timer);
4073
81906791
SH		 4074 flush_scheduled_work();
4075
d27ed387 4076 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 4077 synchronize_irq(hw->pdev->irq);
4078
cd28ab6a 4079 dev0 = hw->dev[0];
793b883e
SH		 4080 dev1 = hw->dev[1];
4081 if (dev1)
4082 unregister_netdev(dev1);
cd28ab6a
SH		 4083 unregister_netdev(dev0);
4084
ae306cca
SH		 4085 sky2_power_aux(hw);
4086
cd28ab6a 4087 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4088 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4089 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4090
4091 free_irq(pdev->irq, hw);
b0a20ded
SH		 4092 if (hw->msi)
4093 pci_disable_msi(pdev);
793b883e 4094 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4095 pci_release_regions(pdev);
4096 pci_disable_device(pdev);
793b883e 4097
cd28ab6a
SH		 4098 if (dev1)
4099 free_netdev(dev1);
4100 free_netdev(dev0);
4101 iounmap(hw->regs);
4102 kfree(hw);
5afa0a9c 4103
cd28ab6a
SH		 4104 pci_set_drvdata(pdev, NULL);
4105}
4106
4107#ifdef CONFIG_PM
4108static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4109{
793b883e 4110 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4111 int i, wol = 0;
cd28ab6a 4112
549a68c3
SH		 4113 if (!hw)
4114 return 0;
4115
eb35cf60 4116 del_timer_sync(&hw->idle_timer);
6a5706b9 4117 netif_poll_disable(hw->dev[0]);
eb35cf60 4118
f05267e7 4119 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4120 struct net_device *dev = hw->dev[i];
e3173832 4121 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4122
e3173832 4123 if (netif_running(dev))
5afa0a9c 4124 sky2_down(dev);
e3173832
SH		 4125
4126 if (sky2->wol)
4127 sky2_wol_init(sky2);
4128
4129 wol |= sky2->wol;
cd28ab6a
SH		 4130 }
4131
8ab8fca2 4132 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4133 sky2_power_aux(hw);
e3173832 4134
d374c1c1 4135 pci_save_state(pdev);
e3173832 4136 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4137 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4138
2ccc99b7 4139 return 0;
cd28ab6a
SH		 4140}
4141
4142static int sky2_resume(struct pci_dev *pdev)
4143{
793b883e 4144 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4145 int i, err;
cd28ab6a 4146
549a68c3
SH		 4147 if (!hw)
4148 return 0;
4149
ae306cca
SH		 4150 err = pci_set_power_state(pdev, PCI_D0);
4151 if (err)
4152 goto out;
4153
4154 err = pci_restore_state(pdev);
4155 if (err)
4156 goto out;
4157
cd28ab6a 4158 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4159
4160 /* Re-enable all clocks */
4161 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4162 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4163
e3173832 4164 sky2_reset(hw);
cd28ab6a 4165
8ab8fca2
SH		 4166 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4167
f05267e7 4168 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4169 struct net_device *dev = hw->dev[i];
6a5706b9 4170 if (netif_running(dev)) {
08c06d8a
SH		 4171 err = sky2_up(dev);
4172 if (err) {
4173 printk(KERN_ERR PFX "%s: could not up: %d\n",
4174 dev->name, err);
4175 dev_close(dev);
eb35cf60 4176 goto out;
5afa0a9c 4177 }
cd28ab6a
SH		 4178 }
4179 }
eb35cf60 4180
6a5706b9 4181 netif_poll_enable(hw->dev[0]);
eb35cf60 4182 sky2_idle_start(hw);
ae306cca 4183 return 0;
08c06d8a 4184out:
b02a9258 4185 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4186 pci_disable_device(pdev);
08c06d8a 4187 return err;
cd28ab6a
SH		 4188}
4189#endif
4190
e3173832
SH		 4191static void sky2_shutdown(struct pci_dev *pdev)
4192{
4193 struct sky2_hw *hw = pci_get_drvdata(pdev);
4194 int i, wol = 0;
4195
549a68c3
SH		 4196 if (!hw)
4197 return;
4198
e3173832
SH		 4199 del_timer_sync(&hw->idle_timer);
4200 netif_poll_disable(hw->dev[0]);
4201
4202 for (i = 0; i < hw->ports; i++) {
4203 struct net_device *dev = hw->dev[i];
4204 struct sky2_port *sky2 = netdev_priv(dev);
4205
4206 if (sky2->wol) {
4207 wol = 1;
4208 sky2_wol_init(sky2);
4209 }
4210 }
4211
4212 if (wol)
4213 sky2_power_aux(hw);
4214
4215 pci_enable_wake(pdev, PCI_D3hot, wol);
4216 pci_enable_wake(pdev, PCI_D3cold, wol);
4217
4218 pci_disable_device(pdev);
4219 pci_set_power_state(pdev, PCI_D3hot);
4220
4221}
4222
cd28ab6a 4223static struct pci_driver sky2_driver = {
793b883e
SH		 4224 .name = DRV_NAME,
4225 .id_table = sky2_id_table,
4226 .probe = sky2_probe,
4227 .remove = __devexit_p(sky2_remove),
cd28ab6a 4228#ifdef CONFIG_PM
793b883e
SH		 4229 .suspend = sky2_suspend,
4230 .resume = sky2_resume,
cd28ab6a 4231#endif
e3173832 4232 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4233};
4234
4235static int __init sky2_init_module(void)
4236{
3cf26753 4237 sky2_debug_init();
50241c4c 4238 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4239}
4240
4241static void __exit sky2_cleanup_module(void)
4242{
4243 pci_unregister_driver(&sky2_driver);
3cf26753 4244 sky2_debug_cleanup();
cd28ab6a
SH		 4245}
4246
4247module_init(sky2_init_module);
4248module_exit(sky2_cleanup_module);
4249
4250MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4251MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4252MODULE_LICENSE("GPL");
5f4f9dc1 4253MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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