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1da177e4 LT |
1 | /*------------------------------------------------------------------------ |
2 | . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. | |
3 | . | |
4 | . Copyright (C) 1996 by Erik Stahlman | |
5 | . Copyright (C) 2001 Standard Microsystems Corporation | |
6 | . Developed by Simple Network Magic Corporation | |
7 | . Copyright (C) 2003 Monta Vista Software, Inc. | |
8 | . Unified SMC91x driver by Nicolas Pitre | |
9 | . | |
10 | . This program is free software; you can redistribute it and/or modify | |
11 | . it under the terms of the GNU General Public License as published by | |
12 | . the Free Software Foundation; either version 2 of the License, or | |
13 | . (at your option) any later version. | |
14 | . | |
15 | . This program is distributed in the hope that it will be useful, | |
16 | . but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | . GNU General Public License for more details. | |
19 | . | |
20 | . You should have received a copy of the GNU General Public License | |
21 | . along with this program; if not, write to the Free Software | |
22 | . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | . | |
24 | . Information contained in this file was obtained from the LAN91C111 | |
25 | . manual from SMC. To get a copy, if you really want one, you can find | |
26 | . information under www.smsc.com. | |
27 | . | |
28 | . Authors | |
29 | . Erik Stahlman <erik@vt.edu> | |
30 | . Daris A Nevil <dnevil@snmc.com> | |
2f82af08 | 31 | . Nicolas Pitre <nico@fluxnic.net> |
1da177e4 LT |
32 | . |
33 | ---------------------------------------------------------------------------*/ | |
34 | #ifndef _SMC91X_H_ | |
35 | #define _SMC91X_H_ | |
36 | ||
3e947943 | 37 | #include <linux/smc91x.h> |
1da177e4 LT |
38 | |
39 | /* | |
40 | * Define your architecture specific bus configuration parameters here. | |
41 | */ | |
42 | ||
38fd6c38 | 43 | #if defined(CONFIG_ARCH_LUBBOCK) ||\ |
88c36eb7 | 44 | defined(CONFIG_MACH_MAINSTONE) ||\ |
e1719da6 | 45 | defined(CONFIG_MACH_ZYLONITE) ||\ |
175ff20f | 46 | defined(CONFIG_MACH_LITTLETON) ||\ |
a6b993c6 | 47 | defined(CONFIG_MACH_ZYLONITE2) ||\ |
80153d1b JC |
48 | defined(CONFIG_ARCH_VIPER) ||\ |
49 | defined(CONFIG_MACH_STARGATE2) | |
1da177e4 | 50 | |
38fd6c38 EM |
51 | #include <asm/mach-types.h> |
52 | ||
53 | /* Now the bus width is specified in the platform data | |
54 | * pretend here to support all I/O access types | |
55 | */ | |
56 | #define SMC_CAN_USE_8BIT 1 | |
1da177e4 | 57 | #define SMC_CAN_USE_16BIT 1 |
38fd6c38 | 58 | #define SMC_CAN_USE_32BIT 1 |
1da177e4 LT |
59 | #define SMC_NOWAIT 1 |
60 | ||
3aed74cd | 61 | #define SMC_IO_SHIFT (lp->io_shift) |
1da177e4 | 62 | |
38fd6c38 | 63 | #define SMC_inb(a, r) readb((a) + (r)) |
1da177e4 | 64 | #define SMC_inw(a, r) readw((a) + (r)) |
38fd6c38 EM |
65 | #define SMC_inl(a, r) readl((a) + (r)) |
66 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
67 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
1da177e4 LT |
68 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
69 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
38fd6c38 EM |
70 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
71 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 72 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 | 73 | |
38fd6c38 EM |
74 | /* We actually can't write halfwords properly if not word aligned */ |
75 | static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg) | |
76 | { | |
80153d1b | 77 | if ((machine_is_mainstone() || machine_is_stargate2()) && reg & 2) { |
38fd6c38 EM |
78 | unsigned int v = val << 16; |
79 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
80 | writel(v, ioaddr + (reg & ~2)); | |
81 | } else { | |
82 | writew(val, ioaddr + reg); | |
83 | } | |
84 | } | |
85 | ||
1da177e4 LT |
86 | #elif defined(CONFIG_SA1100_PLEB) |
87 | /* We can only do 16-bit reads and writes in the static memory space. */ | |
88 | #define SMC_CAN_USE_8BIT 1 | |
89 | #define SMC_CAN_USE_16BIT 1 | |
90 | #define SMC_CAN_USE_32BIT 0 | |
91 | #define SMC_IO_SHIFT 0 | |
92 | #define SMC_NOWAIT 1 | |
93 | ||
1cf99be5 RK |
94 | #define SMC_inb(a, r) readb((a) + (r)) |
95 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
96 | #define SMC_inw(a, r) readw((a) + (r)) | |
97 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
98 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
99 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
100 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
101 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 | 102 | |
e7b3dc7e | 103 | #define SMC_IRQ_FLAGS (-1) |
1da177e4 LT |
104 | |
105 | #elif defined(CONFIG_SA1100_ASSABET) | |
106 | ||
a09e64fb | 107 | #include <mach/neponset.h> |
1da177e4 LT |
108 | |
109 | /* We can only do 8-bit reads and writes in the static memory space. */ | |
110 | #define SMC_CAN_USE_8BIT 1 | |
111 | #define SMC_CAN_USE_16BIT 0 | |
112 | #define SMC_CAN_USE_32BIT 0 | |
113 | #define SMC_NOWAIT 1 | |
114 | ||
115 | /* The first two address lines aren't connected... */ | |
116 | #define SMC_IO_SHIFT 2 | |
117 | ||
118 | #define SMC_inb(a, r) readb((a) + (r)) | |
119 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
120 | #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) | |
121 | #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) | |
e7b3dc7e | 122 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 | 123 | |
8e95a202 JP |
124 | #elif defined(CONFIG_MACH_LOGICPD_PXA270) || \ |
125 | defined(CONFIG_MACH_NOMADIK_8815NHK) | |
b0348b90 LB |
126 | |
127 | #define SMC_CAN_USE_8BIT 0 | |
128 | #define SMC_CAN_USE_16BIT 1 | |
129 | #define SMC_CAN_USE_32BIT 0 | |
130 | #define SMC_IO_SHIFT 0 | |
131 | #define SMC_NOWAIT 1 | |
b0348b90 | 132 | |
b0348b90 | 133 | #define SMC_inw(a, r) readw((a) + (r)) |
b0348b90 | 134 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) |
b0348b90 LB |
135 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
136 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
137 | ||
1da177e4 | 138 | #elif defined(CONFIG_ARCH_INNOKOM) || \ |
1da177e4 | 139 | defined(CONFIG_ARCH_PXA_IDP) || \ |
4f15a980 RS |
140 | defined(CONFIG_ARCH_RAMSES) || \ |
141 | defined(CONFIG_ARCH_PCM027) | |
1da177e4 LT |
142 | |
143 | #define SMC_CAN_USE_8BIT 1 | |
144 | #define SMC_CAN_USE_16BIT 1 | |
145 | #define SMC_CAN_USE_32BIT 1 | |
146 | #define SMC_IO_SHIFT 0 | |
147 | #define SMC_NOWAIT 1 | |
148 | #define SMC_USE_PXA_DMA 1 | |
149 | ||
150 | #define SMC_inb(a, r) readb((a) + (r)) | |
151 | #define SMC_inw(a, r) readw((a) + (r)) | |
152 | #define SMC_inl(a, r) readl((a) + (r)) | |
153 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
154 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
155 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
156 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 157 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
1da177e4 LT |
158 | |
159 | /* We actually can't write halfwords properly if not word aligned */ | |
160 | static inline void | |
eb1d6988 | 161 | SMC_outw(u16 val, void __iomem *ioaddr, int reg) |
1da177e4 LT |
162 | { |
163 | if (reg & 2) { | |
164 | unsigned int v = val << 16; | |
165 | v |= readl(ioaddr + (reg & ~2)) & 0xffff; | |
166 | writel(v, ioaddr + (reg & ~2)); | |
167 | } else { | |
168 | writew(val, ioaddr + reg); | |
169 | } | |
170 | } | |
171 | ||
1da177e4 LT |
172 | #elif defined(CONFIG_SH_SH4202_MICRODEV) |
173 | ||
174 | #define SMC_CAN_USE_8BIT 0 | |
175 | #define SMC_CAN_USE_16BIT 1 | |
176 | #define SMC_CAN_USE_32BIT 0 | |
177 | ||
178 | #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) | |
179 | #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) | |
180 | #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) | |
181 | #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) | |
182 | #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) | |
183 | #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) | |
184 | #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) | |
185 | #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) | |
186 | #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) | |
187 | #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) | |
188 | ||
9ded96f2 | 189 | #define SMC_IRQ_FLAGS (0) |
1da177e4 | 190 | |
1da177e4 LT |
191 | #elif defined(CONFIG_M32R) |
192 | ||
193 | #define SMC_CAN_USE_8BIT 0 | |
194 | #define SMC_CAN_USE_16BIT 1 | |
195 | #define SMC_CAN_USE_32BIT 0 | |
196 | ||
59dc76a4 | 197 | #define SMC_inb(a, r) inb(((u32)a) + (r)) |
f3ac9fbf HT |
198 | #define SMC_inw(a, r) inw(((u32)a) + (r)) |
199 | #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) | |
200 | #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) | |
201 | #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) | |
202 | #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) | |
1da177e4 | 203 | |
9ded96f2 | 204 | #define SMC_IRQ_FLAGS (0) |
1da177e4 LT |
205 | |
206 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
207 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
208 | ||
8e95a202 JP |
209 | #elif defined(CONFIG_MACH_LPD79520) || \ |
210 | defined(CONFIG_MACH_LPD7A400) || \ | |
211 | defined(CONFIG_MACH_LPD7A404) | |
1da177e4 | 212 | |
d4adcffb MS |
213 | /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the |
214 | * way that the CPU handles chip selects and the way that the SMC chip | |
215 | * expects the chip select to operate. Refer to | |
1da177e4 | 216 | * Documentation/arm/Sharp-LH/IOBarrier for details. The read from |
d4adcffb MS |
217 | * IOBARRIER is a byte, in order that we read the least-common |
218 | * denominator. It would be wasteful to read 32 bits from an 8-bit | |
219 | * accessible region. | |
1da177e4 LT |
220 | * |
221 | * There is no explicit protection against interrupts intervening | |
222 | * between the writew and the IOBARRIER. In SMC ISR there is a | |
223 | * preamble that performs an IOBARRIER in the extremely unlikely event | |
224 | * that the driver interrupts itself between a writew to the chip an | |
225 | * the IOBARRIER that follows *and* the cache is large enough that the | |
226 | * first off-chip access while handing the interrupt is to the SMC | |
227 | * chip. Other devices in the same address space as the SMC chip must | |
228 | * be aware of the potential for trouble and perform a similar | |
229 | * IOBARRIER on entry to their ISR. | |
230 | */ | |
231 | ||
a09e64fb | 232 | #include <mach/constants.h> /* IOBARRIER_VIRT */ |
1da177e4 LT |
233 | |
234 | #define SMC_CAN_USE_8BIT 0 | |
235 | #define SMC_CAN_USE_16BIT 1 | |
236 | #define SMC_CAN_USE_32BIT 0 | |
237 | #define SMC_NOWAIT 0 | |
d4adcffb | 238 | #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT) |
1da177e4 | 239 | |
d4adcffb MS |
240 | #define SMC_inw(a,r)\ |
241 | ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; }) | |
242 | #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; }) | |
1da177e4 | 243 | |
d4adcffb MS |
244 | #define SMC_insw LPD7_SMC_insw |
245 | static inline void LPD7_SMC_insw (unsigned char* a, int r, | |
246 | unsigned char* p, int l) | |
247 | { | |
248 | unsigned short* ps = (unsigned short*) p; | |
249 | while (l-- > 0) { | |
250 | *ps++ = readw (a + r); | |
251 | LPD7X_IOBARRIER; | |
252 | } | |
253 | } | |
09779c6d | 254 | |
d4adcffb MS |
255 | #define SMC_outsw LPD7_SMC_outsw |
256 | static inline void LPD7_SMC_outsw (unsigned char* a, int r, | |
257 | unsigned char* p, int l) | |
1da177e4 LT |
258 | { |
259 | unsigned short* ps = (unsigned short*) p; | |
260 | while (l-- > 0) { | |
261 | writew (*ps++, a + r); | |
d4adcffb | 262 | LPD7X_IOBARRIER; |
1da177e4 LT |
263 | } |
264 | } | |
265 | ||
d4adcffb | 266 | #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER |
1da177e4 LT |
267 | |
268 | #define RPC_LSA_DEFAULT RPC_LED_TX_RX | |
269 | #define RPC_LSB_DEFAULT RPC_LED_100_10 | |
270 | ||
33fee56a DS |
271 | #elif defined(CONFIG_ARCH_VERSATILE) |
272 | ||
273 | #define SMC_CAN_USE_8BIT 1 | |
274 | #define SMC_CAN_USE_16BIT 1 | |
275 | #define SMC_CAN_USE_32BIT 1 | |
276 | #define SMC_NOWAIT 1 | |
277 | ||
278 | #define SMC_inb(a, r) readb((a) + (r)) | |
279 | #define SMC_inw(a, r) readw((a) + (r)) | |
280 | #define SMC_inl(a, r) readl((a) + (r)) | |
281 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
282 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
283 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
284 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) | |
285 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
e7b3dc7e | 286 | #define SMC_IRQ_FLAGS (-1) /* from resource */ |
55793455 | 287 | |
b920de1b DH |
288 | #elif defined(CONFIG_MN10300) |
289 | ||
290 | /* | |
291 | * MN10300/AM33 configuration | |
292 | */ | |
293 | ||
2f2a2132 | 294 | #include <unit/smc91111.h> |
b920de1b | 295 | |
4b79a1ae DB |
296 | #elif defined(CONFIG_ARCH_MSM) |
297 | ||
298 | #define SMC_CAN_USE_8BIT 0 | |
299 | #define SMC_CAN_USE_16BIT 1 | |
300 | #define SMC_CAN_USE_32BIT 0 | |
301 | #define SMC_NOWAIT 1 | |
302 | ||
303 | #define SMC_inw(a, r) readw((a) + (r)) | |
304 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
305 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) | |
306 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
307 | ||
308 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH | |
309 | ||
717ea4b3 GU |
310 | #elif defined(CONFIG_COLDFIRE) |
311 | ||
312 | #define SMC_CAN_USE_8BIT 0 | |
313 | #define SMC_CAN_USE_16BIT 1 | |
314 | #define SMC_CAN_USE_32BIT 0 | |
315 | #define SMC_NOWAIT 1 | |
316 | ||
317 | static inline void mcf_insw(void *a, unsigned char *p, int l) | |
318 | { | |
319 | u16 *wp = (u16 *) p; | |
320 | while (l-- > 0) | |
321 | *wp++ = readw(a); | |
322 | } | |
323 | ||
324 | static inline void mcf_outsw(void *a, unsigned char *p, int l) | |
325 | { | |
326 | u16 *wp = (u16 *) p; | |
327 | while (l-- > 0) | |
328 | writew(*wp++, a); | |
329 | } | |
330 | ||
331 | #define SMC_inw(a, r) _swapw(readw((a) + (r))) | |
332 | #define SMC_outw(v, a, r) writew(_swapw(v), (a) + (r)) | |
333 | #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) | |
334 | #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l) | |
335 | ||
336 | #define SMC_IRQ_FLAGS (IRQF_DISABLED) | |
337 | ||
1da177e4 LT |
338 | #else |
339 | ||
b920de1b DH |
340 | /* |
341 | * Default configuration | |
342 | */ | |
343 | ||
1da177e4 LT |
344 | #define SMC_CAN_USE_8BIT 1 |
345 | #define SMC_CAN_USE_16BIT 1 | |
346 | #define SMC_CAN_USE_32BIT 1 | |
347 | #define SMC_NOWAIT 1 | |
348 | ||
d1c5ea33 MD |
349 | #define SMC_IO_SHIFT (lp->io_shift) |
350 | ||
1da177e4 LT |
351 | #define SMC_inb(a, r) readb((a) + (r)) |
352 | #define SMC_inw(a, r) readw((a) + (r)) | |
353 | #define SMC_inl(a, r) readl((a) + (r)) | |
354 | #define SMC_outb(v, a, r) writeb(v, (a) + (r)) | |
355 | #define SMC_outw(v, a, r) writew(v, (a) + (r)) | |
356 | #define SMC_outl(v, a, r) writel(v, (a) + (r)) | |
8a214c12 MD |
357 | #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) |
358 | #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) | |
1da177e4 LT |
359 | #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) |
360 | #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) | |
361 | ||
362 | #define RPC_LSA_DEFAULT RPC_LED_100_10 | |
363 | #define RPC_LSB_DEFAULT RPC_LED_TX_RX | |
364 | ||
365 | #endif | |
366 | ||
073ac8fd RK |
367 | |
368 | /* store this information for the driver.. */ | |
369 | struct smc_local { | |
370 | /* | |
371 | * If I have to wait until memory is available to send a | |
372 | * packet, I will store the skbuff here, until I get the | |
373 | * desired memory. Then, I'll send it out and free it. | |
374 | */ | |
375 | struct sk_buff *pending_tx_skb; | |
376 | struct tasklet_struct tx_task; | |
377 | ||
378 | /* version/revision of the SMC91x chip */ | |
379 | int version; | |
380 | ||
381 | /* Contains the current active transmission mode */ | |
382 | int tcr_cur_mode; | |
383 | ||
384 | /* Contains the current active receive mode */ | |
385 | int rcr_cur_mode; | |
386 | ||
387 | /* Contains the current active receive/phy mode */ | |
388 | int rpc_cur_mode; | |
389 | int ctl_rfduplx; | |
390 | int ctl_rspeed; | |
391 | ||
392 | u32 msg_enable; | |
393 | u32 phy_type; | |
394 | struct mii_if_info mii; | |
395 | ||
396 | /* work queue */ | |
397 | struct work_struct phy_configure; | |
398 | struct net_device *dev; | |
399 | int work_pending; | |
400 | ||
401 | spinlock_t lock; | |
402 | ||
52256c0e | 403 | #ifdef CONFIG_ARCH_PXA |
073ac8fd RK |
404 | /* DMA needs the physical address of the chip */ |
405 | u_long physaddr; | |
406 | struct device *device; | |
407 | #endif | |
408 | void __iomem *base; | |
409 | void __iomem *datacs; | |
3e947943 | 410 | |
15919886 EM |
411 | /* the low address lines on some platforms aren't connected... */ |
412 | int io_shift; | |
413 | ||
3e947943 | 414 | struct smc91x_platdata cfg; |
073ac8fd RK |
415 | }; |
416 | ||
fa6d3be0 EM |
417 | #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT) |
418 | #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT) | |
419 | #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT) | |
073ac8fd | 420 | |
52256c0e | 421 | #ifdef CONFIG_ARCH_PXA |
1da177e4 LT |
422 | /* |
423 | * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is | |
424 | * always happening in irq context so no need to worry about races. TX is | |
425 | * different and probably not worth it for that reason, and not as critical | |
426 | * as RX which can overrun memory and lose packets. | |
427 | */ | |
428 | #include <linux/dma-mapping.h> | |
dcea83ad | 429 | #include <mach/dma.h> |
1da177e4 LT |
430 | |
431 | #ifdef SMC_insl | |
432 | #undef SMC_insl | |
433 | #define SMC_insl(a, r, p, l) \ | |
073ac8fd | 434 | smc_pxa_dma_insl(a, lp, r, dev->dma, p, l) |
1da177e4 | 435 | static inline void |
073ac8fd | 436 | smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
437 | u_char *buf, int len) |
438 | { | |
073ac8fd | 439 | u_long physaddr = lp->physaddr; |
1da177e4 LT |
440 | dma_addr_t dmabuf; |
441 | ||
442 | /* fallback if no DMA available */ | |
443 | if (dma == (unsigned char)-1) { | |
444 | readsl(ioaddr + reg, buf, len); | |
445 | return; | |
446 | } | |
447 | ||
448 | /* 64 bit alignment is required for memory to memory DMA */ | |
449 | if ((long)buf & 4) { | |
450 | *((u32 *)buf) = SMC_inl(ioaddr, reg); | |
451 | buf += 4; | |
452 | len--; | |
453 | } | |
454 | ||
455 | len *= 4; | |
073ac8fd | 456 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
457 | DCSR(dma) = DCSR_NODESC; |
458 | DTADR(dma) = dmabuf; | |
459 | DSADR(dma) = physaddr + reg; | |
460 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
461 | DCMD_WIDTH4 | (DCMD_LENGTH & len)); | |
462 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
463 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
464 | cpu_relax(); | |
465 | DCSR(dma) = 0; | |
073ac8fd | 466 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
467 | } |
468 | #endif | |
469 | ||
470 | #ifdef SMC_insw | |
471 | #undef SMC_insw | |
472 | #define SMC_insw(a, r, p, l) \ | |
073ac8fd | 473 | smc_pxa_dma_insw(a, lp, r, dev->dma, p, l) |
1da177e4 | 474 | static inline void |
073ac8fd | 475 | smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, |
1da177e4 LT |
476 | u_char *buf, int len) |
477 | { | |
073ac8fd | 478 | u_long physaddr = lp->physaddr; |
1da177e4 LT |
479 | dma_addr_t dmabuf; |
480 | ||
481 | /* fallback if no DMA available */ | |
482 | if (dma == (unsigned char)-1) { | |
483 | readsw(ioaddr + reg, buf, len); | |
484 | return; | |
485 | } | |
486 | ||
487 | /* 64 bit alignment is required for memory to memory DMA */ | |
488 | while ((long)buf & 6) { | |
489 | *((u16 *)buf) = SMC_inw(ioaddr, reg); | |
490 | buf += 2; | |
491 | len--; | |
492 | } | |
493 | ||
494 | len *= 2; | |
073ac8fd | 495 | dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
496 | DCSR(dma) = DCSR_NODESC; |
497 | DTADR(dma) = dmabuf; | |
498 | DSADR(dma) = physaddr + reg; | |
499 | DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | | |
500 | DCMD_WIDTH2 | (DCMD_LENGTH & len)); | |
501 | DCSR(dma) = DCSR_NODESC | DCSR_RUN; | |
502 | while (!(DCSR(dma) & DCSR_STOPSTATE)) | |
503 | cpu_relax(); | |
504 | DCSR(dma) = 0; | |
073ac8fd | 505 | dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); |
1da177e4 LT |
506 | } |
507 | #endif | |
508 | ||
509 | static void | |
7d12e780 | 510 | smc_pxa_dma_irq(int dma, void *dummy) |
1da177e4 LT |
511 | { |
512 | DCSR(dma) = 0; | |
513 | } | |
52256c0e | 514 | #endif /* CONFIG_ARCH_PXA */ |
1da177e4 LT |
515 | |
516 | ||
09779c6d NP |
517 | /* |
518 | * Everything a particular hardware setup needs should have been defined | |
519 | * at this point. Add stubs for the undefined cases, mainly to avoid | |
520 | * compilation warnings since they'll be optimized away, or to prevent buggy | |
521 | * use of them. | |
522 | */ | |
523 | ||
524 | #if ! SMC_CAN_USE_32BIT | |
525 | #define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) | |
526 | #define SMC_outl(x, ioaddr, reg) BUG() | |
527 | #define SMC_insl(a, r, p, l) BUG() | |
528 | #define SMC_outsl(a, r, p, l) BUG() | |
529 | #endif | |
530 | ||
531 | #if !defined(SMC_insl) || !defined(SMC_outsl) | |
532 | #define SMC_insl(a, r, p, l) BUG() | |
533 | #define SMC_outsl(a, r, p, l) BUG() | |
534 | #endif | |
535 | ||
536 | #if ! SMC_CAN_USE_16BIT | |
537 | ||
538 | /* | |
539 | * Any 16-bit access is performed with two 8-bit accesses if the hardware | |
540 | * can't do it directly. Most registers are 16-bit so those are mandatory. | |
541 | */ | |
542 | #define SMC_outw(x, ioaddr, reg) \ | |
543 | do { \ | |
544 | unsigned int __val16 = (x); \ | |
545 | SMC_outb( __val16, ioaddr, reg ); \ | |
546 | SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ | |
547 | } while (0) | |
548 | #define SMC_inw(ioaddr, reg) \ | |
549 | ({ \ | |
550 | unsigned int __val16; \ | |
551 | __val16 = SMC_inb( ioaddr, reg ); \ | |
552 | __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ | |
553 | __val16; \ | |
554 | }) | |
555 | ||
556 | #define SMC_insw(a, r, p, l) BUG() | |
557 | #define SMC_outsw(a, r, p, l) BUG() | |
558 | ||
559 | #endif | |
560 | ||
561 | #if !defined(SMC_insw) || !defined(SMC_outsw) | |
562 | #define SMC_insw(a, r, p, l) BUG() | |
563 | #define SMC_outsw(a, r, p, l) BUG() | |
564 | #endif | |
565 | ||
566 | #if ! SMC_CAN_USE_8BIT | |
567 | #define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) | |
568 | #define SMC_outb(x, ioaddr, reg) BUG() | |
569 | #define SMC_insb(a, r, p, l) BUG() | |
570 | #define SMC_outsb(a, r, p, l) BUG() | |
571 | #endif | |
572 | ||
573 | #if !defined(SMC_insb) || !defined(SMC_outsb) | |
574 | #define SMC_insb(a, r, p, l) BUG() | |
575 | #define SMC_outsb(a, r, p, l) BUG() | |
576 | #endif | |
577 | ||
578 | #ifndef SMC_CAN_USE_DATACS | |
579 | #define SMC_CAN_USE_DATACS 0 | |
580 | #endif | |
581 | ||
1da177e4 LT |
582 | #ifndef SMC_IO_SHIFT |
583 | #define SMC_IO_SHIFT 0 | |
584 | #endif | |
09779c6d NP |
585 | |
586 | #ifndef SMC_IRQ_FLAGS | |
1fb9df5d | 587 | #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING |
09779c6d NP |
588 | #endif |
589 | ||
590 | #ifndef SMC_INTERRUPT_PREAMBLE | |
591 | #define SMC_INTERRUPT_PREAMBLE | |
592 | #endif | |
593 | ||
594 | ||
595 | /* Because of bank switching, the LAN91x uses only 16 I/O ports */ | |
1da177e4 LT |
596 | #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) |
597 | #define SMC_DATA_EXTENT (4) | |
598 | ||
599 | /* | |
600 | . Bank Select Register: | |
601 | . | |
602 | . yyyy yyyy 0000 00xx | |
603 | . xx = bank number | |
604 | . yyyy yyyy = 0x33, for identification purposes. | |
605 | */ | |
606 | #define BANK_SELECT (14 << SMC_IO_SHIFT) | |
607 | ||
608 | ||
609 | // Transmit Control Register | |
610 | /* BANK 0 */ | |
cfdfa865 | 611 | #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0) |
1da177e4 LT |
612 | #define TCR_ENABLE 0x0001 // When 1 we can transmit |
613 | #define TCR_LOOP 0x0002 // Controls output pin LBK | |
614 | #define TCR_FORCOL 0x0004 // When 1 will force a collision | |
615 | #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 | |
616 | #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames | |
617 | #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier | |
618 | #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation | |
619 | #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error | |
620 | #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback | |
621 | #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode | |
622 | ||
623 | #define TCR_CLEAR 0 /* do NOTHING */ | |
624 | /* the default settings for the TCR register : */ | |
625 | #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) | |
626 | ||
627 | ||
628 | // EPH Status Register | |
629 | /* BANK 0 */ | |
cfdfa865 | 630 | #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0) |
1da177e4 LT |
631 | #define ES_TX_SUC 0x0001 // Last TX was successful |
632 | #define ES_SNGL_COL 0x0002 // Single collision detected for last tx | |
633 | #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx | |
634 | #define ES_LTX_MULT 0x0008 // Last tx was a multicast | |
635 | #define ES_16COL 0x0010 // 16 Collisions Reached | |
636 | #define ES_SQET 0x0020 // Signal Quality Error Test | |
637 | #define ES_LTXBRD 0x0040 // Last tx was a broadcast | |
638 | #define ES_TXDEFR 0x0080 // Transmit Deferred | |
639 | #define ES_LATCOL 0x0200 // Late collision detected on last tx | |
640 | #define ES_LOSTCARR 0x0400 // Lost Carrier Sense | |
641 | #define ES_EXC_DEF 0x0800 // Excessive Deferral | |
642 | #define ES_CTR_ROL 0x1000 // Counter Roll Over indication | |
643 | #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin | |
644 | #define ES_TXUNRN 0x8000 // Tx Underrun | |
645 | ||
646 | ||
647 | // Receive Control Register | |
648 | /* BANK 0 */ | |
cfdfa865 | 649 | #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0) |
1da177e4 LT |
650 | #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted |
651 | #define RCR_PRMS 0x0002 // Enable promiscuous mode | |
652 | #define RCR_ALMUL 0x0004 // When set accepts all multicast frames | |
653 | #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets | |
654 | #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets | |
655 | #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision | |
656 | #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier | |
657 | #define RCR_SOFTRST 0x8000 // resets the chip | |
658 | ||
659 | /* the normal settings for the RCR register : */ | |
660 | #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) | |
661 | #define RCR_CLEAR 0x0 // set it to a base state | |
662 | ||
663 | ||
664 | // Counter Register | |
665 | /* BANK 0 */ | |
cfdfa865 | 666 | #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0) |
1da177e4 LT |
667 | |
668 | ||
669 | // Memory Information Register | |
670 | /* BANK 0 */ | |
cfdfa865 | 671 | #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0) |
1da177e4 LT |
672 | |
673 | ||
674 | // Receive/Phy Control Register | |
675 | /* BANK 0 */ | |
cfdfa865 | 676 | #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0) |
1da177e4 LT |
677 | #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. |
678 | #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode | |
679 | #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode | |
680 | #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb | |
681 | #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb | |
1da177e4 LT |
682 | |
683 | #ifndef RPC_LSA_DEFAULT | |
684 | #define RPC_LSA_DEFAULT RPC_LED_100 | |
685 | #endif | |
686 | #ifndef RPC_LSB_DEFAULT | |
687 | #define RPC_LSB_DEFAULT RPC_LED_FD | |
688 | #endif | |
689 | ||
b0dbcf51 | 690 | #define RPC_DEFAULT (RPC_ANEG | RPC_SPEED | RPC_DPLX) |
1da177e4 LT |
691 | |
692 | ||
693 | /* Bank 0 0x0C is reserved */ | |
694 | ||
695 | // Bank Select Register | |
696 | /* All Banks */ | |
697 | #define BSR_REG 0x000E | |
698 | ||
699 | ||
700 | // Configuration Reg | |
701 | /* BANK 1 */ | |
cfdfa865 | 702 | #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1) |
1da177e4 LT |
703 | #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy |
704 | #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL | |
705 | #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus | |
706 | #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. | |
707 | ||
708 | // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low | |
709 | #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) | |
710 | ||
711 | ||
712 | // Base Address Register | |
713 | /* BANK 1 */ | |
cfdfa865 | 714 | #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1) |
1da177e4 LT |
715 | |
716 | ||
717 | // Individual Address Registers | |
718 | /* BANK 1 */ | |
cfdfa865 MD |
719 | #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1) |
720 | #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1) | |
721 | #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1) | |
1da177e4 LT |
722 | |
723 | ||
724 | // General Purpose Register | |
725 | /* BANK 1 */ | |
cfdfa865 | 726 | #define GP_REG(lp) SMC_REG(lp, 0x000A, 1) |
1da177e4 LT |
727 | |
728 | ||
729 | // Control Register | |
730 | /* BANK 1 */ | |
cfdfa865 | 731 | #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1) |
1da177e4 LT |
732 | #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received |
733 | #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically | |
734 | #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt | |
735 | #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt | |
736 | #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt | |
737 | #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store | |
738 | #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers | |
739 | #define CTL_STORE 0x0001 // When set stores registers into EEPROM | |
740 | ||
741 | ||
742 | // MMU Command Register | |
743 | /* BANK 2 */ | |
cfdfa865 | 744 | #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2) |
1da177e4 LT |
745 | #define MC_BUSY 1 // When 1 the last release has not completed |
746 | #define MC_NOP (0<<5) // No Op | |
747 | #define MC_ALLOC (1<<5) // OR with number of 256 byte packets | |
748 | #define MC_RESET (2<<5) // Reset MMU to initial state | |
749 | #define MC_REMOVE (3<<5) // Remove the current rx packet | |
750 | #define MC_RELEASE (4<<5) // Remove and release the current rx packet | |
751 | #define MC_FREEPKT (5<<5) // Release packet in PNR register | |
752 | #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit | |
753 | #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs | |
754 | ||
755 | ||
756 | // Packet Number Register | |
757 | /* BANK 2 */ | |
cfdfa865 | 758 | #define PN_REG(lp) SMC_REG(lp, 0x0002, 2) |
1da177e4 LT |
759 | |
760 | ||
761 | // Allocation Result Register | |
762 | /* BANK 2 */ | |
cfdfa865 | 763 | #define AR_REG(lp) SMC_REG(lp, 0x0003, 2) |
1da177e4 LT |
764 | #define AR_FAILED 0x80 // Alocation Failed |
765 | ||
766 | ||
767 | // TX FIFO Ports Register | |
768 | /* BANK 2 */ | |
cfdfa865 | 769 | #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2) |
1da177e4 LT |
770 | #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty |
771 | ||
772 | // RX FIFO Ports Register | |
773 | /* BANK 2 */ | |
cfdfa865 | 774 | #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2) |
1da177e4 LT |
775 | #define RXFIFO_REMPTY 0x80 // RX FIFO Empty |
776 | ||
cfdfa865 | 777 | #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2) |
1da177e4 LT |
778 | |
779 | // Pointer Register | |
780 | /* BANK 2 */ | |
cfdfa865 | 781 | #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2) |
1da177e4 LT |
782 | #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area |
783 | #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access | |
784 | #define PTR_READ 0x2000 // When 1 the operation is a read | |
785 | ||
786 | ||
787 | // Data Register | |
788 | /* BANK 2 */ | |
cfdfa865 | 789 | #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2) |
1da177e4 LT |
790 | |
791 | ||
792 | // Interrupt Status/Acknowledge Register | |
793 | /* BANK 2 */ | |
cfdfa865 | 794 | #define INT_REG(lp) SMC_REG(lp, 0x000C, 2) |
1da177e4 LT |
795 | |
796 | ||
797 | // Interrupt Mask Register | |
798 | /* BANK 2 */ | |
cfdfa865 | 799 | #define IM_REG(lp) SMC_REG(lp, 0x000D, 2) |
1da177e4 LT |
800 | #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt |
801 | #define IM_ERCV_INT 0x40 // Early Receive Interrupt | |
802 | #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section | |
803 | #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns | |
804 | #define IM_ALLOC_INT 0x08 // Set when allocation request is completed | |
805 | #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty | |
806 | #define IM_TX_INT 0x02 // Transmit Interrupt | |
807 | #define IM_RCV_INT 0x01 // Receive Interrupt | |
808 | ||
809 | ||
810 | // Multicast Table Registers | |
811 | /* BANK 3 */ | |
cfdfa865 MD |
812 | #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3) |
813 | #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3) | |
814 | #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3) | |
815 | #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3) | |
1da177e4 LT |
816 | |
817 | ||
818 | // Management Interface Register (MII) | |
819 | /* BANK 3 */ | |
cfdfa865 | 820 | #define MII_REG(lp) SMC_REG(lp, 0x0008, 3) |
1da177e4 LT |
821 | #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup |
822 | #define MII_MDOE 0x0008 // MII Output Enable | |
823 | #define MII_MCLK 0x0004 // MII Clock, pin MDCLK | |
824 | #define MII_MDI 0x0002 // MII Input, pin MDI | |
825 | #define MII_MDO 0x0001 // MII Output, pin MDO | |
826 | ||
827 | ||
828 | // Revision Register | |
829 | /* BANK 3 */ | |
830 | /* ( hi: chip id low: rev # ) */ | |
cfdfa865 | 831 | #define REV_REG(lp) SMC_REG(lp, 0x000A, 3) |
1da177e4 LT |
832 | |
833 | ||
834 | // Early RCV Register | |
835 | /* BANK 3 */ | |
836 | /* this is NOT on SMC9192 */ | |
cfdfa865 | 837 | #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3) |
1da177e4 LT |
838 | #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received |
839 | #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask | |
840 | ||
841 | ||
842 | // External Register | |
843 | /* BANK 7 */ | |
cfdfa865 | 844 | #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7) |
1da177e4 LT |
845 | |
846 | ||
847 | #define CHIP_9192 3 | |
848 | #define CHIP_9194 4 | |
849 | #define CHIP_9195 5 | |
850 | #define CHIP_9196 6 | |
851 | #define CHIP_91100 7 | |
852 | #define CHIP_91100FD 8 | |
853 | #define CHIP_91111FD 9 | |
854 | ||
855 | static const char * chip_ids[ 16 ] = { | |
856 | NULL, NULL, NULL, | |
857 | /* 3 */ "SMC91C90/91C92", | |
858 | /* 4 */ "SMC91C94", | |
859 | /* 5 */ "SMC91C95", | |
860 | /* 6 */ "SMC91C96", | |
861 | /* 7 */ "SMC91C100", | |
862 | /* 8 */ "SMC91C100FD", | |
863 | /* 9 */ "SMC91C11xFD", | |
864 | NULL, NULL, NULL, | |
865 | NULL, NULL, NULL}; | |
866 | ||
867 | ||
1da177e4 LT |
868 | /* |
869 | . Receive status bits | |
870 | */ | |
871 | #define RS_ALGNERR 0x8000 | |
872 | #define RS_BRODCAST 0x4000 | |
873 | #define RS_BADCRC 0x2000 | |
874 | #define RS_ODDFRAME 0x1000 | |
875 | #define RS_TOOLONG 0x0800 | |
876 | #define RS_TOOSHORT 0x0400 | |
877 | #define RS_MULTICAST 0x0001 | |
878 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | |
879 | ||
880 | ||
881 | /* | |
882 | * PHY IDs | |
883 | * LAN83C183 == LAN91C111 Internal PHY | |
884 | */ | |
885 | #define PHY_LAN83C183 0x0016f840 | |
886 | #define PHY_LAN83C180 0x02821c50 | |
887 | ||
888 | /* | |
889 | * PHY Register Addresses (LAN91C111 Internal PHY) | |
890 | * | |
891 | * Generic PHY registers can be found in <linux/mii.h> | |
892 | * | |
893 | * These phy registers are specific to our on-board phy. | |
894 | */ | |
895 | ||
896 | // PHY Configuration Register 1 | |
897 | #define PHY_CFG1_REG 0x10 | |
898 | #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled | |
899 | #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled | |
900 | #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down | |
901 | #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler | |
902 | #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable | |
903 | #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled | |
904 | #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) | |
905 | #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db | |
906 | #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust | |
907 | #define PHY_CFG1_TLVL_MASK 0x003C | |
908 | #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time | |
909 | ||
910 | ||
911 | // PHY Configuration Register 2 | |
912 | #define PHY_CFG2_REG 0x11 | |
913 | #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled | |
914 | #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled | |
915 | #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) | |
916 | #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo | |
917 | ||
918 | // PHY Status Output (and Interrupt status) Register | |
919 | #define PHY_INT_REG 0x12 // Status Output (Interrupt Status) | |
920 | #define PHY_INT_INT 0x8000 // 1=bits have changed since last read | |
921 | #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected | |
922 | #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync | |
923 | #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx | |
924 | #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx | |
925 | #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx | |
926 | #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected | |
927 | #define PHY_INT_JAB 0x0100 // 1=Jabber detected | |
928 | #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode | |
929 | #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex | |
930 | ||
931 | // PHY Interrupt/Status Mask Register | |
932 | #define PHY_MASK_REG 0x13 // Interrupt Mask | |
933 | // Uses the same bit definitions as PHY_INT_REG | |
934 | ||
935 | ||
936 | /* | |
937 | * SMC91C96 ethernet config and status registers. | |
938 | * These are in the "attribute" space. | |
939 | */ | |
940 | #define ECOR 0x8000 | |
941 | #define ECOR_RESET 0x80 | |
942 | #define ECOR_LEVEL_IRQ 0x40 | |
943 | #define ECOR_WR_ATTRIB 0x04 | |
944 | #define ECOR_ENABLE 0x01 | |
945 | ||
946 | #define ECSR 0x8002 | |
947 | #define ECSR_IOIS8 0x20 | |
948 | #define ECSR_PWRDWN 0x04 | |
949 | #define ECSR_INT 0x02 | |
950 | ||
951 | #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) | |
952 | ||
953 | ||
954 | /* | |
955 | * Macros to abstract register access according to the data bus | |
956 | * capabilities. Please use those and not the in/out primitives. | |
957 | * Note: the following macros do *not* select the bank -- this must | |
958 | * be done separately as needed in the main code. The SMC_REG() macro | |
959 | * only uses the bank argument for debugging purposes (when enabled). | |
09779c6d NP |
960 | * |
961 | * Note: despite inline functions being safer, everything leading to this | |
962 | * should preferably be macros to let BUG() display the line number in | |
963 | * the core source code since we're interested in the top call site | |
964 | * not in any inline function location. | |
1da177e4 LT |
965 | */ |
966 | ||
967 | #if SMC_DEBUG > 0 | |
cfdfa865 | 968 | #define SMC_REG(lp, reg, bank) \ |
1da177e4 | 969 | ({ \ |
cfdfa865 | 970 | int __b = SMC_CURRENT_BANK(lp); \ |
1da177e4 LT |
971 | if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ |
972 | printk( "%s: bank reg screwed (0x%04x)\n", \ | |
973 | CARDNAME, __b ); \ | |
974 | BUG(); \ | |
975 | } \ | |
976 | reg<<SMC_IO_SHIFT; \ | |
977 | }) | |
978 | #else | |
cfdfa865 | 979 | #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT) |
1da177e4 LT |
980 | #endif |
981 | ||
09779c6d NP |
982 | /* |
983 | * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not | |
984 | * aligned to a 32 bit boundary. I tell you that does exist! | |
985 | * Fortunately the affected register accesses can be easily worked around | |
986 | * since we can write zeroes to the preceeding 16 bits without adverse | |
987 | * effects and use a 32-bit access. | |
988 | * | |
989 | * Enforce it on any 32-bit capable setup for now. | |
990 | */ | |
3e947943 | 991 | #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp) |
09779c6d | 992 | |
cfdfa865 | 993 | #define SMC_GET_PN(lp) \ |
3e947943 | 994 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \ |
cfdfa865 | 995 | : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF)) |
09779c6d | 996 | |
cfdfa865 | 997 | #define SMC_SET_PN(lp, x) \ |
09779c6d | 998 | do { \ |
3e947943 | 999 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1000 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \ |
3e947943 | 1001 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1002 | SMC_outb(x, ioaddr, PN_REG(lp)); \ |
09779c6d | 1003 | else \ |
cfdfa865 | 1004 | SMC_outw(x, ioaddr, PN_REG(lp)); \ |
09779c6d NP |
1005 | } while (0) |
1006 | ||
cfdfa865 | 1007 | #define SMC_GET_AR(lp) \ |
3e947943 | 1008 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \ |
cfdfa865 | 1009 | : (SMC_inw(ioaddr, PN_REG(lp)) >> 8)) |
09779c6d | 1010 | |
cfdfa865 | 1011 | #define SMC_GET_TXFIFO(lp) \ |
3e947943 | 1012 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \ |
cfdfa865 | 1013 | : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF)) |
09779c6d | 1014 | |
cfdfa865 | 1015 | #define SMC_GET_RXFIFO(lp) \ |
3e947943 | 1016 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \ |
cfdfa865 | 1017 | : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8)) |
09779c6d | 1018 | |
cfdfa865 | 1019 | #define SMC_GET_INT(lp) \ |
3e947943 | 1020 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \ |
cfdfa865 | 1021 | : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF)) |
09779c6d | 1022 | |
cfdfa865 | 1023 | #define SMC_ACK_INT(lp, x) \ |
1da177e4 | 1024 | do { \ |
3e947943 | 1025 | if (SMC_8BIT(lp)) \ |
cfdfa865 | 1026 | SMC_outb(x, ioaddr, INT_REG(lp)); \ |
09779c6d NP |
1027 | else { \ |
1028 | unsigned long __flags; \ | |
1029 | int __mask; \ | |
1030 | local_irq_save(__flags); \ | |
cfdfa865 MD |
1031 | __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \ |
1032 | SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \ | |
09779c6d NP |
1033 | local_irq_restore(__flags); \ |
1034 | } \ | |
1035 | } while (0) | |
1036 | ||
cfdfa865 | 1037 | #define SMC_GET_INT_MASK(lp) \ |
3e947943 | 1038 | (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \ |
cfdfa865 | 1039 | : (SMC_inw(ioaddr, INT_REG(lp)) >> 8)) |
09779c6d | 1040 | |
cfdfa865 | 1041 | #define SMC_SET_INT_MASK(lp, x) \ |
09779c6d | 1042 | do { \ |
3e947943 | 1043 | if (SMC_8BIT(lp)) \ |
cfdfa865 | 1044 | SMC_outb(x, ioaddr, IM_REG(lp)); \ |
09779c6d | 1045 | else \ |
cfdfa865 | 1046 | SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \ |
09779c6d NP |
1047 | } while (0) |
1048 | ||
cfdfa865 | 1049 | #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) |
09779c6d | 1050 | |
cfdfa865 | 1051 | #define SMC_SELECT_BANK(lp, x) \ |
09779c6d | 1052 | do { \ |
3e947943 | 1053 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
09779c6d NP |
1054 | SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ |
1055 | else \ | |
1056 | SMC_outw(x, ioaddr, BANK_SELECT); \ | |
1057 | } while (0) | |
1058 | ||
cfdfa865 | 1059 | #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp)) |
09779c6d | 1060 | |
cfdfa865 | 1061 | #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp)) |
09779c6d | 1062 | |
cfdfa865 | 1063 | #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp)) |
09779c6d | 1064 | |
cfdfa865 | 1065 | #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp)) |
09779c6d | 1066 | |
cfdfa865 | 1067 | #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp)) |
09779c6d | 1068 | |
cfdfa865 | 1069 | #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp)) |
09779c6d | 1070 | |
cfdfa865 | 1071 | #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp)) |
09779c6d | 1072 | |
cfdfa865 | 1073 | #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp)) |
09779c6d | 1074 | |
357fe2c6 VS |
1075 | #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp)) |
1076 | ||
1077 | #define SMC_SET_GP(lp, x) \ | |
1078 | do { \ | |
1079 | if (SMC_MUST_ALIGN_WRITE(lp)) \ | |
1080 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \ | |
1081 | else \ | |
1082 | SMC_outw(x, ioaddr, GP_REG(lp)); \ | |
1083 | } while (0) | |
1084 | ||
cfdfa865 | 1085 | #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp)) |
09779c6d | 1086 | |
cfdfa865 | 1087 | #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp)) |
09779c6d | 1088 | |
cfdfa865 | 1089 | #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp)) |
09779c6d | 1090 | |
cfdfa865 | 1091 | #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp)) |
09779c6d | 1092 | |
cfdfa865 | 1093 | #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp)) |
09779c6d | 1094 | |
cfdfa865 | 1095 | #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp)) |
09779c6d | 1096 | |
cfdfa865 | 1097 | #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp)) |
09779c6d | 1098 | |
cfdfa865 | 1099 | #define SMC_SET_PTR(lp, x) \ |
09779c6d | 1100 | do { \ |
3e947943 | 1101 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1102 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \ |
09779c6d | 1103 | else \ |
cfdfa865 | 1104 | SMC_outw(x, ioaddr, PTR_REG(lp)); \ |
1da177e4 | 1105 | } while (0) |
1da177e4 | 1106 | |
cfdfa865 | 1107 | #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp)) |
09779c6d | 1108 | |
cfdfa865 | 1109 | #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp)) |
09779c6d | 1110 | |
cfdfa865 | 1111 | #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp)) |
09779c6d | 1112 | |
cfdfa865 | 1113 | #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp)) |
09779c6d | 1114 | |
cfdfa865 | 1115 | #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp)) |
09779c6d | 1116 | |
cfdfa865 | 1117 | #define SMC_SET_RPC(lp, x) \ |
09779c6d | 1118 | do { \ |
3e947943 | 1119 | if (SMC_MUST_ALIGN_WRITE(lp)) \ |
cfdfa865 | 1120 | SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \ |
09779c6d | 1121 | else \ |
cfdfa865 | 1122 | SMC_outw(x, ioaddr, RPC_REG(lp)); \ |
09779c6d NP |
1123 | } while (0) |
1124 | ||
cfdfa865 | 1125 | #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp)) |
09779c6d | 1126 | |
cfdfa865 | 1127 | #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp)) |
1da177e4 LT |
1128 | |
1129 | #ifndef SMC_GET_MAC_ADDR | |
cfdfa865 | 1130 | #define SMC_GET_MAC_ADDR(lp, addr) \ |
1da177e4 LT |
1131 | do { \ |
1132 | unsigned int __v; \ | |
cfdfa865 | 1133 | __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \ |
1da177e4 | 1134 | addr[0] = __v; addr[1] = __v >> 8; \ |
cfdfa865 | 1135 | __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ |
1da177e4 | 1136 | addr[2] = __v; addr[3] = __v >> 8; \ |
cfdfa865 | 1137 | __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ |
1da177e4 LT |
1138 | addr[4] = __v; addr[5] = __v >> 8; \ |
1139 | } while (0) | |
1140 | #endif | |
1141 | ||
cfdfa865 | 1142 | #define SMC_SET_MAC_ADDR(lp, addr) \ |
1da177e4 | 1143 | do { \ |
cfdfa865 MD |
1144 | SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ |
1145 | SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ | |
1146 | SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ | |
1da177e4 LT |
1147 | } while (0) |
1148 | ||
cfdfa865 | 1149 | #define SMC_SET_MCAST(lp, x) \ |
1da177e4 LT |
1150 | do { \ |
1151 | const unsigned char *mt = (x); \ | |
cfdfa865 MD |
1152 | SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ |
1153 | SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ | |
1154 | SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ | |
1155 | SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ | |
1da177e4 LT |
1156 | } while (0) |
1157 | ||
cfdfa865 | 1158 | #define SMC_PUT_PKT_HDR(lp, status, length) \ |
1da177e4 | 1159 | do { \ |
3e947943 | 1160 | if (SMC_32BIT(lp)) \ |
cfdfa865 MD |
1161 | SMC_outl((status) | (length)<<16, ioaddr, \ |
1162 | DATA_REG(lp)); \ | |
09779c6d | 1163 | else { \ |
cfdfa865 MD |
1164 | SMC_outw(status, ioaddr, DATA_REG(lp)); \ |
1165 | SMC_outw(length, ioaddr, DATA_REG(lp)); \ | |
09779c6d | 1166 | } \ |
1da177e4 | 1167 | } while (0) |
1da177e4 | 1168 | |
cfdfa865 | 1169 | #define SMC_GET_PKT_HDR(lp, status, length) \ |
1da177e4 | 1170 | do { \ |
3e947943 | 1171 | if (SMC_32BIT(lp)) { \ |
cfdfa865 | 1172 | unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \ |
09779c6d NP |
1173 | (status) = __val & 0xffff; \ |
1174 | (length) = __val >> 16; \ | |
1175 | } else { \ | |
cfdfa865 MD |
1176 | (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ |
1177 | (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ | |
1da177e4 LT |
1178 | } \ |
1179 | } while (0) | |
1da177e4 | 1180 | |
cfdfa865 | 1181 | #define SMC_PUSH_DATA(lp, p, l) \ |
1da177e4 | 1182 | do { \ |
3e947943 | 1183 | if (SMC_32BIT(lp)) { \ |
09779c6d NP |
1184 | void *__ptr = (p); \ |
1185 | int __len = (l); \ | |
fbd81976 | 1186 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1187 | if (__len >= 2 && (unsigned long)__ptr & 2) { \ |
1188 | __len -= 2; \ | |
cfdfa865 MD |
1189 | SMC_outw(*(u16 *)__ptr, ioaddr, \ |
1190 | DATA_REG(lp)); \ | |
09779c6d NP |
1191 | __ptr += 2; \ |
1192 | } \ | |
1193 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1194 | __ioaddr = lp->datacs; \ | |
cfdfa865 | 1195 | SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ |
09779c6d NP |
1196 | if (__len & 2) { \ |
1197 | __ptr += (__len & ~3); \ | |
cfdfa865 MD |
1198 | SMC_outw(*((u16 *)__ptr), ioaddr, \ |
1199 | DATA_REG(lp)); \ | |
09779c6d | 1200 | } \ |
3e947943 | 1201 | } else if (SMC_16BIT(lp)) \ |
cfdfa865 | 1202 | SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ |
3e947943 | 1203 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1204 | SMC_outsb(ioaddr, DATA_REG(lp), p, l); \ |
1da177e4 | 1205 | } while (0) |
1da177e4 | 1206 | |
cfdfa865 | 1207 | #define SMC_PULL_DATA(lp, p, l) \ |
09779c6d | 1208 | do { \ |
3e947943 | 1209 | if (SMC_32BIT(lp)) { \ |
09779c6d NP |
1210 | void *__ptr = (p); \ |
1211 | int __len = (l); \ | |
fbd81976 | 1212 | void __iomem *__ioaddr = ioaddr; \ |
09779c6d NP |
1213 | if ((unsigned long)__ptr & 2) { \ |
1214 | /* \ | |
1215 | * We want 32bit alignment here. \ | |
1216 | * Since some buses perform a full \ | |
1217 | * 32bit fetch even for 16bit data \ | |
1218 | * we can't use SMC_inw() here. \ | |
1219 | * Back both source (on-chip) and \ | |
1220 | * destination pointers of 2 bytes. \ | |
1221 | * This is possible since the call to \ | |
1222 | * SMC_GET_PKT_HDR() already advanced \ | |
1223 | * the source pointer of 4 bytes, and \ | |
1224 | * the skb_reserve(skb, 2) advanced \ | |
1225 | * the destination pointer of 2 bytes. \ | |
1226 | */ \ | |
1227 | __ptr -= 2; \ | |
1228 | __len += 2; \ | |
cfdfa865 MD |
1229 | SMC_SET_PTR(lp, \ |
1230 | 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ | |
09779c6d NP |
1231 | } \ |
1232 | if (SMC_CAN_USE_DATACS && lp->datacs) \ | |
1233 | __ioaddr = lp->datacs; \ | |
1da177e4 | 1234 | __len += 2; \ |
cfdfa865 | 1235 | SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \ |
3e947943 | 1236 | } else if (SMC_16BIT(lp)) \ |
cfdfa865 | 1237 | SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \ |
3e947943 | 1238 | else if (SMC_8BIT(lp)) \ |
cfdfa865 | 1239 | SMC_insb(ioaddr, DATA_REG(lp), p, l); \ |
09779c6d | 1240 | } while (0) |
1da177e4 LT |
1241 | |
1242 | #endif /* _SMC91X_H_ */ |