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1da177e4 LT |
1 | /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */ |
2 | /* | |
3 | Written 1998-2000 by Donald Becker. | |
4 | ||
fdecea66 | 5 | Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please |
1da177e4 LT |
6 | send all bug reports to me, and not to Donald Becker, as this code |
7 | has been heavily modified from Donald's original version. | |
8 | ||
9 | This software may be used and distributed according to the terms of | |
10 | the GNU General Public License (GPL), incorporated herein by reference. | |
11 | Drivers based on or derived from this code fall under the GPL and must | |
12 | retain the authorship, copyright and license notice. This file is not | |
13 | a complete program and may only be used when the entire operating | |
14 | system is licensed under the GPL. | |
15 | ||
16 | The information below comes from Donald Becker's original driver: | |
17 | ||
18 | The author may be reached as becker@scyld.com, or C/O | |
19 | Scyld Computing Corporation | |
20 | 410 Severn Ave., Suite 210 | |
21 | Annapolis MD 21403 | |
22 | ||
23 | Support and updates available at | |
24 | http://www.scyld.com/network/starfire.html | |
03a8c661 | 25 | [link no longer provides useful info -jgarzik] |
1da177e4 | 26 | |
1da177e4 LT |
27 | */ |
28 | ||
29 | #define DRV_NAME "starfire" | |
03a8c661 JG |
30 | #define DRV_VERSION "2.0" |
31 | #define DRV_RELDATE "June 27, 2006" | |
1da177e4 | 32 | |
1da177e4 LT |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/delay.h> | |
fdecea66 JG |
40 | #include <linux/crc32.h> |
41 | #include <linux/ethtool.h> | |
42 | #include <linux/mii.h> | |
43 | #include <linux/if_vlan.h> | |
1da177e4 LT |
44 | #include <asm/processor.h> /* Processor type for cache alignment. */ |
45 | #include <asm/uaccess.h> | |
46 | #include <asm/io.h> | |
47 | ||
fdecea66 | 48 | #include "starfire_firmware.h" |
1da177e4 LT |
49 | /* |
50 | * The current frame processor firmware fails to checksum a fragment | |
51 | * of length 1. If and when this is fixed, the #define below can be removed. | |
52 | */ | |
53 | #define HAS_BROKEN_FIRMWARE | |
67974231 IB |
54 | |
55 | /* | |
56 | * If using the broken firmware, data must be padded to the next 32-bit boundary. | |
57 | */ | |
58 | #ifdef HAS_BROKEN_FIRMWARE | |
59 | #define PADDING_MASK 3 | |
60 | #endif | |
61 | ||
1da177e4 LT |
62 | /* |
63 | * Define this if using the driver with the zero-copy patch | |
64 | */ | |
1da177e4 | 65 | #define ZEROCOPY |
1da177e4 LT |
66 | |
67 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
68 | #define VLAN_SUPPORT | |
69 | #endif | |
70 | ||
71 | #ifndef CONFIG_ADAPTEC_STARFIRE_NAPI | |
72 | #undef HAVE_NETDEV_POLL | |
73 | #endif | |
74 | ||
75 | /* The user-configurable values. | |
76 | These may be modified when a driver module is loaded.*/ | |
77 | ||
78 | /* Used for tuning interrupt latency vs. overhead. */ | |
79 | static int intr_latency; | |
80 | static int small_frames; | |
81 | ||
82 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
83 | static int max_interrupt_work = 20; | |
84 | static int mtu; | |
85 | /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). | |
86 | The Starfire has a 512 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 87 | static const int multicast_filter_limit = 512; |
1da177e4 | 88 | /* Whether to do TCP/UDP checksums in hardware */ |
1da177e4 | 89 | static int enable_hw_cksum = 1; |
1da177e4 LT |
90 | |
91 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
92 | /* | |
93 | * Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
94 | * Setting to > 1518 effectively disables this feature. | |
95 | * | |
96 | * NOTE: | |
97 | * The ia64 doesn't allow for unaligned loads even of integers being | |
98 | * misaligned on a 2 byte boundary. Thus always force copying of | |
99 | * packets as the starfire doesn't allow for misaligned DMAs ;-( | |
100 | * 23/10/2000 - Jes | |
101 | * | |
102 | * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64, | |
103 | * at least, having unaligned frames leads to a rather serious performance | |
104 | * penalty. -Ion | |
105 | */ | |
106 | #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__) | |
107 | static int rx_copybreak = PKT_BUF_SZ; | |
108 | #else | |
109 | static int rx_copybreak /* = 0 */; | |
110 | #endif | |
111 | ||
112 | /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */ | |
113 | #ifdef __sparc__ | |
114 | #define DMA_BURST_SIZE 64 | |
115 | #else | |
116 | #define DMA_BURST_SIZE 128 | |
117 | #endif | |
118 | ||
119 | /* Used to pass the media type, etc. | |
120 | Both 'options[]' and 'full_duplex[]' exist for driver interoperability. | |
121 | The media type is usually passed in 'options[]'. | |
122 | These variables are deprecated, use ethtool instead. -Ion | |
123 | */ | |
124 | #define MAX_UNITS 8 /* More are supported, limit only on options */ | |
125 | static int options[MAX_UNITS] = {0, }; | |
126 | static int full_duplex[MAX_UNITS] = {0, }; | |
127 | ||
128 | /* Operational parameters that are set at compile time. */ | |
129 | ||
130 | /* The "native" ring sizes are either 256 or 2048. | |
131 | However in some modes a descriptor may be marked to wrap the ring earlier. | |
132 | */ | |
133 | #define RX_RING_SIZE 256 | |
134 | #define TX_RING_SIZE 32 | |
135 | /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */ | |
136 | #define DONE_Q_SIZE 1024 | |
137 | /* All queues must be aligned on a 256-byte boundary */ | |
138 | #define QUEUE_ALIGN 256 | |
139 | ||
140 | #if RX_RING_SIZE > 256 | |
141 | #define RX_Q_ENTRIES Rx2048QEntries | |
142 | #else | |
143 | #define RX_Q_ENTRIES Rx256QEntries | |
144 | #endif | |
145 | ||
146 | /* Operational parameters that usually are not changed. */ | |
147 | /* Time in jiffies before concluding the transmitter is hung. */ | |
148 | #define TX_TIMEOUT (2 * HZ) | |
149 | ||
150 | /* | |
151 | * This SUCKS. | |
152 | * We need a much better method to determine if dma_addr_t is 64-bit. | |
153 | */ | |
67974231 | 154 | #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) |
1da177e4 LT |
155 | /* 64-bit dma_addr_t */ |
156 | #define ADDR_64BITS /* This chip uses 64 bit addresses. */ | |
67974231 | 157 | #define netdrv_addr_t u64 |
1da177e4 LT |
158 | #define cpu_to_dma(x) cpu_to_le64(x) |
159 | #define dma_to_cpu(x) le64_to_cpu(x) | |
160 | #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit | |
161 | #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit | |
162 | #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit | |
163 | #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit | |
164 | #define RX_DESC_ADDR_SIZE RxDescAddr64bit | |
165 | #else /* 32-bit dma_addr_t */ | |
67974231 | 166 | #define netdrv_addr_t u32 |
1da177e4 LT |
167 | #define cpu_to_dma(x) cpu_to_le32(x) |
168 | #define dma_to_cpu(x) le32_to_cpu(x) | |
169 | #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit | |
170 | #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit | |
171 | #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit | |
172 | #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit | |
173 | #define RX_DESC_ADDR_SIZE RxDescAddr32bit | |
174 | #endif | |
175 | ||
1da177e4 LT |
176 | #define skb_first_frag_len(skb) skb_headlen(skb) |
177 | #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1) | |
1da177e4 LT |
178 | |
179 | #ifdef HAVE_NETDEV_POLL | |
180 | #define init_poll(dev) \ | |
fdecea66 | 181 | do { \ |
1da177e4 | 182 | dev->poll = &netdev_poll; \ |
fdecea66 JG |
183 | dev->weight = max_interrupt_work; \ |
184 | } while (0) | |
1da177e4 LT |
185 | #define netdev_rx(dev, ioaddr) \ |
186 | do { \ | |
187 | u32 intr_enable; \ | |
188 | if (netif_rx_schedule_prep(dev)) { \ | |
189 | __netif_rx_schedule(dev); \ | |
190 | intr_enable = readl(ioaddr + IntrEnable); \ | |
191 | intr_enable &= ~(IntrRxDone | IntrRxEmpty); \ | |
192 | writel(intr_enable, ioaddr + IntrEnable); \ | |
193 | readl(ioaddr + IntrEnable); /* flush PCI posting buffers */ \ | |
194 | } else { \ | |
195 | /* Paranoia check */ \ | |
196 | intr_enable = readl(ioaddr + IntrEnable); \ | |
197 | if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \ | |
fdecea66 | 198 | printk(KERN_INFO "%s: interrupt while in polling mode!\n", dev->name); \ |
1da177e4 LT |
199 | intr_enable &= ~(IntrRxDone | IntrRxEmpty); \ |
200 | writel(intr_enable, ioaddr + IntrEnable); \ | |
201 | } \ | |
202 | } \ | |
203 | } while (0) | |
204 | #define netdev_receive_skb(skb) netif_receive_skb(skb) | |
205 | #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_receive_skb(skb, vlgrp, vlid) | |
206 | static int netdev_poll(struct net_device *dev, int *budget); | |
207 | #else /* not HAVE_NETDEV_POLL */ | |
208 | #define init_poll(dev) | |
209 | #define netdev_receive_skb(skb) netif_rx(skb) | |
210 | #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_rx(skb, vlgrp, vlid) | |
211 | #define netdev_rx(dev, ioaddr) \ | |
212 | do { \ | |
213 | int quota = np->dirty_rx + RX_RING_SIZE - np->cur_rx; \ | |
214 | __netdev_rx(dev, "a);\ | |
215 | } while (0) | |
216 | #endif /* not HAVE_NETDEV_POLL */ | |
217 | /* end of compatibility code */ | |
218 | ||
219 | ||
220 | /* These identify the driver base version and may not be removed. */ | |
e19360f2 | 221 | static const char version[] __devinitdata = |
1da177e4 LT |
222 | KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n" |
223 | KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n"; | |
224 | ||
225 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
226 | MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver"); | |
227 | MODULE_LICENSE("GPL"); | |
fdecea66 | 228 | MODULE_VERSION(DRV_VERSION); |
1da177e4 LT |
229 | |
230 | module_param(max_interrupt_work, int, 0); | |
231 | module_param(mtu, int, 0); | |
232 | module_param(debug, int, 0); | |
233 | module_param(rx_copybreak, int, 0); | |
234 | module_param(intr_latency, int, 0); | |
235 | module_param(small_frames, int, 0); | |
236 | module_param_array(options, int, NULL, 0); | |
237 | module_param_array(full_duplex, int, NULL, 0); | |
238 | module_param(enable_hw_cksum, int, 0); | |
239 | MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt"); | |
240 | MODULE_PARM_DESC(mtu, "MTU (all boards)"); | |
241 | MODULE_PARM_DESC(debug, "Debug level (0-6)"); | |
242 | MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); | |
243 | MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds"); | |
244 | MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)"); | |
245 | MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex"); | |
246 | MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)"); | |
247 | MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)"); | |
248 | ||
249 | /* | |
250 | Theory of Operation | |
251 | ||
252 | I. Board Compatibility | |
253 | ||
254 | This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter. | |
255 | ||
256 | II. Board-specific settings | |
257 | ||
258 | III. Driver operation | |
259 | ||
260 | IIIa. Ring buffers | |
261 | ||
262 | The Starfire hardware uses multiple fixed-size descriptor queues/rings. The | |
263 | ring sizes are set fixed by the hardware, but may optionally be wrapped | |
264 | earlier by the END bit in the descriptor. | |
265 | This driver uses that hardware queue size for the Rx ring, where a large | |
266 | number of entries has no ill effect beyond increases the potential backlog. | |
267 | The Tx ring is wrapped with the END bit, since a large hardware Tx queue | |
268 | disables the queue layer priority ordering and we have no mechanism to | |
269 | utilize the hardware two-level priority queue. When modifying the | |
270 | RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning | |
271 | levels. | |
272 | ||
273 | IIIb/c. Transmit/Receive Structure | |
274 | ||
275 | See the Adaptec manual for the many possible structures, and options for | |
276 | each structure. There are far too many to document all of them here. | |
277 | ||
278 | For transmit this driver uses type 0/1 transmit descriptors (depending | |
279 | on the 32/64 bitness of the architecture), and relies on automatic | |
280 | minimum-length padding. It does not use the completion queue | |
281 | consumer index, but instead checks for non-zero status entries. | |
282 | ||
fdecea66 | 283 | For receive this driver uses type 2/3 receive descriptors. The driver |
1da177e4 LT |
284 | allocates full frame size skbuffs for the Rx ring buffers, so all frames |
285 | should fit in a single descriptor. The driver does not use the completion | |
286 | queue consumer index, but instead checks for non-zero status entries. | |
287 | ||
288 | When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff | |
289 | is allocated and the frame is copied to the new skbuff. When the incoming | |
290 | frame is larger, the skbuff is passed directly up the protocol stack. | |
291 | Buffers consumed this way are replaced by newly allocated skbuffs in a later | |
292 | phase of receive. | |
293 | ||
294 | A notable aspect of operation is that unaligned buffers are not permitted by | |
295 | the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame | |
296 | isn't longword aligned, which may cause problems on some machine | |
297 | e.g. Alphas and IA64. For these architectures, the driver is forced to copy | |
298 | the frame into a new skbuff unconditionally. Copied frames are put into the | |
299 | skbuff at an offset of "+2", thus 16-byte aligning the IP header. | |
300 | ||
301 | IIId. Synchronization | |
302 | ||
303 | The driver runs as two independent, single-threaded flows of control. One | |
304 | is the send-packet routine, which enforces single-threaded use by the | |
305 | dev->tbusy flag. The other thread is the interrupt handler, which is single | |
306 | threaded by the hardware and interrupt handling software. | |
307 | ||
308 | The send packet thread has partial control over the Tx ring and the netif_queue | |
309 | status. If the number of free Tx slots in the ring falls below a certain number | |
310 | (currently hardcoded to 4), it signals the upper layer to stop the queue. | |
311 | ||
312 | The interrupt handler has exclusive control over the Rx ring and records stats | |
313 | from the Tx ring. After reaping the stats, it marks the Tx queue entry as | |
314 | empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the | |
315 | number of free Tx slow is above the threshold, it signals the upper layer to | |
316 | restart the queue. | |
317 | ||
318 | IV. Notes | |
319 | ||
320 | IVb. References | |
321 | ||
322 | The Adaptec Starfire manuals, available only from Adaptec. | |
323 | http://www.scyld.com/expert/100mbps.html | |
324 | http://www.scyld.com/expert/NWay.html | |
325 | ||
326 | IVc. Errata | |
327 | ||
328 | - StopOnPerr is broken, don't enable | |
329 | - Hardware ethernet padding exposes random data, perform software padding | |
330 | instead (unverified -- works correctly for all the hardware I have) | |
331 | ||
332 | */ | |
333 | ||
fdecea66 | 334 | |
1da177e4 LT |
335 | |
336 | enum chip_capability_flags {CanHaveMII=1, }; | |
337 | ||
338 | enum chipset { | |
339 | CH_6915 = 0, | |
340 | }; | |
341 | ||
342 | static struct pci_device_id starfire_pci_tbl[] = { | |
343 | { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 }, | |
344 | { 0, } | |
345 | }; | |
346 | MODULE_DEVICE_TABLE(pci, starfire_pci_tbl); | |
347 | ||
348 | /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */ | |
f71e1309 | 349 | static const struct chip_info { |
1da177e4 LT |
350 | const char *name; |
351 | int drv_flags; | |
352 | } netdrv_tbl[] __devinitdata = { | |
353 | { "Adaptec Starfire 6915", CanHaveMII }, | |
354 | }; | |
355 | ||
356 | ||
357 | /* Offsets to the device registers. | |
358 | Unlike software-only systems, device drivers interact with complex hardware. | |
359 | It's not useful to define symbolic names for every register bit in the | |
360 | device. The name can only partially document the semantics and make | |
361 | the driver longer and more difficult to read. | |
362 | In general, only the important configuration values or bits changed | |
363 | multiple times should be defined symbolically. | |
364 | */ | |
365 | enum register_offsets { | |
366 | PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074, | |
367 | IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088, | |
368 | MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000, | |
369 | GPIOCtrl=0x5008C, TxDescCtrl=0x50090, | |
370 | TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */ | |
371 | TxRingHiAddr=0x5009C, /* 64 bit address extension. */ | |
372 | TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4, | |
373 | TxThreshold=0x500B0, | |
374 | CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8, | |
375 | RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0, | |
376 | CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0, | |
377 | RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0, | |
378 | RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4, | |
379 | TxMode=0x55000, VlanType=0x55064, | |
380 | PerfFilterTable=0x56000, HashTable=0x56100, | |
381 | TxGfpMem=0x58000, RxGfpMem=0x5a000, | |
382 | }; | |
383 | ||
384 | /* | |
385 | * Bits in the interrupt status/mask registers. | |
386 | * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register | |
387 | * enables all the interrupt sources that are or'ed into those status bits. | |
388 | */ | |
389 | enum intr_status_bits { | |
390 | IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000, | |
391 | IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000, | |
392 | IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000, | |
393 | IntrTxComplQLow=0x200000, IntrPCI=0x100000, | |
394 | IntrDMAErr=0x080000, IntrTxDataLow=0x040000, | |
395 | IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000, | |
396 | IntrNormalSummary=0x8000, IntrTxDone=0x4000, | |
397 | IntrTxDMADone=0x2000, IntrTxEmpty=0x1000, | |
398 | IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400, | |
399 | IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100, | |
400 | IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40, | |
401 | IntrNoTxCsum=0x20, IntrTxBadID=0x10, | |
402 | IntrHiPriTxBadID=0x08, IntrRxGfp=0x04, | |
403 | IntrTxGfp=0x02, IntrPCIPad=0x01, | |
404 | /* not quite bits */ | |
405 | IntrRxDone=IntrRxQ2Done | IntrRxQ1Done, | |
406 | IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low, | |
407 | IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe, | |
408 | }; | |
409 | ||
410 | /* Bits in the RxFilterMode register. */ | |
411 | enum rx_mode_bits { | |
412 | AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01, | |
413 | AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30, | |
414 | PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200, | |
415 | WakeupOnGFP=0x0800, | |
416 | }; | |
417 | ||
418 | /* Bits in the TxMode register */ | |
419 | enum tx_mode_bits { | |
420 | MiiSoftReset=0x8000, MIILoopback=0x4000, | |
421 | TxFlowEnable=0x0800, RxFlowEnable=0x0400, | |
422 | PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01, | |
423 | }; | |
424 | ||
425 | /* Bits in the TxDescCtrl register. */ | |
426 | enum tx_ctrl_bits { | |
427 | TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20, | |
428 | TxDescSpace128=0x30, TxDescSpace256=0x40, | |
429 | TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02, | |
430 | TxDescType3=0x03, TxDescType4=0x04, | |
431 | TxNoDMACompletion=0x08, | |
432 | TxDescQAddr64bit=0x80, TxDescQAddr32bit=0, | |
433 | TxHiPriFIFOThreshShift=24, TxPadLenShift=16, | |
434 | TxDMABurstSizeShift=8, | |
435 | }; | |
436 | ||
437 | /* Bits in the RxDescQCtrl register. */ | |
438 | enum rx_ctrl_bits { | |
439 | RxBufferLenShift=16, RxMinDescrThreshShift=0, | |
440 | RxPrefetchMode=0x8000, RxVariableQ=0x2000, | |
441 | Rx2048QEntries=0x4000, Rx256QEntries=0, | |
442 | RxDescAddr64bit=0x1000, RxDescAddr32bit=0, | |
443 | RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0, | |
444 | RxDescSpace4=0x000, RxDescSpace8=0x100, | |
445 | RxDescSpace16=0x200, RxDescSpace32=0x300, | |
446 | RxDescSpace64=0x400, RxDescSpace128=0x500, | |
447 | RxConsumerWrEn=0x80, | |
448 | }; | |
449 | ||
450 | /* Bits in the RxDMACtrl register. */ | |
451 | enum rx_dmactrl_bits { | |
452 | RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000, | |
453 | RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000, | |
454 | RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000, | |
455 | RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000, | |
456 | RxChecksumRejectTCPOnly=0x01000000, | |
457 | RxCompletionQ2Enable=0x800000, | |
458 | RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000, | |
459 | RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000, | |
460 | RxDMAQ2NonIP=0x400000, | |
461 | RxUseBackupQueue=0x080000, RxDMACRC=0x040000, | |
462 | RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8, | |
463 | RxBurstSizeShift=0, | |
464 | }; | |
465 | ||
466 | /* Bits in the RxCompletionAddr register */ | |
467 | enum rx_compl_bits { | |
468 | RxComplQAddr64bit=0x80, RxComplQAddr32bit=0, | |
469 | RxComplProducerWrEn=0x40, | |
470 | RxComplType0=0x00, RxComplType1=0x10, | |
471 | RxComplType2=0x20, RxComplType3=0x30, | |
472 | RxComplThreshShift=0, | |
473 | }; | |
474 | ||
475 | /* Bits in the TxCompletionAddr register */ | |
476 | enum tx_compl_bits { | |
477 | TxComplQAddr64bit=0x80, TxComplQAddr32bit=0, | |
478 | TxComplProducerWrEn=0x40, | |
479 | TxComplIntrStatus=0x20, | |
480 | CommonQueueMode=0x10, | |
481 | TxComplThreshShift=0, | |
482 | }; | |
483 | ||
484 | /* Bits in the GenCtrl register */ | |
485 | enum gen_ctrl_bits { | |
486 | RxEnable=0x05, TxEnable=0x0a, | |
487 | RxGFPEnable=0x10, TxGFPEnable=0x20, | |
488 | }; | |
489 | ||
490 | /* Bits in the IntrTimerCtrl register */ | |
491 | enum intr_ctrl_bits { | |
492 | Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100, | |
493 | SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600, | |
494 | IntrLatencyMask=0x1f, | |
495 | }; | |
496 | ||
497 | /* The Rx and Tx buffer descriptors. */ | |
498 | struct starfire_rx_desc { | |
499 | dma_addr_t rxaddr; | |
500 | }; | |
501 | enum rx_desc_bits { | |
502 | RxDescValid=1, RxDescEndRing=2, | |
503 | }; | |
504 | ||
505 | /* Completion queue entry. */ | |
506 | struct short_rx_done_desc { | |
507 | u32 status; /* Low 16 bits is length. */ | |
508 | }; | |
509 | struct basic_rx_done_desc { | |
510 | u32 status; /* Low 16 bits is length. */ | |
511 | u16 vlanid; | |
512 | u16 status2; | |
513 | }; | |
514 | struct csum_rx_done_desc { | |
515 | u32 status; /* Low 16 bits is length. */ | |
516 | u16 csum; /* Partial checksum */ | |
517 | u16 status2; | |
518 | }; | |
519 | struct full_rx_done_desc { | |
520 | u32 status; /* Low 16 bits is length. */ | |
521 | u16 status3; | |
522 | u16 status2; | |
523 | u16 vlanid; | |
524 | u16 csum; /* partial checksum */ | |
525 | u32 timestamp; | |
526 | }; | |
527 | /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */ | |
1da177e4 LT |
528 | #ifdef VLAN_SUPPORT |
529 | typedef struct full_rx_done_desc rx_done_desc; | |
530 | #define RxComplType RxComplType3 | |
531 | #else /* not VLAN_SUPPORT */ | |
532 | typedef struct csum_rx_done_desc rx_done_desc; | |
533 | #define RxComplType RxComplType2 | |
534 | #endif /* not VLAN_SUPPORT */ | |
1da177e4 LT |
535 | |
536 | enum rx_done_bits { | |
537 | RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000, | |
538 | }; | |
539 | ||
540 | /* Type 1 Tx descriptor. */ | |
541 | struct starfire_tx_desc_1 { | |
542 | u32 status; /* Upper bits are status, lower 16 length. */ | |
543 | u32 addr; | |
544 | }; | |
545 | ||
546 | /* Type 2 Tx descriptor. */ | |
547 | struct starfire_tx_desc_2 { | |
548 | u32 status; /* Upper bits are status, lower 16 length. */ | |
549 | u32 reserved; | |
550 | u64 addr; | |
551 | }; | |
552 | ||
553 | #ifdef ADDR_64BITS | |
554 | typedef struct starfire_tx_desc_2 starfire_tx_desc; | |
555 | #define TX_DESC_TYPE TxDescType2 | |
556 | #else /* not ADDR_64BITS */ | |
557 | typedef struct starfire_tx_desc_1 starfire_tx_desc; | |
558 | #define TX_DESC_TYPE TxDescType1 | |
559 | #endif /* not ADDR_64BITS */ | |
560 | #define TX_DESC_SPACING TxDescSpaceUnlim | |
561 | ||
562 | enum tx_desc_bits { | |
563 | TxDescID=0xB0000000, | |
564 | TxCRCEn=0x01000000, TxDescIntr=0x08000000, | |
565 | TxRingWrap=0x04000000, TxCalTCP=0x02000000, | |
566 | }; | |
567 | struct tx_done_desc { | |
568 | u32 status; /* timestamp, index. */ | |
569 | #if 0 | |
570 | u32 intrstatus; /* interrupt status */ | |
571 | #endif | |
572 | }; | |
573 | ||
574 | struct rx_ring_info { | |
575 | struct sk_buff *skb; | |
576 | dma_addr_t mapping; | |
577 | }; | |
578 | struct tx_ring_info { | |
579 | struct sk_buff *skb; | |
580 | dma_addr_t mapping; | |
581 | unsigned int used_slots; | |
582 | }; | |
583 | ||
584 | #define PHY_CNT 2 | |
585 | struct netdev_private { | |
586 | /* Descriptor rings first for alignment. */ | |
587 | struct starfire_rx_desc *rx_ring; | |
588 | starfire_tx_desc *tx_ring; | |
589 | dma_addr_t rx_ring_dma; | |
590 | dma_addr_t tx_ring_dma; | |
591 | /* The addresses of rx/tx-in-place skbuffs. */ | |
592 | struct rx_ring_info rx_info[RX_RING_SIZE]; | |
593 | struct tx_ring_info tx_info[TX_RING_SIZE]; | |
594 | /* Pointers to completion queues (full pages). */ | |
595 | rx_done_desc *rx_done_q; | |
596 | dma_addr_t rx_done_q_dma; | |
597 | unsigned int rx_done; | |
598 | struct tx_done_desc *tx_done_q; | |
599 | dma_addr_t tx_done_q_dma; | |
600 | unsigned int tx_done; | |
601 | struct net_device_stats stats; | |
602 | struct pci_dev *pci_dev; | |
603 | #ifdef VLAN_SUPPORT | |
604 | struct vlan_group *vlgrp; | |
605 | #endif | |
606 | void *queue_mem; | |
607 | dma_addr_t queue_mem_dma; | |
608 | size_t queue_mem_size; | |
609 | ||
610 | /* Frequently used values: keep some adjacent for cache effect. */ | |
611 | spinlock_t lock; | |
612 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
613 | unsigned int cur_tx, dirty_tx, reap_tx; | |
614 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
615 | /* These values keep track of the transceiver/media in use. */ | |
616 | int speed100; /* Set if speed == 100MBit. */ | |
617 | u32 tx_mode; | |
618 | u32 intr_timer_ctrl; | |
619 | u8 tx_threshold; | |
620 | /* MII transceiver section. */ | |
621 | struct mii_if_info mii_if; /* MII lib hooks/info */ | |
622 | int phy_cnt; /* MII device addresses. */ | |
623 | unsigned char phys[PHY_CNT]; /* MII device addresses. */ | |
624 | void __iomem *base; | |
625 | }; | |
626 | ||
627 | ||
628 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
629 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
630 | static int netdev_open(struct net_device *dev); | |
631 | static void check_duplex(struct net_device *dev); | |
632 | static void tx_timeout(struct net_device *dev); | |
633 | static void init_ring(struct net_device *dev); | |
634 | static int start_tx(struct sk_buff *skb, struct net_device *dev); | |
635 | static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs); | |
636 | static void netdev_error(struct net_device *dev, int intr_status); | |
637 | static int __netdev_rx(struct net_device *dev, int *quota); | |
638 | static void refill_rx_ring(struct net_device *dev); | |
639 | static void netdev_error(struct net_device *dev, int intr_status); | |
640 | static void set_rx_mode(struct net_device *dev); | |
641 | static struct net_device_stats *get_stats(struct net_device *dev); | |
642 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
643 | static int netdev_close(struct net_device *dev); | |
644 | static void netdev_media_change(struct net_device *dev); | |
645 | static struct ethtool_ops ethtool_ops; | |
646 | ||
647 | ||
648 | #ifdef VLAN_SUPPORT | |
649 | static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
650 | { | |
651 | struct netdev_private *np = netdev_priv(dev); | |
652 | ||
653 | spin_lock(&np->lock); | |
654 | if (debug > 2) | |
655 | printk("%s: Setting vlgrp to %p\n", dev->name, grp); | |
656 | np->vlgrp = grp; | |
657 | set_rx_mode(dev); | |
658 | spin_unlock(&np->lock); | |
659 | } | |
660 | ||
661 | static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid) | |
662 | { | |
663 | struct netdev_private *np = netdev_priv(dev); | |
664 | ||
665 | spin_lock(&np->lock); | |
666 | if (debug > 1) | |
667 | printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid); | |
668 | set_rx_mode(dev); | |
669 | spin_unlock(&np->lock); | |
670 | } | |
671 | ||
672 | static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
673 | { | |
674 | struct netdev_private *np = netdev_priv(dev); | |
675 | ||
676 | spin_lock(&np->lock); | |
677 | if (debug > 1) | |
678 | printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid); | |
679 | if (np->vlgrp) | |
680 | np->vlgrp->vlan_devices[vid] = NULL; | |
681 | set_rx_mode(dev); | |
682 | spin_unlock(&np->lock); | |
683 | } | |
684 | #endif /* VLAN_SUPPORT */ | |
685 | ||
686 | ||
687 | static int __devinit starfire_init_one(struct pci_dev *pdev, | |
688 | const struct pci_device_id *ent) | |
689 | { | |
690 | struct netdev_private *np; | |
691 | int i, irq, option, chip_idx = ent->driver_data; | |
692 | struct net_device *dev; | |
693 | static int card_idx = -1; | |
694 | long ioaddr; | |
695 | void __iomem *base; | |
696 | int drv_flags, io_size; | |
697 | int boguscnt; | |
698 | ||
699 | /* when built into the kernel, we only print version if device is found */ | |
700 | #ifndef MODULE | |
701 | static int printed_version; | |
702 | if (!printed_version++) | |
703 | printk(version); | |
704 | #endif | |
705 | ||
706 | card_idx++; | |
707 | ||
708 | if (pci_enable_device (pdev)) | |
709 | return -EIO; | |
710 | ||
711 | ioaddr = pci_resource_start(pdev, 0); | |
712 | io_size = pci_resource_len(pdev, 0); | |
713 | if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) { | |
714 | printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx); | |
715 | return -ENODEV; | |
716 | } | |
717 | ||
718 | dev = alloc_etherdev(sizeof(*np)); | |
719 | if (!dev) { | |
720 | printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx); | |
721 | return -ENOMEM; | |
722 | } | |
723 | SET_MODULE_OWNER(dev); | |
724 | SET_NETDEV_DEV(dev, &pdev->dev); | |
725 | ||
726 | irq = pdev->irq; | |
727 | ||
728 | if (pci_request_regions (pdev, DRV_NAME)) { | |
729 | printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx); | |
730 | goto err_out_free_netdev; | |
731 | } | |
732 | ||
1da177e4 LT |
733 | base = ioremap(ioaddr, io_size); |
734 | if (!base) { | |
735 | printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n", | |
736 | card_idx, io_size, ioaddr); | |
737 | goto err_out_free_res; | |
738 | } | |
739 | ||
740 | pci_set_master(pdev); | |
741 | ||
742 | /* enable MWI -- it vastly improves Rx performance on sparc64 */ | |
743 | pci_set_mwi(pdev); | |
744 | ||
1da177e4 LT |
745 | #ifdef ZEROCOPY |
746 | /* Starfire can do TCP/UDP checksumming */ | |
747 | if (enable_hw_cksum) | |
fdecea66 | 748 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
1da177e4 LT |
749 | #endif /* ZEROCOPY */ |
750 | #ifdef VLAN_SUPPORT | |
751 | dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER; | |
752 | dev->vlan_rx_register = netdev_vlan_rx_register; | |
753 | dev->vlan_rx_add_vid = netdev_vlan_rx_add_vid; | |
754 | dev->vlan_rx_kill_vid = netdev_vlan_rx_kill_vid; | |
755 | #endif /* VLAN_RX_KILL_VID */ | |
756 | #ifdef ADDR_64BITS | |
757 | dev->features |= NETIF_F_HIGHDMA; | |
758 | #endif /* ADDR_64BITS */ | |
759 | ||
760 | /* Serial EEPROM reads are hidden by the hardware. */ | |
761 | for (i = 0; i < 6; i++) | |
762 | dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i); | |
763 | ||
764 | #if ! defined(final_version) /* Dump the EEPROM contents during development. */ | |
765 | if (debug > 4) | |
766 | for (i = 0; i < 0x20; i++) | |
767 | printk("%2.2x%s", | |
768 | (unsigned int)readb(base + EEPROMCtrl + i), | |
769 | i % 16 != 15 ? " " : "\n"); | |
770 | #endif | |
771 | ||
772 | /* Issue soft reset */ | |
773 | writel(MiiSoftReset, base + TxMode); | |
774 | udelay(1000); | |
775 | writel(0, base + TxMode); | |
776 | ||
777 | /* Reset the chip to erase previous misconfiguration. */ | |
778 | writel(1, base + PCIDeviceConfig); | |
779 | boguscnt = 1000; | |
780 | while (--boguscnt > 0) { | |
781 | udelay(10); | |
782 | if ((readl(base + PCIDeviceConfig) & 1) == 0) | |
783 | break; | |
784 | } | |
785 | if (boguscnt == 0) | |
786 | printk("%s: chipset reset never completed!\n", dev->name); | |
787 | /* wait a little longer */ | |
788 | udelay(1000); | |
789 | ||
790 | dev->base_addr = (unsigned long)base; | |
791 | dev->irq = irq; | |
792 | ||
793 | np = netdev_priv(dev); | |
794 | np->base = base; | |
795 | spin_lock_init(&np->lock); | |
796 | pci_set_drvdata(pdev, dev); | |
797 | ||
798 | np->pci_dev = pdev; | |
799 | ||
800 | np->mii_if.dev = dev; | |
801 | np->mii_if.mdio_read = mdio_read; | |
802 | np->mii_if.mdio_write = mdio_write; | |
803 | np->mii_if.phy_id_mask = 0x1f; | |
804 | np->mii_if.reg_num_mask = 0x1f; | |
805 | ||
806 | drv_flags = netdrv_tbl[chip_idx].drv_flags; | |
807 | ||
808 | option = card_idx < MAX_UNITS ? options[card_idx] : 0; | |
809 | if (dev->mem_start) | |
810 | option = dev->mem_start; | |
811 | ||
812 | /* The lower four bits are the media type. */ | |
813 | if (option & 0x200) | |
814 | np->mii_if.full_duplex = 1; | |
815 | ||
816 | if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) | |
817 | np->mii_if.full_duplex = 1; | |
818 | ||
819 | if (np->mii_if.full_duplex) | |
820 | np->mii_if.force_media = 1; | |
821 | else | |
822 | np->mii_if.force_media = 0; | |
823 | np->speed100 = 1; | |
824 | ||
825 | /* timer resolution is 128 * 0.8us */ | |
826 | np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) | | |
827 | Timer10X | EnableIntrMasking; | |
828 | ||
829 | if (small_frames > 0) { | |
830 | np->intr_timer_ctrl |= SmallFrameBypass; | |
831 | switch (small_frames) { | |
832 | case 1 ... 64: | |
833 | np->intr_timer_ctrl |= SmallFrame64; | |
834 | break; | |
835 | case 65 ... 128: | |
836 | np->intr_timer_ctrl |= SmallFrame128; | |
837 | break; | |
838 | case 129 ... 256: | |
839 | np->intr_timer_ctrl |= SmallFrame256; | |
840 | break; | |
841 | default: | |
842 | np->intr_timer_ctrl |= SmallFrame512; | |
843 | if (small_frames > 512) | |
844 | printk("Adjusting small_frames down to 512\n"); | |
845 | break; | |
846 | } | |
847 | } | |
848 | ||
849 | /* The chip-specific entries in the device structure. */ | |
850 | dev->open = &netdev_open; | |
851 | dev->hard_start_xmit = &start_tx; | |
fdecea66 JG |
852 | dev->tx_timeout = tx_timeout; |
853 | dev->watchdog_timeo = TX_TIMEOUT; | |
1da177e4 LT |
854 | init_poll(dev); |
855 | dev->stop = &netdev_close; | |
856 | dev->get_stats = &get_stats; | |
857 | dev->set_multicast_list = &set_rx_mode; | |
858 | dev->do_ioctl = &netdev_ioctl; | |
859 | SET_ETHTOOL_OPS(dev, ðtool_ops); | |
860 | ||
861 | if (mtu) | |
862 | dev->mtu = mtu; | |
863 | ||
864 | if (register_netdev(dev)) | |
865 | goto err_out_cleardev; | |
866 | ||
867 | printk(KERN_INFO "%s: %s at %p, ", | |
868 | dev->name, netdrv_tbl[chip_idx].name, base); | |
869 | for (i = 0; i < 5; i++) | |
870 | printk("%2.2x:", dev->dev_addr[i]); | |
871 | printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq); | |
872 | ||
873 | if (drv_flags & CanHaveMII) { | |
874 | int phy, phy_idx = 0; | |
875 | int mii_status; | |
876 | for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) { | |
877 | mdio_write(dev, phy, MII_BMCR, BMCR_RESET); | |
878 | mdelay(100); | |
879 | boguscnt = 1000; | |
880 | while (--boguscnt > 0) | |
881 | if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0) | |
882 | break; | |
883 | if (boguscnt == 0) { | |
fdecea66 | 884 | printk("%s: PHY#%d reset never completed!\n", dev->name, phy); |
1da177e4 LT |
885 | continue; |
886 | } | |
887 | mii_status = mdio_read(dev, phy, MII_BMSR); | |
888 | if (mii_status != 0) { | |
889 | np->phys[phy_idx++] = phy; | |
890 | np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE); | |
891 | printk(KERN_INFO "%s: MII PHY found at address %d, status " | |
892 | "%#4.4x advertising %#4.4x.\n", | |
893 | dev->name, phy, mii_status, np->mii_if.advertising); | |
894 | /* there can be only one PHY on-board */ | |
895 | break; | |
896 | } | |
897 | } | |
898 | np->phy_cnt = phy_idx; | |
899 | if (np->phy_cnt > 0) | |
900 | np->mii_if.phy_id = np->phys[0]; | |
901 | else | |
902 | memset(&np->mii_if, 0, sizeof(np->mii_if)); | |
903 | } | |
904 | ||
905 | printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n", | |
906 | dev->name, enable_hw_cksum ? "enabled" : "disabled"); | |
907 | return 0; | |
908 | ||
909 | err_out_cleardev: | |
910 | pci_set_drvdata(pdev, NULL); | |
911 | iounmap(base); | |
912 | err_out_free_res: | |
913 | pci_release_regions (pdev); | |
914 | err_out_free_netdev: | |
915 | free_netdev(dev); | |
916 | return -ENODEV; | |
917 | } | |
918 | ||
919 | ||
920 | /* Read the MII Management Data I/O (MDIO) interfaces. */ | |
921 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
922 | { | |
923 | struct netdev_private *np = netdev_priv(dev); | |
924 | void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); | |
925 | int result, boguscnt=1000; | |
926 | /* ??? Should we add a busy-wait here? */ | |
927 | do | |
928 | result = readl(mdio_addr); | |
929 | while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0); | |
930 | if (boguscnt == 0) | |
931 | return 0; | |
932 | if ((result & 0xffff) == 0xffff) | |
933 | return 0; | |
934 | return result & 0xffff; | |
935 | } | |
936 | ||
937 | ||
938 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
939 | { | |
940 | struct netdev_private *np = netdev_priv(dev); | |
941 | void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2); | |
942 | writel(value, mdio_addr); | |
943 | /* The busy-wait will occur before a read. */ | |
944 | } | |
945 | ||
946 | ||
947 | static int netdev_open(struct net_device *dev) | |
948 | { | |
949 | struct netdev_private *np = netdev_priv(dev); | |
950 | void __iomem *ioaddr = np->base; | |
951 | int i, retval; | |
952 | size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size; | |
953 | ||
954 | /* Do we ever need to reset the chip??? */ | |
fdecea66 | 955 | |
1fb9df5d | 956 | retval = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
957 | if (retval) |
958 | return retval; | |
959 | ||
960 | /* Disable the Rx and Tx, and reset the chip. */ | |
961 | writel(0, ioaddr + GenCtrl); | |
962 | writel(1, ioaddr + PCIDeviceConfig); | |
963 | if (debug > 1) | |
964 | printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", | |
965 | dev->name, dev->irq); | |
966 | ||
967 | /* Allocate the various queues. */ | |
968 | if (np->queue_mem == 0) { | |
969 | tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; | |
970 | rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; | |
971 | tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; | |
972 | rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE; | |
973 | np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size; | |
974 | np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma); | |
d8840ac9 AD |
975 | if (np->queue_mem == NULL) { |
976 | free_irq(dev->irq, dev); | |
1da177e4 | 977 | return -ENOMEM; |
d8840ac9 | 978 | } |
1da177e4 LT |
979 | |
980 | np->tx_done_q = np->queue_mem; | |
981 | np->tx_done_q_dma = np->queue_mem_dma; | |
982 | np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size; | |
983 | np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size; | |
984 | np->tx_ring = (void *) np->rx_done_q + rx_done_q_size; | |
985 | np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size; | |
986 | np->rx_ring = (void *) np->tx_ring + tx_ring_size; | |
987 | np->rx_ring_dma = np->tx_ring_dma + tx_ring_size; | |
988 | } | |
989 | ||
990 | /* Start with no carrier, it gets adjusted later */ | |
991 | netif_carrier_off(dev); | |
992 | init_ring(dev); | |
993 | /* Set the size of the Rx buffers. */ | |
994 | writel((np->rx_buf_sz << RxBufferLenShift) | | |
995 | (0 << RxMinDescrThreshShift) | | |
996 | RxPrefetchMode | RxVariableQ | | |
997 | RX_Q_ENTRIES | | |
998 | RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE | | |
999 | RxDescSpace4, | |
1000 | ioaddr + RxDescQCtrl); | |
1001 | ||
1002 | /* Set up the Rx DMA controller. */ | |
1003 | writel(RxChecksumIgnore | | |
1004 | (0 << RxEarlyIntThreshShift) | | |
1005 | (6 << RxHighPrioThreshShift) | | |
1006 | ((DMA_BURST_SIZE / 32) << RxBurstSizeShift), | |
1007 | ioaddr + RxDMACtrl); | |
1008 | ||
1009 | /* Set Tx descriptor */ | |
1010 | writel((2 << TxHiPriFIFOThreshShift) | | |
1011 | (0 << TxPadLenShift) | | |
1012 | ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) | | |
1013 | TX_DESC_Q_ADDR_SIZE | | |
1014 | TX_DESC_SPACING | TX_DESC_TYPE, | |
1015 | ioaddr + TxDescCtrl); | |
1016 | ||
1017 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr); | |
1018 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr); | |
1019 | writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr); | |
1020 | writel(np->rx_ring_dma, ioaddr + RxDescQAddr); | |
1021 | writel(np->tx_ring_dma, ioaddr + TxRingPtr); | |
1022 | ||
1023 | writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr); | |
1024 | writel(np->rx_done_q_dma | | |
1025 | RxComplType | | |
1026 | (0 << RxComplThreshShift), | |
1027 | ioaddr + RxCompletionAddr); | |
1028 | ||
1029 | if (debug > 1) | |
1030 | printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name); | |
1031 | ||
1032 | /* Fill both the Tx SA register and the Rx perfect filter. */ | |
1033 | for (i = 0; i < 6; i++) | |
1034 | writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i); | |
1035 | /* The first entry is special because it bypasses the VLAN filter. | |
1036 | Don't use it. */ | |
1037 | writew(0, ioaddr + PerfFilterTable); | |
1038 | writew(0, ioaddr + PerfFilterTable + 4); | |
1039 | writew(0, ioaddr + PerfFilterTable + 8); | |
1040 | for (i = 1; i < 16; i++) { | |
1041 | u16 *eaddrs = (u16 *)dev->dev_addr; | |
1042 | void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16; | |
1043 | writew(cpu_to_be16(eaddrs[2]), setup_frm); setup_frm += 4; | |
1044 | writew(cpu_to_be16(eaddrs[1]), setup_frm); setup_frm += 4; | |
1045 | writew(cpu_to_be16(eaddrs[0]), setup_frm); setup_frm += 8; | |
1046 | } | |
1047 | ||
1048 | /* Initialize other registers. */ | |
1049 | /* Configure the PCI bus bursts and FIFO thresholds. */ | |
1050 | np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */ | |
1051 | writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode); | |
1052 | udelay(1000); | |
1053 | writel(np->tx_mode, ioaddr + TxMode); | |
1054 | np->tx_threshold = 4; | |
1055 | writel(np->tx_threshold, ioaddr + TxThreshold); | |
1056 | ||
1057 | writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl); | |
1058 | ||
1da177e4 LT |
1059 | netif_start_queue(dev); |
1060 | ||
1061 | if (debug > 1) | |
1062 | printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name); | |
1063 | set_rx_mode(dev); | |
1064 | ||
1065 | np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE); | |
1066 | check_duplex(dev); | |
1067 | ||
1068 | /* Enable GPIO interrupts on link change */ | |
1069 | writel(0x0f00ff00, ioaddr + GPIOCtrl); | |
1070 | ||
1071 | /* Set the interrupt mask */ | |
1072 | writel(IntrRxDone | IntrRxEmpty | IntrDMAErr | | |
1073 | IntrTxDMADone | IntrStatsMax | IntrLinkChange | | |
1074 | IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID, | |
1075 | ioaddr + IntrEnable); | |
1076 | /* Enable PCI interrupts. */ | |
1077 | writel(0x00800000 | readl(ioaddr + PCIDeviceConfig), | |
1078 | ioaddr + PCIDeviceConfig); | |
1079 | ||
1080 | #ifdef VLAN_SUPPORT | |
1081 | /* Set VLAN type to 802.1q */ | |
1082 | writel(ETH_P_8021Q, ioaddr + VlanType); | |
1083 | #endif /* VLAN_SUPPORT */ | |
1084 | ||
1da177e4 LT |
1085 | /* Load Rx/Tx firmware into the frame processors */ |
1086 | for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++) | |
1087 | writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4); | |
1088 | for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++) | |
1089 | writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4); | |
1da177e4 LT |
1090 | if (enable_hw_cksum) |
1091 | /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */ | |
1092 | writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl); | |
1093 | else | |
1094 | /* Enable the Rx and Tx units only. */ | |
1095 | writel(TxEnable|RxEnable, ioaddr + GenCtrl); | |
1096 | ||
1097 | if (debug > 1) | |
1098 | printk(KERN_DEBUG "%s: Done netdev_open().\n", | |
1099 | dev->name); | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | ||
1105 | static void check_duplex(struct net_device *dev) | |
1106 | { | |
1107 | struct netdev_private *np = netdev_priv(dev); | |
1108 | u16 reg0; | |
1109 | int silly_count = 1000; | |
1110 | ||
1111 | mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising); | |
1112 | mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET); | |
1113 | udelay(500); | |
1114 | while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET) | |
1115 | /* do nothing */; | |
1116 | if (!silly_count) { | |
1117 | printk("%s: MII reset failed!\n", dev->name); | |
1118 | return; | |
1119 | } | |
1120 | ||
1121 | reg0 = mdio_read(dev, np->phys[0], MII_BMCR); | |
1122 | ||
1123 | if (!np->mii_if.force_media) { | |
1124 | reg0 |= BMCR_ANENABLE | BMCR_ANRESTART; | |
1125 | } else { | |
1126 | reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART); | |
1127 | if (np->speed100) | |
1128 | reg0 |= BMCR_SPEED100; | |
1129 | if (np->mii_if.full_duplex) | |
1130 | reg0 |= BMCR_FULLDPLX; | |
1131 | printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n", | |
1132 | dev->name, | |
1133 | np->speed100 ? "100" : "10", | |
1134 | np->mii_if.full_duplex ? "full" : "half"); | |
1135 | } | |
1136 | mdio_write(dev, np->phys[0], MII_BMCR, reg0); | |
1137 | } | |
1138 | ||
1139 | ||
1140 | static void tx_timeout(struct net_device *dev) | |
1141 | { | |
1142 | struct netdev_private *np = netdev_priv(dev); | |
1143 | void __iomem *ioaddr = np->base; | |
1144 | int old_debug; | |
1145 | ||
1146 | printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, " | |
1147 | "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus)); | |
1148 | ||
1149 | /* Perhaps we should reinitialize the hardware here. */ | |
1150 | ||
1151 | /* | |
1152 | * Stop and restart the interface. | |
1153 | * Cheat and increase the debug level temporarily. | |
1154 | */ | |
1155 | old_debug = debug; | |
1156 | debug = 2; | |
1157 | netdev_close(dev); | |
1158 | netdev_open(dev); | |
1159 | debug = old_debug; | |
1160 | ||
1161 | /* Trigger an immediate transmit demand. */ | |
1162 | ||
1163 | dev->trans_start = jiffies; | |
1164 | np->stats.tx_errors++; | |
1165 | netif_wake_queue(dev); | |
1166 | } | |
1167 | ||
1168 | ||
1169 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
1170 | static void init_ring(struct net_device *dev) | |
1171 | { | |
1172 | struct netdev_private *np = netdev_priv(dev); | |
1173 | int i; | |
1174 | ||
1175 | np->cur_rx = np->cur_tx = np->reap_tx = 0; | |
1176 | np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0; | |
1177 | ||
1178 | np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
1179 | ||
1180 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
1181 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1182 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz); | |
1183 | np->rx_info[i].skb = skb; | |
1184 | if (skb == NULL) | |
1185 | break; | |
689be439 | 1186 | np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1187 | skb->dev = dev; /* Mark as being used by this device. */ |
1188 | /* Grrr, we cannot offset to correctly align the IP header. */ | |
1189 | np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid); | |
1190 | } | |
1191 | writew(i - 1, np->base + RxDescQIdx); | |
1192 | np->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
1193 | ||
1194 | /* Clear the remainder of the Rx buffer ring. */ | |
1195 | for ( ; i < RX_RING_SIZE; i++) { | |
1196 | np->rx_ring[i].rxaddr = 0; | |
1197 | np->rx_info[i].skb = NULL; | |
1198 | np->rx_info[i].mapping = 0; | |
1199 | } | |
1200 | /* Mark the last entry as wrapping the ring. */ | |
1201 | np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing); | |
1202 | ||
1203 | /* Clear the completion rings. */ | |
1204 | for (i = 0; i < DONE_Q_SIZE; i++) { | |
1205 | np->rx_done_q[i].status = 0; | |
1206 | np->tx_done_q[i].status = 0; | |
1207 | } | |
1208 | ||
1209 | for (i = 0; i < TX_RING_SIZE; i++) | |
1210 | memset(&np->tx_info[i], 0, sizeof(np->tx_info[i])); | |
1211 | ||
1212 | return; | |
1213 | } | |
1214 | ||
1215 | ||
1216 | static int start_tx(struct sk_buff *skb, struct net_device *dev) | |
1217 | { | |
1218 | struct netdev_private *np = netdev_priv(dev); | |
1219 | unsigned int entry; | |
1220 | u32 status; | |
1221 | int i; | |
1222 | ||
1da177e4 LT |
1223 | /* |
1224 | * be cautious here, wrapping the queue has weird semantics | |
1225 | * and we may not have enough slots even when it seems we do. | |
1226 | */ | |
1227 | if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) { | |
1228 | netif_stop_queue(dev); | |
1229 | return 1; | |
1230 | } | |
1231 | ||
1232 | #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE) | |
84fa7933 | 1233 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
5b057c6b | 1234 | if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK)) |
67974231 | 1235 | return NETDEV_TX_OK; |
1da177e4 LT |
1236 | } |
1237 | #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */ | |
1238 | ||
1239 | entry = np->cur_tx % TX_RING_SIZE; | |
1240 | for (i = 0; i < skb_num_frags(skb); i++) { | |
1241 | int wrap_ring = 0; | |
1242 | status = TxDescID; | |
1243 | ||
1244 | if (i == 0) { | |
1245 | np->tx_info[entry].skb = skb; | |
1246 | status |= TxCRCEn; | |
1247 | if (entry >= TX_RING_SIZE - skb_num_frags(skb)) { | |
1248 | status |= TxRingWrap; | |
1249 | wrap_ring = 1; | |
1250 | } | |
1251 | if (np->reap_tx) { | |
1252 | status |= TxDescIntr; | |
1253 | np->reap_tx = 0; | |
1254 | } | |
84fa7933 | 1255 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
1da177e4 LT |
1256 | status |= TxCalTCP; |
1257 | np->stats.tx_compressed++; | |
1258 | } | |
1259 | status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16); | |
1260 | ||
1261 | np->tx_info[entry].mapping = | |
1262 | pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE); | |
1263 | } else { | |
1da177e4 LT |
1264 | skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1]; |
1265 | status |= this_frag->size; | |
1266 | np->tx_info[entry].mapping = | |
1267 | pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE); | |
1da177e4 LT |
1268 | } |
1269 | ||
1270 | np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping); | |
1271 | np->tx_ring[entry].status = cpu_to_le32(status); | |
1272 | if (debug > 3) | |
1273 | printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n", | |
1274 | dev->name, np->cur_tx, np->dirty_tx, | |
1275 | entry, status); | |
1276 | if (wrap_ring) { | |
1277 | np->tx_info[entry].used_slots = TX_RING_SIZE - entry; | |
1278 | np->cur_tx += np->tx_info[entry].used_slots; | |
1279 | entry = 0; | |
1280 | } else { | |
1281 | np->tx_info[entry].used_slots = 1; | |
1282 | np->cur_tx += np->tx_info[entry].used_slots; | |
1283 | entry++; | |
1284 | } | |
1285 | /* scavenge the tx descriptors twice per TX_RING_SIZE */ | |
1286 | if (np->cur_tx % (TX_RING_SIZE / 2) == 0) | |
1287 | np->reap_tx = 1; | |
1288 | } | |
1289 | ||
1290 | /* Non-x86: explicitly flush descriptor cache lines here. */ | |
1291 | /* Ensure all descriptors are written back before the transmit is | |
1292 | initiated. - Jes */ | |
1293 | wmb(); | |
1294 | ||
1295 | /* Update the producer index. */ | |
1296 | writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx); | |
1297 | ||
1298 | /* 4 is arbitrary, but should be ok */ | |
1299 | if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE) | |
1300 | netif_stop_queue(dev); | |
1301 | ||
1302 | dev->trans_start = jiffies; | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
1307 | ||
1308 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1309 | after the Tx thread. */ | |
1310 | static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs) | |
1311 | { | |
1312 | struct net_device *dev = dev_instance; | |
1313 | struct netdev_private *np = netdev_priv(dev); | |
1314 | void __iomem *ioaddr = np->base; | |
1315 | int boguscnt = max_interrupt_work; | |
1316 | int consumer; | |
1317 | int tx_status; | |
1318 | int handled = 0; | |
1319 | ||
1320 | do { | |
1321 | u32 intr_status = readl(ioaddr + IntrClear); | |
1322 | ||
1323 | if (debug > 4) | |
1324 | printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n", | |
1325 | dev->name, intr_status); | |
1326 | ||
1327 | if (intr_status == 0 || intr_status == (u32) -1) | |
1328 | break; | |
1329 | ||
1330 | handled = 1; | |
1331 | ||
1332 | if (intr_status & (IntrRxDone | IntrRxEmpty)) | |
1333 | netdev_rx(dev, ioaddr); | |
1334 | ||
1335 | /* Scavenge the skbuff list based on the Tx-done queue. | |
1336 | There are redundant checks here that may be cleaned up | |
1337 | after the driver has proven to be reliable. */ | |
1338 | consumer = readl(ioaddr + TxConsumerIdx); | |
1339 | if (debug > 3) | |
1340 | printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n", | |
1341 | dev->name, consumer); | |
1342 | ||
1343 | while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) { | |
1344 | if (debug > 3) | |
1345 | printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n", | |
1346 | dev->name, np->dirty_tx, np->tx_done, tx_status); | |
1347 | if ((tx_status & 0xe0000000) == 0xa0000000) { | |
1348 | np->stats.tx_packets++; | |
1349 | } else if ((tx_status & 0xe0000000) == 0x80000000) { | |
1350 | u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc); | |
1351 | struct sk_buff *skb = np->tx_info[entry].skb; | |
1352 | np->tx_info[entry].skb = NULL; | |
1353 | pci_unmap_single(np->pci_dev, | |
1354 | np->tx_info[entry].mapping, | |
1355 | skb_first_frag_len(skb), | |
1356 | PCI_DMA_TODEVICE); | |
1357 | np->tx_info[entry].mapping = 0; | |
1358 | np->dirty_tx += np->tx_info[entry].used_slots; | |
1359 | entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE; | |
1da177e4 LT |
1360 | { |
1361 | int i; | |
1362 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1363 | pci_unmap_single(np->pci_dev, | |
1364 | np->tx_info[entry].mapping, | |
1365 | skb_shinfo(skb)->frags[i].size, | |
1366 | PCI_DMA_TODEVICE); | |
1367 | np->dirty_tx++; | |
1368 | entry++; | |
1369 | } | |
1370 | } | |
fdecea66 | 1371 | |
1da177e4 LT |
1372 | dev_kfree_skb_irq(skb); |
1373 | } | |
1374 | np->tx_done_q[np->tx_done].status = 0; | |
1375 | np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE; | |
1376 | } | |
1377 | writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2); | |
1378 | ||
1379 | if (netif_queue_stopped(dev) && | |
1380 | (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) { | |
1381 | /* The ring is no longer full, wake the queue. */ | |
1382 | netif_wake_queue(dev); | |
1383 | } | |
1384 | ||
1385 | /* Stats overflow */ | |
1386 | if (intr_status & IntrStatsMax) | |
1387 | get_stats(dev); | |
1388 | ||
1389 | /* Media change interrupt. */ | |
1390 | if (intr_status & IntrLinkChange) | |
1391 | netdev_media_change(dev); | |
1392 | ||
1393 | /* Abnormal error summary/uncommon events handlers. */ | |
1394 | if (intr_status & IntrAbnormalSummary) | |
1395 | netdev_error(dev, intr_status); | |
1396 | ||
1397 | if (--boguscnt < 0) { | |
1398 | if (debug > 1) | |
1399 | printk(KERN_WARNING "%s: Too much work at interrupt, " | |
1400 | "status=%#8.8x.\n", | |
1401 | dev->name, intr_status); | |
1402 | break; | |
1403 | } | |
1404 | } while (1); | |
1405 | ||
1406 | if (debug > 4) | |
1407 | printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n", | |
1408 | dev->name, (int) readl(ioaddr + IntrStatus)); | |
1409 | return IRQ_RETVAL(handled); | |
1410 | } | |
1411 | ||
1412 | ||
1413 | /* This routine is logically part of the interrupt/poll handler, but separated | |
1414 | for clarity, code sharing between NAPI/non-NAPI, and better register allocation. */ | |
1415 | static int __netdev_rx(struct net_device *dev, int *quota) | |
1416 | { | |
1417 | struct netdev_private *np = netdev_priv(dev); | |
1418 | u32 desc_status; | |
1419 | int retcode = 0; | |
1420 | ||
1421 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
1422 | while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) { | |
1423 | struct sk_buff *skb; | |
1424 | u16 pkt_len; | |
1425 | int entry; | |
1426 | rx_done_desc *desc = &np->rx_done_q[np->rx_done]; | |
1427 | ||
1428 | if (debug > 4) | |
1429 | printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status); | |
1430 | if (!(desc_status & RxOK)) { | |
fdecea66 | 1431 | /* There was an error. */ |
1da177e4 LT |
1432 | if (debug > 2) |
1433 | printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status); | |
1434 | np->stats.rx_errors++; | |
1435 | if (desc_status & RxFIFOErr) | |
1436 | np->stats.rx_fifo_errors++; | |
1437 | goto next_rx; | |
1438 | } | |
1439 | ||
1440 | if (*quota <= 0) { /* out of rx quota */ | |
1441 | retcode = 1; | |
1442 | goto out; | |
1443 | } | |
1444 | (*quota)--; | |
1445 | ||
1446 | pkt_len = desc_status; /* Implicitly Truncate */ | |
1447 | entry = (desc_status >> 16) & 0x7ff; | |
1448 | ||
1449 | if (debug > 4) | |
1450 | printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota); | |
1451 | /* Check if the packet is long enough to accept without copying | |
1452 | to a minimally-sized skbuff. */ | |
1453 | if (pkt_len < rx_copybreak | |
1454 | && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { | |
1455 | skb->dev = dev; | |
1456 | skb_reserve(skb, 2); /* 16 byte align the IP header */ | |
1457 | pci_dma_sync_single_for_cpu(np->pci_dev, | |
1458 | np->rx_info[entry].mapping, | |
1459 | pkt_len, PCI_DMA_FROMDEVICE); | |
689be439 | 1460 | eth_copy_and_sum(skb, np->rx_info[entry].skb->data, pkt_len, 0); |
1da177e4 LT |
1461 | pci_dma_sync_single_for_device(np->pci_dev, |
1462 | np->rx_info[entry].mapping, | |
1463 | pkt_len, PCI_DMA_FROMDEVICE); | |
1464 | skb_put(skb, pkt_len); | |
1465 | } else { | |
1466 | pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
1467 | skb = np->rx_info[entry].skb; | |
1468 | skb_put(skb, pkt_len); | |
1469 | np->rx_info[entry].skb = NULL; | |
1470 | np->rx_info[entry].mapping = 0; | |
1471 | } | |
1472 | #ifndef final_version /* Remove after testing. */ | |
1473 | /* You will want this info for the initial debug. */ | |
1474 | if (debug > 5) | |
1475 | printk(KERN_DEBUG " Rx data %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:" | |
1476 | "%2.2x %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x %2.2x%2.2x.\n", | |
1477 | skb->data[0], skb->data[1], skb->data[2], skb->data[3], | |
1478 | skb->data[4], skb->data[5], skb->data[6], skb->data[7], | |
1479 | skb->data[8], skb->data[9], skb->data[10], | |
1480 | skb->data[11], skb->data[12], skb->data[13]); | |
1481 | #endif | |
1482 | ||
1483 | skb->protocol = eth_type_trans(skb, dev); | |
fdecea66 | 1484 | #ifdef VLAN_SUPPORT |
1da177e4 LT |
1485 | if (debug > 4) |
1486 | printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2)); | |
1487 | #endif | |
1da177e4 LT |
1488 | if (le16_to_cpu(desc->status2) & 0x0100) { |
1489 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1490 | np->stats.rx_compressed++; | |
1491 | } | |
1492 | /* | |
1493 | * This feature doesn't seem to be working, at least | |
1494 | * with the two firmware versions I have. If the GFP sees | |
1495 | * an IP fragment, it either ignores it completely, or reports | |
1496 | * "bad checksum" on it. | |
1497 | * | |
1498 | * Maybe I missed something -- corrections are welcome. | |
1499 | * Until then, the printk stays. :-) -Ion | |
1500 | */ | |
1501 | else if (le16_to_cpu(desc->status2) & 0x0040) { | |
84fa7933 | 1502 | skb->ip_summed = CHECKSUM_COMPLETE; |
1da177e4 LT |
1503 | skb->csum = le16_to_cpu(desc->csum); |
1504 | printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2)); | |
1505 | } | |
1da177e4 LT |
1506 | #ifdef VLAN_SUPPORT |
1507 | if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) { | |
1508 | if (debug > 4) | |
1509 | printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", le16_to_cpu(desc->vlanid)); | |
1510 | /* vlan_netdev_receive_skb() expects a packet with the VLAN tag stripped out */ | |
1511 | vlan_netdev_receive_skb(skb, np->vlgrp, le16_to_cpu(desc->vlanid) & VLAN_VID_MASK); | |
1512 | } else | |
1513 | #endif /* VLAN_SUPPORT */ | |
1514 | netdev_receive_skb(skb); | |
1515 | dev->last_rx = jiffies; | |
1516 | np->stats.rx_packets++; | |
1517 | ||
1518 | next_rx: | |
1519 | np->cur_rx++; | |
1520 | desc->status = 0; | |
1521 | np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE; | |
1522 | } | |
1523 | writew(np->rx_done, np->base + CompletionQConsumerIdx); | |
1524 | ||
1525 | out: | |
1526 | refill_rx_ring(dev); | |
1527 | if (debug > 5) | |
1528 | printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n", | |
1529 | retcode, np->rx_done, desc_status); | |
1530 | return retcode; | |
1531 | } | |
1532 | ||
1533 | ||
1534 | #ifdef HAVE_NETDEV_POLL | |
1535 | static int netdev_poll(struct net_device *dev, int *budget) | |
1536 | { | |
1537 | u32 intr_status; | |
1538 | struct netdev_private *np = netdev_priv(dev); | |
1539 | void __iomem *ioaddr = np->base; | |
1540 | int retcode = 0, quota = dev->quota; | |
1541 | ||
1542 | do { | |
1543 | writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear); | |
1544 | ||
1545 | retcode = __netdev_rx(dev, "a); | |
1546 | *budget -= (dev->quota - quota); | |
1547 | dev->quota = quota; | |
1548 | if (retcode) | |
1549 | goto out; | |
1550 | ||
1551 | intr_status = readl(ioaddr + IntrStatus); | |
1552 | } while (intr_status & (IntrRxDone | IntrRxEmpty)); | |
1553 | ||
1554 | netif_rx_complete(dev); | |
1555 | intr_status = readl(ioaddr + IntrEnable); | |
1556 | intr_status |= IntrRxDone | IntrRxEmpty; | |
1557 | writel(intr_status, ioaddr + IntrEnable); | |
1558 | ||
1559 | out: | |
1560 | if (debug > 5) | |
1561 | printk(KERN_DEBUG " exiting netdev_poll(): %d.\n", retcode); | |
1562 | ||
1563 | /* Restart Rx engine if stopped. */ | |
1564 | return retcode; | |
1565 | } | |
1566 | #endif /* HAVE_NETDEV_POLL */ | |
1567 | ||
1568 | ||
1569 | static void refill_rx_ring(struct net_device *dev) | |
1570 | { | |
1571 | struct netdev_private *np = netdev_priv(dev); | |
1572 | struct sk_buff *skb; | |
1573 | int entry = -1; | |
1574 | ||
1575 | /* Refill the Rx ring buffers. */ | |
1576 | for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { | |
1577 | entry = np->dirty_rx % RX_RING_SIZE; | |
1578 | if (np->rx_info[entry].skb == NULL) { | |
1579 | skb = dev_alloc_skb(np->rx_buf_sz); | |
1580 | np->rx_info[entry].skb = skb; | |
1581 | if (skb == NULL) | |
1582 | break; /* Better luck next round. */ | |
1583 | np->rx_info[entry].mapping = | |
689be439 | 1584 | pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE); |
1da177e4 LT |
1585 | skb->dev = dev; /* Mark as being used by this device. */ |
1586 | np->rx_ring[entry].rxaddr = | |
1587 | cpu_to_dma(np->rx_info[entry].mapping | RxDescValid); | |
1588 | } | |
1589 | if (entry == RX_RING_SIZE - 1) | |
1590 | np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing); | |
1591 | } | |
1592 | if (entry >= 0) | |
1593 | writew(entry, np->base + RxDescQIdx); | |
1594 | } | |
1595 | ||
1596 | ||
1597 | static void netdev_media_change(struct net_device *dev) | |
1598 | { | |
1599 | struct netdev_private *np = netdev_priv(dev); | |
1600 | void __iomem *ioaddr = np->base; | |
1601 | u16 reg0, reg1, reg4, reg5; | |
1602 | u32 new_tx_mode; | |
1603 | u32 new_intr_timer_ctrl; | |
1604 | ||
1605 | /* reset status first */ | |
1606 | mdio_read(dev, np->phys[0], MII_BMCR); | |
1607 | mdio_read(dev, np->phys[0], MII_BMSR); | |
1608 | ||
1609 | reg0 = mdio_read(dev, np->phys[0], MII_BMCR); | |
1610 | reg1 = mdio_read(dev, np->phys[0], MII_BMSR); | |
1611 | ||
1612 | if (reg1 & BMSR_LSTATUS) { | |
1613 | /* link is up */ | |
1614 | if (reg0 & BMCR_ANENABLE) { | |
1615 | /* autonegotiation is enabled */ | |
1616 | reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE); | |
1617 | reg5 = mdio_read(dev, np->phys[0], MII_LPA); | |
1618 | if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) { | |
1619 | np->speed100 = 1; | |
1620 | np->mii_if.full_duplex = 1; | |
1621 | } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) { | |
1622 | np->speed100 = 1; | |
1623 | np->mii_if.full_duplex = 0; | |
1624 | } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) { | |
1625 | np->speed100 = 0; | |
1626 | np->mii_if.full_duplex = 1; | |
1627 | } else { | |
1628 | np->speed100 = 0; | |
1629 | np->mii_if.full_duplex = 0; | |
1630 | } | |
1631 | } else { | |
1632 | /* autonegotiation is disabled */ | |
1633 | if (reg0 & BMCR_SPEED100) | |
1634 | np->speed100 = 1; | |
1635 | else | |
1636 | np->speed100 = 0; | |
1637 | if (reg0 & BMCR_FULLDPLX) | |
1638 | np->mii_if.full_duplex = 1; | |
1639 | else | |
1640 | np->mii_if.full_duplex = 0; | |
1641 | } | |
1642 | netif_carrier_on(dev); | |
1643 | printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n", | |
1644 | dev->name, | |
1645 | np->speed100 ? "100" : "10", | |
1646 | np->mii_if.full_duplex ? "full" : "half"); | |
1647 | ||
1648 | new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */ | |
1649 | if (np->mii_if.full_duplex) | |
1650 | new_tx_mode |= FullDuplex; | |
1651 | if (np->tx_mode != new_tx_mode) { | |
1652 | np->tx_mode = new_tx_mode; | |
1653 | writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode); | |
1654 | udelay(1000); | |
1655 | writel(np->tx_mode, ioaddr + TxMode); | |
1656 | } | |
1657 | ||
1658 | new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X; | |
1659 | if (np->speed100) | |
1660 | new_intr_timer_ctrl |= Timer10X; | |
1661 | if (np->intr_timer_ctrl != new_intr_timer_ctrl) { | |
1662 | np->intr_timer_ctrl = new_intr_timer_ctrl; | |
1663 | writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl); | |
1664 | } | |
1665 | } else { | |
1666 | netif_carrier_off(dev); | |
1667 | printk(KERN_DEBUG "%s: Link is down\n", dev->name); | |
1668 | } | |
1669 | } | |
1670 | ||
1671 | ||
1672 | static void netdev_error(struct net_device *dev, int intr_status) | |
1673 | { | |
1674 | struct netdev_private *np = netdev_priv(dev); | |
1675 | ||
1676 | /* Came close to underrunning the Tx FIFO, increase threshold. */ | |
1677 | if (intr_status & IntrTxDataLow) { | |
1678 | if (np->tx_threshold <= PKT_BUF_SZ / 16) { | |
1679 | writel(++np->tx_threshold, np->base + TxThreshold); | |
1680 | printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n", | |
1681 | dev->name, np->tx_threshold * 16); | |
1682 | } else | |
1683 | printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name); | |
1684 | } | |
1685 | if (intr_status & IntrRxGFPDead) { | |
1686 | np->stats.rx_fifo_errors++; | |
1687 | np->stats.rx_errors++; | |
1688 | } | |
1689 | if (intr_status & (IntrNoTxCsum | IntrDMAErr)) { | |
1690 | np->stats.tx_fifo_errors++; | |
1691 | np->stats.tx_errors++; | |
1692 | } | |
1693 | if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug) | |
1694 | printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n", | |
1695 | dev->name, intr_status); | |
1696 | } | |
1697 | ||
1698 | ||
1699 | static struct net_device_stats *get_stats(struct net_device *dev) | |
1700 | { | |
1701 | struct netdev_private *np = netdev_priv(dev); | |
1702 | void __iomem *ioaddr = np->base; | |
1703 | ||
1704 | /* This adapter architecture needs no SMP locks. */ | |
1705 | np->stats.tx_bytes = readl(ioaddr + 0x57010); | |
1706 | np->stats.rx_bytes = readl(ioaddr + 0x57044); | |
1707 | np->stats.tx_packets = readl(ioaddr + 0x57000); | |
1708 | np->stats.tx_aborted_errors = | |
1709 | readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028); | |
1710 | np->stats.tx_window_errors = readl(ioaddr + 0x57018); | |
1711 | np->stats.collisions = | |
1712 | readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008); | |
1713 | ||
1714 | /* The chip only need report frame silently dropped. */ | |
1715 | np->stats.rx_dropped += readw(ioaddr + RxDMAStatus); | |
1716 | writew(0, ioaddr + RxDMAStatus); | |
1717 | np->stats.rx_crc_errors = readl(ioaddr + 0x5703C); | |
1718 | np->stats.rx_frame_errors = readl(ioaddr + 0x57040); | |
1719 | np->stats.rx_length_errors = readl(ioaddr + 0x57058); | |
1720 | np->stats.rx_missed_errors = readl(ioaddr + 0x5707C); | |
1721 | ||
1722 | return &np->stats; | |
1723 | } | |
1724 | ||
1725 | ||
1da177e4 LT |
1726 | static void set_rx_mode(struct net_device *dev) |
1727 | { | |
1728 | struct netdev_private *np = netdev_priv(dev); | |
1729 | void __iomem *ioaddr = np->base; | |
1730 | u32 rx_mode = MinVLANPrio; | |
1731 | struct dev_mc_list *mclist; | |
1732 | int i; | |
1733 | #ifdef VLAN_SUPPORT | |
1734 | ||
1735 | rx_mode |= VlanMode; | |
1736 | if (np->vlgrp) { | |
1737 | int vlan_count = 0; | |
1738 | void __iomem *filter_addr = ioaddr + HashTable + 8; | |
1739 | for (i = 0; i < VLAN_VID_MASK; i++) { | |
1740 | if (np->vlgrp->vlan_devices[i]) { | |
1741 | if (vlan_count >= 32) | |
1742 | break; | |
1743 | writew(cpu_to_be16(i), filter_addr); | |
1744 | filter_addr += 16; | |
1745 | vlan_count++; | |
1746 | } | |
1747 | } | |
1748 | if (i == VLAN_VID_MASK) { | |
1749 | rx_mode |= PerfectFilterVlan; | |
1750 | while (vlan_count < 32) { | |
1751 | writew(0, filter_addr); | |
1752 | filter_addr += 16; | |
1753 | vlan_count++; | |
1754 | } | |
1755 | } | |
1756 | } | |
1757 | #endif /* VLAN_SUPPORT */ | |
1758 | ||
1759 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1760 | rx_mode |= AcceptAll; | |
1761 | } else if ((dev->mc_count > multicast_filter_limit) | |
1762 | || (dev->flags & IFF_ALLMULTI)) { | |
1763 | /* Too many to match, or accept all multicasts. */ | |
1764 | rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter; | |
1765 | } else if (dev->mc_count <= 14) { | |
1766 | /* Use the 16 element perfect filter, skip first two entries. */ | |
1767 | void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16; | |
1768 | u16 *eaddrs; | |
1769 | for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2; | |
1770 | i++, mclist = mclist->next) { | |
1771 | eaddrs = (u16 *)mclist->dmi_addr; | |
1772 | writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 4; | |
1773 | writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; | |
1774 | writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 8; | |
1775 | } | |
1776 | eaddrs = (u16 *)dev->dev_addr; | |
1777 | while (i++ < 16) { | |
1778 | writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4; | |
1779 | writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; | |
1780 | writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8; | |
1781 | } | |
1782 | rx_mode |= AcceptBroadcast|PerfectFilter; | |
1783 | } else { | |
1784 | /* Must use a multicast hash table. */ | |
1785 | void __iomem *filter_addr; | |
1786 | u16 *eaddrs; | |
1787 | u16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */ | |
1788 | ||
1789 | memset(mc_filter, 0, sizeof(mc_filter)); | |
1790 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1791 | i++, mclist = mclist->next) { | |
fdecea66 JG |
1792 | /* The chip uses the upper 9 CRC bits |
1793 | as index into the hash table */ | |
1da177e4 LT |
1794 | int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23; |
1795 | __u32 *fptr = (__u32 *) &mc_filter[(bit_nr >> 4) & ~1]; | |
1796 | ||
1797 | *fptr |= cpu_to_le32(1 << (bit_nr & 31)); | |
1798 | } | |
1799 | /* Clear the perfect filter list, skip first two entries. */ | |
1800 | filter_addr = ioaddr + PerfFilterTable + 2 * 16; | |
1801 | eaddrs = (u16 *)dev->dev_addr; | |
1802 | for (i = 2; i < 16; i++) { | |
1803 | writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4; | |
1804 | writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; | |
1805 | writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8; | |
1806 | } | |
1807 | for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++) | |
1808 | writew(mc_filter[i], filter_addr); | |
1809 | rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter; | |
1810 | } | |
1811 | writel(rx_mode, ioaddr + RxFilterMode); | |
1812 | } | |
1813 | ||
1814 | static int check_if_running(struct net_device *dev) | |
1815 | { | |
1816 | if (!netif_running(dev)) | |
1817 | return -EINVAL; | |
1818 | return 0; | |
1819 | } | |
1820 | ||
1821 | static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1822 | { | |
1823 | struct netdev_private *np = netdev_priv(dev); | |
1824 | strcpy(info->driver, DRV_NAME); | |
1825 | strcpy(info->version, DRV_VERSION); | |
fdecea66 | 1826 | strcpy(info->bus_info, pci_name(np->pci_dev)); |
1da177e4 LT |
1827 | } |
1828 | ||
1829 | static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1830 | { | |
1831 | struct netdev_private *np = netdev_priv(dev); | |
1832 | spin_lock_irq(&np->lock); | |
1833 | mii_ethtool_gset(&np->mii_if, ecmd); | |
1834 | spin_unlock_irq(&np->lock); | |
1835 | return 0; | |
1836 | } | |
1837 | ||
1838 | static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1839 | { | |
1840 | struct netdev_private *np = netdev_priv(dev); | |
1841 | int res; | |
1842 | spin_lock_irq(&np->lock); | |
1843 | res = mii_ethtool_sset(&np->mii_if, ecmd); | |
1844 | spin_unlock_irq(&np->lock); | |
1845 | check_duplex(dev); | |
1846 | return res; | |
1847 | } | |
1848 | ||
1849 | static int nway_reset(struct net_device *dev) | |
1850 | { | |
1851 | struct netdev_private *np = netdev_priv(dev); | |
1852 | return mii_nway_restart(&np->mii_if); | |
1853 | } | |
1854 | ||
1855 | static u32 get_link(struct net_device *dev) | |
1856 | { | |
1857 | struct netdev_private *np = netdev_priv(dev); | |
1858 | return mii_link_ok(&np->mii_if); | |
1859 | } | |
1860 | ||
1861 | static u32 get_msglevel(struct net_device *dev) | |
1862 | { | |
1863 | return debug; | |
1864 | } | |
1865 | ||
1866 | static void set_msglevel(struct net_device *dev, u32 val) | |
1867 | { | |
1868 | debug = val; | |
1869 | } | |
1870 | ||
1871 | static struct ethtool_ops ethtool_ops = { | |
1872 | .begin = check_if_running, | |
1873 | .get_drvinfo = get_drvinfo, | |
1874 | .get_settings = get_settings, | |
1875 | .set_settings = set_settings, | |
1876 | .nway_reset = nway_reset, | |
1877 | .get_link = get_link, | |
1878 | .get_msglevel = get_msglevel, | |
1879 | .set_msglevel = set_msglevel, | |
1880 | }; | |
1881 | ||
1882 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1883 | { | |
1884 | struct netdev_private *np = netdev_priv(dev); | |
1885 | struct mii_ioctl_data *data = if_mii(rq); | |
1886 | int rc; | |
1887 | ||
1888 | if (!netif_running(dev)) | |
1889 | return -EINVAL; | |
1890 | ||
1891 | spin_lock_irq(&np->lock); | |
1892 | rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL); | |
1893 | spin_unlock_irq(&np->lock); | |
1894 | ||
1895 | if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0])) | |
1896 | check_duplex(dev); | |
1897 | ||
1898 | return rc; | |
1899 | } | |
1900 | ||
1901 | static int netdev_close(struct net_device *dev) | |
1902 | { | |
1903 | struct netdev_private *np = netdev_priv(dev); | |
1904 | void __iomem *ioaddr = np->base; | |
1905 | int i; | |
1906 | ||
1907 | netif_stop_queue(dev); | |
1da177e4 LT |
1908 | |
1909 | if (debug > 1) { | |
1910 | printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n", | |
1911 | dev->name, (int) readl(ioaddr + IntrStatus)); | |
1912 | printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", | |
1913 | dev->name, np->cur_tx, np->dirty_tx, | |
1914 | np->cur_rx, np->dirty_rx); | |
1915 | } | |
1916 | ||
1917 | /* Disable interrupts by clearing the interrupt mask. */ | |
1918 | writel(0, ioaddr + IntrEnable); | |
1919 | ||
1920 | /* Stop the chip's Tx and Rx processes. */ | |
1921 | writel(0, ioaddr + GenCtrl); | |
1922 | readl(ioaddr + GenCtrl); | |
1923 | ||
1924 | if (debug > 5) { | |
1925 | printk(KERN_DEBUG" Tx ring at %#llx:\n", | |
1926 | (long long) np->tx_ring_dma); | |
1927 | for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++) | |
1928 | printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n", | |
1929 | i, le32_to_cpu(np->tx_ring[i].status), | |
1930 | (long long) dma_to_cpu(np->tx_ring[i].addr), | |
1931 | le32_to_cpu(np->tx_done_q[i].status)); | |
1932 | printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n", | |
1933 | (long long) np->rx_ring_dma, np->rx_done_q); | |
1934 | if (np->rx_done_q) | |
1935 | for (i = 0; i < 8 /* RX_RING_SIZE */; i++) { | |
1936 | printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n", | |
1937 | i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status)); | |
1938 | } | |
1939 | } | |
1940 | ||
1941 | free_irq(dev->irq, dev); | |
1942 | ||
1943 | /* Free all the skbuffs in the Rx queue. */ | |
1944 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1945 | np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */ | |
1946 | if (np->rx_info[i].skb != NULL) { | |
1947 | pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
1948 | dev_kfree_skb(np->rx_info[i].skb); | |
1949 | } | |
1950 | np->rx_info[i].skb = NULL; | |
1951 | np->rx_info[i].mapping = 0; | |
1952 | } | |
1953 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1954 | struct sk_buff *skb = np->tx_info[i].skb; | |
1955 | if (skb == NULL) | |
1956 | continue; | |
1957 | pci_unmap_single(np->pci_dev, | |
1958 | np->tx_info[i].mapping, | |
1959 | skb_first_frag_len(skb), PCI_DMA_TODEVICE); | |
1960 | np->tx_info[i].mapping = 0; | |
1961 | dev_kfree_skb(skb); | |
1962 | np->tx_info[i].skb = NULL; | |
1963 | } | |
1964 | ||
1965 | return 0; | |
1966 | } | |
1967 | ||
d4fbeabb SR |
1968 | #ifdef CONFIG_PM |
1969 | static int starfire_suspend(struct pci_dev *pdev, pm_message_t state) | |
1970 | { | |
1971 | struct net_device *dev = pci_get_drvdata(pdev); | |
1972 | ||
1973 | if (netif_running(dev)) { | |
1974 | netif_device_detach(dev); | |
1975 | netdev_close(dev); | |
1976 | } | |
1977 | ||
1978 | pci_save_state(pdev); | |
1979 | pci_set_power_state(pdev, pci_choose_state(pdev,state)); | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
1984 | static int starfire_resume(struct pci_dev *pdev) | |
1985 | { | |
1986 | struct net_device *dev = pci_get_drvdata(pdev); | |
1987 | ||
1988 | pci_set_power_state(pdev, PCI_D0); | |
1989 | pci_restore_state(pdev); | |
1990 | ||
1991 | if (netif_running(dev)) { | |
1992 | netdev_open(dev); | |
1993 | netif_device_attach(dev); | |
1994 | } | |
1995 | ||
1996 | return 0; | |
1997 | } | |
1998 | #endif /* CONFIG_PM */ | |
1999 | ||
1da177e4 LT |
2000 | |
2001 | static void __devexit starfire_remove_one (struct pci_dev *pdev) | |
2002 | { | |
2003 | struct net_device *dev = pci_get_drvdata(pdev); | |
2004 | struct netdev_private *np = netdev_priv(dev); | |
2005 | ||
5d9428de | 2006 | BUG_ON(!dev); |
1da177e4 LT |
2007 | |
2008 | unregister_netdev(dev); | |
2009 | ||
2010 | if (np->queue_mem) | |
2011 | pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma); | |
2012 | ||
2013 | ||
2014 | /* XXX: add wakeup code -- requires firmware for MagicPacket */ | |
2015 | pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */ | |
2016 | pci_disable_device(pdev); | |
2017 | ||
2018 | iounmap(np->base); | |
2019 | pci_release_regions(pdev); | |
2020 | ||
2021 | pci_set_drvdata(pdev, NULL); | |
2022 | free_netdev(dev); /* Will also free np!! */ | |
2023 | } | |
2024 | ||
2025 | ||
2026 | static struct pci_driver starfire_driver = { | |
2027 | .name = DRV_NAME, | |
2028 | .probe = starfire_init_one, | |
2029 | .remove = __devexit_p(starfire_remove_one), | |
d4fbeabb SR |
2030 | #ifdef CONFIG_PM |
2031 | .suspend = starfire_suspend, | |
2032 | .resume = starfire_resume, | |
2033 | #endif /* CONFIG_PM */ | |
1da177e4 LT |
2034 | .id_table = starfire_pci_tbl, |
2035 | }; | |
2036 | ||
2037 | ||
2038 | static int __init starfire_init (void) | |
2039 | { | |
2040 | /* when a module, this is printed whether or not devices are found in probe */ | |
2041 | #ifdef MODULE | |
2042 | printk(version); | |
fdecea66 JG |
2043 | #ifdef HAVE_NETDEV_POLL |
2044 | printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n"); | |
2045 | #else | |
2046 | printk(KERN_INFO DRV_NAME ": polling (NAPI) disabled\n"); | |
1da177e4 | 2047 | #endif |
fdecea66 JG |
2048 | #endif |
2049 | ||
1da177e4 | 2050 | /* we can do this test only at run-time... sigh */ |
67974231 IB |
2051 | if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) { |
2052 | printk("This driver has dma_addr_t issues, please send email to maintainer\n"); | |
1da177e4 LT |
2053 | return -ENODEV; |
2054 | } | |
67974231 | 2055 | |
1da177e4 LT |
2056 | return pci_module_init (&starfire_driver); |
2057 | } | |
2058 | ||
2059 | ||
2060 | static void __exit starfire_cleanup (void) | |
2061 | { | |
2062 | pci_unregister_driver (&starfire_driver); | |
2063 | } | |
2064 | ||
2065 | ||
2066 | module_init(starfire_init); | |
2067 | module_exit(starfire_cleanup); | |
2068 | ||
2069 | ||
2070 | /* | |
2071 | * Local variables: | |
2072 | * c-basic-offset: 8 | |
2073 | * tab-width: 8 | |
2074 | * End: | |
2075 | */ |