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47dd7a54 GC |
1 | /******************************************************************************* |
2 | Copyright (C) 2007-2009 STMicroelectronics Ltd | |
3 | ||
4 | This program is free software; you can redistribute it and/or modify it | |
5 | under the terms and conditions of the GNU General Public License, | |
6 | version 2, as published by the Free Software Foundation. | |
7 | ||
8 | This program is distributed in the hope it will be useful, but WITHOUT | |
9 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | more details. | |
12 | ||
13 | You should have received a copy of the GNU General Public License along with | |
14 | this program; if not, write to the Free Software Foundation, Inc., | |
15 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
16 | ||
17 | The full GNU General Public License is included in this distribution in | |
18 | the file called "COPYING". | |
19 | ||
20 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
21 | *******************************************************************************/ | |
22 | ||
23 | #define GMAC_CONTROL 0x00000000 /* Configuration */ | |
24 | #define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ | |
25 | #define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ | |
26 | #define GMAC_HASH_LOW 0x0000000c /* Multicast Hash Table Low */ | |
27 | #define GMAC_MII_ADDR 0x00000010 /* MII Address */ | |
28 | #define GMAC_MII_DATA 0x00000014 /* MII Data */ | |
29 | #define GMAC_FLOW_CTRL 0x00000018 /* Flow Control */ | |
30 | #define GMAC_VLAN_TAG 0x0000001c /* VLAN Tag */ | |
31 | #define GMAC_VERSION 0x00000020 /* GMAC CORE Version */ | |
32 | #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ | |
33 | ||
34 | #define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ | |
35 | enum gmac_irq_status { | |
36 | time_stamp_irq = 0x0200, | |
37 | mmc_rx_csum_offload_irq = 0x0080, | |
38 | mmc_tx_irq = 0x0040, | |
39 | mmc_rx_irq = 0x0020, | |
40 | mmc_irq = 0x0010, | |
41 | pmt_irq = 0x0008, | |
42 | pcs_ane_irq = 0x0004, | |
43 | pcs_link_irq = 0x0002, | |
44 | rgmii_irq = 0x0001, | |
45 | }; | |
46 | #define GMAC_INT_MASK 0x0000003c /* interrupt mask register */ | |
47 | ||
48 | /* PMT Control and Status */ | |
49 | #define GMAC_PMT 0x0000002c | |
50 | enum power_event { | |
51 | pointer_reset = 0x80000000, | |
52 | global_unicast = 0x00000200, | |
53 | wake_up_rx_frame = 0x00000040, | |
54 | magic_frame = 0x00000020, | |
55 | wake_up_frame_en = 0x00000004, | |
56 | magic_pkt_en = 0x00000002, | |
57 | power_down = 0x00000001, | |
58 | }; | |
59 | ||
60 | /* GMAC HW ADDR regs */ | |
61 | #define GMAC_ADDR_HIGH(reg) (0x00000040+(reg * 8)) | |
62 | #define GMAC_ADDR_LOW(reg) (0x00000044+(reg * 8)) | |
63 | #define GMAC_MAX_UNICAST_ADDRESSES 16 | |
64 | ||
65 | #define GMAC_AN_CTRL 0x000000c0 /* AN control */ | |
66 | #define GMAC_AN_STATUS 0x000000c4 /* AN status */ | |
67 | #define GMAC_ANE_ADV 0x000000c8 /* Auto-Neg. Advertisement */ | |
68 | #define GMAC_ANE_LINK 0x000000cc /* Auto-Neg. link partener ability */ | |
69 | #define GMAC_ANE_EXP 0x000000d0 /* ANE expansion */ | |
70 | #define GMAC_TBI 0x000000d4 /* TBI extend status */ | |
71 | #define GMAC_GMII_STATUS 0x000000d8 /* S/R-GMII status */ | |
72 | ||
73 | /* GMAC Configuration defines */ | |
74 | #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */ | |
75 | #define GMAC_CONTROL_WD 0x00800000 /* Disable Watchdog on receive */ | |
76 | #define GMAC_CONTROL_JD 0x00400000 /* Jabber disable */ | |
77 | #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */ | |
78 | #define GMAC_CONTROL_JE 0x00100000 /* Jumbo frame */ | |
79 | enum inter_frame_gap { | |
80 | GMAC_CONTROL_IFG_88 = 0x00040000, | |
81 | GMAC_CONTROL_IFG_80 = 0x00020000, | |
82 | GMAC_CONTROL_IFG_40 = 0x000e0000, | |
83 | }; | |
84 | #define GMAC_CONTROL_DCRS 0x00010000 /* Disable carrier sense during tx */ | |
85 | #define GMAC_CONTROL_PS 0x00008000 /* Port Select 0:GMI 1:MII */ | |
86 | #define GMAC_CONTROL_FES 0x00004000 /* Speed 0:10 1:100 */ | |
87 | #define GMAC_CONTROL_DO 0x00002000 /* Disable Rx Own */ | |
88 | #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */ | |
89 | #define GMAC_CONTROL_DM 0x00000800 /* Duplex Mode */ | |
90 | #define GMAC_CONTROL_IPC 0x00000400 /* Checksum Offload */ | |
91 | #define GMAC_CONTROL_DR 0x00000200 /* Disable Retry */ | |
92 | #define GMAC_CONTROL_LUD 0x00000100 /* Link up/down */ | |
93 | #define GMAC_CONTROL_ACS 0x00000080 /* Automatic Pad Stripping */ | |
94 | #define GMAC_CONTROL_DC 0x00000010 /* Deferral Check */ | |
95 | #define GMAC_CONTROL_TE 0x00000008 /* Transmitter Enable */ | |
96 | #define GMAC_CONTROL_RE 0x00000004 /* Receiver Enable */ | |
97 | ||
98 | #define GMAC_CORE_INIT (GMAC_CONTROL_JD | GMAC_CONTROL_PS | GMAC_CONTROL_ACS | \ | |
99 | GMAC_CONTROL_IPC | GMAC_CONTROL_JE | GMAC_CONTROL_BE) | |
100 | ||
101 | /* GMAC Frame Filter defines */ | |
102 | #define GMAC_FRAME_FILTER_PR 0x00000001 /* Promiscuous Mode */ | |
103 | #define GMAC_FRAME_FILTER_HUC 0x00000002 /* Hash Unicast */ | |
104 | #define GMAC_FRAME_FILTER_HMC 0x00000004 /* Hash Multicast */ | |
105 | #define GMAC_FRAME_FILTER_DAIF 0x00000008 /* DA Inverse Filtering */ | |
106 | #define GMAC_FRAME_FILTER_PM 0x00000010 /* Pass all multicast */ | |
107 | #define GMAC_FRAME_FILTER_DBF 0x00000020 /* Disable Broadcast frames */ | |
108 | #define GMAC_FRAME_FILTER_SAIF 0x00000100 /* Inverse Filtering */ | |
109 | #define GMAC_FRAME_FILTER_SAF 0x00000200 /* Source Address Filter */ | |
110 | #define GMAC_FRAME_FILTER_HPF 0x00000400 /* Hash or perfect Filter */ | |
111 | #define GMAC_FRAME_FILTER_RA 0x80000000 /* Receive all mode */ | |
112 | /* GMII ADDR defines */ | |
113 | #define GMAC_MII_ADDR_WRITE 0x00000002 /* MII Write */ | |
114 | #define GMAC_MII_ADDR_BUSY 0x00000001 /* MII Busy */ | |
115 | /* GMAC FLOW CTRL defines */ | |
116 | #define GMAC_FLOW_CTRL_PT_MASK 0xffff0000 /* Pause Time Mask */ | |
117 | #define GMAC_FLOW_CTRL_PT_SHIFT 16 | |
118 | #define GMAC_FLOW_CTRL_RFE 0x00000004 /* Rx Flow Control Enable */ | |
119 | #define GMAC_FLOW_CTRL_TFE 0x00000002 /* Tx Flow Control Enable */ | |
120 | #define GMAC_FLOW_CTRL_FCB_BPA 0x00000001 /* Flow Control Busy ... */ | |
121 | ||
122 | /*--- DMA BLOCK defines ---*/ | |
123 | /* DMA Bus Mode register defines */ | |
124 | #define DMA_BUS_MODE_SFT_RESET 0x00000001 /* Software Reset */ | |
125 | #define DMA_BUS_MODE_DA 0x00000002 /* Arbitration scheme */ | |
126 | #define DMA_BUS_MODE_DSL_MASK 0x0000007c /* Descriptor Skip Length */ | |
127 | #define DMA_BUS_MODE_DSL_SHIFT 2 /* (in DWORDS) */ | |
128 | /* Programmable burst length (passed thorugh platform)*/ | |
129 | #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */ | |
130 | #define DMA_BUS_MODE_PBL_SHIFT 8 | |
131 | ||
132 | enum rx_tx_priority_ratio { | |
133 | double_ratio = 0x00004000, /*2:1 */ | |
134 | triple_ratio = 0x00008000, /*3:1 */ | |
135 | quadruple_ratio = 0x0000c000, /*4:1 */ | |
136 | }; | |
137 | ||
138 | #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */ | |
139 | #define DMA_BUS_MODE_RPBL_MASK 0x003e0000 /* Rx-Programmable Burst Len */ | |
140 | #define DMA_BUS_MODE_RPBL_SHIFT 17 | |
141 | #define DMA_BUS_MODE_USP 0x00800000 | |
142 | #define DMA_BUS_MODE_4PBL 0x01000000 | |
143 | #define DMA_BUS_MODE_AAL 0x02000000 | |
144 | ||
145 | /* DMA CRS Control and Status Register Mapping */ | |
146 | #define DMA_HOST_TX_DESC 0x00001048 /* Current Host Tx descriptor */ | |
147 | #define DMA_HOST_RX_DESC 0x0000104c /* Current Host Rx descriptor */ | |
148 | /* DMA Bus Mode register defines */ | |
149 | #define DMA_BUS_PR_RATIO_MASK 0x0000c000 /* Rx/Tx priority ratio */ | |
150 | #define DMA_BUS_PR_RATIO_SHIFT 14 | |
151 | #define DMA_BUS_FB 0x00010000 /* Fixed Burst */ | |
152 | ||
153 | /* DMA operation mode defines (start/stop tx/rx are placed in common header)*/ | |
154 | #define DMA_CONTROL_DT 0x04000000 /* Disable Drop TCP/IP csum error */ | |
155 | #define DMA_CONTROL_RSF 0x02000000 /* Receive Store and Forward */ | |
156 | #define DMA_CONTROL_DFF 0x01000000 /* Disaable flushing */ | |
157 | /* Theshold for Activating the FC */ | |
158 | enum rfa { | |
159 | act_full_minus_1 = 0x00800000, | |
160 | act_full_minus_2 = 0x00800200, | |
161 | act_full_minus_3 = 0x00800400, | |
162 | act_full_minus_4 = 0x00800600, | |
163 | }; | |
164 | /* Theshold for Deactivating the FC */ | |
165 | enum rfd { | |
166 | deac_full_minus_1 = 0x00400000, | |
167 | deac_full_minus_2 = 0x00400800, | |
168 | deac_full_minus_3 = 0x00401000, | |
169 | deac_full_minus_4 = 0x00401800, | |
170 | }; | |
171 | #define DMA_CONTROL_TSF 0x00200000 /* Transmit Store and Forward */ | |
172 | #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */ | |
173 | ||
174 | enum ttc_control { | |
175 | DMA_CONTROL_TTC_64 = 0x00000000, | |
176 | DMA_CONTROL_TTC_128 = 0x00004000, | |
177 | DMA_CONTROL_TTC_192 = 0x00008000, | |
178 | DMA_CONTROL_TTC_256 = 0x0000c000, | |
179 | DMA_CONTROL_TTC_40 = 0x00010000, | |
180 | DMA_CONTROL_TTC_32 = 0x00014000, | |
181 | DMA_CONTROL_TTC_24 = 0x00018000, | |
182 | DMA_CONTROL_TTC_16 = 0x0001c000, | |
183 | }; | |
184 | #define DMA_CONTROL_TC_TX_MASK 0xfffe3fff | |
185 | ||
186 | #define DMA_CONTROL_EFC 0x00000100 | |
187 | #define DMA_CONTROL_FEF 0x00000080 | |
188 | #define DMA_CONTROL_FUF 0x00000040 | |
189 | ||
190 | enum rtc_control { | |
191 | DMA_CONTROL_RTC_64 = 0x00000000, | |
192 | DMA_CONTROL_RTC_32 = 0x00000008, | |
193 | DMA_CONTROL_RTC_96 = 0x00000010, | |
194 | DMA_CONTROL_RTC_128 = 0x00000018, | |
195 | }; | |
196 | #define DMA_CONTROL_TC_RX_MASK 0xffffffe7 | |
197 | ||
198 | #define DMA_CONTROL_OSF 0x00000004 /* Operate on second frame */ | |
199 | ||
200 | /* MMC registers offset */ | |
201 | #define GMAC_MMC_CTRL 0x100 | |
202 | #define GMAC_MMC_RX_INTR 0x104 | |
203 | #define GMAC_MMC_TX_INTR 0x108 | |
204 | #define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 |