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1da177e4 LT |
1 | /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */ |
2 | /* | |
3 | Written 1999-2000 by Donald Becker. | |
4 | ||
5 | This software may be used and distributed according to the terms of | |
6 | the GNU General Public License (GPL), incorporated herein by reference. | |
7 | Drivers based on or derived from this code fall under the GPL and must | |
8 | retain the authorship, copyright and license notice. This file is not | |
9 | a complete program and may only be used when the entire operating | |
10 | system is licensed under the GPL. | |
11 | ||
12 | The author may be reached as becker@scyld.com, or C/O | |
13 | Scyld Computing Corporation | |
14 | 410 Severn Ave., Suite 210 | |
15 | Annapolis MD 21403 | |
16 | ||
17 | Support and updates available at | |
18 | http://www.scyld.com/network/sundance.html | |
03a8c661 | 19 | [link no longer provides useful info -jgarzik] |
e714d99c PDM |
20 | Archives of the mailing list are still available at |
21 | http://www.beowulf.org/pipermail/netdrivers/ | |
1da177e4 | 22 | |
1da177e4 LT |
23 | */ |
24 | ||
25 | #define DRV_NAME "sundance" | |
d5b20697 AG |
26 | #define DRV_VERSION "1.2" |
27 | #define DRV_RELDATE "11-Sep-2006" | |
1da177e4 LT |
28 | |
29 | ||
30 | /* The user-configurable values. | |
31 | These may be modified when a driver module is loaded.*/ | |
32 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
33 | /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). | |
34 | Typical is a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 35 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
36 | |
37 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
38 | Setting to > 1518 effectively disables this feature. | |
39 | This chip can receive into offset buffers, so the Alpha does not | |
40 | need a copy-align. */ | |
41 | static int rx_copybreak; | |
42 | static int flowctrl=1; | |
43 | ||
44 | /* media[] specifies the media type the NIC operates at. | |
45 | autosense Autosensing active media. | |
46 | 10mbps_hd 10Mbps half duplex. | |
47 | 10mbps_fd 10Mbps full duplex. | |
48 | 100mbps_hd 100Mbps half duplex. | |
49 | 100mbps_fd 100Mbps full duplex. | |
50 | 0 Autosensing active media. | |
51 | 1 10Mbps half duplex. | |
52 | 2 10Mbps full duplex. | |
53 | 3 100Mbps half duplex. | |
54 | 4 100Mbps full duplex. | |
55 | */ | |
56 | #define MAX_UNITS 8 | |
57 | static char *media[MAX_UNITS]; | |
58 | ||
59 | ||
60 | /* Operational parameters that are set at compile time. */ | |
61 | ||
62 | /* Keep the ring sizes a power of two for compile efficiency. | |
63 | The compiler will convert <unsigned>'%'<2^N> into a bit mask. | |
64 | Making the Tx ring too large decreases the effectiveness of channel | |
65 | bonding and packet priority, and more than 128 requires modifying the | |
66 | Tx error recovery. | |
67 | Large receive rings merely waste memory. */ | |
68 | #define TX_RING_SIZE 32 | |
69 | #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */ | |
70 | #define RX_RING_SIZE 64 | |
71 | #define RX_BUDGET 32 | |
72 | #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc) | |
73 | #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc) | |
74 | ||
75 | /* Operational parameters that usually are not changed. */ | |
76 | /* Time in jiffies before concluding the transmitter is hung. */ | |
77 | #define TX_TIMEOUT (4*HZ) | |
78 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
79 | ||
80 | /* Include files, designed to support most kernel versions 2.0.0 and later. */ | |
81 | #include <linux/module.h> | |
82 | #include <linux/kernel.h> | |
83 | #include <linux/string.h> | |
84 | #include <linux/timer.h> | |
85 | #include <linux/errno.h> | |
86 | #include <linux/ioport.h> | |
87 | #include <linux/slab.h> | |
88 | #include <linux/interrupt.h> | |
89 | #include <linux/pci.h> | |
90 | #include <linux/netdevice.h> | |
91 | #include <linux/etherdevice.h> | |
92 | #include <linux/skbuff.h> | |
93 | #include <linux/init.h> | |
94 | #include <linux/bitops.h> | |
95 | #include <asm/uaccess.h> | |
96 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
97 | #include <asm/io.h> | |
98 | #include <linux/delay.h> | |
99 | #include <linux/spinlock.h> | |
100 | #ifndef _COMPAT_WITH_OLD_KERNEL | |
101 | #include <linux/crc32.h> | |
102 | #include <linux/ethtool.h> | |
103 | #include <linux/mii.h> | |
104 | #else | |
105 | #include "crc32.h" | |
106 | #include "ethtool.h" | |
107 | #include "mii.h" | |
108 | #include "compat.h" | |
109 | #endif | |
110 | ||
111 | /* These identify the driver base version and may not be removed. */ | |
3418e469 | 112 | static char version[] = |
2c2a8c53 | 113 | KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"; |
1da177e4 LT |
114 | |
115 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
116 | MODULE_DESCRIPTION("Sundance Alta Ethernet driver"); | |
117 | MODULE_LICENSE("GPL"); | |
118 | ||
119 | module_param(debug, int, 0); | |
120 | module_param(rx_copybreak, int, 0); | |
121 | module_param_array(media, charp, NULL, 0); | |
122 | module_param(flowctrl, int, 0); | |
123 | MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)"); | |
124 | MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames"); | |
125 | MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]"); | |
126 | ||
127 | /* | |
128 | Theory of Operation | |
129 | ||
130 | I. Board Compatibility | |
131 | ||
132 | This driver is designed for the Sundance Technologies "Alta" ST201 chip. | |
133 | ||
134 | II. Board-specific settings | |
135 | ||
136 | III. Driver operation | |
137 | ||
138 | IIIa. Ring buffers | |
139 | ||
140 | This driver uses two statically allocated fixed-size descriptor lists | |
141 | formed into rings by a branch from the final descriptor to the beginning of | |
142 | the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. | |
143 | Some chips explicitly use only 2^N sized rings, while others use a | |
144 | 'next descriptor' pointer that the driver forms into rings. | |
145 | ||
146 | IIIb/c. Transmit/Receive Structure | |
147 | ||
148 | This driver uses a zero-copy receive and transmit scheme. | |
149 | The driver allocates full frame size skbuffs for the Rx ring buffers at | |
150 | open() time and passes the skb->data field to the chip as receive data | |
151 | buffers. When an incoming frame is less than RX_COPYBREAK bytes long, | |
152 | a fresh skbuff is allocated and the frame is copied to the new skbuff. | |
153 | When the incoming frame is larger, the skbuff is passed directly up the | |
154 | protocol stack. Buffers consumed this way are replaced by newly allocated | |
155 | skbuffs in a later phase of receives. | |
156 | ||
157 | The RX_COPYBREAK value is chosen to trade-off the memory wasted by | |
158 | using a full-sized skbuff for small frames vs. the copying costs of larger | |
159 | frames. New boards are typically used in generously configured machines | |
160 | and the underfilled buffers have negligible impact compared to the benefit of | |
161 | a single allocation size, so the default value of zero results in never | |
162 | copying packets. When copying is done, the cost is usually mitigated by using | |
163 | a combined copy/checksum routine. Copying also preloads the cache, which is | |
164 | most useful with small frames. | |
165 | ||
166 | A subtle aspect of the operation is that the IP header at offset 14 in an | |
167 | ethernet frame isn't longword aligned for further processing. | |
168 | Unaligned buffers are permitted by the Sundance hardware, so | |
169 | frames are received into the skbuff at an offset of "+2", 16-byte aligning | |
170 | the IP header. | |
171 | ||
172 | IIId. Synchronization | |
173 | ||
174 | The driver runs as two independent, single-threaded flows of control. One | |
175 | is the send-packet routine, which enforces single-threaded use by the | |
176 | dev->tbusy flag. The other thread is the interrupt handler, which is single | |
177 | threaded by the hardware and interrupt handling software. | |
178 | ||
179 | The send packet thread has partial control over the Tx ring and 'dev->tbusy' | |
180 | flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next | |
181 | queue slot is empty, it clears the tbusy flag when finished otherwise it sets | |
182 | the 'lp->tx_full' flag. | |
183 | ||
184 | The interrupt handler has exclusive control over the Rx ring and records stats | |
185 | from the Tx ring. After reaping the stats, it marks the Tx queue entry as | |
186 | empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it | |
187 | clears both the tx_full and tbusy flags. | |
188 | ||
189 | IV. Notes | |
190 | ||
191 | IVb. References | |
192 | ||
193 | The Sundance ST201 datasheet, preliminary version. | |
b71b95ef PDM |
194 | The Kendin KS8723 datasheet, preliminary version. |
195 | The ICplus IP100 datasheet, preliminary version. | |
196 | http://www.scyld.com/expert/100mbps.html | |
197 | http://www.scyld.com/expert/NWay.html | |
1da177e4 LT |
198 | |
199 | IVc. Errata | |
200 | ||
201 | */ | |
202 | ||
203 | /* Work-around for Kendin chip bugs. */ | |
204 | #ifndef CONFIG_SUNDANCE_MMIO | |
205 | #define USE_IO_OPS 1 | |
206 | #endif | |
207 | ||
46009c8b JG |
208 | static const struct pci_device_id sundance_pci_tbl[] = { |
209 | { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 }, | |
210 | { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 }, | |
211 | { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 }, | |
212 | { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 }, | |
213 | { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, | |
214 | { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 }, | |
215 | { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 }, | |
216 | { } | |
1da177e4 LT |
217 | }; |
218 | MODULE_DEVICE_TABLE(pci, sundance_pci_tbl); | |
219 | ||
220 | enum { | |
221 | netdev_io_size = 128 | |
222 | }; | |
223 | ||
224 | struct pci_id_info { | |
225 | const char *name; | |
226 | }; | |
46009c8b | 227 | static const struct pci_id_info pci_id_tbl[] __devinitdata = { |
1da177e4 LT |
228 | {"D-Link DFE-550TX FAST Ethernet Adapter"}, |
229 | {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"}, | |
230 | {"D-Link DFE-580TX 4 port Server Adapter"}, | |
231 | {"D-Link DFE-530TXS FAST Ethernet Adapter"}, | |
232 | {"D-Link DL10050-based FAST Ethernet Adapter"}, | |
233 | {"Sundance Technology Alta"}, | |
1668b19f | 234 | {"IC Plus Corporation IP100A FAST Ethernet Adapter"}, |
46009c8b | 235 | { } /* terminate list. */ |
1da177e4 LT |
236 | }; |
237 | ||
238 | /* This driver was written to use PCI memory space, however x86-oriented | |
239 | hardware often uses I/O space accesses. */ | |
240 | ||
241 | /* Offsets to the device registers. | |
242 | Unlike software-only systems, device drivers interact with complex hardware. | |
243 | It's not useful to define symbolic names for every register bit in the | |
244 | device. The name can only partially document the semantics and make | |
245 | the driver longer and more difficult to read. | |
246 | In general, only the important configuration values or bits changed | |
247 | multiple times should be defined symbolically. | |
248 | */ | |
249 | enum alta_offsets { | |
250 | DMACtrl = 0x00, | |
251 | TxListPtr = 0x04, | |
252 | TxDMABurstThresh = 0x08, | |
253 | TxDMAUrgentThresh = 0x09, | |
254 | TxDMAPollPeriod = 0x0a, | |
255 | RxDMAStatus = 0x0c, | |
256 | RxListPtr = 0x10, | |
257 | DebugCtrl0 = 0x1a, | |
258 | DebugCtrl1 = 0x1c, | |
259 | RxDMABurstThresh = 0x14, | |
260 | RxDMAUrgentThresh = 0x15, | |
261 | RxDMAPollPeriod = 0x16, | |
262 | LEDCtrl = 0x1a, | |
263 | ASICCtrl = 0x30, | |
264 | EEData = 0x34, | |
265 | EECtrl = 0x36, | |
1da177e4 LT |
266 | FlashAddr = 0x40, |
267 | FlashData = 0x44, | |
268 | TxStatus = 0x46, | |
269 | TxFrameId = 0x47, | |
270 | DownCounter = 0x18, | |
271 | IntrClear = 0x4a, | |
272 | IntrEnable = 0x4c, | |
273 | IntrStatus = 0x4e, | |
274 | MACCtrl0 = 0x50, | |
275 | MACCtrl1 = 0x52, | |
276 | StationAddr = 0x54, | |
277 | MaxFrameSize = 0x5A, | |
278 | RxMode = 0x5c, | |
279 | MIICtrl = 0x5e, | |
280 | MulticastFilter0 = 0x60, | |
281 | MulticastFilter1 = 0x64, | |
282 | RxOctetsLow = 0x68, | |
283 | RxOctetsHigh = 0x6a, | |
284 | TxOctetsLow = 0x6c, | |
285 | TxOctetsHigh = 0x6e, | |
286 | TxFramesOK = 0x70, | |
287 | RxFramesOK = 0x72, | |
288 | StatsCarrierError = 0x74, | |
289 | StatsLateColl = 0x75, | |
290 | StatsMultiColl = 0x76, | |
291 | StatsOneColl = 0x77, | |
292 | StatsTxDefer = 0x78, | |
293 | RxMissed = 0x79, | |
294 | StatsTxXSDefer = 0x7a, | |
295 | StatsTxAbort = 0x7b, | |
296 | StatsBcastTx = 0x7c, | |
297 | StatsBcastRx = 0x7d, | |
298 | StatsMcastTx = 0x7e, | |
299 | StatsMcastRx = 0x7f, | |
300 | /* Aliased and bogus values! */ | |
301 | RxStatus = 0x0c, | |
302 | }; | |
303 | enum ASICCtrl_HiWord_bit { | |
304 | GlobalReset = 0x0001, | |
305 | RxReset = 0x0002, | |
306 | TxReset = 0x0004, | |
307 | DMAReset = 0x0008, | |
308 | FIFOReset = 0x0010, | |
309 | NetworkReset = 0x0020, | |
310 | HostReset = 0x0040, | |
311 | ResetBusy = 0x0400, | |
312 | }; | |
313 | ||
314 | /* Bits in the interrupt status/mask registers. */ | |
315 | enum intr_status_bits { | |
316 | IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008, | |
317 | IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020, | |
318 | IntrDrvRqst=0x0040, | |
319 | StatsMax=0x0080, LinkChange=0x0100, | |
320 | IntrTxDMADone=0x0200, IntrRxDMADone=0x0400, | |
321 | }; | |
322 | ||
323 | /* Bits in the RxMode register. */ | |
324 | enum rx_mode_bits { | |
325 | AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08, | |
326 | AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01, | |
327 | }; | |
328 | /* Bits in MACCtrl. */ | |
329 | enum mac_ctrl0_bits { | |
330 | EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40, | |
331 | EnbFlowCtrl=0x100, EnbPassRxCRC=0x200, | |
332 | }; | |
333 | enum mac_ctrl1_bits { | |
334 | StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080, | |
335 | TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400, | |
336 | RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000, | |
337 | }; | |
338 | ||
339 | /* The Rx and Tx buffer descriptors. */ | |
340 | /* Note that using only 32 bit fields simplifies conversion to big-endian | |
341 | architectures. */ | |
342 | struct netdev_desc { | |
14c9d9b0 AV |
343 | __le32 next_desc; |
344 | __le32 status; | |
345 | struct desc_frag { __le32 addr, length; } frag[1]; | |
1da177e4 LT |
346 | }; |
347 | ||
348 | /* Bits in netdev_desc.status */ | |
349 | enum desc_status_bits { | |
350 | DescOwn=0x8000, | |
351 | DescEndPacket=0x4000, | |
352 | DescEndRing=0x2000, | |
353 | LastFrag=0x80000000, | |
354 | DescIntrOnTx=0x8000, | |
355 | DescIntrOnDMADone=0x80000000, | |
356 | DisableAlign = 0x00000001, | |
357 | }; | |
358 | ||
359 | #define PRIV_ALIGN 15 /* Required alignment mask */ | |
360 | /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment | |
361 | within the structure. */ | |
362 | #define MII_CNT 4 | |
363 | struct netdev_private { | |
364 | /* Descriptor rings first for alignment. */ | |
365 | struct netdev_desc *rx_ring; | |
366 | struct netdev_desc *tx_ring; | |
367 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; | |
368 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; | |
369 | dma_addr_t tx_ring_dma; | |
370 | dma_addr_t rx_ring_dma; | |
371 | struct net_device_stats stats; | |
372 | struct timer_list timer; /* Media monitoring timer. */ | |
373 | /* Frequently used values: keep some adjacent for cache effect. */ | |
374 | spinlock_t lock; | |
375 | spinlock_t rx_lock; /* Group with Tx control cache line. */ | |
376 | int msg_enable; | |
377 | int chip_id; | |
378 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
379 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
380 | struct netdev_desc *last_tx; /* Last Tx descriptor used. */ | |
381 | unsigned int cur_tx, dirty_tx; | |
382 | /* These values are keep track of the transceiver/media in use. */ | |
383 | unsigned int flowctrl:1; | |
384 | unsigned int default_port:4; /* Last dev->if_port value. */ | |
385 | unsigned int an_enable:1; | |
386 | unsigned int speed; | |
387 | struct tasklet_struct rx_tasklet; | |
388 | struct tasklet_struct tx_tasklet; | |
389 | int budget; | |
390 | int cur_task; | |
391 | /* Multicast and receive mode. */ | |
392 | spinlock_t mcastlock; /* SMP lock multicast updates. */ | |
393 | u16 mcast_filter[4]; | |
394 | /* MII transceiver section. */ | |
395 | struct mii_if_info mii_if; | |
396 | int mii_preamble_required; | |
397 | unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */ | |
398 | struct pci_dev *pci_dev; | |
399 | void __iomem *base; | |
1da177e4 LT |
400 | }; |
401 | ||
402 | /* The station address location in the EEPROM. */ | |
403 | #define EEPROM_SA_OFFSET 0x10 | |
404 | #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \ | |
405 | IntrDrvRqst | IntrTxDone | StatsMax | \ | |
406 | LinkChange) | |
407 | ||
408 | static int change_mtu(struct net_device *dev, int new_mtu); | |
409 | static int eeprom_read(void __iomem *ioaddr, int location); | |
410 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
411 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
50500155 | 412 | static int mdio_wait_link(struct net_device *dev, int wait); |
1da177e4 LT |
413 | static int netdev_open(struct net_device *dev); |
414 | static void check_duplex(struct net_device *dev); | |
415 | static void netdev_timer(unsigned long data); | |
416 | static void tx_timeout(struct net_device *dev); | |
417 | static void init_ring(struct net_device *dev); | |
418 | static int start_tx(struct sk_buff *skb, struct net_device *dev); | |
419 | static int reset_tx (struct net_device *dev); | |
7d12e780 | 420 | static irqreturn_t intr_handler(int irq, void *dev_instance); |
1da177e4 LT |
421 | static void rx_poll(unsigned long data); |
422 | static void tx_poll(unsigned long data); | |
423 | static void refill_rx (struct net_device *dev); | |
424 | static void netdev_error(struct net_device *dev, int intr_status); | |
425 | static void netdev_error(struct net_device *dev, int intr_status); | |
426 | static void set_rx_mode(struct net_device *dev); | |
427 | static int __set_mac_addr(struct net_device *dev); | |
428 | static struct net_device_stats *get_stats(struct net_device *dev); | |
429 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
430 | static int netdev_close(struct net_device *dev); | |
7282d491 | 431 | static const struct ethtool_ops ethtool_ops; |
1da177e4 | 432 | |
b71b95ef PDM |
433 | static void sundance_reset(struct net_device *dev, unsigned long reset_cmd) |
434 | { | |
435 | struct netdev_private *np = netdev_priv(dev); | |
436 | void __iomem *ioaddr = np->base + ASICCtrl; | |
437 | int countdown; | |
438 | ||
439 | /* ST201 documentation states ASICCtrl is a 32bit register */ | |
440 | iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr); | |
441 | /* ST201 documentation states reset can take up to 1 ms */ | |
442 | countdown = 10 + 1; | |
443 | while (ioread32 (ioaddr) & (ResetBusy << 16)) { | |
444 | if (--countdown == 0) { | |
445 | printk(KERN_WARNING "%s : reset not completed !!\n", dev->name); | |
446 | break; | |
447 | } | |
448 | udelay(100); | |
449 | } | |
450 | } | |
451 | ||
1da177e4 LT |
452 | static int __devinit sundance_probe1 (struct pci_dev *pdev, |
453 | const struct pci_device_id *ent) | |
454 | { | |
455 | struct net_device *dev; | |
456 | struct netdev_private *np; | |
457 | static int card_idx; | |
458 | int chip_idx = ent->driver_data; | |
459 | int irq; | |
460 | int i; | |
461 | void __iomem *ioaddr; | |
462 | u16 mii_ctl; | |
463 | void *ring_space; | |
464 | dma_addr_t ring_dma; | |
465 | #ifdef USE_IO_OPS | |
466 | int bar = 0; | |
467 | #else | |
468 | int bar = 1; | |
469 | #endif | |
ac1d49f8 | 470 | int phy, phy_end, phy_idx = 0; |
1da177e4 LT |
471 | |
472 | /* when built into the kernel, we only print version if device is found */ | |
473 | #ifndef MODULE | |
474 | static int printed_version; | |
475 | if (!printed_version++) | |
476 | printk(version); | |
477 | #endif | |
478 | ||
479 | if (pci_enable_device(pdev)) | |
480 | return -EIO; | |
481 | pci_set_master(pdev); | |
482 | ||
483 | irq = pdev->irq; | |
484 | ||
485 | dev = alloc_etherdev(sizeof(*np)); | |
486 | if (!dev) | |
487 | return -ENOMEM; | |
1da177e4 LT |
488 | SET_NETDEV_DEV(dev, &pdev->dev); |
489 | ||
490 | if (pci_request_regions(pdev, DRV_NAME)) | |
491 | goto err_out_netdev; | |
492 | ||
493 | ioaddr = pci_iomap(pdev, bar, netdev_io_size); | |
494 | if (!ioaddr) | |
495 | goto err_out_res; | |
496 | ||
497 | for (i = 0; i < 3; i++) | |
14c9d9b0 AV |
498 | ((__le16 *)dev->dev_addr)[i] = |
499 | cpu_to_le16(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET)); | |
30d60a82 | 500 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
501 | |
502 | dev->base_addr = (unsigned long)ioaddr; | |
503 | dev->irq = irq; | |
504 | ||
505 | np = netdev_priv(dev); | |
506 | np->base = ioaddr; | |
507 | np->pci_dev = pdev; | |
508 | np->chip_id = chip_idx; | |
509 | np->msg_enable = (1 << debug) - 1; | |
510 | spin_lock_init(&np->lock); | |
511 | tasklet_init(&np->rx_tasklet, rx_poll, (unsigned long)dev); | |
512 | tasklet_init(&np->tx_tasklet, tx_poll, (unsigned long)dev); | |
513 | ||
514 | ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma); | |
515 | if (!ring_space) | |
516 | goto err_out_cleardev; | |
517 | np->tx_ring = (struct netdev_desc *)ring_space; | |
518 | np->tx_ring_dma = ring_dma; | |
519 | ||
520 | ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma); | |
521 | if (!ring_space) | |
522 | goto err_out_unmap_tx; | |
523 | np->rx_ring = (struct netdev_desc *)ring_space; | |
524 | np->rx_ring_dma = ring_dma; | |
525 | ||
526 | np->mii_if.dev = dev; | |
527 | np->mii_if.mdio_read = mdio_read; | |
528 | np->mii_if.mdio_write = mdio_write; | |
529 | np->mii_if.phy_id_mask = 0x1f; | |
530 | np->mii_if.reg_num_mask = 0x1f; | |
531 | ||
532 | /* The chip-specific entries in the device structure. */ | |
533 | dev->open = &netdev_open; | |
534 | dev->hard_start_xmit = &start_tx; | |
535 | dev->stop = &netdev_close; | |
536 | dev->get_stats = &get_stats; | |
537 | dev->set_multicast_list = &set_rx_mode; | |
538 | dev->do_ioctl = &netdev_ioctl; | |
539 | SET_ETHTOOL_OPS(dev, ðtool_ops); | |
540 | dev->tx_timeout = &tx_timeout; | |
541 | dev->watchdog_timeo = TX_TIMEOUT; | |
542 | dev->change_mtu = &change_mtu; | |
543 | pci_set_drvdata(pdev, dev); | |
544 | ||
1da177e4 LT |
545 | i = register_netdev(dev); |
546 | if (i) | |
547 | goto err_out_unmap_rx; | |
548 | ||
e174961c | 549 | printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n", |
0795af57 | 550 | dev->name, pci_id_tbl[chip_idx].name, ioaddr, |
e174961c | 551 | dev->dev_addr, irq); |
1da177e4 | 552 | |
67ec2f80 JL |
553 | np->phys[0] = 1; /* Default setting */ |
554 | np->mii_preamble_required++; | |
ac1d49f8 | 555 | |
0d615ec2 ACM |
556 | /* |
557 | * It seems some phys doesn't deal well with address 0 being accessed | |
ac1d49f8 | 558 | * first |
0d615ec2 | 559 | */ |
ac1d49f8 JG |
560 | if (sundance_pci_tbl[np->chip_id].device == 0x0200) { |
561 | phy = 0; | |
562 | phy_end = 31; | |
563 | } else { | |
564 | phy = 1; | |
565 | phy_end = 32; /* wraps to zero, due to 'phy & 0x1f' */ | |
566 | } | |
567 | for (; phy <= phy_end && phy_idx < MII_CNT; phy++) { | |
b06c093e | 568 | int phyx = phy & 0x1f; |
0d615ec2 | 569 | int mii_status = mdio_read(dev, phyx, MII_BMSR); |
67ec2f80 | 570 | if (mii_status != 0xffff && mii_status != 0x0000) { |
b06c093e JL |
571 | np->phys[phy_idx++] = phyx; |
572 | np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE); | |
67ec2f80 JL |
573 | if ((mii_status & 0x0040) == 0) |
574 | np->mii_preamble_required++; | |
575 | printk(KERN_INFO "%s: MII PHY found at address %d, status " | |
576 | "0x%4.4x advertising %4.4x.\n", | |
b06c093e | 577 | dev->name, phyx, mii_status, np->mii_if.advertising); |
1da177e4 | 578 | } |
67ec2f80 JL |
579 | } |
580 | np->mii_preamble_required--; | |
1da177e4 | 581 | |
67ec2f80 JL |
582 | if (phy_idx == 0) { |
583 | printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n", | |
584 | dev->name, ioread32(ioaddr + ASICCtrl)); | |
585 | goto err_out_unregister; | |
1da177e4 LT |
586 | } |
587 | ||
67ec2f80 JL |
588 | np->mii_if.phy_id = np->phys[0]; |
589 | ||
1da177e4 LT |
590 | /* Parse override configuration */ |
591 | np->an_enable = 1; | |
592 | if (card_idx < MAX_UNITS) { | |
593 | if (media[card_idx] != NULL) { | |
594 | np->an_enable = 0; | |
595 | if (strcmp (media[card_idx], "100mbps_fd") == 0 || | |
596 | strcmp (media[card_idx], "4") == 0) { | |
597 | np->speed = 100; | |
598 | np->mii_if.full_duplex = 1; | |
599 | } else if (strcmp (media[card_idx], "100mbps_hd") == 0 | |
600 | || strcmp (media[card_idx], "3") == 0) { | |
601 | np->speed = 100; | |
602 | np->mii_if.full_duplex = 0; | |
603 | } else if (strcmp (media[card_idx], "10mbps_fd") == 0 || | |
604 | strcmp (media[card_idx], "2") == 0) { | |
605 | np->speed = 10; | |
606 | np->mii_if.full_duplex = 1; | |
607 | } else if (strcmp (media[card_idx], "10mbps_hd") == 0 || | |
608 | strcmp (media[card_idx], "1") == 0) { | |
609 | np->speed = 10; | |
610 | np->mii_if.full_duplex = 0; | |
611 | } else { | |
612 | np->an_enable = 1; | |
613 | } | |
614 | } | |
615 | if (flowctrl == 1) | |
616 | np->flowctrl = 1; | |
617 | } | |
618 | ||
619 | /* Fibre PHY? */ | |
620 | if (ioread32 (ioaddr + ASICCtrl) & 0x80) { | |
621 | /* Default 100Mbps Full */ | |
622 | if (np->an_enable) { | |
623 | np->speed = 100; | |
624 | np->mii_if.full_duplex = 1; | |
625 | np->an_enable = 0; | |
626 | } | |
627 | } | |
628 | /* Reset PHY */ | |
629 | mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET); | |
630 | mdelay (300); | |
631 | /* If flow control enabled, we need to advertise it.*/ | |
632 | if (np->flowctrl) | |
633 | mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400); | |
634 | mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART); | |
635 | /* Force media type */ | |
636 | if (!np->an_enable) { | |
637 | mii_ctl = 0; | |
638 | mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0; | |
639 | mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0; | |
640 | mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl); | |
641 | printk (KERN_INFO "Override speed=%d, %s duplex\n", | |
642 | np->speed, np->mii_if.full_duplex ? "Full" : "Half"); | |
643 | ||
644 | } | |
645 | ||
646 | /* Perhaps move the reset here? */ | |
647 | /* Reset the chip to erase previous misconfiguration. */ | |
648 | if (netif_msg_hw(np)) | |
649 | printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl)); | |
e714d99c | 650 | sundance_reset(dev, 0x00ff << 16); |
1da177e4 LT |
651 | if (netif_msg_hw(np)) |
652 | printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl)); | |
653 | ||
654 | card_idx++; | |
655 | return 0; | |
656 | ||
657 | err_out_unregister: | |
658 | unregister_netdev(dev); | |
659 | err_out_unmap_rx: | |
660 | pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma); | |
661 | err_out_unmap_tx: | |
662 | pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma); | |
663 | err_out_cleardev: | |
664 | pci_set_drvdata(pdev, NULL); | |
665 | pci_iounmap(pdev, ioaddr); | |
666 | err_out_res: | |
667 | pci_release_regions(pdev); | |
668 | err_out_netdev: | |
669 | free_netdev (dev); | |
670 | return -ENODEV; | |
671 | } | |
672 | ||
673 | static int change_mtu(struct net_device *dev, int new_mtu) | |
674 | { | |
675 | if ((new_mtu < 68) || (new_mtu > 8191)) /* Set by RxDMAFrameLen */ | |
676 | return -EINVAL; | |
677 | if (netif_running(dev)) | |
678 | return -EBUSY; | |
679 | dev->mtu = new_mtu; | |
680 | return 0; | |
681 | } | |
682 | ||
683 | #define eeprom_delay(ee_addr) ioread32(ee_addr) | |
684 | /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */ | |
685 | static int __devinit eeprom_read(void __iomem *ioaddr, int location) | |
686 | { | |
687 | int boguscnt = 10000; /* Typical 1900 ticks. */ | |
688 | iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl); | |
689 | do { | |
690 | eeprom_delay(ioaddr + EECtrl); | |
691 | if (! (ioread16(ioaddr + EECtrl) & 0x8000)) { | |
692 | return ioread16(ioaddr + EEData); | |
693 | } | |
694 | } while (--boguscnt > 0); | |
695 | return 0; | |
696 | } | |
697 | ||
698 | /* MII transceiver control section. | |
699 | Read and write the MII registers using software-generated serial | |
700 | MDIO protocol. See the MII specifications or DP83840A data sheet | |
701 | for details. | |
702 | ||
703 | The maximum data clock rate is 2.5 Mhz. The minimum timing is usually | |
704 | met by back-to-back 33Mhz PCI cycles. */ | |
705 | #define mdio_delay() ioread8(mdio_addr) | |
706 | ||
707 | enum mii_reg_bits { | |
708 | MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004, | |
709 | }; | |
710 | #define MDIO_EnbIn (0) | |
711 | #define MDIO_WRITE0 (MDIO_EnbOutput) | |
712 | #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) | |
713 | ||
714 | /* Generate the preamble required for initial synchronization and | |
715 | a few older transceivers. */ | |
716 | static void mdio_sync(void __iomem *mdio_addr) | |
717 | { | |
718 | int bits = 32; | |
719 | ||
720 | /* Establish sync by sending at least 32 logic ones. */ | |
721 | while (--bits >= 0) { | |
722 | iowrite8(MDIO_WRITE1, mdio_addr); | |
723 | mdio_delay(); | |
724 | iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr); | |
725 | mdio_delay(); | |
726 | } | |
727 | } | |
728 | ||
729 | static int mdio_read(struct net_device *dev, int phy_id, int location) | |
730 | { | |
731 | struct netdev_private *np = netdev_priv(dev); | |
732 | void __iomem *mdio_addr = np->base + MIICtrl; | |
733 | int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location; | |
734 | int i, retval = 0; | |
735 | ||
736 | if (np->mii_preamble_required) | |
737 | mdio_sync(mdio_addr); | |
738 | ||
739 | /* Shift the read command bits out. */ | |
740 | for (i = 15; i >= 0; i--) { | |
741 | int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; | |
742 | ||
743 | iowrite8(dataval, mdio_addr); | |
744 | mdio_delay(); | |
745 | iowrite8(dataval | MDIO_ShiftClk, mdio_addr); | |
746 | mdio_delay(); | |
747 | } | |
748 | /* Read the two transition, 16 data, and wire-idle bits. */ | |
749 | for (i = 19; i > 0; i--) { | |
750 | iowrite8(MDIO_EnbIn, mdio_addr); | |
751 | mdio_delay(); | |
752 | retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0); | |
753 | iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); | |
754 | mdio_delay(); | |
755 | } | |
756 | return (retval>>1) & 0xffff; | |
757 | } | |
758 | ||
759 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value) | |
760 | { | |
761 | struct netdev_private *np = netdev_priv(dev); | |
762 | void __iomem *mdio_addr = np->base + MIICtrl; | |
763 | int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value; | |
764 | int i; | |
765 | ||
766 | if (np->mii_preamble_required) | |
767 | mdio_sync(mdio_addr); | |
768 | ||
769 | /* Shift the command bits out. */ | |
770 | for (i = 31; i >= 0; i--) { | |
771 | int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; | |
772 | ||
773 | iowrite8(dataval, mdio_addr); | |
774 | mdio_delay(); | |
775 | iowrite8(dataval | MDIO_ShiftClk, mdio_addr); | |
776 | mdio_delay(); | |
777 | } | |
778 | /* Clear out extra bits. */ | |
779 | for (i = 2; i > 0; i--) { | |
780 | iowrite8(MDIO_EnbIn, mdio_addr); | |
781 | mdio_delay(); | |
782 | iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr); | |
783 | mdio_delay(); | |
784 | } | |
785 | return; | |
786 | } | |
787 | ||
50500155 DN |
788 | static int mdio_wait_link(struct net_device *dev, int wait) |
789 | { | |
790 | int bmsr; | |
791 | int phy_id; | |
792 | struct netdev_private *np; | |
793 | ||
794 | np = netdev_priv(dev); | |
795 | phy_id = np->phys[0]; | |
796 | ||
797 | do { | |
798 | bmsr = mdio_read(dev, phy_id, MII_BMSR); | |
799 | if (bmsr & 0x0004) | |
800 | return 0; | |
801 | mdelay(1); | |
802 | } while (--wait > 0); | |
803 | return -1; | |
804 | } | |
805 | ||
1da177e4 LT |
806 | static int netdev_open(struct net_device *dev) |
807 | { | |
808 | struct netdev_private *np = netdev_priv(dev); | |
809 | void __iomem *ioaddr = np->base; | |
acd70c2b | 810 | unsigned long flags; |
1da177e4 LT |
811 | int i; |
812 | ||
813 | /* Do we need to reset the chip??? */ | |
814 | ||
1fb9df5d | 815 | i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev); |
1da177e4 LT |
816 | if (i) |
817 | return i; | |
818 | ||
819 | if (netif_msg_ifup(np)) | |
820 | printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", | |
821 | dev->name, dev->irq); | |
822 | init_ring(dev); | |
823 | ||
824 | iowrite32(np->rx_ring_dma, ioaddr + RxListPtr); | |
825 | /* The Tx list pointer is written as packets are queued. */ | |
826 | ||
827 | /* Initialize other registers. */ | |
828 | __set_mac_addr(dev); | |
829 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) | |
830 | iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize); | |
831 | #else | |
832 | iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize); | |
833 | #endif | |
834 | if (dev->mtu > 2047) | |
835 | iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl); | |
836 | ||
837 | /* Configure the PCI bus bursts and FIFO thresholds. */ | |
838 | ||
839 | if (dev->if_port == 0) | |
840 | dev->if_port = np->default_port; | |
841 | ||
842 | spin_lock_init(&np->mcastlock); | |
843 | ||
844 | set_rx_mode(dev); | |
845 | iowrite16(0, ioaddr + IntrEnable); | |
846 | iowrite16(0, ioaddr + DownCounter); | |
847 | /* Set the chip to poll every N*320nsec. */ | |
848 | iowrite8(100, ioaddr + RxDMAPollPeriod); | |
849 | iowrite8(127, ioaddr + TxDMAPollPeriod); | |
850 | /* Fix DFE-580TX packet drop issue */ | |
44c10138 | 851 | if (np->pci_dev->revision >= 0x14) |
1da177e4 LT |
852 | iowrite8(0x01, ioaddr + DebugCtrl1); |
853 | netif_start_queue(dev); | |
854 | ||
acd70c2b JH |
855 | spin_lock_irqsave(&np->lock, flags); |
856 | reset_tx(dev); | |
857 | spin_unlock_irqrestore(&np->lock, flags); | |
858 | ||
1da177e4 LT |
859 | iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1); |
860 | ||
861 | if (netif_msg_ifup(np)) | |
862 | printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x " | |
863 | "MAC Control %x, %4.4x %4.4x.\n", | |
864 | dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus), | |
865 | ioread32(ioaddr + MACCtrl0), | |
866 | ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0)); | |
867 | ||
868 | /* Set the timer to check for link beat. */ | |
869 | init_timer(&np->timer); | |
870 | np->timer.expires = jiffies + 3*HZ; | |
871 | np->timer.data = (unsigned long)dev; | |
872 | np->timer.function = &netdev_timer; /* timer handler */ | |
873 | add_timer(&np->timer); | |
874 | ||
875 | /* Enable interrupts by setting the interrupt mask. */ | |
876 | iowrite16(DEFAULT_INTR, ioaddr + IntrEnable); | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | static void check_duplex(struct net_device *dev) | |
882 | { | |
883 | struct netdev_private *np = netdev_priv(dev); | |
884 | void __iomem *ioaddr = np->base; | |
885 | int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA); | |
886 | int negotiated = mii_lpa & np->mii_if.advertising; | |
887 | int duplex; | |
888 | ||
889 | /* Force media */ | |
890 | if (!np->an_enable || mii_lpa == 0xffff) { | |
891 | if (np->mii_if.full_duplex) | |
892 | iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex, | |
893 | ioaddr + MACCtrl0); | |
894 | return; | |
895 | } | |
896 | ||
897 | /* Autonegotiation */ | |
898 | duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040; | |
899 | if (np->mii_if.full_duplex != duplex) { | |
900 | np->mii_if.full_duplex = duplex; | |
901 | if (netif_msg_link(np)) | |
902 | printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d " | |
903 | "negotiated capability %4.4x.\n", dev->name, | |
904 | duplex ? "full" : "half", np->phys[0], negotiated); | |
905 | iowrite16(ioread16(ioaddr + MACCtrl0) | duplex ? 0x20 : 0, ioaddr + MACCtrl0); | |
906 | } | |
907 | } | |
908 | ||
909 | static void netdev_timer(unsigned long data) | |
910 | { | |
911 | struct net_device *dev = (struct net_device *)data; | |
912 | struct netdev_private *np = netdev_priv(dev); | |
913 | void __iomem *ioaddr = np->base; | |
914 | int next_tick = 10*HZ; | |
915 | ||
916 | if (netif_msg_timer(np)) { | |
917 | printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, " | |
918 | "Tx %x Rx %x.\n", | |
919 | dev->name, ioread16(ioaddr + IntrEnable), | |
920 | ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus)); | |
921 | } | |
922 | check_duplex(dev); | |
923 | np->timer.expires = jiffies + next_tick; | |
924 | add_timer(&np->timer); | |
925 | } | |
926 | ||
927 | static void tx_timeout(struct net_device *dev) | |
928 | { | |
929 | struct netdev_private *np = netdev_priv(dev); | |
930 | void __iomem *ioaddr = np->base; | |
931 | unsigned long flag; | |
6aa20a22 | 932 | |
1da177e4 LT |
933 | netif_stop_queue(dev); |
934 | tasklet_disable(&np->tx_tasklet); | |
935 | iowrite16(0, ioaddr + IntrEnable); | |
936 | printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x " | |
937 | "TxFrameId %2.2x," | |
938 | " resetting...\n", dev->name, ioread8(ioaddr + TxStatus), | |
939 | ioread8(ioaddr + TxFrameId)); | |
940 | ||
941 | { | |
942 | int i; | |
943 | for (i=0; i<TX_RING_SIZE; i++) { | |
944 | printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i, | |
945 | (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)), | |
946 | le32_to_cpu(np->tx_ring[i].next_desc), | |
947 | le32_to_cpu(np->tx_ring[i].status), | |
948 | (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff, | |
6aa20a22 | 949 | le32_to_cpu(np->tx_ring[i].frag[0].addr), |
1da177e4 LT |
950 | le32_to_cpu(np->tx_ring[i].frag[0].length)); |
951 | } | |
6aa20a22 JG |
952 | printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n", |
953 | ioread32(np->base + TxListPtr), | |
1da177e4 | 954 | netif_queue_stopped(dev)); |
6aa20a22 | 955 | printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n", |
1da177e4 LT |
956 | np->cur_tx, np->cur_tx % TX_RING_SIZE, |
957 | np->dirty_tx, np->dirty_tx % TX_RING_SIZE); | |
958 | printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx); | |
959 | printk(KERN_DEBUG "cur_task=%d\n", np->cur_task); | |
960 | } | |
961 | spin_lock_irqsave(&np->lock, flag); | |
962 | ||
963 | /* Stop and restart the chip's Tx processes . */ | |
964 | reset_tx(dev); | |
965 | spin_unlock_irqrestore(&np->lock, flag); | |
966 | ||
967 | dev->if_port = 0; | |
968 | ||
969 | dev->trans_start = jiffies; | |
970 | np->stats.tx_errors++; | |
971 | if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) { | |
972 | netif_wake_queue(dev); | |
973 | } | |
974 | iowrite16(DEFAULT_INTR, ioaddr + IntrEnable); | |
975 | tasklet_enable(&np->tx_tasklet); | |
976 | } | |
977 | ||
978 | ||
979 | /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ | |
980 | static void init_ring(struct net_device *dev) | |
981 | { | |
982 | struct netdev_private *np = netdev_priv(dev); | |
983 | int i; | |
984 | ||
985 | np->cur_rx = np->cur_tx = 0; | |
986 | np->dirty_rx = np->dirty_tx = 0; | |
987 | np->cur_task = 0; | |
988 | ||
989 | np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16); | |
990 | ||
991 | /* Initialize all Rx descriptors. */ | |
992 | for (i = 0; i < RX_RING_SIZE; i++) { | |
993 | np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma + | |
994 | ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring)); | |
995 | np->rx_ring[i].status = 0; | |
996 | np->rx_ring[i].frag[0].length = 0; | |
997 | np->rx_skbuff[i] = NULL; | |
998 | } | |
999 | ||
1000 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
1001 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1002 | struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz); | |
1003 | np->rx_skbuff[i] = skb; | |
1004 | if (skb == NULL) | |
1005 | break; | |
1006 | skb->dev = dev; /* Mark as being used by this device. */ | |
1007 | skb_reserve(skb, 2); /* 16 byte align the IP header. */ | |
1008 | np->rx_ring[i].frag[0].addr = cpu_to_le32( | |
689be439 | 1009 | pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, |
1da177e4 LT |
1010 | PCI_DMA_FROMDEVICE)); |
1011 | np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag); | |
1012 | } | |
1013 | np->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
1014 | ||
1015 | for (i = 0; i < TX_RING_SIZE; i++) { | |
1016 | np->tx_skbuff[i] = NULL; | |
1017 | np->tx_ring[i].status = 0; | |
1018 | } | |
1019 | return; | |
1020 | } | |
1021 | ||
1022 | static void tx_poll (unsigned long data) | |
1023 | { | |
1024 | struct net_device *dev = (struct net_device *)data; | |
1025 | struct netdev_private *np = netdev_priv(dev); | |
1026 | unsigned head = np->cur_task % TX_RING_SIZE; | |
6aa20a22 | 1027 | struct netdev_desc *txdesc = |
1da177e4 | 1028 | &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE]; |
6aa20a22 | 1029 | |
1da177e4 LT |
1030 | /* Chain the next pointer */ |
1031 | for (; np->cur_tx - np->cur_task > 0; np->cur_task++) { | |
1032 | int entry = np->cur_task % TX_RING_SIZE; | |
1033 | txdesc = &np->tx_ring[entry]; | |
1034 | if (np->last_tx) { | |
1035 | np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma + | |
1036 | entry*sizeof(struct netdev_desc)); | |
1037 | } | |
1038 | np->last_tx = txdesc; | |
1039 | } | |
1040 | /* Indicate the latest descriptor of tx ring */ | |
1041 | txdesc->status |= cpu_to_le32(DescIntrOnTx); | |
1042 | ||
1043 | if (ioread32 (np->base + TxListPtr) == 0) | |
1044 | iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc), | |
1045 | np->base + TxListPtr); | |
1046 | return; | |
1047 | } | |
1048 | ||
1049 | static int | |
1050 | start_tx (struct sk_buff *skb, struct net_device *dev) | |
1051 | { | |
1052 | struct netdev_private *np = netdev_priv(dev); | |
1053 | struct netdev_desc *txdesc; | |
1054 | unsigned entry; | |
1055 | ||
1056 | /* Calculate the next Tx descriptor entry. */ | |
1057 | entry = np->cur_tx % TX_RING_SIZE; | |
1058 | np->tx_skbuff[entry] = skb; | |
1059 | txdesc = &np->tx_ring[entry]; | |
1060 | ||
1061 | txdesc->next_desc = 0; | |
1062 | txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign); | |
1063 | txdesc->frag[0].addr = cpu_to_le32 (pci_map_single (np->pci_dev, skb->data, | |
1064 | skb->len, | |
1065 | PCI_DMA_TODEVICE)); | |
1066 | txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag); | |
1067 | ||
1068 | /* Increment cur_tx before tasklet_schedule() */ | |
1069 | np->cur_tx++; | |
1070 | mb(); | |
1071 | /* Schedule a tx_poll() task */ | |
1072 | tasklet_schedule(&np->tx_tasklet); | |
1073 | ||
1074 | /* On some architectures: explicitly flush cache lines here. */ | |
1075 | if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1 | |
1076 | && !netif_queue_stopped(dev)) { | |
1077 | /* do nothing */ | |
1078 | } else { | |
1079 | netif_stop_queue (dev); | |
1080 | } | |
1081 | dev->trans_start = jiffies; | |
1082 | if (netif_msg_tx_queued(np)) { | |
1083 | printk (KERN_DEBUG | |
1084 | "%s: Transmit frame #%d queued in slot %d.\n", | |
1085 | dev->name, np->cur_tx, entry); | |
1086 | } | |
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | /* Reset hardware tx and free all of tx buffers */ | |
1091 | static int | |
1092 | reset_tx (struct net_device *dev) | |
1093 | { | |
1094 | struct netdev_private *np = netdev_priv(dev); | |
1095 | void __iomem *ioaddr = np->base; | |
1096 | struct sk_buff *skb; | |
1097 | int i; | |
1098 | int irq = in_interrupt(); | |
6aa20a22 | 1099 | |
1da177e4 LT |
1100 | /* Reset tx logic, TxListPtr will be cleaned */ |
1101 | iowrite16 (TxDisable, ioaddr + MACCtrl1); | |
e714d99c PDM |
1102 | sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16); |
1103 | ||
1da177e4 LT |
1104 | /* free all tx skbuff */ |
1105 | for (i = 0; i < TX_RING_SIZE; i++) { | |
2109f89f JH |
1106 | np->tx_ring[i].next_desc = 0; |
1107 | ||
1da177e4 LT |
1108 | skb = np->tx_skbuff[i]; |
1109 | if (skb) { | |
6aa20a22 | 1110 | pci_unmap_single(np->pci_dev, |
14c9d9b0 AV |
1111 | le32_to_cpu(np->tx_ring[i].frag[0].addr), |
1112 | skb->len, PCI_DMA_TODEVICE); | |
1da177e4 LT |
1113 | if (irq) |
1114 | dev_kfree_skb_irq (skb); | |
1115 | else | |
1116 | dev_kfree_skb (skb); | |
1117 | np->tx_skbuff[i] = NULL; | |
1118 | np->stats.tx_dropped++; | |
1119 | } | |
1120 | } | |
1121 | np->cur_tx = np->dirty_tx = 0; | |
1122 | np->cur_task = 0; | |
2109f89f | 1123 | |
bca79eb7 | 1124 | np->last_tx = NULL; |
2109f89f JH |
1125 | iowrite8(127, ioaddr + TxDMAPollPeriod); |
1126 | ||
1da177e4 LT |
1127 | iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1); |
1128 | return 0; | |
1129 | } | |
1130 | ||
6aa20a22 | 1131 | /* The interrupt handler cleans up after the Tx thread, |
1da177e4 | 1132 | and schedule a Rx thread work */ |
7d12e780 | 1133 | static irqreturn_t intr_handler(int irq, void *dev_instance) |
1da177e4 LT |
1134 | { |
1135 | struct net_device *dev = (struct net_device *)dev_instance; | |
1136 | struct netdev_private *np = netdev_priv(dev); | |
1137 | void __iomem *ioaddr = np->base; | |
1138 | int hw_frame_id; | |
1139 | int tx_cnt; | |
1140 | int tx_status; | |
1141 | int handled = 0; | |
e242040d | 1142 | int i; |
1da177e4 LT |
1143 | |
1144 | ||
1145 | do { | |
1146 | int intr_status = ioread16(ioaddr + IntrStatus); | |
1147 | iowrite16(intr_status, ioaddr + IntrStatus); | |
1148 | ||
1149 | if (netif_msg_intr(np)) | |
1150 | printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", | |
1151 | dev->name, intr_status); | |
1152 | ||
1153 | if (!(intr_status & DEFAULT_INTR)) | |
1154 | break; | |
1155 | ||
1156 | handled = 1; | |
1157 | ||
1158 | if (intr_status & (IntrRxDMADone)) { | |
1159 | iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone), | |
1160 | ioaddr + IntrEnable); | |
1161 | if (np->budget < 0) | |
1162 | np->budget = RX_BUDGET; | |
1163 | tasklet_schedule(&np->rx_tasklet); | |
1164 | } | |
1165 | if (intr_status & (IntrTxDone | IntrDrvRqst)) { | |
1166 | tx_status = ioread16 (ioaddr + TxStatus); | |
1167 | for (tx_cnt=32; tx_status & 0x80; --tx_cnt) { | |
1168 | if (netif_msg_tx_done(np)) | |
1169 | printk | |
1170 | ("%s: Transmit status is %2.2x.\n", | |
1171 | dev->name, tx_status); | |
1172 | if (tx_status & 0x1e) { | |
b71b95ef PDM |
1173 | if (netif_msg_tx_err(np)) |
1174 | printk("%s: Transmit error status %4.4x.\n", | |
1175 | dev->name, tx_status); | |
1da177e4 LT |
1176 | np->stats.tx_errors++; |
1177 | if (tx_status & 0x10) | |
1178 | np->stats.tx_fifo_errors++; | |
1179 | if (tx_status & 0x08) | |
1180 | np->stats.collisions++; | |
b71b95ef PDM |
1181 | if (tx_status & 0x04) |
1182 | np->stats.tx_fifo_errors++; | |
1da177e4 LT |
1183 | if (tx_status & 0x02) |
1184 | np->stats.tx_window_errors++; | |
e242040d | 1185 | |
b71b95ef PDM |
1186 | /* |
1187 | ** This reset has been verified on | |
1188 | ** DFE-580TX boards ! phdm@macqel.be. | |
1189 | */ | |
1190 | if (tx_status & 0x10) { /* TxUnderrun */ | |
b71b95ef PDM |
1191 | /* Restart Tx FIFO and transmitter */ |
1192 | sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16); | |
b71b95ef | 1193 | /* No need to reset the Tx pointer here */ |
1da177e4 | 1194 | } |
2109f89f JH |
1195 | /* Restart the Tx. Need to make sure tx enabled */ |
1196 | i = 10; | |
1197 | do { | |
1198 | iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1); | |
1199 | if (ioread16(ioaddr + MACCtrl1) & TxEnabled) | |
1200 | break; | |
1201 | mdelay(1); | |
1202 | } while (--i); | |
1da177e4 LT |
1203 | } |
1204 | /* Yup, this is a documentation bug. It cost me *hours*. */ | |
1205 | iowrite16 (0, ioaddr + TxStatus); | |
1206 | if (tx_cnt < 0) { | |
1207 | iowrite32(5000, ioaddr + DownCounter); | |
1208 | break; | |
1209 | } | |
1210 | tx_status = ioread16 (ioaddr + TxStatus); | |
1211 | } | |
1212 | hw_frame_id = (tx_status >> 8) & 0xff; | |
1213 | } else { | |
1214 | hw_frame_id = ioread8(ioaddr + TxFrameId); | |
1215 | } | |
6aa20a22 | 1216 | |
44c10138 | 1217 | if (np->pci_dev->revision >= 0x14) { |
1da177e4 LT |
1218 | spin_lock(&np->lock); |
1219 | for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { | |
1220 | int entry = np->dirty_tx % TX_RING_SIZE; | |
1221 | struct sk_buff *skb; | |
1222 | int sw_frame_id; | |
1223 | sw_frame_id = (le32_to_cpu( | |
1224 | np->tx_ring[entry].status) >> 2) & 0xff; | |
1225 | if (sw_frame_id == hw_frame_id && | |
1226 | !(le32_to_cpu(np->tx_ring[entry].status) | |
1227 | & 0x00010000)) | |
1228 | break; | |
6aa20a22 | 1229 | if (sw_frame_id == (hw_frame_id + 1) % |
1da177e4 LT |
1230 | TX_RING_SIZE) |
1231 | break; | |
1232 | skb = np->tx_skbuff[entry]; | |
1233 | /* Free the original skb. */ | |
1234 | pci_unmap_single(np->pci_dev, | |
14c9d9b0 | 1235 | le32_to_cpu(np->tx_ring[entry].frag[0].addr), |
1da177e4 LT |
1236 | skb->len, PCI_DMA_TODEVICE); |
1237 | dev_kfree_skb_irq (np->tx_skbuff[entry]); | |
1238 | np->tx_skbuff[entry] = NULL; | |
1239 | np->tx_ring[entry].frag[0].addr = 0; | |
1240 | np->tx_ring[entry].frag[0].length = 0; | |
1241 | } | |
1242 | spin_unlock(&np->lock); | |
1243 | } else { | |
1244 | spin_lock(&np->lock); | |
1245 | for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { | |
1246 | int entry = np->dirty_tx % TX_RING_SIZE; | |
1247 | struct sk_buff *skb; | |
6aa20a22 | 1248 | if (!(le32_to_cpu(np->tx_ring[entry].status) |
1da177e4 LT |
1249 | & 0x00010000)) |
1250 | break; | |
1251 | skb = np->tx_skbuff[entry]; | |
1252 | /* Free the original skb. */ | |
1253 | pci_unmap_single(np->pci_dev, | |
14c9d9b0 | 1254 | le32_to_cpu(np->tx_ring[entry].frag[0].addr), |
1da177e4 LT |
1255 | skb->len, PCI_DMA_TODEVICE); |
1256 | dev_kfree_skb_irq (np->tx_skbuff[entry]); | |
1257 | np->tx_skbuff[entry] = NULL; | |
1258 | np->tx_ring[entry].frag[0].addr = 0; | |
1259 | np->tx_ring[entry].frag[0].length = 0; | |
1260 | } | |
1261 | spin_unlock(&np->lock); | |
1262 | } | |
6aa20a22 | 1263 | |
1da177e4 LT |
1264 | if (netif_queue_stopped(dev) && |
1265 | np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) { | |
1266 | /* The ring is no longer full, clear busy flag. */ | |
1267 | netif_wake_queue (dev); | |
1268 | } | |
1269 | /* Abnormal error summary/uncommon events handlers. */ | |
1270 | if (intr_status & (IntrPCIErr | LinkChange | StatsMax)) | |
1271 | netdev_error(dev, intr_status); | |
1272 | } while (0); | |
1273 | if (netif_msg_intr(np)) | |
1274 | printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n", | |
1275 | dev->name, ioread16(ioaddr + IntrStatus)); | |
1276 | return IRQ_RETVAL(handled); | |
1277 | } | |
1278 | ||
1279 | static void rx_poll(unsigned long data) | |
1280 | { | |
1281 | struct net_device *dev = (struct net_device *)data; | |
1282 | struct netdev_private *np = netdev_priv(dev); | |
1283 | int entry = np->cur_rx % RX_RING_SIZE; | |
1284 | int boguscnt = np->budget; | |
1285 | void __iomem *ioaddr = np->base; | |
1286 | int received = 0; | |
1287 | ||
1288 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
1289 | while (1) { | |
1290 | struct netdev_desc *desc = &(np->rx_ring[entry]); | |
1291 | u32 frame_status = le32_to_cpu(desc->status); | |
1292 | int pkt_len; | |
1293 | ||
1294 | if (--boguscnt < 0) { | |
1295 | goto not_done; | |
1296 | } | |
1297 | if (!(frame_status & DescOwn)) | |
1298 | break; | |
1299 | pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */ | |
1300 | if (netif_msg_rx_status(np)) | |
1301 | printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", | |
1302 | frame_status); | |
1303 | if (frame_status & 0x001f4000) { | |
1304 | /* There was a error. */ | |
1305 | if (netif_msg_rx_err(np)) | |
1306 | printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n", | |
1307 | frame_status); | |
1308 | np->stats.rx_errors++; | |
1309 | if (frame_status & 0x00100000) np->stats.rx_length_errors++; | |
1310 | if (frame_status & 0x00010000) np->stats.rx_fifo_errors++; | |
1311 | if (frame_status & 0x00060000) np->stats.rx_frame_errors++; | |
1312 | if (frame_status & 0x00080000) np->stats.rx_crc_errors++; | |
1313 | if (frame_status & 0x00100000) { | |
1314 | printk(KERN_WARNING "%s: Oversized Ethernet frame," | |
1315 | " status %8.8x.\n", | |
1316 | dev->name, frame_status); | |
1317 | } | |
1318 | } else { | |
1319 | struct sk_buff *skb; | |
1320 | #ifndef final_version | |
1321 | if (netif_msg_rx_status(np)) | |
1322 | printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d" | |
1323 | ", bogus_cnt %d.\n", | |
1324 | pkt_len, boguscnt); | |
1325 | #endif | |
1326 | /* Check if the packet is long enough to accept without copying | |
1327 | to a minimally-sized skbuff. */ | |
1328 | if (pkt_len < rx_copybreak | |
1329 | && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) { | |
1da177e4 LT |
1330 | skb_reserve(skb, 2); /* 16 byte align the IP header */ |
1331 | pci_dma_sync_single_for_cpu(np->pci_dev, | |
14c9d9b0 | 1332 | le32_to_cpu(desc->frag[0].addr), |
1da177e4 LT |
1333 | np->rx_buf_sz, |
1334 | PCI_DMA_FROMDEVICE); | |
1335 | ||
8c7b7faa | 1336 | skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len); |
1da177e4 | 1337 | pci_dma_sync_single_for_device(np->pci_dev, |
14c9d9b0 | 1338 | le32_to_cpu(desc->frag[0].addr), |
1da177e4 LT |
1339 | np->rx_buf_sz, |
1340 | PCI_DMA_FROMDEVICE); | |
1341 | skb_put(skb, pkt_len); | |
1342 | } else { | |
1343 | pci_unmap_single(np->pci_dev, | |
14c9d9b0 | 1344 | le32_to_cpu(desc->frag[0].addr), |
1da177e4 LT |
1345 | np->rx_buf_sz, |
1346 | PCI_DMA_FROMDEVICE); | |
1347 | skb_put(skb = np->rx_skbuff[entry], pkt_len); | |
1348 | np->rx_skbuff[entry] = NULL; | |
1349 | } | |
1350 | skb->protocol = eth_type_trans(skb, dev); | |
1351 | /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */ | |
1352 | netif_rx(skb); | |
1da177e4 LT |
1353 | } |
1354 | entry = (entry + 1) % RX_RING_SIZE; | |
1355 | received++; | |
1356 | } | |
1357 | np->cur_rx = entry; | |
1358 | refill_rx (dev); | |
1359 | np->budget -= received; | |
1360 | iowrite16(DEFAULT_INTR, ioaddr + IntrEnable); | |
1361 | return; | |
1362 | ||
1363 | not_done: | |
1364 | np->cur_rx = entry; | |
1365 | refill_rx (dev); | |
1366 | if (!received) | |
1367 | received = 1; | |
1368 | np->budget -= received; | |
1369 | if (np->budget <= 0) | |
1370 | np->budget = RX_BUDGET; | |
1371 | tasklet_schedule(&np->rx_tasklet); | |
1372 | return; | |
1373 | } | |
1374 | ||
1375 | static void refill_rx (struct net_device *dev) | |
1376 | { | |
1377 | struct netdev_private *np = netdev_priv(dev); | |
1378 | int entry; | |
1379 | int cnt = 0; | |
1380 | ||
1381 | /* Refill the Rx ring buffers. */ | |
1382 | for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0; | |
1383 | np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) { | |
1384 | struct sk_buff *skb; | |
1385 | entry = np->dirty_rx % RX_RING_SIZE; | |
1386 | if (np->rx_skbuff[entry] == NULL) { | |
1387 | skb = dev_alloc_skb(np->rx_buf_sz); | |
1388 | np->rx_skbuff[entry] = skb; | |
1389 | if (skb == NULL) | |
1390 | break; /* Better luck next round. */ | |
1391 | skb->dev = dev; /* Mark as being used by this device. */ | |
1392 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ | |
1393 | np->rx_ring[entry].frag[0].addr = cpu_to_le32( | |
689be439 | 1394 | pci_map_single(np->pci_dev, skb->data, |
1da177e4 LT |
1395 | np->rx_buf_sz, PCI_DMA_FROMDEVICE)); |
1396 | } | |
1397 | /* Perhaps we need not reset this field. */ | |
1398 | np->rx_ring[entry].frag[0].length = | |
1399 | cpu_to_le32(np->rx_buf_sz | LastFrag); | |
1400 | np->rx_ring[entry].status = 0; | |
1401 | cnt++; | |
1402 | } | |
1403 | return; | |
1404 | } | |
1405 | static void netdev_error(struct net_device *dev, int intr_status) | |
1406 | { | |
1407 | struct netdev_private *np = netdev_priv(dev); | |
1408 | void __iomem *ioaddr = np->base; | |
1409 | u16 mii_ctl, mii_advertise, mii_lpa; | |
1410 | int speed; | |
1411 | ||
1412 | if (intr_status & LinkChange) { | |
50500155 DN |
1413 | if (mdio_wait_link(dev, 10) == 0) { |
1414 | printk(KERN_INFO "%s: Link up\n", dev->name); | |
1415 | if (np->an_enable) { | |
1416 | mii_advertise = mdio_read(dev, np->phys[0], | |
1417 | MII_ADVERTISE); | |
1418 | mii_lpa = mdio_read(dev, np->phys[0], MII_LPA); | |
1419 | mii_advertise &= mii_lpa; | |
1420 | printk(KERN_INFO "%s: Link changed: ", | |
1421 | dev->name); | |
1422 | if (mii_advertise & ADVERTISE_100FULL) { | |
1423 | np->speed = 100; | |
1424 | printk("100Mbps, full duplex\n"); | |
1425 | } else if (mii_advertise & ADVERTISE_100HALF) { | |
1426 | np->speed = 100; | |
1427 | printk("100Mbps, half duplex\n"); | |
1428 | } else if (mii_advertise & ADVERTISE_10FULL) { | |
1429 | np->speed = 10; | |
1430 | printk("10Mbps, full duplex\n"); | |
1431 | } else if (mii_advertise & ADVERTISE_10HALF) { | |
1432 | np->speed = 10; | |
1433 | printk("10Mbps, half duplex\n"); | |
1434 | } else | |
1435 | printk("\n"); | |
1da177e4 | 1436 | |
50500155 DN |
1437 | } else { |
1438 | mii_ctl = mdio_read(dev, np->phys[0], MII_BMCR); | |
1439 | speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10; | |
1440 | np->speed = speed; | |
1441 | printk(KERN_INFO "%s: Link changed: %dMbps ,", | |
1442 | dev->name, speed); | |
1443 | printk("%s duplex.\n", | |
1444 | (mii_ctl & BMCR_FULLDPLX) ? | |
1445 | "full" : "half"); | |
1446 | } | |
1447 | check_duplex(dev); | |
1448 | if (np->flowctrl && np->mii_if.full_duplex) { | |
1449 | iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200, | |
1450 | ioaddr + MulticastFilter1+2); | |
1451 | iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl, | |
1452 | ioaddr + MACCtrl0); | |
1453 | } | |
1454 | netif_carrier_on(dev); | |
1da177e4 | 1455 | } else { |
50500155 DN |
1456 | printk(KERN_INFO "%s: Link down\n", dev->name); |
1457 | netif_carrier_off(dev); | |
1da177e4 LT |
1458 | } |
1459 | } | |
1460 | if (intr_status & StatsMax) { | |
1461 | get_stats(dev); | |
1462 | } | |
1463 | if (intr_status & IntrPCIErr) { | |
1464 | printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n", | |
1465 | dev->name, intr_status); | |
1466 | /* We must do a global reset of DMA to continue. */ | |
1467 | } | |
1468 | } | |
1469 | ||
1470 | static struct net_device_stats *get_stats(struct net_device *dev) | |
1471 | { | |
1472 | struct netdev_private *np = netdev_priv(dev); | |
1473 | void __iomem *ioaddr = np->base; | |
1474 | int i; | |
1475 | ||
1476 | /* We should lock this segment of code for SMP eventually, although | |
1477 | the vulnerability window is very small and statistics are | |
1478 | non-critical. */ | |
1479 | /* The chip only need report frame silently dropped. */ | |
1480 | np->stats.rx_missed_errors += ioread8(ioaddr + RxMissed); | |
1481 | np->stats.tx_packets += ioread16(ioaddr + TxFramesOK); | |
1482 | np->stats.rx_packets += ioread16(ioaddr + RxFramesOK); | |
1483 | np->stats.collisions += ioread8(ioaddr + StatsLateColl); | |
1484 | np->stats.collisions += ioread8(ioaddr + StatsMultiColl); | |
1485 | np->stats.collisions += ioread8(ioaddr + StatsOneColl); | |
1486 | np->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError); | |
1487 | ioread8(ioaddr + StatsTxDefer); | |
1488 | for (i = StatsTxDefer; i <= StatsMcastRx; i++) | |
1489 | ioread8(ioaddr + i); | |
1490 | np->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow); | |
1491 | np->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16; | |
1492 | np->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow); | |
1493 | np->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16; | |
1494 | ||
1495 | return &np->stats; | |
1496 | } | |
1497 | ||
1498 | static void set_rx_mode(struct net_device *dev) | |
1499 | { | |
1500 | struct netdev_private *np = netdev_priv(dev); | |
1501 | void __iomem *ioaddr = np->base; | |
1502 | u16 mc_filter[4]; /* Multicast hash filter */ | |
1503 | u32 rx_mode; | |
1504 | int i; | |
1505 | ||
1506 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1da177e4 LT |
1507 | memset(mc_filter, 0xff, sizeof(mc_filter)); |
1508 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys; | |
1509 | } else if ((dev->mc_count > multicast_filter_limit) | |
1510 | || (dev->flags & IFF_ALLMULTI)) { | |
1511 | /* Too many to match, or accept all multicasts. */ | |
1512 | memset(mc_filter, 0xff, sizeof(mc_filter)); | |
1513 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
1514 | } else if (dev->mc_count) { | |
1515 | struct dev_mc_list *mclist; | |
1516 | int bit; | |
1517 | int index; | |
1518 | int crc; | |
1519 | memset (mc_filter, 0, sizeof (mc_filter)); | |
1520 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1521 | i++, mclist = mclist->next) { | |
1522 | crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr); | |
1523 | for (index=0, bit=0; bit < 6; bit++, crc <<= 1) | |
1524 | if (crc & 0x80000000) index |= 1 << bit; | |
1525 | mc_filter[index/16] |= (1 << (index % 16)); | |
1526 | } | |
1527 | rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys; | |
1528 | } else { | |
1529 | iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode); | |
1530 | return; | |
1531 | } | |
1532 | if (np->mii_if.full_duplex && np->flowctrl) | |
1533 | mc_filter[3] |= 0x0200; | |
1534 | ||
1535 | for (i = 0; i < 4; i++) | |
1536 | iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2); | |
1537 | iowrite8(rx_mode, ioaddr + RxMode); | |
1538 | } | |
1539 | ||
1540 | static int __set_mac_addr(struct net_device *dev) | |
1541 | { | |
1542 | struct netdev_private *np = netdev_priv(dev); | |
1543 | u16 addr16; | |
1544 | ||
1545 | addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8)); | |
1546 | iowrite16(addr16, np->base + StationAddr); | |
1547 | addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8)); | |
1548 | iowrite16(addr16, np->base + StationAddr+2); | |
1549 | addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8)); | |
1550 | iowrite16(addr16, np->base + StationAddr+4); | |
1551 | return 0; | |
1552 | } | |
1553 | ||
1554 | static int check_if_running(struct net_device *dev) | |
1555 | { | |
1556 | if (!netif_running(dev)) | |
1557 | return -EINVAL; | |
1558 | return 0; | |
1559 | } | |
1560 | ||
1561 | static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1562 | { | |
1563 | struct netdev_private *np = netdev_priv(dev); | |
1564 | strcpy(info->driver, DRV_NAME); | |
1565 | strcpy(info->version, DRV_VERSION); | |
1566 | strcpy(info->bus_info, pci_name(np->pci_dev)); | |
1567 | } | |
1568 | ||
1569 | static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1570 | { | |
1571 | struct netdev_private *np = netdev_priv(dev); | |
1572 | spin_lock_irq(&np->lock); | |
1573 | mii_ethtool_gset(&np->mii_if, ecmd); | |
1574 | spin_unlock_irq(&np->lock); | |
1575 | return 0; | |
1576 | } | |
1577 | ||
1578 | static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
1579 | { | |
1580 | struct netdev_private *np = netdev_priv(dev); | |
1581 | int res; | |
1582 | spin_lock_irq(&np->lock); | |
1583 | res = mii_ethtool_sset(&np->mii_if, ecmd); | |
1584 | spin_unlock_irq(&np->lock); | |
1585 | return res; | |
1586 | } | |
1587 | ||
1588 | static int nway_reset(struct net_device *dev) | |
1589 | { | |
1590 | struct netdev_private *np = netdev_priv(dev); | |
1591 | return mii_nway_restart(&np->mii_if); | |
1592 | } | |
1593 | ||
1594 | static u32 get_link(struct net_device *dev) | |
1595 | { | |
1596 | struct netdev_private *np = netdev_priv(dev); | |
1597 | return mii_link_ok(&np->mii_if); | |
1598 | } | |
1599 | ||
1600 | static u32 get_msglevel(struct net_device *dev) | |
1601 | { | |
1602 | struct netdev_private *np = netdev_priv(dev); | |
1603 | return np->msg_enable; | |
1604 | } | |
1605 | ||
1606 | static void set_msglevel(struct net_device *dev, u32 val) | |
1607 | { | |
1608 | struct netdev_private *np = netdev_priv(dev); | |
1609 | np->msg_enable = val; | |
1610 | } | |
1611 | ||
7282d491 | 1612 | static const struct ethtool_ops ethtool_ops = { |
1da177e4 LT |
1613 | .begin = check_if_running, |
1614 | .get_drvinfo = get_drvinfo, | |
1615 | .get_settings = get_settings, | |
1616 | .set_settings = set_settings, | |
1617 | .nway_reset = nway_reset, | |
1618 | .get_link = get_link, | |
1619 | .get_msglevel = get_msglevel, | |
1620 | .set_msglevel = set_msglevel, | |
1621 | }; | |
1622 | ||
1623 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1624 | { | |
1625 | struct netdev_private *np = netdev_priv(dev); | |
1da177e4 | 1626 | int rc; |
1da177e4 LT |
1627 | |
1628 | if (!netif_running(dev)) | |
1629 | return -EINVAL; | |
1630 | ||
1631 | spin_lock_irq(&np->lock); | |
1632 | rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL); | |
1633 | spin_unlock_irq(&np->lock); | |
1da177e4 LT |
1634 | |
1635 | return rc; | |
1636 | } | |
1637 | ||
1638 | static int netdev_close(struct net_device *dev) | |
1639 | { | |
1640 | struct netdev_private *np = netdev_priv(dev); | |
1641 | void __iomem *ioaddr = np->base; | |
1642 | struct sk_buff *skb; | |
1643 | int i; | |
1644 | ||
31f817e9 JH |
1645 | /* Wait and kill tasklet */ |
1646 | tasklet_kill(&np->rx_tasklet); | |
1647 | tasklet_kill(&np->tx_tasklet); | |
1648 | np->cur_tx = 0; | |
1649 | np->dirty_tx = 0; | |
1650 | np->cur_task = 0; | |
bca79eb7 | 1651 | np->last_tx = NULL; |
31f817e9 | 1652 | |
1da177e4 LT |
1653 | netif_stop_queue(dev); |
1654 | ||
1655 | if (netif_msg_ifdown(np)) { | |
1656 | printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x " | |
1657 | "Rx %4.4x Int %2.2x.\n", | |
1658 | dev->name, ioread8(ioaddr + TxStatus), | |
1659 | ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus)); | |
1660 | printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", | |
1661 | dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx); | |
1662 | } | |
1663 | ||
1664 | /* Disable interrupts by clearing the interrupt mask. */ | |
1665 | iowrite16(0x0000, ioaddr + IntrEnable); | |
1666 | ||
acd70c2b JH |
1667 | /* Disable Rx and Tx DMA for safely release resource */ |
1668 | iowrite32(0x500, ioaddr + DMACtrl); | |
1669 | ||
1da177e4 LT |
1670 | /* Stop the chip's Tx and Rx processes. */ |
1671 | iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1); | |
1672 | ||
31f817e9 JH |
1673 | for (i = 2000; i > 0; i--) { |
1674 | if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0) | |
1675 | break; | |
1676 | mdelay(1); | |
1677 | } | |
1678 | ||
1679 | iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset, | |
1680 | ioaddr +ASICCtrl + 2); | |
1681 | ||
1682 | for (i = 2000; i > 0; i--) { | |
1683 | if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0) | |
1684 | break; | |
1685 | mdelay(1); | |
1686 | } | |
1da177e4 LT |
1687 | |
1688 | #ifdef __i386__ | |
1689 | if (netif_msg_hw(np)) { | |
1690 | printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n", | |
1691 | (int)(np->tx_ring_dma)); | |
1692 | for (i = 0; i < TX_RING_SIZE; i++) | |
1693 | printk(" #%d desc. %4.4x %8.8x %8.8x.\n", | |
1694 | i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr, | |
1695 | np->tx_ring[i].frag[0].length); | |
1696 | printk("\n"KERN_DEBUG " Rx ring %8.8x:\n", | |
1697 | (int)(np->rx_ring_dma)); | |
1698 | for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) { | |
1699 | printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n", | |
1700 | i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr, | |
1701 | np->rx_ring[i].frag[0].length); | |
1702 | } | |
1703 | } | |
1704 | #endif /* __i386__ debugging only */ | |
1705 | ||
1706 | free_irq(dev->irq, dev); | |
1707 | ||
1708 | del_timer_sync(&np->timer); | |
1709 | ||
1710 | /* Free all the skbuffs in the Rx queue. */ | |
1711 | for (i = 0; i < RX_RING_SIZE; i++) { | |
1712 | np->rx_ring[i].status = 0; | |
1da177e4 LT |
1713 | skb = np->rx_skbuff[i]; |
1714 | if (skb) { | |
1715 | pci_unmap_single(np->pci_dev, | |
14c9d9b0 AV |
1716 | le32_to_cpu(np->rx_ring[i].frag[0].addr), |
1717 | np->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
1da177e4 LT |
1718 | dev_kfree_skb(skb); |
1719 | np->rx_skbuff[i] = NULL; | |
1720 | } | |
14c9d9b0 | 1721 | np->rx_ring[i].frag[0].addr = cpu_to_le32(0xBADF00D0); /* poison */ |
1da177e4 LT |
1722 | } |
1723 | for (i = 0; i < TX_RING_SIZE; i++) { | |
31f817e9 | 1724 | np->tx_ring[i].next_desc = 0; |
1da177e4 LT |
1725 | skb = np->tx_skbuff[i]; |
1726 | if (skb) { | |
1727 | pci_unmap_single(np->pci_dev, | |
14c9d9b0 AV |
1728 | le32_to_cpu(np->tx_ring[i].frag[0].addr), |
1729 | skb->len, PCI_DMA_TODEVICE); | |
1da177e4 LT |
1730 | dev_kfree_skb(skb); |
1731 | np->tx_skbuff[i] = NULL; | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | return 0; | |
1736 | } | |
1737 | ||
1738 | static void __devexit sundance_remove1 (struct pci_dev *pdev) | |
1739 | { | |
1740 | struct net_device *dev = pci_get_drvdata(pdev); | |
1741 | ||
1742 | if (dev) { | |
1743 | struct netdev_private *np = netdev_priv(dev); | |
1744 | ||
1745 | unregister_netdev(dev); | |
1746 | pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, | |
1747 | np->rx_ring_dma); | |
1748 | pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, | |
1749 | np->tx_ring_dma); | |
1750 | pci_iounmap(pdev, np->base); | |
1751 | pci_release_regions(pdev); | |
1752 | free_netdev(dev); | |
1753 | pci_set_drvdata(pdev, NULL); | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | static struct pci_driver sundance_driver = { | |
1758 | .name = DRV_NAME, | |
1759 | .id_table = sundance_pci_tbl, | |
1760 | .probe = sundance_probe1, | |
1761 | .remove = __devexit_p(sundance_remove1), | |
1762 | }; | |
1763 | ||
1764 | static int __init sundance_init(void) | |
1765 | { | |
1766 | /* when a module, this is printed whether or not devices are found in probe */ | |
1767 | #ifdef MODULE | |
1768 | printk(version); | |
1769 | #endif | |
29917620 | 1770 | return pci_register_driver(&sundance_driver); |
1da177e4 LT |
1771 | } |
1772 | ||
1773 | static void __exit sundance_exit(void) | |
1774 | { | |
1775 | pci_unregister_driver(&sundance_driver); | |
1776 | } | |
1777 | ||
1778 | module_init(sundance_init); | |
1779 | module_exit(sundance_exit); | |
1780 | ||
1781 |