Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * tg3.c: Broadcom Tigon3 ethernet driver. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) | |
6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
ba5b0bfa | 7 | * Copyright (C) 2005-2010 Broadcom Corporation. |
1da177e4 LT |
8 | * |
9 | * Firmware is: | |
49cabf49 MC |
10 | * Derived from proprietary unpublished source code, |
11 | * Copyright (C) 2000-2003 Broadcom Corporation. | |
12 | * | |
13 | * Permission is hereby granted for the distribution of this firmware | |
14 | * data in hexadecimal or equivalent format, provided this copyright | |
15 | * notice is accompanying it. | |
1da177e4 LT |
16 | */ |
17 | ||
1da177e4 LT |
18 | |
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/compiler.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/delay.h> | |
14c85021 | 26 | #include <linux/in.h> |
1da177e4 LT |
27 | #include <linux/init.h> |
28 | #include <linux/ioport.h> | |
29 | #include <linux/pci.h> | |
30 | #include <linux/netdevice.h> | |
31 | #include <linux/etherdevice.h> | |
32 | #include <linux/skbuff.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/mii.h> | |
158d7abd | 35 | #include <linux/phy.h> |
a9daf367 | 36 | #include <linux/brcmphy.h> |
1da177e4 LT |
37 | #include <linux/if_vlan.h> |
38 | #include <linux/ip.h> | |
39 | #include <linux/tcp.h> | |
40 | #include <linux/workqueue.h> | |
61487480 | 41 | #include <linux/prefetch.h> |
f9a5f7d3 | 42 | #include <linux/dma-mapping.h> |
077f849d | 43 | #include <linux/firmware.h> |
1da177e4 LT |
44 | |
45 | #include <net/checksum.h> | |
c9bdd4b5 | 46 | #include <net/ip.h> |
1da177e4 LT |
47 | |
48 | #include <asm/system.h> | |
49 | #include <asm/io.h> | |
50 | #include <asm/byteorder.h> | |
51 | #include <asm/uaccess.h> | |
52 | ||
49b6e95f | 53 | #ifdef CONFIG_SPARC |
1da177e4 | 54 | #include <asm/idprom.h> |
49b6e95f | 55 | #include <asm/prom.h> |
1da177e4 LT |
56 | #endif |
57 | ||
63532394 MC |
58 | #define BAR_0 0 |
59 | #define BAR_2 2 | |
60 | ||
1da177e4 LT |
61 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
62 | #define TG3_VLAN_TAG_USED 1 | |
63 | #else | |
64 | #define TG3_VLAN_TAG_USED 0 | |
65 | #endif | |
66 | ||
1da177e4 LT |
67 | #include "tg3.h" |
68 | ||
69 | #define DRV_MODULE_NAME "tg3" | |
7ae554e5 MC |
70 | #define DRV_MODULE_VERSION "3.109" |
71 | #define DRV_MODULE_RELDATE "April 2, 2010" | |
1da177e4 LT |
72 | |
73 | #define TG3_DEF_MAC_MODE 0 | |
74 | #define TG3_DEF_RX_MODE 0 | |
75 | #define TG3_DEF_TX_MODE 0 | |
76 | #define TG3_DEF_MSG_ENABLE \ | |
77 | (NETIF_MSG_DRV | \ | |
78 | NETIF_MSG_PROBE | \ | |
79 | NETIF_MSG_LINK | \ | |
80 | NETIF_MSG_TIMER | \ | |
81 | NETIF_MSG_IFDOWN | \ | |
82 | NETIF_MSG_IFUP | \ | |
83 | NETIF_MSG_RX_ERR | \ | |
84 | NETIF_MSG_TX_ERR) | |
85 | ||
86 | /* length of time before we decide the hardware is borked, | |
87 | * and dev->tx_timeout() should be called to fix the problem | |
88 | */ | |
89 | #define TG3_TX_TIMEOUT (5 * HZ) | |
90 | ||
91 | /* hardware minimum and maximum for a single frame's data payload */ | |
92 | #define TG3_MIN_MTU 60 | |
93 | #define TG3_MAX_MTU(tp) \ | |
8f666b07 | 94 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500) |
1da177e4 LT |
95 | |
96 | /* These numbers seem to be hard coded in the NIC firmware somehow. | |
97 | * You can't change the ring sizes, but you can change where you place | |
98 | * them in the NIC onboard memory. | |
99 | */ | |
100 | #define TG3_RX_RING_SIZE 512 | |
101 | #define TG3_DEF_RX_RING_PENDING 200 | |
102 | #define TG3_RX_JUMBO_RING_SIZE 256 | |
103 | #define TG3_DEF_RX_JUMBO_RING_PENDING 100 | |
c6cdf436 | 104 | #define TG3_RSS_INDIR_TBL_SIZE 128 |
1da177e4 LT |
105 | |
106 | /* Do not place this n-ring entries value into the tp struct itself, | |
107 | * we really want to expose these constants to GCC so that modulo et | |
108 | * al. operations are done with shifts and masks instead of with | |
109 | * hw multiply/modulo instructions. Another solution would be to | |
110 | * replace things like '% foo' with '& (foo - 1)'. | |
111 | */ | |
112 | #define TG3_RX_RCB_RING_SIZE(tp) \ | |
f6eb9b1f | 113 | (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \ |
5ea1c506 | 114 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512) |
1da177e4 LT |
115 | |
116 | #define TG3_TX_RING_SIZE 512 | |
117 | #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) | |
118 | ||
119 | #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \ | |
120 | TG3_RX_RING_SIZE) | |
79ed5ac7 MC |
121 | #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \ |
122 | TG3_RX_JUMBO_RING_SIZE) | |
1da177e4 | 123 | #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \ |
79ed5ac7 | 124 | TG3_RX_RCB_RING_SIZE(tp)) |
1da177e4 LT |
125 | #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \ |
126 | TG3_TX_RING_SIZE) | |
1da177e4 LT |
127 | #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
128 | ||
9dc7a113 MC |
129 | #define TG3_RX_DMA_ALIGN 16 |
130 | #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN) | |
131 | ||
287be12e MC |
132 | #define TG3_DMA_BYTE_ENAB 64 |
133 | ||
134 | #define TG3_RX_STD_DMA_SZ 1536 | |
135 | #define TG3_RX_JMB_DMA_SZ 9046 | |
136 | ||
137 | #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) | |
138 | ||
139 | #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) | |
140 | #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) | |
1da177e4 | 141 | |
2b2cdb65 MC |
142 | #define TG3_RX_STD_BUFF_RING_SIZE \ |
143 | (sizeof(struct ring_info) * TG3_RX_RING_SIZE) | |
144 | ||
145 | #define TG3_RX_JMB_BUFF_RING_SIZE \ | |
146 | (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE) | |
147 | ||
c6cdf436 MC |
148 | #define TG3_RSS_MIN_NUM_MSIX_VECS 2 |
149 | ||
d2757fc4 MC |
150 | /* Due to a hardware bug, the 5701 can only DMA to memory addresses |
151 | * that are at least dword aligned when used in PCIX mode. The driver | |
152 | * works around this bug by double copying the packet. This workaround | |
153 | * is built into the normal double copy length check for efficiency. | |
154 | * | |
155 | * However, the double copy is only necessary on those architectures | |
156 | * where unaligned memory accesses are inefficient. For those architectures | |
157 | * where unaligned memory accesses incur little penalty, we can reintegrate | |
158 | * the 5701 in the normal rx path. Doing so saves a device structure | |
159 | * dereference by hardcoding the double copy threshold in place. | |
160 | */ | |
161 | #define TG3_RX_COPY_THRESHOLD 256 | |
162 | #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) | |
163 | #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD | |
164 | #else | |
165 | #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) | |
166 | #endif | |
167 | ||
1da177e4 | 168 | /* minimum number of free TX descriptors required to wake up TX process */ |
f3f3f27e | 169 | #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
1da177e4 | 170 | |
ad829268 MC |
171 | #define TG3_RAW_IP_ALIGN 2 |
172 | ||
1da177e4 LT |
173 | /* number of ETHTOOL_GSTATS u64's */ |
174 | #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64)) | |
175 | ||
4cafd3f5 MC |
176 | #define TG3_NUM_TEST 6 |
177 | ||
c6cdf436 MC |
178 | #define TG3_FW_UPDATE_TIMEOUT_SEC 5 |
179 | ||
077f849d JSR |
180 | #define FIRMWARE_TG3 "tigon/tg3.bin" |
181 | #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin" | |
182 | #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" | |
183 | ||
1da177e4 | 184 | static char version[] __devinitdata = |
05dbe005 | 185 | DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")"; |
1da177e4 LT |
186 | |
187 | MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)"); | |
188 | MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); | |
189 | MODULE_LICENSE("GPL"); | |
190 | MODULE_VERSION(DRV_MODULE_VERSION); | |
077f849d JSR |
191 | MODULE_FIRMWARE(FIRMWARE_TG3); |
192 | MODULE_FIRMWARE(FIRMWARE_TG3TSO); | |
193 | MODULE_FIRMWARE(FIRMWARE_TG3TSO5); | |
194 | ||
1da177e4 LT |
195 | static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */ |
196 | module_param(tg3_debug, int, 0); | |
197 | MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value"); | |
198 | ||
a3aa1884 | 199 | static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = { |
13185217 HK |
200 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)}, |
201 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)}, | |
202 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)}, | |
203 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)}, | |
204 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)}, | |
205 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)}, | |
206 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)}, | |
207 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)}, | |
208 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)}, | |
209 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)}, | |
210 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)}, | |
211 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)}, | |
212 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)}, | |
213 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)}, | |
214 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)}, | |
215 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)}, | |
216 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)}, | |
217 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)}, | |
218 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)}, | |
219 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)}, | |
220 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)}, | |
221 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)}, | |
222 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)}, | |
223 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)}, | |
126a3368 | 224 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)}, |
13185217 HK |
225 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)}, |
226 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)}, | |
227 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)}, | |
228 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)}, | |
229 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)}, | |
230 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)}, | |
231 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)}, | |
232 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)}, | |
233 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)}, | |
234 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)}, | |
235 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)}, | |
236 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)}, | |
237 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)}, | |
238 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)}, | |
126a3368 | 239 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)}, |
13185217 HK |
240 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)}, |
241 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)}, | |
242 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)}, | |
676917d4 | 243 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)}, |
13185217 HK |
244 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)}, |
245 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)}, | |
246 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)}, | |
247 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)}, | |
248 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)}, | |
249 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)}, | |
250 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)}, | |
b5d3772c MC |
251 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)}, |
252 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)}, | |
d30cdd28 MC |
253 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)}, |
254 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)}, | |
6c7af27c | 255 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)}, |
9936bcf6 MC |
256 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)}, |
257 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)}, | |
c88e668b MC |
258 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)}, |
259 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)}, | |
2befdcea MC |
260 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)}, |
261 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)}, | |
321d32a0 MC |
262 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)}, |
263 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)}, | |
264 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)}, | |
5e7ccf20 | 265 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)}, |
5001e2f6 MC |
266 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)}, |
267 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)}, | |
268 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)}, | |
b0f75221 MC |
269 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)}, |
270 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)}, | |
271 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)}, | |
272 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)}, | |
273 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)}, | |
274 | {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)}, | |
13185217 HK |
275 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)}, |
276 | {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)}, | |
277 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)}, | |
278 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)}, | |
279 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)}, | |
280 | {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)}, | |
281 | {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)}, | |
282 | {} | |
1da177e4 LT |
283 | }; |
284 | ||
285 | MODULE_DEVICE_TABLE(pci, tg3_pci_tbl); | |
286 | ||
50da859d | 287 | static const struct { |
1da177e4 LT |
288 | const char string[ETH_GSTRING_LEN]; |
289 | } ethtool_stats_keys[TG3_NUM_STATS] = { | |
290 | { "rx_octets" }, | |
291 | { "rx_fragments" }, | |
292 | { "rx_ucast_packets" }, | |
293 | { "rx_mcast_packets" }, | |
294 | { "rx_bcast_packets" }, | |
295 | { "rx_fcs_errors" }, | |
296 | { "rx_align_errors" }, | |
297 | { "rx_xon_pause_rcvd" }, | |
298 | { "rx_xoff_pause_rcvd" }, | |
299 | { "rx_mac_ctrl_rcvd" }, | |
300 | { "rx_xoff_entered" }, | |
301 | { "rx_frame_too_long_errors" }, | |
302 | { "rx_jabbers" }, | |
303 | { "rx_undersize_packets" }, | |
304 | { "rx_in_length_errors" }, | |
305 | { "rx_out_length_errors" }, | |
306 | { "rx_64_or_less_octet_packets" }, | |
307 | { "rx_65_to_127_octet_packets" }, | |
308 | { "rx_128_to_255_octet_packets" }, | |
309 | { "rx_256_to_511_octet_packets" }, | |
310 | { "rx_512_to_1023_octet_packets" }, | |
311 | { "rx_1024_to_1522_octet_packets" }, | |
312 | { "rx_1523_to_2047_octet_packets" }, | |
313 | { "rx_2048_to_4095_octet_packets" }, | |
314 | { "rx_4096_to_8191_octet_packets" }, | |
315 | { "rx_8192_to_9022_octet_packets" }, | |
316 | ||
317 | { "tx_octets" }, | |
318 | { "tx_collisions" }, | |
319 | ||
320 | { "tx_xon_sent" }, | |
321 | { "tx_xoff_sent" }, | |
322 | { "tx_flow_control" }, | |
323 | { "tx_mac_errors" }, | |
324 | { "tx_single_collisions" }, | |
325 | { "tx_mult_collisions" }, | |
326 | { "tx_deferred" }, | |
327 | { "tx_excessive_collisions" }, | |
328 | { "tx_late_collisions" }, | |
329 | { "tx_collide_2times" }, | |
330 | { "tx_collide_3times" }, | |
331 | { "tx_collide_4times" }, | |
332 | { "tx_collide_5times" }, | |
333 | { "tx_collide_6times" }, | |
334 | { "tx_collide_7times" }, | |
335 | { "tx_collide_8times" }, | |
336 | { "tx_collide_9times" }, | |
337 | { "tx_collide_10times" }, | |
338 | { "tx_collide_11times" }, | |
339 | { "tx_collide_12times" }, | |
340 | { "tx_collide_13times" }, | |
341 | { "tx_collide_14times" }, | |
342 | { "tx_collide_15times" }, | |
343 | { "tx_ucast_packets" }, | |
344 | { "tx_mcast_packets" }, | |
345 | { "tx_bcast_packets" }, | |
346 | { "tx_carrier_sense_errors" }, | |
347 | { "tx_discards" }, | |
348 | { "tx_errors" }, | |
349 | ||
350 | { "dma_writeq_full" }, | |
351 | { "dma_write_prioq_full" }, | |
352 | { "rxbds_empty" }, | |
353 | { "rx_discards" }, | |
354 | { "rx_errors" }, | |
355 | { "rx_threshold_hit" }, | |
356 | ||
357 | { "dma_readq_full" }, | |
358 | { "dma_read_prioq_full" }, | |
359 | { "tx_comp_queue_full" }, | |
360 | ||
361 | { "ring_set_send_prod_index" }, | |
362 | { "ring_status_update" }, | |
363 | { "nic_irqs" }, | |
364 | { "nic_avoided_irqs" }, | |
365 | { "nic_tx_threshold_hit" } | |
366 | }; | |
367 | ||
50da859d | 368 | static const struct { |
4cafd3f5 MC |
369 | const char string[ETH_GSTRING_LEN]; |
370 | } ethtool_test_keys[TG3_NUM_TEST] = { | |
371 | { "nvram test (online) " }, | |
372 | { "link test (online) " }, | |
373 | { "register test (offline)" }, | |
374 | { "memory test (offline)" }, | |
375 | { "loopback test (offline)" }, | |
376 | { "interrupt test (offline)" }, | |
377 | }; | |
378 | ||
b401e9e2 MC |
379 | static void tg3_write32(struct tg3 *tp, u32 off, u32 val) |
380 | { | |
381 | writel(val, tp->regs + off); | |
382 | } | |
383 | ||
384 | static u32 tg3_read32(struct tg3 *tp, u32 off) | |
385 | { | |
de6f31eb | 386 | return readl(tp->regs + off); |
b401e9e2 MC |
387 | } |
388 | ||
0d3031d9 MC |
389 | static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) |
390 | { | |
391 | writel(val, tp->aperegs + off); | |
392 | } | |
393 | ||
394 | static u32 tg3_ape_read32(struct tg3 *tp, u32 off) | |
395 | { | |
de6f31eb | 396 | return readl(tp->aperegs + off); |
0d3031d9 MC |
397 | } |
398 | ||
1da177e4 LT |
399 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
400 | { | |
6892914f MC |
401 | unsigned long flags; |
402 | ||
403 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
1ee582d8 MC |
404 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); |
405 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
6892914f | 406 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1ee582d8 MC |
407 | } |
408 | ||
409 | static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) | |
410 | { | |
411 | writel(val, tp->regs + off); | |
412 | readl(tp->regs + off); | |
1da177e4 LT |
413 | } |
414 | ||
6892914f | 415 | static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) |
1da177e4 | 416 | { |
6892914f MC |
417 | unsigned long flags; |
418 | u32 val; | |
419 | ||
420 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
421 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); | |
422 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
423 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
424 | return val; | |
425 | } | |
426 | ||
427 | static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) | |
428 | { | |
429 | unsigned long flags; | |
430 | ||
431 | if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) { | |
432 | pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + | |
433 | TG3_64BIT_REG_LOW, val); | |
434 | return; | |
435 | } | |
66711e66 | 436 | if (off == TG3_RX_STD_PROD_IDX_REG) { |
6892914f MC |
437 | pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + |
438 | TG3_64BIT_REG_LOW, val); | |
439 | return; | |
1da177e4 | 440 | } |
6892914f MC |
441 | |
442 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
443 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
444 | pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); | |
445 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
446 | ||
447 | /* In indirect mode when disabling interrupts, we also need | |
448 | * to clear the interrupt bit in the GRC local ctrl register. | |
449 | */ | |
450 | if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) && | |
451 | (val == 0x1)) { | |
452 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, | |
453 | tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); | |
454 | } | |
455 | } | |
456 | ||
457 | static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) | |
458 | { | |
459 | unsigned long flags; | |
460 | u32 val; | |
461 | ||
462 | spin_lock_irqsave(&tp->indirect_lock, flags); | |
463 | pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); | |
464 | pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); | |
465 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
466 | return val; | |
467 | } | |
468 | ||
b401e9e2 MC |
469 | /* usec_wait specifies the wait time in usec when writing to certain registers |
470 | * where it is unsafe to read back the register without some delay. | |
471 | * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power. | |
472 | * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed. | |
473 | */ | |
474 | static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) | |
6892914f | 475 | { |
b401e9e2 MC |
476 | if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) || |
477 | (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
478 | /* Non-posted methods */ | |
479 | tp->write32(tp, off, val); | |
480 | else { | |
481 | /* Posted method */ | |
482 | tg3_write32(tp, off, val); | |
483 | if (usec_wait) | |
484 | udelay(usec_wait); | |
485 | tp->read32(tp, off); | |
486 | } | |
487 | /* Wait again after the read for the posted method to guarantee that | |
488 | * the wait time is met. | |
489 | */ | |
490 | if (usec_wait) | |
491 | udelay(usec_wait); | |
1da177e4 LT |
492 | } |
493 | ||
09ee929c MC |
494 | static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) |
495 | { | |
496 | tp->write32_mbox(tp, off, val); | |
6892914f MC |
497 | if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) && |
498 | !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND)) | |
499 | tp->read32_mbox(tp, off); | |
09ee929c MC |
500 | } |
501 | ||
20094930 | 502 | static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) |
1da177e4 LT |
503 | { |
504 | void __iomem *mbox = tp->regs + off; | |
505 | writel(val, mbox); | |
506 | if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) | |
507 | writel(val, mbox); | |
508 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
509 | readl(mbox); | |
510 | } | |
511 | ||
b5d3772c MC |
512 | static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) |
513 | { | |
de6f31eb | 514 | return readl(tp->regs + off + GRCMBOX_BASE); |
b5d3772c MC |
515 | } |
516 | ||
517 | static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) | |
518 | { | |
519 | writel(val, tp->regs + off + GRCMBOX_BASE); | |
520 | } | |
521 | ||
c6cdf436 | 522 | #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
09ee929c | 523 | #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
c6cdf436 MC |
524 | #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
525 | #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) | |
526 | #define tr32_mailbox(reg) tp->read32_mbox(tp, reg) | |
20094930 | 527 | |
c6cdf436 MC |
528 | #define tw32(reg, val) tp->write32(tp, reg, val) |
529 | #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) | |
530 | #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) | |
531 | #define tr32(reg) tp->read32(tp, reg) | |
1da177e4 LT |
532 | |
533 | static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) | |
534 | { | |
6892914f MC |
535 | unsigned long flags; |
536 | ||
b5d3772c MC |
537 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
538 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) | |
539 | return; | |
540 | ||
6892914f | 541 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
542 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
543 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
544 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 545 | |
bbadf503 MC |
546 | /* Always leave this as zero. */ |
547 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
548 | } else { | |
549 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
550 | tw32_f(TG3PCI_MEM_WIN_DATA, val); | |
28fbef78 | 551 | |
bbadf503 MC |
552 | /* Always leave this as zero. */ |
553 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
554 | } | |
555 | spin_unlock_irqrestore(&tp->indirect_lock, flags); | |
758a6139 DM |
556 | } |
557 | ||
1da177e4 LT |
558 | static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) |
559 | { | |
6892914f MC |
560 | unsigned long flags; |
561 | ||
b5d3772c MC |
562 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) && |
563 | (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) { | |
564 | *val = 0; | |
565 | return; | |
566 | } | |
567 | ||
6892914f | 568 | spin_lock_irqsave(&tp->indirect_lock, flags); |
bbadf503 MC |
569 | if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) { |
570 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); | |
571 | pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
1da177e4 | 572 | |
bbadf503 MC |
573 | /* Always leave this as zero. */ |
574 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
575 | } else { | |
576 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off); | |
577 | *val = tr32(TG3PCI_MEM_WIN_DATA); | |
578 | ||
579 | /* Always leave this as zero. */ | |
580 | tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
581 | } | |
6892914f | 582 | spin_unlock_irqrestore(&tp->indirect_lock, flags); |
1da177e4 LT |
583 | } |
584 | ||
0d3031d9 MC |
585 | static void tg3_ape_lock_init(struct tg3 *tp) |
586 | { | |
587 | int i; | |
588 | ||
589 | /* Make sure the driver hasn't any stale locks. */ | |
590 | for (i = 0; i < 8; i++) | |
591 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i, | |
592 | APE_LOCK_GRANT_DRIVER); | |
593 | } | |
594 | ||
595 | static int tg3_ape_lock(struct tg3 *tp, int locknum) | |
596 | { | |
597 | int i, off; | |
598 | int ret = 0; | |
599 | u32 status; | |
600 | ||
601 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
602 | return 0; | |
603 | ||
604 | switch (locknum) { | |
33f401ae MC |
605 | case TG3_APE_LOCK_GRC: |
606 | case TG3_APE_LOCK_MEM: | |
607 | break; | |
608 | default: | |
609 | return -EINVAL; | |
0d3031d9 MC |
610 | } |
611 | ||
612 | off = 4 * locknum; | |
613 | ||
614 | tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER); | |
615 | ||
616 | /* Wait for up to 1 millisecond to acquire lock. */ | |
617 | for (i = 0; i < 100; i++) { | |
618 | status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off); | |
619 | if (status == APE_LOCK_GRANT_DRIVER) | |
620 | break; | |
621 | udelay(10); | |
622 | } | |
623 | ||
624 | if (status != APE_LOCK_GRANT_DRIVER) { | |
625 | /* Revoke the lock request. */ | |
626 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, | |
627 | APE_LOCK_GRANT_DRIVER); | |
628 | ||
629 | ret = -EBUSY; | |
630 | } | |
631 | ||
632 | return ret; | |
633 | } | |
634 | ||
635 | static void tg3_ape_unlock(struct tg3 *tp, int locknum) | |
636 | { | |
637 | int off; | |
638 | ||
639 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
640 | return; | |
641 | ||
642 | switch (locknum) { | |
33f401ae MC |
643 | case TG3_APE_LOCK_GRC: |
644 | case TG3_APE_LOCK_MEM: | |
645 | break; | |
646 | default: | |
647 | return; | |
0d3031d9 MC |
648 | } |
649 | ||
650 | off = 4 * locknum; | |
651 | tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER); | |
652 | } | |
653 | ||
1da177e4 LT |
654 | static void tg3_disable_ints(struct tg3 *tp) |
655 | { | |
89aeb3bc MC |
656 | int i; |
657 | ||
1da177e4 LT |
658 | tw32(TG3PCI_MISC_HOST_CTRL, |
659 | (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc MC |
660 | for (i = 0; i < tp->irq_max; i++) |
661 | tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); | |
1da177e4 LT |
662 | } |
663 | ||
1da177e4 LT |
664 | static void tg3_enable_ints(struct tg3 *tp) |
665 | { | |
89aeb3bc | 666 | int i; |
89aeb3bc | 667 | |
bbe832c0 MC |
668 | tp->irq_sync = 0; |
669 | wmb(); | |
670 | ||
1da177e4 LT |
671 | tw32(TG3PCI_MISC_HOST_CTRL, |
672 | (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); | |
89aeb3bc | 673 | |
f89f38b8 | 674 | tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; |
89aeb3bc MC |
675 | for (i = 0; i < tp->irq_cnt; i++) { |
676 | struct tg3_napi *tnapi = &tp->napi[i]; | |
c6cdf436 | 677 | |
898a56f8 | 678 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); |
89aeb3bc MC |
679 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) |
680 | tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); | |
f19af9c2 | 681 | |
f89f38b8 | 682 | tp->coal_now |= tnapi->coal_now; |
89aeb3bc | 683 | } |
f19af9c2 MC |
684 | |
685 | /* Force an initial interrupt */ | |
686 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
687 | (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) | |
688 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
689 | else | |
f89f38b8 MC |
690 | tw32(HOSTCC_MODE, tp->coal_now); |
691 | ||
692 | tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); | |
1da177e4 LT |
693 | } |
694 | ||
17375d25 | 695 | static inline unsigned int tg3_has_work(struct tg3_napi *tnapi) |
04237ddd | 696 | { |
17375d25 | 697 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 698 | struct tg3_hw_status *sblk = tnapi->hw_status; |
04237ddd MC |
699 | unsigned int work_exists = 0; |
700 | ||
701 | /* check for phy events */ | |
702 | if (!(tp->tg3_flags & | |
703 | (TG3_FLAG_USE_LINKCHG_REG | | |
704 | TG3_FLAG_POLL_SERDES))) { | |
705 | if (sblk->status & SD_STATUS_LINK_CHG) | |
706 | work_exists = 1; | |
707 | } | |
708 | /* check for RX/TX work to do */ | |
f3f3f27e | 709 | if (sblk->idx[0].tx_consumer != tnapi->tx_cons || |
8d9d7cfc | 710 | *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
04237ddd MC |
711 | work_exists = 1; |
712 | ||
713 | return work_exists; | |
714 | } | |
715 | ||
17375d25 | 716 | /* tg3_int_reenable |
04237ddd MC |
717 | * similar to tg3_enable_ints, but it accurately determines whether there |
718 | * is new work pending and can return without flushing the PIO write | |
6aa20a22 | 719 | * which reenables interrupts |
1da177e4 | 720 | */ |
17375d25 | 721 | static void tg3_int_reenable(struct tg3_napi *tnapi) |
1da177e4 | 722 | { |
17375d25 MC |
723 | struct tg3 *tp = tnapi->tp; |
724 | ||
898a56f8 | 725 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); |
1da177e4 LT |
726 | mmiowb(); |
727 | ||
fac9b83e DM |
728 | /* When doing tagged status, this work check is unnecessary. |
729 | * The last_tag we write above tells the chip which piece of | |
730 | * work we've completed. | |
731 | */ | |
732 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) && | |
17375d25 | 733 | tg3_has_work(tnapi)) |
04237ddd | 734 | tw32(HOSTCC_MODE, tp->coalesce_mode | |
fd2ce37f | 735 | HOSTCC_MODE_ENABLE | tnapi->coal_now); |
1da177e4 LT |
736 | } |
737 | ||
fed97810 MC |
738 | static void tg3_napi_disable(struct tg3 *tp) |
739 | { | |
740 | int i; | |
741 | ||
742 | for (i = tp->irq_cnt - 1; i >= 0; i--) | |
743 | napi_disable(&tp->napi[i].napi); | |
744 | } | |
745 | ||
746 | static void tg3_napi_enable(struct tg3 *tp) | |
747 | { | |
748 | int i; | |
749 | ||
750 | for (i = 0; i < tp->irq_cnt; i++) | |
751 | napi_enable(&tp->napi[i].napi); | |
752 | } | |
753 | ||
1da177e4 LT |
754 | static inline void tg3_netif_stop(struct tg3 *tp) |
755 | { | |
bbe832c0 | 756 | tp->dev->trans_start = jiffies; /* prevent tx timeout */ |
fed97810 | 757 | tg3_napi_disable(tp); |
1da177e4 LT |
758 | netif_tx_disable(tp->dev); |
759 | } | |
760 | ||
761 | static inline void tg3_netif_start(struct tg3 *tp) | |
762 | { | |
fe5f5787 MC |
763 | /* NOTE: unconditional netif_tx_wake_all_queues is only |
764 | * appropriate so long as all callers are assured to | |
765 | * have free tx slots (such as after tg3_init_hw) | |
1da177e4 | 766 | */ |
fe5f5787 MC |
767 | netif_tx_wake_all_queues(tp->dev); |
768 | ||
fed97810 MC |
769 | tg3_napi_enable(tp); |
770 | tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; | |
f47c11ee | 771 | tg3_enable_ints(tp); |
1da177e4 LT |
772 | } |
773 | ||
774 | static void tg3_switch_clocks(struct tg3 *tp) | |
775 | { | |
f6eb9b1f | 776 | u32 clock_ctrl; |
1da177e4 LT |
777 | u32 orig_clock_ctrl; |
778 | ||
795d01c5 MC |
779 | if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
780 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) | |
4cf78e4f MC |
781 | return; |
782 | ||
f6eb9b1f MC |
783 | clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); |
784 | ||
1da177e4 LT |
785 | orig_clock_ctrl = clock_ctrl; |
786 | clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | | |
787 | CLOCK_CTRL_CLKRUN_OENABLE | | |
788 | 0x1f); | |
789 | tp->pci_clock_ctrl = clock_ctrl; | |
790 | ||
791 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
792 | if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) { | |
b401e9e2 MC |
793 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
794 | clock_ctrl | CLOCK_CTRL_625_CORE, 40); | |
1da177e4 LT |
795 | } |
796 | } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) { | |
b401e9e2 MC |
797 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
798 | clock_ctrl | | |
799 | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK), | |
800 | 40); | |
801 | tw32_wait_f(TG3PCI_CLOCK_CTRL, | |
802 | clock_ctrl | (CLOCK_CTRL_ALTCLK), | |
803 | 40); | |
1da177e4 | 804 | } |
b401e9e2 | 805 | tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40); |
1da177e4 LT |
806 | } |
807 | ||
808 | #define PHY_BUSY_LOOPS 5000 | |
809 | ||
810 | static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |
811 | { | |
812 | u32 frame_val; | |
813 | unsigned int loops; | |
814 | int ret; | |
815 | ||
816 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
817 | tw32_f(MAC_MI_MODE, | |
818 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
819 | udelay(80); | |
820 | } | |
821 | ||
822 | *val = 0x0; | |
823 | ||
882e9793 | 824 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
825 | MI_COM_PHY_ADDR_MASK); |
826 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
827 | MI_COM_REG_ADDR_MASK); | |
828 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | |
6aa20a22 | 829 | |
1da177e4 LT |
830 | tw32_f(MAC_MI_COM, frame_val); |
831 | ||
832 | loops = PHY_BUSY_LOOPS; | |
833 | while (loops != 0) { | |
834 | udelay(10); | |
835 | frame_val = tr32(MAC_MI_COM); | |
836 | ||
837 | if ((frame_val & MI_COM_BUSY) == 0) { | |
838 | udelay(5); | |
839 | frame_val = tr32(MAC_MI_COM); | |
840 | break; | |
841 | } | |
842 | loops -= 1; | |
843 | } | |
844 | ||
845 | ret = -EBUSY; | |
846 | if (loops != 0) { | |
847 | *val = frame_val & MI_COM_DATA_MASK; | |
848 | ret = 0; | |
849 | } | |
850 | ||
851 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
852 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
853 | udelay(80); | |
854 | } | |
855 | ||
856 | return ret; | |
857 | } | |
858 | ||
859 | static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |
860 | { | |
861 | u32 frame_val; | |
862 | unsigned int loops; | |
863 | int ret; | |
864 | ||
7f97a4bd | 865 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
b5d3772c MC |
866 | (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL)) |
867 | return 0; | |
868 | ||
1da177e4 LT |
869 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
870 | tw32_f(MAC_MI_MODE, | |
871 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
872 | udelay(80); | |
873 | } | |
874 | ||
882e9793 | 875 | frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) & |
1da177e4 LT |
876 | MI_COM_PHY_ADDR_MASK); |
877 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | |
878 | MI_COM_REG_ADDR_MASK); | |
879 | frame_val |= (val & MI_COM_DATA_MASK); | |
880 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | |
6aa20a22 | 881 | |
1da177e4 LT |
882 | tw32_f(MAC_MI_COM, frame_val); |
883 | ||
884 | loops = PHY_BUSY_LOOPS; | |
885 | while (loops != 0) { | |
886 | udelay(10); | |
887 | frame_val = tr32(MAC_MI_COM); | |
888 | if ((frame_val & MI_COM_BUSY) == 0) { | |
889 | udelay(5); | |
890 | frame_val = tr32(MAC_MI_COM); | |
891 | break; | |
892 | } | |
893 | loops -= 1; | |
894 | } | |
895 | ||
896 | ret = -EBUSY; | |
897 | if (loops != 0) | |
898 | ret = 0; | |
899 | ||
900 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { | |
901 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
902 | udelay(80); | |
903 | } | |
904 | ||
905 | return ret; | |
906 | } | |
907 | ||
95e2869a MC |
908 | static int tg3_bmcr_reset(struct tg3 *tp) |
909 | { | |
910 | u32 phy_control; | |
911 | int limit, err; | |
912 | ||
913 | /* OK, reset it, and poll the BMCR_RESET bit until it | |
914 | * clears or we time out. | |
915 | */ | |
916 | phy_control = BMCR_RESET; | |
917 | err = tg3_writephy(tp, MII_BMCR, phy_control); | |
918 | if (err != 0) | |
919 | return -EBUSY; | |
920 | ||
921 | limit = 5000; | |
922 | while (limit--) { | |
923 | err = tg3_readphy(tp, MII_BMCR, &phy_control); | |
924 | if (err != 0) | |
925 | return -EBUSY; | |
926 | ||
927 | if ((phy_control & BMCR_RESET) == 0) { | |
928 | udelay(40); | |
929 | break; | |
930 | } | |
931 | udelay(10); | |
932 | } | |
d4675b52 | 933 | if (limit < 0) |
95e2869a MC |
934 | return -EBUSY; |
935 | ||
936 | return 0; | |
937 | } | |
938 | ||
158d7abd MC |
939 | static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg) |
940 | { | |
3d16543d | 941 | struct tg3 *tp = bp->priv; |
158d7abd MC |
942 | u32 val; |
943 | ||
24bb4fb6 | 944 | spin_lock_bh(&tp->lock); |
158d7abd MC |
945 | |
946 | if (tg3_readphy(tp, reg, &val)) | |
24bb4fb6 MC |
947 | val = -EIO; |
948 | ||
949 | spin_unlock_bh(&tp->lock); | |
158d7abd MC |
950 | |
951 | return val; | |
952 | } | |
953 | ||
954 | static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val) | |
955 | { | |
3d16543d | 956 | struct tg3 *tp = bp->priv; |
24bb4fb6 | 957 | u32 ret = 0; |
158d7abd | 958 | |
24bb4fb6 | 959 | spin_lock_bh(&tp->lock); |
158d7abd MC |
960 | |
961 | if (tg3_writephy(tp, reg, val)) | |
24bb4fb6 | 962 | ret = -EIO; |
158d7abd | 963 | |
24bb4fb6 MC |
964 | spin_unlock_bh(&tp->lock); |
965 | ||
966 | return ret; | |
158d7abd MC |
967 | } |
968 | ||
969 | static int tg3_mdio_reset(struct mii_bus *bp) | |
970 | { | |
971 | return 0; | |
972 | } | |
973 | ||
9c61d6bc | 974 | static void tg3_mdio_config_5785(struct tg3 *tp) |
a9daf367 MC |
975 | { |
976 | u32 val; | |
fcb389df | 977 | struct phy_device *phydev; |
a9daf367 | 978 | |
3f0e3ad7 | 979 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
fcb389df | 980 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { |
6a443a0f MC |
981 | case PHY_ID_BCM50610: |
982 | case PHY_ID_BCM50610M: | |
fcb389df MC |
983 | val = MAC_PHYCFG2_50610_LED_MODES; |
984 | break; | |
6a443a0f | 985 | case PHY_ID_BCMAC131: |
fcb389df MC |
986 | val = MAC_PHYCFG2_AC131_LED_MODES; |
987 | break; | |
6a443a0f | 988 | case PHY_ID_RTL8211C: |
fcb389df MC |
989 | val = MAC_PHYCFG2_RTL8211C_LED_MODES; |
990 | break; | |
6a443a0f | 991 | case PHY_ID_RTL8201E: |
fcb389df MC |
992 | val = MAC_PHYCFG2_RTL8201E_LED_MODES; |
993 | break; | |
994 | default: | |
a9daf367 | 995 | return; |
fcb389df MC |
996 | } |
997 | ||
998 | if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { | |
999 | tw32(MAC_PHYCFG2, val); | |
1000 | ||
1001 | val = tr32(MAC_PHYCFG1); | |
bb85fbb6 MC |
1002 | val &= ~(MAC_PHYCFG1_RGMII_INT | |
1003 | MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK); | |
1004 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT; | |
fcb389df MC |
1005 | tw32(MAC_PHYCFG1, val); |
1006 | ||
1007 | return; | |
1008 | } | |
1009 | ||
14417063 | 1010 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) |
fcb389df MC |
1011 | val |= MAC_PHYCFG2_EMODE_MASK_MASK | |
1012 | MAC_PHYCFG2_FMODE_MASK_MASK | | |
1013 | MAC_PHYCFG2_GMODE_MASK_MASK | | |
1014 | MAC_PHYCFG2_ACT_MASK_MASK | | |
1015 | MAC_PHYCFG2_QUAL_MASK_MASK | | |
1016 | MAC_PHYCFG2_INBAND_ENABLE; | |
1017 | ||
1018 | tw32(MAC_PHYCFG2, val); | |
a9daf367 | 1019 | |
bb85fbb6 MC |
1020 | val = tr32(MAC_PHYCFG1); |
1021 | val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK | | |
1022 | MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN); | |
14417063 | 1023 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
1024 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1025 | val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC; | |
1026 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1027 | val |= MAC_PHYCFG1_RGMII_SND_STAT_EN; | |
1028 | } | |
bb85fbb6 MC |
1029 | val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT | |
1030 | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV; | |
1031 | tw32(MAC_PHYCFG1, val); | |
a9daf367 | 1032 | |
a9daf367 MC |
1033 | val = tr32(MAC_EXT_RGMII_MODE); |
1034 | val &= ~(MAC_RGMII_MODE_RX_INT_B | | |
1035 | MAC_RGMII_MODE_RX_QUALITY | | |
1036 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1037 | MAC_RGMII_MODE_RX_ENG_DET | | |
1038 | MAC_RGMII_MODE_TX_ENABLE | | |
1039 | MAC_RGMII_MODE_TX_LOWPWR | | |
1040 | MAC_RGMII_MODE_TX_RESET); | |
14417063 | 1041 | if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) { |
a9daf367 MC |
1042 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) |
1043 | val |= MAC_RGMII_MODE_RX_INT_B | | |
1044 | MAC_RGMII_MODE_RX_QUALITY | | |
1045 | MAC_RGMII_MODE_RX_ACTIVITY | | |
1046 | MAC_RGMII_MODE_RX_ENG_DET; | |
1047 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1048 | val |= MAC_RGMII_MODE_TX_ENABLE | | |
1049 | MAC_RGMII_MODE_TX_LOWPWR | | |
1050 | MAC_RGMII_MODE_TX_RESET; | |
1051 | } | |
1052 | tw32(MAC_EXT_RGMII_MODE, val); | |
1053 | } | |
1054 | ||
158d7abd MC |
1055 | static void tg3_mdio_start(struct tg3 *tp) |
1056 | { | |
158d7abd MC |
1057 | tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; |
1058 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
1059 | udelay(80); | |
a9daf367 | 1060 | |
9ea4818d MC |
1061 | if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) && |
1062 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1063 | tg3_mdio_config_5785(tp); | |
1064 | } | |
1065 | ||
1066 | static int tg3_mdio_init(struct tg3 *tp) | |
1067 | { | |
1068 | int i; | |
1069 | u32 reg; | |
1070 | struct phy_device *phydev; | |
1071 | ||
882e9793 MC |
1072 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
1073 | u32 funcnum, is_serdes; | |
1074 | ||
1075 | funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC; | |
1076 | if (funcnum) | |
1077 | tp->phy_addr = 2; | |
1078 | else | |
1079 | tp->phy_addr = 1; | |
1080 | ||
d1ec96af MC |
1081 | if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) |
1082 | is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; | |
1083 | else | |
1084 | is_serdes = tr32(TG3_CPMU_PHY_STRAP) & | |
1085 | TG3_CPMU_PHY_STRAP_IS_SERDES; | |
882e9793 MC |
1086 | if (is_serdes) |
1087 | tp->phy_addr += 7; | |
1088 | } else | |
3f0e3ad7 | 1089 | tp->phy_addr = TG3_PHY_MII_ADDR; |
882e9793 | 1090 | |
158d7abd MC |
1091 | tg3_mdio_start(tp); |
1092 | ||
1093 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) || | |
1094 | (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED)) | |
1095 | return 0; | |
1096 | ||
298cf9be LB |
1097 | tp->mdio_bus = mdiobus_alloc(); |
1098 | if (tp->mdio_bus == NULL) | |
1099 | return -ENOMEM; | |
158d7abd | 1100 | |
298cf9be LB |
1101 | tp->mdio_bus->name = "tg3 mdio bus"; |
1102 | snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", | |
158d7abd | 1103 | (tp->pdev->bus->number << 8) | tp->pdev->devfn); |
298cf9be LB |
1104 | tp->mdio_bus->priv = tp; |
1105 | tp->mdio_bus->parent = &tp->pdev->dev; | |
1106 | tp->mdio_bus->read = &tg3_mdio_read; | |
1107 | tp->mdio_bus->write = &tg3_mdio_write; | |
1108 | tp->mdio_bus->reset = &tg3_mdio_reset; | |
3f0e3ad7 | 1109 | tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR); |
298cf9be | 1110 | tp->mdio_bus->irq = &tp->mdio_irq[0]; |
158d7abd MC |
1111 | |
1112 | for (i = 0; i < PHY_MAX_ADDR; i++) | |
298cf9be | 1113 | tp->mdio_bus->irq[i] = PHY_POLL; |
158d7abd MC |
1114 | |
1115 | /* The bus registration will look for all the PHYs on the mdio bus. | |
1116 | * Unfortunately, it does not ensure the PHY is powered up before | |
1117 | * accessing the PHY ID registers. A chip reset is the | |
1118 | * quickest way to bring the device back to an operational state.. | |
1119 | */ | |
1120 | if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) | |
1121 | tg3_bmcr_reset(tp); | |
1122 | ||
298cf9be | 1123 | i = mdiobus_register(tp->mdio_bus); |
a9daf367 | 1124 | if (i) { |
ab96b241 | 1125 | dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); |
9c61d6bc | 1126 | mdiobus_free(tp->mdio_bus); |
a9daf367 MC |
1127 | return i; |
1128 | } | |
158d7abd | 1129 | |
3f0e3ad7 | 1130 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
a9daf367 | 1131 | |
9c61d6bc | 1132 | if (!phydev || !phydev->drv) { |
ab96b241 | 1133 | dev_warn(&tp->pdev->dev, "No PHY devices\n"); |
9c61d6bc MC |
1134 | mdiobus_unregister(tp->mdio_bus); |
1135 | mdiobus_free(tp->mdio_bus); | |
1136 | return -ENODEV; | |
1137 | } | |
1138 | ||
1139 | switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { | |
6a443a0f | 1140 | case PHY_ID_BCM57780: |
321d32a0 | 1141 | phydev->interface = PHY_INTERFACE_MODE_GMII; |
c704dc23 | 1142 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
321d32a0 | 1143 | break; |
6a443a0f MC |
1144 | case PHY_ID_BCM50610: |
1145 | case PHY_ID_BCM50610M: | |
32e5a8d6 | 1146 | phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | |
c704dc23 | 1147 | PHY_BRCM_RX_REFCLK_UNUSED | |
52fae083 | 1148 | PHY_BRCM_DIS_TXCRXC_NOENRGY | |
c704dc23 | 1149 | PHY_BRCM_AUTO_PWRDWN_ENABLE; |
14417063 | 1150 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE) |
a9daf367 MC |
1151 | phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE; |
1152 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN) | |
1153 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE; | |
1154 | if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN) | |
1155 | phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE; | |
fcb389df | 1156 | /* fallthru */ |
6a443a0f | 1157 | case PHY_ID_RTL8211C: |
fcb389df | 1158 | phydev->interface = PHY_INTERFACE_MODE_RGMII; |
a9daf367 | 1159 | break; |
6a443a0f MC |
1160 | case PHY_ID_RTL8201E: |
1161 | case PHY_ID_BCMAC131: | |
a9daf367 | 1162 | phydev->interface = PHY_INTERFACE_MODE_MII; |
cdd4e09d | 1163 | phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; |
7f97a4bd | 1164 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; |
a9daf367 MC |
1165 | break; |
1166 | } | |
1167 | ||
9c61d6bc MC |
1168 | tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED; |
1169 | ||
1170 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1171 | tg3_mdio_config_5785(tp); | |
a9daf367 MC |
1172 | |
1173 | return 0; | |
158d7abd MC |
1174 | } |
1175 | ||
1176 | static void tg3_mdio_fini(struct tg3 *tp) | |
1177 | { | |
1178 | if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) { | |
1179 | tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED; | |
298cf9be LB |
1180 | mdiobus_unregister(tp->mdio_bus); |
1181 | mdiobus_free(tp->mdio_bus); | |
158d7abd MC |
1182 | } |
1183 | } | |
1184 | ||
4ba526ce MC |
1185 | /* tp->lock is held. */ |
1186 | static inline void tg3_generate_fw_event(struct tg3 *tp) | |
1187 | { | |
1188 | u32 val; | |
1189 | ||
1190 | val = tr32(GRC_RX_CPU_EVENT); | |
1191 | val |= GRC_RX_CPU_DRIVER_EVENT; | |
1192 | tw32_f(GRC_RX_CPU_EVENT, val); | |
1193 | ||
1194 | tp->last_event_jiffies = jiffies; | |
1195 | } | |
1196 | ||
1197 | #define TG3_FW_EVENT_TIMEOUT_USEC 2500 | |
1198 | ||
95e2869a MC |
1199 | /* tp->lock is held. */ |
1200 | static void tg3_wait_for_event_ack(struct tg3 *tp) | |
1201 | { | |
1202 | int i; | |
4ba526ce MC |
1203 | unsigned int delay_cnt; |
1204 | long time_remain; | |
1205 | ||
1206 | /* If enough time has passed, no wait is necessary. */ | |
1207 | time_remain = (long)(tp->last_event_jiffies + 1 + | |
1208 | usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - | |
1209 | (long)jiffies; | |
1210 | if (time_remain < 0) | |
1211 | return; | |
1212 | ||
1213 | /* Check if we can shorten the wait time. */ | |
1214 | delay_cnt = jiffies_to_usecs(time_remain); | |
1215 | if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC) | |
1216 | delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC; | |
1217 | delay_cnt = (delay_cnt >> 3) + 1; | |
95e2869a | 1218 | |
4ba526ce | 1219 | for (i = 0; i < delay_cnt; i++) { |
95e2869a MC |
1220 | if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT)) |
1221 | break; | |
4ba526ce | 1222 | udelay(8); |
95e2869a MC |
1223 | } |
1224 | } | |
1225 | ||
1226 | /* tp->lock is held. */ | |
1227 | static void tg3_ump_link_report(struct tg3 *tp) | |
1228 | { | |
1229 | u32 reg; | |
1230 | u32 val; | |
1231 | ||
1232 | if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || | |
1233 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
1234 | return; | |
1235 | ||
1236 | tg3_wait_for_event_ack(tp); | |
1237 | ||
1238 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); | |
1239 | ||
1240 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); | |
1241 | ||
1242 | val = 0; | |
1243 | if (!tg3_readphy(tp, MII_BMCR, ®)) | |
1244 | val = reg << 16; | |
1245 | if (!tg3_readphy(tp, MII_BMSR, ®)) | |
1246 | val |= (reg & 0xffff); | |
1247 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val); | |
1248 | ||
1249 | val = 0; | |
1250 | if (!tg3_readphy(tp, MII_ADVERTISE, ®)) | |
1251 | val = reg << 16; | |
1252 | if (!tg3_readphy(tp, MII_LPA, ®)) | |
1253 | val |= (reg & 0xffff); | |
1254 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val); | |
1255 | ||
1256 | val = 0; | |
1257 | if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) { | |
1258 | if (!tg3_readphy(tp, MII_CTRL1000, ®)) | |
1259 | val = reg << 16; | |
1260 | if (!tg3_readphy(tp, MII_STAT1000, ®)) | |
1261 | val |= (reg & 0xffff); | |
1262 | } | |
1263 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val); | |
1264 | ||
1265 | if (!tg3_readphy(tp, MII_PHYADDR, ®)) | |
1266 | val = reg << 16; | |
1267 | else | |
1268 | val = 0; | |
1269 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val); | |
1270 | ||
4ba526ce | 1271 | tg3_generate_fw_event(tp); |
95e2869a MC |
1272 | } |
1273 | ||
1274 | static void tg3_link_report(struct tg3 *tp) | |
1275 | { | |
1276 | if (!netif_carrier_ok(tp->dev)) { | |
05dbe005 | 1277 | netif_info(tp, link, tp->dev, "Link is down\n"); |
95e2869a MC |
1278 | tg3_ump_link_report(tp); |
1279 | } else if (netif_msg_link(tp)) { | |
05dbe005 JP |
1280 | netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", |
1281 | (tp->link_config.active_speed == SPEED_1000 ? | |
1282 | 1000 : | |
1283 | (tp->link_config.active_speed == SPEED_100 ? | |
1284 | 100 : 10)), | |
1285 | (tp->link_config.active_duplex == DUPLEX_FULL ? | |
1286 | "full" : "half")); | |
1287 | ||
1288 | netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", | |
1289 | (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? | |
1290 | "on" : "off", | |
1291 | (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? | |
1292 | "on" : "off"); | |
95e2869a MC |
1293 | tg3_ump_link_report(tp); |
1294 | } | |
1295 | } | |
1296 | ||
1297 | static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl) | |
1298 | { | |
1299 | u16 miireg; | |
1300 | ||
e18ce346 | 1301 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1302 | miireg = ADVERTISE_PAUSE_CAP; |
e18ce346 | 1303 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1304 | miireg = ADVERTISE_PAUSE_ASYM; |
e18ce346 | 1305 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1306 | miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1307 | else | |
1308 | miireg = 0; | |
1309 | ||
1310 | return miireg; | |
1311 | } | |
1312 | ||
1313 | static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl) | |
1314 | { | |
1315 | u16 miireg; | |
1316 | ||
e18ce346 | 1317 | if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX)) |
95e2869a | 1318 | miireg = ADVERTISE_1000XPAUSE; |
e18ce346 | 1319 | else if (flow_ctrl & FLOW_CTRL_TX) |
95e2869a | 1320 | miireg = ADVERTISE_1000XPSE_ASYM; |
e18ce346 | 1321 | else if (flow_ctrl & FLOW_CTRL_RX) |
95e2869a MC |
1322 | miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1323 | else | |
1324 | miireg = 0; | |
1325 | ||
1326 | return miireg; | |
1327 | } | |
1328 | ||
95e2869a MC |
1329 | static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) |
1330 | { | |
1331 | u8 cap = 0; | |
1332 | ||
1333 | if (lcladv & ADVERTISE_1000XPAUSE) { | |
1334 | if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1335 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1336 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a | 1337 | else if (rmtadv & LPA_1000XPAUSE_ASYM) |
e18ce346 | 1338 | cap = FLOW_CTRL_RX; |
95e2869a MC |
1339 | } else { |
1340 | if (rmtadv & LPA_1000XPAUSE) | |
e18ce346 | 1341 | cap = FLOW_CTRL_TX | FLOW_CTRL_RX; |
95e2869a MC |
1342 | } |
1343 | } else if (lcladv & ADVERTISE_1000XPSE_ASYM) { | |
1344 | if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM)) | |
e18ce346 | 1345 | cap = FLOW_CTRL_TX; |
95e2869a MC |
1346 | } |
1347 | ||
1348 | return cap; | |
1349 | } | |
1350 | ||
f51f3562 | 1351 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
95e2869a | 1352 | { |
b02fd9e3 | 1353 | u8 autoneg; |
f51f3562 | 1354 | u8 flowctrl = 0; |
95e2869a MC |
1355 | u32 old_rx_mode = tp->rx_mode; |
1356 | u32 old_tx_mode = tp->tx_mode; | |
1357 | ||
b02fd9e3 | 1358 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
3f0e3ad7 | 1359 | autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg; |
b02fd9e3 MC |
1360 | else |
1361 | autoneg = tp->link_config.autoneg; | |
1362 | ||
1363 | if (autoneg == AUTONEG_ENABLE && | |
95e2869a MC |
1364 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { |
1365 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | |
f51f3562 | 1366 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
95e2869a | 1367 | else |
bc02ff95 | 1368 | flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv); |
f51f3562 MC |
1369 | } else |
1370 | flowctrl = tp->link_config.flowctrl; | |
95e2869a | 1371 | |
f51f3562 | 1372 | tp->link_config.active_flowctrl = flowctrl; |
95e2869a | 1373 | |
e18ce346 | 1374 | if (flowctrl & FLOW_CTRL_RX) |
95e2869a MC |
1375 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1376 | else | |
1377 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | |
1378 | ||
f51f3562 | 1379 | if (old_rx_mode != tp->rx_mode) |
95e2869a | 1380 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
95e2869a | 1381 | |
e18ce346 | 1382 | if (flowctrl & FLOW_CTRL_TX) |
95e2869a MC |
1383 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1384 | else | |
1385 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | |
1386 | ||
f51f3562 | 1387 | if (old_tx_mode != tp->tx_mode) |
95e2869a | 1388 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
95e2869a MC |
1389 | } |
1390 | ||
b02fd9e3 MC |
1391 | static void tg3_adjust_link(struct net_device *dev) |
1392 | { | |
1393 | u8 oldflowctrl, linkmesg = 0; | |
1394 | u32 mac_mode, lcl_adv, rmt_adv; | |
1395 | struct tg3 *tp = netdev_priv(dev); | |
3f0e3ad7 | 1396 | struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 | 1397 | |
24bb4fb6 | 1398 | spin_lock_bh(&tp->lock); |
b02fd9e3 MC |
1399 | |
1400 | mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | | |
1401 | MAC_MODE_HALF_DUPLEX); | |
1402 | ||
1403 | oldflowctrl = tp->link_config.active_flowctrl; | |
1404 | ||
1405 | if (phydev->link) { | |
1406 | lcl_adv = 0; | |
1407 | rmt_adv = 0; | |
1408 | ||
1409 | if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) | |
1410 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
c3df0748 MC |
1411 | else if (phydev->speed == SPEED_1000 || |
1412 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) | |
b02fd9e3 | 1413 | mac_mode |= MAC_MODE_PORT_MODE_GMII; |
c3df0748 MC |
1414 | else |
1415 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
b02fd9e3 MC |
1416 | |
1417 | if (phydev->duplex == DUPLEX_HALF) | |
1418 | mac_mode |= MAC_MODE_HALF_DUPLEX; | |
1419 | else { | |
1420 | lcl_adv = tg3_advert_flowctrl_1000T( | |
1421 | tp->link_config.flowctrl); | |
1422 | ||
1423 | if (phydev->pause) | |
1424 | rmt_adv = LPA_PAUSE_CAP; | |
1425 | if (phydev->asym_pause) | |
1426 | rmt_adv |= LPA_PAUSE_ASYM; | |
1427 | } | |
1428 | ||
1429 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1430 | } else | |
1431 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
1432 | ||
1433 | if (mac_mode != tp->mac_mode) { | |
1434 | tp->mac_mode = mac_mode; | |
1435 | tw32_f(MAC_MODE, tp->mac_mode); | |
1436 | udelay(40); | |
1437 | } | |
1438 | ||
fcb389df MC |
1439 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
1440 | if (phydev->speed == SPEED_10) | |
1441 | tw32(MAC_MI_STAT, | |
1442 | MAC_MI_STAT_10MBPS_MODE | | |
1443 | MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1444 | else | |
1445 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
1446 | } | |
1447 | ||
b02fd9e3 MC |
1448 | if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) |
1449 | tw32(MAC_TX_LENGTHS, | |
1450 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1451 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1452 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1453 | else | |
1454 | tw32(MAC_TX_LENGTHS, | |
1455 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
1456 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
1457 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
1458 | ||
1459 | if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) || | |
1460 | (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) || | |
1461 | phydev->speed != tp->link_config.active_speed || | |
1462 | phydev->duplex != tp->link_config.active_duplex || | |
1463 | oldflowctrl != tp->link_config.active_flowctrl) | |
c6cdf436 | 1464 | linkmesg = 1; |
b02fd9e3 MC |
1465 | |
1466 | tp->link_config.active_speed = phydev->speed; | |
1467 | tp->link_config.active_duplex = phydev->duplex; | |
1468 | ||
24bb4fb6 | 1469 | spin_unlock_bh(&tp->lock); |
b02fd9e3 MC |
1470 | |
1471 | if (linkmesg) | |
1472 | tg3_link_report(tp); | |
1473 | } | |
1474 | ||
1475 | static int tg3_phy_init(struct tg3 *tp) | |
1476 | { | |
1477 | struct phy_device *phydev; | |
1478 | ||
1479 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) | |
1480 | return 0; | |
1481 | ||
1482 | /* Bring the PHY back to a known state. */ | |
1483 | tg3_bmcr_reset(tp); | |
1484 | ||
3f0e3ad7 | 1485 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1486 | |
1487 | /* Attach the MAC to the PHY. */ | |
fb28ad35 | 1488 | phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link, |
a9daf367 | 1489 | phydev->dev_flags, phydev->interface); |
b02fd9e3 | 1490 | if (IS_ERR(phydev)) { |
ab96b241 | 1491 | dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); |
b02fd9e3 MC |
1492 | return PTR_ERR(phydev); |
1493 | } | |
1494 | ||
b02fd9e3 | 1495 | /* Mask with MAC supported features. */ |
9c61d6bc MC |
1496 | switch (phydev->interface) { |
1497 | case PHY_INTERFACE_MODE_GMII: | |
1498 | case PHY_INTERFACE_MODE_RGMII: | |
321d32a0 MC |
1499 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { |
1500 | phydev->supported &= (PHY_GBIT_FEATURES | | |
1501 | SUPPORTED_Pause | | |
1502 | SUPPORTED_Asym_Pause); | |
1503 | break; | |
1504 | } | |
1505 | /* fallthru */ | |
9c61d6bc MC |
1506 | case PHY_INTERFACE_MODE_MII: |
1507 | phydev->supported &= (PHY_BASIC_FEATURES | | |
1508 | SUPPORTED_Pause | | |
1509 | SUPPORTED_Asym_Pause); | |
1510 | break; | |
1511 | default: | |
3f0e3ad7 | 1512 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
9c61d6bc MC |
1513 | return -EINVAL; |
1514 | } | |
1515 | ||
1516 | tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED; | |
b02fd9e3 MC |
1517 | |
1518 | phydev->advertising = phydev->supported; | |
1519 | ||
b02fd9e3 MC |
1520 | return 0; |
1521 | } | |
1522 | ||
1523 | static void tg3_phy_start(struct tg3 *tp) | |
1524 | { | |
1525 | struct phy_device *phydev; | |
1526 | ||
1527 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1528 | return; | |
1529 | ||
3f0e3ad7 | 1530 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
1531 | |
1532 | if (tp->link_config.phy_is_low_power) { | |
1533 | tp->link_config.phy_is_low_power = 0; | |
1534 | phydev->speed = tp->link_config.orig_speed; | |
1535 | phydev->duplex = tp->link_config.orig_duplex; | |
1536 | phydev->autoneg = tp->link_config.orig_autoneg; | |
1537 | phydev->advertising = tp->link_config.orig_advertising; | |
1538 | } | |
1539 | ||
1540 | phy_start(phydev); | |
1541 | ||
1542 | phy_start_aneg(phydev); | |
1543 | } | |
1544 | ||
1545 | static void tg3_phy_stop(struct tg3 *tp) | |
1546 | { | |
1547 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
1548 | return; | |
1549 | ||
3f0e3ad7 | 1550 | phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1551 | } |
1552 | ||
1553 | static void tg3_phy_fini(struct tg3 *tp) | |
1554 | { | |
1555 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
3f0e3ad7 | 1556 | phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
1557 | tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED; |
1558 | } | |
1559 | } | |
1560 | ||
b2a5c19c MC |
1561 | static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) |
1562 | { | |
1563 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); | |
1564 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); | |
1565 | } | |
1566 | ||
7f97a4bd MC |
1567 | static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) |
1568 | { | |
1569 | u32 phytest; | |
1570 | ||
1571 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
1572 | u32 phy; | |
1573 | ||
1574 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1575 | phytest | MII_TG3_FET_SHADOW_EN); | |
1576 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { | |
1577 | if (enable) | |
1578 | phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1579 | else | |
1580 | phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD; | |
1581 | tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); | |
1582 | } | |
1583 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
1584 | } | |
1585 | } | |
1586 | ||
6833c043 MC |
1587 | static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) |
1588 | { | |
1589 | u32 reg; | |
1590 | ||
ecf1410b MC |
1591 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
1592 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && | |
1593 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
6833c043 MC |
1594 | return; |
1595 | ||
7f97a4bd MC |
1596 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
1597 | tg3_phy_fet_toggle_apd(tp, enable); | |
1598 | return; | |
1599 | } | |
1600 | ||
6833c043 MC |
1601 | reg = MII_TG3_MISC_SHDW_WREN | |
1602 | MII_TG3_MISC_SHDW_SCR5_SEL | | |
1603 | MII_TG3_MISC_SHDW_SCR5_LPED | | |
1604 | MII_TG3_MISC_SHDW_SCR5_DLPTLM | | |
1605 | MII_TG3_MISC_SHDW_SCR5_SDTL | | |
1606 | MII_TG3_MISC_SHDW_SCR5_C125OE; | |
1607 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable) | |
1608 | reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD; | |
1609 | ||
1610 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1611 | ||
1612 | ||
1613 | reg = MII_TG3_MISC_SHDW_WREN | | |
1614 | MII_TG3_MISC_SHDW_APD_SEL | | |
1615 | MII_TG3_MISC_SHDW_APD_WKTM_84MS; | |
1616 | if (enable) | |
1617 | reg |= MII_TG3_MISC_SHDW_APD_ENABLE; | |
1618 | ||
1619 | tg3_writephy(tp, MII_TG3_MISC_SHDW, reg); | |
1620 | } | |
1621 | ||
9ef8ca99 MC |
1622 | static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable) |
1623 | { | |
1624 | u32 phy; | |
1625 | ||
1626 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | |
1627 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
1628 | return; | |
1629 | ||
7f97a4bd | 1630 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
9ef8ca99 MC |
1631 | u32 ephy; |
1632 | ||
535ef6e1 MC |
1633 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { |
1634 | u32 reg = MII_TG3_FET_SHDW_MISCCTRL; | |
1635 | ||
1636 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
1637 | ephy | MII_TG3_FET_SHADOW_EN); | |
1638 | if (!tg3_readphy(tp, reg, &phy)) { | |
9ef8ca99 | 1639 | if (enable) |
535ef6e1 | 1640 | phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
9ef8ca99 | 1641 | else |
535ef6e1 MC |
1642 | phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX; |
1643 | tg3_writephy(tp, reg, phy); | |
9ef8ca99 | 1644 | } |
535ef6e1 | 1645 | tg3_writephy(tp, MII_TG3_FET_TEST, ephy); |
9ef8ca99 MC |
1646 | } |
1647 | } else { | |
1648 | phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC | | |
1649 | MII_TG3_AUXCTL_SHDWSEL_MISC; | |
1650 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) && | |
1651 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) { | |
1652 | if (enable) | |
1653 | phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1654 | else | |
1655 | phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX; | |
1656 | phy |= MII_TG3_AUXCTL_MISC_WREN; | |
1657 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1658 | } | |
1659 | } | |
1660 | } | |
1661 | ||
1da177e4 LT |
1662 | static void tg3_phy_set_wirespeed(struct tg3 *tp) |
1663 | { | |
1664 | u32 val; | |
1665 | ||
1666 | if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) | |
1667 | return; | |
1668 | ||
1669 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) && | |
1670 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val)) | |
1671 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
1672 | (val | (1 << 15) | (1 << 4))); | |
1673 | } | |
1674 | ||
b2a5c19c MC |
1675 | static void tg3_phy_apply_otp(struct tg3 *tp) |
1676 | { | |
1677 | u32 otp, phy; | |
1678 | ||
1679 | if (!tp->phy_otp) | |
1680 | return; | |
1681 | ||
1682 | otp = tp->phy_otp; | |
1683 | ||
1684 | /* Enable SM_DSP clock and tx 6dB coding. */ | |
1685 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1686 | MII_TG3_AUXCTL_ACTL_SMDSP_ENA | | |
1687 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1688 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1689 | ||
1690 | phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT); | |
1691 | phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT; | |
1692 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); | |
1693 | ||
1694 | phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) | | |
1695 | ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT); | |
1696 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); | |
1697 | ||
1698 | phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT); | |
1699 | phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ; | |
1700 | tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); | |
1701 | ||
1702 | phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT); | |
1703 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); | |
1704 | ||
1705 | phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT); | |
1706 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); | |
1707 | ||
1708 | phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) | | |
1709 | ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT); | |
1710 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); | |
1711 | ||
1712 | /* Turn off SM_DSP clock. */ | |
1713 | phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | | |
1714 | MII_TG3_AUXCTL_ACTL_TX_6DB; | |
1715 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy); | |
1716 | } | |
1717 | ||
1da177e4 LT |
1718 | static int tg3_wait_macro_done(struct tg3 *tp) |
1719 | { | |
1720 | int limit = 100; | |
1721 | ||
1722 | while (limit--) { | |
1723 | u32 tmp32; | |
1724 | ||
1725 | if (!tg3_readphy(tp, 0x16, &tmp32)) { | |
1726 | if ((tmp32 & 0x1000) == 0) | |
1727 | break; | |
1728 | } | |
1729 | } | |
d4675b52 | 1730 | if (limit < 0) |
1da177e4 LT |
1731 | return -EBUSY; |
1732 | ||
1733 | return 0; | |
1734 | } | |
1735 | ||
1736 | static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) | |
1737 | { | |
1738 | static const u32 test_pat[4][6] = { | |
1739 | { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 }, | |
1740 | { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 }, | |
1741 | { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 }, | |
1742 | { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 } | |
1743 | }; | |
1744 | int chan; | |
1745 | ||
1746 | for (chan = 0; chan < 4; chan++) { | |
1747 | int i; | |
1748 | ||
1749 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1750 | (chan * 0x2000) | 0x0200); | |
1751 | tg3_writephy(tp, 0x16, 0x0002); | |
1752 | ||
1753 | for (i = 0; i < 6; i++) | |
1754 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, | |
1755 | test_pat[chan][i]); | |
1756 | ||
1757 | tg3_writephy(tp, 0x16, 0x0202); | |
1758 | if (tg3_wait_macro_done(tp)) { | |
1759 | *resetp = 1; | |
1760 | return -EBUSY; | |
1761 | } | |
1762 | ||
1763 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1764 | (chan * 0x2000) | 0x0200); | |
1765 | tg3_writephy(tp, 0x16, 0x0082); | |
1766 | if (tg3_wait_macro_done(tp)) { | |
1767 | *resetp = 1; | |
1768 | return -EBUSY; | |
1769 | } | |
1770 | ||
1771 | tg3_writephy(tp, 0x16, 0x0802); | |
1772 | if (tg3_wait_macro_done(tp)) { | |
1773 | *resetp = 1; | |
1774 | return -EBUSY; | |
1775 | } | |
1776 | ||
1777 | for (i = 0; i < 6; i += 2) { | |
1778 | u32 low, high; | |
1779 | ||
1780 | if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || | |
1781 | tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || | |
1782 | tg3_wait_macro_done(tp)) { | |
1783 | *resetp = 1; | |
1784 | return -EBUSY; | |
1785 | } | |
1786 | low &= 0x7fff; | |
1787 | high &= 0x000f; | |
1788 | if (low != test_pat[chan][i] || | |
1789 | high != test_pat[chan][i+1]) { | |
1790 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); | |
1791 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); | |
1792 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); | |
1793 | ||
1794 | return -EBUSY; | |
1795 | } | |
1796 | } | |
1797 | } | |
1798 | ||
1799 | return 0; | |
1800 | } | |
1801 | ||
1802 | static int tg3_phy_reset_chanpat(struct tg3 *tp) | |
1803 | { | |
1804 | int chan; | |
1805 | ||
1806 | for (chan = 0; chan < 4; chan++) { | |
1807 | int i; | |
1808 | ||
1809 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, | |
1810 | (chan * 0x2000) | 0x0200); | |
1811 | tg3_writephy(tp, 0x16, 0x0002); | |
1812 | for (i = 0; i < 6; i++) | |
1813 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); | |
1814 | tg3_writephy(tp, 0x16, 0x0202); | |
1815 | if (tg3_wait_macro_done(tp)) | |
1816 | return -EBUSY; | |
1817 | } | |
1818 | ||
1819 | return 0; | |
1820 | } | |
1821 | ||
1822 | static int tg3_phy_reset_5703_4_5(struct tg3 *tp) | |
1823 | { | |
1824 | u32 reg32, phy9_orig; | |
1825 | int retries, do_phy_reset, err; | |
1826 | ||
1827 | retries = 10; | |
1828 | do_phy_reset = 1; | |
1829 | do { | |
1830 | if (do_phy_reset) { | |
1831 | err = tg3_bmcr_reset(tp); | |
1832 | if (err) | |
1833 | return err; | |
1834 | do_phy_reset = 0; | |
1835 | } | |
1836 | ||
1837 | /* Disable transmitter and interrupt. */ | |
1838 | if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) | |
1839 | continue; | |
1840 | ||
1841 | reg32 |= 0x3000; | |
1842 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1843 | ||
1844 | /* Set full-duplex, 1000 mbps. */ | |
1845 | tg3_writephy(tp, MII_BMCR, | |
1846 | BMCR_FULLDPLX | TG3_BMCR_SPEED1000); | |
1847 | ||
1848 | /* Set to master mode. */ | |
1849 | if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig)) | |
1850 | continue; | |
1851 | ||
1852 | tg3_writephy(tp, MII_TG3_CTRL, | |
1853 | (MII_TG3_CTRL_AS_MASTER | | |
1854 | MII_TG3_CTRL_ENABLE_AS_MASTER)); | |
1855 | ||
1856 | /* Enable SM_DSP_CLOCK and 6dB. */ | |
1857 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1858 | ||
1859 | /* Block the PHY control access. */ | |
1860 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1861 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800); | |
1862 | ||
1863 | err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); | |
1864 | if (!err) | |
1865 | break; | |
1866 | } while (--retries); | |
1867 | ||
1868 | err = tg3_phy_reset_chanpat(tp); | |
1869 | if (err) | |
1870 | return err; | |
1871 | ||
1872 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005); | |
1873 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000); | |
1874 | ||
1875 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); | |
1876 | tg3_writephy(tp, 0x16, 0x0000); | |
1877 | ||
1878 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
1879 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
1880 | /* Set Extended packet length bit for jumbo frames */ | |
1881 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400); | |
859a5887 | 1882 | } else { |
1da177e4 LT |
1883 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
1884 | } | |
1885 | ||
1886 | tg3_writephy(tp, MII_TG3_CTRL, phy9_orig); | |
1887 | ||
1888 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { | |
1889 | reg32 &= ~0x3000; | |
1890 | tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); | |
1891 | } else if (!err) | |
1892 | err = -EBUSY; | |
1893 | ||
1894 | return err; | |
1895 | } | |
1896 | ||
1897 | /* This will reset the tigon3 PHY if there is no valid | |
1898 | * link unless the FORCE argument is non-zero. | |
1899 | */ | |
1900 | static int tg3_phy_reset(struct tg3 *tp) | |
1901 | { | |
b2a5c19c | 1902 | u32 cpmuctrl; |
1da177e4 LT |
1903 | u32 phy_status; |
1904 | int err; | |
1905 | ||
60189ddf MC |
1906 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
1907 | u32 val; | |
1908 | ||
1909 | val = tr32(GRC_MISC_CFG); | |
1910 | tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ); | |
1911 | udelay(40); | |
1912 | } | |
1da177e4 LT |
1913 | err = tg3_readphy(tp, MII_BMSR, &phy_status); |
1914 | err |= tg3_readphy(tp, MII_BMSR, &phy_status); | |
1915 | if (err != 0) | |
1916 | return -EBUSY; | |
1917 | ||
c8e1e82b MC |
1918 | if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) { |
1919 | netif_carrier_off(tp->dev); | |
1920 | tg3_link_report(tp); | |
1921 | } | |
1922 | ||
1da177e4 LT |
1923 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || |
1924 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
1925 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
1926 | err = tg3_phy_reset_5703_4_5(tp); | |
1927 | if (err) | |
1928 | return err; | |
1929 | goto out; | |
1930 | } | |
1931 | ||
b2a5c19c MC |
1932 | cpmuctrl = 0; |
1933 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && | |
1934 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
1935 | cpmuctrl = tr32(TG3_CPMU_CTRL); | |
1936 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) | |
1937 | tw32(TG3_CPMU_CTRL, | |
1938 | cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY); | |
1939 | } | |
1940 | ||
1da177e4 LT |
1941 | err = tg3_bmcr_reset(tp); |
1942 | if (err) | |
1943 | return err; | |
1944 | ||
b2a5c19c MC |
1945 | if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) { |
1946 | u32 phy; | |
1947 | ||
1948 | phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz; | |
1949 | tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy); | |
1950 | ||
1951 | tw32(TG3_CPMU_CTRL, cpmuctrl); | |
1952 | } | |
1953 | ||
bcb37f6c MC |
1954 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
1955 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
1956 | u32 val; |
1957 | ||
1958 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); | |
1959 | if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) == | |
1960 | CPMU_LSPD_1000MB_MACCLK_12_5) { | |
1961 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
1962 | udelay(40); | |
1963 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
1964 | } | |
1965 | } | |
1966 | ||
ecf1410b MC |
1967 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && |
1968 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) | |
1969 | return 0; | |
1970 | ||
b2a5c19c MC |
1971 | tg3_phy_apply_otp(tp); |
1972 | ||
6833c043 MC |
1973 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) |
1974 | tg3_phy_toggle_apd(tp, true); | |
1975 | else | |
1976 | tg3_phy_toggle_apd(tp, false); | |
1977 | ||
1da177e4 LT |
1978 | out: |
1979 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) { | |
1980 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1981 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1982 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa); | |
1983 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1984 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323); | |
1985 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
1986 | } | |
1987 | if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) { | |
1988 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1989 | tg3_writephy(tp, 0x1c, 0x8d68); | |
1990 | } | |
1991 | if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) { | |
1992 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); | |
1993 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
1994 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b); | |
1995 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
1996 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506); | |
1997 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f); | |
1998 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); | |
1999 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); | |
859a5887 | 2000 | } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) { |
c424cb24 MC |
2001 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); |
2002 | tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); | |
c1d2a196 MC |
2003 | if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) { |
2004 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); | |
2005 | tg3_writephy(tp, MII_TG3_TEST1, | |
2006 | MII_TG3_TEST1_TRIM_EN | 0x4); | |
2007 | } else | |
2008 | tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); | |
c424cb24 MC |
2009 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); |
2010 | } | |
1da177e4 LT |
2011 | /* Set Extended packet length bit (bit 14) on all chips that */ |
2012 | /* support jumbo frames */ | |
79eb6904 | 2013 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
2014 | /* Cannot do read-modify-write on 5401 */ |
2015 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
8f666b07 | 2016 | } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
2017 | u32 phy_reg; |
2018 | ||
2019 | /* Set bit 14 with read-modify-write to preserve other bits */ | |
2020 | if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) && | |
2021 | !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg)) | |
2022 | tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000); | |
2023 | } | |
2024 | ||
2025 | /* Set phy register 0x10 bit 0 to high fifo elasticity to support | |
2026 | * jumbo frames transmission. | |
2027 | */ | |
8f666b07 | 2028 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
1da177e4 LT |
2029 | u32 phy_reg; |
2030 | ||
2031 | if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) | |
c6cdf436 MC |
2032 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2033 | phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC); | |
1da177e4 LT |
2034 | } |
2035 | ||
715116a1 | 2036 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
715116a1 | 2037 | /* adjust output voltage */ |
535ef6e1 | 2038 | tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); |
715116a1 MC |
2039 | } |
2040 | ||
9ef8ca99 | 2041 | tg3_phy_toggle_automdix(tp, 1); |
1da177e4 LT |
2042 | tg3_phy_set_wirespeed(tp); |
2043 | return 0; | |
2044 | } | |
2045 | ||
2046 | static void tg3_frob_aux_power(struct tg3 *tp) | |
2047 | { | |
2048 | struct tg3 *tp_peer = tp; | |
2049 | ||
334355aa MC |
2050 | /* The GPIOs do something completely different on 57765. */ |
2051 | if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 || | |
2052 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
1da177e4 LT |
2053 | return; |
2054 | ||
f6eb9b1f MC |
2055 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
2056 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
2057 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { | |
8c2dc7e1 MC |
2058 | struct net_device *dev_peer; |
2059 | ||
2060 | dev_peer = pci_get_drvdata(tp->pdev_peer); | |
bc1c7567 | 2061 | /* remove_one() may have been run on the peer. */ |
8c2dc7e1 | 2062 | if (!dev_peer) |
bc1c7567 MC |
2063 | tp_peer = tp; |
2064 | else | |
2065 | tp_peer = netdev_priv(dev_peer); | |
1da177e4 LT |
2066 | } |
2067 | ||
1da177e4 | 2068 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || |
6921d201 MC |
2069 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 || |
2070 | (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 || | |
2071 | (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { | |
1da177e4 LT |
2072 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
2073 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
b401e9e2 MC |
2074 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2075 | (GRC_LCLCTRL_GPIO_OE0 | | |
2076 | GRC_LCLCTRL_GPIO_OE1 | | |
2077 | GRC_LCLCTRL_GPIO_OE2 | | |
2078 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2079 | GRC_LCLCTRL_GPIO_OUTPUT1), | |
2080 | 100); | |
8d519ab2 MC |
2081 | } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
2082 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
2083 | /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ |
2084 | u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 | | |
2085 | GRC_LCLCTRL_GPIO_OE1 | | |
2086 | GRC_LCLCTRL_GPIO_OE2 | | |
2087 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
2088 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2089 | tp->grc_local_ctrl; | |
2090 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2091 | ||
2092 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2; | |
2093 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
2094 | ||
2095 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0; | |
2096 | tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100); | |
1da177e4 LT |
2097 | } else { |
2098 | u32 no_gpio2; | |
dc56b7d4 | 2099 | u32 grc_local_ctrl = 0; |
1da177e4 LT |
2100 | |
2101 | if (tp_peer != tp && | |
2102 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2103 | return; | |
2104 | ||
dc56b7d4 MC |
2105 | /* Workaround to prevent overdrawing Amps. */ |
2106 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2107 | ASIC_REV_5714) { | |
2108 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
b401e9e2 MC |
2109 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2110 | grc_local_ctrl, 100); | |
dc56b7d4 MC |
2111 | } |
2112 | ||
1da177e4 LT |
2113 | /* On 5753 and variants, GPIO2 cannot be used. */ |
2114 | no_gpio2 = tp->nic_sram_data_cfg & | |
2115 | NIC_SRAM_DATA_CFG_NO_GPIO2; | |
2116 | ||
dc56b7d4 | 2117 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | |
1da177e4 LT |
2118 | GRC_LCLCTRL_GPIO_OE1 | |
2119 | GRC_LCLCTRL_GPIO_OE2 | | |
2120 | GRC_LCLCTRL_GPIO_OUTPUT1 | | |
2121 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
2122 | if (no_gpio2) { | |
2123 | grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 | | |
2124 | GRC_LCLCTRL_GPIO_OUTPUT2); | |
2125 | } | |
b401e9e2 MC |
2126 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2127 | grc_local_ctrl, 100); | |
1da177e4 LT |
2128 | |
2129 | grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0; | |
2130 | ||
b401e9e2 MC |
2131 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2132 | grc_local_ctrl, 100); | |
1da177e4 LT |
2133 | |
2134 | if (!no_gpio2) { | |
2135 | grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2; | |
b401e9e2 MC |
2136 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2137 | grc_local_ctrl, 100); | |
1da177e4 LT |
2138 | } |
2139 | } | |
2140 | } else { | |
2141 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
2142 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
2143 | if (tp_peer != tp && | |
2144 | (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0) | |
2145 | return; | |
2146 | ||
b401e9e2 MC |
2147 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2148 | (GRC_LCLCTRL_GPIO_OE1 | | |
2149 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 | 2150 | |
b401e9e2 MC |
2151 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2152 | GRC_LCLCTRL_GPIO_OE1, 100); | |
1da177e4 | 2153 | |
b401e9e2 MC |
2154 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | |
2155 | (GRC_LCLCTRL_GPIO_OE1 | | |
2156 | GRC_LCLCTRL_GPIO_OUTPUT1), 100); | |
1da177e4 LT |
2157 | } |
2158 | } | |
2159 | } | |
2160 | ||
e8f3f6ca MC |
2161 | static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) |
2162 | { | |
2163 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) | |
2164 | return 1; | |
79eb6904 | 2165 | else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { |
e8f3f6ca MC |
2166 | if (speed != SPEED_10) |
2167 | return 1; | |
2168 | } else if (speed == SPEED_10) | |
2169 | return 1; | |
2170 | ||
2171 | return 0; | |
2172 | } | |
2173 | ||
1da177e4 LT |
2174 | static int tg3_setup_phy(struct tg3 *, int); |
2175 | ||
2176 | #define RESET_KIND_SHUTDOWN 0 | |
2177 | #define RESET_KIND_INIT 1 | |
2178 | #define RESET_KIND_SUSPEND 2 | |
2179 | ||
2180 | static void tg3_write_sig_post_reset(struct tg3 *, int); | |
2181 | static int tg3_halt_cpu(struct tg3 *, u32); | |
2182 | ||
0a459aac | 2183 | static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) |
15c3b696 | 2184 | { |
ce057f01 MC |
2185 | u32 val; |
2186 | ||
5129724a MC |
2187 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { |
2188 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2189 | u32 sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
2190 | u32 serdes_cfg = tr32(MAC_SERDES_CFG); | |
2191 | ||
2192 | sg_dig_ctrl |= | |
2193 | SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET; | |
2194 | tw32(SG_DIG_CTRL, sg_dig_ctrl); | |
2195 | tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15)); | |
2196 | } | |
3f7045c1 | 2197 | return; |
5129724a | 2198 | } |
3f7045c1 | 2199 | |
60189ddf | 2200 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
60189ddf MC |
2201 | tg3_bmcr_reset(tp); |
2202 | val = tr32(GRC_MISC_CFG); | |
2203 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | |
2204 | udelay(40); | |
2205 | return; | |
0e5f784c MC |
2206 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
2207 | u32 phytest; | |
2208 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | |
2209 | u32 phy; | |
2210 | ||
2211 | tg3_writephy(tp, MII_ADVERTISE, 0); | |
2212 | tg3_writephy(tp, MII_BMCR, | |
2213 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2214 | ||
2215 | tg3_writephy(tp, MII_TG3_FET_TEST, | |
2216 | phytest | MII_TG3_FET_SHADOW_EN); | |
2217 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | |
2218 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | |
2219 | tg3_writephy(tp, | |
2220 | MII_TG3_FET_SHDW_AUXMODE4, | |
2221 | phy); | |
2222 | } | |
2223 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | |
2224 | } | |
2225 | return; | |
0a459aac | 2226 | } else if (do_low_power) { |
715116a1 MC |
2227 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2228 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | |
0a459aac MC |
2229 | |
2230 | tg3_writephy(tp, MII_TG3_AUX_CTRL, | |
2231 | MII_TG3_AUXCTL_SHDWSEL_PWRCTL | | |
2232 | MII_TG3_AUXCTL_PCTL_100TX_LPWR | | |
2233 | MII_TG3_AUXCTL_PCTL_SPR_ISOLATE | | |
2234 | MII_TG3_AUXCTL_PCTL_VREG_11V); | |
715116a1 | 2235 | } |
3f7045c1 | 2236 | |
15c3b696 MC |
2237 | /* The PHY should not be powered down on some chips because |
2238 | * of bugs. | |
2239 | */ | |
2240 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2241 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
2242 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 && | |
2243 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
2244 | return; | |
ce057f01 | 2245 | |
bcb37f6c MC |
2246 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX || |
2247 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) { | |
ce057f01 MC |
2248 | val = tr32(TG3_CPMU_LSPD_1000MB_CLK); |
2249 | val &= ~CPMU_LSPD_1000MB_MACCLK_MASK; | |
2250 | val |= CPMU_LSPD_1000MB_MACCLK_12_5; | |
2251 | tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val); | |
2252 | } | |
2253 | ||
15c3b696 MC |
2254 | tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); |
2255 | } | |
2256 | ||
ffbcfed4 MC |
2257 | /* tp->lock is held. */ |
2258 | static int tg3_nvram_lock(struct tg3 *tp) | |
2259 | { | |
2260 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2261 | int i; | |
2262 | ||
2263 | if (tp->nvram_lock_cnt == 0) { | |
2264 | tw32(NVRAM_SWARB, SWARB_REQ_SET1); | |
2265 | for (i = 0; i < 8000; i++) { | |
2266 | if (tr32(NVRAM_SWARB) & SWARB_GNT1) | |
2267 | break; | |
2268 | udelay(20); | |
2269 | } | |
2270 | if (i == 8000) { | |
2271 | tw32(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2272 | return -ENODEV; | |
2273 | } | |
2274 | } | |
2275 | tp->nvram_lock_cnt++; | |
2276 | } | |
2277 | return 0; | |
2278 | } | |
2279 | ||
2280 | /* tp->lock is held. */ | |
2281 | static void tg3_nvram_unlock(struct tg3 *tp) | |
2282 | { | |
2283 | if (tp->tg3_flags & TG3_FLAG_NVRAM) { | |
2284 | if (tp->nvram_lock_cnt > 0) | |
2285 | tp->nvram_lock_cnt--; | |
2286 | if (tp->nvram_lock_cnt == 0) | |
2287 | tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1); | |
2288 | } | |
2289 | } | |
2290 | ||
2291 | /* tp->lock is held. */ | |
2292 | static void tg3_enable_nvram_access(struct tg3 *tp) | |
2293 | { | |
2294 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2295 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2296 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2297 | ||
2298 | tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); | |
2299 | } | |
2300 | } | |
2301 | ||
2302 | /* tp->lock is held. */ | |
2303 | static void tg3_disable_nvram_access(struct tg3 *tp) | |
2304 | { | |
2305 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 2306 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) { |
ffbcfed4 MC |
2307 | u32 nvaccess = tr32(NVRAM_ACCESS); |
2308 | ||
2309 | tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); | |
2310 | } | |
2311 | } | |
2312 | ||
2313 | static int tg3_nvram_read_using_eeprom(struct tg3 *tp, | |
2314 | u32 offset, u32 *val) | |
2315 | { | |
2316 | u32 tmp; | |
2317 | int i; | |
2318 | ||
2319 | if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0) | |
2320 | return -EINVAL; | |
2321 | ||
2322 | tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK | | |
2323 | EEPROM_ADDR_DEVID_MASK | | |
2324 | EEPROM_ADDR_READ); | |
2325 | tw32(GRC_EEPROM_ADDR, | |
2326 | tmp | | |
2327 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
2328 | ((offset << EEPROM_ADDR_ADDR_SHIFT) & | |
2329 | EEPROM_ADDR_ADDR_MASK) | | |
2330 | EEPROM_ADDR_READ | EEPROM_ADDR_START); | |
2331 | ||
2332 | for (i = 0; i < 1000; i++) { | |
2333 | tmp = tr32(GRC_EEPROM_ADDR); | |
2334 | ||
2335 | if (tmp & EEPROM_ADDR_COMPLETE) | |
2336 | break; | |
2337 | msleep(1); | |
2338 | } | |
2339 | if (!(tmp & EEPROM_ADDR_COMPLETE)) | |
2340 | return -EBUSY; | |
2341 | ||
62cedd11 MC |
2342 | tmp = tr32(GRC_EEPROM_DATA); |
2343 | ||
2344 | /* | |
2345 | * The data will always be opposite the native endian | |
2346 | * format. Perform a blind byteswap to compensate. | |
2347 | */ | |
2348 | *val = swab32(tmp); | |
2349 | ||
ffbcfed4 MC |
2350 | return 0; |
2351 | } | |
2352 | ||
2353 | #define NVRAM_CMD_TIMEOUT 10000 | |
2354 | ||
2355 | static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |
2356 | { | |
2357 | int i; | |
2358 | ||
2359 | tw32(NVRAM_CMD, nvram_cmd); | |
2360 | for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) { | |
2361 | udelay(10); | |
2362 | if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) { | |
2363 | udelay(10); | |
2364 | break; | |
2365 | } | |
2366 | } | |
2367 | ||
2368 | if (i == NVRAM_CMD_TIMEOUT) | |
2369 | return -EBUSY; | |
2370 | ||
2371 | return 0; | |
2372 | } | |
2373 | ||
2374 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | |
2375 | { | |
2376 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2377 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2378 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2379 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2380 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2381 | ||
2382 | addr = ((addr / tp->nvram_pagesize) << | |
2383 | ATMEL_AT45DB0X1B_PAGE_POS) + | |
2384 | (addr % tp->nvram_pagesize); | |
2385 | ||
2386 | return addr; | |
2387 | } | |
2388 | ||
2389 | static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) | |
2390 | { | |
2391 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | |
2392 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | |
2393 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | |
2394 | !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) && | |
2395 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | |
2396 | ||
2397 | addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) * | |
2398 | tp->nvram_pagesize) + | |
2399 | (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); | |
2400 | ||
2401 | return addr; | |
2402 | } | |
2403 | ||
e4f34110 MC |
2404 | /* NOTE: Data read in from NVRAM is byteswapped according to |
2405 | * the byteswapping settings for all other register accesses. | |
2406 | * tg3 devices are BE devices, so on a BE machine, the data | |
2407 | * returned will be exactly as it is seen in NVRAM. On a LE | |
2408 | * machine, the 32-bit value will be byteswapped. | |
2409 | */ | |
ffbcfed4 MC |
2410 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
2411 | { | |
2412 | int ret; | |
2413 | ||
2414 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | |
2415 | return tg3_nvram_read_using_eeprom(tp, offset, val); | |
2416 | ||
2417 | offset = tg3_nvram_phys_addr(tp, offset); | |
2418 | ||
2419 | if (offset > NVRAM_ADDR_MSK) | |
2420 | return -EINVAL; | |
2421 | ||
2422 | ret = tg3_nvram_lock(tp); | |
2423 | if (ret) | |
2424 | return ret; | |
2425 | ||
2426 | tg3_enable_nvram_access(tp); | |
2427 | ||
2428 | tw32(NVRAM_ADDR, offset); | |
2429 | ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | | |
2430 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); | |
2431 | ||
2432 | if (ret == 0) | |
e4f34110 | 2433 | *val = tr32(NVRAM_RDDATA); |
ffbcfed4 MC |
2434 | |
2435 | tg3_disable_nvram_access(tp); | |
2436 | ||
2437 | tg3_nvram_unlock(tp); | |
2438 | ||
2439 | return ret; | |
2440 | } | |
2441 | ||
a9dc529d MC |
2442 | /* Ensures NVRAM data is in bytestream format. */ |
2443 | static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) | |
ffbcfed4 MC |
2444 | { |
2445 | u32 v; | |
a9dc529d | 2446 | int res = tg3_nvram_read(tp, offset, &v); |
ffbcfed4 | 2447 | if (!res) |
a9dc529d | 2448 | *val = cpu_to_be32(v); |
ffbcfed4 MC |
2449 | return res; |
2450 | } | |
2451 | ||
3f007891 MC |
2452 | /* tp->lock is held. */ |
2453 | static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1) | |
2454 | { | |
2455 | u32 addr_high, addr_low; | |
2456 | int i; | |
2457 | ||
2458 | addr_high = ((tp->dev->dev_addr[0] << 8) | | |
2459 | tp->dev->dev_addr[1]); | |
2460 | addr_low = ((tp->dev->dev_addr[2] << 24) | | |
2461 | (tp->dev->dev_addr[3] << 16) | | |
2462 | (tp->dev->dev_addr[4] << 8) | | |
2463 | (tp->dev->dev_addr[5] << 0)); | |
2464 | for (i = 0; i < 4; i++) { | |
2465 | if (i == 1 && skip_mac_1) | |
2466 | continue; | |
2467 | tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high); | |
2468 | tw32(MAC_ADDR_0_LOW + (i * 8), addr_low); | |
2469 | } | |
2470 | ||
2471 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
2472 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
2473 | for (i = 0; i < 12; i++) { | |
2474 | tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high); | |
2475 | tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low); | |
2476 | } | |
2477 | } | |
2478 | ||
2479 | addr_high = (tp->dev->dev_addr[0] + | |
2480 | tp->dev->dev_addr[1] + | |
2481 | tp->dev->dev_addr[2] + | |
2482 | tp->dev->dev_addr[3] + | |
2483 | tp->dev->dev_addr[4] + | |
2484 | tp->dev->dev_addr[5]) & | |
2485 | TX_BACKOFF_SEED_MASK; | |
2486 | tw32(MAC_TX_BACKOFF_SEED, addr_high); | |
2487 | } | |
2488 | ||
bc1c7567 | 2489 | static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) |
1da177e4 LT |
2490 | { |
2491 | u32 misc_host_ctrl; | |
0a459aac | 2492 | bool device_should_wake, do_low_power; |
1da177e4 LT |
2493 | |
2494 | /* Make sure register accesses (indirect or otherwise) | |
2495 | * will function correctly. | |
2496 | */ | |
2497 | pci_write_config_dword(tp->pdev, | |
2498 | TG3PCI_MISC_HOST_CTRL, | |
2499 | tp->misc_host_ctrl); | |
2500 | ||
1da177e4 | 2501 | switch (state) { |
bc1c7567 | 2502 | case PCI_D0: |
12dac075 RW |
2503 | pci_enable_wake(tp->pdev, state, false); |
2504 | pci_set_power_state(tp->pdev, PCI_D0); | |
8c6bda1a | 2505 | |
9d26e213 MC |
2506 | /* Switch out of Vaux if it is a NIC */ |
2507 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
b401e9e2 | 2508 | tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100); |
1da177e4 LT |
2509 | |
2510 | return 0; | |
2511 | ||
bc1c7567 | 2512 | case PCI_D1: |
bc1c7567 | 2513 | case PCI_D2: |
bc1c7567 | 2514 | case PCI_D3hot: |
1da177e4 LT |
2515 | break; |
2516 | ||
2517 | default: | |
05dbe005 JP |
2518 | netdev_err(tp->dev, "Invalid power state (D%d) requested\n", |
2519 | state); | |
1da177e4 | 2520 | return -EINVAL; |
855e1111 | 2521 | } |
5e7dfd0f MC |
2522 | |
2523 | /* Restore the CLKREQ setting. */ | |
2524 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
2525 | u16 lnkctl; | |
2526 | ||
2527 | pci_read_config_word(tp->pdev, | |
2528 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2529 | &lnkctl); | |
2530 | lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
2531 | pci_write_config_word(tp->pdev, | |
2532 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
2533 | lnkctl); | |
2534 | } | |
2535 | ||
1da177e4 LT |
2536 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
2537 | tw32(TG3PCI_MISC_HOST_CTRL, | |
2538 | misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT); | |
2539 | ||
05ac4cb7 MC |
2540 | device_should_wake = pci_pme_capable(tp->pdev, state) && |
2541 | device_may_wakeup(&tp->pdev->dev) && | |
2542 | (tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
2543 | ||
dd477003 | 2544 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
0a459aac | 2545 | do_low_power = false; |
b02fd9e3 MC |
2546 | if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) && |
2547 | !tp->link_config.phy_is_low_power) { | |
2548 | struct phy_device *phydev; | |
0a459aac | 2549 | u32 phyid, advertising; |
b02fd9e3 | 2550 | |
3f0e3ad7 | 2551 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
b02fd9e3 MC |
2552 | |
2553 | tp->link_config.phy_is_low_power = 1; | |
2554 | ||
2555 | tp->link_config.orig_speed = phydev->speed; | |
2556 | tp->link_config.orig_duplex = phydev->duplex; | |
2557 | tp->link_config.orig_autoneg = phydev->autoneg; | |
2558 | tp->link_config.orig_advertising = phydev->advertising; | |
2559 | ||
2560 | advertising = ADVERTISED_TP | | |
2561 | ADVERTISED_Pause | | |
2562 | ADVERTISED_Autoneg | | |
2563 | ADVERTISED_10baseT_Half; | |
2564 | ||
2565 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
05ac4cb7 | 2566 | device_should_wake) { |
b02fd9e3 MC |
2567 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) |
2568 | advertising |= | |
2569 | ADVERTISED_100baseT_Half | | |
2570 | ADVERTISED_100baseT_Full | | |
2571 | ADVERTISED_10baseT_Full; | |
2572 | else | |
2573 | advertising |= ADVERTISED_10baseT_Full; | |
2574 | } | |
2575 | ||
2576 | phydev->advertising = advertising; | |
2577 | ||
2578 | phy_start_aneg(phydev); | |
0a459aac MC |
2579 | |
2580 | phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; | |
6a443a0f MC |
2581 | if (phyid != PHY_ID_BCMAC131) { |
2582 | phyid &= PHY_BCM_OUI_MASK; | |
2583 | if (phyid == PHY_BCM_OUI_1 || | |
2584 | phyid == PHY_BCM_OUI_2 || | |
2585 | phyid == PHY_BCM_OUI_3) | |
0a459aac MC |
2586 | do_low_power = true; |
2587 | } | |
b02fd9e3 | 2588 | } |
dd477003 | 2589 | } else { |
2023276e | 2590 | do_low_power = true; |
0a459aac | 2591 | |
dd477003 MC |
2592 | if (tp->link_config.phy_is_low_power == 0) { |
2593 | tp->link_config.phy_is_low_power = 1; | |
2594 | tp->link_config.orig_speed = tp->link_config.speed; | |
2595 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
2596 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
2597 | } | |
1da177e4 | 2598 | |
dd477003 MC |
2599 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { |
2600 | tp->link_config.speed = SPEED_10; | |
2601 | tp->link_config.duplex = DUPLEX_HALF; | |
2602 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
2603 | tg3_setup_phy(tp, 0); | |
2604 | } | |
1da177e4 LT |
2605 | } |
2606 | ||
b5d3772c MC |
2607 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
2608 | u32 val; | |
2609 | ||
2610 | val = tr32(GRC_VCPU_EXT_CTRL); | |
2611 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL); | |
2612 | } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { | |
6921d201 MC |
2613 | int i; |
2614 | u32 val; | |
2615 | ||
2616 | for (i = 0; i < 200; i++) { | |
2617 | tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); | |
2618 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
2619 | break; | |
2620 | msleep(1); | |
2621 | } | |
2622 | } | |
a85feb8c GZ |
2623 | if (tp->tg3_flags & TG3_FLAG_WOL_CAP) |
2624 | tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | | |
2625 | WOL_DRV_STATE_SHUTDOWN | | |
2626 | WOL_DRV_WOL | | |
2627 | WOL_SET_MAGIC_PKT); | |
6921d201 | 2628 | |
05ac4cb7 | 2629 | if (device_should_wake) { |
1da177e4 LT |
2630 | u32 mac_mode; |
2631 | ||
2632 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
0a459aac | 2633 | if (do_low_power) { |
dd477003 MC |
2634 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a); |
2635 | udelay(40); | |
2636 | } | |
1da177e4 | 2637 | |
3f7045c1 MC |
2638 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
2639 | mac_mode = MAC_MODE_PORT_MODE_GMII; | |
2640 | else | |
2641 | mac_mode = MAC_MODE_PORT_MODE_MII; | |
1da177e4 | 2642 | |
e8f3f6ca MC |
2643 | mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; |
2644 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
2645 | ASIC_REV_5700) { | |
2646 | u32 speed = (tp->tg3_flags & | |
2647 | TG3_FLAG_WOL_SPEED_100MB) ? | |
2648 | SPEED_100 : SPEED_10; | |
2649 | if (tg3_5700_link_polarity(tp, speed)) | |
2650 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
2651 | else | |
2652 | mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
2653 | } | |
1da177e4 LT |
2654 | } else { |
2655 | mac_mode = MAC_MODE_PORT_MODE_TBI; | |
2656 | } | |
2657 | ||
cbf46853 | 2658 | if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) |
1da177e4 LT |
2659 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
2660 | ||
05ac4cb7 MC |
2661 | mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE; |
2662 | if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && | |
2663 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) && | |
2664 | ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
2665 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))) | |
2666 | mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL; | |
1da177e4 | 2667 | |
3bda1258 MC |
2668 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
2669 | mac_mode |= tp->mac_mode & | |
2670 | (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
2671 | if (mac_mode & MAC_MODE_APE_TX_EN) | |
2672 | mac_mode |= MAC_MODE_TDE_ENABLE; | |
2673 | } | |
2674 | ||
1da177e4 LT |
2675 | tw32_f(MAC_MODE, mac_mode); |
2676 | udelay(100); | |
2677 | ||
2678 | tw32_f(MAC_RX_MODE, RX_MODE_ENABLE); | |
2679 | udelay(10); | |
2680 | } | |
2681 | ||
2682 | if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) && | |
2683 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2684 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
2685 | u32 base_val; | |
2686 | ||
2687 | base_val = tp->pci_clock_ctrl; | |
2688 | base_val |= (CLOCK_CTRL_RXCLK_DISABLE | | |
2689 | CLOCK_CTRL_TXCLK_DISABLE); | |
2690 | ||
b401e9e2 MC |
2691 | tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK | |
2692 | CLOCK_CTRL_PWRDOWN_PLL133, 40); | |
d7b0a857 | 2693 | } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
795d01c5 | 2694 | (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
d7b0a857 | 2695 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) { |
4cf78e4f | 2696 | /* do nothing */ |
85e94ced | 2697 | } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
1da177e4 LT |
2698 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { |
2699 | u32 newbits1, newbits2; | |
2700 | ||
2701 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2702 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2703 | newbits1 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2704 | CLOCK_CTRL_TXCLK_DISABLE | | |
2705 | CLOCK_CTRL_ALTCLK); | |
2706 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2707 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
2708 | newbits1 = CLOCK_CTRL_625_CORE; | |
2709 | newbits2 = newbits1 | CLOCK_CTRL_ALTCLK; | |
2710 | } else { | |
2711 | newbits1 = CLOCK_CTRL_ALTCLK; | |
2712 | newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE; | |
2713 | } | |
2714 | ||
b401e9e2 MC |
2715 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, |
2716 | 40); | |
1da177e4 | 2717 | |
b401e9e2 MC |
2718 | tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, |
2719 | 40); | |
1da177e4 LT |
2720 | |
2721 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
2722 | u32 newbits3; | |
2723 | ||
2724 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
2725 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
2726 | newbits3 = (CLOCK_CTRL_RXCLK_DISABLE | | |
2727 | CLOCK_CTRL_TXCLK_DISABLE | | |
2728 | CLOCK_CTRL_44MHZ_CORE); | |
2729 | } else { | |
2730 | newbits3 = CLOCK_CTRL_44MHZ_CORE; | |
2731 | } | |
2732 | ||
b401e9e2 MC |
2733 | tw32_wait_f(TG3PCI_CLOCK_CTRL, |
2734 | tp->pci_clock_ctrl | newbits3, 40); | |
1da177e4 LT |
2735 | } |
2736 | } | |
2737 | ||
05ac4cb7 | 2738 | if (!(device_should_wake) && |
22435849 | 2739 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) |
0a459aac | 2740 | tg3_power_down_phy(tp, do_low_power); |
6921d201 | 2741 | |
1da177e4 LT |
2742 | tg3_frob_aux_power(tp); |
2743 | ||
2744 | /* Workaround for unstable PLL clock */ | |
2745 | if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) || | |
2746 | (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) { | |
2747 | u32 val = tr32(0x7d00); | |
2748 | ||
2749 | val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1); | |
2750 | tw32(0x7d00, val); | |
6921d201 | 2751 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
ec41c7df MC |
2752 | int err; |
2753 | ||
2754 | err = tg3_nvram_lock(tp); | |
1da177e4 | 2755 | tg3_halt_cpu(tp, RX_CPU_BASE); |
ec41c7df MC |
2756 | if (!err) |
2757 | tg3_nvram_unlock(tp); | |
6921d201 | 2758 | } |
1da177e4 LT |
2759 | } |
2760 | ||
bbadf503 MC |
2761 | tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); |
2762 | ||
05ac4cb7 | 2763 | if (device_should_wake) |
12dac075 RW |
2764 | pci_enable_wake(tp->pdev, state, true); |
2765 | ||
1da177e4 | 2766 | /* Finally, set the new power state. */ |
12dac075 | 2767 | pci_set_power_state(tp->pdev, state); |
1da177e4 | 2768 | |
1da177e4 LT |
2769 | return 0; |
2770 | } | |
2771 | ||
1da177e4 LT |
2772 | static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex) |
2773 | { | |
2774 | switch (val & MII_TG3_AUX_STAT_SPDMASK) { | |
2775 | case MII_TG3_AUX_STAT_10HALF: | |
2776 | *speed = SPEED_10; | |
2777 | *duplex = DUPLEX_HALF; | |
2778 | break; | |
2779 | ||
2780 | case MII_TG3_AUX_STAT_10FULL: | |
2781 | *speed = SPEED_10; | |
2782 | *duplex = DUPLEX_FULL; | |
2783 | break; | |
2784 | ||
2785 | case MII_TG3_AUX_STAT_100HALF: | |
2786 | *speed = SPEED_100; | |
2787 | *duplex = DUPLEX_HALF; | |
2788 | break; | |
2789 | ||
2790 | case MII_TG3_AUX_STAT_100FULL: | |
2791 | *speed = SPEED_100; | |
2792 | *duplex = DUPLEX_FULL; | |
2793 | break; | |
2794 | ||
2795 | case MII_TG3_AUX_STAT_1000HALF: | |
2796 | *speed = SPEED_1000; | |
2797 | *duplex = DUPLEX_HALF; | |
2798 | break; | |
2799 | ||
2800 | case MII_TG3_AUX_STAT_1000FULL: | |
2801 | *speed = SPEED_1000; | |
2802 | *duplex = DUPLEX_FULL; | |
2803 | break; | |
2804 | ||
2805 | default: | |
7f97a4bd | 2806 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
715116a1 MC |
2807 | *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 : |
2808 | SPEED_10; | |
2809 | *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL : | |
2810 | DUPLEX_HALF; | |
2811 | break; | |
2812 | } | |
1da177e4 LT |
2813 | *speed = SPEED_INVALID; |
2814 | *duplex = DUPLEX_INVALID; | |
2815 | break; | |
855e1111 | 2816 | } |
1da177e4 LT |
2817 | } |
2818 | ||
2819 | static void tg3_phy_copper_begin(struct tg3 *tp) | |
2820 | { | |
2821 | u32 new_adv; | |
2822 | int i; | |
2823 | ||
2824 | if (tp->link_config.phy_is_low_power) { | |
2825 | /* Entering low power mode. Disable gigabit and | |
2826 | * 100baseT advertisements. | |
2827 | */ | |
2828 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2829 | ||
2830 | new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2831 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
2832 | if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) | |
2833 | new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL); | |
2834 | ||
2835 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
2836 | } else if (tp->link_config.speed == SPEED_INVALID) { | |
1da177e4 LT |
2837 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) |
2838 | tp->link_config.advertising &= | |
2839 | ~(ADVERTISED_1000baseT_Half | | |
2840 | ADVERTISED_1000baseT_Full); | |
2841 | ||
ba4d07a8 | 2842 | new_adv = ADVERTISE_CSMA; |
1da177e4 LT |
2843 | if (tp->link_config.advertising & ADVERTISED_10baseT_Half) |
2844 | new_adv |= ADVERTISE_10HALF; | |
2845 | if (tp->link_config.advertising & ADVERTISED_10baseT_Full) | |
2846 | new_adv |= ADVERTISE_10FULL; | |
2847 | if (tp->link_config.advertising & ADVERTISED_100baseT_Half) | |
2848 | new_adv |= ADVERTISE_100HALF; | |
2849 | if (tp->link_config.advertising & ADVERTISED_100baseT_Full) | |
2850 | new_adv |= ADVERTISE_100FULL; | |
ba4d07a8 MC |
2851 | |
2852 | new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
2853 | ||
1da177e4 LT |
2854 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2855 | ||
2856 | if (tp->link_config.advertising & | |
2857 | (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { | |
2858 | new_adv = 0; | |
2859 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
2860 | new_adv |= MII_TG3_CTRL_ADV_1000_HALF; | |
2861 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
2862 | new_adv |= MII_TG3_CTRL_ADV_1000_FULL; | |
2863 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) && | |
2864 | (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2865 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) | |
2866 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2867 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
2868 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
2869 | } else { | |
2870 | tg3_writephy(tp, MII_TG3_CTRL, 0); | |
2871 | } | |
2872 | } else { | |
ba4d07a8 MC |
2873 | new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); |
2874 | new_adv |= ADVERTISE_CSMA; | |
2875 | ||
1da177e4 LT |
2876 | /* Asking for a specific link mode. */ |
2877 | if (tp->link_config.speed == SPEED_1000) { | |
1da177e4 LT |
2878 | tg3_writephy(tp, MII_ADVERTISE, new_adv); |
2879 | ||
2880 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2881 | new_adv = MII_TG3_CTRL_ADV_1000_FULL; | |
2882 | else | |
2883 | new_adv = MII_TG3_CTRL_ADV_1000_HALF; | |
2884 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
2885 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
2886 | new_adv |= (MII_TG3_CTRL_AS_MASTER | | |
2887 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
1da177e4 | 2888 | } else { |
1da177e4 LT |
2889 | if (tp->link_config.speed == SPEED_100) { |
2890 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2891 | new_adv |= ADVERTISE_100FULL; | |
2892 | else | |
2893 | new_adv |= ADVERTISE_100HALF; | |
2894 | } else { | |
2895 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2896 | new_adv |= ADVERTISE_10FULL; | |
2897 | else | |
2898 | new_adv |= ADVERTISE_10HALF; | |
2899 | } | |
2900 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
ba4d07a8 MC |
2901 | |
2902 | new_adv = 0; | |
1da177e4 | 2903 | } |
ba4d07a8 MC |
2904 | |
2905 | tg3_writephy(tp, MII_TG3_CTRL, new_adv); | |
1da177e4 LT |
2906 | } |
2907 | ||
2908 | if (tp->link_config.autoneg == AUTONEG_DISABLE && | |
2909 | tp->link_config.speed != SPEED_INVALID) { | |
2910 | u32 bmcr, orig_bmcr; | |
2911 | ||
2912 | tp->link_config.active_speed = tp->link_config.speed; | |
2913 | tp->link_config.active_duplex = tp->link_config.duplex; | |
2914 | ||
2915 | bmcr = 0; | |
2916 | switch (tp->link_config.speed) { | |
2917 | default: | |
2918 | case SPEED_10: | |
2919 | break; | |
2920 | ||
2921 | case SPEED_100: | |
2922 | bmcr |= BMCR_SPEED100; | |
2923 | break; | |
2924 | ||
2925 | case SPEED_1000: | |
2926 | bmcr |= TG3_BMCR_SPEED1000; | |
2927 | break; | |
855e1111 | 2928 | } |
1da177e4 LT |
2929 | |
2930 | if (tp->link_config.duplex == DUPLEX_FULL) | |
2931 | bmcr |= BMCR_FULLDPLX; | |
2932 | ||
2933 | if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && | |
2934 | (bmcr != orig_bmcr)) { | |
2935 | tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); | |
2936 | for (i = 0; i < 1500; i++) { | |
2937 | u32 tmp; | |
2938 | ||
2939 | udelay(10); | |
2940 | if (tg3_readphy(tp, MII_BMSR, &tmp) || | |
2941 | tg3_readphy(tp, MII_BMSR, &tmp)) | |
2942 | continue; | |
2943 | if (!(tmp & BMSR_LSTATUS)) { | |
2944 | udelay(40); | |
2945 | break; | |
2946 | } | |
2947 | } | |
2948 | tg3_writephy(tp, MII_BMCR, bmcr); | |
2949 | udelay(40); | |
2950 | } | |
2951 | } else { | |
2952 | tg3_writephy(tp, MII_BMCR, | |
2953 | BMCR_ANENABLE | BMCR_ANRESTART); | |
2954 | } | |
2955 | } | |
2956 | ||
2957 | static int tg3_init_5401phy_dsp(struct tg3 *tp) | |
2958 | { | |
2959 | int err; | |
2960 | ||
2961 | /* Turn off tap power management. */ | |
2962 | /* Set Extended packet length bit */ | |
2963 | err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); | |
2964 | ||
2965 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012); | |
2966 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804); | |
2967 | ||
2968 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013); | |
2969 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204); | |
2970 | ||
2971 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2972 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132); | |
2973 | ||
2974 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006); | |
2975 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232); | |
2976 | ||
2977 | err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f); | |
2978 | err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20); | |
2979 | ||
2980 | udelay(40); | |
2981 | ||
2982 | return err; | |
2983 | } | |
2984 | ||
3600d918 | 2985 | static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask) |
1da177e4 | 2986 | { |
3600d918 MC |
2987 | u32 adv_reg, all_mask = 0; |
2988 | ||
2989 | if (mask & ADVERTISED_10baseT_Half) | |
2990 | all_mask |= ADVERTISE_10HALF; | |
2991 | if (mask & ADVERTISED_10baseT_Full) | |
2992 | all_mask |= ADVERTISE_10FULL; | |
2993 | if (mask & ADVERTISED_100baseT_Half) | |
2994 | all_mask |= ADVERTISE_100HALF; | |
2995 | if (mask & ADVERTISED_100baseT_Full) | |
2996 | all_mask |= ADVERTISE_100FULL; | |
1da177e4 LT |
2997 | |
2998 | if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg)) | |
2999 | return 0; | |
3000 | ||
1da177e4 LT |
3001 | if ((adv_reg & all_mask) != all_mask) |
3002 | return 0; | |
3003 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
3004 | u32 tg3_ctrl; | |
3005 | ||
3600d918 MC |
3006 | all_mask = 0; |
3007 | if (mask & ADVERTISED_1000baseT_Half) | |
3008 | all_mask |= ADVERTISE_1000HALF; | |
3009 | if (mask & ADVERTISED_1000baseT_Full) | |
3010 | all_mask |= ADVERTISE_1000FULL; | |
3011 | ||
1da177e4 LT |
3012 | if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl)) |
3013 | return 0; | |
3014 | ||
1da177e4 LT |
3015 | if ((tg3_ctrl & all_mask) != all_mask) |
3016 | return 0; | |
3017 | } | |
3018 | return 1; | |
3019 | } | |
3020 | ||
ef167e27 MC |
3021 | static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv) |
3022 | { | |
3023 | u32 curadv, reqadv; | |
3024 | ||
3025 | if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) | |
3026 | return 1; | |
3027 | ||
3028 | curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM); | |
3029 | reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl); | |
3030 | ||
3031 | if (tp->link_config.active_duplex == DUPLEX_FULL) { | |
3032 | if (curadv != reqadv) | |
3033 | return 0; | |
3034 | ||
3035 | if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) | |
3036 | tg3_readphy(tp, MII_LPA, rmtadv); | |
3037 | } else { | |
3038 | /* Reprogram the advertisement register, even if it | |
3039 | * does not affect the current link. If the link | |
3040 | * gets renegotiated in the future, we can save an | |
3041 | * additional renegotiation cycle by advertising | |
3042 | * it correctly in the first place. | |
3043 | */ | |
3044 | if (curadv != reqadv) { | |
3045 | *lcladv &= ~(ADVERTISE_PAUSE_CAP | | |
3046 | ADVERTISE_PAUSE_ASYM); | |
3047 | tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv); | |
3048 | } | |
3049 | } | |
3050 | ||
3051 | return 1; | |
3052 | } | |
3053 | ||
1da177e4 LT |
3054 | static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset) |
3055 | { | |
3056 | int current_link_up; | |
3057 | u32 bmsr, dummy; | |
ef167e27 | 3058 | u32 lcl_adv, rmt_adv; |
1da177e4 LT |
3059 | u16 current_speed; |
3060 | u8 current_duplex; | |
3061 | int i, err; | |
3062 | ||
3063 | tw32(MAC_EVENT, 0); | |
3064 | ||
3065 | tw32_f(MAC_STATUS, | |
3066 | (MAC_STATUS_SYNC_CHANGED | | |
3067 | MAC_STATUS_CFG_CHANGED | | |
3068 | MAC_STATUS_MI_COMPLETION | | |
3069 | MAC_STATUS_LNKSTATE_CHANGED)); | |
3070 | udelay(40); | |
3071 | ||
8ef21428 MC |
3072 | if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { |
3073 | tw32_f(MAC_MI_MODE, | |
3074 | (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); | |
3075 | udelay(80); | |
3076 | } | |
1da177e4 LT |
3077 | |
3078 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02); | |
3079 | ||
3080 | /* Some third-party PHYs need to be reset on link going | |
3081 | * down. | |
3082 | */ | |
3083 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
3084 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || | |
3085 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
3086 | netif_carrier_ok(tp->dev)) { | |
3087 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3088 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3089 | !(bmsr & BMSR_LSTATUS)) | |
3090 | force_reset = 1; | |
3091 | } | |
3092 | if (force_reset) | |
3093 | tg3_phy_reset(tp); | |
3094 | ||
79eb6904 | 3095 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
3096 | tg3_readphy(tp, MII_BMSR, &bmsr); |
3097 | if (tg3_readphy(tp, MII_BMSR, &bmsr) || | |
3098 | !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) | |
3099 | bmsr = 0; | |
3100 | ||
3101 | if (!(bmsr & BMSR_LSTATUS)) { | |
3102 | err = tg3_init_5401phy_dsp(tp); | |
3103 | if (err) | |
3104 | return err; | |
3105 | ||
3106 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3107 | for (i = 0; i < 1000; i++) { | |
3108 | udelay(10); | |
3109 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3110 | (bmsr & BMSR_LSTATUS)) { | |
3111 | udelay(40); | |
3112 | break; | |
3113 | } | |
3114 | } | |
3115 | ||
79eb6904 MC |
3116 | if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == |
3117 | TG3_PHY_REV_BCM5401_B0 && | |
1da177e4 LT |
3118 | !(bmsr & BMSR_LSTATUS) && |
3119 | tp->link_config.active_speed == SPEED_1000) { | |
3120 | err = tg3_phy_reset(tp); | |
3121 | if (!err) | |
3122 | err = tg3_init_5401phy_dsp(tp); | |
3123 | if (err) | |
3124 | return err; | |
3125 | } | |
3126 | } | |
3127 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
3128 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) { | |
3129 | /* 5701 {A0,B0} CRC bug workaround */ | |
3130 | tg3_writephy(tp, 0x15, 0x0a75); | |
3131 | tg3_writephy(tp, 0x1c, 0x8c68); | |
3132 | tg3_writephy(tp, 0x1c, 0x8d68); | |
3133 | tg3_writephy(tp, 0x1c, 0x8c68); | |
3134 | } | |
3135 | ||
3136 | /* Clear pending interrupts... */ | |
3137 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
3138 | tg3_readphy(tp, MII_TG3_ISTAT, &dummy); | |
3139 | ||
3140 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) | |
3141 | tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); | |
7f97a4bd | 3142 | else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) |
1da177e4 LT |
3143 | tg3_writephy(tp, MII_TG3_IMASK, ~0); |
3144 | ||
3145 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
3146 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
3147 | if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) | |
3148 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | |
3149 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
3150 | else | |
3151 | tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); | |
3152 | } | |
3153 | ||
3154 | current_link_up = 0; | |
3155 | current_speed = SPEED_INVALID; | |
3156 | current_duplex = DUPLEX_INVALID; | |
3157 | ||
3158 | if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) { | |
3159 | u32 val; | |
3160 | ||
3161 | tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007); | |
3162 | tg3_readphy(tp, MII_TG3_AUX_CTRL, &val); | |
3163 | if (!(val & (1 << 10))) { | |
3164 | val |= (1 << 10); | |
3165 | tg3_writephy(tp, MII_TG3_AUX_CTRL, val); | |
3166 | goto relink; | |
3167 | } | |
3168 | } | |
3169 | ||
3170 | bmsr = 0; | |
3171 | for (i = 0; i < 100; i++) { | |
3172 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
3173 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
3174 | (bmsr & BMSR_LSTATUS)) | |
3175 | break; | |
3176 | udelay(40); | |
3177 | } | |
3178 | ||
3179 | if (bmsr & BMSR_LSTATUS) { | |
3180 | u32 aux_stat, bmcr; | |
3181 | ||
3182 | tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); | |
3183 | for (i = 0; i < 2000; i++) { | |
3184 | udelay(10); | |
3185 | if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && | |
3186 | aux_stat) | |
3187 | break; | |
3188 | } | |
3189 | ||
3190 | tg3_aux_stat_to_speed_duplex(tp, aux_stat, | |
3191 | ¤t_speed, | |
3192 | ¤t_duplex); | |
3193 | ||
3194 | bmcr = 0; | |
3195 | for (i = 0; i < 200; i++) { | |
3196 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
3197 | if (tg3_readphy(tp, MII_BMCR, &bmcr)) | |
3198 | continue; | |
3199 | if (bmcr && bmcr != 0x7fff) | |
3200 | break; | |
3201 | udelay(10); | |
3202 | } | |
3203 | ||
ef167e27 MC |
3204 | lcl_adv = 0; |
3205 | rmt_adv = 0; | |
1da177e4 | 3206 | |
ef167e27 MC |
3207 | tp->link_config.active_speed = current_speed; |
3208 | tp->link_config.active_duplex = current_duplex; | |
3209 | ||
3210 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
3211 | if ((bmcr & BMCR_ANENABLE) && | |
3212 | tg3_copper_is_advertising_all(tp, | |
3213 | tp->link_config.advertising)) { | |
3214 | if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv, | |
3215 | &rmt_adv)) | |
3216 | current_link_up = 1; | |
1da177e4 LT |
3217 | } |
3218 | } else { | |
3219 | if (!(bmcr & BMCR_ANENABLE) && | |
3220 | tp->link_config.speed == current_speed && | |
ef167e27 MC |
3221 | tp->link_config.duplex == current_duplex && |
3222 | tp->link_config.flowctrl == | |
3223 | tp->link_config.active_flowctrl) { | |
1da177e4 | 3224 | current_link_up = 1; |
1da177e4 LT |
3225 | } |
3226 | } | |
3227 | ||
ef167e27 MC |
3228 | if (current_link_up == 1 && |
3229 | tp->link_config.active_duplex == DUPLEX_FULL) | |
3230 | tg3_setup_flow_control(tp, lcl_adv, rmt_adv); | |
1da177e4 LT |
3231 | } |
3232 | ||
1da177e4 | 3233 | relink: |
6921d201 | 3234 | if (current_link_up == 0 || tp->link_config.phy_is_low_power) { |
1da177e4 LT |
3235 | u32 tmp; |
3236 | ||
3237 | tg3_phy_copper_begin(tp); | |
3238 | ||
3239 | tg3_readphy(tp, MII_BMSR, &tmp); | |
3240 | if (!tg3_readphy(tp, MII_BMSR, &tmp) && | |
3241 | (tmp & BMSR_LSTATUS)) | |
3242 | current_link_up = 1; | |
3243 | } | |
3244 | ||
3245 | tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; | |
3246 | if (current_link_up == 1) { | |
3247 | if (tp->link_config.active_speed == SPEED_100 || | |
3248 | tp->link_config.active_speed == SPEED_10) | |
3249 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3250 | else | |
3251 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
7f97a4bd MC |
3252 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) |
3253 | tp->mac_mode |= MAC_MODE_PORT_MODE_MII; | |
3254 | else | |
1da177e4 LT |
3255 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; |
3256 | ||
3257 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; | |
3258 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
3259 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
3260 | ||
1da177e4 | 3261 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
e8f3f6ca MC |
3262 | if (current_link_up == 1 && |
3263 | tg3_5700_link_polarity(tp, tp->link_config.active_speed)) | |
1da177e4 | 3264 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; |
e8f3f6ca MC |
3265 | else |
3266 | tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
3267 | } |
3268 | ||
3269 | /* ??? Without this setting Netgear GA302T PHY does not | |
3270 | * ??? send/receive packets... | |
3271 | */ | |
79eb6904 | 3272 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && |
1da177e4 LT |
3273 | tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) { |
3274 | tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; | |
3275 | tw32_f(MAC_MI_MODE, tp->mi_mode); | |
3276 | udelay(80); | |
3277 | } | |
3278 | ||
3279 | tw32_f(MAC_MODE, tp->mac_mode); | |
3280 | udelay(40); | |
3281 | ||
3282 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { | |
3283 | /* Polled via timer. */ | |
3284 | tw32_f(MAC_EVENT, 0); | |
3285 | } else { | |
3286 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3287 | } | |
3288 | udelay(40); | |
3289 | ||
3290 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 && | |
3291 | current_link_up == 1 && | |
3292 | tp->link_config.active_speed == SPEED_1000 && | |
3293 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) || | |
3294 | (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) { | |
3295 | udelay(120); | |
3296 | tw32_f(MAC_STATUS, | |
3297 | (MAC_STATUS_SYNC_CHANGED | | |
3298 | MAC_STATUS_CFG_CHANGED)); | |
3299 | udelay(40); | |
3300 | tg3_write_mem(tp, | |
3301 | NIC_SRAM_FIRMWARE_MBOX, | |
3302 | NIC_SRAM_FIRMWARE_MBOX_MAGIC2); | |
3303 | } | |
3304 | ||
5e7dfd0f MC |
3305 | /* Prevent send BD corruption. */ |
3306 | if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) { | |
3307 | u16 oldlnkctl, newlnkctl; | |
3308 | ||
3309 | pci_read_config_word(tp->pdev, | |
3310 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3311 | &oldlnkctl); | |
3312 | if (tp->link_config.active_speed == SPEED_100 || | |
3313 | tp->link_config.active_speed == SPEED_10) | |
3314 | newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3315 | else | |
3316 | newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN; | |
3317 | if (newlnkctl != oldlnkctl) | |
3318 | pci_write_config_word(tp->pdev, | |
3319 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
3320 | newlnkctl); | |
3321 | } | |
3322 | ||
1da177e4 LT |
3323 | if (current_link_up != netif_carrier_ok(tp->dev)) { |
3324 | if (current_link_up) | |
3325 | netif_carrier_on(tp->dev); | |
3326 | else | |
3327 | netif_carrier_off(tp->dev); | |
3328 | tg3_link_report(tp); | |
3329 | } | |
3330 | ||
3331 | return 0; | |
3332 | } | |
3333 | ||
3334 | struct tg3_fiber_aneginfo { | |
3335 | int state; | |
3336 | #define ANEG_STATE_UNKNOWN 0 | |
3337 | #define ANEG_STATE_AN_ENABLE 1 | |
3338 | #define ANEG_STATE_RESTART_INIT 2 | |
3339 | #define ANEG_STATE_RESTART 3 | |
3340 | #define ANEG_STATE_DISABLE_LINK_OK 4 | |
3341 | #define ANEG_STATE_ABILITY_DETECT_INIT 5 | |
3342 | #define ANEG_STATE_ABILITY_DETECT 6 | |
3343 | #define ANEG_STATE_ACK_DETECT_INIT 7 | |
3344 | #define ANEG_STATE_ACK_DETECT 8 | |
3345 | #define ANEG_STATE_COMPLETE_ACK_INIT 9 | |
3346 | #define ANEG_STATE_COMPLETE_ACK 10 | |
3347 | #define ANEG_STATE_IDLE_DETECT_INIT 11 | |
3348 | #define ANEG_STATE_IDLE_DETECT 12 | |
3349 | #define ANEG_STATE_LINK_OK 13 | |
3350 | #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 | |
3351 | #define ANEG_STATE_NEXT_PAGE_WAIT 15 | |
3352 | ||
3353 | u32 flags; | |
3354 | #define MR_AN_ENABLE 0x00000001 | |
3355 | #define MR_RESTART_AN 0x00000002 | |
3356 | #define MR_AN_COMPLETE 0x00000004 | |
3357 | #define MR_PAGE_RX 0x00000008 | |
3358 | #define MR_NP_LOADED 0x00000010 | |
3359 | #define MR_TOGGLE_TX 0x00000020 | |
3360 | #define MR_LP_ADV_FULL_DUPLEX 0x00000040 | |
3361 | #define MR_LP_ADV_HALF_DUPLEX 0x00000080 | |
3362 | #define MR_LP_ADV_SYM_PAUSE 0x00000100 | |
3363 | #define MR_LP_ADV_ASYM_PAUSE 0x00000200 | |
3364 | #define MR_LP_ADV_REMOTE_FAULT1 0x00000400 | |
3365 | #define MR_LP_ADV_REMOTE_FAULT2 0x00000800 | |
3366 | #define MR_LP_ADV_NEXT_PAGE 0x00001000 | |
3367 | #define MR_TOGGLE_RX 0x00002000 | |
3368 | #define MR_NP_RX 0x00004000 | |
3369 | ||
3370 | #define MR_LINK_OK 0x80000000 | |
3371 | ||
3372 | unsigned long link_time, cur_time; | |
3373 | ||
3374 | u32 ability_match_cfg; | |
3375 | int ability_match_count; | |
3376 | ||
3377 | char ability_match, idle_match, ack_match; | |
3378 | ||
3379 | u32 txconfig, rxconfig; | |
3380 | #define ANEG_CFG_NP 0x00000080 | |
3381 | #define ANEG_CFG_ACK 0x00000040 | |
3382 | #define ANEG_CFG_RF2 0x00000020 | |
3383 | #define ANEG_CFG_RF1 0x00000010 | |
3384 | #define ANEG_CFG_PS2 0x00000001 | |
3385 | #define ANEG_CFG_PS1 0x00008000 | |
3386 | #define ANEG_CFG_HD 0x00004000 | |
3387 | #define ANEG_CFG_FD 0x00002000 | |
3388 | #define ANEG_CFG_INVAL 0x00001f06 | |
3389 | ||
3390 | }; | |
3391 | #define ANEG_OK 0 | |
3392 | #define ANEG_DONE 1 | |
3393 | #define ANEG_TIMER_ENAB 2 | |
3394 | #define ANEG_FAILED -1 | |
3395 | ||
3396 | #define ANEG_STATE_SETTLE_TIME 10000 | |
3397 | ||
3398 | static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |
3399 | struct tg3_fiber_aneginfo *ap) | |
3400 | { | |
5be73b47 | 3401 | u16 flowctrl; |
1da177e4 LT |
3402 | unsigned long delta; |
3403 | u32 rx_cfg_reg; | |
3404 | int ret; | |
3405 | ||
3406 | if (ap->state == ANEG_STATE_UNKNOWN) { | |
3407 | ap->rxconfig = 0; | |
3408 | ap->link_time = 0; | |
3409 | ap->cur_time = 0; | |
3410 | ap->ability_match_cfg = 0; | |
3411 | ap->ability_match_count = 0; | |
3412 | ap->ability_match = 0; | |
3413 | ap->idle_match = 0; | |
3414 | ap->ack_match = 0; | |
3415 | } | |
3416 | ap->cur_time++; | |
3417 | ||
3418 | if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) { | |
3419 | rx_cfg_reg = tr32(MAC_RX_AUTO_NEG); | |
3420 | ||
3421 | if (rx_cfg_reg != ap->ability_match_cfg) { | |
3422 | ap->ability_match_cfg = rx_cfg_reg; | |
3423 | ap->ability_match = 0; | |
3424 | ap->ability_match_count = 0; | |
3425 | } else { | |
3426 | if (++ap->ability_match_count > 1) { | |
3427 | ap->ability_match = 1; | |
3428 | ap->ability_match_cfg = rx_cfg_reg; | |
3429 | } | |
3430 | } | |
3431 | if (rx_cfg_reg & ANEG_CFG_ACK) | |
3432 | ap->ack_match = 1; | |
3433 | else | |
3434 | ap->ack_match = 0; | |
3435 | ||
3436 | ap->idle_match = 0; | |
3437 | } else { | |
3438 | ap->idle_match = 1; | |
3439 | ap->ability_match_cfg = 0; | |
3440 | ap->ability_match_count = 0; | |
3441 | ap->ability_match = 0; | |
3442 | ap->ack_match = 0; | |
3443 | ||
3444 | rx_cfg_reg = 0; | |
3445 | } | |
3446 | ||
3447 | ap->rxconfig = rx_cfg_reg; | |
3448 | ret = ANEG_OK; | |
3449 | ||
33f401ae | 3450 | switch (ap->state) { |
1da177e4 LT |
3451 | case ANEG_STATE_UNKNOWN: |
3452 | if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) | |
3453 | ap->state = ANEG_STATE_AN_ENABLE; | |
3454 | ||
3455 | /* fallthru */ | |
3456 | case ANEG_STATE_AN_ENABLE: | |
3457 | ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); | |
3458 | if (ap->flags & MR_AN_ENABLE) { | |
3459 | ap->link_time = 0; | |
3460 | ap->cur_time = 0; | |
3461 | ap->ability_match_cfg = 0; | |
3462 | ap->ability_match_count = 0; | |
3463 | ap->ability_match = 0; | |
3464 | ap->idle_match = 0; | |
3465 | ap->ack_match = 0; | |
3466 | ||
3467 | ap->state = ANEG_STATE_RESTART_INIT; | |
3468 | } else { | |
3469 | ap->state = ANEG_STATE_DISABLE_LINK_OK; | |
3470 | } | |
3471 | break; | |
3472 | ||
3473 | case ANEG_STATE_RESTART_INIT: | |
3474 | ap->link_time = ap->cur_time; | |
3475 | ap->flags &= ~(MR_NP_LOADED); | |
3476 | ap->txconfig = 0; | |
3477 | tw32(MAC_TX_AUTO_NEG, 0); | |
3478 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3479 | tw32_f(MAC_MODE, tp->mac_mode); | |
3480 | udelay(40); | |
3481 | ||
3482 | ret = ANEG_TIMER_ENAB; | |
3483 | ap->state = ANEG_STATE_RESTART; | |
3484 | ||
3485 | /* fallthru */ | |
3486 | case ANEG_STATE_RESTART: | |
3487 | delta = ap->cur_time - ap->link_time; | |
859a5887 | 3488 | if (delta > ANEG_STATE_SETTLE_TIME) |
1da177e4 | 3489 | ap->state = ANEG_STATE_ABILITY_DETECT_INIT; |
859a5887 | 3490 | else |
1da177e4 | 3491 | ret = ANEG_TIMER_ENAB; |
1da177e4 LT |
3492 | break; |
3493 | ||
3494 | case ANEG_STATE_DISABLE_LINK_OK: | |
3495 | ret = ANEG_DONE; | |
3496 | break; | |
3497 | ||
3498 | case ANEG_STATE_ABILITY_DETECT_INIT: | |
3499 | ap->flags &= ~(MR_TOGGLE_TX); | |
5be73b47 MC |
3500 | ap->txconfig = ANEG_CFG_FD; |
3501 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); | |
3502 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3503 | ap->txconfig |= ANEG_CFG_PS1; | |
3504 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3505 | ap->txconfig |= ANEG_CFG_PS2; | |
1da177e4 LT |
3506 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); |
3507 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3508 | tw32_f(MAC_MODE, tp->mac_mode); | |
3509 | udelay(40); | |
3510 | ||
3511 | ap->state = ANEG_STATE_ABILITY_DETECT; | |
3512 | break; | |
3513 | ||
3514 | case ANEG_STATE_ABILITY_DETECT: | |
859a5887 | 3515 | if (ap->ability_match != 0 && ap->rxconfig != 0) |
1da177e4 | 3516 | ap->state = ANEG_STATE_ACK_DETECT_INIT; |
1da177e4 LT |
3517 | break; |
3518 | ||
3519 | case ANEG_STATE_ACK_DETECT_INIT: | |
3520 | ap->txconfig |= ANEG_CFG_ACK; | |
3521 | tw32(MAC_TX_AUTO_NEG, ap->txconfig); | |
3522 | tp->mac_mode |= MAC_MODE_SEND_CONFIGS; | |
3523 | tw32_f(MAC_MODE, tp->mac_mode); | |
3524 | udelay(40); | |
3525 | ||
3526 | ap->state = ANEG_STATE_ACK_DETECT; | |
3527 | ||
3528 | /* fallthru */ | |
3529 | case ANEG_STATE_ACK_DETECT: | |
3530 | if (ap->ack_match != 0) { | |
3531 | if ((ap->rxconfig & ~ANEG_CFG_ACK) == | |
3532 | (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { | |
3533 | ap->state = ANEG_STATE_COMPLETE_ACK_INIT; | |
3534 | } else { | |
3535 | ap->state = ANEG_STATE_AN_ENABLE; | |
3536 | } | |
3537 | } else if (ap->ability_match != 0 && | |
3538 | ap->rxconfig == 0) { | |
3539 | ap->state = ANEG_STATE_AN_ENABLE; | |
3540 | } | |
3541 | break; | |
3542 | ||
3543 | case ANEG_STATE_COMPLETE_ACK_INIT: | |
3544 | if (ap->rxconfig & ANEG_CFG_INVAL) { | |
3545 | ret = ANEG_FAILED; | |
3546 | break; | |
3547 | } | |
3548 | ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | | |
3549 | MR_LP_ADV_HALF_DUPLEX | | |
3550 | MR_LP_ADV_SYM_PAUSE | | |
3551 | MR_LP_ADV_ASYM_PAUSE | | |
3552 | MR_LP_ADV_REMOTE_FAULT1 | | |
3553 | MR_LP_ADV_REMOTE_FAULT2 | | |
3554 | MR_LP_ADV_NEXT_PAGE | | |
3555 | MR_TOGGLE_RX | | |
3556 | MR_NP_RX); | |
3557 | if (ap->rxconfig & ANEG_CFG_FD) | |
3558 | ap->flags |= MR_LP_ADV_FULL_DUPLEX; | |
3559 | if (ap->rxconfig & ANEG_CFG_HD) | |
3560 | ap->flags |= MR_LP_ADV_HALF_DUPLEX; | |
3561 | if (ap->rxconfig & ANEG_CFG_PS1) | |
3562 | ap->flags |= MR_LP_ADV_SYM_PAUSE; | |
3563 | if (ap->rxconfig & ANEG_CFG_PS2) | |
3564 | ap->flags |= MR_LP_ADV_ASYM_PAUSE; | |
3565 | if (ap->rxconfig & ANEG_CFG_RF1) | |
3566 | ap->flags |= MR_LP_ADV_REMOTE_FAULT1; | |
3567 | if (ap->rxconfig & ANEG_CFG_RF2) | |
3568 | ap->flags |= MR_LP_ADV_REMOTE_FAULT2; | |
3569 | if (ap->rxconfig & ANEG_CFG_NP) | |
3570 | ap->flags |= MR_LP_ADV_NEXT_PAGE; | |
3571 | ||
3572 | ap->link_time = ap->cur_time; | |
3573 | ||
3574 | ap->flags ^= (MR_TOGGLE_TX); | |
3575 | if (ap->rxconfig & 0x0008) | |
3576 | ap->flags |= MR_TOGGLE_RX; | |
3577 | if (ap->rxconfig & ANEG_CFG_NP) | |
3578 | ap->flags |= MR_NP_RX; | |
3579 | ap->flags |= MR_PAGE_RX; | |
3580 | ||
3581 | ap->state = ANEG_STATE_COMPLETE_ACK; | |
3582 | ret = ANEG_TIMER_ENAB; | |
3583 | break; | |
3584 | ||
3585 | case ANEG_STATE_COMPLETE_ACK: | |
3586 | if (ap->ability_match != 0 && | |
3587 | ap->rxconfig == 0) { | |
3588 | ap->state = ANEG_STATE_AN_ENABLE; | |
3589 | break; | |
3590 | } | |
3591 | delta = ap->cur_time - ap->link_time; | |
3592 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3593 | if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { | |
3594 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3595 | } else { | |
3596 | if ((ap->txconfig & ANEG_CFG_NP) == 0 && | |
3597 | !(ap->flags & MR_NP_RX)) { | |
3598 | ap->state = ANEG_STATE_IDLE_DETECT_INIT; | |
3599 | } else { | |
3600 | ret = ANEG_FAILED; | |
3601 | } | |
3602 | } | |
3603 | } | |
3604 | break; | |
3605 | ||
3606 | case ANEG_STATE_IDLE_DETECT_INIT: | |
3607 | ap->link_time = ap->cur_time; | |
3608 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3609 | tw32_f(MAC_MODE, tp->mac_mode); | |
3610 | udelay(40); | |
3611 | ||
3612 | ap->state = ANEG_STATE_IDLE_DETECT; | |
3613 | ret = ANEG_TIMER_ENAB; | |
3614 | break; | |
3615 | ||
3616 | case ANEG_STATE_IDLE_DETECT: | |
3617 | if (ap->ability_match != 0 && | |
3618 | ap->rxconfig == 0) { | |
3619 | ap->state = ANEG_STATE_AN_ENABLE; | |
3620 | break; | |
3621 | } | |
3622 | delta = ap->cur_time - ap->link_time; | |
3623 | if (delta > ANEG_STATE_SETTLE_TIME) { | |
3624 | /* XXX another gem from the Broadcom driver :( */ | |
3625 | ap->state = ANEG_STATE_LINK_OK; | |
3626 | } | |
3627 | break; | |
3628 | ||
3629 | case ANEG_STATE_LINK_OK: | |
3630 | ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); | |
3631 | ret = ANEG_DONE; | |
3632 | break; | |
3633 | ||
3634 | case ANEG_STATE_NEXT_PAGE_WAIT_INIT: | |
3635 | /* ??? unimplemented */ | |
3636 | break; | |
3637 | ||
3638 | case ANEG_STATE_NEXT_PAGE_WAIT: | |
3639 | /* ??? unimplemented */ | |
3640 | break; | |
3641 | ||
3642 | default: | |
3643 | ret = ANEG_FAILED; | |
3644 | break; | |
855e1111 | 3645 | } |
1da177e4 LT |
3646 | |
3647 | return ret; | |
3648 | } | |
3649 | ||
5be73b47 | 3650 | static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) |
1da177e4 LT |
3651 | { |
3652 | int res = 0; | |
3653 | struct tg3_fiber_aneginfo aninfo; | |
3654 | int status = ANEG_FAILED; | |
3655 | unsigned int tick; | |
3656 | u32 tmp; | |
3657 | ||
3658 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3659 | ||
3660 | tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; | |
3661 | tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII); | |
3662 | udelay(40); | |
3663 | ||
3664 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); | |
3665 | udelay(40); | |
3666 | ||
3667 | memset(&aninfo, 0, sizeof(aninfo)); | |
3668 | aninfo.flags |= MR_AN_ENABLE; | |
3669 | aninfo.state = ANEG_STATE_UNKNOWN; | |
3670 | aninfo.cur_time = 0; | |
3671 | tick = 0; | |
3672 | while (++tick < 195000) { | |
3673 | status = tg3_fiber_aneg_smachine(tp, &aninfo); | |
3674 | if (status == ANEG_DONE || status == ANEG_FAILED) | |
3675 | break; | |
3676 | ||
3677 | udelay(1); | |
3678 | } | |
3679 | ||
3680 | tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; | |
3681 | tw32_f(MAC_MODE, tp->mac_mode); | |
3682 | udelay(40); | |
3683 | ||
5be73b47 MC |
3684 | *txflags = aninfo.txconfig; |
3685 | *rxflags = aninfo.flags; | |
1da177e4 LT |
3686 | |
3687 | if (status == ANEG_DONE && | |
3688 | (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK | | |
3689 | MR_LP_ADV_FULL_DUPLEX))) | |
3690 | res = 1; | |
3691 | ||
3692 | return res; | |
3693 | } | |
3694 | ||
3695 | static void tg3_init_bcm8002(struct tg3 *tp) | |
3696 | { | |
3697 | u32 mac_status = tr32(MAC_STATUS); | |
3698 | int i; | |
3699 | ||
3700 | /* Reset when initting first time or we have a link. */ | |
3701 | if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) && | |
3702 | !(mac_status & MAC_STATUS_PCS_SYNCED)) | |
3703 | return; | |
3704 | ||
3705 | /* Set PLL lock range. */ | |
3706 | tg3_writephy(tp, 0x16, 0x8007); | |
3707 | ||
3708 | /* SW reset */ | |
3709 | tg3_writephy(tp, MII_BMCR, BMCR_RESET); | |
3710 | ||
3711 | /* Wait for reset to complete. */ | |
3712 | /* XXX schedule_timeout() ... */ | |
3713 | for (i = 0; i < 500; i++) | |
3714 | udelay(10); | |
3715 | ||
3716 | /* Config mode; select PMA/Ch 1 regs. */ | |
3717 | tg3_writephy(tp, 0x10, 0x8411); | |
3718 | ||
3719 | /* Enable auto-lock and comdet, select txclk for tx. */ | |
3720 | tg3_writephy(tp, 0x11, 0x0a10); | |
3721 | ||
3722 | tg3_writephy(tp, 0x18, 0x00a0); | |
3723 | tg3_writephy(tp, 0x16, 0x41ff); | |
3724 | ||
3725 | /* Assert and deassert POR. */ | |
3726 | tg3_writephy(tp, 0x13, 0x0400); | |
3727 | udelay(40); | |
3728 | tg3_writephy(tp, 0x13, 0x0000); | |
3729 | ||
3730 | tg3_writephy(tp, 0x11, 0x0a50); | |
3731 | udelay(40); | |
3732 | tg3_writephy(tp, 0x11, 0x0a10); | |
3733 | ||
3734 | /* Wait for signal to stabilize */ | |
3735 | /* XXX schedule_timeout() ... */ | |
3736 | for (i = 0; i < 15000; i++) | |
3737 | udelay(10); | |
3738 | ||
3739 | /* Deselect the channel register so we can read the PHYID | |
3740 | * later. | |
3741 | */ | |
3742 | tg3_writephy(tp, 0x10, 0x8011); | |
3743 | } | |
3744 | ||
3745 | static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) | |
3746 | { | |
82cd3d11 | 3747 | u16 flowctrl; |
1da177e4 LT |
3748 | u32 sg_dig_ctrl, sg_dig_status; |
3749 | u32 serdes_cfg, expected_sg_dig_ctrl; | |
3750 | int workaround, port_a; | |
3751 | int current_link_up; | |
3752 | ||
3753 | serdes_cfg = 0; | |
3754 | expected_sg_dig_ctrl = 0; | |
3755 | workaround = 0; | |
3756 | port_a = 1; | |
3757 | current_link_up = 0; | |
3758 | ||
3759 | if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 && | |
3760 | tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) { | |
3761 | workaround = 1; | |
3762 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) | |
3763 | port_a = 0; | |
3764 | ||
3765 | /* preserve bits 0-11,13,14 for signal pre-emphasis */ | |
3766 | /* preserve bits 20-23 for voltage regulator */ | |
3767 | serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff; | |
3768 | } | |
3769 | ||
3770 | sg_dig_ctrl = tr32(SG_DIG_CTRL); | |
3771 | ||
3772 | if (tp->link_config.autoneg != AUTONEG_ENABLE) { | |
c98f6e3b | 3773 | if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) { |
1da177e4 LT |
3774 | if (workaround) { |
3775 | u32 val = serdes_cfg; | |
3776 | ||
3777 | if (port_a) | |
3778 | val |= 0xc010000; | |
3779 | else | |
3780 | val |= 0x4010000; | |
3781 | tw32_f(MAC_SERDES_CFG, val); | |
3782 | } | |
c98f6e3b MC |
3783 | |
3784 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); | |
1da177e4 LT |
3785 | } |
3786 | if (mac_status & MAC_STATUS_PCS_SYNCED) { | |
3787 | tg3_setup_flow_control(tp, 0, 0); | |
3788 | current_link_up = 1; | |
3789 | } | |
3790 | goto out; | |
3791 | } | |
3792 | ||
3793 | /* Want auto-negotiation. */ | |
c98f6e3b | 3794 | expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP; |
1da177e4 | 3795 | |
82cd3d11 MC |
3796 | flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
3797 | if (flowctrl & ADVERTISE_1000XPAUSE) | |
3798 | expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP; | |
3799 | if (flowctrl & ADVERTISE_1000XPSE_ASYM) | |
3800 | expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE; | |
1da177e4 LT |
3801 | |
3802 | if (sg_dig_ctrl != expected_sg_dig_ctrl) { | |
3d3ebe74 MC |
3803 | if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) && |
3804 | tp->serdes_counter && | |
3805 | ((mac_status & (MAC_STATUS_PCS_SYNCED | | |
3806 | MAC_STATUS_RCVD_CFG)) == | |
3807 | MAC_STATUS_PCS_SYNCED)) { | |
3808 | tp->serdes_counter--; | |
3809 | current_link_up = 1; | |
3810 | goto out; | |
3811 | } | |
3812 | restart_autoneg: | |
1da177e4 LT |
3813 | if (workaround) |
3814 | tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000); | |
c98f6e3b | 3815 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET); |
1da177e4 LT |
3816 | udelay(5); |
3817 | tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl); | |
3818 | ||
3d3ebe74 MC |
3819 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; |
3820 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
1da177e4 LT |
3821 | } else if (mac_status & (MAC_STATUS_PCS_SYNCED | |
3822 | MAC_STATUS_SIGNAL_DET)) { | |
3d3ebe74 | 3823 | sg_dig_status = tr32(SG_DIG_STATUS); |
1da177e4 LT |
3824 | mac_status = tr32(MAC_STATUS); |
3825 | ||
c98f6e3b | 3826 | if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) && |
1da177e4 | 3827 | (mac_status & MAC_STATUS_PCS_SYNCED)) { |
82cd3d11 MC |
3828 | u32 local_adv = 0, remote_adv = 0; |
3829 | ||
3830 | if (sg_dig_ctrl & SG_DIG_PAUSE_CAP) | |
3831 | local_adv |= ADVERTISE_1000XPAUSE; | |
3832 | if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE) | |
3833 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
1da177e4 | 3834 | |
c98f6e3b | 3835 | if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE) |
82cd3d11 | 3836 | remote_adv |= LPA_1000XPAUSE; |
c98f6e3b | 3837 | if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE) |
82cd3d11 | 3838 | remote_adv |= LPA_1000XPAUSE_ASYM; |
1da177e4 LT |
3839 | |
3840 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3841 | current_link_up = 1; | |
3d3ebe74 MC |
3842 | tp->serdes_counter = 0; |
3843 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
c98f6e3b | 3844 | } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) { |
3d3ebe74 MC |
3845 | if (tp->serdes_counter) |
3846 | tp->serdes_counter--; | |
1da177e4 LT |
3847 | else { |
3848 | if (workaround) { | |
3849 | u32 val = serdes_cfg; | |
3850 | ||
3851 | if (port_a) | |
3852 | val |= 0xc010000; | |
3853 | else | |
3854 | val |= 0x4010000; | |
3855 | ||
3856 | tw32_f(MAC_SERDES_CFG, val); | |
3857 | } | |
3858 | ||
c98f6e3b | 3859 | tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP); |
1da177e4 LT |
3860 | udelay(40); |
3861 | ||
3862 | /* Link parallel detection - link is up */ | |
3863 | /* only if we have PCS_SYNC and not */ | |
3864 | /* receiving config code words */ | |
3865 | mac_status = tr32(MAC_STATUS); | |
3866 | if ((mac_status & MAC_STATUS_PCS_SYNCED) && | |
3867 | !(mac_status & MAC_STATUS_RCVD_CFG)) { | |
3868 | tg3_setup_flow_control(tp, 0, 0); | |
3869 | current_link_up = 1; | |
3d3ebe74 MC |
3870 | tp->tg3_flags2 |= |
3871 | TG3_FLG2_PARALLEL_DETECT; | |
3872 | tp->serdes_counter = | |
3873 | SERDES_PARALLEL_DET_TIMEOUT; | |
3874 | } else | |
3875 | goto restart_autoneg; | |
1da177e4 LT |
3876 | } |
3877 | } | |
3d3ebe74 MC |
3878 | } else { |
3879 | tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; | |
3880 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
1da177e4 LT |
3881 | } |
3882 | ||
3883 | out: | |
3884 | return current_link_up; | |
3885 | } | |
3886 | ||
3887 | static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |
3888 | { | |
3889 | int current_link_up = 0; | |
3890 | ||
5cf64b8a | 3891 | if (!(mac_status & MAC_STATUS_PCS_SYNCED)) |
1da177e4 | 3892 | goto out; |
1da177e4 LT |
3893 | |
3894 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
5be73b47 | 3895 | u32 txflags, rxflags; |
1da177e4 | 3896 | int i; |
6aa20a22 | 3897 | |
5be73b47 MC |
3898 | if (fiber_autoneg(tp, &txflags, &rxflags)) { |
3899 | u32 local_adv = 0, remote_adv = 0; | |
1da177e4 | 3900 | |
5be73b47 MC |
3901 | if (txflags & ANEG_CFG_PS1) |
3902 | local_adv |= ADVERTISE_1000XPAUSE; | |
3903 | if (txflags & ANEG_CFG_PS2) | |
3904 | local_adv |= ADVERTISE_1000XPSE_ASYM; | |
3905 | ||
3906 | if (rxflags & MR_LP_ADV_SYM_PAUSE) | |
3907 | remote_adv |= LPA_1000XPAUSE; | |
3908 | if (rxflags & MR_LP_ADV_ASYM_PAUSE) | |
3909 | remote_adv |= LPA_1000XPAUSE_ASYM; | |
1da177e4 LT |
3910 | |
3911 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
3912 | ||
1da177e4 LT |
3913 | current_link_up = 1; |
3914 | } | |
3915 | for (i = 0; i < 30; i++) { | |
3916 | udelay(20); | |
3917 | tw32_f(MAC_STATUS, | |
3918 | (MAC_STATUS_SYNC_CHANGED | | |
3919 | MAC_STATUS_CFG_CHANGED)); | |
3920 | udelay(40); | |
3921 | if ((tr32(MAC_STATUS) & | |
3922 | (MAC_STATUS_SYNC_CHANGED | | |
3923 | MAC_STATUS_CFG_CHANGED)) == 0) | |
3924 | break; | |
3925 | } | |
3926 | ||
3927 | mac_status = tr32(MAC_STATUS); | |
3928 | if (current_link_up == 0 && | |
3929 | (mac_status & MAC_STATUS_PCS_SYNCED) && | |
3930 | !(mac_status & MAC_STATUS_RCVD_CFG)) | |
3931 | current_link_up = 1; | |
3932 | } else { | |
5be73b47 MC |
3933 | tg3_setup_flow_control(tp, 0, 0); |
3934 | ||
1da177e4 LT |
3935 | /* Forcing 1000FD link up. */ |
3936 | current_link_up = 1; | |
1da177e4 LT |
3937 | |
3938 | tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); | |
3939 | udelay(40); | |
e8f3f6ca MC |
3940 | |
3941 | tw32_f(MAC_MODE, tp->mac_mode); | |
3942 | udelay(40); | |
1da177e4 LT |
3943 | } |
3944 | ||
3945 | out: | |
3946 | return current_link_up; | |
3947 | } | |
3948 | ||
3949 | static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset) | |
3950 | { | |
3951 | u32 orig_pause_cfg; | |
3952 | u16 orig_active_speed; | |
3953 | u8 orig_active_duplex; | |
3954 | u32 mac_status; | |
3955 | int current_link_up; | |
3956 | int i; | |
3957 | ||
8d018621 | 3958 | orig_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
3959 | orig_active_speed = tp->link_config.active_speed; |
3960 | orig_active_duplex = tp->link_config.active_duplex; | |
3961 | ||
3962 | if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) && | |
3963 | netif_carrier_ok(tp->dev) && | |
3964 | (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) { | |
3965 | mac_status = tr32(MAC_STATUS); | |
3966 | mac_status &= (MAC_STATUS_PCS_SYNCED | | |
3967 | MAC_STATUS_SIGNAL_DET | | |
3968 | MAC_STATUS_CFG_CHANGED | | |
3969 | MAC_STATUS_RCVD_CFG); | |
3970 | if (mac_status == (MAC_STATUS_PCS_SYNCED | | |
3971 | MAC_STATUS_SIGNAL_DET)) { | |
3972 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
3973 | MAC_STATUS_CFG_CHANGED)); | |
3974 | return 0; | |
3975 | } | |
3976 | } | |
3977 | ||
3978 | tw32_f(MAC_TX_AUTO_NEG, 0); | |
3979 | ||
3980 | tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); | |
3981 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | |
3982 | tw32_f(MAC_MODE, tp->mac_mode); | |
3983 | udelay(40); | |
3984 | ||
79eb6904 | 3985 | if (tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
3986 | tg3_init_bcm8002(tp); |
3987 | ||
3988 | /* Enable link change event even when serdes polling. */ | |
3989 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3990 | udelay(40); | |
3991 | ||
3992 | current_link_up = 0; | |
3993 | mac_status = tr32(MAC_STATUS); | |
3994 | ||
3995 | if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) | |
3996 | current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); | |
3997 | else | |
3998 | current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); | |
3999 | ||
898a56f8 | 4000 | tp->napi[0].hw_status->status = |
1da177e4 | 4001 | (SD_STATUS_UPDATED | |
898a56f8 | 4002 | (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); |
1da177e4 LT |
4003 | |
4004 | for (i = 0; i < 100; i++) { | |
4005 | tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED | | |
4006 | MAC_STATUS_CFG_CHANGED)); | |
4007 | udelay(5); | |
4008 | if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED | | |
3d3ebe74 MC |
4009 | MAC_STATUS_CFG_CHANGED | |
4010 | MAC_STATUS_LNKSTATE_CHANGED)) == 0) | |
1da177e4 LT |
4011 | break; |
4012 | } | |
4013 | ||
4014 | mac_status = tr32(MAC_STATUS); | |
4015 | if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) { | |
4016 | current_link_up = 0; | |
3d3ebe74 MC |
4017 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
4018 | tp->serdes_counter == 0) { | |
1da177e4 LT |
4019 | tw32_f(MAC_MODE, (tp->mac_mode | |
4020 | MAC_MODE_SEND_CONFIGS)); | |
4021 | udelay(1); | |
4022 | tw32_f(MAC_MODE, tp->mac_mode); | |
4023 | } | |
4024 | } | |
4025 | ||
4026 | if (current_link_up == 1) { | |
4027 | tp->link_config.active_speed = SPEED_1000; | |
4028 | tp->link_config.active_duplex = DUPLEX_FULL; | |
4029 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4030 | LED_CTRL_LNKLED_OVERRIDE | | |
4031 | LED_CTRL_1000MBPS_ON)); | |
4032 | } else { | |
4033 | tp->link_config.active_speed = SPEED_INVALID; | |
4034 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
4035 | tw32(MAC_LED_CTRL, (tp->led_ctrl | | |
4036 | LED_CTRL_LNKLED_OVERRIDE | | |
4037 | LED_CTRL_TRAFFIC_OVERRIDE)); | |
4038 | } | |
4039 | ||
4040 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4041 | if (current_link_up) | |
4042 | netif_carrier_on(tp->dev); | |
4043 | else | |
4044 | netif_carrier_off(tp->dev); | |
4045 | tg3_link_report(tp); | |
4046 | } else { | |
8d018621 | 4047 | u32 now_pause_cfg = tp->link_config.active_flowctrl; |
1da177e4 LT |
4048 | if (orig_pause_cfg != now_pause_cfg || |
4049 | orig_active_speed != tp->link_config.active_speed || | |
4050 | orig_active_duplex != tp->link_config.active_duplex) | |
4051 | tg3_link_report(tp); | |
4052 | } | |
4053 | ||
4054 | return 0; | |
4055 | } | |
4056 | ||
747e8f8b MC |
4057 | static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset) |
4058 | { | |
4059 | int current_link_up, err = 0; | |
4060 | u32 bmsr, bmcr; | |
4061 | u16 current_speed; | |
4062 | u8 current_duplex; | |
ef167e27 | 4063 | u32 local_adv, remote_adv; |
747e8f8b MC |
4064 | |
4065 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
4066 | tw32_f(MAC_MODE, tp->mac_mode); | |
4067 | udelay(40); | |
4068 | ||
4069 | tw32(MAC_EVENT, 0); | |
4070 | ||
4071 | tw32_f(MAC_STATUS, | |
4072 | (MAC_STATUS_SYNC_CHANGED | | |
4073 | MAC_STATUS_CFG_CHANGED | | |
4074 | MAC_STATUS_MI_COMPLETION | | |
4075 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4076 | udelay(40); | |
4077 | ||
4078 | if (force_reset) | |
4079 | tg3_phy_reset(tp); | |
4080 | ||
4081 | current_link_up = 0; | |
4082 | current_speed = SPEED_INVALID; | |
4083 | current_duplex = DUPLEX_INVALID; | |
4084 | ||
4085 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4086 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4087 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
4088 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4089 | bmsr |= BMSR_LSTATUS; | |
4090 | else | |
4091 | bmsr &= ~BMSR_LSTATUS; | |
4092 | } | |
747e8f8b MC |
4093 | |
4094 | err |= tg3_readphy(tp, MII_BMCR, &bmcr); | |
4095 | ||
4096 | if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && | |
2bd3ed04 | 4097 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { |
747e8f8b MC |
4098 | /* do nothing, just check for link up at the end */ |
4099 | } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { | |
4100 | u32 adv, new_adv; | |
4101 | ||
4102 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4103 | new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | | |
4104 | ADVERTISE_1000XPAUSE | | |
4105 | ADVERTISE_1000XPSE_ASYM | | |
4106 | ADVERTISE_SLCT); | |
4107 | ||
ba4d07a8 | 4108 | new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); |
747e8f8b MC |
4109 | |
4110 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) | |
4111 | new_adv |= ADVERTISE_1000XHALF; | |
4112 | if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) | |
4113 | new_adv |= ADVERTISE_1000XFULL; | |
4114 | ||
4115 | if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) { | |
4116 | tg3_writephy(tp, MII_ADVERTISE, new_adv); | |
4117 | bmcr |= BMCR_ANENABLE | BMCR_ANRESTART; | |
4118 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4119 | ||
4120 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
3d3ebe74 | 4121 | tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; |
747e8f8b MC |
4122 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; |
4123 | ||
4124 | return err; | |
4125 | } | |
4126 | } else { | |
4127 | u32 new_bmcr; | |
4128 | ||
4129 | bmcr &= ~BMCR_SPEED1000; | |
4130 | new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX); | |
4131 | ||
4132 | if (tp->link_config.duplex == DUPLEX_FULL) | |
4133 | new_bmcr |= BMCR_FULLDPLX; | |
4134 | ||
4135 | if (new_bmcr != bmcr) { | |
4136 | /* BMCR_SPEED1000 is a reserved bit that needs | |
4137 | * to be set on write. | |
4138 | */ | |
4139 | new_bmcr |= BMCR_SPEED1000; | |
4140 | ||
4141 | /* Force a linkdown */ | |
4142 | if (netif_carrier_ok(tp->dev)) { | |
4143 | u32 adv; | |
4144 | ||
4145 | err |= tg3_readphy(tp, MII_ADVERTISE, &adv); | |
4146 | adv &= ~(ADVERTISE_1000XFULL | | |
4147 | ADVERTISE_1000XHALF | | |
4148 | ADVERTISE_SLCT); | |
4149 | tg3_writephy(tp, MII_ADVERTISE, adv); | |
4150 | tg3_writephy(tp, MII_BMCR, bmcr | | |
4151 | BMCR_ANRESTART | | |
4152 | BMCR_ANENABLE); | |
4153 | udelay(10); | |
4154 | netif_carrier_off(tp->dev); | |
4155 | } | |
4156 | tg3_writephy(tp, MII_BMCR, new_bmcr); | |
4157 | bmcr = new_bmcr; | |
4158 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
4159 | err |= tg3_readphy(tp, MII_BMSR, &bmsr); | |
d4d2c558 MC |
4160 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == |
4161 | ASIC_REV_5714) { | |
4162 | if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP) | |
4163 | bmsr |= BMSR_LSTATUS; | |
4164 | else | |
4165 | bmsr &= ~BMSR_LSTATUS; | |
4166 | } | |
747e8f8b MC |
4167 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; |
4168 | } | |
4169 | } | |
4170 | ||
4171 | if (bmsr & BMSR_LSTATUS) { | |
4172 | current_speed = SPEED_1000; | |
4173 | current_link_up = 1; | |
4174 | if (bmcr & BMCR_FULLDPLX) | |
4175 | current_duplex = DUPLEX_FULL; | |
4176 | else | |
4177 | current_duplex = DUPLEX_HALF; | |
4178 | ||
ef167e27 MC |
4179 | local_adv = 0; |
4180 | remote_adv = 0; | |
4181 | ||
747e8f8b | 4182 | if (bmcr & BMCR_ANENABLE) { |
ef167e27 | 4183 | u32 common; |
747e8f8b MC |
4184 | |
4185 | err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); | |
4186 | err |= tg3_readphy(tp, MII_LPA, &remote_adv); | |
4187 | common = local_adv & remote_adv; | |
4188 | if (common & (ADVERTISE_1000XHALF | | |
4189 | ADVERTISE_1000XFULL)) { | |
4190 | if (common & ADVERTISE_1000XFULL) | |
4191 | current_duplex = DUPLEX_FULL; | |
4192 | else | |
4193 | current_duplex = DUPLEX_HALF; | |
859a5887 | 4194 | } else { |
747e8f8b | 4195 | current_link_up = 0; |
859a5887 | 4196 | } |
747e8f8b MC |
4197 | } |
4198 | } | |
4199 | ||
ef167e27 MC |
4200 | if (current_link_up == 1 && current_duplex == DUPLEX_FULL) |
4201 | tg3_setup_flow_control(tp, local_adv, remote_adv); | |
4202 | ||
747e8f8b MC |
4203 | tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; |
4204 | if (tp->link_config.active_duplex == DUPLEX_HALF) | |
4205 | tp->mac_mode |= MAC_MODE_HALF_DUPLEX; | |
4206 | ||
4207 | tw32_f(MAC_MODE, tp->mac_mode); | |
4208 | udelay(40); | |
4209 | ||
4210 | tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED); | |
4211 | ||
4212 | tp->link_config.active_speed = current_speed; | |
4213 | tp->link_config.active_duplex = current_duplex; | |
4214 | ||
4215 | if (current_link_up != netif_carrier_ok(tp->dev)) { | |
4216 | if (current_link_up) | |
4217 | netif_carrier_on(tp->dev); | |
4218 | else { | |
4219 | netif_carrier_off(tp->dev); | |
4220 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4221 | } | |
4222 | tg3_link_report(tp); | |
4223 | } | |
4224 | return err; | |
4225 | } | |
4226 | ||
4227 | static void tg3_serdes_parallel_detect(struct tg3 *tp) | |
4228 | { | |
3d3ebe74 | 4229 | if (tp->serdes_counter) { |
747e8f8b | 4230 | /* Give autoneg time to complete. */ |
3d3ebe74 | 4231 | tp->serdes_counter--; |
747e8f8b MC |
4232 | return; |
4233 | } | |
c6cdf436 | 4234 | |
747e8f8b MC |
4235 | if (!netif_carrier_ok(tp->dev) && |
4236 | (tp->link_config.autoneg == AUTONEG_ENABLE)) { | |
4237 | u32 bmcr; | |
4238 | ||
4239 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4240 | if (bmcr & BMCR_ANENABLE) { | |
4241 | u32 phy1, phy2; | |
4242 | ||
4243 | /* Select shadow register 0x1f */ | |
4244 | tg3_writephy(tp, 0x1c, 0x7c00); | |
4245 | tg3_readphy(tp, 0x1c, &phy1); | |
4246 | ||
4247 | /* Select expansion interrupt status register */ | |
4248 | tg3_writephy(tp, 0x17, 0x0f01); | |
4249 | tg3_readphy(tp, 0x15, &phy2); | |
4250 | tg3_readphy(tp, 0x15, &phy2); | |
4251 | ||
4252 | if ((phy1 & 0x10) && !(phy2 & 0x20)) { | |
4253 | /* We have signal detect and not receiving | |
4254 | * config code words, link is up by parallel | |
4255 | * detection. | |
4256 | */ | |
4257 | ||
4258 | bmcr &= ~BMCR_ANENABLE; | |
4259 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | |
4260 | tg3_writephy(tp, MII_BMCR, bmcr); | |
4261 | tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT; | |
4262 | } | |
4263 | } | |
859a5887 MC |
4264 | } else if (netif_carrier_ok(tp->dev) && |
4265 | (tp->link_config.autoneg == AUTONEG_ENABLE) && | |
4266 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) { | |
747e8f8b MC |
4267 | u32 phy2; |
4268 | ||
4269 | /* Select expansion interrupt status register */ | |
4270 | tg3_writephy(tp, 0x17, 0x0f01); | |
4271 | tg3_readphy(tp, 0x15, &phy2); | |
4272 | if (phy2 & 0x20) { | |
4273 | u32 bmcr; | |
4274 | ||
4275 | /* Config code words received, turn on autoneg. */ | |
4276 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
4277 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); | |
4278 | ||
4279 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
4280 | ||
4281 | } | |
4282 | } | |
4283 | } | |
4284 | ||
1da177e4 LT |
4285 | static int tg3_setup_phy(struct tg3 *tp, int force_reset) |
4286 | { | |
4287 | int err; | |
4288 | ||
859a5887 | 4289 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) |
1da177e4 | 4290 | err = tg3_setup_fiber_phy(tp, force_reset); |
859a5887 | 4291 | else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
747e8f8b | 4292 | err = tg3_setup_fiber_mii_phy(tp, force_reset); |
859a5887 | 4293 | else |
1da177e4 | 4294 | err = tg3_setup_copper_phy(tp, force_reset); |
1da177e4 | 4295 | |
bcb37f6c | 4296 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
aa6c91fe MC |
4297 | u32 val, scale; |
4298 | ||
4299 | val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK; | |
4300 | if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5) | |
4301 | scale = 65; | |
4302 | else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25) | |
4303 | scale = 6; | |
4304 | else | |
4305 | scale = 12; | |
4306 | ||
4307 | val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK; | |
4308 | val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
4309 | tw32(GRC_MISC_CFG, val); | |
4310 | } | |
4311 | ||
1da177e4 LT |
4312 | if (tp->link_config.active_speed == SPEED_1000 && |
4313 | tp->link_config.active_duplex == DUPLEX_HALF) | |
4314 | tw32(MAC_TX_LENGTHS, | |
4315 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4316 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4317 | (0xff << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4318 | else | |
4319 | tw32(MAC_TX_LENGTHS, | |
4320 | ((2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
4321 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
4322 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT))); | |
4323 | ||
4324 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
4325 | if (netif_carrier_ok(tp->dev)) { | |
4326 | tw32(HOSTCC_STAT_COAL_TICKS, | |
15f9850d | 4327 | tp->coal.stats_block_coalesce_usecs); |
1da177e4 LT |
4328 | } else { |
4329 | tw32(HOSTCC_STAT_COAL_TICKS, 0); | |
4330 | } | |
4331 | } | |
4332 | ||
8ed5d97e MC |
4333 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) { |
4334 | u32 val = tr32(PCIE_PWR_MGMT_THRESH); | |
4335 | if (!netif_carrier_ok(tp->dev)) | |
4336 | val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) | | |
4337 | tp->pwrmgmt_thresh; | |
4338 | else | |
4339 | val |= PCIE_PWR_MGMT_L1_THRESH_MSK; | |
4340 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
4341 | } | |
4342 | ||
1da177e4 LT |
4343 | return err; |
4344 | } | |
4345 | ||
df3e6548 MC |
4346 | /* This is called whenever we suspect that the system chipset is re- |
4347 | * ordering the sequence of MMIO to the tx send mailbox. The symptom | |
4348 | * is bogus tx completions. We try to recover by setting the | |
4349 | * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later | |
4350 | * in the workqueue. | |
4351 | */ | |
4352 | static void tg3_tx_recover(struct tg3 *tp) | |
4353 | { | |
4354 | BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) || | |
4355 | tp->write32_tx_mbox == tg3_write_indirect_mbox); | |
4356 | ||
5129c3a3 MC |
4357 | netdev_warn(tp->dev, |
4358 | "The system may be re-ordering memory-mapped I/O " | |
4359 | "cycles to the network device, attempting to recover. " | |
4360 | "Please report the problem to the driver maintainer " | |
4361 | "and include system chipset information.\n"); | |
df3e6548 MC |
4362 | |
4363 | spin_lock(&tp->lock); | |
df3e6548 | 4364 | tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING; |
df3e6548 MC |
4365 | spin_unlock(&tp->lock); |
4366 | } | |
4367 | ||
f3f3f27e | 4368 | static inline u32 tg3_tx_avail(struct tg3_napi *tnapi) |
1b2a7205 MC |
4369 | { |
4370 | smp_mb(); | |
f3f3f27e MC |
4371 | return tnapi->tx_pending - |
4372 | ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); | |
1b2a7205 MC |
4373 | } |
4374 | ||
1da177e4 LT |
4375 | /* Tigon3 never reports partial packet sends. So we do not |
4376 | * need special logic to handle SKBs that have not had all | |
4377 | * of their frags sent yet, like SunGEM does. | |
4378 | */ | |
17375d25 | 4379 | static void tg3_tx(struct tg3_napi *tnapi) |
1da177e4 | 4380 | { |
17375d25 | 4381 | struct tg3 *tp = tnapi->tp; |
898a56f8 | 4382 | u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; |
f3f3f27e | 4383 | u32 sw_idx = tnapi->tx_cons; |
fe5f5787 MC |
4384 | struct netdev_queue *txq; |
4385 | int index = tnapi - tp->napi; | |
4386 | ||
19cfaecc | 4387 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 MC |
4388 | index--; |
4389 | ||
4390 | txq = netdev_get_tx_queue(tp->dev, index); | |
1da177e4 LT |
4391 | |
4392 | while (sw_idx != hw_idx) { | |
f4188d8a | 4393 | struct ring_info *ri = &tnapi->tx_buffers[sw_idx]; |
1da177e4 | 4394 | struct sk_buff *skb = ri->skb; |
df3e6548 MC |
4395 | int i, tx_bug = 0; |
4396 | ||
4397 | if (unlikely(skb == NULL)) { | |
4398 | tg3_tx_recover(tp); | |
4399 | return; | |
4400 | } | |
1da177e4 | 4401 | |
f4188d8a AD |
4402 | pci_unmap_single(tp->pdev, |
4403 | pci_unmap_addr(ri, mapping), | |
4404 | skb_headlen(skb), | |
4405 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4406 | |
4407 | ri->skb = NULL; | |
4408 | ||
4409 | sw_idx = NEXT_TX(sw_idx); | |
4410 | ||
4411 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
f3f3f27e | 4412 | ri = &tnapi->tx_buffers[sw_idx]; |
df3e6548 MC |
4413 | if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) |
4414 | tx_bug = 1; | |
f4188d8a AD |
4415 | |
4416 | pci_unmap_page(tp->pdev, | |
4417 | pci_unmap_addr(ri, mapping), | |
4418 | skb_shinfo(skb)->frags[i].size, | |
4419 | PCI_DMA_TODEVICE); | |
1da177e4 LT |
4420 | sw_idx = NEXT_TX(sw_idx); |
4421 | } | |
4422 | ||
f47c11ee | 4423 | dev_kfree_skb(skb); |
df3e6548 MC |
4424 | |
4425 | if (unlikely(tx_bug)) { | |
4426 | tg3_tx_recover(tp); | |
4427 | return; | |
4428 | } | |
1da177e4 LT |
4429 | } |
4430 | ||
f3f3f27e | 4431 | tnapi->tx_cons = sw_idx; |
1da177e4 | 4432 | |
1b2a7205 MC |
4433 | /* Need to make the tx_cons update visible to tg3_start_xmit() |
4434 | * before checking for netif_queue_stopped(). Without the | |
4435 | * memory barrier, there is a small possibility that tg3_start_xmit() | |
4436 | * will miss it and cause the queue to be stopped forever. | |
4437 | */ | |
4438 | smp_mb(); | |
4439 | ||
fe5f5787 | 4440 | if (unlikely(netif_tx_queue_stopped(txq) && |
f3f3f27e | 4441 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) { |
fe5f5787 MC |
4442 | __netif_tx_lock(txq, smp_processor_id()); |
4443 | if (netif_tx_queue_stopped(txq) && | |
f3f3f27e | 4444 | (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))) |
fe5f5787 MC |
4445 | netif_tx_wake_queue(txq); |
4446 | __netif_tx_unlock(txq); | |
51b91468 | 4447 | } |
1da177e4 LT |
4448 | } |
4449 | ||
2b2cdb65 MC |
4450 | static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) |
4451 | { | |
4452 | if (!ri->skb) | |
4453 | return; | |
4454 | ||
4455 | pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping), | |
4456 | map_sz, PCI_DMA_FROMDEVICE); | |
4457 | dev_kfree_skb_any(ri->skb); | |
4458 | ri->skb = NULL; | |
4459 | } | |
4460 | ||
1da177e4 LT |
4461 | /* Returns size of skb allocated or < 0 on error. |
4462 | * | |
4463 | * We only need to fill in the address because the other members | |
4464 | * of the RX descriptor are invariant, see tg3_init_rings. | |
4465 | * | |
4466 | * Note the purposeful assymetry of cpu vs. chip accesses. For | |
4467 | * posting buffers we only dirty the first cache line of the RX | |
4468 | * descriptor (containing the address). Whereas for the RX status | |
4469 | * buffers the cpu only reads the last cacheline of the RX descriptor | |
4470 | * (to fetch the error flags, vlan tag, checksum, and opaque cookie). | |
4471 | */ | |
86b21e59 | 4472 | static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, |
a3896167 | 4473 | u32 opaque_key, u32 dest_idx_unmasked) |
1da177e4 LT |
4474 | { |
4475 | struct tg3_rx_buffer_desc *desc; | |
4476 | struct ring_info *map, *src_map; | |
4477 | struct sk_buff *skb; | |
4478 | dma_addr_t mapping; | |
4479 | int skb_size, dest_idx; | |
4480 | ||
4481 | src_map = NULL; | |
4482 | switch (opaque_key) { | |
4483 | case RXD_OPAQUE_RING_STD: | |
4484 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
21f581a5 MC |
4485 | desc = &tpr->rx_std[dest_idx]; |
4486 | map = &tpr->rx_std_buffers[dest_idx]; | |
287be12e | 4487 | skb_size = tp->rx_pkt_map_sz; |
1da177e4 LT |
4488 | break; |
4489 | ||
4490 | case RXD_OPAQUE_RING_JUMBO: | |
4491 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
79ed5ac7 | 4492 | desc = &tpr->rx_jmb[dest_idx].std; |
21f581a5 | 4493 | map = &tpr->rx_jmb_buffers[dest_idx]; |
287be12e | 4494 | skb_size = TG3_RX_JMB_MAP_SZ; |
1da177e4 LT |
4495 | break; |
4496 | ||
4497 | default: | |
4498 | return -EINVAL; | |
855e1111 | 4499 | } |
1da177e4 LT |
4500 | |
4501 | /* Do not overwrite any of the map or rp information | |
4502 | * until we are sure we can commit to a new buffer. | |
4503 | * | |
4504 | * Callers depend upon this behavior and assume that | |
4505 | * we leave everything unchanged if we fail. | |
4506 | */ | |
287be12e | 4507 | skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset); |
1da177e4 LT |
4508 | if (skb == NULL) |
4509 | return -ENOMEM; | |
4510 | ||
1da177e4 LT |
4511 | skb_reserve(skb, tp->rx_offset); |
4512 | ||
287be12e | 4513 | mapping = pci_map_single(tp->pdev, skb->data, skb_size, |
1da177e4 | 4514 | PCI_DMA_FROMDEVICE); |
a21771dd MC |
4515 | if (pci_dma_mapping_error(tp->pdev, mapping)) { |
4516 | dev_kfree_skb(skb); | |
4517 | return -EIO; | |
4518 | } | |
1da177e4 LT |
4519 | |
4520 | map->skb = skb; | |
4521 | pci_unmap_addr_set(map, mapping, mapping); | |
4522 | ||
1da177e4 LT |
4523 | desc->addr_hi = ((u64)mapping >> 32); |
4524 | desc->addr_lo = ((u64)mapping & 0xffffffff); | |
4525 | ||
4526 | return skb_size; | |
4527 | } | |
4528 | ||
4529 | /* We only need to move over in the address because the other | |
4530 | * members of the RX descriptor are invariant. See notes above | |
4531 | * tg3_alloc_rx_skb for full details. | |
4532 | */ | |
a3896167 MC |
4533 | static void tg3_recycle_rx(struct tg3_napi *tnapi, |
4534 | struct tg3_rx_prodring_set *dpr, | |
4535 | u32 opaque_key, int src_idx, | |
4536 | u32 dest_idx_unmasked) | |
1da177e4 | 4537 | { |
17375d25 | 4538 | struct tg3 *tp = tnapi->tp; |
1da177e4 LT |
4539 | struct tg3_rx_buffer_desc *src_desc, *dest_desc; |
4540 | struct ring_info *src_map, *dest_map; | |
a3896167 | 4541 | struct tg3_rx_prodring_set *spr = &tp->prodring[0]; |
c6cdf436 | 4542 | int dest_idx; |
1da177e4 LT |
4543 | |
4544 | switch (opaque_key) { | |
4545 | case RXD_OPAQUE_RING_STD: | |
4546 | dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE; | |
a3896167 MC |
4547 | dest_desc = &dpr->rx_std[dest_idx]; |
4548 | dest_map = &dpr->rx_std_buffers[dest_idx]; | |
4549 | src_desc = &spr->rx_std[src_idx]; | |
4550 | src_map = &spr->rx_std_buffers[src_idx]; | |
1da177e4 LT |
4551 | break; |
4552 | ||
4553 | case RXD_OPAQUE_RING_JUMBO: | |
4554 | dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE; | |
a3896167 MC |
4555 | dest_desc = &dpr->rx_jmb[dest_idx].std; |
4556 | dest_map = &dpr->rx_jmb_buffers[dest_idx]; | |
4557 | src_desc = &spr->rx_jmb[src_idx].std; | |
4558 | src_map = &spr->rx_jmb_buffers[src_idx]; | |
1da177e4 LT |
4559 | break; |
4560 | ||
4561 | default: | |
4562 | return; | |
855e1111 | 4563 | } |
1da177e4 LT |
4564 | |
4565 | dest_map->skb = src_map->skb; | |
4566 | pci_unmap_addr_set(dest_map, mapping, | |
4567 | pci_unmap_addr(src_map, mapping)); | |
4568 | dest_desc->addr_hi = src_desc->addr_hi; | |
4569 | dest_desc->addr_lo = src_desc->addr_lo; | |
e92967bf MC |
4570 | |
4571 | /* Ensure that the update to the skb happens after the physical | |
4572 | * addresses have been transferred to the new BD location. | |
4573 | */ | |
4574 | smp_wmb(); | |
4575 | ||
1da177e4 LT |
4576 | src_map->skb = NULL; |
4577 | } | |
4578 | ||
1da177e4 LT |
4579 | /* The RX ring scheme is composed of multiple rings which post fresh |
4580 | * buffers to the chip, and one special ring the chip uses to report | |
4581 | * status back to the host. | |
4582 | * | |
4583 | * The special ring reports the status of received packets to the | |
4584 | * host. The chip does not write into the original descriptor the | |
4585 | * RX buffer was obtained from. The chip simply takes the original | |
4586 | * descriptor as provided by the host, updates the status and length | |
4587 | * field, then writes this into the next status ring entry. | |
4588 | * | |
4589 | * Each ring the host uses to post buffers to the chip is described | |
4590 | * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives, | |
4591 | * it is first placed into the on-chip ram. When the packet's length | |
4592 | * is known, it walks down the TG3_BDINFO entries to select the ring. | |
4593 | * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO | |
4594 | * which is within the range of the new packet's length is chosen. | |
4595 | * | |
4596 | * The "separate ring for rx status" scheme may sound queer, but it makes | |
4597 | * sense from a cache coherency perspective. If only the host writes | |
4598 | * to the buffer post rings, and only the chip writes to the rx status | |
4599 | * rings, then cache lines never move beyond shared-modified state. | |
4600 | * If both the host and chip were to write into the same ring, cache line | |
4601 | * eviction could occur since both entities want it in an exclusive state. | |
4602 | */ | |
17375d25 | 4603 | static int tg3_rx(struct tg3_napi *tnapi, int budget) |
1da177e4 | 4604 | { |
17375d25 | 4605 | struct tg3 *tp = tnapi->tp; |
f92905de | 4606 | u32 work_mask, rx_std_posted = 0; |
4361935a | 4607 | u32 std_prod_idx, jmb_prod_idx; |
72334482 | 4608 | u32 sw_idx = tnapi->rx_rcb_ptr; |
483ba50b | 4609 | u16 hw_idx; |
1da177e4 | 4610 | int received; |
b196c7e4 | 4611 | struct tg3_rx_prodring_set *tpr = tnapi->prodring; |
1da177e4 | 4612 | |
8d9d7cfc | 4613 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
1da177e4 LT |
4614 | /* |
4615 | * We need to order the read of hw_idx and the read of | |
4616 | * the opaque cookie. | |
4617 | */ | |
4618 | rmb(); | |
1da177e4 LT |
4619 | work_mask = 0; |
4620 | received = 0; | |
4361935a MC |
4621 | std_prod_idx = tpr->rx_std_prod_idx; |
4622 | jmb_prod_idx = tpr->rx_jmb_prod_idx; | |
1da177e4 | 4623 | while (sw_idx != hw_idx && budget > 0) { |
afc081f8 | 4624 | struct ring_info *ri; |
72334482 | 4625 | struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; |
1da177e4 LT |
4626 | unsigned int len; |
4627 | struct sk_buff *skb; | |
4628 | dma_addr_t dma_addr; | |
4629 | u32 opaque_key, desc_idx, *post_ptr; | |
9dc7a113 MC |
4630 | bool hw_vlan __maybe_unused = false; |
4631 | u16 vtag __maybe_unused = 0; | |
1da177e4 LT |
4632 | |
4633 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; | |
4634 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
4635 | if (opaque_key == RXD_OPAQUE_RING_STD) { | |
b196c7e4 | 4636 | ri = &tp->prodring[0].rx_std_buffers[desc_idx]; |
21f581a5 MC |
4637 | dma_addr = pci_unmap_addr(ri, mapping); |
4638 | skb = ri->skb; | |
4361935a | 4639 | post_ptr = &std_prod_idx; |
f92905de | 4640 | rx_std_posted++; |
1da177e4 | 4641 | } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { |
b196c7e4 | 4642 | ri = &tp->prodring[0].rx_jmb_buffers[desc_idx]; |
21f581a5 MC |
4643 | dma_addr = pci_unmap_addr(ri, mapping); |
4644 | skb = ri->skb; | |
4361935a | 4645 | post_ptr = &jmb_prod_idx; |
21f581a5 | 4646 | } else |
1da177e4 | 4647 | goto next_pkt_nopost; |
1da177e4 LT |
4648 | |
4649 | work_mask |= opaque_key; | |
4650 | ||
4651 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
4652 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) { | |
4653 | drop_it: | |
a3896167 | 4654 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4655 | desc_idx, *post_ptr); |
4656 | drop_it_no_recycle: | |
4657 | /* Other statistics kept track of by card. */ | |
4658 | tp->net_stats.rx_dropped++; | |
4659 | goto next_pkt; | |
4660 | } | |
4661 | ||
ad829268 MC |
4662 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - |
4663 | ETH_FCS_LEN; | |
1da177e4 | 4664 | |
d2757fc4 | 4665 | if (len > TG3_RX_COPY_THRESH(tp)) { |
1da177e4 LT |
4666 | int skb_size; |
4667 | ||
86b21e59 | 4668 | skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key, |
afc081f8 | 4669 | *post_ptr); |
1da177e4 LT |
4670 | if (skb_size < 0) |
4671 | goto drop_it; | |
4672 | ||
287be12e | 4673 | pci_unmap_single(tp->pdev, dma_addr, skb_size, |
1da177e4 LT |
4674 | PCI_DMA_FROMDEVICE); |
4675 | ||
61e800cf MC |
4676 | /* Ensure that the update to the skb happens |
4677 | * after the usage of the old DMA mapping. | |
4678 | */ | |
4679 | smp_wmb(); | |
4680 | ||
4681 | ri->skb = NULL; | |
4682 | ||
1da177e4 LT |
4683 | skb_put(skb, len); |
4684 | } else { | |
4685 | struct sk_buff *copy_skb; | |
4686 | ||
a3896167 | 4687 | tg3_recycle_rx(tnapi, tpr, opaque_key, |
1da177e4 LT |
4688 | desc_idx, *post_ptr); |
4689 | ||
9dc7a113 MC |
4690 | copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN + |
4691 | TG3_RAW_IP_ALIGN); | |
1da177e4 LT |
4692 | if (copy_skb == NULL) |
4693 | goto drop_it_no_recycle; | |
4694 | ||
9dc7a113 | 4695 | skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN); |
1da177e4 LT |
4696 | skb_put(copy_skb, len); |
4697 | pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); | |
d626f62b | 4698 | skb_copy_from_linear_data(skb, copy_skb->data, len); |
1da177e4 LT |
4699 | pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); |
4700 | ||
4701 | /* We'll reuse the original ring buffer. */ | |
4702 | skb = copy_skb; | |
4703 | } | |
4704 | ||
4705 | if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) && | |
4706 | (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && | |
4707 | (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) | |
4708 | >> RXD_TCPCSUM_SHIFT) == 0xffff)) | |
4709 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
4710 | else | |
4711 | skb->ip_summed = CHECKSUM_NONE; | |
4712 | ||
4713 | skb->protocol = eth_type_trans(skb, tp->dev); | |
f7b493e0 MC |
4714 | |
4715 | if (len > (tp->dev->mtu + ETH_HLEN) && | |
4716 | skb->protocol != htons(ETH_P_8021Q)) { | |
4717 | dev_kfree_skb(skb); | |
4718 | goto next_pkt; | |
4719 | } | |
4720 | ||
9dc7a113 MC |
4721 | if (desc->type_flags & RXD_FLAG_VLAN && |
4722 | !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) { | |
4723 | vtag = desc->err_vlan & RXD_VLAN_MASK; | |
1da177e4 | 4724 | #if TG3_VLAN_TAG_USED |
9dc7a113 MC |
4725 | if (tp->vlgrp) |
4726 | hw_vlan = true; | |
4727 | else | |
4728 | #endif | |
4729 | { | |
4730 | struct vlan_ethhdr *ve = (struct vlan_ethhdr *) | |
4731 | __skb_push(skb, VLAN_HLEN); | |
4732 | ||
4733 | memmove(ve, skb->data + VLAN_HLEN, | |
4734 | ETH_ALEN * 2); | |
4735 | ve->h_vlan_proto = htons(ETH_P_8021Q); | |
4736 | ve->h_vlan_TCI = htons(vtag); | |
4737 | } | |
4738 | } | |
4739 | ||
4740 | #if TG3_VLAN_TAG_USED | |
4741 | if (hw_vlan) | |
4742 | vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb); | |
4743 | else | |
1da177e4 | 4744 | #endif |
17375d25 | 4745 | napi_gro_receive(&tnapi->napi, skb); |
1da177e4 | 4746 | |
1da177e4 LT |
4747 | received++; |
4748 | budget--; | |
4749 | ||
4750 | next_pkt: | |
4751 | (*post_ptr)++; | |
f92905de MC |
4752 | |
4753 | if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { | |
86cfe4ff MC |
4754 | tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE; |
4755 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
4756 | tpr->rx_std_prod_idx); | |
f92905de MC |
4757 | work_mask &= ~RXD_OPAQUE_RING_STD; |
4758 | rx_std_posted = 0; | |
4759 | } | |
1da177e4 | 4760 | next_pkt_nopost: |
483ba50b | 4761 | sw_idx++; |
6b31a515 | 4762 | sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1); |
52f6d697 MC |
4763 | |
4764 | /* Refresh hw_idx to see if there is new work */ | |
4765 | if (sw_idx == hw_idx) { | |
8d9d7cfc | 4766 | hw_idx = *(tnapi->rx_rcb_prod_idx); |
52f6d697 MC |
4767 | rmb(); |
4768 | } | |
1da177e4 LT |
4769 | } |
4770 | ||
4771 | /* ACK the status ring. */ | |
72334482 MC |
4772 | tnapi->rx_rcb_ptr = sw_idx; |
4773 | tw32_rx_mbox(tnapi->consmbox, sw_idx); | |
1da177e4 LT |
4774 | |
4775 | /* Refill RX ring(s). */ | |
e4af1af9 | 4776 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) { |
b196c7e4 MC |
4777 | if (work_mask & RXD_OPAQUE_RING_STD) { |
4778 | tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE; | |
4779 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
4780 | tpr->rx_std_prod_idx); | |
4781 | } | |
4782 | if (work_mask & RXD_OPAQUE_RING_JUMBO) { | |
4783 | tpr->rx_jmb_prod_idx = jmb_prod_idx % | |
4784 | TG3_RX_JUMBO_RING_SIZE; | |
4785 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
4786 | tpr->rx_jmb_prod_idx); | |
4787 | } | |
4788 | mmiowb(); | |
4789 | } else if (work_mask) { | |
4790 | /* rx_std_buffers[] and rx_jmb_buffers[] entries must be | |
4791 | * updated before the producer indices can be updated. | |
4792 | */ | |
4793 | smp_wmb(); | |
4794 | ||
4361935a | 4795 | tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE; |
4361935a | 4796 | tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE; |
b196c7e4 | 4797 | |
e4af1af9 MC |
4798 | if (tnapi != &tp->napi[1]) |
4799 | napi_schedule(&tp->napi[1].napi); | |
1da177e4 | 4800 | } |
1da177e4 LT |
4801 | |
4802 | return received; | |
4803 | } | |
4804 | ||
35f2d7d0 | 4805 | static void tg3_poll_link(struct tg3 *tp) |
1da177e4 | 4806 | { |
1da177e4 LT |
4807 | /* handle link change and other phy events */ |
4808 | if (!(tp->tg3_flags & | |
4809 | (TG3_FLAG_USE_LINKCHG_REG | | |
4810 | TG3_FLAG_POLL_SERDES))) { | |
35f2d7d0 MC |
4811 | struct tg3_hw_status *sblk = tp->napi[0].hw_status; |
4812 | ||
1da177e4 LT |
4813 | if (sblk->status & SD_STATUS_LINK_CHG) { |
4814 | sblk->status = SD_STATUS_UPDATED | | |
35f2d7d0 | 4815 | (sblk->status & ~SD_STATUS_LINK_CHG); |
f47c11ee | 4816 | spin_lock(&tp->lock); |
dd477003 MC |
4817 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
4818 | tw32_f(MAC_STATUS, | |
4819 | (MAC_STATUS_SYNC_CHANGED | | |
4820 | MAC_STATUS_CFG_CHANGED | | |
4821 | MAC_STATUS_MI_COMPLETION | | |
4822 | MAC_STATUS_LNKSTATE_CHANGED)); | |
4823 | udelay(40); | |
4824 | } else | |
4825 | tg3_setup_phy(tp, 0); | |
f47c11ee | 4826 | spin_unlock(&tp->lock); |
1da177e4 LT |
4827 | } |
4828 | } | |
35f2d7d0 MC |
4829 | } |
4830 | ||
f89f38b8 MC |
4831 | static int tg3_rx_prodring_xfer(struct tg3 *tp, |
4832 | struct tg3_rx_prodring_set *dpr, | |
4833 | struct tg3_rx_prodring_set *spr) | |
b196c7e4 MC |
4834 | { |
4835 | u32 si, di, cpycnt, src_prod_idx; | |
f89f38b8 | 4836 | int i, err = 0; |
b196c7e4 MC |
4837 | |
4838 | while (1) { | |
4839 | src_prod_idx = spr->rx_std_prod_idx; | |
4840 | ||
4841 | /* Make sure updates to the rx_std_buffers[] entries and the | |
4842 | * standard producer index are seen in the correct order. | |
4843 | */ | |
4844 | smp_rmb(); | |
4845 | ||
4846 | if (spr->rx_std_cons_idx == src_prod_idx) | |
4847 | break; | |
4848 | ||
4849 | if (spr->rx_std_cons_idx < src_prod_idx) | |
4850 | cpycnt = src_prod_idx - spr->rx_std_cons_idx; | |
4851 | else | |
4852 | cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx; | |
4853 | ||
4854 | cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx); | |
4855 | ||
4856 | si = spr->rx_std_cons_idx; | |
4857 | di = dpr->rx_std_prod_idx; | |
4858 | ||
e92967bf MC |
4859 | for (i = di; i < di + cpycnt; i++) { |
4860 | if (dpr->rx_std_buffers[i].skb) { | |
4861 | cpycnt = i - di; | |
f89f38b8 | 4862 | err = -ENOSPC; |
e92967bf MC |
4863 | break; |
4864 | } | |
4865 | } | |
4866 | ||
4867 | if (!cpycnt) | |
4868 | break; | |
4869 | ||
4870 | /* Ensure that updates to the rx_std_buffers ring and the | |
4871 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
4872 | * ordered correctly WRT the skb check above. | |
4873 | */ | |
4874 | smp_rmb(); | |
4875 | ||
b196c7e4 MC |
4876 | memcpy(&dpr->rx_std_buffers[di], |
4877 | &spr->rx_std_buffers[si], | |
4878 | cpycnt * sizeof(struct ring_info)); | |
4879 | ||
4880 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
4881 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
4882 | sbd = &spr->rx_std[si]; | |
4883 | dbd = &dpr->rx_std[di]; | |
4884 | dbd->addr_hi = sbd->addr_hi; | |
4885 | dbd->addr_lo = sbd->addr_lo; | |
4886 | } | |
4887 | ||
4888 | spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) % | |
4889 | TG3_RX_RING_SIZE; | |
4890 | dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) % | |
4891 | TG3_RX_RING_SIZE; | |
4892 | } | |
4893 | ||
4894 | while (1) { | |
4895 | src_prod_idx = spr->rx_jmb_prod_idx; | |
4896 | ||
4897 | /* Make sure updates to the rx_jmb_buffers[] entries and | |
4898 | * the jumbo producer index are seen in the correct order. | |
4899 | */ | |
4900 | smp_rmb(); | |
4901 | ||
4902 | if (spr->rx_jmb_cons_idx == src_prod_idx) | |
4903 | break; | |
4904 | ||
4905 | if (spr->rx_jmb_cons_idx < src_prod_idx) | |
4906 | cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; | |
4907 | else | |
4908 | cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx; | |
4909 | ||
4910 | cpycnt = min(cpycnt, | |
4911 | TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx); | |
4912 | ||
4913 | si = spr->rx_jmb_cons_idx; | |
4914 | di = dpr->rx_jmb_prod_idx; | |
4915 | ||
e92967bf MC |
4916 | for (i = di; i < di + cpycnt; i++) { |
4917 | if (dpr->rx_jmb_buffers[i].skb) { | |
4918 | cpycnt = i - di; | |
f89f38b8 | 4919 | err = -ENOSPC; |
e92967bf MC |
4920 | break; |
4921 | } | |
4922 | } | |
4923 | ||
4924 | if (!cpycnt) | |
4925 | break; | |
4926 | ||
4927 | /* Ensure that updates to the rx_jmb_buffers ring and the | |
4928 | * shadowed hardware producer ring from tg3_recycle_skb() are | |
4929 | * ordered correctly WRT the skb check above. | |
4930 | */ | |
4931 | smp_rmb(); | |
4932 | ||
b196c7e4 MC |
4933 | memcpy(&dpr->rx_jmb_buffers[di], |
4934 | &spr->rx_jmb_buffers[si], | |
4935 | cpycnt * sizeof(struct ring_info)); | |
4936 | ||
4937 | for (i = 0; i < cpycnt; i++, di++, si++) { | |
4938 | struct tg3_rx_buffer_desc *sbd, *dbd; | |
4939 | sbd = &spr->rx_jmb[si].std; | |
4940 | dbd = &dpr->rx_jmb[di].std; | |
4941 | dbd->addr_hi = sbd->addr_hi; | |
4942 | dbd->addr_lo = sbd->addr_lo; | |
4943 | } | |
4944 | ||
4945 | spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) % | |
4946 | TG3_RX_JUMBO_RING_SIZE; | |
4947 | dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) % | |
4948 | TG3_RX_JUMBO_RING_SIZE; | |
4949 | } | |
f89f38b8 MC |
4950 | |
4951 | return err; | |
b196c7e4 MC |
4952 | } |
4953 | ||
35f2d7d0 MC |
4954 | static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget) |
4955 | { | |
4956 | struct tg3 *tp = tnapi->tp; | |
1da177e4 LT |
4957 | |
4958 | /* run TX completion thread */ | |
f3f3f27e | 4959 | if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { |
17375d25 | 4960 | tg3_tx(tnapi); |
6f535763 | 4961 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) |
4fd7ab59 | 4962 | return work_done; |
1da177e4 LT |
4963 | } |
4964 | ||
1da177e4 LT |
4965 | /* run RX thread, within the bounds set by NAPI. |
4966 | * All RX "locking" is done by ensuring outside | |
bea3348e | 4967 | * code synchronizes with tg3->napi.poll() |
1da177e4 | 4968 | */ |
8d9d7cfc | 4969 | if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) |
17375d25 | 4970 | work_done += tg3_rx(tnapi, budget - work_done); |
1da177e4 | 4971 | |
b196c7e4 | 4972 | if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) { |
e4af1af9 | 4973 | struct tg3_rx_prodring_set *dpr = &tp->prodring[0]; |
f89f38b8 | 4974 | int i, err = 0; |
e4af1af9 MC |
4975 | u32 std_prod_idx = dpr->rx_std_prod_idx; |
4976 | u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; | |
b196c7e4 | 4977 | |
e4af1af9 | 4978 | for (i = 1; i < tp->irq_cnt; i++) |
f89f38b8 MC |
4979 | err |= tg3_rx_prodring_xfer(tp, dpr, |
4980 | tp->napi[i].prodring); | |
b196c7e4 MC |
4981 | |
4982 | wmb(); | |
4983 | ||
e4af1af9 MC |
4984 | if (std_prod_idx != dpr->rx_std_prod_idx) |
4985 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, | |
4986 | dpr->rx_std_prod_idx); | |
b196c7e4 | 4987 | |
e4af1af9 MC |
4988 | if (jmb_prod_idx != dpr->rx_jmb_prod_idx) |
4989 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, | |
4990 | dpr->rx_jmb_prod_idx); | |
b196c7e4 MC |
4991 | |
4992 | mmiowb(); | |
f89f38b8 MC |
4993 | |
4994 | if (err) | |
4995 | tw32_f(HOSTCC_MODE, tp->coal_now); | |
b196c7e4 MC |
4996 | } |
4997 | ||
6f535763 DM |
4998 | return work_done; |
4999 | } | |
5000 | ||
35f2d7d0 MC |
5001 | static int tg3_poll_msix(struct napi_struct *napi, int budget) |
5002 | { | |
5003 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); | |
5004 | struct tg3 *tp = tnapi->tp; | |
5005 | int work_done = 0; | |
5006 | struct tg3_hw_status *sblk = tnapi->hw_status; | |
5007 | ||
5008 | while (1) { | |
5009 | work_done = tg3_poll_work(tnapi, work_done, budget); | |
5010 | ||
5011 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5012 | goto tx_recovery; | |
5013 | ||
5014 | if (unlikely(work_done >= budget)) | |
5015 | break; | |
5016 | ||
c6cdf436 | 5017 | /* tp->last_tag is used in tg3_int_reenable() below |
35f2d7d0 MC |
5018 | * to tell the hw how much work has been processed, |
5019 | * so we must read it before checking for more work. | |
5020 | */ | |
5021 | tnapi->last_tag = sblk->status_tag; | |
5022 | tnapi->last_irq_tag = tnapi->last_tag; | |
5023 | rmb(); | |
5024 | ||
5025 | /* check for RX/TX work to do */ | |
6d40db7b MC |
5026 | if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && |
5027 | *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { | |
35f2d7d0 MC |
5028 | napi_complete(napi); |
5029 | /* Reenable interrupts. */ | |
5030 | tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); | |
5031 | mmiowb(); | |
5032 | break; | |
5033 | } | |
5034 | } | |
5035 | ||
5036 | return work_done; | |
5037 | ||
5038 | tx_recovery: | |
5039 | /* work_done is guaranteed to be less than budget. */ | |
5040 | napi_complete(napi); | |
5041 | schedule_work(&tp->reset_task); | |
5042 | return work_done; | |
5043 | } | |
5044 | ||
6f535763 DM |
5045 | static int tg3_poll(struct napi_struct *napi, int budget) |
5046 | { | |
8ef0442f MC |
5047 | struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi); |
5048 | struct tg3 *tp = tnapi->tp; | |
6f535763 | 5049 | int work_done = 0; |
898a56f8 | 5050 | struct tg3_hw_status *sblk = tnapi->hw_status; |
6f535763 DM |
5051 | |
5052 | while (1) { | |
35f2d7d0 MC |
5053 | tg3_poll_link(tp); |
5054 | ||
17375d25 | 5055 | work_done = tg3_poll_work(tnapi, work_done, budget); |
6f535763 DM |
5056 | |
5057 | if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) | |
5058 | goto tx_recovery; | |
5059 | ||
5060 | if (unlikely(work_done >= budget)) | |
5061 | break; | |
5062 | ||
4fd7ab59 | 5063 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { |
17375d25 | 5064 | /* tp->last_tag is used in tg3_int_reenable() below |
4fd7ab59 MC |
5065 | * to tell the hw how much work has been processed, |
5066 | * so we must read it before checking for more work. | |
5067 | */ | |
898a56f8 MC |
5068 | tnapi->last_tag = sblk->status_tag; |
5069 | tnapi->last_irq_tag = tnapi->last_tag; | |
4fd7ab59 MC |
5070 | rmb(); |
5071 | } else | |
5072 | sblk->status &= ~SD_STATUS_UPDATED; | |
6f535763 | 5073 | |
17375d25 | 5074 | if (likely(!tg3_has_work(tnapi))) { |
288379f0 | 5075 | napi_complete(napi); |
17375d25 | 5076 | tg3_int_reenable(tnapi); |
6f535763 DM |
5077 | break; |
5078 | } | |
1da177e4 LT |
5079 | } |
5080 | ||
bea3348e | 5081 | return work_done; |
6f535763 DM |
5082 | |
5083 | tx_recovery: | |
4fd7ab59 | 5084 | /* work_done is guaranteed to be less than budget. */ |
288379f0 | 5085 | napi_complete(napi); |
6f535763 | 5086 | schedule_work(&tp->reset_task); |
4fd7ab59 | 5087 | return work_done; |
1da177e4 LT |
5088 | } |
5089 | ||
f47c11ee DM |
5090 | static void tg3_irq_quiesce(struct tg3 *tp) |
5091 | { | |
4f125f42 MC |
5092 | int i; |
5093 | ||
f47c11ee DM |
5094 | BUG_ON(tp->irq_sync); |
5095 | ||
5096 | tp->irq_sync = 1; | |
5097 | smp_mb(); | |
5098 | ||
4f125f42 MC |
5099 | for (i = 0; i < tp->irq_cnt; i++) |
5100 | synchronize_irq(tp->napi[i].irq_vec); | |
f47c11ee DM |
5101 | } |
5102 | ||
5103 | static inline int tg3_irq_sync(struct tg3 *tp) | |
5104 | { | |
5105 | return tp->irq_sync; | |
5106 | } | |
5107 | ||
5108 | /* Fully shutdown all tg3 driver activity elsewhere in the system. | |
5109 | * If irq_sync is non-zero, then the IRQ handler must be synchronized | |
5110 | * with as well. Most of the time, this is not necessary except when | |
5111 | * shutting down the device. | |
5112 | */ | |
5113 | static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) | |
5114 | { | |
46966545 | 5115 | spin_lock_bh(&tp->lock); |
f47c11ee DM |
5116 | if (irq_sync) |
5117 | tg3_irq_quiesce(tp); | |
f47c11ee DM |
5118 | } |
5119 | ||
5120 | static inline void tg3_full_unlock(struct tg3 *tp) | |
5121 | { | |
f47c11ee DM |
5122 | spin_unlock_bh(&tp->lock); |
5123 | } | |
5124 | ||
fcfa0a32 MC |
5125 | /* One-shot MSI handler - Chip automatically disables interrupt |
5126 | * after sending MSI so driver doesn't have to do it. | |
5127 | */ | |
7d12e780 | 5128 | static irqreturn_t tg3_msi_1shot(int irq, void *dev_id) |
fcfa0a32 | 5129 | { |
09943a18 MC |
5130 | struct tg3_napi *tnapi = dev_id; |
5131 | struct tg3 *tp = tnapi->tp; | |
fcfa0a32 | 5132 | |
898a56f8 | 5133 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5134 | if (tnapi->rx_rcb) |
5135 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
fcfa0a32 MC |
5136 | |
5137 | if (likely(!tg3_irq_sync(tp))) | |
09943a18 | 5138 | napi_schedule(&tnapi->napi); |
fcfa0a32 MC |
5139 | |
5140 | return IRQ_HANDLED; | |
5141 | } | |
5142 | ||
88b06bc2 MC |
5143 | /* MSI ISR - No need to check for interrupt sharing and no need to |
5144 | * flush status block and interrupt mailbox. PCI ordering rules | |
5145 | * guarantee that MSI will arrive after the status block. | |
5146 | */ | |
7d12e780 | 5147 | static irqreturn_t tg3_msi(int irq, void *dev_id) |
88b06bc2 | 5148 | { |
09943a18 MC |
5149 | struct tg3_napi *tnapi = dev_id; |
5150 | struct tg3 *tp = tnapi->tp; | |
88b06bc2 | 5151 | |
898a56f8 | 5152 | prefetch(tnapi->hw_status); |
0c1d0e2b MC |
5153 | if (tnapi->rx_rcb) |
5154 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); | |
88b06bc2 | 5155 | /* |
fac9b83e | 5156 | * Writing any value to intr-mbox-0 clears PCI INTA# and |
88b06bc2 | 5157 | * chip-internal interrupt pending events. |
fac9b83e | 5158 | * Writing non-zero to intr-mbox-0 additional tells the |
88b06bc2 MC |
5159 | * NIC to stop sending us irqs, engaging "in-intr-handler" |
5160 | * event coalescing. | |
5161 | */ | |
5162 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | |
61487480 | 5163 | if (likely(!tg3_irq_sync(tp))) |
09943a18 | 5164 | napi_schedule(&tnapi->napi); |
61487480 | 5165 | |
88b06bc2 MC |
5166 | return IRQ_RETVAL(1); |
5167 | } | |
5168 | ||
7d12e780 | 5169 | static irqreturn_t tg3_interrupt(int irq, void *dev_id) |
1da177e4 | 5170 | { |
09943a18 MC |
5171 | struct tg3_napi *tnapi = dev_id; |
5172 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5173 | struct tg3_hw_status *sblk = tnapi->hw_status; |
1da177e4 LT |
5174 | unsigned int handled = 1; |
5175 | ||
1da177e4 LT |
5176 | /* In INTx mode, it is possible for the interrupt to arrive at |
5177 | * the CPU before the status block posted prior to the interrupt. | |
5178 | * Reading the PCI State register will confirm whether the | |
5179 | * interrupt is ours and will flush the status block. | |
5180 | */ | |
d18edcb2 MC |
5181 | if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { |
5182 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || | |
5183 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5184 | handled = 0; | |
f47c11ee | 5185 | goto out; |
fac9b83e | 5186 | } |
d18edcb2 MC |
5187 | } |
5188 | ||
5189 | /* | |
5190 | * Writing any value to intr-mbox-0 clears PCI INTA# and | |
5191 | * chip-internal interrupt pending events. | |
5192 | * Writing non-zero to intr-mbox-0 additional tells the | |
5193 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5194 | * event coalescing. | |
c04cb347 MC |
5195 | * |
5196 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5197 | * spurious interrupts. The flush impacts performance but | |
5198 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5199 | */ |
c04cb347 | 5200 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
d18edcb2 MC |
5201 | if (tg3_irq_sync(tp)) |
5202 | goto out; | |
5203 | sblk->status &= ~SD_STATUS_UPDATED; | |
17375d25 | 5204 | if (likely(tg3_has_work(tnapi))) { |
72334482 | 5205 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
09943a18 | 5206 | napi_schedule(&tnapi->napi); |
d18edcb2 MC |
5207 | } else { |
5208 | /* No work, shared interrupt perhaps? re-enable | |
5209 | * interrupts, and flush that PCI write | |
5210 | */ | |
5211 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | |
5212 | 0x00000000); | |
fac9b83e | 5213 | } |
f47c11ee | 5214 | out: |
fac9b83e DM |
5215 | return IRQ_RETVAL(handled); |
5216 | } | |
5217 | ||
7d12e780 | 5218 | static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id) |
fac9b83e | 5219 | { |
09943a18 MC |
5220 | struct tg3_napi *tnapi = dev_id; |
5221 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5222 | struct tg3_hw_status *sblk = tnapi->hw_status; |
fac9b83e DM |
5223 | unsigned int handled = 1; |
5224 | ||
fac9b83e DM |
5225 | /* In INTx mode, it is possible for the interrupt to arrive at |
5226 | * the CPU before the status block posted prior to the interrupt. | |
5227 | * Reading the PCI State register will confirm whether the | |
5228 | * interrupt is ours and will flush the status block. | |
5229 | */ | |
898a56f8 | 5230 | if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { |
d18edcb2 MC |
5231 | if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) || |
5232 | (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
5233 | handled = 0; | |
f47c11ee | 5234 | goto out; |
1da177e4 | 5235 | } |
d18edcb2 MC |
5236 | } |
5237 | ||
5238 | /* | |
5239 | * writing any value to intr-mbox-0 clears PCI INTA# and | |
5240 | * chip-internal interrupt pending events. | |
5241 | * writing non-zero to intr-mbox-0 additional tells the | |
5242 | * NIC to stop sending us irqs, engaging "in-intr-handler" | |
5243 | * event coalescing. | |
c04cb347 MC |
5244 | * |
5245 | * Flush the mailbox to de-assert the IRQ immediately to prevent | |
5246 | * spurious interrupts. The flush impacts performance but | |
5247 | * excessive spurious interrupts can be worse in some cases. | |
d18edcb2 | 5248 | */ |
c04cb347 | 5249 | tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); |
624f8e50 MC |
5250 | |
5251 | /* | |
5252 | * In a shared interrupt configuration, sometimes other devices' | |
5253 | * interrupts will scream. We record the current status tag here | |
5254 | * so that the above check can report that the screaming interrupts | |
5255 | * are unhandled. Eventually they will be silenced. | |
5256 | */ | |
898a56f8 | 5257 | tnapi->last_irq_tag = sblk->status_tag; |
624f8e50 | 5258 | |
d18edcb2 MC |
5259 | if (tg3_irq_sync(tp)) |
5260 | goto out; | |
624f8e50 | 5261 | |
72334482 | 5262 | prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); |
624f8e50 | 5263 | |
09943a18 | 5264 | napi_schedule(&tnapi->napi); |
624f8e50 | 5265 | |
f47c11ee | 5266 | out: |
1da177e4 LT |
5267 | return IRQ_RETVAL(handled); |
5268 | } | |
5269 | ||
7938109f | 5270 | /* ISR for interrupt test */ |
7d12e780 | 5271 | static irqreturn_t tg3_test_isr(int irq, void *dev_id) |
7938109f | 5272 | { |
09943a18 MC |
5273 | struct tg3_napi *tnapi = dev_id; |
5274 | struct tg3 *tp = tnapi->tp; | |
898a56f8 | 5275 | struct tg3_hw_status *sblk = tnapi->hw_status; |
7938109f | 5276 | |
f9804ddb MC |
5277 | if ((sblk->status & SD_STATUS_UPDATED) || |
5278 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) { | |
b16250e3 | 5279 | tg3_disable_ints(tp); |
7938109f MC |
5280 | return IRQ_RETVAL(1); |
5281 | } | |
5282 | return IRQ_RETVAL(0); | |
5283 | } | |
5284 | ||
8e7a22e3 | 5285 | static int tg3_init_hw(struct tg3 *, int); |
944d980e | 5286 | static int tg3_halt(struct tg3 *, int, int); |
1da177e4 | 5287 | |
b9ec6c1b MC |
5288 | /* Restart hardware after configuration changes, self-test, etc. |
5289 | * Invoked with tp->lock held. | |
5290 | */ | |
5291 | static int tg3_restart_hw(struct tg3 *tp, int reset_phy) | |
78c6146f ED |
5292 | __releases(tp->lock) |
5293 | __acquires(tp->lock) | |
b9ec6c1b MC |
5294 | { |
5295 | int err; | |
5296 | ||
5297 | err = tg3_init_hw(tp, reset_phy); | |
5298 | if (err) { | |
5129c3a3 MC |
5299 | netdev_err(tp->dev, |
5300 | "Failed to re-initialize device, aborting\n"); | |
b9ec6c1b MC |
5301 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
5302 | tg3_full_unlock(tp); | |
5303 | del_timer_sync(&tp->timer); | |
5304 | tp->irq_sync = 0; | |
fed97810 | 5305 | tg3_napi_enable(tp); |
b9ec6c1b MC |
5306 | dev_close(tp->dev); |
5307 | tg3_full_lock(tp, 0); | |
5308 | } | |
5309 | return err; | |
5310 | } | |
5311 | ||
1da177e4 LT |
5312 | #ifdef CONFIG_NET_POLL_CONTROLLER |
5313 | static void tg3_poll_controller(struct net_device *dev) | |
5314 | { | |
4f125f42 | 5315 | int i; |
88b06bc2 MC |
5316 | struct tg3 *tp = netdev_priv(dev); |
5317 | ||
4f125f42 | 5318 | for (i = 0; i < tp->irq_cnt; i++) |
fe234f0e | 5319 | tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); |
1da177e4 LT |
5320 | } |
5321 | #endif | |
5322 | ||
c4028958 | 5323 | static void tg3_reset_task(struct work_struct *work) |
1da177e4 | 5324 | { |
c4028958 | 5325 | struct tg3 *tp = container_of(work, struct tg3, reset_task); |
b02fd9e3 | 5326 | int err; |
1da177e4 LT |
5327 | unsigned int restart_timer; |
5328 | ||
7faa006f | 5329 | tg3_full_lock(tp, 0); |
7faa006f MC |
5330 | |
5331 | if (!netif_running(tp->dev)) { | |
7faa006f MC |
5332 | tg3_full_unlock(tp); |
5333 | return; | |
5334 | } | |
5335 | ||
5336 | tg3_full_unlock(tp); | |
5337 | ||
b02fd9e3 MC |
5338 | tg3_phy_stop(tp); |
5339 | ||
1da177e4 LT |
5340 | tg3_netif_stop(tp); |
5341 | ||
f47c11ee | 5342 | tg3_full_lock(tp, 1); |
1da177e4 LT |
5343 | |
5344 | restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER; | |
5345 | tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER; | |
5346 | ||
df3e6548 MC |
5347 | if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) { |
5348 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
5349 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
5350 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
5351 | tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING; | |
5352 | } | |
5353 | ||
944d980e | 5354 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); |
b02fd9e3 MC |
5355 | err = tg3_init_hw(tp, 1); |
5356 | if (err) | |
b9ec6c1b | 5357 | goto out; |
1da177e4 LT |
5358 | |
5359 | tg3_netif_start(tp); | |
5360 | ||
1da177e4 LT |
5361 | if (restart_timer) |
5362 | mod_timer(&tp->timer, jiffies + 1); | |
7faa006f | 5363 | |
b9ec6c1b | 5364 | out: |
7faa006f | 5365 | tg3_full_unlock(tp); |
b02fd9e3 MC |
5366 | |
5367 | if (!err) | |
5368 | tg3_phy_start(tp); | |
1da177e4 LT |
5369 | } |
5370 | ||
b0408751 MC |
5371 | static void tg3_dump_short_state(struct tg3 *tp) |
5372 | { | |
05dbe005 JP |
5373 | netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n", |
5374 | tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS)); | |
5375 | netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n", | |
5376 | tr32(RDMAC_STATUS), tr32(WDMAC_STATUS)); | |
b0408751 MC |
5377 | } |
5378 | ||
1da177e4 LT |
5379 | static void tg3_tx_timeout(struct net_device *dev) |
5380 | { | |
5381 | struct tg3 *tp = netdev_priv(dev); | |
5382 | ||
b0408751 | 5383 | if (netif_msg_tx_err(tp)) { |
05dbe005 | 5384 | netdev_err(dev, "transmit timed out, resetting\n"); |
b0408751 MC |
5385 | tg3_dump_short_state(tp); |
5386 | } | |
1da177e4 LT |
5387 | |
5388 | schedule_work(&tp->reset_task); | |
5389 | } | |
5390 | ||
c58ec932 MC |
5391 | /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */ |
5392 | static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len) | |
5393 | { | |
5394 | u32 base = (u32) mapping & 0xffffffff; | |
5395 | ||
5396 | return ((base > 0xffffdcc0) && | |
5397 | (base + len + 8 < base)); | |
5398 | } | |
5399 | ||
72f2afb8 MC |
5400 | /* Test for DMA addresses > 40-bit */ |
5401 | static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, | |
5402 | int len) | |
5403 | { | |
5404 | #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64) | |
6728a8e2 | 5405 | if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) |
50cf156a | 5406 | return (((u64) mapping + len) > DMA_BIT_MASK(40)); |
72f2afb8 MC |
5407 | return 0; |
5408 | #else | |
5409 | return 0; | |
5410 | #endif | |
5411 | } | |
5412 | ||
f3f3f27e | 5413 | static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32); |
1da177e4 | 5414 | |
72f2afb8 | 5415 | /* Workaround 4GB and 40-bit hardware DMA bugs. */ |
24f4efd4 MC |
5416 | static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi, |
5417 | struct sk_buff *skb, u32 last_plus_one, | |
5418 | u32 *start, u32 base_flags, u32 mss) | |
1da177e4 | 5419 | { |
24f4efd4 | 5420 | struct tg3 *tp = tnapi->tp; |
41588ba1 | 5421 | struct sk_buff *new_skb; |
c58ec932 | 5422 | dma_addr_t new_addr = 0; |
1da177e4 | 5423 | u32 entry = *start; |
c58ec932 | 5424 | int i, ret = 0; |
1da177e4 | 5425 | |
41588ba1 MC |
5426 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) |
5427 | new_skb = skb_copy(skb, GFP_ATOMIC); | |
5428 | else { | |
5429 | int more_headroom = 4 - ((unsigned long)skb->data & 3); | |
5430 | ||
5431 | new_skb = skb_copy_expand(skb, | |
5432 | skb_headroom(skb) + more_headroom, | |
5433 | skb_tailroom(skb), GFP_ATOMIC); | |
5434 | } | |
5435 | ||
1da177e4 | 5436 | if (!new_skb) { |
c58ec932 MC |
5437 | ret = -1; |
5438 | } else { | |
5439 | /* New SKB is guaranteed to be linear. */ | |
5440 | entry = *start; | |
f4188d8a AD |
5441 | new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, |
5442 | PCI_DMA_TODEVICE); | |
5443 | /* Make sure the mapping succeeded */ | |
5444 | if (pci_dma_mapping_error(tp->pdev, new_addr)) { | |
5445 | ret = -1; | |
5446 | dev_kfree_skb(new_skb); | |
5447 | new_skb = NULL; | |
90079ce8 | 5448 | |
c58ec932 MC |
5449 | /* Make sure new skb does not cross any 4G boundaries. |
5450 | * Drop the packet if it does. | |
5451 | */ | |
f4188d8a AD |
5452 | } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5453 | tg3_4g_overflow_test(new_addr, new_skb->len)) { | |
5454 | pci_unmap_single(tp->pdev, new_addr, new_skb->len, | |
5455 | PCI_DMA_TODEVICE); | |
c58ec932 MC |
5456 | ret = -1; |
5457 | dev_kfree_skb(new_skb); | |
5458 | new_skb = NULL; | |
5459 | } else { | |
f3f3f27e | 5460 | tg3_set_txd(tnapi, entry, new_addr, new_skb->len, |
c58ec932 MC |
5461 | base_flags, 1 | (mss << 1)); |
5462 | *start = NEXT_TX(entry); | |
5463 | } | |
1da177e4 LT |
5464 | } |
5465 | ||
1da177e4 LT |
5466 | /* Now clean up the sw ring entries. */ |
5467 | i = 0; | |
5468 | while (entry != last_plus_one) { | |
f4188d8a AD |
5469 | int len; |
5470 | ||
f3f3f27e | 5471 | if (i == 0) |
f4188d8a | 5472 | len = skb_headlen(skb); |
f3f3f27e | 5473 | else |
f4188d8a AD |
5474 | len = skb_shinfo(skb)->frags[i-1].size; |
5475 | ||
5476 | pci_unmap_single(tp->pdev, | |
5477 | pci_unmap_addr(&tnapi->tx_buffers[entry], | |
5478 | mapping), | |
5479 | len, PCI_DMA_TODEVICE); | |
5480 | if (i == 0) { | |
5481 | tnapi->tx_buffers[entry].skb = new_skb; | |
5482 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, | |
5483 | new_addr); | |
5484 | } else { | |
f3f3f27e | 5485 | tnapi->tx_buffers[entry].skb = NULL; |
f4188d8a | 5486 | } |
1da177e4 LT |
5487 | entry = NEXT_TX(entry); |
5488 | i++; | |
5489 | } | |
5490 | ||
5491 | dev_kfree_skb(skb); | |
5492 | ||
c58ec932 | 5493 | return ret; |
1da177e4 LT |
5494 | } |
5495 | ||
f3f3f27e | 5496 | static void tg3_set_txd(struct tg3_napi *tnapi, int entry, |
1da177e4 LT |
5497 | dma_addr_t mapping, int len, u32 flags, |
5498 | u32 mss_and_is_end) | |
5499 | { | |
f3f3f27e | 5500 | struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry]; |
1da177e4 LT |
5501 | int is_end = (mss_and_is_end & 0x1); |
5502 | u32 mss = (mss_and_is_end >> 1); | |
5503 | u32 vlan_tag = 0; | |
5504 | ||
5505 | if (is_end) | |
5506 | flags |= TXD_FLAG_END; | |
5507 | if (flags & TXD_FLAG_VLAN) { | |
5508 | vlan_tag = flags >> 16; | |
5509 | flags &= 0xffff; | |
5510 | } | |
5511 | vlan_tag |= (mss << TXD_MSS_SHIFT); | |
5512 | ||
5513 | txd->addr_hi = ((u64) mapping >> 32); | |
5514 | txd->addr_lo = ((u64) mapping & 0xffffffff); | |
5515 | txd->len_flags = (len << TXD_LEN_SHIFT) | flags; | |
5516 | txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT; | |
5517 | } | |
5518 | ||
5a6f3074 | 5519 | /* hard_start_xmit for devices that don't have any bugs and |
e849cdc3 | 5520 | * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only. |
5a6f3074 | 5521 | */ |
61357325 SH |
5522 | static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, |
5523 | struct net_device *dev) | |
5a6f3074 MC |
5524 | { |
5525 | struct tg3 *tp = netdev_priv(dev); | |
5a6f3074 | 5526 | u32 len, entry, base_flags, mss; |
90079ce8 | 5527 | dma_addr_t mapping; |
fe5f5787 MC |
5528 | struct tg3_napi *tnapi; |
5529 | struct netdev_queue *txq; | |
f4188d8a AD |
5530 | unsigned int i, last; |
5531 | ||
fe5f5787 MC |
5532 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5533 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 5534 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
fe5f5787 | 5535 | tnapi++; |
5a6f3074 | 5536 | |
00b70504 | 5537 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5538 | * and TX reclaim runs via tp->napi.poll inside of a software |
5a6f3074 MC |
5539 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5540 | * no IRQ context deadlocks to worry about either. Rejoice! | |
5541 | */ | |
f3f3f27e | 5542 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
fe5f5787 MC |
5543 | if (!netif_tx_queue_stopped(txq)) { |
5544 | netif_tx_stop_queue(txq); | |
5a6f3074 MC |
5545 | |
5546 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5547 | netdev_err(dev, |
5548 | "BUG! Tx Ring full when queue awake!\n"); | |
5a6f3074 | 5549 | } |
5a6f3074 MC |
5550 | return NETDEV_TX_BUSY; |
5551 | } | |
5552 | ||
f3f3f27e | 5553 | entry = tnapi->tx_prod; |
5a6f3074 | 5554 | base_flags = 0; |
5a6f3074 | 5555 | mss = 0; |
c13e3713 | 5556 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { |
5a6f3074 | 5557 | int tcp_opt_len, ip_tcp_len; |
f6eb9b1f | 5558 | u32 hdrlen; |
5a6f3074 MC |
5559 | |
5560 | if (skb_header_cloned(skb) && | |
5561 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5562 | dev_kfree_skb(skb); | |
5563 | goto out_unlock; | |
5564 | } | |
5565 | ||
b0026624 | 5566 | if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) |
f6eb9b1f | 5567 | hdrlen = skb_headlen(skb) - ETH_HLEN; |
b0026624 | 5568 | else { |
eddc9ec5 ACM |
5569 | struct iphdr *iph = ip_hdr(skb); |
5570 | ||
ab6a5bb6 | 5571 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5572 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
b0026624 | 5573 | |
eddc9ec5 ACM |
5574 | iph->check = 0; |
5575 | iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len); | |
f6eb9b1f | 5576 | hdrlen = ip_tcp_len + tcp_opt_len; |
b0026624 | 5577 | } |
5a6f3074 | 5578 | |
e849cdc3 | 5579 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
f6eb9b1f MC |
5580 | mss |= (hdrlen & 0xc) << 12; |
5581 | if (hdrlen & 0x10) | |
5582 | base_flags |= 0x00000010; | |
5583 | base_flags |= (hdrlen & 0x3e0) << 5; | |
5584 | } else | |
5585 | mss |= hdrlen << 9; | |
5586 | ||
5a6f3074 MC |
5587 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5588 | TXD_FLAG_CPU_POST_DMA); | |
5589 | ||
aa8223c7 | 5590 | tcp_hdr(skb)->check = 0; |
5a6f3074 | 5591 | |
859a5887 | 5592 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
5a6f3074 | 5593 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
859a5887 MC |
5594 | } |
5595 | ||
5a6f3074 MC |
5596 | #if TG3_VLAN_TAG_USED |
5597 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5598 | base_flags |= (TXD_FLAG_VLAN | | |
5599 | (vlan_tx_tag_get(skb) << 16)); | |
5600 | #endif | |
5601 | ||
f4188d8a AD |
5602 | len = skb_headlen(skb); |
5603 | ||
5604 | /* Queue skb data, a.k.a. the main skb fragment. */ | |
5605 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5606 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
5607 | dev_kfree_skb(skb); |
5608 | goto out_unlock; | |
5609 | } | |
5610 | ||
f3f3f27e | 5611 | tnapi->tx_buffers[entry].skb = skb; |
f4188d8a | 5612 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
fe5f5787 | 5613 | |
b703df6f | 5614 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
f6eb9b1f MC |
5615 | !mss && skb->len > ETH_DATA_LEN) |
5616 | base_flags |= TXD_FLAG_JMB_PKT; | |
5617 | ||
f3f3f27e | 5618 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
5a6f3074 MC |
5619 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5620 | ||
5621 | entry = NEXT_TX(entry); | |
5622 | ||
5623 | /* Now loop through additional data fragments, and queue them. */ | |
5624 | if (skb_shinfo(skb)->nr_frags > 0) { | |
5a6f3074 MC |
5625 | last = skb_shinfo(skb)->nr_frags - 1; |
5626 | for (i = 0; i <= last; i++) { | |
5627 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5628 | ||
5629 | len = frag->size; | |
f4188d8a AD |
5630 | mapping = pci_map_page(tp->pdev, |
5631 | frag->page, | |
5632 | frag->page_offset, | |
5633 | len, PCI_DMA_TODEVICE); | |
5634 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
5635 | goto dma_error; | |
5636 | ||
f3f3f27e | 5637 | tnapi->tx_buffers[entry].skb = NULL; |
f4188d8a AD |
5638 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
5639 | mapping); | |
5a6f3074 | 5640 | |
f3f3f27e | 5641 | tg3_set_txd(tnapi, entry, mapping, len, |
5a6f3074 MC |
5642 | base_flags, (i == last) | (mss << 1)); |
5643 | ||
5644 | entry = NEXT_TX(entry); | |
5645 | } | |
5646 | } | |
5647 | ||
5648 | /* Packets are ready, update Tx producer idx local and on card. */ | |
f3f3f27e | 5649 | tw32_tx_mbox(tnapi->prodmbox, entry); |
5a6f3074 | 5650 | |
f3f3f27e MC |
5651 | tnapi->tx_prod = entry; |
5652 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
fe5f5787 | 5653 | netif_tx_stop_queue(txq); |
f3f3f27e | 5654 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
fe5f5787 | 5655 | netif_tx_wake_queue(txq); |
5a6f3074 MC |
5656 | } |
5657 | ||
5658 | out_unlock: | |
cdd0db05 | 5659 | mmiowb(); |
5a6f3074 MC |
5660 | |
5661 | return NETDEV_TX_OK; | |
f4188d8a AD |
5662 | |
5663 | dma_error: | |
5664 | last = i; | |
5665 | entry = tnapi->tx_prod; | |
5666 | tnapi->tx_buffers[entry].skb = NULL; | |
5667 | pci_unmap_single(tp->pdev, | |
5668 | pci_unmap_addr(&tnapi->tx_buffers[entry], mapping), | |
5669 | skb_headlen(skb), | |
5670 | PCI_DMA_TODEVICE); | |
5671 | for (i = 0; i <= last; i++) { | |
5672 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5673 | entry = NEXT_TX(entry); | |
5674 | ||
5675 | pci_unmap_page(tp->pdev, | |
5676 | pci_unmap_addr(&tnapi->tx_buffers[entry], | |
5677 | mapping), | |
5678 | frag->size, PCI_DMA_TODEVICE); | |
5679 | } | |
5680 | ||
5681 | dev_kfree_skb(skb); | |
5682 | return NETDEV_TX_OK; | |
5a6f3074 MC |
5683 | } |
5684 | ||
61357325 SH |
5685 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *, |
5686 | struct net_device *); | |
52c0fd83 MC |
5687 | |
5688 | /* Use GSO to workaround a rare TSO bug that may be triggered when the | |
5689 | * TSO header is greater than 80 bytes. | |
5690 | */ | |
5691 | static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb) | |
5692 | { | |
5693 | struct sk_buff *segs, *nskb; | |
f3f3f27e | 5694 | u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; |
52c0fd83 MC |
5695 | |
5696 | /* Estimate the number of fragments in the worst case */ | |
f3f3f27e | 5697 | if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) { |
52c0fd83 | 5698 | netif_stop_queue(tp->dev); |
f3f3f27e | 5699 | if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est) |
7f62ad5d MC |
5700 | return NETDEV_TX_BUSY; |
5701 | ||
5702 | netif_wake_queue(tp->dev); | |
52c0fd83 MC |
5703 | } |
5704 | ||
5705 | segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); | |
801678c5 | 5706 | if (IS_ERR(segs)) |
52c0fd83 MC |
5707 | goto tg3_tso_bug_end; |
5708 | ||
5709 | do { | |
5710 | nskb = segs; | |
5711 | segs = segs->next; | |
5712 | nskb->next = NULL; | |
5713 | tg3_start_xmit_dma_bug(nskb, tp->dev); | |
5714 | } while (segs); | |
5715 | ||
5716 | tg3_tso_bug_end: | |
5717 | dev_kfree_skb(skb); | |
5718 | ||
5719 | return NETDEV_TX_OK; | |
5720 | } | |
52c0fd83 | 5721 | |
5a6f3074 MC |
5722 | /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and |
5723 | * support TG3_FLG2_HW_TSO_1 or firmware TSO only. | |
5724 | */ | |
61357325 SH |
5725 | static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb, |
5726 | struct net_device *dev) | |
1da177e4 LT |
5727 | { |
5728 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 LT |
5729 | u32 len, entry, base_flags, mss; |
5730 | int would_hit_hwbug; | |
90079ce8 | 5731 | dma_addr_t mapping; |
24f4efd4 MC |
5732 | struct tg3_napi *tnapi; |
5733 | struct netdev_queue *txq; | |
f4188d8a AD |
5734 | unsigned int i, last; |
5735 | ||
24f4efd4 MC |
5736 | txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); |
5737 | tnapi = &tp->napi[skb_get_queue_mapping(skb)]; | |
19cfaecc | 5738 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
24f4efd4 | 5739 | tnapi++; |
1da177e4 | 5740 | |
00b70504 | 5741 | /* We are running in BH disabled context with netif_tx_lock |
bea3348e | 5742 | * and TX reclaim runs via tp->napi.poll inside of a software |
f47c11ee DM |
5743 | * interrupt. Furthermore, IRQ processing runs lockless so we have |
5744 | * no IRQ context deadlocks to worry about either. Rejoice! | |
1da177e4 | 5745 | */ |
f3f3f27e | 5746 | if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) { |
24f4efd4 MC |
5747 | if (!netif_tx_queue_stopped(txq)) { |
5748 | netif_tx_stop_queue(txq); | |
1f064a87 SH |
5749 | |
5750 | /* This is a hard error, log it. */ | |
5129c3a3 MC |
5751 | netdev_err(dev, |
5752 | "BUG! Tx Ring full when queue awake!\n"); | |
1f064a87 | 5753 | } |
1da177e4 LT |
5754 | return NETDEV_TX_BUSY; |
5755 | } | |
5756 | ||
f3f3f27e | 5757 | entry = tnapi->tx_prod; |
1da177e4 | 5758 | base_flags = 0; |
84fa7933 | 5759 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
1da177e4 | 5760 | base_flags |= TXD_FLAG_TCPUDP_CSUM; |
24f4efd4 | 5761 | |
c13e3713 | 5762 | if ((mss = skb_shinfo(skb)->gso_size) != 0) { |
eddc9ec5 | 5763 | struct iphdr *iph; |
92c6b8d1 | 5764 | u32 tcp_opt_len, ip_tcp_len, hdr_len; |
1da177e4 LT |
5765 | |
5766 | if (skb_header_cloned(skb) && | |
5767 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
5768 | dev_kfree_skb(skb); | |
5769 | goto out_unlock; | |
5770 | } | |
5771 | ||
ab6a5bb6 | 5772 | tcp_opt_len = tcp_optlen(skb); |
c9bdd4b5 | 5773 | ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr); |
1da177e4 | 5774 | |
52c0fd83 MC |
5775 | hdr_len = ip_tcp_len + tcp_opt_len; |
5776 | if (unlikely((ETH_HLEN + hdr_len) > 80) && | |
7f62ad5d | 5777 | (tp->tg3_flags2 & TG3_FLG2_TSO_BUG)) |
de6f31eb | 5778 | return tg3_tso_bug(tp, skb); |
52c0fd83 | 5779 | |
1da177e4 LT |
5780 | base_flags |= (TXD_FLAG_CPU_PRE_DMA | |
5781 | TXD_FLAG_CPU_POST_DMA); | |
5782 | ||
eddc9ec5 ACM |
5783 | iph = ip_hdr(skb); |
5784 | iph->check = 0; | |
5785 | iph->tot_len = htons(mss + hdr_len); | |
1da177e4 | 5786 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { |
aa8223c7 | 5787 | tcp_hdr(skb)->check = 0; |
1da177e4 | 5788 | base_flags &= ~TXD_FLAG_TCPUDP_CSUM; |
aa8223c7 ACM |
5789 | } else |
5790 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5791 | iph->daddr, 0, | |
5792 | IPPROTO_TCP, | |
5793 | 0); | |
1da177e4 | 5794 | |
615774fe MC |
5795 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) { |
5796 | mss |= (hdr_len & 0xc) << 12; | |
5797 | if (hdr_len & 0x10) | |
5798 | base_flags |= 0x00000010; | |
5799 | base_flags |= (hdr_len & 0x3e0) << 5; | |
5800 | } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) | |
92c6b8d1 MC |
5801 | mss |= hdr_len << 9; |
5802 | else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) || | |
5803 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
eddc9ec5 | 5804 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5805 | int tsflags; |
5806 | ||
eddc9ec5 | 5807 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5808 | mss |= (tsflags << 11); |
5809 | } | |
5810 | } else { | |
eddc9ec5 | 5811 | if (tcp_opt_len || iph->ihl > 5) { |
1da177e4 LT |
5812 | int tsflags; |
5813 | ||
eddc9ec5 | 5814 | tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); |
1da177e4 LT |
5815 | base_flags |= tsflags << 12; |
5816 | } | |
5817 | } | |
5818 | } | |
1da177e4 LT |
5819 | #if TG3_VLAN_TAG_USED |
5820 | if (tp->vlgrp != NULL && vlan_tx_tag_present(skb)) | |
5821 | base_flags |= (TXD_FLAG_VLAN | | |
5822 | (vlan_tx_tag_get(skb) << 16)); | |
5823 | #endif | |
5824 | ||
b703df6f | 5825 | if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) && |
615774fe MC |
5826 | !mss && skb->len > ETH_DATA_LEN) |
5827 | base_flags |= TXD_FLAG_JMB_PKT; | |
5828 | ||
f4188d8a AD |
5829 | len = skb_headlen(skb); |
5830 | ||
5831 | mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
5832 | if (pci_dma_mapping_error(tp->pdev, mapping)) { | |
90079ce8 DM |
5833 | dev_kfree_skb(skb); |
5834 | goto out_unlock; | |
5835 | } | |
5836 | ||
f3f3f27e | 5837 | tnapi->tx_buffers[entry].skb = skb; |
f4188d8a | 5838 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); |
1da177e4 LT |
5839 | |
5840 | would_hit_hwbug = 0; | |
5841 | ||
92c6b8d1 MC |
5842 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8) |
5843 | would_hit_hwbug = 1; | |
5844 | ||
0e1406dd MC |
5845 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5846 | tg3_4g_overflow_test(mapping, len)) | |
5847 | would_hit_hwbug = 1; | |
5848 | ||
5849 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && | |
5850 | tg3_40bit_overflow_test(tp, mapping, len)) | |
41588ba1 | 5851 | would_hit_hwbug = 1; |
0e1406dd MC |
5852 | |
5853 | if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG) | |
c58ec932 | 5854 | would_hit_hwbug = 1; |
1da177e4 | 5855 | |
f3f3f27e | 5856 | tg3_set_txd(tnapi, entry, mapping, len, base_flags, |
1da177e4 LT |
5857 | (skb_shinfo(skb)->nr_frags == 0) | (mss << 1)); |
5858 | ||
5859 | entry = NEXT_TX(entry); | |
5860 | ||
5861 | /* Now loop through additional data fragments, and queue them. */ | |
5862 | if (skb_shinfo(skb)->nr_frags > 0) { | |
1da177e4 LT |
5863 | last = skb_shinfo(skb)->nr_frags - 1; |
5864 | for (i = 0; i <= last; i++) { | |
5865 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5866 | ||
5867 | len = frag->size; | |
f4188d8a AD |
5868 | mapping = pci_map_page(tp->pdev, |
5869 | frag->page, | |
5870 | frag->page_offset, | |
5871 | len, PCI_DMA_TODEVICE); | |
1da177e4 | 5872 | |
f3f3f27e | 5873 | tnapi->tx_buffers[entry].skb = NULL; |
f4188d8a AD |
5874 | pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, |
5875 | mapping); | |
5876 | if (pci_dma_mapping_error(tp->pdev, mapping)) | |
5877 | goto dma_error; | |
1da177e4 | 5878 | |
92c6b8d1 MC |
5879 | if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && |
5880 | len <= 8) | |
5881 | would_hit_hwbug = 1; | |
5882 | ||
0e1406dd MC |
5883 | if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) && |
5884 | tg3_4g_overflow_test(mapping, len)) | |
c58ec932 | 5885 | would_hit_hwbug = 1; |
1da177e4 | 5886 | |
0e1406dd MC |
5887 | if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) && |
5888 | tg3_40bit_overflow_test(tp, mapping, len)) | |
72f2afb8 MC |
5889 | would_hit_hwbug = 1; |
5890 | ||
1da177e4 | 5891 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
f3f3f27e | 5892 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
5893 | base_flags, (i == last)|(mss << 1)); |
5894 | else | |
f3f3f27e | 5895 | tg3_set_txd(tnapi, entry, mapping, len, |
1da177e4 LT |
5896 | base_flags, (i == last)); |
5897 | ||
5898 | entry = NEXT_TX(entry); | |
5899 | } | |
5900 | } | |
5901 | ||
5902 | if (would_hit_hwbug) { | |
5903 | u32 last_plus_one = entry; | |
5904 | u32 start; | |
1da177e4 | 5905 | |
c58ec932 MC |
5906 | start = entry - 1 - skb_shinfo(skb)->nr_frags; |
5907 | start &= (TG3_TX_RING_SIZE - 1); | |
1da177e4 LT |
5908 | |
5909 | /* If the workaround fails due to memory/mapping | |
5910 | * failure, silently drop this packet. | |
5911 | */ | |
24f4efd4 | 5912 | if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one, |
c58ec932 | 5913 | &start, base_flags, mss)) |
1da177e4 LT |
5914 | goto out_unlock; |
5915 | ||
5916 | entry = start; | |
5917 | } | |
5918 | ||
5919 | /* Packets are ready, update Tx producer idx local and on card. */ | |
24f4efd4 | 5920 | tw32_tx_mbox(tnapi->prodmbox, entry); |
1da177e4 | 5921 | |
f3f3f27e MC |
5922 | tnapi->tx_prod = entry; |
5923 | if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) { | |
24f4efd4 | 5924 | netif_tx_stop_queue(txq); |
f3f3f27e | 5925 | if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)) |
24f4efd4 | 5926 | netif_tx_wake_queue(txq); |
51b91468 | 5927 | } |
1da177e4 LT |
5928 | |
5929 | out_unlock: | |
cdd0db05 | 5930 | mmiowb(); |
1da177e4 LT |
5931 | |
5932 | return NETDEV_TX_OK; | |
f4188d8a AD |
5933 | |
5934 | dma_error: | |
5935 | last = i; | |
5936 | entry = tnapi->tx_prod; | |
5937 | tnapi->tx_buffers[entry].skb = NULL; | |
5938 | pci_unmap_single(tp->pdev, | |
5939 | pci_unmap_addr(&tnapi->tx_buffers[entry], mapping), | |
5940 | skb_headlen(skb), | |
5941 | PCI_DMA_TODEVICE); | |
5942 | for (i = 0; i <= last; i++) { | |
5943 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
5944 | entry = NEXT_TX(entry); | |
5945 | ||
5946 | pci_unmap_page(tp->pdev, | |
5947 | pci_unmap_addr(&tnapi->tx_buffers[entry], | |
5948 | mapping), | |
5949 | frag->size, PCI_DMA_TODEVICE); | |
5950 | } | |
5951 | ||
5952 | dev_kfree_skb(skb); | |
5953 | return NETDEV_TX_OK; | |
1da177e4 LT |
5954 | } |
5955 | ||
5956 | static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, | |
5957 | int new_mtu) | |
5958 | { | |
5959 | dev->mtu = new_mtu; | |
5960 | ||
ef7f5ec0 | 5961 | if (new_mtu > ETH_DATA_LEN) { |
a4e2b347 | 5962 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { |
ef7f5ec0 MC |
5963 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
5964 | ethtool_op_set_tso(dev, 0); | |
859a5887 | 5965 | } else { |
ef7f5ec0 | 5966 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
859a5887 | 5967 | } |
ef7f5ec0 | 5968 | } else { |
a4e2b347 | 5969 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) |
ef7f5ec0 | 5970 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
0f893dc6 | 5971 | tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE; |
ef7f5ec0 | 5972 | } |
1da177e4 LT |
5973 | } |
5974 | ||
5975 | static int tg3_change_mtu(struct net_device *dev, int new_mtu) | |
5976 | { | |
5977 | struct tg3 *tp = netdev_priv(dev); | |
b9ec6c1b | 5978 | int err; |
1da177e4 LT |
5979 | |
5980 | if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp)) | |
5981 | return -EINVAL; | |
5982 | ||
5983 | if (!netif_running(dev)) { | |
5984 | /* We'll just catch it later when the | |
5985 | * device is up'd. | |
5986 | */ | |
5987 | tg3_set_mtu(dev, tp, new_mtu); | |
5988 | return 0; | |
5989 | } | |
5990 | ||
b02fd9e3 MC |
5991 | tg3_phy_stop(tp); |
5992 | ||
1da177e4 | 5993 | tg3_netif_stop(tp); |
f47c11ee DM |
5994 | |
5995 | tg3_full_lock(tp, 1); | |
1da177e4 | 5996 | |
944d980e | 5997 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
5998 | |
5999 | tg3_set_mtu(dev, tp, new_mtu); | |
6000 | ||
b9ec6c1b | 6001 | err = tg3_restart_hw(tp, 0); |
1da177e4 | 6002 | |
b9ec6c1b MC |
6003 | if (!err) |
6004 | tg3_netif_start(tp); | |
1da177e4 | 6005 | |
f47c11ee | 6006 | tg3_full_unlock(tp); |
1da177e4 | 6007 | |
b02fd9e3 MC |
6008 | if (!err) |
6009 | tg3_phy_start(tp); | |
6010 | ||
b9ec6c1b | 6011 | return err; |
1da177e4 LT |
6012 | } |
6013 | ||
21f581a5 MC |
6014 | static void tg3_rx_prodring_free(struct tg3 *tp, |
6015 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6016 | { |
1da177e4 LT |
6017 | int i; |
6018 | ||
b196c7e4 MC |
6019 | if (tpr != &tp->prodring[0]) { |
6020 | for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; | |
6021 | i = (i + 1) % TG3_RX_RING_SIZE) | |
6022 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], | |
6023 | tp->rx_pkt_map_sz); | |
6024 | ||
6025 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
6026 | for (i = tpr->rx_jmb_cons_idx; | |
6027 | i != tpr->rx_jmb_prod_idx; | |
6028 | i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) { | |
6029 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], | |
6030 | TG3_RX_JMB_MAP_SZ); | |
6031 | } | |
6032 | } | |
6033 | ||
2b2cdb65 | 6034 | return; |
b196c7e4 | 6035 | } |
1da177e4 | 6036 | |
2b2cdb65 MC |
6037 | for (i = 0; i < TG3_RX_RING_SIZE; i++) |
6038 | tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i], | |
6039 | tp->rx_pkt_map_sz); | |
1da177e4 | 6040 | |
cf7a7298 | 6041 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { |
2b2cdb65 MC |
6042 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) |
6043 | tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i], | |
6044 | TG3_RX_JMB_MAP_SZ); | |
1da177e4 LT |
6045 | } |
6046 | } | |
6047 | ||
c6cdf436 | 6048 | /* Initialize rx rings for packet processing. |
1da177e4 LT |
6049 | * |
6050 | * The chip has been shut down and the driver detached from | |
6051 | * the networking, so no interrupts or new tx packets will | |
6052 | * end up in the driver. tp->{tx,}lock are held and thus | |
6053 | * we may not sleep. | |
6054 | */ | |
21f581a5 MC |
6055 | static int tg3_rx_prodring_alloc(struct tg3 *tp, |
6056 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6057 | { |
287be12e | 6058 | u32 i, rx_pkt_dma_sz; |
1da177e4 | 6059 | |
b196c7e4 MC |
6060 | tpr->rx_std_cons_idx = 0; |
6061 | tpr->rx_std_prod_idx = 0; | |
6062 | tpr->rx_jmb_cons_idx = 0; | |
6063 | tpr->rx_jmb_prod_idx = 0; | |
6064 | ||
2b2cdb65 MC |
6065 | if (tpr != &tp->prodring[0]) { |
6066 | memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE); | |
6067 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) | |
6068 | memset(&tpr->rx_jmb_buffers[0], 0, | |
6069 | TG3_RX_JMB_BUFF_RING_SIZE); | |
6070 | goto done; | |
6071 | } | |
6072 | ||
1da177e4 | 6073 | /* Zero out all descriptors. */ |
21f581a5 | 6074 | memset(tpr->rx_std, 0, TG3_RX_RING_BYTES); |
1da177e4 | 6075 | |
287be12e | 6076 | rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ; |
a4e2b347 | 6077 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) && |
287be12e MC |
6078 | tp->dev->mtu > ETH_DATA_LEN) |
6079 | rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ; | |
6080 | tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); | |
7e72aad4 | 6081 | |
1da177e4 LT |
6082 | /* Initialize invariants of the rings, we only set this |
6083 | * stuff once. This works because the card does not | |
6084 | * write into the rx buffer posting rings. | |
6085 | */ | |
6086 | for (i = 0; i < TG3_RX_RING_SIZE; i++) { | |
6087 | struct tg3_rx_buffer_desc *rxd; | |
6088 | ||
21f581a5 | 6089 | rxd = &tpr->rx_std[i]; |
287be12e | 6090 | rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; |
1da177e4 LT |
6091 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); |
6092 | rxd->opaque = (RXD_OPAQUE_RING_STD | | |
6093 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6094 | } | |
6095 | ||
1da177e4 LT |
6096 | /* Now allocate fresh SKBs for each rx ring. */ |
6097 | for (i = 0; i < tp->rx_pending; i++) { | |
86b21e59 | 6098 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) { |
5129c3a3 MC |
6099 | netdev_warn(tp->dev, |
6100 | "Using a smaller RX standard ring. Only " | |
6101 | "%d out of %d buffers were allocated " | |
6102 | "successfully\n", i, tp->rx_pending); | |
32d8c572 | 6103 | if (i == 0) |
cf7a7298 | 6104 | goto initfail; |
32d8c572 | 6105 | tp->rx_pending = i; |
1da177e4 | 6106 | break; |
32d8c572 | 6107 | } |
1da177e4 LT |
6108 | } |
6109 | ||
cf7a7298 MC |
6110 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)) |
6111 | goto done; | |
6112 | ||
21f581a5 | 6113 | memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES); |
cf7a7298 | 6114 | |
0d86df80 MC |
6115 | if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)) |
6116 | goto done; | |
cf7a7298 | 6117 | |
0d86df80 MC |
6118 | for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) { |
6119 | struct tg3_rx_buffer_desc *rxd; | |
6120 | ||
6121 | rxd = &tpr->rx_jmb[i].std; | |
6122 | rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; | |
6123 | rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | | |
6124 | RXD_FLAG_JUMBO; | |
6125 | rxd->opaque = (RXD_OPAQUE_RING_JUMBO | | |
6126 | (i << RXD_OPAQUE_INDEX_SHIFT)); | |
6127 | } | |
6128 | ||
6129 | for (i = 0; i < tp->rx_jumbo_pending; i++) { | |
6130 | if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) { | |
5129c3a3 MC |
6131 | netdev_warn(tp->dev, |
6132 | "Using a smaller RX jumbo ring. Only %d " | |
6133 | "out of %d buffers were allocated " | |
6134 | "successfully\n", i, tp->rx_jumbo_pending); | |
0d86df80 MC |
6135 | if (i == 0) |
6136 | goto initfail; | |
6137 | tp->rx_jumbo_pending = i; | |
6138 | break; | |
1da177e4 LT |
6139 | } |
6140 | } | |
cf7a7298 MC |
6141 | |
6142 | done: | |
32d8c572 | 6143 | return 0; |
cf7a7298 MC |
6144 | |
6145 | initfail: | |
21f581a5 | 6146 | tg3_rx_prodring_free(tp, tpr); |
cf7a7298 | 6147 | return -ENOMEM; |
1da177e4 LT |
6148 | } |
6149 | ||
21f581a5 MC |
6150 | static void tg3_rx_prodring_fini(struct tg3 *tp, |
6151 | struct tg3_rx_prodring_set *tpr) | |
1da177e4 | 6152 | { |
21f581a5 MC |
6153 | kfree(tpr->rx_std_buffers); |
6154 | tpr->rx_std_buffers = NULL; | |
6155 | kfree(tpr->rx_jmb_buffers); | |
6156 | tpr->rx_jmb_buffers = NULL; | |
6157 | if (tpr->rx_std) { | |
1da177e4 | 6158 | pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES, |
21f581a5 MC |
6159 | tpr->rx_std, tpr->rx_std_mapping); |
6160 | tpr->rx_std = NULL; | |
1da177e4 | 6161 | } |
21f581a5 | 6162 | if (tpr->rx_jmb) { |
1da177e4 | 6163 | pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES, |
21f581a5 MC |
6164 | tpr->rx_jmb, tpr->rx_jmb_mapping); |
6165 | tpr->rx_jmb = NULL; | |
1da177e4 | 6166 | } |
cf7a7298 MC |
6167 | } |
6168 | ||
21f581a5 MC |
6169 | static int tg3_rx_prodring_init(struct tg3 *tp, |
6170 | struct tg3_rx_prodring_set *tpr) | |
cf7a7298 | 6171 | { |
2b2cdb65 | 6172 | tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL); |
21f581a5 | 6173 | if (!tpr->rx_std_buffers) |
cf7a7298 MC |
6174 | return -ENOMEM; |
6175 | ||
21f581a5 MC |
6176 | tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES, |
6177 | &tpr->rx_std_mapping); | |
6178 | if (!tpr->rx_std) | |
cf7a7298 MC |
6179 | goto err_out; |
6180 | ||
6181 | if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) { | |
2b2cdb65 | 6182 | tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE, |
21f581a5 MC |
6183 | GFP_KERNEL); |
6184 | if (!tpr->rx_jmb_buffers) | |
cf7a7298 MC |
6185 | goto err_out; |
6186 | ||
21f581a5 MC |
6187 | tpr->rx_jmb = pci_alloc_consistent(tp->pdev, |
6188 | TG3_RX_JUMBO_RING_BYTES, | |
6189 | &tpr->rx_jmb_mapping); | |
6190 | if (!tpr->rx_jmb) | |
cf7a7298 MC |
6191 | goto err_out; |
6192 | } | |
6193 | ||
6194 | return 0; | |
6195 | ||
6196 | err_out: | |
21f581a5 | 6197 | tg3_rx_prodring_fini(tp, tpr); |
cf7a7298 MC |
6198 | return -ENOMEM; |
6199 | } | |
6200 | ||
6201 | /* Free up pending packets in all rx/tx rings. | |
6202 | * | |
6203 | * The chip has been shut down and the driver detached from | |
6204 | * the networking, so no interrupts or new tx packets will | |
6205 | * end up in the driver. tp->{tx,}lock is not held and we are not | |
6206 | * in an interrupt context and thus may sleep. | |
6207 | */ | |
6208 | static void tg3_free_rings(struct tg3 *tp) | |
6209 | { | |
f77a6a8e | 6210 | int i, j; |
cf7a7298 | 6211 | |
f77a6a8e MC |
6212 | for (j = 0; j < tp->irq_cnt; j++) { |
6213 | struct tg3_napi *tnapi = &tp->napi[j]; | |
cf7a7298 | 6214 | |
0c1d0e2b MC |
6215 | if (!tnapi->tx_buffers) |
6216 | continue; | |
6217 | ||
f77a6a8e | 6218 | for (i = 0; i < TG3_TX_RING_SIZE; ) { |
f4188d8a | 6219 | struct ring_info *txp; |
f77a6a8e | 6220 | struct sk_buff *skb; |
f4188d8a | 6221 | unsigned int k; |
cf7a7298 | 6222 | |
f77a6a8e MC |
6223 | txp = &tnapi->tx_buffers[i]; |
6224 | skb = txp->skb; | |
cf7a7298 | 6225 | |
f77a6a8e MC |
6226 | if (skb == NULL) { |
6227 | i++; | |
6228 | continue; | |
6229 | } | |
cf7a7298 | 6230 | |
f4188d8a AD |
6231 | pci_unmap_single(tp->pdev, |
6232 | pci_unmap_addr(txp, mapping), | |
6233 | skb_headlen(skb), | |
6234 | PCI_DMA_TODEVICE); | |
f77a6a8e | 6235 | txp->skb = NULL; |
cf7a7298 | 6236 | |
f4188d8a AD |
6237 | i++; |
6238 | ||
6239 | for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) { | |
6240 | txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)]; | |
6241 | pci_unmap_page(tp->pdev, | |
6242 | pci_unmap_addr(txp, mapping), | |
6243 | skb_shinfo(skb)->frags[k].size, | |
6244 | PCI_DMA_TODEVICE); | |
6245 | i++; | |
6246 | } | |
f77a6a8e MC |
6247 | |
6248 | dev_kfree_skb_any(skb); | |
6249 | } | |
cf7a7298 | 6250 | |
e4af1af9 | 6251 | tg3_rx_prodring_free(tp, &tp->prodring[j]); |
2b2cdb65 | 6252 | } |
cf7a7298 MC |
6253 | } |
6254 | ||
6255 | /* Initialize tx/rx rings for packet processing. | |
6256 | * | |
6257 | * The chip has been shut down and the driver detached from | |
6258 | * the networking, so no interrupts or new tx packets will | |
6259 | * end up in the driver. tp->{tx,}lock are held and thus | |
6260 | * we may not sleep. | |
6261 | */ | |
6262 | static int tg3_init_rings(struct tg3 *tp) | |
6263 | { | |
f77a6a8e | 6264 | int i; |
72334482 | 6265 | |
cf7a7298 MC |
6266 | /* Free up all the SKBs. */ |
6267 | tg3_free_rings(tp); | |
6268 | ||
f77a6a8e MC |
6269 | for (i = 0; i < tp->irq_cnt; i++) { |
6270 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6271 | ||
6272 | tnapi->last_tag = 0; | |
6273 | tnapi->last_irq_tag = 0; | |
6274 | tnapi->hw_status->status = 0; | |
6275 | tnapi->hw_status->status_tag = 0; | |
6276 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
cf7a7298 | 6277 | |
f77a6a8e MC |
6278 | tnapi->tx_prod = 0; |
6279 | tnapi->tx_cons = 0; | |
0c1d0e2b MC |
6280 | if (tnapi->tx_ring) |
6281 | memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); | |
f77a6a8e MC |
6282 | |
6283 | tnapi->rx_rcb_ptr = 0; | |
0c1d0e2b MC |
6284 | if (tnapi->rx_rcb) |
6285 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); | |
2b2cdb65 | 6286 | |
e4af1af9 MC |
6287 | if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) { |
6288 | tg3_free_rings(tp); | |
2b2cdb65 | 6289 | return -ENOMEM; |
e4af1af9 | 6290 | } |
f77a6a8e | 6291 | } |
72334482 | 6292 | |
2b2cdb65 | 6293 | return 0; |
cf7a7298 MC |
6294 | } |
6295 | ||
6296 | /* | |
6297 | * Must not be invoked with interrupt sources disabled and | |
6298 | * the hardware shutdown down. | |
6299 | */ | |
6300 | static void tg3_free_consistent(struct tg3 *tp) | |
6301 | { | |
f77a6a8e | 6302 | int i; |
898a56f8 | 6303 | |
f77a6a8e MC |
6304 | for (i = 0; i < tp->irq_cnt; i++) { |
6305 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6306 | ||
6307 | if (tnapi->tx_ring) { | |
6308 | pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES, | |
6309 | tnapi->tx_ring, tnapi->tx_desc_mapping); | |
6310 | tnapi->tx_ring = NULL; | |
6311 | } | |
6312 | ||
6313 | kfree(tnapi->tx_buffers); | |
6314 | tnapi->tx_buffers = NULL; | |
6315 | ||
6316 | if (tnapi->rx_rcb) { | |
6317 | pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp), | |
6318 | tnapi->rx_rcb, | |
6319 | tnapi->rx_rcb_mapping); | |
6320 | tnapi->rx_rcb = NULL; | |
6321 | } | |
6322 | ||
6323 | if (tnapi->hw_status) { | |
6324 | pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE, | |
6325 | tnapi->hw_status, | |
6326 | tnapi->status_mapping); | |
6327 | tnapi->hw_status = NULL; | |
6328 | } | |
1da177e4 | 6329 | } |
f77a6a8e | 6330 | |
1da177e4 LT |
6331 | if (tp->hw_stats) { |
6332 | pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats), | |
6333 | tp->hw_stats, tp->stats_mapping); | |
6334 | tp->hw_stats = NULL; | |
6335 | } | |
f77a6a8e | 6336 | |
e4af1af9 | 6337 | for (i = 0; i < tp->irq_cnt; i++) |
2b2cdb65 | 6338 | tg3_rx_prodring_fini(tp, &tp->prodring[i]); |
1da177e4 LT |
6339 | } |
6340 | ||
6341 | /* | |
6342 | * Must not be invoked with interrupt sources disabled and | |
6343 | * the hardware shutdown down. Can sleep. | |
6344 | */ | |
6345 | static int tg3_alloc_consistent(struct tg3 *tp) | |
6346 | { | |
f77a6a8e | 6347 | int i; |
898a56f8 | 6348 | |
e4af1af9 | 6349 | for (i = 0; i < tp->irq_cnt; i++) { |
2b2cdb65 MC |
6350 | if (tg3_rx_prodring_init(tp, &tp->prodring[i])) |
6351 | goto err_out; | |
6352 | } | |
1da177e4 | 6353 | |
f77a6a8e MC |
6354 | tp->hw_stats = pci_alloc_consistent(tp->pdev, |
6355 | sizeof(struct tg3_hw_stats), | |
6356 | &tp->stats_mapping); | |
6357 | if (!tp->hw_stats) | |
1da177e4 LT |
6358 | goto err_out; |
6359 | ||
f77a6a8e | 6360 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); |
1da177e4 | 6361 | |
f77a6a8e MC |
6362 | for (i = 0; i < tp->irq_cnt; i++) { |
6363 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8d9d7cfc | 6364 | struct tg3_hw_status *sblk; |
1da177e4 | 6365 | |
f77a6a8e MC |
6366 | tnapi->hw_status = pci_alloc_consistent(tp->pdev, |
6367 | TG3_HW_STATUS_SIZE, | |
6368 | &tnapi->status_mapping); | |
6369 | if (!tnapi->hw_status) | |
6370 | goto err_out; | |
898a56f8 | 6371 | |
f77a6a8e | 6372 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); |
8d9d7cfc MC |
6373 | sblk = tnapi->hw_status; |
6374 | ||
19cfaecc MC |
6375 | /* If multivector TSS is enabled, vector 0 does not handle |
6376 | * tx interrupts. Don't allocate any resources for it. | |
6377 | */ | |
6378 | if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) || | |
6379 | (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) { | |
6380 | tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) * | |
6381 | TG3_TX_RING_SIZE, | |
6382 | GFP_KERNEL); | |
6383 | if (!tnapi->tx_buffers) | |
6384 | goto err_out; | |
6385 | ||
6386 | tnapi->tx_ring = pci_alloc_consistent(tp->pdev, | |
6387 | TG3_TX_RING_BYTES, | |
6388 | &tnapi->tx_desc_mapping); | |
6389 | if (!tnapi->tx_ring) | |
6390 | goto err_out; | |
6391 | } | |
6392 | ||
8d9d7cfc MC |
6393 | /* |
6394 | * When RSS is enabled, the status block format changes | |
6395 | * slightly. The "rx_jumbo_consumer", "reserved", | |
6396 | * and "rx_mini_consumer" members get mapped to the | |
6397 | * other three rx return ring producer indexes. | |
6398 | */ | |
6399 | switch (i) { | |
6400 | default: | |
6401 | tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; | |
6402 | break; | |
6403 | case 2: | |
6404 | tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer; | |
6405 | break; | |
6406 | case 3: | |
6407 | tnapi->rx_rcb_prod_idx = &sblk->reserved; | |
6408 | break; | |
6409 | case 4: | |
6410 | tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer; | |
6411 | break; | |
6412 | } | |
72334482 | 6413 | |
e4af1af9 | 6414 | tnapi->prodring = &tp->prodring[i]; |
b196c7e4 | 6415 | |
0c1d0e2b MC |
6416 | /* |
6417 | * If multivector RSS is enabled, vector 0 does not handle | |
6418 | * rx or tx interrupts. Don't allocate any resources for it. | |
6419 | */ | |
6420 | if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) | |
6421 | continue; | |
6422 | ||
f77a6a8e MC |
6423 | tnapi->rx_rcb = pci_alloc_consistent(tp->pdev, |
6424 | TG3_RX_RCB_RING_BYTES(tp), | |
6425 | &tnapi->rx_rcb_mapping); | |
6426 | if (!tnapi->rx_rcb) | |
6427 | goto err_out; | |
72334482 | 6428 | |
f77a6a8e | 6429 | memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); |
f77a6a8e | 6430 | } |
1da177e4 LT |
6431 | |
6432 | return 0; | |
6433 | ||
6434 | err_out: | |
6435 | tg3_free_consistent(tp); | |
6436 | return -ENOMEM; | |
6437 | } | |
6438 | ||
6439 | #define MAX_WAIT_CNT 1000 | |
6440 | ||
6441 | /* To stop a block, clear the enable bit and poll till it | |
6442 | * clears. tp->lock is held. | |
6443 | */ | |
b3b7d6be | 6444 | static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent) |
1da177e4 LT |
6445 | { |
6446 | unsigned int i; | |
6447 | u32 val; | |
6448 | ||
6449 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
6450 | switch (ofs) { | |
6451 | case RCVLSC_MODE: | |
6452 | case DMAC_MODE: | |
6453 | case MBFREE_MODE: | |
6454 | case BUFMGR_MODE: | |
6455 | case MEMARB_MODE: | |
6456 | /* We can't enable/disable these bits of the | |
6457 | * 5705/5750, just say success. | |
6458 | */ | |
6459 | return 0; | |
6460 | ||
6461 | default: | |
6462 | break; | |
855e1111 | 6463 | } |
1da177e4 LT |
6464 | } |
6465 | ||
6466 | val = tr32(ofs); | |
6467 | val &= ~enable_bit; | |
6468 | tw32_f(ofs, val); | |
6469 | ||
6470 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6471 | udelay(100); | |
6472 | val = tr32(ofs); | |
6473 | if ((val & enable_bit) == 0) | |
6474 | break; | |
6475 | } | |
6476 | ||
b3b7d6be | 6477 | if (i == MAX_WAIT_CNT && !silent) { |
2445e461 MC |
6478 | dev_err(&tp->pdev->dev, |
6479 | "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n", | |
6480 | ofs, enable_bit); | |
1da177e4 LT |
6481 | return -ENODEV; |
6482 | } | |
6483 | ||
6484 | return 0; | |
6485 | } | |
6486 | ||
6487 | /* tp->lock is held. */ | |
b3b7d6be | 6488 | static int tg3_abort_hw(struct tg3 *tp, int silent) |
1da177e4 LT |
6489 | { |
6490 | int i, err; | |
6491 | ||
6492 | tg3_disable_ints(tp); | |
6493 | ||
6494 | tp->rx_mode &= ~RX_MODE_ENABLE; | |
6495 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
6496 | udelay(10); | |
6497 | ||
b3b7d6be DM |
6498 | err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); |
6499 | err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); | |
6500 | err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); | |
6501 | err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); | |
6502 | err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); | |
6503 | err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); | |
6504 | ||
6505 | err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); | |
6506 | err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); | |
6507 | err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); | |
6508 | err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); | |
6509 | err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); | |
6510 | err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); | |
6511 | err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); | |
1da177e4 LT |
6512 | |
6513 | tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; | |
6514 | tw32_f(MAC_MODE, tp->mac_mode); | |
6515 | udelay(40); | |
6516 | ||
6517 | tp->tx_mode &= ~TX_MODE_ENABLE; | |
6518 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
6519 | ||
6520 | for (i = 0; i < MAX_WAIT_CNT; i++) { | |
6521 | udelay(100); | |
6522 | if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE)) | |
6523 | break; | |
6524 | } | |
6525 | if (i >= MAX_WAIT_CNT) { | |
ab96b241 MC |
6526 | dev_err(&tp->pdev->dev, |
6527 | "%s timed out, TX_MODE_ENABLE will not clear " | |
6528 | "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE)); | |
e6de8ad1 | 6529 | err |= -ENODEV; |
1da177e4 LT |
6530 | } |
6531 | ||
e6de8ad1 | 6532 | err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); |
b3b7d6be DM |
6533 | err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); |
6534 | err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); | |
1da177e4 LT |
6535 | |
6536 | tw32(FTQ_RESET, 0xffffffff); | |
6537 | tw32(FTQ_RESET, 0x00000000); | |
6538 | ||
b3b7d6be DM |
6539 | err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); |
6540 | err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); | |
1da177e4 | 6541 | |
f77a6a8e MC |
6542 | for (i = 0; i < tp->irq_cnt; i++) { |
6543 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6544 | if (tnapi->hw_status) | |
6545 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
6546 | } | |
1da177e4 LT |
6547 | if (tp->hw_stats) |
6548 | memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); | |
6549 | ||
1da177e4 LT |
6550 | return err; |
6551 | } | |
6552 | ||
0d3031d9 MC |
6553 | static void tg3_ape_send_event(struct tg3 *tp, u32 event) |
6554 | { | |
6555 | int i; | |
6556 | u32 apedata; | |
6557 | ||
6558 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
6559 | if (apedata != APE_SEG_SIG_MAGIC) | |
6560 | return; | |
6561 | ||
6562 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
731fd79c | 6563 | if (!(apedata & APE_FW_STATUS_READY)) |
0d3031d9 MC |
6564 | return; |
6565 | ||
6566 | /* Wait for up to 1 millisecond for APE to service previous event. */ | |
6567 | for (i = 0; i < 10; i++) { | |
6568 | if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) | |
6569 | return; | |
6570 | ||
6571 | apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); | |
6572 | ||
6573 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6574 | tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, | |
6575 | event | APE_EVENT_STATUS_EVENT_PENDING); | |
6576 | ||
6577 | tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); | |
6578 | ||
6579 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6580 | break; | |
6581 | ||
6582 | udelay(100); | |
6583 | } | |
6584 | ||
6585 | if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING)) | |
6586 | tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); | |
6587 | } | |
6588 | ||
6589 | static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) | |
6590 | { | |
6591 | u32 event; | |
6592 | u32 apedata; | |
6593 | ||
6594 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | |
6595 | return; | |
6596 | ||
6597 | switch (kind) { | |
33f401ae MC |
6598 | case RESET_KIND_INIT: |
6599 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, | |
6600 | APE_HOST_SEG_SIG_MAGIC); | |
6601 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, | |
6602 | APE_HOST_SEG_LEN_MAGIC); | |
6603 | apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); | |
6604 | tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); | |
6605 | tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, | |
6606 | APE_HOST_DRIVER_ID_MAGIC); | |
6607 | tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, | |
6608 | APE_HOST_BEHAV_NO_PHYLOCK); | |
6609 | ||
6610 | event = APE_EVENT_STATUS_STATE_START; | |
6611 | break; | |
6612 | case RESET_KIND_SHUTDOWN: | |
6613 | /* With the interface we are currently using, | |
6614 | * APE does not track driver state. Wiping | |
6615 | * out the HOST SEGMENT SIGNATURE forces | |
6616 | * the APE to assume OS absent status. | |
6617 | */ | |
6618 | tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0); | |
b2aee154 | 6619 | |
33f401ae MC |
6620 | event = APE_EVENT_STATUS_STATE_UNLOAD; |
6621 | break; | |
6622 | case RESET_KIND_SUSPEND: | |
6623 | event = APE_EVENT_STATUS_STATE_SUSPEND; | |
6624 | break; | |
6625 | default: | |
6626 | return; | |
0d3031d9 MC |
6627 | } |
6628 | ||
6629 | event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE; | |
6630 | ||
6631 | tg3_ape_send_event(tp, event); | |
6632 | } | |
6633 | ||
1da177e4 LT |
6634 | /* tp->lock is held. */ |
6635 | static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |
6636 | { | |
f49639e6 DM |
6637 | tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, |
6638 | NIC_SRAM_FIRMWARE_MBOX_MAGIC1); | |
1da177e4 LT |
6639 | |
6640 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6641 | switch (kind) { | |
6642 | case RESET_KIND_INIT: | |
6643 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6644 | DRV_STATE_START); | |
6645 | break; | |
6646 | ||
6647 | case RESET_KIND_SHUTDOWN: | |
6648 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6649 | DRV_STATE_UNLOAD); | |
6650 | break; | |
6651 | ||
6652 | case RESET_KIND_SUSPEND: | |
6653 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6654 | DRV_STATE_SUSPEND); | |
6655 | break; | |
6656 | ||
6657 | default: | |
6658 | break; | |
855e1111 | 6659 | } |
1da177e4 | 6660 | } |
0d3031d9 MC |
6661 | |
6662 | if (kind == RESET_KIND_INIT || | |
6663 | kind == RESET_KIND_SUSPEND) | |
6664 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6665 | } |
6666 | ||
6667 | /* tp->lock is held. */ | |
6668 | static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |
6669 | { | |
6670 | if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) { | |
6671 | switch (kind) { | |
6672 | case RESET_KIND_INIT: | |
6673 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6674 | DRV_STATE_START_DONE); | |
6675 | break; | |
6676 | ||
6677 | case RESET_KIND_SHUTDOWN: | |
6678 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6679 | DRV_STATE_UNLOAD_DONE); | |
6680 | break; | |
6681 | ||
6682 | default: | |
6683 | break; | |
855e1111 | 6684 | } |
1da177e4 | 6685 | } |
0d3031d9 MC |
6686 | |
6687 | if (kind == RESET_KIND_SHUTDOWN) | |
6688 | tg3_ape_driver_state_change(tp, kind); | |
1da177e4 LT |
6689 | } |
6690 | ||
6691 | /* tp->lock is held. */ | |
6692 | static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |
6693 | { | |
6694 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { | |
6695 | switch (kind) { | |
6696 | case RESET_KIND_INIT: | |
6697 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6698 | DRV_STATE_START); | |
6699 | break; | |
6700 | ||
6701 | case RESET_KIND_SHUTDOWN: | |
6702 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6703 | DRV_STATE_UNLOAD); | |
6704 | break; | |
6705 | ||
6706 | case RESET_KIND_SUSPEND: | |
6707 | tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, | |
6708 | DRV_STATE_SUSPEND); | |
6709 | break; | |
6710 | ||
6711 | default: | |
6712 | break; | |
855e1111 | 6713 | } |
1da177e4 LT |
6714 | } |
6715 | } | |
6716 | ||
7a6f4369 MC |
6717 | static int tg3_poll_fw(struct tg3 *tp) |
6718 | { | |
6719 | int i; | |
6720 | u32 val; | |
6721 | ||
b5d3772c | 6722 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
0ccead18 GZ |
6723 | /* Wait up to 20ms for init done. */ |
6724 | for (i = 0; i < 200; i++) { | |
b5d3772c MC |
6725 | if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE) |
6726 | return 0; | |
0ccead18 | 6727 | udelay(100); |
b5d3772c MC |
6728 | } |
6729 | return -ENODEV; | |
6730 | } | |
6731 | ||
7a6f4369 MC |
6732 | /* Wait for firmware initialization to complete. */ |
6733 | for (i = 0; i < 100000; i++) { | |
6734 | tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); | |
6735 | if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1) | |
6736 | break; | |
6737 | udelay(10); | |
6738 | } | |
6739 | ||
6740 | /* Chip might not be fitted with firmware. Some Sun onboard | |
6741 | * parts are configured like that. So don't signal the timeout | |
6742 | * of the above loop as an error, but do report the lack of | |
6743 | * running firmware once. | |
6744 | */ | |
6745 | if (i >= 100000 && | |
6746 | !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) { | |
6747 | tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED; | |
6748 | ||
05dbe005 | 6749 | netdev_info(tp->dev, "No firmware running\n"); |
7a6f4369 MC |
6750 | } |
6751 | ||
6b10c165 MC |
6752 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
6753 | /* The 57765 A0 needs a little more | |
6754 | * time to do some important work. | |
6755 | */ | |
6756 | mdelay(10); | |
6757 | } | |
6758 | ||
7a6f4369 MC |
6759 | return 0; |
6760 | } | |
6761 | ||
ee6a99b5 MC |
6762 | /* Save PCI command register before chip reset */ |
6763 | static void tg3_save_pci_state(struct tg3 *tp) | |
6764 | { | |
8a6eac90 | 6765 | pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); |
ee6a99b5 MC |
6766 | } |
6767 | ||
6768 | /* Restore PCI state after chip reset */ | |
6769 | static void tg3_restore_pci_state(struct tg3 *tp) | |
6770 | { | |
6771 | u32 val; | |
6772 | ||
6773 | /* Re-enable indirect register accesses. */ | |
6774 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
6775 | tp->misc_host_ctrl); | |
6776 | ||
6777 | /* Set MAX PCI retry to zero. */ | |
6778 | val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE); | |
6779 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
6780 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) | |
6781 | val |= PCISTATE_RETRY_SAME_DMA; | |
0d3031d9 MC |
6782 | /* Allow reads and writes to the APE register and memory space. */ |
6783 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
6784 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
6785 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
ee6a99b5 MC |
6786 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); |
6787 | ||
8a6eac90 | 6788 | pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); |
ee6a99b5 | 6789 | |
fcb389df MC |
6790 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) { |
6791 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) | |
6792 | pcie_set_readrq(tp->pdev, 4096); | |
6793 | else { | |
6794 | pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, | |
6795 | tp->pci_cacheline_sz); | |
6796 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
6797 | tp->pci_lat_timer); | |
6798 | } | |
114342f2 | 6799 | } |
5f5c51e3 | 6800 | |
ee6a99b5 | 6801 | /* Make sure PCI-X relaxed ordering bit is clear. */ |
52f4490c | 6802 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
9974a356 MC |
6803 | u16 pcix_cmd; |
6804 | ||
6805 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6806 | &pcix_cmd); | |
6807 | pcix_cmd &= ~PCI_X_CMD_ERO; | |
6808 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
6809 | pcix_cmd); | |
6810 | } | |
ee6a99b5 MC |
6811 | |
6812 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { | |
ee6a99b5 MC |
6813 | |
6814 | /* Chip reset on 5780 will reset MSI enable bit, | |
6815 | * so need to restore it. | |
6816 | */ | |
6817 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | |
6818 | u16 ctrl; | |
6819 | ||
6820 | pci_read_config_word(tp->pdev, | |
6821 | tp->msi_cap + PCI_MSI_FLAGS, | |
6822 | &ctrl); | |
6823 | pci_write_config_word(tp->pdev, | |
6824 | tp->msi_cap + PCI_MSI_FLAGS, | |
6825 | ctrl | PCI_MSI_FLAGS_ENABLE); | |
6826 | val = tr32(MSGINT_MODE); | |
6827 | tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE); | |
6828 | } | |
6829 | } | |
6830 | } | |
6831 | ||
1da177e4 LT |
6832 | static void tg3_stop_fw(struct tg3 *); |
6833 | ||
6834 | /* tp->lock is held. */ | |
6835 | static int tg3_chip_reset(struct tg3 *tp) | |
6836 | { | |
6837 | u32 val; | |
1ee582d8 | 6838 | void (*write_op)(struct tg3 *, u32, u32); |
4f125f42 | 6839 | int i, err; |
1da177e4 | 6840 | |
f49639e6 DM |
6841 | tg3_nvram_lock(tp); |
6842 | ||
77b483f1 MC |
6843 | tg3_ape_lock(tp, TG3_APE_LOCK_GRC); |
6844 | ||
f49639e6 DM |
6845 | /* No matching tg3_nvram_unlock() after this because |
6846 | * chip reset below will undo the nvram lock. | |
6847 | */ | |
6848 | tp->nvram_lock_cnt = 0; | |
1da177e4 | 6849 | |
ee6a99b5 MC |
6850 | /* GRC_MISC_CFG core clock reset will clear the memory |
6851 | * enable bit in PCI register 4 and the MSI enable bit | |
6852 | * on some chips, so we save relevant registers here. | |
6853 | */ | |
6854 | tg3_save_pci_state(tp); | |
6855 | ||
d9ab5ad1 | 6856 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || |
321d32a0 | 6857 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) |
d9ab5ad1 MC |
6858 | tw32(GRC_FASTBOOT_PC, 0); |
6859 | ||
1da177e4 LT |
6860 | /* |
6861 | * We must avoid the readl() that normally takes place. | |
6862 | * It locks machines, causes machine checks, and other | |
6863 | * fun things. So, temporarily disable the 5701 | |
6864 | * hardware workaround, while we do the reset. | |
6865 | */ | |
1ee582d8 MC |
6866 | write_op = tp->write32; |
6867 | if (write_op == tg3_write_flush_reg32) | |
6868 | tp->write32 = tg3_write32; | |
1da177e4 | 6869 | |
d18edcb2 MC |
6870 | /* Prevent the irq handler from reading or writing PCI registers |
6871 | * during chip reset when the memory enable bit in the PCI command | |
6872 | * register may be cleared. The chip does not generate interrupt | |
6873 | * at this time, but the irq handler may still be called due to irq | |
6874 | * sharing or irqpoll. | |
6875 | */ | |
6876 | tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING; | |
f77a6a8e MC |
6877 | for (i = 0; i < tp->irq_cnt; i++) { |
6878 | struct tg3_napi *tnapi = &tp->napi[i]; | |
6879 | if (tnapi->hw_status) { | |
6880 | tnapi->hw_status->status = 0; | |
6881 | tnapi->hw_status->status_tag = 0; | |
6882 | } | |
6883 | tnapi->last_tag = 0; | |
6884 | tnapi->last_irq_tag = 0; | |
b8fa2f3a | 6885 | } |
d18edcb2 | 6886 | smp_mb(); |
4f125f42 MC |
6887 | |
6888 | for (i = 0; i < tp->irq_cnt; i++) | |
6889 | synchronize_irq(tp->napi[i].irq_vec); | |
d18edcb2 | 6890 | |
255ca311 MC |
6891 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
6892 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; | |
6893 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
6894 | } | |
6895 | ||
1da177e4 LT |
6896 | /* do the reset */ |
6897 | val = GRC_MISC_CFG_CORECLK_RESET; | |
6898 | ||
6899 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
6900 | if (tr32(0x7e2c) == 0x60) { | |
6901 | tw32(0x7e2c, 0x20); | |
6902 | } | |
6903 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { | |
6904 | tw32(GRC_MISC_CFG, (1 << 29)); | |
6905 | val |= (1 << 29); | |
6906 | } | |
6907 | } | |
6908 | ||
b5d3772c MC |
6909 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
6910 | tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET); | |
6911 | tw32(GRC_VCPU_EXT_CTRL, | |
6912 | tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU); | |
6913 | } | |
6914 | ||
1da177e4 LT |
6915 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
6916 | val |= GRC_MISC_CFG_KEEP_GPHY_POWER; | |
6917 | tw32(GRC_MISC_CFG, val); | |
6918 | ||
1ee582d8 MC |
6919 | /* restore 5701 hardware bug workaround write method */ |
6920 | tp->write32 = write_op; | |
1da177e4 LT |
6921 | |
6922 | /* Unfortunately, we have to delay before the PCI read back. | |
6923 | * Some 575X chips even will not respond to a PCI cfg access | |
6924 | * when the reset command is given to the chip. | |
6925 | * | |
6926 | * How do these hardware designers expect things to work | |
6927 | * properly if the PCI write is posted for a long period | |
6928 | * of time? It is always necessary to have some method by | |
6929 | * which a register read back can occur to push the write | |
6930 | * out which does the reset. | |
6931 | * | |
6932 | * For most tg3 variants the trick below was working. | |
6933 | * Ho hum... | |
6934 | */ | |
6935 | udelay(120); | |
6936 | ||
6937 | /* Flush PCI posted writes. The normal MMIO registers | |
6938 | * are inaccessible at this time so this is the only | |
6939 | * way to make this reliably (actually, this is no longer | |
6940 | * the case, see above). I tried to use indirect | |
6941 | * register read/write but this upset some 5701 variants. | |
6942 | */ | |
6943 | pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); | |
6944 | ||
6945 | udelay(120); | |
6946 | ||
5e7dfd0f | 6947 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) { |
e7126997 MC |
6948 | u16 val16; |
6949 | ||
1da177e4 LT |
6950 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) { |
6951 | int i; | |
6952 | u32 cfg_val; | |
6953 | ||
6954 | /* Wait for link training to complete. */ | |
6955 | for (i = 0; i < 5000; i++) | |
6956 | udelay(100); | |
6957 | ||
6958 | pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); | |
6959 | pci_write_config_dword(tp->pdev, 0xc4, | |
6960 | cfg_val | (1 << 15)); | |
6961 | } | |
5e7dfd0f | 6962 | |
e7126997 MC |
6963 | /* Clear the "no snoop" and "relaxed ordering" bits. */ |
6964 | pci_read_config_word(tp->pdev, | |
6965 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
6966 | &val16); | |
6967 | val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN | | |
6968 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
6969 | /* | |
6970 | * Older PCIe devices only support the 128 byte | |
6971 | * MPS setting. Enforce the restriction. | |
5e7dfd0f | 6972 | */ |
e7126997 MC |
6973 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) || |
6974 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784)) | |
6975 | val16 &= ~PCI_EXP_DEVCTL_PAYLOAD; | |
5e7dfd0f MC |
6976 | pci_write_config_word(tp->pdev, |
6977 | tp->pcie_cap + PCI_EXP_DEVCTL, | |
e7126997 | 6978 | val16); |
5e7dfd0f MC |
6979 | |
6980 | pcie_set_readrq(tp->pdev, 4096); | |
6981 | ||
6982 | /* Clear error status */ | |
6983 | pci_write_config_word(tp->pdev, | |
6984 | tp->pcie_cap + PCI_EXP_DEVSTA, | |
6985 | PCI_EXP_DEVSTA_CED | | |
6986 | PCI_EXP_DEVSTA_NFED | | |
6987 | PCI_EXP_DEVSTA_FED | | |
6988 | PCI_EXP_DEVSTA_URD); | |
1da177e4 LT |
6989 | } |
6990 | ||
ee6a99b5 | 6991 | tg3_restore_pci_state(tp); |
1da177e4 | 6992 | |
d18edcb2 MC |
6993 | tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING; |
6994 | ||
ee6a99b5 MC |
6995 | val = 0; |
6996 | if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) | |
4cf78e4f | 6997 | val = tr32(MEMARB_MODE); |
ee6a99b5 | 6998 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); |
1da177e4 LT |
6999 | |
7000 | if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { | |
7001 | tg3_stop_fw(tp); | |
7002 | tw32(0x5000, 0x400); | |
7003 | } | |
7004 | ||
7005 | tw32(GRC_MODE, tp->grc_mode); | |
7006 | ||
7007 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { | |
ab0049b4 | 7008 | val = tr32(0xc4); |
1da177e4 LT |
7009 | |
7010 | tw32(0xc4, val | (1 << 15)); | |
7011 | } | |
7012 | ||
7013 | if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && | |
7014 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { | |
7015 | tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; | |
7016 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) | |
7017 | tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; | |
7018 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7019 | } | |
7020 | ||
7021 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
7022 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; | |
7023 | tw32_f(MAC_MODE, tp->mac_mode); | |
747e8f8b MC |
7024 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { |
7025 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; | |
7026 | tw32_f(MAC_MODE, tp->mac_mode); | |
3bda1258 MC |
7027 | } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
7028 | tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN); | |
7029 | if (tp->mac_mode & MAC_MODE_APE_TX_EN) | |
7030 | tp->mac_mode |= MAC_MODE_TDE_ENABLE; | |
7031 | tw32_f(MAC_MODE, tp->mac_mode); | |
1da177e4 LT |
7032 | } else |
7033 | tw32_f(MAC_MODE, 0); | |
7034 | udelay(40); | |
7035 | ||
77b483f1 MC |
7036 | tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); |
7037 | ||
7a6f4369 MC |
7038 | err = tg3_poll_fw(tp); |
7039 | if (err) | |
7040 | return err; | |
1da177e4 | 7041 | |
0a9140cf MC |
7042 | tg3_mdio_start(tp); |
7043 | ||
52cdf852 MC |
7044 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7045 | u8 phy_addr; | |
7046 | ||
7047 | phy_addr = tp->phy_addr; | |
7048 | tp->phy_addr = TG3_PHY_PCIE_ADDR; | |
7049 | ||
7050 | tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR, | |
7051 | TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT); | |
7052 | val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL | | |
7053 | TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL | | |
7054 | TG3_PCIEPHY_TX0CTRL1_NB_EN; | |
7055 | tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val); | |
7056 | udelay(10); | |
7057 | ||
7058 | tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR, | |
7059 | TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT); | |
7060 | val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN | | |
7061 | TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN; | |
7062 | tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val); | |
7063 | udelay(10); | |
7064 | ||
7065 | tp->phy_addr = phy_addr; | |
7066 | } | |
7067 | ||
1da177e4 | 7068 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
f6eb9b1f MC |
7069 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7070 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | |
b703df6f MC |
7071 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
7072 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) { | |
ab0049b4 | 7073 | val = tr32(0x7c00); |
1da177e4 LT |
7074 | |
7075 | tw32(0x7c00, val | (1 << 25)); | |
7076 | } | |
7077 | ||
7078 | /* Reprobe ASF enable state. */ | |
7079 | tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF; | |
7080 | tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE; | |
7081 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); | |
7082 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
7083 | u32 nic_cfg; | |
7084 | ||
7085 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
7086 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
7087 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
4ba526ce | 7088 | tp->last_event_jiffies = jiffies; |
cbf46853 | 7089 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
7090 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
7091 | } | |
7092 | } | |
7093 | ||
7094 | return 0; | |
7095 | } | |
7096 | ||
7097 | /* tp->lock is held. */ | |
7098 | static void tg3_stop_fw(struct tg3 *tp) | |
7099 | { | |
0d3031d9 MC |
7100 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
7101 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
7102 | /* Wait for RX cpu to ACK the previous event. */ |
7103 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7104 | |
7105 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); | |
4ba526ce MC |
7106 | |
7107 | tg3_generate_fw_event(tp); | |
1da177e4 | 7108 | |
7c5026aa MC |
7109 | /* Wait for RX cpu to ACK this event. */ |
7110 | tg3_wait_for_event_ack(tp); | |
1da177e4 LT |
7111 | } |
7112 | } | |
7113 | ||
7114 | /* tp->lock is held. */ | |
944d980e | 7115 | static int tg3_halt(struct tg3 *tp, int kind, int silent) |
1da177e4 LT |
7116 | { |
7117 | int err; | |
7118 | ||
7119 | tg3_stop_fw(tp); | |
7120 | ||
944d980e | 7121 | tg3_write_sig_pre_reset(tp, kind); |
1da177e4 | 7122 | |
b3b7d6be | 7123 | tg3_abort_hw(tp, silent); |
1da177e4 LT |
7124 | err = tg3_chip_reset(tp); |
7125 | ||
daba2a63 MC |
7126 | __tg3_set_mac_addr(tp, 0); |
7127 | ||
944d980e MC |
7128 | tg3_write_sig_legacy(tp, kind); |
7129 | tg3_write_sig_post_reset(tp, kind); | |
1da177e4 LT |
7130 | |
7131 | if (err) | |
7132 | return err; | |
7133 | ||
7134 | return 0; | |
7135 | } | |
7136 | ||
1da177e4 LT |
7137 | #define RX_CPU_SCRATCH_BASE 0x30000 |
7138 | #define RX_CPU_SCRATCH_SIZE 0x04000 | |
7139 | #define TX_CPU_SCRATCH_BASE 0x34000 | |
7140 | #define TX_CPU_SCRATCH_SIZE 0x04000 | |
7141 | ||
7142 | /* tp->lock is held. */ | |
7143 | static int tg3_halt_cpu(struct tg3 *tp, u32 offset) | |
7144 | { | |
7145 | int i; | |
7146 | ||
5d9428de ES |
7147 | BUG_ON(offset == TX_CPU_BASE && |
7148 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)); | |
1da177e4 | 7149 | |
b5d3772c MC |
7150 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7151 | u32 val = tr32(GRC_VCPU_EXT_CTRL); | |
7152 | ||
7153 | tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU); | |
7154 | return 0; | |
7155 | } | |
1da177e4 LT |
7156 | if (offset == RX_CPU_BASE) { |
7157 | for (i = 0; i < 10000; i++) { | |
7158 | tw32(offset + CPU_STATE, 0xffffffff); | |
7159 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7160 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7161 | break; | |
7162 | } | |
7163 | ||
7164 | tw32(offset + CPU_STATE, 0xffffffff); | |
7165 | tw32_f(offset + CPU_MODE, CPU_MODE_HALT); | |
7166 | udelay(10); | |
7167 | } else { | |
7168 | for (i = 0; i < 10000; i++) { | |
7169 | tw32(offset + CPU_STATE, 0xffffffff); | |
7170 | tw32(offset + CPU_MODE, CPU_MODE_HALT); | |
7171 | if (tr32(offset + CPU_MODE) & CPU_MODE_HALT) | |
7172 | break; | |
7173 | } | |
7174 | } | |
7175 | ||
7176 | if (i >= 10000) { | |
05dbe005 JP |
7177 | netdev_err(tp->dev, "%s timed out, %s CPU\n", |
7178 | __func__, offset == RX_CPU_BASE ? "RX" : "TX"); | |
1da177e4 LT |
7179 | return -ENODEV; |
7180 | } | |
ec41c7df MC |
7181 | |
7182 | /* Clear firmware's nvram arbitration. */ | |
7183 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
7184 | tw32(NVRAM_SWARB, SWARB_REQ_CLR0); | |
1da177e4 LT |
7185 | return 0; |
7186 | } | |
7187 | ||
7188 | struct fw_info { | |
077f849d JSR |
7189 | unsigned int fw_base; |
7190 | unsigned int fw_len; | |
7191 | const __be32 *fw_data; | |
1da177e4 LT |
7192 | }; |
7193 | ||
7194 | /* tp->lock is held. */ | |
7195 | static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base, | |
7196 | int cpu_scratch_size, struct fw_info *info) | |
7197 | { | |
ec41c7df | 7198 | int err, lock_err, i; |
1da177e4 LT |
7199 | void (*write_op)(struct tg3 *, u32, u32); |
7200 | ||
7201 | if (cpu_base == TX_CPU_BASE && | |
7202 | (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
5129c3a3 MC |
7203 | netdev_err(tp->dev, |
7204 | "%s: Trying to load TX cpu firmware which is 5705\n", | |
05dbe005 | 7205 | __func__); |
1da177e4 LT |
7206 | return -EINVAL; |
7207 | } | |
7208 | ||
7209 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
7210 | write_op = tg3_write_mem; | |
7211 | else | |
7212 | write_op = tg3_write_indirect_reg32; | |
7213 | ||
1b628151 MC |
7214 | /* It is possible that bootcode is still loading at this point. |
7215 | * Get the nvram lock first before halting the cpu. | |
7216 | */ | |
ec41c7df | 7217 | lock_err = tg3_nvram_lock(tp); |
1da177e4 | 7218 | err = tg3_halt_cpu(tp, cpu_base); |
ec41c7df MC |
7219 | if (!lock_err) |
7220 | tg3_nvram_unlock(tp); | |
1da177e4 LT |
7221 | if (err) |
7222 | goto out; | |
7223 | ||
7224 | for (i = 0; i < cpu_scratch_size; i += sizeof(u32)) | |
7225 | write_op(tp, cpu_scratch_base + i, 0); | |
7226 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7227 | tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT); | |
077f849d | 7228 | for (i = 0; i < (info->fw_len / sizeof(u32)); i++) |
1da177e4 | 7229 | write_op(tp, (cpu_scratch_base + |
077f849d | 7230 | (info->fw_base & 0xffff) + |
1da177e4 | 7231 | (i * sizeof(u32))), |
077f849d | 7232 | be32_to_cpu(info->fw_data[i])); |
1da177e4 LT |
7233 | |
7234 | err = 0; | |
7235 | ||
7236 | out: | |
1da177e4 LT |
7237 | return err; |
7238 | } | |
7239 | ||
7240 | /* tp->lock is held. */ | |
7241 | static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) | |
7242 | { | |
7243 | struct fw_info info; | |
077f849d | 7244 | const __be32 *fw_data; |
1da177e4 LT |
7245 | int err, i; |
7246 | ||
077f849d JSR |
7247 | fw_data = (void *)tp->fw->data; |
7248 | ||
7249 | /* Firmware blob starts with version numbers, followed by | |
7250 | start address and length. We are setting complete length. | |
7251 | length = end_address_of_bss - start_address_of_text. | |
7252 | Remainder is the blob to be loaded contiguously | |
7253 | from start address. */ | |
7254 | ||
7255 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7256 | info.fw_len = tp->fw->size - 12; | |
7257 | info.fw_data = &fw_data[3]; | |
1da177e4 LT |
7258 | |
7259 | err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, | |
7260 | RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE, | |
7261 | &info); | |
7262 | if (err) | |
7263 | return err; | |
7264 | ||
7265 | err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, | |
7266 | TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE, | |
7267 | &info); | |
7268 | if (err) | |
7269 | return err; | |
7270 | ||
7271 | /* Now startup only the RX cpu. */ | |
7272 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
077f849d | 7273 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7274 | |
7275 | for (i = 0; i < 5; i++) { | |
077f849d | 7276 | if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base) |
1da177e4 LT |
7277 | break; |
7278 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7279 | tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7280 | tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base); |
1da177e4 LT |
7281 | udelay(1000); |
7282 | } | |
7283 | if (i >= 5) { | |
5129c3a3 MC |
7284 | netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " |
7285 | "should be %08x\n", __func__, | |
05dbe005 | 7286 | tr32(RX_CPU_BASE + CPU_PC), info.fw_base); |
1da177e4 LT |
7287 | return -ENODEV; |
7288 | } | |
7289 | tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff); | |
7290 | tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000); | |
7291 | ||
7292 | return 0; | |
7293 | } | |
7294 | ||
1da177e4 | 7295 | /* 5705 needs a special version of the TSO firmware. */ |
1da177e4 LT |
7296 | |
7297 | /* tp->lock is held. */ | |
7298 | static int tg3_load_tso_firmware(struct tg3 *tp) | |
7299 | { | |
7300 | struct fw_info info; | |
077f849d | 7301 | const __be32 *fw_data; |
1da177e4 LT |
7302 | unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size; |
7303 | int err, i; | |
7304 | ||
7305 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) | |
7306 | return 0; | |
7307 | ||
077f849d JSR |
7308 | fw_data = (void *)tp->fw->data; |
7309 | ||
7310 | /* Firmware blob starts with version numbers, followed by | |
7311 | start address and length. We are setting complete length. | |
7312 | length = end_address_of_bss - start_address_of_text. | |
7313 | Remainder is the blob to be loaded contiguously | |
7314 | from start address. */ | |
7315 | ||
7316 | info.fw_base = be32_to_cpu(fw_data[1]); | |
7317 | cpu_scratch_size = tp->fw_len; | |
7318 | info.fw_len = tp->fw->size - 12; | |
7319 | info.fw_data = &fw_data[3]; | |
7320 | ||
1da177e4 | 7321 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7322 | cpu_base = RX_CPU_BASE; |
7323 | cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705; | |
1da177e4 | 7324 | } else { |
1da177e4 LT |
7325 | cpu_base = TX_CPU_BASE; |
7326 | cpu_scratch_base = TX_CPU_SCRATCH_BASE; | |
7327 | cpu_scratch_size = TX_CPU_SCRATCH_SIZE; | |
7328 | } | |
7329 | ||
7330 | err = tg3_load_firmware_cpu(tp, cpu_base, | |
7331 | cpu_scratch_base, cpu_scratch_size, | |
7332 | &info); | |
7333 | if (err) | |
7334 | return err; | |
7335 | ||
7336 | /* Now startup the cpu. */ | |
7337 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
077f849d | 7338 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7339 | |
7340 | for (i = 0; i < 5; i++) { | |
077f849d | 7341 | if (tr32(cpu_base + CPU_PC) == info.fw_base) |
1da177e4 LT |
7342 | break; |
7343 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7344 | tw32(cpu_base + CPU_MODE, CPU_MODE_HALT); | |
077f849d | 7345 | tw32_f(cpu_base + CPU_PC, info.fw_base); |
1da177e4 LT |
7346 | udelay(1000); |
7347 | } | |
7348 | if (i >= 5) { | |
5129c3a3 MC |
7349 | netdev_err(tp->dev, |
7350 | "%s fails to set CPU PC, is %08x should be %08x\n", | |
05dbe005 | 7351 | __func__, tr32(cpu_base + CPU_PC), info.fw_base); |
1da177e4 LT |
7352 | return -ENODEV; |
7353 | } | |
7354 | tw32(cpu_base + CPU_STATE, 0xffffffff); | |
7355 | tw32_f(cpu_base + CPU_MODE, 0x00000000); | |
7356 | return 0; | |
7357 | } | |
7358 | ||
1da177e4 | 7359 | |
1da177e4 LT |
7360 | static int tg3_set_mac_addr(struct net_device *dev, void *p) |
7361 | { | |
7362 | struct tg3 *tp = netdev_priv(dev); | |
7363 | struct sockaddr *addr = p; | |
986e0aeb | 7364 | int err = 0, skip_mac_1 = 0; |
1da177e4 | 7365 | |
f9804ddb MC |
7366 | if (!is_valid_ether_addr(addr->sa_data)) |
7367 | return -EINVAL; | |
7368 | ||
1da177e4 LT |
7369 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
7370 | ||
e75f7c90 MC |
7371 | if (!netif_running(dev)) |
7372 | return 0; | |
7373 | ||
58712ef9 | 7374 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) { |
986e0aeb | 7375 | u32 addr0_high, addr0_low, addr1_high, addr1_low; |
58712ef9 | 7376 | |
986e0aeb MC |
7377 | addr0_high = tr32(MAC_ADDR_0_HIGH); |
7378 | addr0_low = tr32(MAC_ADDR_0_LOW); | |
7379 | addr1_high = tr32(MAC_ADDR_1_HIGH); | |
7380 | addr1_low = tr32(MAC_ADDR_1_LOW); | |
7381 | ||
7382 | /* Skip MAC addr 1 if ASF is using it. */ | |
7383 | if ((addr0_high != addr1_high || addr0_low != addr1_low) && | |
7384 | !(addr1_high == 0 && addr1_low == 0)) | |
7385 | skip_mac_1 = 1; | |
58712ef9 | 7386 | } |
986e0aeb MC |
7387 | spin_lock_bh(&tp->lock); |
7388 | __tg3_set_mac_addr(tp, skip_mac_1); | |
7389 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 7390 | |
b9ec6c1b | 7391 | return err; |
1da177e4 LT |
7392 | } |
7393 | ||
7394 | /* tp->lock is held. */ | |
7395 | static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, | |
7396 | dma_addr_t mapping, u32 maxlen_flags, | |
7397 | u32 nic_addr) | |
7398 | { | |
7399 | tg3_write_mem(tp, | |
7400 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH), | |
7401 | ((u64) mapping >> 32)); | |
7402 | tg3_write_mem(tp, | |
7403 | (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW), | |
7404 | ((u64) mapping & 0xffffffff)); | |
7405 | tg3_write_mem(tp, | |
7406 | (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS), | |
7407 | maxlen_flags); | |
7408 | ||
7409 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7410 | tg3_write_mem(tp, | |
7411 | (bdinfo_addr + TG3_BDINFO_NIC_ADDR), | |
7412 | nic_addr); | |
7413 | } | |
7414 | ||
7415 | static void __tg3_set_rx_mode(struct net_device *); | |
d244c892 | 7416 | static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) |
15f9850d | 7417 | { |
b6080e12 MC |
7418 | int i; |
7419 | ||
19cfaecc | 7420 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) { |
b6080e12 MC |
7421 | tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); |
7422 | tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); | |
7423 | tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); | |
b6080e12 MC |
7424 | } else { |
7425 | tw32(HOSTCC_TXCOL_TICKS, 0); | |
7426 | tw32(HOSTCC_TXMAX_FRAMES, 0); | |
7427 | tw32(HOSTCC_TXCOAL_MAXF_INT, 0); | |
19cfaecc | 7428 | } |
b6080e12 | 7429 | |
19cfaecc MC |
7430 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { |
7431 | tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); | |
7432 | tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); | |
7433 | tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); | |
7434 | } else { | |
b6080e12 MC |
7435 | tw32(HOSTCC_RXCOL_TICKS, 0); |
7436 | tw32(HOSTCC_RXMAX_FRAMES, 0); | |
7437 | tw32(HOSTCC_RXCOAL_MAXF_INT, 0); | |
15f9850d | 7438 | } |
b6080e12 | 7439 | |
15f9850d DM |
7440 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
7441 | u32 val = ec->stats_block_coalesce_usecs; | |
7442 | ||
b6080e12 MC |
7443 | tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); |
7444 | tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); | |
7445 | ||
15f9850d DM |
7446 | if (!netif_carrier_ok(tp->dev)) |
7447 | val = 0; | |
7448 | ||
7449 | tw32(HOSTCC_STAT_COAL_TICKS, val); | |
7450 | } | |
b6080e12 MC |
7451 | |
7452 | for (i = 0; i < tp->irq_cnt - 1; i++) { | |
7453 | u32 reg; | |
7454 | ||
7455 | reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18; | |
7456 | tw32(reg, ec->rx_coalesce_usecs); | |
b6080e12 MC |
7457 | reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18; |
7458 | tw32(reg, ec->rx_max_coalesced_frames); | |
b6080e12 MC |
7459 | reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18; |
7460 | tw32(reg, ec->rx_max_coalesced_frames_irq); | |
19cfaecc MC |
7461 | |
7462 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7463 | reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18; | |
7464 | tw32(reg, ec->tx_coalesce_usecs); | |
7465 | reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18; | |
7466 | tw32(reg, ec->tx_max_coalesced_frames); | |
7467 | reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18; | |
7468 | tw32(reg, ec->tx_max_coalesced_frames_irq); | |
7469 | } | |
b6080e12 MC |
7470 | } |
7471 | ||
7472 | for (; i < tp->irq_max - 1; i++) { | |
7473 | tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0); | |
b6080e12 | 7474 | tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0); |
b6080e12 | 7475 | tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); |
19cfaecc MC |
7476 | |
7477 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) { | |
7478 | tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0); | |
7479 | tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0); | |
7480 | tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0); | |
7481 | } | |
b6080e12 | 7482 | } |
15f9850d | 7483 | } |
1da177e4 | 7484 | |
2d31ecaf MC |
7485 | /* tp->lock is held. */ |
7486 | static void tg3_rings_reset(struct tg3 *tp) | |
7487 | { | |
7488 | int i; | |
f77a6a8e | 7489 | u32 stblk, txrcb, rxrcb, limit; |
2d31ecaf MC |
7490 | struct tg3_napi *tnapi = &tp->napi[0]; |
7491 | ||
7492 | /* Disable all transmit rings but the first. */ | |
7493 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
7494 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; | |
b703df6f MC |
7495 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
7496 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; | |
2d31ecaf MC |
7497 | else |
7498 | limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7499 | ||
7500 | for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; | |
7501 | txrcb < limit; txrcb += TG3_BDINFO_SIZE) | |
7502 | tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7503 | BDINFO_FLAGS_DISABLED); | |
7504 | ||
7505 | ||
7506 | /* Disable all receive return rings but the first. */ | |
f6eb9b1f MC |
7507 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
7508 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; | |
7509 | else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
2d31ecaf | 7510 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; |
b703df6f MC |
7511 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
7512 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
2d31ecaf MC |
7513 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; |
7514 | else | |
7515 | limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7516 | ||
7517 | for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; | |
7518 | rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) | |
7519 | tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, | |
7520 | BDINFO_FLAGS_DISABLED); | |
7521 | ||
7522 | /* Disable interrupts */ | |
7523 | tw32_mailbox_f(tp->napi[0].int_mbox, 1); | |
7524 | ||
7525 | /* Zero mailbox registers. */ | |
f77a6a8e MC |
7526 | if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) { |
7527 | for (i = 1; i < TG3_IRQ_MAX_VECS; i++) { | |
7528 | tp->napi[i].tx_prod = 0; | |
7529 | tp->napi[i].tx_cons = 0; | |
c2353a32 MC |
7530 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
7531 | tw32_mailbox(tp->napi[i].prodmbox, 0); | |
f77a6a8e MC |
7532 | tw32_rx_mbox(tp->napi[i].consmbox, 0); |
7533 | tw32_mailbox_f(tp->napi[i].int_mbox, 1); | |
7534 | } | |
c2353a32 MC |
7535 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) |
7536 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
f77a6a8e MC |
7537 | } else { |
7538 | tp->napi[0].tx_prod = 0; | |
7539 | tp->napi[0].tx_cons = 0; | |
7540 | tw32_mailbox(tp->napi[0].prodmbox, 0); | |
7541 | tw32_rx_mbox(tp->napi[0].consmbox, 0); | |
7542 | } | |
2d31ecaf MC |
7543 | |
7544 | /* Make sure the NIC-based send BD rings are disabled. */ | |
7545 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
7546 | u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
7547 | for (i = 0; i < 16; i++) | |
7548 | tw32_tx_mbox(mbox + i * 8, 0); | |
7549 | } | |
7550 | ||
7551 | txrcb = NIC_SRAM_SEND_RCB; | |
7552 | rxrcb = NIC_SRAM_RCV_RET_RCB; | |
7553 | ||
7554 | /* Clear status block in ram. */ | |
7555 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7556 | ||
7557 | /* Set status block DMA address */ | |
7558 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
7559 | ((u64) tnapi->status_mapping >> 32)); | |
7560 | tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
7561 | ((u64) tnapi->status_mapping & 0xffffffff)); | |
7562 | ||
f77a6a8e MC |
7563 | if (tnapi->tx_ring) { |
7564 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7565 | (TG3_TX_RING_SIZE << | |
7566 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7567 | NIC_SRAM_TX_BUFFER_DESC); | |
7568 | txrcb += TG3_BDINFO_SIZE; | |
7569 | } | |
7570 | ||
7571 | if (tnapi->rx_rcb) { | |
7572 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7573 | (TG3_RX_RCB_RING_SIZE(tp) << | |
7574 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); | |
7575 | rxrcb += TG3_BDINFO_SIZE; | |
7576 | } | |
7577 | ||
7578 | stblk = HOSTCC_STATBLCK_RING1; | |
2d31ecaf | 7579 | |
f77a6a8e MC |
7580 | for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { |
7581 | u64 mapping = (u64)tnapi->status_mapping; | |
7582 | tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32); | |
7583 | tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff); | |
7584 | ||
7585 | /* Clear status block in ram. */ | |
7586 | memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); | |
7587 | ||
19cfaecc MC |
7588 | if (tnapi->tx_ring) { |
7589 | tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, | |
7590 | (TG3_TX_RING_SIZE << | |
7591 | BDINFO_FLAGS_MAXLEN_SHIFT), | |
7592 | NIC_SRAM_TX_BUFFER_DESC); | |
7593 | txrcb += TG3_BDINFO_SIZE; | |
7594 | } | |
f77a6a8e MC |
7595 | |
7596 | tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, | |
7597 | (TG3_RX_RCB_RING_SIZE(tp) << | |
7598 | BDINFO_FLAGS_MAXLEN_SHIFT), 0); | |
7599 | ||
7600 | stblk += 8; | |
f77a6a8e MC |
7601 | rxrcb += TG3_BDINFO_SIZE; |
7602 | } | |
2d31ecaf MC |
7603 | } |
7604 | ||
1da177e4 | 7605 | /* tp->lock is held. */ |
8e7a22e3 | 7606 | static int tg3_reset_hw(struct tg3 *tp, int reset_phy) |
1da177e4 LT |
7607 | { |
7608 | u32 val, rdmac_mode; | |
7609 | int i, err, limit; | |
21f581a5 | 7610 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
1da177e4 LT |
7611 | |
7612 | tg3_disable_ints(tp); | |
7613 | ||
7614 | tg3_stop_fw(tp); | |
7615 | ||
7616 | tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); | |
7617 | ||
859a5887 | 7618 | if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) |
e6de8ad1 | 7619 | tg3_abort_hw(tp, 1); |
1da177e4 | 7620 | |
603f1173 | 7621 | if (reset_phy) |
d4d2c558 MC |
7622 | tg3_phy_reset(tp); |
7623 | ||
1da177e4 LT |
7624 | err = tg3_chip_reset(tp); |
7625 | if (err) | |
7626 | return err; | |
7627 | ||
7628 | tg3_write_sig_legacy(tp, RESET_KIND_INIT); | |
7629 | ||
bcb37f6c | 7630 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) { |
d30cdd28 MC |
7631 | val = tr32(TG3_CPMU_CTRL); |
7632 | val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE); | |
7633 | tw32(TG3_CPMU_CTRL, val); | |
9acb961e MC |
7634 | |
7635 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7636 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7637 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7638 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
7639 | ||
7640 | val = tr32(TG3_CPMU_LNK_AWARE_PWRMD); | |
7641 | val &= ~CPMU_LNK_AWARE_MACCLK_MASK; | |
7642 | val |= CPMU_LNK_AWARE_MACCLK_6_25; | |
7643 | tw32(TG3_CPMU_LNK_AWARE_PWRMD, val); | |
7644 | ||
7645 | val = tr32(TG3_CPMU_HST_ACC); | |
7646 | val &= ~CPMU_HST_ACC_MACCLK_MASK; | |
7647 | val |= CPMU_HST_ACC_MACCLK_6_25; | |
7648 | tw32(TG3_CPMU_HST_ACC, val); | |
d30cdd28 MC |
7649 | } |
7650 | ||
33466d93 MC |
7651 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { |
7652 | val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; | |
7653 | val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | | |
7654 | PCIE_PWR_MGMT_L1_THRESH_4MS; | |
7655 | tw32(PCIE_PWR_MGMT_THRESH, val); | |
521e6b90 MC |
7656 | |
7657 | val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK; | |
7658 | tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); | |
7659 | ||
7660 | tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); | |
33466d93 | 7661 | |
f40386c8 MC |
7662 | val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN; |
7663 | tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS); | |
255ca311 MC |
7664 | } |
7665 | ||
614b0590 MC |
7666 | if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) { |
7667 | u32 grc_mode = tr32(GRC_MODE); | |
7668 | ||
7669 | /* Access the lower 1K of PL PCIE block registers. */ | |
7670 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7671 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
7672 | ||
7673 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1); | |
7674 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1, | |
7675 | val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN); | |
7676 | ||
7677 | tw32(GRC_MODE, grc_mode); | |
7678 | } | |
7679 | ||
cea46462 MC |
7680 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
7681 | u32 grc_mode = tr32(GRC_MODE); | |
7682 | ||
7683 | /* Access the lower 1K of PL PCIE block registers. */ | |
7684 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | |
7685 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | |
7686 | ||
7687 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5); | |
7688 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | |
7689 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | |
7690 | ||
7691 | tw32(GRC_MODE, grc_mode); | |
a977dbe8 MC |
7692 | |
7693 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | |
7694 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | |
7695 | val |= CPMU_LSPD_10MB_MACCLK_6_25; | |
7696 | tw32(TG3_CPMU_LSPD_10MB_CLK, val); | |
cea46462 MC |
7697 | } |
7698 | ||
1da177e4 LT |
7699 | /* This works around an issue with Athlon chipsets on |
7700 | * B3 tigon3 silicon. This bit has no effect on any | |
7701 | * other revision. But do not set this on PCI Express | |
795d01c5 | 7702 | * chips and don't even touch the clocks if the CPMU is present. |
1da177e4 | 7703 | */ |
795d01c5 MC |
7704 | if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) { |
7705 | if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
7706 | tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; | |
7707 | tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | |
7708 | } | |
1da177e4 LT |
7709 | |
7710 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 && | |
7711 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
7712 | val = tr32(TG3PCI_PCISTATE); | |
7713 | val |= PCISTATE_RETRY_SAME_DMA; | |
7714 | tw32(TG3PCI_PCISTATE, val); | |
7715 | } | |
7716 | ||
0d3031d9 MC |
7717 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
7718 | /* Allow reads and writes to the | |
7719 | * APE register and memory space. | |
7720 | */ | |
7721 | val = tr32(TG3PCI_PCISTATE); | |
7722 | val |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
7723 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
7724 | tw32(TG3PCI_PCISTATE, val); | |
7725 | } | |
7726 | ||
1da177e4 LT |
7727 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) { |
7728 | /* Enable some hw fixes. */ | |
7729 | val = tr32(TG3PCI_MSI_DATA); | |
7730 | val |= (1 << 26) | (1 << 28) | (1 << 29); | |
7731 | tw32(TG3PCI_MSI_DATA, val); | |
7732 | } | |
7733 | ||
7734 | /* Descriptor ring init may make accesses to the | |
7735 | * NIC SRAM area to setup the TX descriptors, so we | |
7736 | * can only do this after the hardware has been | |
7737 | * successfully reset. | |
7738 | */ | |
32d8c572 MC |
7739 | err = tg3_init_rings(tp); |
7740 | if (err) | |
7741 | return err; | |
1da177e4 | 7742 | |
b703df6f MC |
7743 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
7744 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
cbf9ca6c MC |
7745 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
7746 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | |
1a319025 MC |
7747 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
7748 | val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK; | |
cbf9ca6c MC |
7749 | tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); |
7750 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | |
7751 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) { | |
d30cdd28 MC |
7752 | /* This value is determined during the probe time DMA |
7753 | * engine test, tg3_test_dma. | |
7754 | */ | |
7755 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
7756 | } | |
1da177e4 LT |
7757 | |
7758 | tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | | |
7759 | GRC_MODE_4X_NIC_SEND_RINGS | | |
7760 | GRC_MODE_NO_TX_PHDR_CSUM | | |
7761 | GRC_MODE_NO_RX_PHDR_CSUM); | |
7762 | tp->grc_mode |= GRC_MODE_HOST_SENDBDS; | |
d2d746f8 MC |
7763 | |
7764 | /* Pseudo-header checksum is done by hardware logic and not | |
7765 | * the offload processers, so make the chip do the pseudo- | |
7766 | * header checksums on receive. For transmit it is more | |
7767 | * convenient to do the pseudo-header checksum in software | |
7768 | * as Linux does that on transmit for us in all cases. | |
7769 | */ | |
7770 | tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; | |
1da177e4 LT |
7771 | |
7772 | tw32(GRC_MODE, | |
7773 | tp->grc_mode | | |
7774 | (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP)); | |
7775 | ||
7776 | /* Setup the timer prescalar register. Clock is always 66Mhz. */ | |
7777 | val = tr32(GRC_MISC_CFG); | |
7778 | val &= ~0xff; | |
7779 | val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT); | |
7780 | tw32(GRC_MISC_CFG, val); | |
7781 | ||
7782 | /* Initialize MBUF/DESC pool. */ | |
cbf46853 | 7783 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
1da177e4 LT |
7784 | /* Do nothing. */ |
7785 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { | |
7786 | tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); | |
7787 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
7788 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64); | |
7789 | else | |
7790 | tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96); | |
7791 | tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE); | |
7792 | tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE); | |
859a5887 | 7793 | } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
1da177e4 LT |
7794 | int fw_len; |
7795 | ||
077f849d | 7796 | fw_len = tp->fw_len; |
1da177e4 LT |
7797 | fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); |
7798 | tw32(BUFMGR_MB_POOL_ADDR, | |
7799 | NIC_SRAM_MBUF_POOL_BASE5705 + fw_len); | |
7800 | tw32(BUFMGR_MB_POOL_SIZE, | |
7801 | NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); | |
7802 | } | |
1da177e4 | 7803 | |
0f893dc6 | 7804 | if (tp->dev->mtu <= ETH_DATA_LEN) { |
1da177e4 LT |
7805 | tw32(BUFMGR_MB_RDMA_LOW_WATER, |
7806 | tp->bufmgr_config.mbuf_read_dma_low_water); | |
7807 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
7808 | tp->bufmgr_config.mbuf_mac_rx_low_water); | |
7809 | tw32(BUFMGR_MB_HIGH_WATER, | |
7810 | tp->bufmgr_config.mbuf_high_water); | |
7811 | } else { | |
7812 | tw32(BUFMGR_MB_RDMA_LOW_WATER, | |
7813 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); | |
7814 | tw32(BUFMGR_MB_MACRX_LOW_WATER, | |
7815 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); | |
7816 | tw32(BUFMGR_MB_HIGH_WATER, | |
7817 | tp->bufmgr_config.mbuf_high_water_jumbo); | |
7818 | } | |
7819 | tw32(BUFMGR_DMA_LOW_WATER, | |
7820 | tp->bufmgr_config.dma_low_water); | |
7821 | tw32(BUFMGR_DMA_HIGH_WATER, | |
7822 | tp->bufmgr_config.dma_high_water); | |
7823 | ||
7824 | tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); | |
7825 | for (i = 0; i < 2000; i++) { | |
7826 | if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) | |
7827 | break; | |
7828 | udelay(10); | |
7829 | } | |
7830 | if (i >= 2000) { | |
05dbe005 | 7831 | netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); |
1da177e4 LT |
7832 | return -ENODEV; |
7833 | } | |
7834 | ||
7835 | /* Setup replenish threshold. */ | |
f92905de MC |
7836 | val = tp->rx_pending / 8; |
7837 | if (val == 0) | |
7838 | val = 1; | |
7839 | else if (val > tp->rx_std_max_post) | |
7840 | val = tp->rx_std_max_post; | |
b5d3772c MC |
7841 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
7842 | if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1) | |
7843 | tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2); | |
7844 | ||
7845 | if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2)) | |
7846 | val = TG3_RX_INTERNAL_RING_SZ_5906 / 2; | |
7847 | } | |
f92905de MC |
7848 | |
7849 | tw32(RCVBDI_STD_THRESH, val); | |
1da177e4 LT |
7850 | |
7851 | /* Initialize TG3_BDINFO's at: | |
7852 | * RCVDBDI_STD_BD: standard eth size rx ring | |
7853 | * RCVDBDI_JUMBO_BD: jumbo frame rx ring | |
7854 | * RCVDBDI_MINI_BD: small frame rx ring (??? does not work) | |
7855 | * | |
7856 | * like so: | |
7857 | * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring | |
7858 | * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) | | |
7859 | * ring attribute flags | |
7860 | * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM | |
7861 | * | |
7862 | * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries. | |
7863 | * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries. | |
7864 | * | |
7865 | * The size of each ring is fixed in the firmware, but the location is | |
7866 | * configurable. | |
7867 | */ | |
7868 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, | |
21f581a5 | 7869 | ((u64) tpr->rx_std_mapping >> 32)); |
1da177e4 | 7870 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 7871 | ((u64) tpr->rx_std_mapping & 0xffffffff)); |
13fa95b0 | 7872 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) |
87668d35 MC |
7873 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, |
7874 | NIC_SRAM_RX_BUFFER_DESC); | |
1da177e4 | 7875 | |
fdb72b38 MC |
7876 | /* Disable the mini ring */ |
7877 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
1da177e4 LT |
7878 | tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS, |
7879 | BDINFO_FLAGS_DISABLED); | |
7880 | ||
fdb72b38 MC |
7881 | /* Program the jumbo buffer descriptor ring control |
7882 | * blocks on those devices that have them. | |
7883 | */ | |
8f666b07 | 7884 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
fdb72b38 | 7885 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
7886 | /* Setup replenish threshold. */ |
7887 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); | |
7888 | ||
0f893dc6 | 7889 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) { |
1da177e4 | 7890 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, |
21f581a5 | 7891 | ((u64) tpr->rx_jmb_mapping >> 32)); |
1da177e4 | 7892 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, |
21f581a5 | 7893 | ((u64) tpr->rx_jmb_mapping & 0xffffffff)); |
1da177e4 | 7894 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, |
79ed5ac7 MC |
7895 | (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) | |
7896 | BDINFO_FLAGS_USE_EXT_RECV); | |
5fd68fbd | 7897 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) |
87668d35 MC |
7898 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR, |
7899 | NIC_SRAM_RX_JUMBO_BUFFER_DESC); | |
1da177e4 LT |
7900 | } else { |
7901 | tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, | |
7902 | BDINFO_FLAGS_DISABLED); | |
7903 | } | |
7904 | ||
b703df6f MC |
7905 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
7906 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
f6eb9b1f | 7907 | val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) | |
04380d40 | 7908 | (TG3_RX_STD_DMA_SZ << 2); |
f6eb9b1f | 7909 | else |
04380d40 | 7910 | val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT; |
fdb72b38 MC |
7911 | } else |
7912 | val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT; | |
7913 | ||
7914 | tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); | |
1da177e4 | 7915 | |
411da640 | 7916 | tpr->rx_std_prod_idx = tp->rx_pending; |
66711e66 | 7917 | tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); |
1da177e4 | 7918 | |
411da640 | 7919 | tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? |
21f581a5 | 7920 | tp->rx_jumbo_pending : 0; |
66711e66 | 7921 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
1da177e4 | 7922 | |
b703df6f MC |
7923 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
7924 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
f6eb9b1f MC |
7925 | tw32(STD_REPLENISH_LWM, 32); |
7926 | tw32(JMB_REPLENISH_LWM, 16); | |
7927 | } | |
7928 | ||
2d31ecaf MC |
7929 | tg3_rings_reset(tp); |
7930 | ||
1da177e4 | 7931 | /* Initialize MAC address and backoff seed. */ |
986e0aeb | 7932 | __tg3_set_mac_addr(tp, 0); |
1da177e4 LT |
7933 | |
7934 | /* MTU + ethernet header + FCS + optional VLAN tag */ | |
f7b493e0 MC |
7935 | tw32(MAC_RX_MTU_SIZE, |
7936 | tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); | |
1da177e4 LT |
7937 | |
7938 | /* The slot time is changed by tg3_setup_phy if we | |
7939 | * run at gigabit with half duplex. | |
7940 | */ | |
7941 | tw32(MAC_TX_LENGTHS, | |
7942 | (2 << TX_LENGTHS_IPG_CRS_SHIFT) | | |
7943 | (6 << TX_LENGTHS_IPG_SHIFT) | | |
7944 | (32 << TX_LENGTHS_SLOT_TIME_SHIFT)); | |
7945 | ||
7946 | /* Receive rules. */ | |
7947 | tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS); | |
7948 | tw32(RCVLPC_CONFIG, 0x0181); | |
7949 | ||
7950 | /* Calculate RDMAC_MODE setting early, we need it to determine | |
7951 | * the RCVLPC_STATE_ENABLE mask. | |
7952 | */ | |
7953 | rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB | | |
7954 | RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB | | |
7955 | RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB | | |
7956 | RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB | | |
7957 | RDMAC_MODE_LNGREAD_ENAB); | |
85e94ced | 7958 | |
0339e4e3 MC |
7959 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
7960 | rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS; | |
7961 | ||
57e6983c | 7962 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 MC |
7963 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
7964 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
d30cdd28 MC |
7965 | rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB | |
7966 | RDMAC_MODE_MBUF_RBD_CRPT_ENAB | | |
7967 | RDMAC_MODE_MBUF_SBD_CRPT_ENAB; | |
7968 | ||
85e94ced MC |
7969 | /* If statement applies to 5705 and 5750 PCI devices only */ |
7970 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
7971 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
7972 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { | |
1da177e4 | 7973 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && |
c13e3713 | 7974 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) { |
1da177e4 LT |
7975 | rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128; |
7976 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
7977 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) { | |
7978 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
7979 | } | |
7980 | } | |
7981 | ||
85e94ced MC |
7982 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) |
7983 | rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST; | |
7984 | ||
1da177e4 | 7985 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
027455ad MC |
7986 | rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN; |
7987 | ||
e849cdc3 MC |
7988 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
7989 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | |
027455ad MC |
7990 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
7991 | rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN; | |
1da177e4 LT |
7992 | |
7993 | /* Receive/send statistics. */ | |
1661394e MC |
7994 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7995 | val = tr32(RCVLPC_STATS_ENABLE); | |
7996 | val &= ~RCVLPC_STATSENAB_DACK_FIX; | |
7997 | tw32(RCVLPC_STATS_ENABLE, val); | |
7998 | } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) && | |
7999 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
1da177e4 LT |
8000 | val = tr32(RCVLPC_STATS_ENABLE); |
8001 | val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX; | |
8002 | tw32(RCVLPC_STATS_ENABLE, val); | |
8003 | } else { | |
8004 | tw32(RCVLPC_STATS_ENABLE, 0xffffff); | |
8005 | } | |
8006 | tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE); | |
8007 | tw32(SNDDATAI_STATSENAB, 0xffffff); | |
8008 | tw32(SNDDATAI_STATSCTRL, | |
8009 | (SNDDATAI_SCTRL_ENABLE | | |
8010 | SNDDATAI_SCTRL_FASTUPD)); | |
8011 | ||
8012 | /* Setup host coalescing engine. */ | |
8013 | tw32(HOSTCC_MODE, 0); | |
8014 | for (i = 0; i < 2000; i++) { | |
8015 | if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE)) | |
8016 | break; | |
8017 | udelay(10); | |
8018 | } | |
8019 | ||
d244c892 | 8020 | __tg3_set_coalesce(tp, &tp->coal); |
1da177e4 | 8021 | |
1da177e4 LT |
8022 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8023 | /* Status/statistics block address. See tg3_timer, | |
8024 | * the tg3_periodic_fetch_stats call there, and | |
8025 | * tg3_get_stats to see how this works for 5705/5750 chips. | |
8026 | */ | |
1da177e4 LT |
8027 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, |
8028 | ((u64) tp->stats_mapping >> 32)); | |
8029 | tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW, | |
8030 | ((u64) tp->stats_mapping & 0xffffffff)); | |
8031 | tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK); | |
2d31ecaf | 8032 | |
1da177e4 | 8033 | tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK); |
2d31ecaf MC |
8034 | |
8035 | /* Clear statistics and status block memory areas */ | |
8036 | for (i = NIC_SRAM_STATS_BLK; | |
8037 | i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; | |
8038 | i += sizeof(u32)) { | |
8039 | tg3_write_mem(tp, i, 0); | |
8040 | udelay(40); | |
8041 | } | |
1da177e4 LT |
8042 | } |
8043 | ||
8044 | tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); | |
8045 | ||
8046 | tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE); | |
8047 | tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE); | |
8048 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8049 | tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE); | |
8050 | ||
c94e3941 MC |
8051 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { |
8052 | tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT; | |
8053 | /* reset to prevent losing 1st rx packet intermittently */ | |
8054 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
8055 | udelay(10); | |
8056 | } | |
8057 | ||
3bda1258 MC |
8058 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
8059 | tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
8060 | else | |
8061 | tp->mac_mode = 0; | |
8062 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | |
1da177e4 | 8063 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; |
e8f3f6ca MC |
8064 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
8065 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
8066 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | |
8067 | tp->mac_mode |= MAC_MODE_LINK_POLARITY; | |
1da177e4 LT |
8068 | tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); |
8069 | udelay(40); | |
8070 | ||
314fba34 | 8071 | /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). |
9d26e213 | 8072 | * If TG3_FLG2_IS_NIC is zero, we should read the |
314fba34 MC |
8073 | * register to preserve the GPIO settings for LOMs. The GPIOs, |
8074 | * whether used as inputs or outputs, are set by boot code after | |
8075 | * reset. | |
8076 | */ | |
9d26e213 | 8077 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) { |
314fba34 MC |
8078 | u32 gpio_mask; |
8079 | ||
9d26e213 MC |
8080 | gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 | |
8081 | GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 | | |
8082 | GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2; | |
3e7d83bc MC |
8083 | |
8084 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
8085 | gpio_mask |= GRC_LCLCTRL_GPIO_OE3 | | |
8086 | GRC_LCLCTRL_GPIO_OUTPUT3; | |
8087 | ||
af36e6b6 MC |
8088 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
8089 | gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL; | |
8090 | ||
aaf84465 | 8091 | tp->grc_local_ctrl &= ~gpio_mask; |
314fba34 MC |
8092 | tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; |
8093 | ||
8094 | /* GPIO1 must be driven high for eeprom write protect */ | |
9d26e213 MC |
8095 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) |
8096 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
8097 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
314fba34 | 8098 | } |
1da177e4 LT |
8099 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
8100 | udelay(100); | |
8101 | ||
baf8a94a MC |
8102 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) { |
8103 | val = tr32(MSGINT_MODE); | |
8104 | val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE; | |
8105 | tw32(MSGINT_MODE, val); | |
8106 | } | |
8107 | ||
1da177e4 LT |
8108 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { |
8109 | tw32_f(DMAC_MODE, DMAC_MODE_ENABLE); | |
8110 | udelay(40); | |
8111 | } | |
8112 | ||
8113 | val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB | | |
8114 | WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB | | |
8115 | WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB | | |
8116 | WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB | | |
8117 | WDMAC_MODE_LNGREAD_ENAB); | |
8118 | ||
85e94ced MC |
8119 | /* If statement applies to 5705 and 5750 PCI devices only */ |
8120 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
8121 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || | |
8122 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { | |
29ea095f | 8123 | if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && |
1da177e4 LT |
8124 | (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || |
8125 | tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { | |
8126 | /* nothing */ | |
8127 | } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) && | |
8128 | !(tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
8129 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
8130 | val |= WDMAC_MODE_RX_ACCEL; | |
8131 | } | |
8132 | } | |
8133 | ||
d9ab5ad1 | 8134 | /* Enable host coalescing bug fix */ |
321d32a0 | 8135 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
f51f3562 | 8136 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
d9ab5ad1 | 8137 | |
788a035e MC |
8138 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
8139 | val |= WDMAC_MODE_BURST_ALL_DATA; | |
8140 | ||
1da177e4 LT |
8141 | tw32_f(WDMAC_MODE, val); |
8142 | udelay(40); | |
8143 | ||
9974a356 MC |
8144 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
8145 | u16 pcix_cmd; | |
8146 | ||
8147 | pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, | |
8148 | &pcix_cmd); | |
1da177e4 | 8149 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) { |
9974a356 MC |
8150 | pcix_cmd &= ~PCI_X_CMD_MAX_READ; |
8151 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8152 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { |
9974a356 MC |
8153 | pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ); |
8154 | pcix_cmd |= PCI_X_CMD_READ_2K; | |
1da177e4 | 8155 | } |
9974a356 MC |
8156 | pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, |
8157 | pcix_cmd); | |
1da177e4 LT |
8158 | } |
8159 | ||
8160 | tw32_f(RDMAC_MODE, rdmac_mode); | |
8161 | udelay(40); | |
8162 | ||
8163 | tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE); | |
8164 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
8165 | tw32(MBFREE_MODE, MBFREE_MODE_ENABLE); | |
9936bcf6 MC |
8166 | |
8167 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | |
8168 | tw32(SNDDATAC_MODE, | |
8169 | SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY); | |
8170 | else | |
8171 | tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE); | |
8172 | ||
1da177e4 LT |
8173 | tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE); |
8174 | tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB); | |
8175 | tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ); | |
8176 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE); | |
1da177e4 LT |
8177 | if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) |
8178 | tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8); | |
baf8a94a | 8179 | val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE; |
19cfaecc | 8180 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
baf8a94a MC |
8181 | val |= SNDBDI_MODE_MULTI_TXQ_EN; |
8182 | tw32(SNDBDI_MODE, val); | |
1da177e4 LT |
8183 | tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE); |
8184 | ||
8185 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8186 | err = tg3_load_5701_a0_firmware_fix(tp); | |
8187 | if (err) | |
8188 | return err; | |
8189 | } | |
8190 | ||
1da177e4 LT |
8191 | if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) { |
8192 | err = tg3_load_tso_firmware(tp); | |
8193 | if (err) | |
8194 | return err; | |
8195 | } | |
1da177e4 LT |
8196 | |
8197 | tp->tx_mode = TX_MODE_ENABLE; | |
8198 | tw32_f(MAC_TX_MODE, tp->tx_mode); | |
8199 | udelay(100); | |
8200 | ||
baf8a94a MC |
8201 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) { |
8202 | u32 reg = MAC_RSS_INDIR_TBL_0; | |
8203 | u8 *ent = (u8 *)&val; | |
8204 | ||
8205 | /* Setup the indirection table */ | |
8206 | for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) { | |
8207 | int idx = i % sizeof(val); | |
8208 | ||
8209 | ent[idx] = i % (tp->irq_cnt - 1); | |
8210 | if (idx == sizeof(val) - 1) { | |
8211 | tw32(reg, val); | |
8212 | reg += 4; | |
8213 | } | |
8214 | } | |
8215 | ||
8216 | /* Setup the "secret" hash key. */ | |
8217 | tw32(MAC_RSS_HASH_KEY_0, 0x5f865437); | |
8218 | tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc); | |
8219 | tw32(MAC_RSS_HASH_KEY_2, 0x50103a45); | |
8220 | tw32(MAC_RSS_HASH_KEY_3, 0x36621985); | |
8221 | tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8); | |
8222 | tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e); | |
8223 | tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556); | |
8224 | tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe); | |
8225 | tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7); | |
8226 | tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481); | |
8227 | } | |
8228 | ||
1da177e4 | 8229 | tp->rx_mode = RX_MODE_ENABLE; |
321d32a0 | 8230 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
af36e6b6 MC |
8231 | tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; |
8232 | ||
baf8a94a MC |
8233 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) |
8234 | tp->rx_mode |= RX_MODE_RSS_ENABLE | | |
8235 | RX_MODE_RSS_ITBL_HASH_BITS_7 | | |
8236 | RX_MODE_RSS_IPV6_HASH_EN | | |
8237 | RX_MODE_RSS_TCP_IPV6_HASH_EN | | |
8238 | RX_MODE_RSS_IPV4_HASH_EN | | |
8239 | RX_MODE_RSS_TCP_IPV4_HASH_EN; | |
8240 | ||
1da177e4 LT |
8241 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
8242 | udelay(10); | |
8243 | ||
1da177e4 LT |
8244 | tw32(MAC_LED_CTRL, tp->led_ctrl); |
8245 | ||
8246 | tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB); | |
c94e3941 | 8247 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { |
1da177e4 LT |
8248 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); |
8249 | udelay(10); | |
8250 | } | |
8251 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
8252 | udelay(10); | |
8253 | ||
8254 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
8255 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) && | |
8256 | !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) { | |
8257 | /* Set drive transmission level to 1.2V */ | |
8258 | /* only if the signal pre-emphasis bit is not set */ | |
8259 | val = tr32(MAC_SERDES_CFG); | |
8260 | val &= 0xfffff000; | |
8261 | val |= 0x880; | |
8262 | tw32(MAC_SERDES_CFG, val); | |
8263 | } | |
8264 | if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) | |
8265 | tw32(MAC_SERDES_CFG, 0x616000); | |
8266 | } | |
8267 | ||
8268 | /* Prevent chip from dropping frames when flow control | |
8269 | * is enabled. | |
8270 | */ | |
666bc831 MC |
8271 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) |
8272 | val = 1; | |
8273 | else | |
8274 | val = 2; | |
8275 | tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val); | |
1da177e4 LT |
8276 | |
8277 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && | |
8278 | (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { | |
8279 | /* Use hardware link auto-negotiation */ | |
8280 | tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG; | |
8281 | } | |
8282 | ||
d4d2c558 MC |
8283 | if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) && |
8284 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) { | |
8285 | u32 tmp; | |
8286 | ||
8287 | tmp = tr32(SERDES_RX_CTRL); | |
8288 | tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT); | |
8289 | tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; | |
8290 | tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; | |
8291 | tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); | |
8292 | } | |
8293 | ||
dd477003 MC |
8294 | if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { |
8295 | if (tp->link_config.phy_is_low_power) { | |
8296 | tp->link_config.phy_is_low_power = 0; | |
8297 | tp->link_config.speed = tp->link_config.orig_speed; | |
8298 | tp->link_config.duplex = tp->link_config.orig_duplex; | |
8299 | tp->link_config.autoneg = tp->link_config.orig_autoneg; | |
8300 | } | |
1da177e4 | 8301 | |
dd477003 MC |
8302 | err = tg3_setup_phy(tp, 0); |
8303 | if (err) | |
8304 | return err; | |
1da177e4 | 8305 | |
dd477003 | 8306 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
7f97a4bd | 8307 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) { |
dd477003 MC |
8308 | u32 tmp; |
8309 | ||
8310 | /* Clear CRC stats. */ | |
8311 | if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { | |
8312 | tg3_writephy(tp, MII_TG3_TEST1, | |
8313 | tmp | MII_TG3_TEST1_CRC_EN); | |
8314 | tg3_readphy(tp, 0x14, &tmp); | |
8315 | } | |
1da177e4 LT |
8316 | } |
8317 | } | |
8318 | ||
8319 | __tg3_set_rx_mode(tp->dev); | |
8320 | ||
8321 | /* Initialize receive rules. */ | |
8322 | tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK); | |
8323 | tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8324 | tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); | |
8325 | tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); | |
8326 | ||
4cf78e4f | 8327 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
a4e2b347 | 8328 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
1da177e4 LT |
8329 | limit = 8; |
8330 | else | |
8331 | limit = 16; | |
8332 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
8333 | limit -= 4; | |
8334 | switch (limit) { | |
8335 | case 16: | |
8336 | tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0); | |
8337 | case 15: | |
8338 | tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0); | |
8339 | case 14: | |
8340 | tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0); | |
8341 | case 13: | |
8342 | tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0); | |
8343 | case 12: | |
8344 | tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0); | |
8345 | case 11: | |
8346 | tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0); | |
8347 | case 10: | |
8348 | tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0); | |
8349 | case 9: | |
8350 | tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0); | |
8351 | case 8: | |
8352 | tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0); | |
8353 | case 7: | |
8354 | tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0); | |
8355 | case 6: | |
8356 | tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0); | |
8357 | case 5: | |
8358 | tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0); | |
8359 | case 4: | |
8360 | /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */ | |
8361 | case 3: | |
8362 | /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */ | |
8363 | case 2: | |
8364 | case 1: | |
8365 | ||
8366 | default: | |
8367 | break; | |
855e1111 | 8368 | } |
1da177e4 | 8369 | |
9ce768ea MC |
8370 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
8371 | /* Write our heartbeat update interval to APE. */ | |
8372 | tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, | |
8373 | APE_HOST_HEARTBEAT_INT_DISABLE); | |
0d3031d9 | 8374 | |
1da177e4 LT |
8375 | tg3_write_sig_post_reset(tp, RESET_KIND_INIT); |
8376 | ||
1da177e4 LT |
8377 | return 0; |
8378 | } | |
8379 | ||
8380 | /* Called at device open time to get the chip ready for | |
8381 | * packet processing. Invoked with tp->lock held. | |
8382 | */ | |
8e7a22e3 | 8383 | static int tg3_init_hw(struct tg3 *tp, int reset_phy) |
1da177e4 | 8384 | { |
1da177e4 LT |
8385 | tg3_switch_clocks(tp); |
8386 | ||
8387 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
8388 | ||
2f751b67 | 8389 | return tg3_reset_hw(tp, reset_phy); |
1da177e4 LT |
8390 | } |
8391 | ||
8392 | #define TG3_STAT_ADD32(PSTAT, REG) \ | |
8393 | do { u32 __val = tr32(REG); \ | |
8394 | (PSTAT)->low += __val; \ | |
8395 | if ((PSTAT)->low < __val) \ | |
8396 | (PSTAT)->high += 1; \ | |
8397 | } while (0) | |
8398 | ||
8399 | static void tg3_periodic_fetch_stats(struct tg3 *tp) | |
8400 | { | |
8401 | struct tg3_hw_stats *sp = tp->hw_stats; | |
8402 | ||
8403 | if (!netif_carrier_ok(tp->dev)) | |
8404 | return; | |
8405 | ||
8406 | TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); | |
8407 | TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); | |
8408 | TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); | |
8409 | TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); | |
8410 | TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); | |
8411 | TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); | |
8412 | TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); | |
8413 | TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); | |
8414 | TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); | |
8415 | TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); | |
8416 | TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); | |
8417 | TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); | |
8418 | TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); | |
8419 | ||
8420 | TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); | |
8421 | TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); | |
8422 | TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); | |
8423 | TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); | |
8424 | TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); | |
8425 | TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); | |
8426 | TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); | |
8427 | TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); | |
8428 | TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); | |
8429 | TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); | |
8430 | TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); | |
8431 | TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); | |
8432 | TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); | |
8433 | TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); | |
463d305b MC |
8434 | |
8435 | TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); | |
8436 | TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); | |
8437 | TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); | |
1da177e4 LT |
8438 | } |
8439 | ||
8440 | static void tg3_timer(unsigned long __opaque) | |
8441 | { | |
8442 | struct tg3 *tp = (struct tg3 *) __opaque; | |
1da177e4 | 8443 | |
f475f163 MC |
8444 | if (tp->irq_sync) |
8445 | goto restart_timer; | |
8446 | ||
f47c11ee | 8447 | spin_lock(&tp->lock); |
1da177e4 | 8448 | |
fac9b83e DM |
8449 | if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { |
8450 | /* All of this garbage is because when using non-tagged | |
8451 | * IRQ status the mailbox/status_block protocol the chip | |
8452 | * uses with the cpu is race prone. | |
8453 | */ | |
898a56f8 | 8454 | if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { |
fac9b83e DM |
8455 | tw32(GRC_LOCAL_CTRL, |
8456 | tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); | |
8457 | } else { | |
8458 | tw32(HOSTCC_MODE, tp->coalesce_mode | | |
fd2ce37f | 8459 | HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW); |
fac9b83e | 8460 | } |
1da177e4 | 8461 | |
fac9b83e DM |
8462 | if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { |
8463 | tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER; | |
f47c11ee | 8464 | spin_unlock(&tp->lock); |
fac9b83e DM |
8465 | schedule_work(&tp->reset_task); |
8466 | return; | |
8467 | } | |
1da177e4 LT |
8468 | } |
8469 | ||
1da177e4 LT |
8470 | /* This part only runs once per second. */ |
8471 | if (!--tp->timer_counter) { | |
fac9b83e DM |
8472 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) |
8473 | tg3_periodic_fetch_stats(tp); | |
8474 | ||
1da177e4 LT |
8475 | if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) { |
8476 | u32 mac_stat; | |
8477 | int phy_event; | |
8478 | ||
8479 | mac_stat = tr32(MAC_STATUS); | |
8480 | ||
8481 | phy_event = 0; | |
8482 | if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) { | |
8483 | if (mac_stat & MAC_STATUS_MI_INTERRUPT) | |
8484 | phy_event = 1; | |
8485 | } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) | |
8486 | phy_event = 1; | |
8487 | ||
8488 | if (phy_event) | |
8489 | tg3_setup_phy(tp, 0); | |
8490 | } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) { | |
8491 | u32 mac_stat = tr32(MAC_STATUS); | |
8492 | int need_setup = 0; | |
8493 | ||
8494 | if (netif_carrier_ok(tp->dev) && | |
8495 | (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) { | |
8496 | need_setup = 1; | |
8497 | } | |
8498 | if (! netif_carrier_ok(tp->dev) && | |
8499 | (mac_stat & (MAC_STATUS_PCS_SYNCED | | |
8500 | MAC_STATUS_SIGNAL_DET))) { | |
8501 | need_setup = 1; | |
8502 | } | |
8503 | if (need_setup) { | |
3d3ebe74 MC |
8504 | if (!tp->serdes_counter) { |
8505 | tw32_f(MAC_MODE, | |
8506 | (tp->mac_mode & | |
8507 | ~MAC_MODE_PORT_MODE_MASK)); | |
8508 | udelay(40); | |
8509 | tw32_f(MAC_MODE, tp->mac_mode); | |
8510 | udelay(40); | |
8511 | } | |
1da177e4 LT |
8512 | tg3_setup_phy(tp, 0); |
8513 | } | |
747e8f8b MC |
8514 | } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
8515 | tg3_serdes_parallel_detect(tp); | |
1da177e4 LT |
8516 | |
8517 | tp->timer_counter = tp->timer_multiplier; | |
8518 | } | |
8519 | ||
130b8e4d MC |
8520 | /* Heartbeat is only sent once every 2 seconds. |
8521 | * | |
8522 | * The heartbeat is to tell the ASF firmware that the host | |
8523 | * driver is still alive. In the event that the OS crashes, | |
8524 | * ASF needs to reset the hardware to free up the FIFO space | |
8525 | * that may be filled with rx packets destined for the host. | |
8526 | * If the FIFO is full, ASF will no longer function properly. | |
8527 | * | |
8528 | * Unintended resets have been reported on real time kernels | |
8529 | * where the timer doesn't run on time. Netpoll will also have | |
8530 | * same problem. | |
8531 | * | |
8532 | * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware | |
8533 | * to check the ring condition when the heartbeat is expiring | |
8534 | * before doing the reset. This will prevent most unintended | |
8535 | * resets. | |
8536 | */ | |
1da177e4 | 8537 | if (!--tp->asf_counter) { |
bc7959b2 MC |
8538 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) && |
8539 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
7c5026aa MC |
8540 | tg3_wait_for_event_ack(tp); |
8541 | ||
bbadf503 | 8542 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, |
130b8e4d | 8543 | FWCMD_NICDRV_ALIVE3); |
bbadf503 | 8544 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); |
c6cdf436 MC |
8545 | tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, |
8546 | TG3_FW_UPDATE_TIMEOUT_SEC); | |
4ba526ce MC |
8547 | |
8548 | tg3_generate_fw_event(tp); | |
1da177e4 LT |
8549 | } |
8550 | tp->asf_counter = tp->asf_multiplier; | |
8551 | } | |
8552 | ||
f47c11ee | 8553 | spin_unlock(&tp->lock); |
1da177e4 | 8554 | |
f475f163 | 8555 | restart_timer: |
1da177e4 LT |
8556 | tp->timer.expires = jiffies + tp->timer_offset; |
8557 | add_timer(&tp->timer); | |
8558 | } | |
8559 | ||
4f125f42 | 8560 | static int tg3_request_irq(struct tg3 *tp, int irq_num) |
fcfa0a32 | 8561 | { |
7d12e780 | 8562 | irq_handler_t fn; |
fcfa0a32 | 8563 | unsigned long flags; |
4f125f42 MC |
8564 | char *name; |
8565 | struct tg3_napi *tnapi = &tp->napi[irq_num]; | |
8566 | ||
8567 | if (tp->irq_cnt == 1) | |
8568 | name = tp->dev->name; | |
8569 | else { | |
8570 | name = &tnapi->irq_lbl[0]; | |
8571 | snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num); | |
8572 | name[IFNAMSIZ-1] = 0; | |
8573 | } | |
fcfa0a32 | 8574 | |
679563f4 | 8575 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { |
fcfa0a32 MC |
8576 | fn = tg3_msi; |
8577 | if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) | |
8578 | fn = tg3_msi_1shot; | |
1fb9df5d | 8579 | flags = IRQF_SAMPLE_RANDOM; |
fcfa0a32 MC |
8580 | } else { |
8581 | fn = tg3_interrupt; | |
8582 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) | |
8583 | fn = tg3_interrupt_tagged; | |
1fb9df5d | 8584 | flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM; |
fcfa0a32 | 8585 | } |
4f125f42 MC |
8586 | |
8587 | return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); | |
fcfa0a32 MC |
8588 | } |
8589 | ||
7938109f MC |
8590 | static int tg3_test_interrupt(struct tg3 *tp) |
8591 | { | |
09943a18 | 8592 | struct tg3_napi *tnapi = &tp->napi[0]; |
7938109f | 8593 | struct net_device *dev = tp->dev; |
b16250e3 | 8594 | int err, i, intr_ok = 0; |
f6eb9b1f | 8595 | u32 val; |
7938109f | 8596 | |
d4bc3927 MC |
8597 | if (!netif_running(dev)) |
8598 | return -ENODEV; | |
8599 | ||
7938109f MC |
8600 | tg3_disable_ints(tp); |
8601 | ||
4f125f42 | 8602 | free_irq(tnapi->irq_vec, tnapi); |
7938109f | 8603 | |
f6eb9b1f MC |
8604 | /* |
8605 | * Turn off MSI one shot mode. Otherwise this test has no | |
8606 | * observable way to know whether the interrupt was delivered. | |
8607 | */ | |
b703df6f MC |
8608 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8609 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
f6eb9b1f MC |
8610 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8611 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | |
8612 | tw32(MSGINT_MODE, val); | |
8613 | } | |
8614 | ||
4f125f42 | 8615 | err = request_irq(tnapi->irq_vec, tg3_test_isr, |
09943a18 | 8616 | IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi); |
7938109f MC |
8617 | if (err) |
8618 | return err; | |
8619 | ||
898a56f8 | 8620 | tnapi->hw_status->status &= ~SD_STATUS_UPDATED; |
7938109f MC |
8621 | tg3_enable_ints(tp); |
8622 | ||
8623 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 8624 | tnapi->coal_now); |
7938109f MC |
8625 | |
8626 | for (i = 0; i < 5; i++) { | |
b16250e3 MC |
8627 | u32 int_mbox, misc_host_ctrl; |
8628 | ||
898a56f8 | 8629 | int_mbox = tr32_mailbox(tnapi->int_mbox); |
b16250e3 MC |
8630 | misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL); |
8631 | ||
8632 | if ((int_mbox != 0) || | |
8633 | (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) { | |
8634 | intr_ok = 1; | |
7938109f | 8635 | break; |
b16250e3 MC |
8636 | } |
8637 | ||
7938109f MC |
8638 | msleep(10); |
8639 | } | |
8640 | ||
8641 | tg3_disable_ints(tp); | |
8642 | ||
4f125f42 | 8643 | free_irq(tnapi->irq_vec, tnapi); |
6aa20a22 | 8644 | |
4f125f42 | 8645 | err = tg3_request_irq(tp, 0); |
7938109f MC |
8646 | |
8647 | if (err) | |
8648 | return err; | |
8649 | ||
f6eb9b1f MC |
8650 | if (intr_ok) { |
8651 | /* Reenable MSI one shot mode. */ | |
b703df6f MC |
8652 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
8653 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | |
f6eb9b1f MC |
8654 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8655 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | |
8656 | tw32(MSGINT_MODE, val); | |
8657 | } | |
7938109f | 8658 | return 0; |
f6eb9b1f | 8659 | } |
7938109f MC |
8660 | |
8661 | return -EIO; | |
8662 | } | |
8663 | ||
8664 | /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is | |
8665 | * successfully restored | |
8666 | */ | |
8667 | static int tg3_test_msi(struct tg3 *tp) | |
8668 | { | |
7938109f MC |
8669 | int err; |
8670 | u16 pci_cmd; | |
8671 | ||
8672 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) | |
8673 | return 0; | |
8674 | ||
8675 | /* Turn off SERR reporting in case MSI terminates with Master | |
8676 | * Abort. | |
8677 | */ | |
8678 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
8679 | pci_write_config_word(tp->pdev, PCI_COMMAND, | |
8680 | pci_cmd & ~PCI_COMMAND_SERR); | |
8681 | ||
8682 | err = tg3_test_interrupt(tp); | |
8683 | ||
8684 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
8685 | ||
8686 | if (!err) | |
8687 | return 0; | |
8688 | ||
8689 | /* other failures */ | |
8690 | if (err != -EIO) | |
8691 | return err; | |
8692 | ||
8693 | /* MSI test failed, go back to INTx mode */ | |
5129c3a3 MC |
8694 | netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " |
8695 | "to INTx mode. Please report this failure to the PCI " | |
8696 | "maintainer and include system chipset information\n"); | |
7938109f | 8697 | |
4f125f42 | 8698 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
09943a18 | 8699 | |
7938109f MC |
8700 | pci_disable_msi(tp->pdev); |
8701 | ||
8702 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | |
8703 | ||
4f125f42 | 8704 | err = tg3_request_irq(tp, 0); |
7938109f MC |
8705 | if (err) |
8706 | return err; | |
8707 | ||
8708 | /* Need to reset the chip because the MSI cycle may have terminated | |
8709 | * with Master Abort. | |
8710 | */ | |
f47c11ee | 8711 | tg3_full_lock(tp, 1); |
7938109f | 8712 | |
944d980e | 8713 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
8e7a22e3 | 8714 | err = tg3_init_hw(tp, 1); |
7938109f | 8715 | |
f47c11ee | 8716 | tg3_full_unlock(tp); |
7938109f MC |
8717 | |
8718 | if (err) | |
4f125f42 | 8719 | free_irq(tp->napi[0].irq_vec, &tp->napi[0]); |
7938109f MC |
8720 | |
8721 | return err; | |
8722 | } | |
8723 | ||
9e9fd12d MC |
8724 | static int tg3_request_firmware(struct tg3 *tp) |
8725 | { | |
8726 | const __be32 *fw_data; | |
8727 | ||
8728 | if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { | |
05dbe005 JP |
8729 | netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", |
8730 | tp->fw_needed); | |
9e9fd12d MC |
8731 | return -ENOENT; |
8732 | } | |
8733 | ||
8734 | fw_data = (void *)tp->fw->data; | |
8735 | ||
8736 | /* Firmware blob starts with version numbers, followed by | |
8737 | * start address and _full_ length including BSS sections | |
8738 | * (which must be longer than the actual data, of course | |
8739 | */ | |
8740 | ||
8741 | tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */ | |
8742 | if (tp->fw_len < (tp->fw->size - 12)) { | |
05dbe005 JP |
8743 | netdev_err(tp->dev, "bogus length %d in \"%s\"\n", |
8744 | tp->fw_len, tp->fw_needed); | |
9e9fd12d MC |
8745 | release_firmware(tp->fw); |
8746 | tp->fw = NULL; | |
8747 | return -EINVAL; | |
8748 | } | |
8749 | ||
8750 | /* We no longer need firmware; we have it. */ | |
8751 | tp->fw_needed = NULL; | |
8752 | return 0; | |
8753 | } | |
8754 | ||
679563f4 MC |
8755 | static bool tg3_enable_msix(struct tg3 *tp) |
8756 | { | |
8757 | int i, rc, cpus = num_online_cpus(); | |
8758 | struct msix_entry msix_ent[tp->irq_max]; | |
8759 | ||
8760 | if (cpus == 1) | |
8761 | /* Just fallback to the simpler MSI mode. */ | |
8762 | return false; | |
8763 | ||
8764 | /* | |
8765 | * We want as many rx rings enabled as there are cpus. | |
8766 | * The first MSIX vector only deals with link interrupts, etc, | |
8767 | * so we add one to the number of vectors we are requesting. | |
8768 | */ | |
8769 | tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max); | |
8770 | ||
8771 | for (i = 0; i < tp->irq_max; i++) { | |
8772 | msix_ent[i].entry = i; | |
8773 | msix_ent[i].vector = 0; | |
8774 | } | |
8775 | ||
8776 | rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt); | |
8777 | if (rc != 0) { | |
8778 | if (rc < TG3_RSS_MIN_NUM_MSIX_VECS) | |
8779 | return false; | |
8780 | if (pci_enable_msix(tp->pdev, msix_ent, rc)) | |
8781 | return false; | |
05dbe005 JP |
8782 | netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", |
8783 | tp->irq_cnt, rc); | |
679563f4 MC |
8784 | tp->irq_cnt = rc; |
8785 | } | |
8786 | ||
baf8a94a MC |
8787 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS; |
8788 | ||
679563f4 MC |
8789 | for (i = 0; i < tp->irq_max; i++) |
8790 | tp->napi[i].irq_vec = msix_ent[i].vector; | |
8791 | ||
19cfaecc MC |
8792 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
8793 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS; | |
8794 | tp->dev->real_num_tx_queues = tp->irq_cnt - 1; | |
8795 | } else | |
8796 | tp->dev->real_num_tx_queues = 1; | |
fe5f5787 | 8797 | |
679563f4 MC |
8798 | return true; |
8799 | } | |
8800 | ||
07b0173c MC |
8801 | static void tg3_ints_init(struct tg3 *tp) |
8802 | { | |
679563f4 MC |
8803 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) && |
8804 | !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) { | |
07b0173c MC |
8805 | /* All MSI supporting chips should support tagged |
8806 | * status. Assert that this is the case. | |
8807 | */ | |
5129c3a3 MC |
8808 | netdev_warn(tp->dev, |
8809 | "MSI without TAGGED_STATUS? Not using MSI\n"); | |
679563f4 | 8810 | goto defcfg; |
07b0173c | 8811 | } |
4f125f42 | 8812 | |
679563f4 MC |
8813 | if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp)) |
8814 | tp->tg3_flags2 |= TG3_FLG2_USING_MSIX; | |
8815 | else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) && | |
8816 | pci_enable_msi(tp->pdev) == 0) | |
8817 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | |
8818 | ||
8819 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) { | |
8820 | u32 msi_mode = tr32(MSGINT_MODE); | |
baf8a94a MC |
8821 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) |
8822 | msi_mode |= MSGINT_MODE_MULTIVEC_EN; | |
679563f4 MC |
8823 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); |
8824 | } | |
8825 | defcfg: | |
8826 | if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) { | |
8827 | tp->irq_cnt = 1; | |
8828 | tp->napi[0].irq_vec = tp->pdev->irq; | |
fe5f5787 | 8829 | tp->dev->real_num_tx_queues = 1; |
679563f4 | 8830 | } |
07b0173c MC |
8831 | } |
8832 | ||
8833 | static void tg3_ints_fini(struct tg3 *tp) | |
8834 | { | |
679563f4 MC |
8835 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) |
8836 | pci_disable_msix(tp->pdev); | |
8837 | else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | |
8838 | pci_disable_msi(tp->pdev); | |
8839 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX; | |
baf8a94a | 8840 | tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS; |
07b0173c MC |
8841 | } |
8842 | ||
1da177e4 LT |
8843 | static int tg3_open(struct net_device *dev) |
8844 | { | |
8845 | struct tg3 *tp = netdev_priv(dev); | |
4f125f42 | 8846 | int i, err; |
1da177e4 | 8847 | |
9e9fd12d MC |
8848 | if (tp->fw_needed) { |
8849 | err = tg3_request_firmware(tp); | |
8850 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) { | |
8851 | if (err) | |
8852 | return err; | |
8853 | } else if (err) { | |
05dbe005 | 8854 | netdev_warn(tp->dev, "TSO capability disabled\n"); |
9e9fd12d MC |
8855 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; |
8856 | } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
05dbe005 | 8857 | netdev_notice(tp->dev, "TSO capability restored\n"); |
9e9fd12d MC |
8858 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
8859 | } | |
8860 | } | |
8861 | ||
c49a1561 MC |
8862 | netif_carrier_off(tp->dev); |
8863 | ||
bc1c7567 | 8864 | err = tg3_set_power_state(tp, PCI_D0); |
2f751b67 | 8865 | if (err) |
bc1c7567 | 8866 | return err; |
2f751b67 MC |
8867 | |
8868 | tg3_full_lock(tp, 0); | |
bc1c7567 | 8869 | |
1da177e4 LT |
8870 | tg3_disable_ints(tp); |
8871 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; | |
8872 | ||
f47c11ee | 8873 | tg3_full_unlock(tp); |
1da177e4 | 8874 | |
679563f4 MC |
8875 | /* |
8876 | * Setup interrupts first so we know how | |
8877 | * many NAPI resources to allocate | |
8878 | */ | |
8879 | tg3_ints_init(tp); | |
8880 | ||
1da177e4 LT |
8881 | /* The placement of this call is tied |
8882 | * to the setup and use of Host TX descriptors. | |
8883 | */ | |
8884 | err = tg3_alloc_consistent(tp); | |
8885 | if (err) | |
679563f4 | 8886 | goto err_out1; |
88b06bc2 | 8887 | |
fed97810 | 8888 | tg3_napi_enable(tp); |
1da177e4 | 8889 | |
4f125f42 MC |
8890 | for (i = 0; i < tp->irq_cnt; i++) { |
8891 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8892 | err = tg3_request_irq(tp, i); | |
8893 | if (err) { | |
8894 | for (i--; i >= 0; i--) | |
8895 | free_irq(tnapi->irq_vec, tnapi); | |
8896 | break; | |
8897 | } | |
8898 | } | |
1da177e4 | 8899 | |
07b0173c | 8900 | if (err) |
679563f4 | 8901 | goto err_out2; |
bea3348e | 8902 | |
f47c11ee | 8903 | tg3_full_lock(tp, 0); |
1da177e4 | 8904 | |
8e7a22e3 | 8905 | err = tg3_init_hw(tp, 1); |
1da177e4 | 8906 | if (err) { |
944d980e | 8907 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
8908 | tg3_free_rings(tp); |
8909 | } else { | |
fac9b83e DM |
8910 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) |
8911 | tp->timer_offset = HZ; | |
8912 | else | |
8913 | tp->timer_offset = HZ / 10; | |
8914 | ||
8915 | BUG_ON(tp->timer_offset > HZ); | |
8916 | tp->timer_counter = tp->timer_multiplier = | |
8917 | (HZ / tp->timer_offset); | |
8918 | tp->asf_counter = tp->asf_multiplier = | |
28fbef78 | 8919 | ((HZ / tp->timer_offset) * 2); |
1da177e4 LT |
8920 | |
8921 | init_timer(&tp->timer); | |
8922 | tp->timer.expires = jiffies + tp->timer_offset; | |
8923 | tp->timer.data = (unsigned long) tp; | |
8924 | tp->timer.function = tg3_timer; | |
1da177e4 LT |
8925 | } |
8926 | ||
f47c11ee | 8927 | tg3_full_unlock(tp); |
1da177e4 | 8928 | |
07b0173c | 8929 | if (err) |
679563f4 | 8930 | goto err_out3; |
1da177e4 | 8931 | |
7938109f MC |
8932 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { |
8933 | err = tg3_test_msi(tp); | |
fac9b83e | 8934 | |
7938109f | 8935 | if (err) { |
f47c11ee | 8936 | tg3_full_lock(tp, 0); |
944d980e | 8937 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
7938109f | 8938 | tg3_free_rings(tp); |
f47c11ee | 8939 | tg3_full_unlock(tp); |
7938109f | 8940 | |
679563f4 | 8941 | goto err_out2; |
7938109f | 8942 | } |
fcfa0a32 | 8943 | |
f6eb9b1f | 8944 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
b703df6f | 8945 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && |
f6eb9b1f MC |
8946 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI) && |
8947 | (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) { | |
8948 | u32 val = tr32(PCIE_TRANSACTION_CFG); | |
fcfa0a32 | 8949 | |
f6eb9b1f MC |
8950 | tw32(PCIE_TRANSACTION_CFG, |
8951 | val | PCIE_TRANS_CFG_1SHOT_MSI); | |
fcfa0a32 | 8952 | } |
7938109f MC |
8953 | } |
8954 | ||
b02fd9e3 MC |
8955 | tg3_phy_start(tp); |
8956 | ||
f47c11ee | 8957 | tg3_full_lock(tp, 0); |
1da177e4 | 8958 | |
7938109f MC |
8959 | add_timer(&tp->timer); |
8960 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
1da177e4 LT |
8961 | tg3_enable_ints(tp); |
8962 | ||
f47c11ee | 8963 | tg3_full_unlock(tp); |
1da177e4 | 8964 | |
fe5f5787 | 8965 | netif_tx_start_all_queues(dev); |
1da177e4 LT |
8966 | |
8967 | return 0; | |
07b0173c | 8968 | |
679563f4 | 8969 | err_out3: |
4f125f42 MC |
8970 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
8971 | struct tg3_napi *tnapi = &tp->napi[i]; | |
8972 | free_irq(tnapi->irq_vec, tnapi); | |
8973 | } | |
07b0173c | 8974 | |
679563f4 | 8975 | err_out2: |
fed97810 | 8976 | tg3_napi_disable(tp); |
07b0173c | 8977 | tg3_free_consistent(tp); |
679563f4 MC |
8978 | |
8979 | err_out1: | |
8980 | tg3_ints_fini(tp); | |
07b0173c | 8981 | return err; |
1da177e4 LT |
8982 | } |
8983 | ||
1da177e4 LT |
8984 | static struct net_device_stats *tg3_get_stats(struct net_device *); |
8985 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *); | |
8986 | ||
8987 | static int tg3_close(struct net_device *dev) | |
8988 | { | |
4f125f42 | 8989 | int i; |
1da177e4 LT |
8990 | struct tg3 *tp = netdev_priv(dev); |
8991 | ||
fed97810 | 8992 | tg3_napi_disable(tp); |
28e53bdd | 8993 | cancel_work_sync(&tp->reset_task); |
7faa006f | 8994 | |
fe5f5787 | 8995 | netif_tx_stop_all_queues(dev); |
1da177e4 LT |
8996 | |
8997 | del_timer_sync(&tp->timer); | |
8998 | ||
24bb4fb6 MC |
8999 | tg3_phy_stop(tp); |
9000 | ||
f47c11ee | 9001 | tg3_full_lock(tp, 1); |
1da177e4 LT |
9002 | |
9003 | tg3_disable_ints(tp); | |
9004 | ||
944d980e | 9005 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 | 9006 | tg3_free_rings(tp); |
5cf64b8a | 9007 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
1da177e4 | 9008 | |
f47c11ee | 9009 | tg3_full_unlock(tp); |
1da177e4 | 9010 | |
4f125f42 MC |
9011 | for (i = tp->irq_cnt - 1; i >= 0; i--) { |
9012 | struct tg3_napi *tnapi = &tp->napi[i]; | |
9013 | free_irq(tnapi->irq_vec, tnapi); | |
9014 | } | |
07b0173c MC |
9015 | |
9016 | tg3_ints_fini(tp); | |
1da177e4 LT |
9017 | |
9018 | memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev), | |
9019 | sizeof(tp->net_stats_prev)); | |
9020 | memcpy(&tp->estats_prev, tg3_get_estats(tp), | |
9021 | sizeof(tp->estats_prev)); | |
9022 | ||
9023 | tg3_free_consistent(tp); | |
9024 | ||
bc1c7567 MC |
9025 | tg3_set_power_state(tp, PCI_D3hot); |
9026 | ||
9027 | netif_carrier_off(tp->dev); | |
9028 | ||
1da177e4 LT |
9029 | return 0; |
9030 | } | |
9031 | ||
9032 | static inline unsigned long get_stat64(tg3_stat64_t *val) | |
9033 | { | |
9034 | unsigned long ret; | |
9035 | ||
9036 | #if (BITS_PER_LONG == 32) | |
9037 | ret = val->low; | |
9038 | #else | |
9039 | ret = ((u64)val->high << 32) | ((u64)val->low); | |
9040 | #endif | |
9041 | return ret; | |
9042 | } | |
9043 | ||
816f8b86 SB |
9044 | static inline u64 get_estat64(tg3_stat64_t *val) |
9045 | { | |
9046 | return ((u64)val->high << 32) | ((u64)val->low); | |
9047 | } | |
9048 | ||
1da177e4 LT |
9049 | static unsigned long calc_crc_errors(struct tg3 *tp) |
9050 | { | |
9051 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9052 | ||
9053 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && | |
9054 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
9055 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { | |
1da177e4 LT |
9056 | u32 val; |
9057 | ||
f47c11ee | 9058 | spin_lock_bh(&tp->lock); |
569a5df8 MC |
9059 | if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { |
9060 | tg3_writephy(tp, MII_TG3_TEST1, | |
9061 | val | MII_TG3_TEST1_CRC_EN); | |
1da177e4 LT |
9062 | tg3_readphy(tp, 0x14, &val); |
9063 | } else | |
9064 | val = 0; | |
f47c11ee | 9065 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
9066 | |
9067 | tp->phy_crc_errors += val; | |
9068 | ||
9069 | return tp->phy_crc_errors; | |
9070 | } | |
9071 | ||
9072 | return get_stat64(&hw_stats->rx_fcs_errors); | |
9073 | } | |
9074 | ||
9075 | #define ESTAT_ADD(member) \ | |
9076 | estats->member = old_estats->member + \ | |
816f8b86 | 9077 | get_estat64(&hw_stats->member) |
1da177e4 LT |
9078 | |
9079 | static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp) | |
9080 | { | |
9081 | struct tg3_ethtool_stats *estats = &tp->estats; | |
9082 | struct tg3_ethtool_stats *old_estats = &tp->estats_prev; | |
9083 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9084 | ||
9085 | if (!hw_stats) | |
9086 | return old_estats; | |
9087 | ||
9088 | ESTAT_ADD(rx_octets); | |
9089 | ESTAT_ADD(rx_fragments); | |
9090 | ESTAT_ADD(rx_ucast_packets); | |
9091 | ESTAT_ADD(rx_mcast_packets); | |
9092 | ESTAT_ADD(rx_bcast_packets); | |
9093 | ESTAT_ADD(rx_fcs_errors); | |
9094 | ESTAT_ADD(rx_align_errors); | |
9095 | ESTAT_ADD(rx_xon_pause_rcvd); | |
9096 | ESTAT_ADD(rx_xoff_pause_rcvd); | |
9097 | ESTAT_ADD(rx_mac_ctrl_rcvd); | |
9098 | ESTAT_ADD(rx_xoff_entered); | |
9099 | ESTAT_ADD(rx_frame_too_long_errors); | |
9100 | ESTAT_ADD(rx_jabbers); | |
9101 | ESTAT_ADD(rx_undersize_packets); | |
9102 | ESTAT_ADD(rx_in_length_errors); | |
9103 | ESTAT_ADD(rx_out_length_errors); | |
9104 | ESTAT_ADD(rx_64_or_less_octet_packets); | |
9105 | ESTAT_ADD(rx_65_to_127_octet_packets); | |
9106 | ESTAT_ADD(rx_128_to_255_octet_packets); | |
9107 | ESTAT_ADD(rx_256_to_511_octet_packets); | |
9108 | ESTAT_ADD(rx_512_to_1023_octet_packets); | |
9109 | ESTAT_ADD(rx_1024_to_1522_octet_packets); | |
9110 | ESTAT_ADD(rx_1523_to_2047_octet_packets); | |
9111 | ESTAT_ADD(rx_2048_to_4095_octet_packets); | |
9112 | ESTAT_ADD(rx_4096_to_8191_octet_packets); | |
9113 | ESTAT_ADD(rx_8192_to_9022_octet_packets); | |
9114 | ||
9115 | ESTAT_ADD(tx_octets); | |
9116 | ESTAT_ADD(tx_collisions); | |
9117 | ESTAT_ADD(tx_xon_sent); | |
9118 | ESTAT_ADD(tx_xoff_sent); | |
9119 | ESTAT_ADD(tx_flow_control); | |
9120 | ESTAT_ADD(tx_mac_errors); | |
9121 | ESTAT_ADD(tx_single_collisions); | |
9122 | ESTAT_ADD(tx_mult_collisions); | |
9123 | ESTAT_ADD(tx_deferred); | |
9124 | ESTAT_ADD(tx_excessive_collisions); | |
9125 | ESTAT_ADD(tx_late_collisions); | |
9126 | ESTAT_ADD(tx_collide_2times); | |
9127 | ESTAT_ADD(tx_collide_3times); | |
9128 | ESTAT_ADD(tx_collide_4times); | |
9129 | ESTAT_ADD(tx_collide_5times); | |
9130 | ESTAT_ADD(tx_collide_6times); | |
9131 | ESTAT_ADD(tx_collide_7times); | |
9132 | ESTAT_ADD(tx_collide_8times); | |
9133 | ESTAT_ADD(tx_collide_9times); | |
9134 | ESTAT_ADD(tx_collide_10times); | |
9135 | ESTAT_ADD(tx_collide_11times); | |
9136 | ESTAT_ADD(tx_collide_12times); | |
9137 | ESTAT_ADD(tx_collide_13times); | |
9138 | ESTAT_ADD(tx_collide_14times); | |
9139 | ESTAT_ADD(tx_collide_15times); | |
9140 | ESTAT_ADD(tx_ucast_packets); | |
9141 | ESTAT_ADD(tx_mcast_packets); | |
9142 | ESTAT_ADD(tx_bcast_packets); | |
9143 | ESTAT_ADD(tx_carrier_sense_errors); | |
9144 | ESTAT_ADD(tx_discards); | |
9145 | ESTAT_ADD(tx_errors); | |
9146 | ||
9147 | ESTAT_ADD(dma_writeq_full); | |
9148 | ESTAT_ADD(dma_write_prioq_full); | |
9149 | ESTAT_ADD(rxbds_empty); | |
9150 | ESTAT_ADD(rx_discards); | |
9151 | ESTAT_ADD(rx_errors); | |
9152 | ESTAT_ADD(rx_threshold_hit); | |
9153 | ||
9154 | ESTAT_ADD(dma_readq_full); | |
9155 | ESTAT_ADD(dma_read_prioq_full); | |
9156 | ESTAT_ADD(tx_comp_queue_full); | |
9157 | ||
9158 | ESTAT_ADD(ring_set_send_prod_index); | |
9159 | ESTAT_ADD(ring_status_update); | |
9160 | ESTAT_ADD(nic_irqs); | |
9161 | ESTAT_ADD(nic_avoided_irqs); | |
9162 | ESTAT_ADD(nic_tx_threshold_hit); | |
9163 | ||
9164 | return estats; | |
9165 | } | |
9166 | ||
9167 | static struct net_device_stats *tg3_get_stats(struct net_device *dev) | |
9168 | { | |
9169 | struct tg3 *tp = netdev_priv(dev); | |
9170 | struct net_device_stats *stats = &tp->net_stats; | |
9171 | struct net_device_stats *old_stats = &tp->net_stats_prev; | |
9172 | struct tg3_hw_stats *hw_stats = tp->hw_stats; | |
9173 | ||
9174 | if (!hw_stats) | |
9175 | return old_stats; | |
9176 | ||
9177 | stats->rx_packets = old_stats->rx_packets + | |
9178 | get_stat64(&hw_stats->rx_ucast_packets) + | |
9179 | get_stat64(&hw_stats->rx_mcast_packets) + | |
9180 | get_stat64(&hw_stats->rx_bcast_packets); | |
6aa20a22 | 9181 | |
1da177e4 LT |
9182 | stats->tx_packets = old_stats->tx_packets + |
9183 | get_stat64(&hw_stats->tx_ucast_packets) + | |
9184 | get_stat64(&hw_stats->tx_mcast_packets) + | |
9185 | get_stat64(&hw_stats->tx_bcast_packets); | |
9186 | ||
9187 | stats->rx_bytes = old_stats->rx_bytes + | |
9188 | get_stat64(&hw_stats->rx_octets); | |
9189 | stats->tx_bytes = old_stats->tx_bytes + | |
9190 | get_stat64(&hw_stats->tx_octets); | |
9191 | ||
9192 | stats->rx_errors = old_stats->rx_errors + | |
4f63b877 | 9193 | get_stat64(&hw_stats->rx_errors); |
1da177e4 LT |
9194 | stats->tx_errors = old_stats->tx_errors + |
9195 | get_stat64(&hw_stats->tx_errors) + | |
9196 | get_stat64(&hw_stats->tx_mac_errors) + | |
9197 | get_stat64(&hw_stats->tx_carrier_sense_errors) + | |
9198 | get_stat64(&hw_stats->tx_discards); | |
9199 | ||
9200 | stats->multicast = old_stats->multicast + | |
9201 | get_stat64(&hw_stats->rx_mcast_packets); | |
9202 | stats->collisions = old_stats->collisions + | |
9203 | get_stat64(&hw_stats->tx_collisions); | |
9204 | ||
9205 | stats->rx_length_errors = old_stats->rx_length_errors + | |
9206 | get_stat64(&hw_stats->rx_frame_too_long_errors) + | |
9207 | get_stat64(&hw_stats->rx_undersize_packets); | |
9208 | ||
9209 | stats->rx_over_errors = old_stats->rx_over_errors + | |
9210 | get_stat64(&hw_stats->rxbds_empty); | |
9211 | stats->rx_frame_errors = old_stats->rx_frame_errors + | |
9212 | get_stat64(&hw_stats->rx_align_errors); | |
9213 | stats->tx_aborted_errors = old_stats->tx_aborted_errors + | |
9214 | get_stat64(&hw_stats->tx_discards); | |
9215 | stats->tx_carrier_errors = old_stats->tx_carrier_errors + | |
9216 | get_stat64(&hw_stats->tx_carrier_sense_errors); | |
9217 | ||
9218 | stats->rx_crc_errors = old_stats->rx_crc_errors + | |
9219 | calc_crc_errors(tp); | |
9220 | ||
4f63b877 JL |
9221 | stats->rx_missed_errors = old_stats->rx_missed_errors + |
9222 | get_stat64(&hw_stats->rx_discards); | |
9223 | ||
1da177e4 LT |
9224 | return stats; |
9225 | } | |
9226 | ||
9227 | static inline u32 calc_crc(unsigned char *buf, int len) | |
9228 | { | |
9229 | u32 reg; | |
9230 | u32 tmp; | |
9231 | int j, k; | |
9232 | ||
9233 | reg = 0xffffffff; | |
9234 | ||
9235 | for (j = 0; j < len; j++) { | |
9236 | reg ^= buf[j]; | |
9237 | ||
9238 | for (k = 0; k < 8; k++) { | |
9239 | tmp = reg & 0x01; | |
9240 | ||
9241 | reg >>= 1; | |
9242 | ||
859a5887 | 9243 | if (tmp) |
1da177e4 | 9244 | reg ^= 0xedb88320; |
1da177e4 LT |
9245 | } |
9246 | } | |
9247 | ||
9248 | return ~reg; | |
9249 | } | |
9250 | ||
9251 | static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) | |
9252 | { | |
9253 | /* accept or reject all multicast frames */ | |
9254 | tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0); | |
9255 | tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0); | |
9256 | tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0); | |
9257 | tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0); | |
9258 | } | |
9259 | ||
9260 | static void __tg3_set_rx_mode(struct net_device *dev) | |
9261 | { | |
9262 | struct tg3 *tp = netdev_priv(dev); | |
9263 | u32 rx_mode; | |
9264 | ||
9265 | rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | | |
9266 | RX_MODE_KEEP_VLAN_TAG); | |
9267 | ||
9268 | /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG | |
9269 | * flag clear. | |
9270 | */ | |
9271 | #if TG3_VLAN_TAG_USED | |
9272 | if (!tp->vlgrp && | |
9273 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
9274 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9275 | #else | |
9276 | /* By definition, VLAN is disabled always in this | |
9277 | * case. | |
9278 | */ | |
9279 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
9280 | rx_mode |= RX_MODE_KEEP_VLAN_TAG; | |
9281 | #endif | |
9282 | ||
9283 | if (dev->flags & IFF_PROMISC) { | |
9284 | /* Promiscuous mode. */ | |
9285 | rx_mode |= RX_MODE_PROMISC; | |
9286 | } else if (dev->flags & IFF_ALLMULTI) { | |
9287 | /* Accept all multicast. */ | |
de6f31eb | 9288 | tg3_set_multi(tp, 1); |
4cd24eaf | 9289 | } else if (netdev_mc_empty(dev)) { |
1da177e4 | 9290 | /* Reject all multicast. */ |
de6f31eb | 9291 | tg3_set_multi(tp, 0); |
1da177e4 LT |
9292 | } else { |
9293 | /* Accept one or more multicast(s). */ | |
22bedad3 | 9294 | struct netdev_hw_addr *ha; |
1da177e4 LT |
9295 | u32 mc_filter[4] = { 0, }; |
9296 | u32 regidx; | |
9297 | u32 bit; | |
9298 | u32 crc; | |
9299 | ||
22bedad3 JP |
9300 | netdev_for_each_mc_addr(ha, dev) { |
9301 | crc = calc_crc(ha->addr, ETH_ALEN); | |
1da177e4 LT |
9302 | bit = ~crc & 0x7f; |
9303 | regidx = (bit & 0x60) >> 5; | |
9304 | bit &= 0x1f; | |
9305 | mc_filter[regidx] |= (1 << bit); | |
9306 | } | |
9307 | ||
9308 | tw32(MAC_HASH_REG_0, mc_filter[0]); | |
9309 | tw32(MAC_HASH_REG_1, mc_filter[1]); | |
9310 | tw32(MAC_HASH_REG_2, mc_filter[2]); | |
9311 | tw32(MAC_HASH_REG_3, mc_filter[3]); | |
9312 | } | |
9313 | ||
9314 | if (rx_mode != tp->rx_mode) { | |
9315 | tp->rx_mode = rx_mode; | |
9316 | tw32_f(MAC_RX_MODE, rx_mode); | |
9317 | udelay(10); | |
9318 | } | |
9319 | } | |
9320 | ||
9321 | static void tg3_set_rx_mode(struct net_device *dev) | |
9322 | { | |
9323 | struct tg3 *tp = netdev_priv(dev); | |
9324 | ||
e75f7c90 MC |
9325 | if (!netif_running(dev)) |
9326 | return; | |
9327 | ||
f47c11ee | 9328 | tg3_full_lock(tp, 0); |
1da177e4 | 9329 | __tg3_set_rx_mode(dev); |
f47c11ee | 9330 | tg3_full_unlock(tp); |
1da177e4 LT |
9331 | } |
9332 | ||
9333 | #define TG3_REGDUMP_LEN (32 * 1024) | |
9334 | ||
9335 | static int tg3_get_regs_len(struct net_device *dev) | |
9336 | { | |
9337 | return TG3_REGDUMP_LEN; | |
9338 | } | |
9339 | ||
9340 | static void tg3_get_regs(struct net_device *dev, | |
9341 | struct ethtool_regs *regs, void *_p) | |
9342 | { | |
9343 | u32 *p = _p; | |
9344 | struct tg3 *tp = netdev_priv(dev); | |
9345 | u8 *orig_p = _p; | |
9346 | int i; | |
9347 | ||
9348 | regs->version = 0; | |
9349 | ||
9350 | memset(p, 0, TG3_REGDUMP_LEN); | |
9351 | ||
bc1c7567 MC |
9352 | if (tp->link_config.phy_is_low_power) |
9353 | return; | |
9354 | ||
f47c11ee | 9355 | tg3_full_lock(tp, 0); |
1da177e4 LT |
9356 | |
9357 | #define __GET_REG32(reg) (*(p)++ = tr32(reg)) | |
9358 | #define GET_REG32_LOOP(base,len) \ | |
9359 | do { p = (u32 *)(orig_p + (base)); \ | |
9360 | for (i = 0; i < len; i += 4) \ | |
9361 | __GET_REG32((base) + i); \ | |
9362 | } while (0) | |
9363 | #define GET_REG32_1(reg) \ | |
9364 | do { p = (u32 *)(orig_p + (reg)); \ | |
9365 | __GET_REG32((reg)); \ | |
9366 | } while (0) | |
9367 | ||
9368 | GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0); | |
9369 | GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200); | |
9370 | GET_REG32_LOOP(MAC_MODE, 0x4f0); | |
9371 | GET_REG32_LOOP(SNDDATAI_MODE, 0xe0); | |
9372 | GET_REG32_1(SNDDATAC_MODE); | |
9373 | GET_REG32_LOOP(SNDBDS_MODE, 0x80); | |
9374 | GET_REG32_LOOP(SNDBDI_MODE, 0x48); | |
9375 | GET_REG32_1(SNDBDC_MODE); | |
9376 | GET_REG32_LOOP(RCVLPC_MODE, 0x20); | |
9377 | GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c); | |
9378 | GET_REG32_LOOP(RCVDBDI_MODE, 0x0c); | |
9379 | GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c); | |
9380 | GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44); | |
9381 | GET_REG32_1(RCVDCC_MODE); | |
9382 | GET_REG32_LOOP(RCVBDI_MODE, 0x20); | |
9383 | GET_REG32_LOOP(RCVCC_MODE, 0x14); | |
9384 | GET_REG32_LOOP(RCVLSC_MODE, 0x08); | |
9385 | GET_REG32_1(MBFREE_MODE); | |
9386 | GET_REG32_LOOP(HOSTCC_MODE, 0x100); | |
9387 | GET_REG32_LOOP(MEMARB_MODE, 0x10); | |
9388 | GET_REG32_LOOP(BUFMGR_MODE, 0x58); | |
9389 | GET_REG32_LOOP(RDMAC_MODE, 0x08); | |
9390 | GET_REG32_LOOP(WDMAC_MODE, 0x08); | |
091465d7 CE |
9391 | GET_REG32_1(RX_CPU_MODE); |
9392 | GET_REG32_1(RX_CPU_STATE); | |
9393 | GET_REG32_1(RX_CPU_PGMCTR); | |
9394 | GET_REG32_1(RX_CPU_HWBKPT); | |
9395 | GET_REG32_1(TX_CPU_MODE); | |
9396 | GET_REG32_1(TX_CPU_STATE); | |
9397 | GET_REG32_1(TX_CPU_PGMCTR); | |
1da177e4 LT |
9398 | GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110); |
9399 | GET_REG32_LOOP(FTQ_RESET, 0x120); | |
9400 | GET_REG32_LOOP(MSGINT_MODE, 0x0c); | |
9401 | GET_REG32_1(DMAC_MODE); | |
9402 | GET_REG32_LOOP(GRC_MODE, 0x4c); | |
9403 | if (tp->tg3_flags & TG3_FLAG_NVRAM) | |
9404 | GET_REG32_LOOP(NVRAM_CMD, 0x24); | |
9405 | ||
9406 | #undef __GET_REG32 | |
9407 | #undef GET_REG32_LOOP | |
9408 | #undef GET_REG32_1 | |
9409 | ||
f47c11ee | 9410 | tg3_full_unlock(tp); |
1da177e4 LT |
9411 | } |
9412 | ||
9413 | static int tg3_get_eeprom_len(struct net_device *dev) | |
9414 | { | |
9415 | struct tg3 *tp = netdev_priv(dev); | |
9416 | ||
9417 | return tp->nvram_size; | |
9418 | } | |
9419 | ||
1da177e4 LT |
9420 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
9421 | { | |
9422 | struct tg3 *tp = netdev_priv(dev); | |
9423 | int ret; | |
9424 | u8 *pd; | |
b9fc7dc5 | 9425 | u32 i, offset, len, b_offset, b_count; |
a9dc529d | 9426 | __be32 val; |
1da177e4 | 9427 | |
df259d8c MC |
9428 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
9429 | return -EINVAL; | |
9430 | ||
bc1c7567 MC |
9431 | if (tp->link_config.phy_is_low_power) |
9432 | return -EAGAIN; | |
9433 | ||
1da177e4 LT |
9434 | offset = eeprom->offset; |
9435 | len = eeprom->len; | |
9436 | eeprom->len = 0; | |
9437 | ||
9438 | eeprom->magic = TG3_EEPROM_MAGIC; | |
9439 | ||
9440 | if (offset & 3) { | |
9441 | /* adjustments to start on required 4 byte boundary */ | |
9442 | b_offset = offset & 3; | |
9443 | b_count = 4 - b_offset; | |
9444 | if (b_count > len) { | |
9445 | /* i.e. offset=1 len=2 */ | |
9446 | b_count = len; | |
9447 | } | |
a9dc529d | 9448 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); |
1da177e4 LT |
9449 | if (ret) |
9450 | return ret; | |
1da177e4 LT |
9451 | memcpy(data, ((char*)&val) + b_offset, b_count); |
9452 | len -= b_count; | |
9453 | offset += b_count; | |
c6cdf436 | 9454 | eeprom->len += b_count; |
1da177e4 LT |
9455 | } |
9456 | ||
9457 | /* read bytes upto the last 4 byte boundary */ | |
9458 | pd = &data[eeprom->len]; | |
9459 | for (i = 0; i < (len - (len & 3)); i += 4) { | |
a9dc529d | 9460 | ret = tg3_nvram_read_be32(tp, offset + i, &val); |
1da177e4 LT |
9461 | if (ret) { |
9462 | eeprom->len += i; | |
9463 | return ret; | |
9464 | } | |
1da177e4 LT |
9465 | memcpy(pd + i, &val, 4); |
9466 | } | |
9467 | eeprom->len += i; | |
9468 | ||
9469 | if (len & 3) { | |
9470 | /* read last bytes not ending on 4 byte boundary */ | |
9471 | pd = &data[eeprom->len]; | |
9472 | b_count = len & 3; | |
9473 | b_offset = offset + len - b_count; | |
a9dc529d | 9474 | ret = tg3_nvram_read_be32(tp, b_offset, &val); |
1da177e4 LT |
9475 | if (ret) |
9476 | return ret; | |
b9fc7dc5 | 9477 | memcpy(pd, &val, b_count); |
1da177e4 LT |
9478 | eeprom->len += b_count; |
9479 | } | |
9480 | return 0; | |
9481 | } | |
9482 | ||
6aa20a22 | 9483 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
1da177e4 LT |
9484 | |
9485 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | |
9486 | { | |
9487 | struct tg3 *tp = netdev_priv(dev); | |
9488 | int ret; | |
b9fc7dc5 | 9489 | u32 offset, len, b_offset, odd_len; |
1da177e4 | 9490 | u8 *buf; |
a9dc529d | 9491 | __be32 start, end; |
1da177e4 | 9492 | |
bc1c7567 MC |
9493 | if (tp->link_config.phy_is_low_power) |
9494 | return -EAGAIN; | |
9495 | ||
df259d8c MC |
9496 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
9497 | eeprom->magic != TG3_EEPROM_MAGIC) | |
1da177e4 LT |
9498 | return -EINVAL; |
9499 | ||
9500 | offset = eeprom->offset; | |
9501 | len = eeprom->len; | |
9502 | ||
9503 | if ((b_offset = (offset & 3))) { | |
9504 | /* adjustments to start on required 4 byte boundary */ | |
a9dc529d | 9505 | ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); |
1da177e4 LT |
9506 | if (ret) |
9507 | return ret; | |
1da177e4 LT |
9508 | len += b_offset; |
9509 | offset &= ~3; | |
1c8594b4 MC |
9510 | if (len < 4) |
9511 | len = 4; | |
1da177e4 LT |
9512 | } |
9513 | ||
9514 | odd_len = 0; | |
1c8594b4 | 9515 | if (len & 3) { |
1da177e4 LT |
9516 | /* adjustments to end on required 4 byte boundary */ |
9517 | odd_len = 1; | |
9518 | len = (len + 3) & ~3; | |
a9dc529d | 9519 | ret = tg3_nvram_read_be32(tp, offset+len-4, &end); |
1da177e4 LT |
9520 | if (ret) |
9521 | return ret; | |
1da177e4 LT |
9522 | } |
9523 | ||
9524 | buf = data; | |
9525 | if (b_offset || odd_len) { | |
9526 | buf = kmalloc(len, GFP_KERNEL); | |
ab0049b4 | 9527 | if (!buf) |
1da177e4 LT |
9528 | return -ENOMEM; |
9529 | if (b_offset) | |
9530 | memcpy(buf, &start, 4); | |
9531 | if (odd_len) | |
9532 | memcpy(buf+len-4, &end, 4); | |
9533 | memcpy(buf + b_offset, data, eeprom->len); | |
9534 | } | |
9535 | ||
9536 | ret = tg3_nvram_write_block(tp, offset, len, buf); | |
9537 | ||
9538 | if (buf != data) | |
9539 | kfree(buf); | |
9540 | ||
9541 | return ret; | |
9542 | } | |
9543 | ||
9544 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
9545 | { | |
b02fd9e3 MC |
9546 | struct tg3 *tp = netdev_priv(dev); |
9547 | ||
9548 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { | |
3f0e3ad7 | 9549 | struct phy_device *phydev; |
b02fd9e3 MC |
9550 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) |
9551 | return -EAGAIN; | |
3f0e3ad7 MC |
9552 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9553 | return phy_ethtool_gset(phydev, cmd); | |
b02fd9e3 | 9554 | } |
6aa20a22 | 9555 | |
1da177e4 LT |
9556 | cmd->supported = (SUPPORTED_Autoneg); |
9557 | ||
9558 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
9559 | cmd->supported |= (SUPPORTED_1000baseT_Half | | |
9560 | SUPPORTED_1000baseT_Full); | |
9561 | ||
ef348144 | 9562 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) { |
1da177e4 LT |
9563 | cmd->supported |= (SUPPORTED_100baseT_Half | |
9564 | SUPPORTED_100baseT_Full | | |
9565 | SUPPORTED_10baseT_Half | | |
9566 | SUPPORTED_10baseT_Full | | |
3bebab59 | 9567 | SUPPORTED_TP); |
ef348144 KK |
9568 | cmd->port = PORT_TP; |
9569 | } else { | |
1da177e4 | 9570 | cmd->supported |= SUPPORTED_FIBRE; |
ef348144 KK |
9571 | cmd->port = PORT_FIBRE; |
9572 | } | |
6aa20a22 | 9573 | |
1da177e4 LT |
9574 | cmd->advertising = tp->link_config.advertising; |
9575 | if (netif_running(dev)) { | |
9576 | cmd->speed = tp->link_config.active_speed; | |
9577 | cmd->duplex = tp->link_config.active_duplex; | |
9578 | } | |
882e9793 | 9579 | cmd->phy_address = tp->phy_addr; |
7e5856bd | 9580 | cmd->transceiver = XCVR_INTERNAL; |
1da177e4 LT |
9581 | cmd->autoneg = tp->link_config.autoneg; |
9582 | cmd->maxtxpkt = 0; | |
9583 | cmd->maxrxpkt = 0; | |
9584 | return 0; | |
9585 | } | |
6aa20a22 | 9586 | |
1da177e4 LT |
9587 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
9588 | { | |
9589 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9590 | |
b02fd9e3 | 9591 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 9592 | struct phy_device *phydev; |
b02fd9e3 MC |
9593 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) |
9594 | return -EAGAIN; | |
3f0e3ad7 MC |
9595 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
9596 | return phy_ethtool_sset(phydev, cmd); | |
b02fd9e3 MC |
9597 | } |
9598 | ||
7e5856bd MC |
9599 | if (cmd->autoneg != AUTONEG_ENABLE && |
9600 | cmd->autoneg != AUTONEG_DISABLE) | |
37ff238d | 9601 | return -EINVAL; |
7e5856bd MC |
9602 | |
9603 | if (cmd->autoneg == AUTONEG_DISABLE && | |
9604 | cmd->duplex != DUPLEX_FULL && | |
9605 | cmd->duplex != DUPLEX_HALF) | |
37ff238d | 9606 | return -EINVAL; |
1da177e4 | 9607 | |
7e5856bd MC |
9608 | if (cmd->autoneg == AUTONEG_ENABLE) { |
9609 | u32 mask = ADVERTISED_Autoneg | | |
9610 | ADVERTISED_Pause | | |
9611 | ADVERTISED_Asym_Pause; | |
9612 | ||
3f07d129 | 9613 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) |
7e5856bd MC |
9614 | mask |= ADVERTISED_1000baseT_Half | |
9615 | ADVERTISED_1000baseT_Full; | |
9616 | ||
9617 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) | |
9618 | mask |= ADVERTISED_100baseT_Half | | |
9619 | ADVERTISED_100baseT_Full | | |
9620 | ADVERTISED_10baseT_Half | | |
9621 | ADVERTISED_10baseT_Full | | |
9622 | ADVERTISED_TP; | |
9623 | else | |
9624 | mask |= ADVERTISED_FIBRE; | |
9625 | ||
9626 | if (cmd->advertising & ~mask) | |
9627 | return -EINVAL; | |
9628 | ||
9629 | mask &= (ADVERTISED_1000baseT_Half | | |
9630 | ADVERTISED_1000baseT_Full | | |
9631 | ADVERTISED_100baseT_Half | | |
9632 | ADVERTISED_100baseT_Full | | |
9633 | ADVERTISED_10baseT_Half | | |
9634 | ADVERTISED_10baseT_Full); | |
9635 | ||
9636 | cmd->advertising &= mask; | |
9637 | } else { | |
9638 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { | |
9639 | if (cmd->speed != SPEED_1000) | |
9640 | return -EINVAL; | |
9641 | ||
9642 | if (cmd->duplex != DUPLEX_FULL) | |
9643 | return -EINVAL; | |
9644 | } else { | |
9645 | if (cmd->speed != SPEED_100 && | |
9646 | cmd->speed != SPEED_10) | |
9647 | return -EINVAL; | |
9648 | } | |
9649 | } | |
9650 | ||
f47c11ee | 9651 | tg3_full_lock(tp, 0); |
1da177e4 LT |
9652 | |
9653 | tp->link_config.autoneg = cmd->autoneg; | |
9654 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
405d8e5c AG |
9655 | tp->link_config.advertising = (cmd->advertising | |
9656 | ADVERTISED_Autoneg); | |
1da177e4 LT |
9657 | tp->link_config.speed = SPEED_INVALID; |
9658 | tp->link_config.duplex = DUPLEX_INVALID; | |
9659 | } else { | |
9660 | tp->link_config.advertising = 0; | |
9661 | tp->link_config.speed = cmd->speed; | |
9662 | tp->link_config.duplex = cmd->duplex; | |
b02fd9e3 | 9663 | } |
6aa20a22 | 9664 | |
24fcad6b MC |
9665 | tp->link_config.orig_speed = tp->link_config.speed; |
9666 | tp->link_config.orig_duplex = tp->link_config.duplex; | |
9667 | tp->link_config.orig_autoneg = tp->link_config.autoneg; | |
9668 | ||
1da177e4 LT |
9669 | if (netif_running(dev)) |
9670 | tg3_setup_phy(tp, 1); | |
9671 | ||
f47c11ee | 9672 | tg3_full_unlock(tp); |
6aa20a22 | 9673 | |
1da177e4 LT |
9674 | return 0; |
9675 | } | |
6aa20a22 | 9676 | |
1da177e4 LT |
9677 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
9678 | { | |
9679 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9680 | |
1da177e4 LT |
9681 | strcpy(info->driver, DRV_MODULE_NAME); |
9682 | strcpy(info->version, DRV_MODULE_VERSION); | |
c4e6575c | 9683 | strcpy(info->fw_version, tp->fw_ver); |
1da177e4 LT |
9684 | strcpy(info->bus_info, pci_name(tp->pdev)); |
9685 | } | |
6aa20a22 | 9686 | |
1da177e4 LT |
9687 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
9688 | { | |
9689 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9690 | |
12dac075 RW |
9691 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
9692 | device_can_wakeup(&tp->pdev->dev)) | |
a85feb8c GZ |
9693 | wol->supported = WAKE_MAGIC; |
9694 | else | |
9695 | wol->supported = 0; | |
1da177e4 | 9696 | wol->wolopts = 0; |
05ac4cb7 MC |
9697 | if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) && |
9698 | device_can_wakeup(&tp->pdev->dev)) | |
1da177e4 LT |
9699 | wol->wolopts = WAKE_MAGIC; |
9700 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
9701 | } | |
6aa20a22 | 9702 | |
1da177e4 LT |
9703 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
9704 | { | |
9705 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 9706 | struct device *dp = &tp->pdev->dev; |
6aa20a22 | 9707 | |
1da177e4 LT |
9708 | if (wol->wolopts & ~WAKE_MAGIC) |
9709 | return -EINVAL; | |
9710 | if ((wol->wolopts & WAKE_MAGIC) && | |
12dac075 | 9711 | !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp))) |
1da177e4 | 9712 | return -EINVAL; |
6aa20a22 | 9713 | |
f47c11ee | 9714 | spin_lock_bh(&tp->lock); |
12dac075 | 9715 | if (wol->wolopts & WAKE_MAGIC) { |
1da177e4 | 9716 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
12dac075 RW |
9717 | device_set_wakeup_enable(dp, true); |
9718 | } else { | |
1da177e4 | 9719 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; |
12dac075 RW |
9720 | device_set_wakeup_enable(dp, false); |
9721 | } | |
f47c11ee | 9722 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 9723 | |
1da177e4 LT |
9724 | return 0; |
9725 | } | |
6aa20a22 | 9726 | |
1da177e4 LT |
9727 | static u32 tg3_get_msglevel(struct net_device *dev) |
9728 | { | |
9729 | struct tg3 *tp = netdev_priv(dev); | |
9730 | return tp->msg_enable; | |
9731 | } | |
6aa20a22 | 9732 | |
1da177e4 LT |
9733 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
9734 | { | |
9735 | struct tg3 *tp = netdev_priv(dev); | |
9736 | tp->msg_enable = value; | |
9737 | } | |
6aa20a22 | 9738 | |
1da177e4 LT |
9739 | static int tg3_set_tso(struct net_device *dev, u32 value) |
9740 | { | |
9741 | struct tg3 *tp = netdev_priv(dev); | |
9742 | ||
9743 | if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) { | |
9744 | if (value) | |
9745 | return -EINVAL; | |
9746 | return 0; | |
9747 | } | |
027455ad | 9748 | if ((dev->features & NETIF_F_IPV6_CSUM) && |
e849cdc3 MC |
9749 | ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || |
9750 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) { | |
9936bcf6 | 9751 | if (value) { |
b0026624 | 9752 | dev->features |= NETIF_F_TSO6; |
e849cdc3 MC |
9753 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
9754 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
9755 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
9756 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 9757 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
e849cdc3 | 9758 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
9936bcf6 MC |
9759 | dev->features |= NETIF_F_TSO_ECN; |
9760 | } else | |
9761 | dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN); | |
b0026624 | 9762 | } |
1da177e4 LT |
9763 | return ethtool_op_set_tso(dev, value); |
9764 | } | |
6aa20a22 | 9765 | |
1da177e4 LT |
9766 | static int tg3_nway_reset(struct net_device *dev) |
9767 | { | |
9768 | struct tg3 *tp = netdev_priv(dev); | |
1da177e4 | 9769 | int r; |
6aa20a22 | 9770 | |
1da177e4 LT |
9771 | if (!netif_running(dev)) |
9772 | return -EAGAIN; | |
9773 | ||
c94e3941 MC |
9774 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) |
9775 | return -EINVAL; | |
9776 | ||
b02fd9e3 MC |
9777 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
9778 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) | |
9779 | return -EAGAIN; | |
3f0e3ad7 | 9780 | r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]); |
b02fd9e3 MC |
9781 | } else { |
9782 | u32 bmcr; | |
9783 | ||
9784 | spin_lock_bh(&tp->lock); | |
9785 | r = -EINVAL; | |
9786 | tg3_readphy(tp, MII_BMCR, &bmcr); | |
9787 | if (!tg3_readphy(tp, MII_BMCR, &bmcr) && | |
9788 | ((bmcr & BMCR_ANENABLE) || | |
9789 | (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) { | |
9790 | tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | | |
9791 | BMCR_ANENABLE); | |
9792 | r = 0; | |
9793 | } | |
9794 | spin_unlock_bh(&tp->lock); | |
1da177e4 | 9795 | } |
6aa20a22 | 9796 | |
1da177e4 LT |
9797 | return r; |
9798 | } | |
6aa20a22 | 9799 | |
1da177e4 LT |
9800 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
9801 | { | |
9802 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9803 | |
1da177e4 LT |
9804 | ering->rx_max_pending = TG3_RX_RING_SIZE - 1; |
9805 | ering->rx_mini_max_pending = 0; | |
4f81c32b MC |
9806 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
9807 | ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1; | |
9808 | else | |
9809 | ering->rx_jumbo_max_pending = 0; | |
9810 | ||
9811 | ering->tx_max_pending = TG3_TX_RING_SIZE - 1; | |
1da177e4 LT |
9812 | |
9813 | ering->rx_pending = tp->rx_pending; | |
9814 | ering->rx_mini_pending = 0; | |
4f81c32b MC |
9815 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
9816 | ering->rx_jumbo_pending = tp->rx_jumbo_pending; | |
9817 | else | |
9818 | ering->rx_jumbo_pending = 0; | |
9819 | ||
f3f3f27e | 9820 | ering->tx_pending = tp->napi[0].tx_pending; |
1da177e4 | 9821 | } |
6aa20a22 | 9822 | |
1da177e4 LT |
9823 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
9824 | { | |
9825 | struct tg3 *tp = netdev_priv(dev); | |
646c9edd | 9826 | int i, irq_sync = 0, err = 0; |
6aa20a22 | 9827 | |
1da177e4 LT |
9828 | if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || |
9829 | (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || | |
bc3a9254 MC |
9830 | (ering->tx_pending > TG3_TX_RING_SIZE - 1) || |
9831 | (ering->tx_pending <= MAX_SKB_FRAGS) || | |
7f62ad5d | 9832 | ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) && |
bc3a9254 | 9833 | (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) |
1da177e4 | 9834 | return -EINVAL; |
6aa20a22 | 9835 | |
bbe832c0 | 9836 | if (netif_running(dev)) { |
b02fd9e3 | 9837 | tg3_phy_stop(tp); |
1da177e4 | 9838 | tg3_netif_stop(tp); |
bbe832c0 MC |
9839 | irq_sync = 1; |
9840 | } | |
1da177e4 | 9841 | |
bbe832c0 | 9842 | tg3_full_lock(tp, irq_sync); |
6aa20a22 | 9843 | |
1da177e4 LT |
9844 | tp->rx_pending = ering->rx_pending; |
9845 | ||
9846 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | |
9847 | tp->rx_pending > 63) | |
9848 | tp->rx_pending = 63; | |
9849 | tp->rx_jumbo_pending = ering->rx_jumbo_pending; | |
646c9edd MC |
9850 | |
9851 | for (i = 0; i < TG3_IRQ_MAX_VECS; i++) | |
9852 | tp->napi[i].tx_pending = ering->tx_pending; | |
1da177e4 LT |
9853 | |
9854 | if (netif_running(dev)) { | |
944d980e | 9855 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
b9ec6c1b MC |
9856 | err = tg3_restart_hw(tp, 1); |
9857 | if (!err) | |
9858 | tg3_netif_start(tp); | |
1da177e4 LT |
9859 | } |
9860 | ||
f47c11ee | 9861 | tg3_full_unlock(tp); |
6aa20a22 | 9862 | |
b02fd9e3 MC |
9863 | if (irq_sync && !err) |
9864 | tg3_phy_start(tp); | |
9865 | ||
b9ec6c1b | 9866 | return err; |
1da177e4 | 9867 | } |
6aa20a22 | 9868 | |
1da177e4 LT |
9869 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
9870 | { | |
9871 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9872 | |
1da177e4 | 9873 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; |
8d018621 | 9874 | |
e18ce346 | 9875 | if (tp->link_config.active_flowctrl & FLOW_CTRL_RX) |
8d018621 MC |
9876 | epause->rx_pause = 1; |
9877 | else | |
9878 | epause->rx_pause = 0; | |
9879 | ||
e18ce346 | 9880 | if (tp->link_config.active_flowctrl & FLOW_CTRL_TX) |
8d018621 MC |
9881 | epause->tx_pause = 1; |
9882 | else | |
9883 | epause->tx_pause = 0; | |
1da177e4 | 9884 | } |
6aa20a22 | 9885 | |
1da177e4 LT |
9886 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
9887 | { | |
9888 | struct tg3 *tp = netdev_priv(dev); | |
b02fd9e3 | 9889 | int err = 0; |
6aa20a22 | 9890 | |
b02fd9e3 | 9891 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
2712168f MC |
9892 | u32 newadv; |
9893 | struct phy_device *phydev; | |
1da177e4 | 9894 | |
2712168f | 9895 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
f47c11ee | 9896 | |
2712168f MC |
9897 | if (!(phydev->supported & SUPPORTED_Pause) || |
9898 | (!(phydev->supported & SUPPORTED_Asym_Pause) && | |
9899 | ((epause->rx_pause && !epause->tx_pause) || | |
9900 | (!epause->rx_pause && epause->tx_pause)))) | |
9901 | return -EINVAL; | |
1da177e4 | 9902 | |
2712168f MC |
9903 | tp->link_config.flowctrl = 0; |
9904 | if (epause->rx_pause) { | |
9905 | tp->link_config.flowctrl |= FLOW_CTRL_RX; | |
9906 | ||
9907 | if (epause->tx_pause) { | |
9908 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
9909 | newadv = ADVERTISED_Pause; | |
b02fd9e3 | 9910 | } else |
2712168f MC |
9911 | newadv = ADVERTISED_Pause | |
9912 | ADVERTISED_Asym_Pause; | |
9913 | } else if (epause->tx_pause) { | |
9914 | tp->link_config.flowctrl |= FLOW_CTRL_TX; | |
9915 | newadv = ADVERTISED_Asym_Pause; | |
9916 | } else | |
9917 | newadv = 0; | |
9918 | ||
9919 | if (epause->autoneg) | |
9920 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
9921 | else | |
9922 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
9923 | ||
9924 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { | |
9925 | u32 oldadv = phydev->advertising & | |
9926 | (ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
9927 | if (oldadv != newadv) { | |
9928 | phydev->advertising &= | |
9929 | ~(ADVERTISED_Pause | | |
9930 | ADVERTISED_Asym_Pause); | |
9931 | phydev->advertising |= newadv; | |
9932 | if (phydev->autoneg) { | |
9933 | /* | |
9934 | * Always renegotiate the link to | |
9935 | * inform our link partner of our | |
9936 | * flow control settings, even if the | |
9937 | * flow control is forced. Let | |
9938 | * tg3_adjust_link() do the final | |
9939 | * flow control setup. | |
9940 | */ | |
9941 | return phy_start_aneg(phydev); | |
b02fd9e3 | 9942 | } |
b02fd9e3 | 9943 | } |
b02fd9e3 | 9944 | |
2712168f | 9945 | if (!epause->autoneg) |
b02fd9e3 | 9946 | tg3_setup_flow_control(tp, 0, 0); |
2712168f MC |
9947 | } else { |
9948 | tp->link_config.orig_advertising &= | |
9949 | ~(ADVERTISED_Pause | | |
9950 | ADVERTISED_Asym_Pause); | |
9951 | tp->link_config.orig_advertising |= newadv; | |
b02fd9e3 MC |
9952 | } |
9953 | } else { | |
9954 | int irq_sync = 0; | |
9955 | ||
9956 | if (netif_running(dev)) { | |
9957 | tg3_netif_stop(tp); | |
9958 | irq_sync = 1; | |
9959 | } | |
9960 | ||
9961 | tg3_full_lock(tp, irq_sync); | |
9962 | ||
9963 | if (epause->autoneg) | |
9964 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
9965 | else | |
9966 | tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG; | |
9967 | if (epause->rx_pause) | |
e18ce346 | 9968 | tp->link_config.flowctrl |= FLOW_CTRL_RX; |
b02fd9e3 | 9969 | else |
e18ce346 | 9970 | tp->link_config.flowctrl &= ~FLOW_CTRL_RX; |
b02fd9e3 | 9971 | if (epause->tx_pause) |
e18ce346 | 9972 | tp->link_config.flowctrl |= FLOW_CTRL_TX; |
b02fd9e3 | 9973 | else |
e18ce346 | 9974 | tp->link_config.flowctrl &= ~FLOW_CTRL_TX; |
b02fd9e3 MC |
9975 | |
9976 | if (netif_running(dev)) { | |
9977 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); | |
9978 | err = tg3_restart_hw(tp, 1); | |
9979 | if (!err) | |
9980 | tg3_netif_start(tp); | |
9981 | } | |
9982 | ||
9983 | tg3_full_unlock(tp); | |
9984 | } | |
6aa20a22 | 9985 | |
b9ec6c1b | 9986 | return err; |
1da177e4 | 9987 | } |
6aa20a22 | 9988 | |
1da177e4 LT |
9989 | static u32 tg3_get_rx_csum(struct net_device *dev) |
9990 | { | |
9991 | struct tg3 *tp = netdev_priv(dev); | |
9992 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; | |
9993 | } | |
6aa20a22 | 9994 | |
1da177e4 LT |
9995 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) |
9996 | { | |
9997 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 9998 | |
1da177e4 LT |
9999 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
10000 | if (data != 0) | |
10001 | return -EINVAL; | |
c6cdf436 MC |
10002 | return 0; |
10003 | } | |
6aa20a22 | 10004 | |
f47c11ee | 10005 | spin_lock_bh(&tp->lock); |
1da177e4 LT |
10006 | if (data) |
10007 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
10008 | else | |
10009 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; | |
f47c11ee | 10010 | spin_unlock_bh(&tp->lock); |
6aa20a22 | 10011 | |
1da177e4 LT |
10012 | return 0; |
10013 | } | |
6aa20a22 | 10014 | |
1da177e4 LT |
10015 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) |
10016 | { | |
10017 | struct tg3 *tp = netdev_priv(dev); | |
6aa20a22 | 10018 | |
1da177e4 LT |
10019 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
10020 | if (data != 0) | |
10021 | return -EINVAL; | |
c6cdf436 MC |
10022 | return 0; |
10023 | } | |
6aa20a22 | 10024 | |
321d32a0 | 10025 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) |
6460d948 | 10026 | ethtool_op_set_tx_ipv6_csum(dev, data); |
1da177e4 | 10027 | else |
9c27dbdf | 10028 | ethtool_op_set_tx_csum(dev, data); |
1da177e4 LT |
10029 | |
10030 | return 0; | |
10031 | } | |
10032 | ||
de6f31eb | 10033 | static int tg3_get_sset_count(struct net_device *dev, int sset) |
1da177e4 | 10034 | { |
b9f2c044 JG |
10035 | switch (sset) { |
10036 | case ETH_SS_TEST: | |
10037 | return TG3_NUM_TEST; | |
10038 | case ETH_SS_STATS: | |
10039 | return TG3_NUM_STATS; | |
10040 | default: | |
10041 | return -EOPNOTSUPP; | |
10042 | } | |
4cafd3f5 MC |
10043 | } |
10044 | ||
de6f31eb | 10045 | static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf) |
1da177e4 LT |
10046 | { |
10047 | switch (stringset) { | |
10048 | case ETH_SS_STATS: | |
10049 | memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys)); | |
10050 | break; | |
4cafd3f5 MC |
10051 | case ETH_SS_TEST: |
10052 | memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys)); | |
10053 | break; | |
1da177e4 LT |
10054 | default: |
10055 | WARN_ON(1); /* we need a WARN() */ | |
10056 | break; | |
10057 | } | |
10058 | } | |
10059 | ||
4009a93d MC |
10060 | static int tg3_phys_id(struct net_device *dev, u32 data) |
10061 | { | |
10062 | struct tg3 *tp = netdev_priv(dev); | |
10063 | int i; | |
10064 | ||
10065 | if (!netif_running(tp->dev)) | |
10066 | return -EAGAIN; | |
10067 | ||
10068 | if (data == 0) | |
759afc31 | 10069 | data = UINT_MAX / 2; |
4009a93d MC |
10070 | |
10071 | for (i = 0; i < (data * 2); i++) { | |
10072 | if ((i % 2) == 0) | |
10073 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10074 | LED_CTRL_1000MBPS_ON | | |
10075 | LED_CTRL_100MBPS_ON | | |
10076 | LED_CTRL_10MBPS_ON | | |
10077 | LED_CTRL_TRAFFIC_OVERRIDE | | |
10078 | LED_CTRL_TRAFFIC_BLINK | | |
10079 | LED_CTRL_TRAFFIC_LED); | |
6aa20a22 | 10080 | |
4009a93d MC |
10081 | else |
10082 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | |
10083 | LED_CTRL_TRAFFIC_OVERRIDE); | |
10084 | ||
10085 | if (msleep_interruptible(500)) | |
10086 | break; | |
10087 | } | |
10088 | tw32(MAC_LED_CTRL, tp->led_ctrl); | |
10089 | return 0; | |
10090 | } | |
10091 | ||
de6f31eb | 10092 | static void tg3_get_ethtool_stats(struct net_device *dev, |
1da177e4 LT |
10093 | struct ethtool_stats *estats, u64 *tmp_stats) |
10094 | { | |
10095 | struct tg3 *tp = netdev_priv(dev); | |
10096 | memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats)); | |
10097 | } | |
10098 | ||
566f86ad | 10099 | #define NVRAM_TEST_SIZE 0x100 |
a5767dec MC |
10100 | #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
10101 | #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 | |
10102 | #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c | |
b16250e3 MC |
10103 | #define NVRAM_SELFBOOT_HW_SIZE 0x20 |
10104 | #define NVRAM_SELFBOOT_DATA_SIZE 0x1c | |
566f86ad MC |
10105 | |
10106 | static int tg3_test_nvram(struct tg3 *tp) | |
10107 | { | |
b9fc7dc5 | 10108 | u32 csum, magic; |
a9dc529d | 10109 | __be32 *buf; |
ab0049b4 | 10110 | int i, j, k, err = 0, size; |
566f86ad | 10111 | |
df259d8c MC |
10112 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) |
10113 | return 0; | |
10114 | ||
e4f34110 | 10115 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1b27777a MC |
10116 | return -EIO; |
10117 | ||
1b27777a MC |
10118 | if (magic == TG3_EEPROM_MAGIC) |
10119 | size = NVRAM_TEST_SIZE; | |
b16250e3 | 10120 | else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) { |
a5767dec MC |
10121 | if ((magic & TG3_EEPROM_SB_FORMAT_MASK) == |
10122 | TG3_EEPROM_SB_FORMAT_1) { | |
10123 | switch (magic & TG3_EEPROM_SB_REVISION_MASK) { | |
10124 | case TG3_EEPROM_SB_REVISION_0: | |
10125 | size = NVRAM_SELFBOOT_FORMAT1_0_SIZE; | |
10126 | break; | |
10127 | case TG3_EEPROM_SB_REVISION_2: | |
10128 | size = NVRAM_SELFBOOT_FORMAT1_2_SIZE; | |
10129 | break; | |
10130 | case TG3_EEPROM_SB_REVISION_3: | |
10131 | size = NVRAM_SELFBOOT_FORMAT1_3_SIZE; | |
10132 | break; | |
10133 | default: | |
10134 | return 0; | |
10135 | } | |
10136 | } else | |
1b27777a | 10137 | return 0; |
b16250e3 MC |
10138 | } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
10139 | size = NVRAM_SELFBOOT_HW_SIZE; | |
10140 | else | |
1b27777a MC |
10141 | return -EIO; |
10142 | ||
10143 | buf = kmalloc(size, GFP_KERNEL); | |
566f86ad MC |
10144 | if (buf == NULL) |
10145 | return -ENOMEM; | |
10146 | ||
1b27777a MC |
10147 | err = -EIO; |
10148 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
a9dc529d MC |
10149 | err = tg3_nvram_read_be32(tp, i, &buf[j]); |
10150 | if (err) | |
566f86ad | 10151 | break; |
566f86ad | 10152 | } |
1b27777a | 10153 | if (i < size) |
566f86ad MC |
10154 | goto out; |
10155 | ||
1b27777a | 10156 | /* Selfboot format */ |
a9dc529d | 10157 | magic = be32_to_cpu(buf[0]); |
b9fc7dc5 | 10158 | if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == |
b16250e3 | 10159 | TG3_EEPROM_MAGIC_FW) { |
1b27777a MC |
10160 | u8 *buf8 = (u8 *) buf, csum8 = 0; |
10161 | ||
b9fc7dc5 | 10162 | if ((magic & TG3_EEPROM_SB_REVISION_MASK) == |
a5767dec MC |
10163 | TG3_EEPROM_SB_REVISION_2) { |
10164 | /* For rev 2, the csum doesn't include the MBA. */ | |
10165 | for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++) | |
10166 | csum8 += buf8[i]; | |
10167 | for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++) | |
10168 | csum8 += buf8[i]; | |
10169 | } else { | |
10170 | for (i = 0; i < size; i++) | |
10171 | csum8 += buf8[i]; | |
10172 | } | |
1b27777a | 10173 | |
ad96b485 AB |
10174 | if (csum8 == 0) { |
10175 | err = 0; | |
10176 | goto out; | |
10177 | } | |
10178 | ||
10179 | err = -EIO; | |
10180 | goto out; | |
1b27777a | 10181 | } |
566f86ad | 10182 | |
b9fc7dc5 | 10183 | if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == |
b16250e3 MC |
10184 | TG3_EEPROM_MAGIC_HW) { |
10185 | u8 data[NVRAM_SELFBOOT_DATA_SIZE]; | |
a9dc529d | 10186 | u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; |
b16250e3 | 10187 | u8 *buf8 = (u8 *) buf; |
b16250e3 MC |
10188 | |
10189 | /* Separate the parity bits and the data bytes. */ | |
10190 | for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { | |
10191 | if ((i == 0) || (i == 8)) { | |
10192 | int l; | |
10193 | u8 msk; | |
10194 | ||
10195 | for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1) | |
10196 | parity[k++] = buf8[i] & msk; | |
10197 | i++; | |
859a5887 | 10198 | } else if (i == 16) { |
b16250e3 MC |
10199 | int l; |
10200 | u8 msk; | |
10201 | ||
10202 | for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1) | |
10203 | parity[k++] = buf8[i] & msk; | |
10204 | i++; | |
10205 | ||
10206 | for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1) | |
10207 | parity[k++] = buf8[i] & msk; | |
10208 | i++; | |
10209 | } | |
10210 | data[j++] = buf8[i]; | |
10211 | } | |
10212 | ||
10213 | err = -EIO; | |
10214 | for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) { | |
10215 | u8 hw8 = hweight8(data[i]); | |
10216 | ||
10217 | if ((hw8 & 0x1) && parity[i]) | |
10218 | goto out; | |
10219 | else if (!(hw8 & 0x1) && !parity[i]) | |
10220 | goto out; | |
10221 | } | |
10222 | err = 0; | |
10223 | goto out; | |
10224 | } | |
10225 | ||
566f86ad MC |
10226 | /* Bootstrap checksum at offset 0x10 */ |
10227 | csum = calc_crc((unsigned char *) buf, 0x10); | |
a9dc529d | 10228 | if (csum != be32_to_cpu(buf[0x10/4])) |
566f86ad MC |
10229 | goto out; |
10230 | ||
10231 | /* Manufacturing block starts at offset 0x74, checksum at 0xfc */ | |
10232 | csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88); | |
a9dc529d MC |
10233 | if (csum != be32_to_cpu(buf[0xfc/4])) |
10234 | goto out; | |
566f86ad MC |
10235 | |
10236 | err = 0; | |
10237 | ||
10238 | out: | |
10239 | kfree(buf); | |
10240 | return err; | |
10241 | } | |
10242 | ||
ca43007a MC |
10243 | #define TG3_SERDES_TIMEOUT_SEC 2 |
10244 | #define TG3_COPPER_TIMEOUT_SEC 6 | |
10245 | ||
10246 | static int tg3_test_link(struct tg3 *tp) | |
10247 | { | |
10248 | int i, max; | |
10249 | ||
10250 | if (!netif_running(tp->dev)) | |
10251 | return -ENODEV; | |
10252 | ||
4c987487 | 10253 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) |
ca43007a MC |
10254 | max = TG3_SERDES_TIMEOUT_SEC; |
10255 | else | |
10256 | max = TG3_COPPER_TIMEOUT_SEC; | |
10257 | ||
10258 | for (i = 0; i < max; i++) { | |
10259 | if (netif_carrier_ok(tp->dev)) | |
10260 | return 0; | |
10261 | ||
10262 | if (msleep_interruptible(1000)) | |
10263 | break; | |
10264 | } | |
10265 | ||
10266 | return -EIO; | |
10267 | } | |
10268 | ||
a71116d1 | 10269 | /* Only test the commonly used registers */ |
30ca3e37 | 10270 | static int tg3_test_registers(struct tg3 *tp) |
a71116d1 | 10271 | { |
b16250e3 | 10272 | int i, is_5705, is_5750; |
a71116d1 MC |
10273 | u32 offset, read_mask, write_mask, val, save_val, read_val; |
10274 | static struct { | |
10275 | u16 offset; | |
10276 | u16 flags; | |
10277 | #define TG3_FL_5705 0x1 | |
10278 | #define TG3_FL_NOT_5705 0x2 | |
10279 | #define TG3_FL_NOT_5788 0x4 | |
b16250e3 | 10280 | #define TG3_FL_NOT_5750 0x8 |
a71116d1 MC |
10281 | u32 read_mask; |
10282 | u32 write_mask; | |
10283 | } reg_tbl[] = { | |
10284 | /* MAC Control Registers */ | |
10285 | { MAC_MODE, TG3_FL_NOT_5705, | |
10286 | 0x00000000, 0x00ef6f8c }, | |
10287 | { MAC_MODE, TG3_FL_5705, | |
10288 | 0x00000000, 0x01ef6b8c }, | |
10289 | { MAC_STATUS, TG3_FL_NOT_5705, | |
10290 | 0x03800107, 0x00000000 }, | |
10291 | { MAC_STATUS, TG3_FL_5705, | |
10292 | 0x03800100, 0x00000000 }, | |
10293 | { MAC_ADDR_0_HIGH, 0x0000, | |
10294 | 0x00000000, 0x0000ffff }, | |
10295 | { MAC_ADDR_0_LOW, 0x0000, | |
c6cdf436 | 10296 | 0x00000000, 0xffffffff }, |
a71116d1 MC |
10297 | { MAC_RX_MTU_SIZE, 0x0000, |
10298 | 0x00000000, 0x0000ffff }, | |
10299 | { MAC_TX_MODE, 0x0000, | |
10300 | 0x00000000, 0x00000070 }, | |
10301 | { MAC_TX_LENGTHS, 0x0000, | |
10302 | 0x00000000, 0x00003fff }, | |
10303 | { MAC_RX_MODE, TG3_FL_NOT_5705, | |
10304 | 0x00000000, 0x000007fc }, | |
10305 | { MAC_RX_MODE, TG3_FL_5705, | |
10306 | 0x00000000, 0x000007dc }, | |
10307 | { MAC_HASH_REG_0, 0x0000, | |
10308 | 0x00000000, 0xffffffff }, | |
10309 | { MAC_HASH_REG_1, 0x0000, | |
10310 | 0x00000000, 0xffffffff }, | |
10311 | { MAC_HASH_REG_2, 0x0000, | |
10312 | 0x00000000, 0xffffffff }, | |
10313 | { MAC_HASH_REG_3, 0x0000, | |
10314 | 0x00000000, 0xffffffff }, | |
10315 | ||
10316 | /* Receive Data and Receive BD Initiator Control Registers. */ | |
10317 | { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705, | |
10318 | 0x00000000, 0xffffffff }, | |
10319 | { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705, | |
10320 | 0x00000000, 0xffffffff }, | |
10321 | { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705, | |
10322 | 0x00000000, 0x00000003 }, | |
10323 | { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705, | |
10324 | 0x00000000, 0xffffffff }, | |
10325 | { RCVDBDI_STD_BD+0, 0x0000, | |
10326 | 0x00000000, 0xffffffff }, | |
10327 | { RCVDBDI_STD_BD+4, 0x0000, | |
10328 | 0x00000000, 0xffffffff }, | |
10329 | { RCVDBDI_STD_BD+8, 0x0000, | |
10330 | 0x00000000, 0xffff0002 }, | |
10331 | { RCVDBDI_STD_BD+0xc, 0x0000, | |
10332 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10333 | |
a71116d1 MC |
10334 | /* Receive BD Initiator Control Registers. */ |
10335 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | |
10336 | 0x00000000, 0xffffffff }, | |
10337 | { RCVBDI_STD_THRESH, TG3_FL_5705, | |
10338 | 0x00000000, 0x000003ff }, | |
10339 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | |
10340 | 0x00000000, 0xffffffff }, | |
6aa20a22 | 10341 | |
a71116d1 MC |
10342 | /* Host Coalescing Control Registers. */ |
10343 | { HOSTCC_MODE, TG3_FL_NOT_5705, | |
10344 | 0x00000000, 0x00000004 }, | |
10345 | { HOSTCC_MODE, TG3_FL_5705, | |
10346 | 0x00000000, 0x000000f6 }, | |
10347 | { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705, | |
10348 | 0x00000000, 0xffffffff }, | |
10349 | { HOSTCC_RXCOL_TICKS, TG3_FL_5705, | |
10350 | 0x00000000, 0x000003ff }, | |
10351 | { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705, | |
10352 | 0x00000000, 0xffffffff }, | |
10353 | { HOSTCC_TXCOL_TICKS, TG3_FL_5705, | |
10354 | 0x00000000, 0x000003ff }, | |
10355 | { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705, | |
10356 | 0x00000000, 0xffffffff }, | |
10357 | { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10358 | 0x00000000, 0x000000ff }, | |
10359 | { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705, | |
10360 | 0x00000000, 0xffffffff }, | |
10361 | { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10362 | 0x00000000, 0x000000ff }, | |
10363 | { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10364 | 0x00000000, 0xffffffff }, | |
10365 | { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705, | |
10366 | 0x00000000, 0xffffffff }, | |
10367 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10368 | 0x00000000, 0xffffffff }, | |
10369 | { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10370 | 0x00000000, 0x000000ff }, | |
10371 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705, | |
10372 | 0x00000000, 0xffffffff }, | |
10373 | { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788, | |
10374 | 0x00000000, 0x000000ff }, | |
10375 | { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705, | |
10376 | 0x00000000, 0xffffffff }, | |
10377 | { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705, | |
10378 | 0x00000000, 0xffffffff }, | |
10379 | { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705, | |
10380 | 0x00000000, 0xffffffff }, | |
10381 | { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000, | |
10382 | 0x00000000, 0xffffffff }, | |
10383 | { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000, | |
10384 | 0x00000000, 0xffffffff }, | |
10385 | { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000, | |
10386 | 0xffffffff, 0x00000000 }, | |
10387 | { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000, | |
10388 | 0xffffffff, 0x00000000 }, | |
10389 | ||
10390 | /* Buffer Manager Control Registers. */ | |
b16250e3 | 10391 | { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750, |
a71116d1 | 10392 | 0x00000000, 0x007fff80 }, |
b16250e3 | 10393 | { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750, |
a71116d1 MC |
10394 | 0x00000000, 0x007fffff }, |
10395 | { BUFMGR_MB_RDMA_LOW_WATER, 0x0000, | |
10396 | 0x00000000, 0x0000003f }, | |
10397 | { BUFMGR_MB_MACRX_LOW_WATER, 0x0000, | |
10398 | 0x00000000, 0x000001ff }, | |
10399 | { BUFMGR_MB_HIGH_WATER, 0x0000, | |
10400 | 0x00000000, 0x000001ff }, | |
10401 | { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705, | |
10402 | 0xffffffff, 0x00000000 }, | |
10403 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | |
10404 | 0xffffffff, 0x00000000 }, | |
6aa20a22 | 10405 | |
a71116d1 MC |
10406 | /* Mailbox Registers */ |
10407 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | |
10408 | 0x00000000, 0x000001ff }, | |
10409 | { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705, | |
10410 | 0x00000000, 0x000001ff }, | |
10411 | { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000, | |
10412 | 0x00000000, 0x000007ff }, | |
10413 | { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000, | |
10414 | 0x00000000, 0x000001ff }, | |
10415 | ||
10416 | { 0xffff, 0x0000, 0x00000000, 0x00000000 }, | |
10417 | }; | |
10418 | ||
b16250e3 MC |
10419 | is_5705 = is_5750 = 0; |
10420 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
a71116d1 | 10421 | is_5705 = 1; |
b16250e3 MC |
10422 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
10423 | is_5750 = 1; | |
10424 | } | |
a71116d1 MC |
10425 | |
10426 | for (i = 0; reg_tbl[i].offset != 0xffff; i++) { | |
10427 | if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) | |
10428 | continue; | |
10429 | ||
10430 | if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) | |
10431 | continue; | |
10432 | ||
10433 | if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) && | |
10434 | (reg_tbl[i].flags & TG3_FL_NOT_5788)) | |
10435 | continue; | |
10436 | ||
b16250e3 MC |
10437 | if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) |
10438 | continue; | |
10439 | ||
a71116d1 MC |
10440 | offset = (u32) reg_tbl[i].offset; |
10441 | read_mask = reg_tbl[i].read_mask; | |
10442 | write_mask = reg_tbl[i].write_mask; | |
10443 | ||
10444 | /* Save the original register content */ | |
10445 | save_val = tr32(offset); | |
10446 | ||
10447 | /* Determine the read-only value. */ | |
10448 | read_val = save_val & read_mask; | |
10449 | ||
10450 | /* Write zero to the register, then make sure the read-only bits | |
10451 | * are not changed and the read/write bits are all zeros. | |
10452 | */ | |
10453 | tw32(offset, 0); | |
10454 | ||
10455 | val = tr32(offset); | |
10456 | ||
10457 | /* Test the read-only and read/write bits. */ | |
10458 | if (((val & read_mask) != read_val) || (val & write_mask)) | |
10459 | goto out; | |
10460 | ||
10461 | /* Write ones to all the bits defined by RdMask and WrMask, then | |
10462 | * make sure the read-only bits are not changed and the | |
10463 | * read/write bits are all ones. | |
10464 | */ | |
10465 | tw32(offset, read_mask | write_mask); | |
10466 | ||
10467 | val = tr32(offset); | |
10468 | ||
10469 | /* Test the read-only bits. */ | |
10470 | if ((val & read_mask) != read_val) | |
10471 | goto out; | |
10472 | ||
10473 | /* Test the read/write bits. */ | |
10474 | if ((val & write_mask) != write_mask) | |
10475 | goto out; | |
10476 | ||
10477 | tw32(offset, save_val); | |
10478 | } | |
10479 | ||
10480 | return 0; | |
10481 | ||
10482 | out: | |
9f88f29f | 10483 | if (netif_msg_hw(tp)) |
2445e461 MC |
10484 | netdev_err(tp->dev, |
10485 | "Register test failed at offset %x\n", offset); | |
a71116d1 MC |
10486 | tw32(offset, save_val); |
10487 | return -EIO; | |
10488 | } | |
10489 | ||
7942e1db MC |
10490 | static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) |
10491 | { | |
f71e1309 | 10492 | static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a }; |
7942e1db MC |
10493 | int i; |
10494 | u32 j; | |
10495 | ||
e9edda69 | 10496 | for (i = 0; i < ARRAY_SIZE(test_pattern); i++) { |
7942e1db MC |
10497 | for (j = 0; j < len; j += 4) { |
10498 | u32 val; | |
10499 | ||
10500 | tg3_write_mem(tp, offset + j, test_pattern[i]); | |
10501 | tg3_read_mem(tp, offset + j, &val); | |
10502 | if (val != test_pattern[i]) | |
10503 | return -EIO; | |
10504 | } | |
10505 | } | |
10506 | return 0; | |
10507 | } | |
10508 | ||
10509 | static int tg3_test_memory(struct tg3 *tp) | |
10510 | { | |
10511 | static struct mem_entry { | |
10512 | u32 offset; | |
10513 | u32 len; | |
10514 | } mem_tbl_570x[] = { | |
38690194 | 10515 | { 0x00000000, 0x00b50}, |
7942e1db MC |
10516 | { 0x00002000, 0x1c000}, |
10517 | { 0xffffffff, 0x00000} | |
10518 | }, mem_tbl_5705[] = { | |
10519 | { 0x00000100, 0x0000c}, | |
10520 | { 0x00000200, 0x00008}, | |
7942e1db MC |
10521 | { 0x00004000, 0x00800}, |
10522 | { 0x00006000, 0x01000}, | |
10523 | { 0x00008000, 0x02000}, | |
10524 | { 0x00010000, 0x0e000}, | |
10525 | { 0xffffffff, 0x00000} | |
79f4d13a MC |
10526 | }, mem_tbl_5755[] = { |
10527 | { 0x00000200, 0x00008}, | |
10528 | { 0x00004000, 0x00800}, | |
10529 | { 0x00006000, 0x00800}, | |
10530 | { 0x00008000, 0x02000}, | |
10531 | { 0x00010000, 0x0c000}, | |
10532 | { 0xffffffff, 0x00000} | |
b16250e3 MC |
10533 | }, mem_tbl_5906[] = { |
10534 | { 0x00000200, 0x00008}, | |
10535 | { 0x00004000, 0x00400}, | |
10536 | { 0x00006000, 0x00400}, | |
10537 | { 0x00008000, 0x01000}, | |
10538 | { 0x00010000, 0x01000}, | |
10539 | { 0xffffffff, 0x00000} | |
8b5a6c42 MC |
10540 | }, mem_tbl_5717[] = { |
10541 | { 0x00000200, 0x00008}, | |
10542 | { 0x00010000, 0x0a000}, | |
10543 | { 0x00020000, 0x13c00}, | |
10544 | { 0xffffffff, 0x00000} | |
10545 | }, mem_tbl_57765[] = { | |
10546 | { 0x00000200, 0x00008}, | |
10547 | { 0x00004000, 0x00800}, | |
10548 | { 0x00006000, 0x09800}, | |
10549 | { 0x00010000, 0x0a000}, | |
10550 | { 0xffffffff, 0x00000} | |
7942e1db MC |
10551 | }; |
10552 | struct mem_entry *mem_tbl; | |
10553 | int err = 0; | |
10554 | int i; | |
10555 | ||
8b5a6c42 MC |
10556 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
10557 | mem_tbl = mem_tbl_5717; | |
10558 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
10559 | mem_tbl = mem_tbl_57765; | |
10560 | else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
321d32a0 MC |
10561 | mem_tbl = mem_tbl_5755; |
10562 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
10563 | mem_tbl = mem_tbl_5906; | |
10564 | else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) | |
10565 | mem_tbl = mem_tbl_5705; | |
10566 | else | |
7942e1db MC |
10567 | mem_tbl = mem_tbl_570x; |
10568 | ||
10569 | for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) { | |
10570 | if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset, | |
10571 | mem_tbl[i].len)) != 0) | |
10572 | break; | |
10573 | } | |
6aa20a22 | 10574 | |
7942e1db MC |
10575 | return err; |
10576 | } | |
10577 | ||
9f40dead MC |
10578 | #define TG3_MAC_LOOPBACK 0 |
10579 | #define TG3_PHY_LOOPBACK 1 | |
10580 | ||
10581 | static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |
c76949a6 | 10582 | { |
9f40dead | 10583 | u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key; |
fd2ce37f | 10584 | u32 desc_idx, coal_now; |
c76949a6 MC |
10585 | struct sk_buff *skb, *rx_skb; |
10586 | u8 *tx_data; | |
10587 | dma_addr_t map; | |
10588 | int num_pkts, tx_len, rx_len, i, err; | |
10589 | struct tg3_rx_buffer_desc *desc; | |
898a56f8 | 10590 | struct tg3_napi *tnapi, *rnapi; |
21f581a5 | 10591 | struct tg3_rx_prodring_set *tpr = &tp->prodring[0]; |
c76949a6 | 10592 | |
c8873405 MC |
10593 | tnapi = &tp->napi[0]; |
10594 | rnapi = &tp->napi[0]; | |
0c1d0e2b | 10595 | if (tp->irq_cnt > 1) { |
0c1d0e2b | 10596 | rnapi = &tp->napi[1]; |
c8873405 MC |
10597 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) |
10598 | tnapi = &tp->napi[1]; | |
0c1d0e2b | 10599 | } |
fd2ce37f | 10600 | coal_now = tnapi->coal_now | rnapi->coal_now; |
898a56f8 | 10601 | |
9f40dead | 10602 | if (loopback_mode == TG3_MAC_LOOPBACK) { |
c94e3941 MC |
10603 | /* HW errata - mac loopback fails in some cases on 5780. |
10604 | * Normal traffic and PHY loopback are not affected by | |
10605 | * errata. | |
10606 | */ | |
10607 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) | |
10608 | return 0; | |
10609 | ||
9f40dead | 10610 | mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) | |
e8f3f6ca MC |
10611 | MAC_MODE_PORT_INT_LPBACK; |
10612 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
10613 | mac_mode |= MAC_MODE_LINK_POLARITY; | |
3f7045c1 MC |
10614 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) |
10615 | mac_mode |= MAC_MODE_PORT_MODE_MII; | |
10616 | else | |
10617 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
9f40dead MC |
10618 | tw32(MAC_MODE, mac_mode); |
10619 | } else if (loopback_mode == TG3_PHY_LOOPBACK) { | |
3f7045c1 MC |
10620 | u32 val; |
10621 | ||
7f97a4bd MC |
10622 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
10623 | tg3_phy_fet_toggle_apd(tp, false); | |
5d64ad34 MC |
10624 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100; |
10625 | } else | |
10626 | val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000; | |
3f7045c1 | 10627 | |
9ef8ca99 MC |
10628 | tg3_phy_toggle_automdix(tp, 0); |
10629 | ||
3f7045c1 | 10630 | tg3_writephy(tp, MII_BMCR, val); |
c94e3941 | 10631 | udelay(40); |
5d64ad34 | 10632 | |
e8f3f6ca | 10633 | mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; |
7f97a4bd | 10634 | if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { |
1061b7c5 MC |
10635 | tg3_writephy(tp, MII_TG3_FET_PTEST, |
10636 | MII_TG3_FET_PTEST_FRC_TX_LINK | | |
10637 | MII_TG3_FET_PTEST_FRC_TX_LOCK); | |
10638 | /* The write needs to be flushed for the AC131 */ | |
10639 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
10640 | tg3_readphy(tp, MII_TG3_FET_PTEST, &val); | |
5d64ad34 MC |
10641 | mac_mode |= MAC_MODE_PORT_MODE_MII; |
10642 | } else | |
10643 | mac_mode |= MAC_MODE_PORT_MODE_GMII; | |
b16250e3 | 10644 | |
c94e3941 MC |
10645 | /* reset to prevent losing 1st rx packet intermittently */ |
10646 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { | |
10647 | tw32_f(MAC_RX_MODE, RX_MODE_RESET); | |
10648 | udelay(10); | |
10649 | tw32_f(MAC_RX_MODE, tp->rx_mode); | |
10650 | } | |
e8f3f6ca | 10651 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) { |
79eb6904 MC |
10652 | u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; |
10653 | if (masked_phy_id == TG3_PHY_ID_BCM5401) | |
e8f3f6ca | 10654 | mac_mode &= ~MAC_MODE_LINK_POLARITY; |
79eb6904 | 10655 | else if (masked_phy_id == TG3_PHY_ID_BCM5411) |
e8f3f6ca | 10656 | mac_mode |= MAC_MODE_LINK_POLARITY; |
ff18ff02 MC |
10657 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
10658 | MII_TG3_EXT_CTRL_LNK3_LED_MODE); | |
10659 | } | |
9f40dead | 10660 | tw32(MAC_MODE, mac_mode); |
859a5887 | 10661 | } else { |
9f40dead | 10662 | return -EINVAL; |
859a5887 | 10663 | } |
c76949a6 MC |
10664 | |
10665 | err = -EIO; | |
10666 | ||
c76949a6 | 10667 | tx_len = 1514; |
a20e9c62 | 10668 | skb = netdev_alloc_skb(tp->dev, tx_len); |
a50bb7b9 JJ |
10669 | if (!skb) |
10670 | return -ENOMEM; | |
10671 | ||
c76949a6 MC |
10672 | tx_data = skb_put(skb, tx_len); |
10673 | memcpy(tx_data, tp->dev->dev_addr, 6); | |
10674 | memset(tx_data + 6, 0x0, 8); | |
10675 | ||
10676 | tw32(MAC_RX_MTU_SIZE, tx_len + 4); | |
10677 | ||
10678 | for (i = 14; i < tx_len; i++) | |
10679 | tx_data[i] = (u8) (i & 0xff); | |
10680 | ||
f4188d8a AD |
10681 | map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); |
10682 | if (pci_dma_mapping_error(tp->pdev, map)) { | |
a21771dd MC |
10683 | dev_kfree_skb(skb); |
10684 | return -EIO; | |
10685 | } | |
c76949a6 MC |
10686 | |
10687 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | | |
fd2ce37f | 10688 | rnapi->coal_now); |
c76949a6 MC |
10689 | |
10690 | udelay(10); | |
10691 | ||
898a56f8 | 10692 | rx_start_idx = rnapi->hw_status->idx[0].rx_producer; |
c76949a6 | 10693 | |
c76949a6 MC |
10694 | num_pkts = 0; |
10695 | ||
f4188d8a | 10696 | tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1); |
c76949a6 | 10697 | |
f3f3f27e | 10698 | tnapi->tx_prod++; |
c76949a6 MC |
10699 | num_pkts++; |
10700 | ||
f3f3f27e MC |
10701 | tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); |
10702 | tr32_mailbox(tnapi->prodmbox); | |
c76949a6 MC |
10703 | |
10704 | udelay(10); | |
10705 | ||
303fc921 MC |
10706 | /* 350 usec to allow enough time on some 10/100 Mbps devices. */ |
10707 | for (i = 0; i < 35; i++) { | |
c76949a6 | 10708 | tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | |
fd2ce37f | 10709 | coal_now); |
c76949a6 MC |
10710 | |
10711 | udelay(10); | |
10712 | ||
898a56f8 MC |
10713 | tx_idx = tnapi->hw_status->idx[0].tx_consumer; |
10714 | rx_idx = rnapi->hw_status->idx[0].rx_producer; | |
f3f3f27e | 10715 | if ((tx_idx == tnapi->tx_prod) && |
c76949a6 MC |
10716 | (rx_idx == (rx_start_idx + num_pkts))) |
10717 | break; | |
10718 | } | |
10719 | ||
f4188d8a | 10720 | pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE); |
c76949a6 MC |
10721 | dev_kfree_skb(skb); |
10722 | ||
f3f3f27e | 10723 | if (tx_idx != tnapi->tx_prod) |
c76949a6 MC |
10724 | goto out; |
10725 | ||
10726 | if (rx_idx != rx_start_idx + num_pkts) | |
10727 | goto out; | |
10728 | ||
72334482 | 10729 | desc = &rnapi->rx_rcb[rx_start_idx]; |
c76949a6 MC |
10730 | desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; |
10731 | opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; | |
10732 | if (opaque_key != RXD_OPAQUE_RING_STD) | |
10733 | goto out; | |
10734 | ||
10735 | if ((desc->err_vlan & RXD_ERR_MASK) != 0 && | |
10736 | (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) | |
10737 | goto out; | |
10738 | ||
10739 | rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; | |
10740 | if (rx_len != tx_len) | |
10741 | goto out; | |
10742 | ||
21f581a5 | 10743 | rx_skb = tpr->rx_std_buffers[desc_idx].skb; |
c76949a6 | 10744 | |
21f581a5 | 10745 | map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping); |
c76949a6 MC |
10746 | pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE); |
10747 | ||
10748 | for (i = 14; i < tx_len; i++) { | |
10749 | if (*(rx_skb->data + i) != (u8) (i & 0xff)) | |
10750 | goto out; | |
10751 | } | |
10752 | err = 0; | |
6aa20a22 | 10753 | |
c76949a6 MC |
10754 | /* tg3_free_rings will unmap and free the rx_skb */ |
10755 | out: | |
10756 | return err; | |
10757 | } | |
10758 | ||
9f40dead MC |
10759 | #define TG3_MAC_LOOPBACK_FAILED 1 |
10760 | #define TG3_PHY_LOOPBACK_FAILED 2 | |
10761 | #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \ | |
10762 | TG3_PHY_LOOPBACK_FAILED) | |
10763 | ||
10764 | static int tg3_test_loopback(struct tg3 *tp) | |
10765 | { | |
10766 | int err = 0; | |
9936bcf6 | 10767 | u32 cpmuctrl = 0; |
9f40dead MC |
10768 | |
10769 | if (!netif_running(tp->dev)) | |
10770 | return TG3_LOOPBACK_FAILED; | |
10771 | ||
b9ec6c1b MC |
10772 | err = tg3_reset_hw(tp, 1); |
10773 | if (err) | |
10774 | return TG3_LOOPBACK_FAILED; | |
9f40dead | 10775 | |
6833c043 MC |
10776 | /* Turn off gphy autopowerdown. */ |
10777 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
10778 | tg3_phy_toggle_apd(tp, false); | |
10779 | ||
321d32a0 | 10780 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
10781 | int i; |
10782 | u32 status; | |
10783 | ||
10784 | tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER); | |
10785 | ||
10786 | /* Wait for up to 40 microseconds to acquire lock. */ | |
10787 | for (i = 0; i < 4; i++) { | |
10788 | status = tr32(TG3_CPMU_MUTEX_GNT); | |
10789 | if (status == CPMU_MUTEX_GNT_DRIVER) | |
10790 | break; | |
10791 | udelay(10); | |
10792 | } | |
10793 | ||
10794 | if (status != CPMU_MUTEX_GNT_DRIVER) | |
10795 | return TG3_LOOPBACK_FAILED; | |
10796 | ||
b2a5c19c | 10797 | /* Turn off link-based power management. */ |
e875093c | 10798 | cpmuctrl = tr32(TG3_CPMU_CTRL); |
109115e1 MC |
10799 | tw32(TG3_CPMU_CTRL, |
10800 | cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE | | |
10801 | CPMU_CTRL_LINK_AWARE_MODE)); | |
9936bcf6 MC |
10802 | } |
10803 | ||
9f40dead MC |
10804 | if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK)) |
10805 | err |= TG3_MAC_LOOPBACK_FAILED; | |
9936bcf6 | 10806 | |
321d32a0 | 10807 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) { |
9936bcf6 MC |
10808 | tw32(TG3_CPMU_CTRL, cpmuctrl); |
10809 | ||
10810 | /* Release the mutex */ | |
10811 | tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER); | |
10812 | } | |
10813 | ||
dd477003 MC |
10814 | if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) && |
10815 | !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) { | |
9f40dead MC |
10816 | if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK)) |
10817 | err |= TG3_PHY_LOOPBACK_FAILED; | |
10818 | } | |
10819 | ||
6833c043 MC |
10820 | /* Re-enable gphy autopowerdown. */ |
10821 | if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD) | |
10822 | tg3_phy_toggle_apd(tp, true); | |
10823 | ||
9f40dead MC |
10824 | return err; |
10825 | } | |
10826 | ||
4cafd3f5 MC |
10827 | static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest, |
10828 | u64 *data) | |
10829 | { | |
566f86ad MC |
10830 | struct tg3 *tp = netdev_priv(dev); |
10831 | ||
bc1c7567 MC |
10832 | if (tp->link_config.phy_is_low_power) |
10833 | tg3_set_power_state(tp, PCI_D0); | |
10834 | ||
566f86ad MC |
10835 | memset(data, 0, sizeof(u64) * TG3_NUM_TEST); |
10836 | ||
10837 | if (tg3_test_nvram(tp) != 0) { | |
10838 | etest->flags |= ETH_TEST_FL_FAILED; | |
10839 | data[0] = 1; | |
10840 | } | |
ca43007a MC |
10841 | if (tg3_test_link(tp) != 0) { |
10842 | etest->flags |= ETH_TEST_FL_FAILED; | |
10843 | data[1] = 1; | |
10844 | } | |
a71116d1 | 10845 | if (etest->flags & ETH_TEST_FL_OFFLINE) { |
b02fd9e3 | 10846 | int err, err2 = 0, irq_sync = 0; |
bbe832c0 MC |
10847 | |
10848 | if (netif_running(dev)) { | |
b02fd9e3 | 10849 | tg3_phy_stop(tp); |
a71116d1 | 10850 | tg3_netif_stop(tp); |
bbe832c0 MC |
10851 | irq_sync = 1; |
10852 | } | |
a71116d1 | 10853 | |
bbe832c0 | 10854 | tg3_full_lock(tp, irq_sync); |
a71116d1 MC |
10855 | |
10856 | tg3_halt(tp, RESET_KIND_SUSPEND, 1); | |
ec41c7df | 10857 | err = tg3_nvram_lock(tp); |
a71116d1 MC |
10858 | tg3_halt_cpu(tp, RX_CPU_BASE); |
10859 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
10860 | tg3_halt_cpu(tp, TX_CPU_BASE); | |
ec41c7df MC |
10861 | if (!err) |
10862 | tg3_nvram_unlock(tp); | |
a71116d1 | 10863 | |
d9ab5ad1 MC |
10864 | if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) |
10865 | tg3_phy_reset(tp); | |
10866 | ||
a71116d1 MC |
10867 | if (tg3_test_registers(tp) != 0) { |
10868 | etest->flags |= ETH_TEST_FL_FAILED; | |
10869 | data[2] = 1; | |
10870 | } | |
7942e1db MC |
10871 | if (tg3_test_memory(tp) != 0) { |
10872 | etest->flags |= ETH_TEST_FL_FAILED; | |
10873 | data[3] = 1; | |
10874 | } | |
9f40dead | 10875 | if ((data[4] = tg3_test_loopback(tp)) != 0) |
c76949a6 | 10876 | etest->flags |= ETH_TEST_FL_FAILED; |
a71116d1 | 10877 | |
f47c11ee DM |
10878 | tg3_full_unlock(tp); |
10879 | ||
d4bc3927 MC |
10880 | if (tg3_test_interrupt(tp) != 0) { |
10881 | etest->flags |= ETH_TEST_FL_FAILED; | |
10882 | data[5] = 1; | |
10883 | } | |
f47c11ee DM |
10884 | |
10885 | tg3_full_lock(tp, 0); | |
d4bc3927 | 10886 | |
a71116d1 MC |
10887 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
10888 | if (netif_running(dev)) { | |
10889 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; | |
b02fd9e3 MC |
10890 | err2 = tg3_restart_hw(tp, 1); |
10891 | if (!err2) | |
b9ec6c1b | 10892 | tg3_netif_start(tp); |
a71116d1 | 10893 | } |
f47c11ee DM |
10894 | |
10895 | tg3_full_unlock(tp); | |
b02fd9e3 MC |
10896 | |
10897 | if (irq_sync && !err2) | |
10898 | tg3_phy_start(tp); | |
a71116d1 | 10899 | } |
bc1c7567 MC |
10900 | if (tp->link_config.phy_is_low_power) |
10901 | tg3_set_power_state(tp, PCI_D3hot); | |
10902 | ||
4cafd3f5 MC |
10903 | } |
10904 | ||
1da177e4 LT |
10905 | static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
10906 | { | |
10907 | struct mii_ioctl_data *data = if_mii(ifr); | |
10908 | struct tg3 *tp = netdev_priv(dev); | |
10909 | int err; | |
10910 | ||
b02fd9e3 | 10911 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
3f0e3ad7 | 10912 | struct phy_device *phydev; |
b02fd9e3 MC |
10913 | if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)) |
10914 | return -EAGAIN; | |
3f0e3ad7 MC |
10915 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; |
10916 | return phy_mii_ioctl(phydev, data, cmd); | |
b02fd9e3 MC |
10917 | } |
10918 | ||
33f401ae | 10919 | switch (cmd) { |
1da177e4 | 10920 | case SIOCGMIIPHY: |
882e9793 | 10921 | data->phy_id = tp->phy_addr; |
1da177e4 LT |
10922 | |
10923 | /* fallthru */ | |
10924 | case SIOCGMIIREG: { | |
10925 | u32 mii_regval; | |
10926 | ||
10927 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
10928 | break; /* We have no PHY */ | |
10929 | ||
bc1c7567 MC |
10930 | if (tp->link_config.phy_is_low_power) |
10931 | return -EAGAIN; | |
10932 | ||
f47c11ee | 10933 | spin_lock_bh(&tp->lock); |
1da177e4 | 10934 | err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval); |
f47c11ee | 10935 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
10936 | |
10937 | data->val_out = mii_regval; | |
10938 | ||
10939 | return err; | |
10940 | } | |
10941 | ||
10942 | case SIOCSMIIREG: | |
10943 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
10944 | break; /* We have no PHY */ | |
10945 | ||
bc1c7567 MC |
10946 | if (tp->link_config.phy_is_low_power) |
10947 | return -EAGAIN; | |
10948 | ||
f47c11ee | 10949 | spin_lock_bh(&tp->lock); |
1da177e4 | 10950 | err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in); |
f47c11ee | 10951 | spin_unlock_bh(&tp->lock); |
1da177e4 LT |
10952 | |
10953 | return err; | |
10954 | ||
10955 | default: | |
10956 | /* do nothing */ | |
10957 | break; | |
10958 | } | |
10959 | return -EOPNOTSUPP; | |
10960 | } | |
10961 | ||
10962 | #if TG3_VLAN_TAG_USED | |
10963 | static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
10964 | { | |
10965 | struct tg3 *tp = netdev_priv(dev); | |
10966 | ||
844b3eed MC |
10967 | if (!netif_running(dev)) { |
10968 | tp->vlgrp = grp; | |
10969 | return; | |
10970 | } | |
10971 | ||
10972 | tg3_netif_stop(tp); | |
29315e87 | 10973 | |
f47c11ee | 10974 | tg3_full_lock(tp, 0); |
1da177e4 LT |
10975 | |
10976 | tp->vlgrp = grp; | |
10977 | ||
10978 | /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */ | |
10979 | __tg3_set_rx_mode(dev); | |
10980 | ||
844b3eed | 10981 | tg3_netif_start(tp); |
46966545 MC |
10982 | |
10983 | tg3_full_unlock(tp); | |
1da177e4 | 10984 | } |
1da177e4 LT |
10985 | #endif |
10986 | ||
15f9850d DM |
10987 | static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
10988 | { | |
10989 | struct tg3 *tp = netdev_priv(dev); | |
10990 | ||
10991 | memcpy(ec, &tp->coal, sizeof(*ec)); | |
10992 | return 0; | |
10993 | } | |
10994 | ||
d244c892 MC |
10995 | static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) |
10996 | { | |
10997 | struct tg3 *tp = netdev_priv(dev); | |
10998 | u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0; | |
10999 | u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0; | |
11000 | ||
11001 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) { | |
11002 | max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT; | |
11003 | max_txcoal_tick_int = MAX_TXCOAL_TICK_INT; | |
11004 | max_stat_coal_ticks = MAX_STAT_COAL_TICKS; | |
11005 | min_stat_coal_ticks = MIN_STAT_COAL_TICKS; | |
11006 | } | |
11007 | ||
11008 | if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || | |
11009 | (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || | |
11010 | (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || | |
11011 | (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || | |
11012 | (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || | |
11013 | (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || | |
11014 | (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || | |
11015 | (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || | |
11016 | (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || | |
11017 | (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) | |
11018 | return -EINVAL; | |
11019 | ||
11020 | /* No rx interrupts will be generated if both are zero */ | |
11021 | if ((ec->rx_coalesce_usecs == 0) && | |
11022 | (ec->rx_max_coalesced_frames == 0)) | |
11023 | return -EINVAL; | |
11024 | ||
11025 | /* No tx interrupts will be generated if both are zero */ | |
11026 | if ((ec->tx_coalesce_usecs == 0) && | |
11027 | (ec->tx_max_coalesced_frames == 0)) | |
11028 | return -EINVAL; | |
11029 | ||
11030 | /* Only copy relevant parameters, ignore all others. */ | |
11031 | tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; | |
11032 | tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; | |
11033 | tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; | |
11034 | tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; | |
11035 | tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; | |
11036 | tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; | |
11037 | tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; | |
11038 | tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; | |
11039 | tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; | |
11040 | ||
11041 | if (netif_running(dev)) { | |
11042 | tg3_full_lock(tp, 0); | |
11043 | __tg3_set_coalesce(tp, &tp->coal); | |
11044 | tg3_full_unlock(tp); | |
11045 | } | |
11046 | return 0; | |
11047 | } | |
11048 | ||
7282d491 | 11049 | static const struct ethtool_ops tg3_ethtool_ops = { |
1da177e4 LT |
11050 | .get_settings = tg3_get_settings, |
11051 | .set_settings = tg3_set_settings, | |
11052 | .get_drvinfo = tg3_get_drvinfo, | |
11053 | .get_regs_len = tg3_get_regs_len, | |
11054 | .get_regs = tg3_get_regs, | |
11055 | .get_wol = tg3_get_wol, | |
11056 | .set_wol = tg3_set_wol, | |
11057 | .get_msglevel = tg3_get_msglevel, | |
11058 | .set_msglevel = tg3_set_msglevel, | |
11059 | .nway_reset = tg3_nway_reset, | |
11060 | .get_link = ethtool_op_get_link, | |
11061 | .get_eeprom_len = tg3_get_eeprom_len, | |
11062 | .get_eeprom = tg3_get_eeprom, | |
11063 | .set_eeprom = tg3_set_eeprom, | |
11064 | .get_ringparam = tg3_get_ringparam, | |
11065 | .set_ringparam = tg3_set_ringparam, | |
11066 | .get_pauseparam = tg3_get_pauseparam, | |
11067 | .set_pauseparam = tg3_set_pauseparam, | |
11068 | .get_rx_csum = tg3_get_rx_csum, | |
11069 | .set_rx_csum = tg3_set_rx_csum, | |
1da177e4 | 11070 | .set_tx_csum = tg3_set_tx_csum, |
1da177e4 | 11071 | .set_sg = ethtool_op_set_sg, |
1da177e4 | 11072 | .set_tso = tg3_set_tso, |
4cafd3f5 | 11073 | .self_test = tg3_self_test, |
1da177e4 | 11074 | .get_strings = tg3_get_strings, |
4009a93d | 11075 | .phys_id = tg3_phys_id, |
1da177e4 | 11076 | .get_ethtool_stats = tg3_get_ethtool_stats, |
15f9850d | 11077 | .get_coalesce = tg3_get_coalesce, |
d244c892 | 11078 | .set_coalesce = tg3_set_coalesce, |
b9f2c044 | 11079 | .get_sset_count = tg3_get_sset_count, |
1da177e4 LT |
11080 | }; |
11081 | ||
11082 | static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |
11083 | { | |
1b27777a | 11084 | u32 cursize, val, magic; |
1da177e4 LT |
11085 | |
11086 | tp->nvram_size = EEPROM_CHIP_SIZE; | |
11087 | ||
e4f34110 | 11088 | if (tg3_nvram_read(tp, 0, &magic) != 0) |
1da177e4 LT |
11089 | return; |
11090 | ||
b16250e3 MC |
11091 | if ((magic != TG3_EEPROM_MAGIC) && |
11092 | ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) && | |
11093 | ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW)) | |
1da177e4 LT |
11094 | return; |
11095 | ||
11096 | /* | |
11097 | * Size the chip by reading offsets at increasing powers of two. | |
11098 | * When we encounter our validation signature, we know the addressing | |
11099 | * has wrapped around, and thus have our chip size. | |
11100 | */ | |
1b27777a | 11101 | cursize = 0x10; |
1da177e4 LT |
11102 | |
11103 | while (cursize < tp->nvram_size) { | |
e4f34110 | 11104 | if (tg3_nvram_read(tp, cursize, &val) != 0) |
1da177e4 LT |
11105 | return; |
11106 | ||
1820180b | 11107 | if (val == magic) |
1da177e4 LT |
11108 | break; |
11109 | ||
11110 | cursize <<= 1; | |
11111 | } | |
11112 | ||
11113 | tp->nvram_size = cursize; | |
11114 | } | |
6aa20a22 | 11115 | |
1da177e4 LT |
11116 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
11117 | { | |
11118 | u32 val; | |
11119 | ||
df259d8c MC |
11120 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
11121 | tg3_nvram_read(tp, 0, &val) != 0) | |
1b27777a MC |
11122 | return; |
11123 | ||
11124 | /* Selfboot format */ | |
1820180b | 11125 | if (val != TG3_EEPROM_MAGIC) { |
1b27777a MC |
11126 | tg3_get_eeprom_size(tp); |
11127 | return; | |
11128 | } | |
11129 | ||
6d348f2c | 11130 | if (tg3_nvram_read(tp, 0xf0, &val) == 0) { |
1da177e4 | 11131 | if (val != 0) { |
6d348f2c MC |
11132 | /* This is confusing. We want to operate on the |
11133 | * 16-bit value at offset 0xf2. The tg3_nvram_read() | |
11134 | * call will read from NVRAM and byteswap the data | |
11135 | * according to the byteswapping settings for all | |
11136 | * other register accesses. This ensures the data we | |
11137 | * want will always reside in the lower 16-bits. | |
11138 | * However, the data in NVRAM is in LE format, which | |
11139 | * means the data from the NVRAM read will always be | |
11140 | * opposite the endianness of the CPU. The 16-bit | |
11141 | * byteswap then brings the data to CPU endianness. | |
11142 | */ | |
11143 | tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; | |
1da177e4 LT |
11144 | return; |
11145 | } | |
11146 | } | |
fd1122a2 | 11147 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; |
1da177e4 LT |
11148 | } |
11149 | ||
11150 | static void __devinit tg3_get_nvram_info(struct tg3 *tp) | |
11151 | { | |
11152 | u32 nvcfg1; | |
11153 | ||
11154 | nvcfg1 = tr32(NVRAM_CFG1); | |
11155 | if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) { | |
11156 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
8590a603 | 11157 | } else { |
1da177e4 LT |
11158 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11159 | tw32(NVRAM_CFG1, nvcfg1); | |
11160 | } | |
11161 | ||
4c987487 | 11162 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) || |
a4e2b347 | 11163 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 | 11164 | switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { |
8590a603 MC |
11165 | case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: |
11166 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11167 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11168 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11169 | break; | |
11170 | case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED: | |
11171 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11172 | tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; | |
11173 | break; | |
11174 | case FLASH_VENDOR_ATMEL_EEPROM: | |
11175 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11176 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11177 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11178 | break; | |
11179 | case FLASH_VENDOR_ST: | |
11180 | tp->nvram_jedecnum = JEDEC_ST; | |
11181 | tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; | |
11182 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11183 | break; | |
11184 | case FLASH_VENDOR_SAIFUN: | |
11185 | tp->nvram_jedecnum = JEDEC_SAIFUN; | |
11186 | tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; | |
11187 | break; | |
11188 | case FLASH_VENDOR_SST_SMALL: | |
11189 | case FLASH_VENDOR_SST_LARGE: | |
11190 | tp->nvram_jedecnum = JEDEC_SST; | |
11191 | tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; | |
11192 | break; | |
1da177e4 | 11193 | } |
8590a603 | 11194 | } else { |
1da177e4 LT |
11195 | tp->nvram_jedecnum = JEDEC_ATMEL; |
11196 | tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; | |
11197 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11198 | } | |
11199 | } | |
11200 | ||
a1b950d5 MC |
11201 | static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) |
11202 | { | |
11203 | switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) { | |
11204 | case FLASH_5752PAGE_SIZE_256: | |
11205 | tp->nvram_pagesize = 256; | |
11206 | break; | |
11207 | case FLASH_5752PAGE_SIZE_512: | |
11208 | tp->nvram_pagesize = 512; | |
11209 | break; | |
11210 | case FLASH_5752PAGE_SIZE_1K: | |
11211 | tp->nvram_pagesize = 1024; | |
11212 | break; | |
11213 | case FLASH_5752PAGE_SIZE_2K: | |
11214 | tp->nvram_pagesize = 2048; | |
11215 | break; | |
11216 | case FLASH_5752PAGE_SIZE_4K: | |
11217 | tp->nvram_pagesize = 4096; | |
11218 | break; | |
11219 | case FLASH_5752PAGE_SIZE_264: | |
11220 | tp->nvram_pagesize = 264; | |
11221 | break; | |
11222 | case FLASH_5752PAGE_SIZE_528: | |
11223 | tp->nvram_pagesize = 528; | |
11224 | break; | |
11225 | } | |
11226 | } | |
11227 | ||
361b4ac2 MC |
11228 | static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp) |
11229 | { | |
11230 | u32 nvcfg1; | |
11231 | ||
11232 | nvcfg1 = tr32(NVRAM_CFG1); | |
11233 | ||
e6af301b MC |
11234 | /* NVRAM protection for TPM */ |
11235 | if (nvcfg1 & (1 << 27)) | |
f66a29b0 | 11236 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
e6af301b | 11237 | |
361b4ac2 | 11238 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { |
8590a603 MC |
11239 | case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ: |
11240 | case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ: | |
11241 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11242 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11243 | break; | |
11244 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11245 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11246 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11247 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11248 | break; | |
11249 | case FLASH_5752VENDOR_ST_M45PE10: | |
11250 | case FLASH_5752VENDOR_ST_M45PE20: | |
11251 | case FLASH_5752VENDOR_ST_M45PE40: | |
11252 | tp->nvram_jedecnum = JEDEC_ST; | |
11253 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11254 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11255 | break; | |
361b4ac2 MC |
11256 | } |
11257 | ||
11258 | if (tp->tg3_flags2 & TG3_FLG2_FLASH) { | |
a1b950d5 | 11259 | tg3_nvram_get_pagesize(tp, nvcfg1); |
8590a603 | 11260 | } else { |
361b4ac2 MC |
11261 | /* For eeprom, set pagesize to maximum eeprom size */ |
11262 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11263 | ||
11264 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11265 | tw32(NVRAM_CFG1, nvcfg1); | |
11266 | } | |
11267 | } | |
11268 | ||
d3c7b886 MC |
11269 | static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp) |
11270 | { | |
989a9d23 | 11271 | u32 nvcfg1, protect = 0; |
d3c7b886 MC |
11272 | |
11273 | nvcfg1 = tr32(NVRAM_CFG1); | |
11274 | ||
11275 | /* NVRAM protection for TPM */ | |
989a9d23 | 11276 | if (nvcfg1 & (1 << 27)) { |
f66a29b0 | 11277 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
989a9d23 MC |
11278 | protect = 1; |
11279 | } | |
d3c7b886 | 11280 | |
989a9d23 MC |
11281 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; |
11282 | switch (nvcfg1) { | |
8590a603 MC |
11283 | case FLASH_5755VENDOR_ATMEL_FLASH_1: |
11284 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11285 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11286 | case FLASH_5755VENDOR_ATMEL_FLASH_5: | |
11287 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11288 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11289 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11290 | tp->nvram_pagesize = 264; | |
11291 | if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 || | |
11292 | nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5) | |
11293 | tp->nvram_size = (protect ? 0x3e200 : | |
11294 | TG3_NVRAM_SIZE_512KB); | |
11295 | else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2) | |
11296 | tp->nvram_size = (protect ? 0x1f200 : | |
11297 | TG3_NVRAM_SIZE_256KB); | |
11298 | else | |
11299 | tp->nvram_size = (protect ? 0x1f200 : | |
11300 | TG3_NVRAM_SIZE_128KB); | |
11301 | break; | |
11302 | case FLASH_5752VENDOR_ST_M45PE10: | |
11303 | case FLASH_5752VENDOR_ST_M45PE20: | |
11304 | case FLASH_5752VENDOR_ST_M45PE40: | |
11305 | tp->nvram_jedecnum = JEDEC_ST; | |
11306 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11307 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11308 | tp->nvram_pagesize = 256; | |
11309 | if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10) | |
11310 | tp->nvram_size = (protect ? | |
11311 | TG3_NVRAM_SIZE_64KB : | |
11312 | TG3_NVRAM_SIZE_128KB); | |
11313 | else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20) | |
11314 | tp->nvram_size = (protect ? | |
11315 | TG3_NVRAM_SIZE_64KB : | |
11316 | TG3_NVRAM_SIZE_256KB); | |
11317 | else | |
11318 | tp->nvram_size = (protect ? | |
11319 | TG3_NVRAM_SIZE_128KB : | |
11320 | TG3_NVRAM_SIZE_512KB); | |
11321 | break; | |
d3c7b886 MC |
11322 | } |
11323 | } | |
11324 | ||
1b27777a MC |
11325 | static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp) |
11326 | { | |
11327 | u32 nvcfg1; | |
11328 | ||
11329 | nvcfg1 = tr32(NVRAM_CFG1); | |
11330 | ||
11331 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
8590a603 MC |
11332 | case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ: |
11333 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11334 | case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ: | |
11335 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11336 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11337 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11338 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
1b27777a | 11339 | |
8590a603 MC |
11340 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; |
11341 | tw32(NVRAM_CFG1, nvcfg1); | |
11342 | break; | |
11343 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11344 | case FLASH_5755VENDOR_ATMEL_FLASH_1: | |
11345 | case FLASH_5755VENDOR_ATMEL_FLASH_2: | |
11346 | case FLASH_5755VENDOR_ATMEL_FLASH_3: | |
11347 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11348 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11349 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11350 | tp->nvram_pagesize = 264; | |
11351 | break; | |
11352 | case FLASH_5752VENDOR_ST_M45PE10: | |
11353 | case FLASH_5752VENDOR_ST_M45PE20: | |
11354 | case FLASH_5752VENDOR_ST_M45PE40: | |
11355 | tp->nvram_jedecnum = JEDEC_ST; | |
11356 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11357 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11358 | tp->nvram_pagesize = 256; | |
11359 | break; | |
1b27777a MC |
11360 | } |
11361 | } | |
11362 | ||
6b91fa02 MC |
11363 | static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp) |
11364 | { | |
11365 | u32 nvcfg1, protect = 0; | |
11366 | ||
11367 | nvcfg1 = tr32(NVRAM_CFG1); | |
11368 | ||
11369 | /* NVRAM protection for TPM */ | |
11370 | if (nvcfg1 & (1 << 27)) { | |
f66a29b0 | 11371 | tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM; |
6b91fa02 MC |
11372 | protect = 1; |
11373 | } | |
11374 | ||
11375 | nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK; | |
11376 | switch (nvcfg1) { | |
8590a603 MC |
11377 | case FLASH_5761VENDOR_ATMEL_ADB021D: |
11378 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11379 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11380 | case FLASH_5761VENDOR_ATMEL_ADB161D: | |
11381 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11382 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11383 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11384 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11385 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11386 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11387 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11388 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
11389 | tp->nvram_pagesize = 256; | |
11390 | break; | |
11391 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11392 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11393 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11394 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11395 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11396 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11397 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11398 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11399 | tp->nvram_jedecnum = JEDEC_ST; | |
11400 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11401 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11402 | tp->nvram_pagesize = 256; | |
11403 | break; | |
6b91fa02 MC |
11404 | } |
11405 | ||
11406 | if (protect) { | |
11407 | tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); | |
11408 | } else { | |
11409 | switch (nvcfg1) { | |
8590a603 MC |
11410 | case FLASH_5761VENDOR_ATMEL_ADB161D: |
11411 | case FLASH_5761VENDOR_ATMEL_MDB161D: | |
11412 | case FLASH_5761VENDOR_ST_A_M45PE16: | |
11413 | case FLASH_5761VENDOR_ST_M_M45PE16: | |
11414 | tp->nvram_size = TG3_NVRAM_SIZE_2MB; | |
11415 | break; | |
11416 | case FLASH_5761VENDOR_ATMEL_ADB081D: | |
11417 | case FLASH_5761VENDOR_ATMEL_MDB081D: | |
11418 | case FLASH_5761VENDOR_ST_A_M45PE80: | |
11419 | case FLASH_5761VENDOR_ST_M_M45PE80: | |
11420 | tp->nvram_size = TG3_NVRAM_SIZE_1MB; | |
11421 | break; | |
11422 | case FLASH_5761VENDOR_ATMEL_ADB041D: | |
11423 | case FLASH_5761VENDOR_ATMEL_MDB041D: | |
11424 | case FLASH_5761VENDOR_ST_A_M45PE40: | |
11425 | case FLASH_5761VENDOR_ST_M_M45PE40: | |
11426 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11427 | break; | |
11428 | case FLASH_5761VENDOR_ATMEL_ADB021D: | |
11429 | case FLASH_5761VENDOR_ATMEL_MDB021D: | |
11430 | case FLASH_5761VENDOR_ST_A_M45PE20: | |
11431 | case FLASH_5761VENDOR_ST_M_M45PE20: | |
11432 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11433 | break; | |
6b91fa02 MC |
11434 | } |
11435 | } | |
11436 | } | |
11437 | ||
b5d3772c MC |
11438 | static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp) |
11439 | { | |
11440 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11441 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11442 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11443 | } | |
11444 | ||
321d32a0 MC |
11445 | static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp) |
11446 | { | |
11447 | u32 nvcfg1; | |
11448 | ||
11449 | nvcfg1 = tr32(NVRAM_CFG1); | |
11450 | ||
11451 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11452 | case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ: | |
11453 | case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ: | |
11454 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11455 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11456 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11457 | ||
11458 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11459 | tw32(NVRAM_CFG1, nvcfg1); | |
11460 | return; | |
11461 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11462 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11463 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11464 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11465 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11466 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11467 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11468 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11469 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11470 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11471 | ||
11472 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11473 | case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED: | |
11474 | case FLASH_57780VENDOR_ATMEL_AT45DB011D: | |
11475 | case FLASH_57780VENDOR_ATMEL_AT45DB011B: | |
11476 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11477 | break; | |
11478 | case FLASH_57780VENDOR_ATMEL_AT45DB021D: | |
11479 | case FLASH_57780VENDOR_ATMEL_AT45DB021B: | |
11480 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11481 | break; | |
11482 | case FLASH_57780VENDOR_ATMEL_AT45DB041D: | |
11483 | case FLASH_57780VENDOR_ATMEL_AT45DB041B: | |
11484 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11485 | break; | |
11486 | } | |
11487 | break; | |
11488 | case FLASH_5752VENDOR_ST_M45PE10: | |
11489 | case FLASH_5752VENDOR_ST_M45PE20: | |
11490 | case FLASH_5752VENDOR_ST_M45PE40: | |
11491 | tp->nvram_jedecnum = JEDEC_ST; | |
11492 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11493 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11494 | ||
11495 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11496 | case FLASH_5752VENDOR_ST_M45PE10: | |
11497 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11498 | break; | |
11499 | case FLASH_5752VENDOR_ST_M45PE20: | |
11500 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11501 | break; | |
11502 | case FLASH_5752VENDOR_ST_M45PE40: | |
11503 | tp->nvram_size = TG3_NVRAM_SIZE_512KB; | |
11504 | break; | |
11505 | } | |
11506 | break; | |
11507 | default: | |
df259d8c | 11508 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; |
321d32a0 MC |
11509 | return; |
11510 | } | |
11511 | ||
a1b950d5 MC |
11512 | tg3_nvram_get_pagesize(tp, nvcfg1); |
11513 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
321d32a0 | 11514 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; |
a1b950d5 MC |
11515 | } |
11516 | ||
11517 | ||
11518 | static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp) | |
11519 | { | |
11520 | u32 nvcfg1; | |
11521 | ||
11522 | nvcfg1 = tr32(NVRAM_CFG1); | |
11523 | ||
11524 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11525 | case FLASH_5717VENDOR_ATMEL_EEPROM: | |
11526 | case FLASH_5717VENDOR_MICRO_EEPROM: | |
11527 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11528 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11529 | tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; | |
11530 | ||
11531 | nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS; | |
11532 | tw32(NVRAM_CFG1, nvcfg1); | |
11533 | return; | |
11534 | case FLASH_5717VENDOR_ATMEL_MDB011D: | |
11535 | case FLASH_5717VENDOR_ATMEL_ADB011B: | |
11536 | case FLASH_5717VENDOR_ATMEL_ADB011D: | |
11537 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11538 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11539 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11540 | case FLASH_5717VENDOR_ATMEL_45USPT: | |
11541 | tp->nvram_jedecnum = JEDEC_ATMEL; | |
11542 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11543 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11544 | ||
11545 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11546 | case FLASH_5717VENDOR_ATMEL_MDB021D: | |
11547 | case FLASH_5717VENDOR_ATMEL_ADB021B: | |
11548 | case FLASH_5717VENDOR_ATMEL_ADB021D: | |
11549 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11550 | break; | |
11551 | default: | |
11552 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11553 | break; | |
11554 | } | |
321d32a0 | 11555 | break; |
a1b950d5 MC |
11556 | case FLASH_5717VENDOR_ST_M_M25PE10: |
11557 | case FLASH_5717VENDOR_ST_A_M25PE10: | |
11558 | case FLASH_5717VENDOR_ST_M_M45PE10: | |
11559 | case FLASH_5717VENDOR_ST_A_M45PE10: | |
11560 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11561 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11562 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11563 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11564 | case FLASH_5717VENDOR_ST_25USPT: | |
11565 | case FLASH_5717VENDOR_ST_45USPT: | |
11566 | tp->nvram_jedecnum = JEDEC_ST; | |
11567 | tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED; | |
11568 | tp->tg3_flags2 |= TG3_FLG2_FLASH; | |
11569 | ||
11570 | switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) { | |
11571 | case FLASH_5717VENDOR_ST_M_M25PE20: | |
11572 | case FLASH_5717VENDOR_ST_A_M25PE20: | |
11573 | case FLASH_5717VENDOR_ST_M_M45PE20: | |
11574 | case FLASH_5717VENDOR_ST_A_M45PE20: | |
11575 | tp->nvram_size = TG3_NVRAM_SIZE_256KB; | |
11576 | break; | |
11577 | default: | |
11578 | tp->nvram_size = TG3_NVRAM_SIZE_128KB; | |
11579 | break; | |
11580 | } | |
321d32a0 | 11581 | break; |
a1b950d5 MC |
11582 | default: |
11583 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM; | |
11584 | return; | |
321d32a0 | 11585 | } |
a1b950d5 MC |
11586 | |
11587 | tg3_nvram_get_pagesize(tp, nvcfg1); | |
11588 | if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) | |
11589 | tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; | |
321d32a0 MC |
11590 | } |
11591 | ||
1da177e4 LT |
11592 | /* Chips other than 5700/5701 use the NVRAM for fetching info. */ |
11593 | static void __devinit tg3_nvram_init(struct tg3 *tp) | |
11594 | { | |
1da177e4 LT |
11595 | tw32_f(GRC_EEPROM_ADDR, |
11596 | (EEPROM_ADDR_FSM_RESET | | |
11597 | (EEPROM_DEFAULT_CLOCK_PERIOD << | |
11598 | EEPROM_ADDR_CLKPERD_SHIFT))); | |
11599 | ||
9d57f01c | 11600 | msleep(1); |
1da177e4 LT |
11601 | |
11602 | /* Enable seeprom accesses. */ | |
11603 | tw32_f(GRC_LOCAL_CTRL, | |
11604 | tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM); | |
11605 | udelay(100); | |
11606 | ||
11607 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
11608 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { | |
11609 | tp->tg3_flags |= TG3_FLAG_NVRAM; | |
11610 | ||
ec41c7df | 11611 | if (tg3_nvram_lock(tp)) { |
5129c3a3 MC |
11612 | netdev_warn(tp->dev, |
11613 | "Cannot get nvram lock, %s failed\n", | |
05dbe005 | 11614 | __func__); |
ec41c7df MC |
11615 | return; |
11616 | } | |
e6af301b | 11617 | tg3_enable_nvram_access(tp); |
1da177e4 | 11618 | |
989a9d23 MC |
11619 | tp->nvram_size = 0; |
11620 | ||
361b4ac2 MC |
11621 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) |
11622 | tg3_get_5752_nvram_info(tp); | |
d3c7b886 MC |
11623 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) |
11624 | tg3_get_5755_nvram_info(tp); | |
d30cdd28 | 11625 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
57e6983c MC |
11626 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
11627 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) | |
1b27777a | 11628 | tg3_get_5787_nvram_info(tp); |
6b91fa02 MC |
11629 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) |
11630 | tg3_get_5761_nvram_info(tp); | |
b5d3772c MC |
11631 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
11632 | tg3_get_5906_nvram_info(tp); | |
b703df6f MC |
11633 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
11634 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 | 11635 | tg3_get_57780_nvram_info(tp); |
a1b950d5 MC |
11636 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
11637 | tg3_get_5717_nvram_info(tp); | |
361b4ac2 MC |
11638 | else |
11639 | tg3_get_nvram_info(tp); | |
11640 | ||
989a9d23 MC |
11641 | if (tp->nvram_size == 0) |
11642 | tg3_get_nvram_size(tp); | |
1da177e4 | 11643 | |
e6af301b | 11644 | tg3_disable_nvram_access(tp); |
381291b7 | 11645 | tg3_nvram_unlock(tp); |
1da177e4 LT |
11646 | |
11647 | } else { | |
11648 | tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED); | |
11649 | ||
11650 | tg3_get_eeprom_size(tp); | |
11651 | } | |
11652 | } | |
11653 | ||
1da177e4 LT |
11654 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
11655 | u32 offset, u32 len, u8 *buf) | |
11656 | { | |
11657 | int i, j, rc = 0; | |
11658 | u32 val; | |
11659 | ||
11660 | for (i = 0; i < len; i += 4) { | |
b9fc7dc5 | 11661 | u32 addr; |
a9dc529d | 11662 | __be32 data; |
1da177e4 LT |
11663 | |
11664 | addr = offset + i; | |
11665 | ||
11666 | memcpy(&data, buf + i, 4); | |
11667 | ||
62cedd11 MC |
11668 | /* |
11669 | * The SEEPROM interface expects the data to always be opposite | |
11670 | * the native endian format. We accomplish this by reversing | |
11671 | * all the operations that would have been performed on the | |
11672 | * data from a call to tg3_nvram_read_be32(). | |
11673 | */ | |
11674 | tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data))); | |
1da177e4 LT |
11675 | |
11676 | val = tr32(GRC_EEPROM_ADDR); | |
11677 | tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE); | |
11678 | ||
11679 | val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK | | |
11680 | EEPROM_ADDR_READ); | |
11681 | tw32(GRC_EEPROM_ADDR, val | | |
11682 | (0 << EEPROM_ADDR_DEVID_SHIFT) | | |
11683 | (addr & EEPROM_ADDR_ADDR_MASK) | | |
11684 | EEPROM_ADDR_START | | |
11685 | EEPROM_ADDR_WRITE); | |
6aa20a22 | 11686 | |
9d57f01c | 11687 | for (j = 0; j < 1000; j++) { |
1da177e4 LT |
11688 | val = tr32(GRC_EEPROM_ADDR); |
11689 | ||
11690 | if (val & EEPROM_ADDR_COMPLETE) | |
11691 | break; | |
9d57f01c | 11692 | msleep(1); |
1da177e4 LT |
11693 | } |
11694 | if (!(val & EEPROM_ADDR_COMPLETE)) { | |
11695 | rc = -EBUSY; | |
11696 | break; | |
11697 | } | |
11698 | } | |
11699 | ||
11700 | return rc; | |
11701 | } | |
11702 | ||
11703 | /* offset and length are dword aligned */ | |
11704 | static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |
11705 | u8 *buf) | |
11706 | { | |
11707 | int ret = 0; | |
11708 | u32 pagesize = tp->nvram_pagesize; | |
11709 | u32 pagemask = pagesize - 1; | |
11710 | u32 nvram_cmd; | |
11711 | u8 *tmp; | |
11712 | ||
11713 | tmp = kmalloc(pagesize, GFP_KERNEL); | |
11714 | if (tmp == NULL) | |
11715 | return -ENOMEM; | |
11716 | ||
11717 | while (len) { | |
11718 | int j; | |
e6af301b | 11719 | u32 phy_addr, page_off, size; |
1da177e4 LT |
11720 | |
11721 | phy_addr = offset & ~pagemask; | |
6aa20a22 | 11722 | |
1da177e4 | 11723 | for (j = 0; j < pagesize; j += 4) { |
a9dc529d MC |
11724 | ret = tg3_nvram_read_be32(tp, phy_addr + j, |
11725 | (__be32 *) (tmp + j)); | |
11726 | if (ret) | |
1da177e4 LT |
11727 | break; |
11728 | } | |
11729 | if (ret) | |
11730 | break; | |
11731 | ||
c6cdf436 | 11732 | page_off = offset & pagemask; |
1da177e4 LT |
11733 | size = pagesize; |
11734 | if (len < size) | |
11735 | size = len; | |
11736 | ||
11737 | len -= size; | |
11738 | ||
11739 | memcpy(tmp + page_off, buf, size); | |
11740 | ||
11741 | offset = offset + (pagesize - page_off); | |
11742 | ||
e6af301b | 11743 | tg3_enable_nvram_access(tp); |
1da177e4 LT |
11744 | |
11745 | /* | |
11746 | * Before we can erase the flash page, we need | |
11747 | * to issue a special "write enable" command. | |
11748 | */ | |
11749 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11750 | ||
11751 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11752 | break; | |
11753 | ||
11754 | /* Erase the target page */ | |
11755 | tw32(NVRAM_ADDR, phy_addr); | |
11756 | ||
11757 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR | | |
11758 | NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE; | |
11759 | ||
c6cdf436 | 11760 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) |
1da177e4 LT |
11761 | break; |
11762 | ||
11763 | /* Issue another write enable to start the write. */ | |
11764 | nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11765 | ||
11766 | if (tg3_nvram_exec_cmd(tp, nvram_cmd)) | |
11767 | break; | |
11768 | ||
11769 | for (j = 0; j < pagesize; j += 4) { | |
b9fc7dc5 | 11770 | __be32 data; |
1da177e4 | 11771 | |
b9fc7dc5 | 11772 | data = *((__be32 *) (tmp + j)); |
a9dc529d | 11773 | |
b9fc7dc5 | 11774 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 LT |
11775 | |
11776 | tw32(NVRAM_ADDR, phy_addr + j); | |
11777 | ||
11778 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | | |
11779 | NVRAM_CMD_WR; | |
11780 | ||
11781 | if (j == 0) | |
11782 | nvram_cmd |= NVRAM_CMD_FIRST; | |
11783 | else if (j == (pagesize - 4)) | |
11784 | nvram_cmd |= NVRAM_CMD_LAST; | |
11785 | ||
11786 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
11787 | break; | |
11788 | } | |
11789 | if (ret) | |
11790 | break; | |
11791 | } | |
11792 | ||
11793 | nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE; | |
11794 | tg3_nvram_exec_cmd(tp, nvram_cmd); | |
11795 | ||
11796 | kfree(tmp); | |
11797 | ||
11798 | return ret; | |
11799 | } | |
11800 | ||
11801 | /* offset and length are dword aligned */ | |
11802 | static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |
11803 | u8 *buf) | |
11804 | { | |
11805 | int i, ret = 0; | |
11806 | ||
11807 | for (i = 0; i < len; i += 4, offset += 4) { | |
b9fc7dc5 AV |
11808 | u32 page_off, phy_addr, nvram_cmd; |
11809 | __be32 data; | |
1da177e4 LT |
11810 | |
11811 | memcpy(&data, buf + i, 4); | |
b9fc7dc5 | 11812 | tw32(NVRAM_WRDATA, be32_to_cpu(data)); |
1da177e4 | 11813 | |
c6cdf436 | 11814 | page_off = offset % tp->nvram_pagesize; |
1da177e4 | 11815 | |
1820180b | 11816 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
1da177e4 LT |
11817 | |
11818 | tw32(NVRAM_ADDR, phy_addr); | |
11819 | ||
11820 | nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR; | |
11821 | ||
c6cdf436 | 11822 | if (page_off == 0 || i == 0) |
1da177e4 | 11823 | nvram_cmd |= NVRAM_CMD_FIRST; |
f6d9a256 | 11824 | if (page_off == (tp->nvram_pagesize - 4)) |
1da177e4 LT |
11825 | nvram_cmd |= NVRAM_CMD_LAST; |
11826 | ||
11827 | if (i == (len - 4)) | |
11828 | nvram_cmd |= NVRAM_CMD_LAST; | |
11829 | ||
321d32a0 MC |
11830 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && |
11831 | !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && | |
4c987487 MC |
11832 | (tp->nvram_jedecnum == JEDEC_ST) && |
11833 | (nvram_cmd & NVRAM_CMD_FIRST)) { | |
1da177e4 LT |
11834 | |
11835 | if ((ret = tg3_nvram_exec_cmd(tp, | |
11836 | NVRAM_CMD_WREN | NVRAM_CMD_GO | | |
11837 | NVRAM_CMD_DONE))) | |
11838 | ||
11839 | break; | |
11840 | } | |
11841 | if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
11842 | /* We always do complete word writes to eeprom. */ | |
11843 | nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST); | |
11844 | } | |
11845 | ||
11846 | if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd))) | |
11847 | break; | |
11848 | } | |
11849 | return ret; | |
11850 | } | |
11851 | ||
11852 | /* offset and length are dword aligned */ | |
11853 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) | |
11854 | { | |
11855 | int ret; | |
11856 | ||
1da177e4 | 11857 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { |
314fba34 MC |
11858 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & |
11859 | ~GRC_LCLCTRL_GPIO_OUTPUT1); | |
1da177e4 LT |
11860 | udelay(40); |
11861 | } | |
11862 | ||
11863 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) { | |
11864 | ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); | |
859a5887 | 11865 | } else { |
1da177e4 LT |
11866 | u32 grc_mode; |
11867 | ||
ec41c7df MC |
11868 | ret = tg3_nvram_lock(tp); |
11869 | if (ret) | |
11870 | return ret; | |
1da177e4 | 11871 | |
e6af301b MC |
11872 | tg3_enable_nvram_access(tp); |
11873 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && | |
f66a29b0 | 11874 | !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) |
1da177e4 | 11875 | tw32(NVRAM_WRITE1, 0x406); |
1da177e4 LT |
11876 | |
11877 | grc_mode = tr32(GRC_MODE); | |
11878 | tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE); | |
11879 | ||
11880 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) || | |
11881 | !(tp->tg3_flags2 & TG3_FLG2_FLASH)) { | |
11882 | ||
11883 | ret = tg3_nvram_write_block_buffered(tp, offset, len, | |
11884 | buf); | |
859a5887 | 11885 | } else { |
1da177e4 LT |
11886 | ret = tg3_nvram_write_block_unbuffered(tp, offset, len, |
11887 | buf); | |
11888 | } | |
11889 | ||
11890 | grc_mode = tr32(GRC_MODE); | |
11891 | tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); | |
11892 | ||
e6af301b | 11893 | tg3_disable_nvram_access(tp); |
1da177e4 LT |
11894 | tg3_nvram_unlock(tp); |
11895 | } | |
11896 | ||
11897 | if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) { | |
314fba34 | 11898 | tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); |
1da177e4 LT |
11899 | udelay(40); |
11900 | } | |
11901 | ||
11902 | return ret; | |
11903 | } | |
11904 | ||
11905 | struct subsys_tbl_ent { | |
11906 | u16 subsys_vendor, subsys_devid; | |
11907 | u32 phy_id; | |
11908 | }; | |
11909 | ||
24daf2b0 | 11910 | static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = { |
1da177e4 | 11911 | /* Broadcom boards. */ |
24daf2b0 | 11912 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 11913 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 11914 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 11915 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 11916 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 11917 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 }, |
24daf2b0 MC |
11918 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
11919 | TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 }, | |
11920 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 11921 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 11922 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 11923 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
11924 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
11925 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 }, | |
11926 | { TG3PCI_SUBVENDOR_ID_BROADCOM, | |
79eb6904 | 11927 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 11928 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 11929 | TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 11930 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 11931 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 }, |
24daf2b0 | 11932 | { TG3PCI_SUBVENDOR_ID_BROADCOM, |
79eb6904 | 11933 | TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 }, |
1da177e4 LT |
11934 | |
11935 | /* 3com boards. */ | |
24daf2b0 | 11936 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 11937 | TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 11938 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 11939 | TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
11940 | { TG3PCI_SUBVENDOR_ID_3COM, |
11941 | TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 }, | |
11942 | { TG3PCI_SUBVENDOR_ID_3COM, | |
79eb6904 | 11943 | TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 11944 | { TG3PCI_SUBVENDOR_ID_3COM, |
79eb6904 | 11945 | TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
11946 | |
11947 | /* DELL boards. */ | |
24daf2b0 | 11948 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 11949 | TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 11950 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 11951 | TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 }, |
24daf2b0 | 11952 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 11953 | TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 }, |
24daf2b0 | 11954 | { TG3PCI_SUBVENDOR_ID_DELL, |
79eb6904 | 11955 | TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 }, |
1da177e4 LT |
11956 | |
11957 | /* Compaq boards. */ | |
24daf2b0 | 11958 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 11959 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 11960 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 11961 | TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 }, |
24daf2b0 MC |
11962 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
11963 | TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 }, | |
11964 | { TG3PCI_SUBVENDOR_ID_COMPAQ, | |
79eb6904 | 11965 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 }, |
24daf2b0 | 11966 | { TG3PCI_SUBVENDOR_ID_COMPAQ, |
79eb6904 | 11967 | TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 }, |
1da177e4 LT |
11968 | |
11969 | /* IBM boards. */ | |
24daf2b0 MC |
11970 | { TG3PCI_SUBVENDOR_ID_IBM, |
11971 | TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 } | |
1da177e4 LT |
11972 | }; |
11973 | ||
24daf2b0 | 11974 | static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp) |
1da177e4 LT |
11975 | { |
11976 | int i; | |
11977 | ||
11978 | for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) { | |
11979 | if ((subsys_id_to_phy_id[i].subsys_vendor == | |
11980 | tp->pdev->subsystem_vendor) && | |
11981 | (subsys_id_to_phy_id[i].subsys_devid == | |
11982 | tp->pdev->subsystem_device)) | |
11983 | return &subsys_id_to_phy_id[i]; | |
11984 | } | |
11985 | return NULL; | |
11986 | } | |
11987 | ||
7d0c41ef | 11988 | static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) |
1da177e4 | 11989 | { |
1da177e4 | 11990 | u32 val; |
caf636c7 MC |
11991 | u16 pmcsr; |
11992 | ||
11993 | /* On some early chips the SRAM cannot be accessed in D3hot state, | |
11994 | * so need make sure we're in D0. | |
11995 | */ | |
11996 | pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr); | |
11997 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
11998 | pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr); | |
11999 | msleep(1); | |
7d0c41ef MC |
12000 | |
12001 | /* Make sure register accesses (indirect or otherwise) | |
12002 | * will function correctly. | |
12003 | */ | |
12004 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12005 | tp->misc_host_ctrl); | |
1da177e4 | 12006 | |
f49639e6 DM |
12007 | /* The memory arbiter has to be enabled in order for SRAM accesses |
12008 | * to succeed. Normally on powerup the tg3 chip firmware will make | |
12009 | * sure it is enabled, but other entities such as system netboot | |
12010 | * code might disable it. | |
12011 | */ | |
12012 | val = tr32(MEMARB_MODE); | |
12013 | tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE); | |
12014 | ||
79eb6904 | 12015 | tp->phy_id = TG3_PHY_ID_INVALID; |
7d0c41ef MC |
12016 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; |
12017 | ||
a85feb8c GZ |
12018 | /* Assume an onboard device and WOL capable by default. */ |
12019 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP; | |
72b845e0 | 12020 | |
b5d3772c | 12021 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
9d26e213 | 12022 | if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { |
b5d3772c | 12023 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12024 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12025 | } | |
0527ba35 MC |
12026 | val = tr32(VCPU_CFGSHDW); |
12027 | if (val & VCPU_CFGSHDW_ASPM_DBNC) | |
8ed5d97e | 12028 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; |
0527ba35 | 12029 | if ((val & VCPU_CFGSHDW_WOL_ENABLE) && |
2023276e | 12030 | (val & VCPU_CFGSHDW_WOL_MAGPKT)) |
0527ba35 | 12031 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
05ac4cb7 | 12032 | goto done; |
b5d3772c MC |
12033 | } |
12034 | ||
1da177e4 LT |
12035 | tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); |
12036 | if (val == NIC_SRAM_DATA_SIG_MAGIC) { | |
12037 | u32 nic_cfg, led_cfg; | |
a9daf367 | 12038 | u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id; |
7d0c41ef | 12039 | int eeprom_phy_serdes = 0; |
1da177e4 LT |
12040 | |
12041 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); | |
12042 | tp->nic_sram_data_cfg = nic_cfg; | |
12043 | ||
12044 | tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); | |
12045 | ver >>= NIC_SRAM_DATA_VER_SHIFT; | |
12046 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) && | |
12047 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) && | |
12048 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) && | |
12049 | (ver > 0) && (ver < 0x100)) | |
12050 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); | |
12051 | ||
a9daf367 MC |
12052 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) |
12053 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); | |
12054 | ||
1da177e4 LT |
12055 | if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) == |
12056 | NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) | |
12057 | eeprom_phy_serdes = 1; | |
12058 | ||
12059 | tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); | |
12060 | if (nic_phy_id != 0) { | |
12061 | u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK; | |
12062 | u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK; | |
12063 | ||
12064 | eeprom_phy_id = (id1 >> 16) << 10; | |
12065 | eeprom_phy_id |= (id2 & 0xfc00) << 16; | |
12066 | eeprom_phy_id |= (id2 & 0x03ff) << 0; | |
12067 | } else | |
12068 | eeprom_phy_id = 0; | |
12069 | ||
7d0c41ef | 12070 | tp->phy_id = eeprom_phy_id; |
747e8f8b | 12071 | if (eeprom_phy_serdes) { |
d1ec96af MC |
12072 | if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
12073 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
747e8f8b MC |
12074 | tp->tg3_flags2 |= TG3_FLG2_MII_SERDES; |
12075 | else | |
12076 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; | |
12077 | } | |
7d0c41ef | 12078 | |
cbf46853 | 12079 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12080 | led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | |
12081 | SHASTA_EXT_LED_MODE_MASK); | |
cbf46853 | 12082 | else |
1da177e4 LT |
12083 | led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; |
12084 | ||
12085 | switch (led_cfg) { | |
12086 | default: | |
12087 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1: | |
12088 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12089 | break; | |
12090 | ||
12091 | case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2: | |
12092 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12093 | break; | |
12094 | ||
12095 | case NIC_SRAM_DATA_CFG_LED_MODE_MAC: | |
12096 | tp->led_ctrl = LED_CTRL_MODE_MAC; | |
9ba27794 MC |
12097 | |
12098 | /* Default to PHY_1_MODE if 0 (MAC_MODE) is | |
12099 | * read on some older 5700/5701 bootcode. | |
12100 | */ | |
12101 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12102 | ASIC_REV_5700 || | |
12103 | GET_ASIC_REV(tp->pci_chip_rev_id) == | |
12104 | ASIC_REV_5701) | |
12105 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
12106 | ||
1da177e4 LT |
12107 | break; |
12108 | ||
12109 | case SHASTA_EXT_LED_SHARED: | |
12110 | tp->led_ctrl = LED_CTRL_MODE_SHARED; | |
12111 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | |
12112 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A1) | |
12113 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12114 | LED_CTRL_MODE_PHY_2); | |
12115 | break; | |
12116 | ||
12117 | case SHASTA_EXT_LED_MAC: | |
12118 | tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; | |
12119 | break; | |
12120 | ||
12121 | case SHASTA_EXT_LED_COMBO: | |
12122 | tp->led_ctrl = LED_CTRL_MODE_COMBO; | |
12123 | if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) | |
12124 | tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | | |
12125 | LED_CTRL_MODE_PHY_2); | |
12126 | break; | |
12127 | ||
855e1111 | 12128 | } |
1da177e4 LT |
12129 | |
12130 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
12131 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | |
12132 | tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) | |
12133 | tp->led_ctrl = LED_CTRL_MODE_PHY_2; | |
12134 | ||
b2a5c19c MC |
12135 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) |
12136 | tp->led_ctrl = LED_CTRL_MODE_PHY_1; | |
5f60891b | 12137 | |
9d26e213 | 12138 | if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) { |
1da177e4 | 12139 | tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12140 | if ((tp->pdev->subsystem_vendor == |
12141 | PCI_VENDOR_ID_ARIMA) && | |
12142 | (tp->pdev->subsystem_device == 0x205a || | |
12143 | tp->pdev->subsystem_device == 0x2063)) | |
12144 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; | |
12145 | } else { | |
f49639e6 | 12146 | tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT; |
9d26e213 MC |
12147 | tp->tg3_flags2 |= TG3_FLG2_IS_NIC; |
12148 | } | |
1da177e4 LT |
12149 | |
12150 | if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { | |
12151 | tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; | |
cbf46853 | 12152 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) |
1da177e4 LT |
12153 | tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; |
12154 | } | |
b2b98d4a MC |
12155 | |
12156 | if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) && | |
12157 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
0d3031d9 | 12158 | tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE; |
b2b98d4a | 12159 | |
a85feb8c GZ |
12160 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && |
12161 | !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)) | |
12162 | tp->tg3_flags &= ~TG3_FLAG_WOL_CAP; | |
1da177e4 | 12163 | |
12dac075 | 12164 | if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) && |
05ac4cb7 | 12165 | (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) |
0527ba35 MC |
12166 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
12167 | ||
1da177e4 LT |
12168 | if (cfg2 & (1 << 17)) |
12169 | tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING; | |
12170 | ||
12171 | /* serdes signal pre-emphasis in register 0x590 set by */ | |
12172 | /* bootcode if bit 18 is set */ | |
12173 | if (cfg2 & (1 << 18)) | |
12174 | tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS; | |
8ed5d97e | 12175 | |
321d32a0 MC |
12176 | if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
12177 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) && | |
6833c043 MC |
12178 | (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN)) |
12179 | tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD; | |
12180 | ||
8ed5d97e MC |
12181 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
12182 | u32 cfg3; | |
12183 | ||
12184 | tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); | |
12185 | if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE) | |
12186 | tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND; | |
12187 | } | |
a9daf367 | 12188 | |
14417063 MC |
12189 | if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE) |
12190 | tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE; | |
a9daf367 MC |
12191 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN) |
12192 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN; | |
12193 | if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN) | |
12194 | tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN; | |
1da177e4 | 12195 | } |
05ac4cb7 MC |
12196 | done: |
12197 | device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP); | |
12198 | device_set_wakeup_enable(&tp->pdev->dev, | |
12199 | tp->tg3_flags & TG3_FLAG_WOL_ENABLE); | |
7d0c41ef MC |
12200 | } |
12201 | ||
b2a5c19c MC |
12202 | static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd) |
12203 | { | |
12204 | int i; | |
12205 | u32 val; | |
12206 | ||
12207 | tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START); | |
12208 | tw32(OTP_CTRL, cmd); | |
12209 | ||
12210 | /* Wait for up to 1 ms for command to execute. */ | |
12211 | for (i = 0; i < 100; i++) { | |
12212 | val = tr32(OTP_STATUS); | |
12213 | if (val & OTP_STATUS_CMD_DONE) | |
12214 | break; | |
12215 | udelay(10); | |
12216 | } | |
12217 | ||
12218 | return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; | |
12219 | } | |
12220 | ||
12221 | /* Read the gphy configuration from the OTP region of the chip. The gphy | |
12222 | * configuration is a 32-bit value that straddles the alignment boundary. | |
12223 | * We do two 32-bit reads and then shift and merge the results. | |
12224 | */ | |
12225 | static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp) | |
12226 | { | |
12227 | u32 bhalf_otp, thalf_otp; | |
12228 | ||
12229 | tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC); | |
12230 | ||
12231 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) | |
12232 | return 0; | |
12233 | ||
12234 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1); | |
12235 | ||
12236 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12237 | return 0; | |
12238 | ||
12239 | thalf_otp = tr32(OTP_READ_DATA); | |
12240 | ||
12241 | tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2); | |
12242 | ||
12243 | if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) | |
12244 | return 0; | |
12245 | ||
12246 | bhalf_otp = tr32(OTP_READ_DATA); | |
12247 | ||
12248 | return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16); | |
12249 | } | |
12250 | ||
7d0c41ef MC |
12251 | static int __devinit tg3_phy_probe(struct tg3 *tp) |
12252 | { | |
12253 | u32 hw_phy_id_1, hw_phy_id_2; | |
12254 | u32 hw_phy_id, hw_phy_id_masked; | |
12255 | int err; | |
1da177e4 | 12256 | |
b02fd9e3 MC |
12257 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) |
12258 | return tg3_phy_init(tp); | |
12259 | ||
1da177e4 | 12260 | /* Reading the PHY ID register can conflict with ASF |
877d0310 | 12261 | * firmware access to the PHY hardware. |
1da177e4 LT |
12262 | */ |
12263 | err = 0; | |
0d3031d9 MC |
12264 | if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || |
12265 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) { | |
79eb6904 | 12266 | hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID; |
1da177e4 LT |
12267 | } else { |
12268 | /* Now read the physical PHY_ID from the chip and verify | |
12269 | * that it is sane. If it doesn't look good, we fall back | |
12270 | * to either the hard-coded table based PHY_ID and failing | |
12271 | * that the value found in the eeprom area. | |
12272 | */ | |
12273 | err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); | |
12274 | err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); | |
12275 | ||
12276 | hw_phy_id = (hw_phy_id_1 & 0xffff) << 10; | |
12277 | hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16; | |
12278 | hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0; | |
12279 | ||
79eb6904 | 12280 | hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK; |
1da177e4 LT |
12281 | } |
12282 | ||
79eb6904 | 12283 | if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) { |
1da177e4 | 12284 | tp->phy_id = hw_phy_id; |
79eb6904 | 12285 | if (hw_phy_id_masked == TG3_PHY_ID_BCM8002) |
1da177e4 | 12286 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; |
da6b2d01 MC |
12287 | else |
12288 | tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES; | |
1da177e4 | 12289 | } else { |
79eb6904 | 12290 | if (tp->phy_id != TG3_PHY_ID_INVALID) { |
7d0c41ef MC |
12291 | /* Do nothing, phy ID already set up in |
12292 | * tg3_get_eeprom_hw_cfg(). | |
12293 | */ | |
1da177e4 LT |
12294 | } else { |
12295 | struct subsys_tbl_ent *p; | |
12296 | ||
12297 | /* No eeprom signature? Try the hardcoded | |
12298 | * subsys device table. | |
12299 | */ | |
24daf2b0 | 12300 | p = tg3_lookup_by_subsys(tp); |
1da177e4 LT |
12301 | if (!p) |
12302 | return -ENODEV; | |
12303 | ||
12304 | tp->phy_id = p->phy_id; | |
12305 | if (!tp->phy_id || | |
79eb6904 | 12306 | tp->phy_id == TG3_PHY_ID_BCM8002) |
1da177e4 LT |
12307 | tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; |
12308 | } | |
12309 | } | |
12310 | ||
747e8f8b | 12311 | if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) && |
0d3031d9 | 12312 | !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) && |
1da177e4 | 12313 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) { |
3600d918 | 12314 | u32 bmsr, adv_reg, tg3_ctrl, mask; |
1da177e4 LT |
12315 | |
12316 | tg3_readphy(tp, MII_BMSR, &bmsr); | |
12317 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | |
12318 | (bmsr & BMSR_LSTATUS)) | |
12319 | goto skip_phy_reset; | |
6aa20a22 | 12320 | |
1da177e4 LT |
12321 | err = tg3_phy_reset(tp); |
12322 | if (err) | |
12323 | return err; | |
12324 | ||
12325 | adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL | | |
12326 | ADVERTISE_100HALF | ADVERTISE_100FULL | | |
12327 | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP); | |
12328 | tg3_ctrl = 0; | |
12329 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) { | |
12330 | tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF | | |
12331 | MII_TG3_CTRL_ADV_1000_FULL); | |
12332 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
12333 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) | |
12334 | tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER | | |
12335 | MII_TG3_CTRL_ENABLE_AS_MASTER); | |
12336 | } | |
12337 | ||
3600d918 MC |
12338 | mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
12339 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
12340 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); | |
12341 | if (!tg3_copper_is_advertising_all(tp, mask)) { | |
1da177e4 LT |
12342 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); |
12343 | ||
12344 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
12345 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
12346 | ||
12347 | tg3_writephy(tp, MII_BMCR, | |
12348 | BMCR_ANENABLE | BMCR_ANRESTART); | |
12349 | } | |
12350 | tg3_phy_set_wirespeed(tp); | |
12351 | ||
12352 | tg3_writephy(tp, MII_ADVERTISE, adv_reg); | |
12353 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | |
12354 | tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl); | |
12355 | } | |
12356 | ||
12357 | skip_phy_reset: | |
79eb6904 | 12358 | if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { |
1da177e4 LT |
12359 | err = tg3_init_5401phy_dsp(tp); |
12360 | if (err) | |
12361 | return err; | |
1da177e4 | 12362 | |
1da177e4 LT |
12363 | err = tg3_init_5401phy_dsp(tp); |
12364 | } | |
12365 | ||
747e8f8b | 12366 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) |
1da177e4 LT |
12367 | tp->link_config.advertising = |
12368 | (ADVERTISED_1000baseT_Half | | |
12369 | ADVERTISED_1000baseT_Full | | |
12370 | ADVERTISED_Autoneg | | |
12371 | ADVERTISED_FIBRE); | |
12372 | if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) | |
12373 | tp->link_config.advertising &= | |
12374 | ~(ADVERTISED_1000baseT_Half | | |
12375 | ADVERTISED_1000baseT_Full); | |
12376 | ||
12377 | return err; | |
12378 | } | |
12379 | ||
184b8904 | 12380 | static void __devinit tg3_read_vpd(struct tg3 *tp) |
1da177e4 | 12381 | { |
184b8904 | 12382 | u8 vpd_data[TG3_NVM_VPD_LEN]; |
4181b2c8 | 12383 | unsigned int block_end, rosize, len; |
184b8904 | 12384 | int j, i = 0; |
1b27777a | 12385 | u32 magic; |
1da177e4 | 12386 | |
df259d8c MC |
12387 | if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) || |
12388 | tg3_nvram_read(tp, 0x0, &magic)) | |
f49639e6 | 12389 | goto out_not_found; |
1da177e4 | 12390 | |
1820180b | 12391 | if (magic == TG3_EEPROM_MAGIC) { |
141518c9 | 12392 | for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) { |
1b27777a | 12393 | u32 tmp; |
1da177e4 | 12394 | |
6d348f2c MC |
12395 | /* The data is in little-endian format in NVRAM. |
12396 | * Use the big-endian read routines to preserve | |
12397 | * the byte order as it exists in NVRAM. | |
12398 | */ | |
141518c9 | 12399 | if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp)) |
1b27777a MC |
12400 | goto out_not_found; |
12401 | ||
6d348f2c | 12402 | memcpy(&vpd_data[i], &tmp, sizeof(tmp)); |
1b27777a MC |
12403 | } |
12404 | } else { | |
94c982bd | 12405 | ssize_t cnt; |
4181b2c8 | 12406 | unsigned int pos = 0; |
94c982bd MC |
12407 | |
12408 | for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) { | |
12409 | cnt = pci_read_vpd(tp->pdev, pos, | |
12410 | TG3_NVM_VPD_LEN - pos, | |
12411 | &vpd_data[pos]); | |
12412 | if (cnt == -ETIMEDOUT || -EINTR) | |
12413 | cnt = 0; | |
12414 | else if (cnt < 0) | |
f49639e6 | 12415 | goto out_not_found; |
1b27777a | 12416 | } |
94c982bd MC |
12417 | if (pos != TG3_NVM_VPD_LEN) |
12418 | goto out_not_found; | |
1da177e4 LT |
12419 | } |
12420 | ||
4181b2c8 MC |
12421 | i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN, |
12422 | PCI_VPD_LRDT_RO_DATA); | |
12423 | if (i < 0) | |
12424 | goto out_not_found; | |
1da177e4 | 12425 | |
4181b2c8 MC |
12426 | rosize = pci_vpd_lrdt_size(&vpd_data[i]); |
12427 | block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize; | |
12428 | i += PCI_VPD_LRDT_TAG_SIZE; | |
1da177e4 | 12429 | |
4181b2c8 MC |
12430 | if (block_end > TG3_NVM_VPD_LEN) |
12431 | goto out_not_found; | |
af2c6a4a | 12432 | |
184b8904 MC |
12433 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
12434 | PCI_VPD_RO_KEYWORD_MFR_ID); | |
12435 | if (j > 0) { | |
12436 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
12437 | ||
12438 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12439 | if (j + len > block_end || len != 4 || | |
12440 | memcmp(&vpd_data[j], "1028", 4)) | |
12441 | goto partno; | |
12442 | ||
12443 | j = pci_vpd_find_info_keyword(vpd_data, i, rosize, | |
12444 | PCI_VPD_RO_KEYWORD_VENDOR0); | |
12445 | if (j < 0) | |
12446 | goto partno; | |
12447 | ||
12448 | len = pci_vpd_info_field_size(&vpd_data[j]); | |
12449 | ||
12450 | j += PCI_VPD_INFO_FLD_HDR_SIZE; | |
12451 | if (j + len > block_end) | |
12452 | goto partno; | |
12453 | ||
12454 | memcpy(tp->fw_ver, &vpd_data[j], len); | |
12455 | strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1); | |
12456 | } | |
12457 | ||
12458 | partno: | |
4181b2c8 MC |
12459 | i = pci_vpd_find_info_keyword(vpd_data, i, rosize, |
12460 | PCI_VPD_RO_KEYWORD_PARTNO); | |
12461 | if (i < 0) | |
12462 | goto out_not_found; | |
af2c6a4a | 12463 | |
4181b2c8 | 12464 | len = pci_vpd_info_field_size(&vpd_data[i]); |
1da177e4 | 12465 | |
4181b2c8 MC |
12466 | i += PCI_VPD_INFO_FLD_HDR_SIZE; |
12467 | if (len > TG3_BPN_SIZE || | |
12468 | (len + i) > TG3_NVM_VPD_LEN) | |
12469 | goto out_not_found; | |
1da177e4 | 12470 | |
4181b2c8 | 12471 | memcpy(tp->board_part_number, &vpd_data[i], len); |
1da177e4 | 12472 | |
4181b2c8 | 12473 | return; |
1da177e4 LT |
12474 | |
12475 | out_not_found: | |
b5d3772c MC |
12476 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
12477 | strcpy(tp->board_part_number, "BCM95906"); | |
df259d8c MC |
12478 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && |
12479 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) | |
12480 | strcpy(tp->board_part_number, "BCM57780"); | |
12481 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
12482 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) | |
12483 | strcpy(tp->board_part_number, "BCM57760"); | |
12484 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && | |
12485 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) | |
12486 | strcpy(tp->board_part_number, "BCM57790"); | |
5e7ccf20 MC |
12487 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 && |
12488 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) | |
12489 | strcpy(tp->board_part_number, "BCM57788"); | |
b474eca7 MC |
12490 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && |
12491 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) | |
12492 | strcpy(tp->board_part_number, "BCM57761"); | |
12493 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
12494 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) | |
b703df6f | 12495 | strcpy(tp->board_part_number, "BCM57765"); |
b474eca7 MC |
12496 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && |
12497 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) | |
12498 | strcpy(tp->board_part_number, "BCM57781"); | |
12499 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
12500 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) | |
12501 | strcpy(tp->board_part_number, "BCM57785"); | |
12502 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
12503 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) | |
12504 | strcpy(tp->board_part_number, "BCM57791"); | |
12505 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 && | |
12506 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
12507 | strcpy(tp->board_part_number, "BCM57795"); | |
b5d3772c MC |
12508 | else |
12509 | strcpy(tp->board_part_number, "none"); | |
1da177e4 LT |
12510 | } |
12511 | ||
9c8a620e MC |
12512 | static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) |
12513 | { | |
12514 | u32 val; | |
12515 | ||
e4f34110 | 12516 | if (tg3_nvram_read(tp, offset, &val) || |
9c8a620e | 12517 | (val & 0xfc000000) != 0x0c000000 || |
e4f34110 | 12518 | tg3_nvram_read(tp, offset + 4, &val) || |
9c8a620e MC |
12519 | val != 0) |
12520 | return 0; | |
12521 | ||
12522 | return 1; | |
12523 | } | |
12524 | ||
acd9c119 MC |
12525 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) |
12526 | { | |
ff3a7cb2 | 12527 | u32 val, offset, start, ver_offset; |
75f9936e | 12528 | int i, dst_off; |
ff3a7cb2 | 12529 | bool newver = false; |
acd9c119 MC |
12530 | |
12531 | if (tg3_nvram_read(tp, 0xc, &offset) || | |
12532 | tg3_nvram_read(tp, 0x4, &start)) | |
12533 | return; | |
12534 | ||
12535 | offset = tg3_nvram_logical_addr(tp, offset); | |
12536 | ||
ff3a7cb2 | 12537 | if (tg3_nvram_read(tp, offset, &val)) |
acd9c119 MC |
12538 | return; |
12539 | ||
ff3a7cb2 MC |
12540 | if ((val & 0xfc000000) == 0x0c000000) { |
12541 | if (tg3_nvram_read(tp, offset + 4, &val)) | |
acd9c119 MC |
12542 | return; |
12543 | ||
ff3a7cb2 MC |
12544 | if (val == 0) |
12545 | newver = true; | |
12546 | } | |
12547 | ||
75f9936e MC |
12548 | dst_off = strlen(tp->fw_ver); |
12549 | ||
ff3a7cb2 | 12550 | if (newver) { |
75f9936e MC |
12551 | if (TG3_VER_SIZE - dst_off < 16 || |
12552 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | |
ff3a7cb2 MC |
12553 | return; |
12554 | ||
12555 | offset = offset + ver_offset - start; | |
12556 | for (i = 0; i < 16; i += 4) { | |
12557 | __be32 v; | |
12558 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | |
12559 | return; | |
12560 | ||
75f9936e | 12561 | memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); |
ff3a7cb2 MC |
12562 | } |
12563 | } else { | |
12564 | u32 major, minor; | |
12565 | ||
12566 | if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) | |
12567 | return; | |
12568 | ||
12569 | major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >> | |
12570 | TG3_NVM_BCVER_MAJSFT; | |
12571 | minor = ver_offset & TG3_NVM_BCVER_MINMSK; | |
75f9936e MC |
12572 | snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, |
12573 | "v%d.%02d", major, minor); | |
acd9c119 MC |
12574 | } |
12575 | } | |
12576 | ||
a6f6cb1c MC |
12577 | static void __devinit tg3_read_hwsb_ver(struct tg3 *tp) |
12578 | { | |
12579 | u32 val, major, minor; | |
12580 | ||
12581 | /* Use native endian representation */ | |
12582 | if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) | |
12583 | return; | |
12584 | ||
12585 | major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >> | |
12586 | TG3_NVM_HWSB_CFG1_MAJSFT; | |
12587 | minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >> | |
12588 | TG3_NVM_HWSB_CFG1_MINSFT; | |
12589 | ||
12590 | snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); | |
12591 | } | |
12592 | ||
dfe00d7d MC |
12593 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
12594 | { | |
12595 | u32 offset, major, minor, build; | |
12596 | ||
75f9936e | 12597 | strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); |
dfe00d7d MC |
12598 | |
12599 | if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1) | |
12600 | return; | |
12601 | ||
12602 | switch (val & TG3_EEPROM_SB_REVISION_MASK) { | |
12603 | case TG3_EEPROM_SB_REVISION_0: | |
12604 | offset = TG3_EEPROM_SB_F1R0_EDH_OFF; | |
12605 | break; | |
12606 | case TG3_EEPROM_SB_REVISION_2: | |
12607 | offset = TG3_EEPROM_SB_F1R2_EDH_OFF; | |
12608 | break; | |
12609 | case TG3_EEPROM_SB_REVISION_3: | |
12610 | offset = TG3_EEPROM_SB_F1R3_EDH_OFF; | |
12611 | break; | |
a4153d40 MC |
12612 | case TG3_EEPROM_SB_REVISION_4: |
12613 | offset = TG3_EEPROM_SB_F1R4_EDH_OFF; | |
12614 | break; | |
12615 | case TG3_EEPROM_SB_REVISION_5: | |
12616 | offset = TG3_EEPROM_SB_F1R5_EDH_OFF; | |
12617 | break; | |
dfe00d7d MC |
12618 | default: |
12619 | return; | |
12620 | } | |
12621 | ||
e4f34110 | 12622 | if (tg3_nvram_read(tp, offset, &val)) |
dfe00d7d MC |
12623 | return; |
12624 | ||
12625 | build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >> | |
12626 | TG3_EEPROM_SB_EDH_BLD_SHFT; | |
12627 | major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >> | |
12628 | TG3_EEPROM_SB_EDH_MAJ_SHFT; | |
12629 | minor = val & TG3_EEPROM_SB_EDH_MIN_MASK; | |
12630 | ||
12631 | if (minor > 99 || build > 26) | |
12632 | return; | |
12633 | ||
75f9936e MC |
12634 | offset = strlen(tp->fw_ver); |
12635 | snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, | |
12636 | " v%d.%02d", major, minor); | |
dfe00d7d MC |
12637 | |
12638 | if (build > 0) { | |
75f9936e MC |
12639 | offset = strlen(tp->fw_ver); |
12640 | if (offset < TG3_VER_SIZE - 1) | |
12641 | tp->fw_ver[offset] = 'a' + build - 1; | |
dfe00d7d MC |
12642 | } |
12643 | } | |
12644 | ||
acd9c119 | 12645 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
c4e6575c MC |
12646 | { |
12647 | u32 val, offset, start; | |
acd9c119 | 12648 | int i, vlen; |
9c8a620e MC |
12649 | |
12650 | for (offset = TG3_NVM_DIR_START; | |
12651 | offset < TG3_NVM_DIR_END; | |
12652 | offset += TG3_NVM_DIRENT_SIZE) { | |
e4f34110 | 12653 | if (tg3_nvram_read(tp, offset, &val)) |
c4e6575c MC |
12654 | return; |
12655 | ||
9c8a620e MC |
12656 | if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI) |
12657 | break; | |
12658 | } | |
12659 | ||
12660 | if (offset == TG3_NVM_DIR_END) | |
12661 | return; | |
12662 | ||
12663 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | |
12664 | start = 0x08000000; | |
e4f34110 | 12665 | else if (tg3_nvram_read(tp, offset - 4, &start)) |
9c8a620e MC |
12666 | return; |
12667 | ||
e4f34110 | 12668 | if (tg3_nvram_read(tp, offset + 4, &offset) || |
9c8a620e | 12669 | !tg3_fw_img_is_valid(tp, offset) || |
e4f34110 | 12670 | tg3_nvram_read(tp, offset + 8, &val)) |
9c8a620e MC |
12671 | return; |
12672 | ||
12673 | offset += val - start; | |
12674 | ||
acd9c119 | 12675 | vlen = strlen(tp->fw_ver); |
9c8a620e | 12676 | |
acd9c119 MC |
12677 | tp->fw_ver[vlen++] = ','; |
12678 | tp->fw_ver[vlen++] = ' '; | |
9c8a620e MC |
12679 | |
12680 | for (i = 0; i < 4; i++) { | |
a9dc529d MC |
12681 | __be32 v; |
12682 | if (tg3_nvram_read_be32(tp, offset, &v)) | |
c4e6575c MC |
12683 | return; |
12684 | ||
b9fc7dc5 | 12685 | offset += sizeof(v); |
c4e6575c | 12686 | |
acd9c119 MC |
12687 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
12688 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); | |
9c8a620e | 12689 | break; |
c4e6575c | 12690 | } |
9c8a620e | 12691 | |
acd9c119 MC |
12692 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
12693 | vlen += sizeof(v); | |
c4e6575c | 12694 | } |
acd9c119 MC |
12695 | } |
12696 | ||
7fd76445 MC |
12697 | static void __devinit tg3_read_dash_ver(struct tg3 *tp) |
12698 | { | |
12699 | int vlen; | |
12700 | u32 apedata; | |
12701 | ||
12702 | if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || | |
12703 | !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) | |
12704 | return; | |
12705 | ||
12706 | apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); | |
12707 | if (apedata != APE_SEG_SIG_MAGIC) | |
12708 | return; | |
12709 | ||
12710 | apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); | |
12711 | if (!(apedata & APE_FW_STATUS_READY)) | |
12712 | return; | |
12713 | ||
12714 | apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); | |
12715 | ||
12716 | vlen = strlen(tp->fw_ver); | |
12717 | ||
12718 | snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d", | |
12719 | (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT, | |
12720 | (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT, | |
12721 | (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT, | |
12722 | (apedata & APE_FW_VERSION_BLDMSK)); | |
12723 | } | |
12724 | ||
acd9c119 MC |
12725 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) |
12726 | { | |
12727 | u32 val; | |
75f9936e | 12728 | bool vpd_vers = false; |
acd9c119 | 12729 | |
75f9936e MC |
12730 | if (tp->fw_ver[0] != 0) |
12731 | vpd_vers = true; | |
df259d8c | 12732 | |
75f9936e MC |
12733 | if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) { |
12734 | strcat(tp->fw_ver, "sb"); | |
df259d8c MC |
12735 | return; |
12736 | } | |
12737 | ||
acd9c119 MC |
12738 | if (tg3_nvram_read(tp, 0, &val)) |
12739 | return; | |
12740 | ||
12741 | if (val == TG3_EEPROM_MAGIC) | |
12742 | tg3_read_bc_ver(tp); | |
12743 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | |
12744 | tg3_read_sb_ver(tp, val); | |
a6f6cb1c MC |
12745 | else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW) |
12746 | tg3_read_hwsb_ver(tp); | |
acd9c119 MC |
12747 | else |
12748 | return; | |
12749 | ||
12750 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | |
75f9936e MC |
12751 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers) |
12752 | goto done; | |
acd9c119 MC |
12753 | |
12754 | tg3_read_mgmtfw_ver(tp); | |
9c8a620e | 12755 | |
75f9936e | 12756 | done: |
9c8a620e | 12757 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
c4e6575c MC |
12758 | } |
12759 | ||
7544b097 MC |
12760 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *); |
12761 | ||
1da177e4 LT |
12762 | static int __devinit tg3_get_invariants(struct tg3 *tp) |
12763 | { | |
12764 | static struct pci_device_id write_reorder_chipsets[] = { | |
1da177e4 | 12765 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, |
c6cdf436 | 12766 | PCI_DEVICE_ID_AMD_FE_GATE_700C) }, |
c165b004 | 12767 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, |
c6cdf436 | 12768 | PCI_DEVICE_ID_AMD_8131_BRIDGE) }, |
399de50b MC |
12769 | { PCI_DEVICE(PCI_VENDOR_ID_VIA, |
12770 | PCI_DEVICE_ID_VIA_8385_0) }, | |
1da177e4 LT |
12771 | { }, |
12772 | }; | |
12773 | u32 misc_ctrl_reg; | |
1da177e4 LT |
12774 | u32 pci_state_reg, grc_misc_cfg; |
12775 | u32 val; | |
12776 | u16 pci_cmd; | |
5e7dfd0f | 12777 | int err; |
1da177e4 | 12778 | |
1da177e4 LT |
12779 | /* Force memory write invalidate off. If we leave it on, |
12780 | * then on 5700_BX chips we have to enable a workaround. | |
12781 | * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary | |
12782 | * to match the cacheline size. The Broadcom driver have this | |
12783 | * workaround but turns MWI off all the times so never uses | |
12784 | * it. This seems to suggest that the workaround is insufficient. | |
12785 | */ | |
12786 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
12787 | pci_cmd &= ~PCI_COMMAND_INVALIDATE; | |
12788 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
12789 | ||
12790 | /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL | |
12791 | * has the register indirect write enable bit set before | |
12792 | * we try to access any of the MMIO registers. It is also | |
12793 | * critical that the PCI-X hw workaround situation is decided | |
12794 | * before that as well. | |
12795 | */ | |
12796 | pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12797 | &misc_ctrl_reg); | |
12798 | ||
12799 | tp->pci_chip_rev_id = (misc_ctrl_reg >> | |
12800 | MISC_HOST_CTRL_CHIPREV_SHIFT); | |
795d01c5 MC |
12801 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) { |
12802 | u32 prod_id_asic_rev; | |
12803 | ||
5001e2f6 MC |
12804 | if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || |
12805 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || | |
12806 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724) | |
f6eb9b1f MC |
12807 | pci_read_config_dword(tp->pdev, |
12808 | TG3PCI_GEN2_PRODID_ASICREV, | |
12809 | &prod_id_asic_rev); | |
b703df6f MC |
12810 | else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || |
12811 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || | |
12812 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || | |
12813 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || | |
12814 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || | |
12815 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) | |
12816 | pci_read_config_dword(tp->pdev, | |
12817 | TG3PCI_GEN15_PRODID_ASICREV, | |
12818 | &prod_id_asic_rev); | |
f6eb9b1f MC |
12819 | else |
12820 | pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV, | |
12821 | &prod_id_asic_rev); | |
12822 | ||
321d32a0 | 12823 | tp->pci_chip_rev_id = prod_id_asic_rev; |
795d01c5 | 12824 | } |
1da177e4 | 12825 | |
ff645bec MC |
12826 | /* Wrong chip ID in 5752 A0. This code can be removed later |
12827 | * as A0 is not in production. | |
12828 | */ | |
12829 | if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) | |
12830 | tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; | |
12831 | ||
6892914f MC |
12832 | /* If we have 5702/03 A1 or A2 on certain ICH chipsets, |
12833 | * we need to disable memory and use config. cycles | |
12834 | * only to access all registers. The 5702/03 chips | |
12835 | * can mistakenly decode the special cycles from the | |
12836 | * ICH chipsets as memory write cycles, causing corruption | |
12837 | * of register and memory space. Only certain ICH bridges | |
12838 | * will drive special cycles with non-zero data during the | |
12839 | * address phase which can fall within the 5703's address | |
12840 | * range. This is not an ICH bug as the PCI spec allows | |
12841 | * non-zero address during special cycles. However, only | |
12842 | * these ICH bridges are known to drive non-zero addresses | |
12843 | * during special cycles. | |
12844 | * | |
12845 | * Since special cycles do not cross PCI bridges, we only | |
12846 | * enable this workaround if the 5703 is on the secondary | |
12847 | * bus of these ICH bridges. | |
12848 | */ | |
12849 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) || | |
12850 | (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) { | |
12851 | static struct tg3_dev_id { | |
12852 | u32 vendor; | |
12853 | u32 device; | |
12854 | u32 rev; | |
12855 | } ich_chipsets[] = { | |
12856 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8, | |
12857 | PCI_ANY_ID }, | |
12858 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8, | |
12859 | PCI_ANY_ID }, | |
12860 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11, | |
12861 | 0xa }, | |
12862 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6, | |
12863 | PCI_ANY_ID }, | |
12864 | { }, | |
12865 | }; | |
12866 | struct tg3_dev_id *pci_id = &ich_chipsets[0]; | |
12867 | struct pci_dev *bridge = NULL; | |
12868 | ||
12869 | while (pci_id->vendor != 0) { | |
12870 | bridge = pci_get_device(pci_id->vendor, pci_id->device, | |
12871 | bridge); | |
12872 | if (!bridge) { | |
12873 | pci_id++; | |
12874 | continue; | |
12875 | } | |
12876 | if (pci_id->rev != PCI_ANY_ID) { | |
44c10138 | 12877 | if (bridge->revision > pci_id->rev) |
6892914f MC |
12878 | continue; |
12879 | } | |
12880 | if (bridge->subordinate && | |
12881 | (bridge->subordinate->number == | |
12882 | tp->pdev->bus->number)) { | |
12883 | ||
12884 | tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND; | |
12885 | pci_dev_put(bridge); | |
12886 | break; | |
12887 | } | |
12888 | } | |
12889 | } | |
12890 | ||
41588ba1 MC |
12891 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) { |
12892 | static struct tg3_dev_id { | |
12893 | u32 vendor; | |
12894 | u32 device; | |
12895 | } bridge_chipsets[] = { | |
12896 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 }, | |
12897 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 }, | |
12898 | { }, | |
12899 | }; | |
12900 | struct tg3_dev_id *pci_id = &bridge_chipsets[0]; | |
12901 | struct pci_dev *bridge = NULL; | |
12902 | ||
12903 | while (pci_id->vendor != 0) { | |
12904 | bridge = pci_get_device(pci_id->vendor, | |
12905 | pci_id->device, | |
12906 | bridge); | |
12907 | if (!bridge) { | |
12908 | pci_id++; | |
12909 | continue; | |
12910 | } | |
12911 | if (bridge->subordinate && | |
12912 | (bridge->subordinate->number <= | |
12913 | tp->pdev->bus->number) && | |
12914 | (bridge->subordinate->subordinate >= | |
12915 | tp->pdev->bus->number)) { | |
12916 | tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG; | |
12917 | pci_dev_put(bridge); | |
12918 | break; | |
12919 | } | |
12920 | } | |
12921 | } | |
12922 | ||
4a29cc2e MC |
12923 | /* The EPB bridge inside 5714, 5715, and 5780 cannot support |
12924 | * DMA addresses > 40-bit. This bridge may have other additional | |
12925 | * 57xx devices behind it in some 4-port NIC designs for example. | |
12926 | * Any tg3 device found behind the bridge will also need the 40-bit | |
12927 | * DMA workaround. | |
12928 | */ | |
a4e2b347 MC |
12929 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 || |
12930 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { | |
12931 | tp->tg3_flags2 |= TG3_FLG2_5780_CLASS; | |
4a29cc2e | 12932 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; |
4cf78e4f | 12933 | tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI); |
859a5887 | 12934 | } else { |
4a29cc2e MC |
12935 | struct pci_dev *bridge = NULL; |
12936 | ||
12937 | do { | |
12938 | bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS, | |
12939 | PCI_DEVICE_ID_SERVERWORKS_EPB, | |
12940 | bridge); | |
12941 | if (bridge && bridge->subordinate && | |
12942 | (bridge->subordinate->number <= | |
12943 | tp->pdev->bus->number) && | |
12944 | (bridge->subordinate->subordinate >= | |
12945 | tp->pdev->bus->number)) { | |
12946 | tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG; | |
12947 | pci_dev_put(bridge); | |
12948 | break; | |
12949 | } | |
12950 | } while (bridge); | |
12951 | } | |
4cf78e4f | 12952 | |
1da177e4 LT |
12953 | /* Initialize misc host control in PCI block. */ |
12954 | tp->misc_host_ctrl |= (misc_ctrl_reg & | |
12955 | MISC_HOST_CTRL_CHIPREV); | |
12956 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
12957 | tp->misc_host_ctrl); | |
12958 | ||
f6eb9b1f MC |
12959 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 || |
12960 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 || | |
12961 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | |
7544b097 MC |
12962 | tp->pdev_peer = tg3_find_peer(tp); |
12963 | ||
321d32a0 MC |
12964 | /* Intentionally exclude ASIC_REV_5906 */ |
12965 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | |
d9ab5ad1 | 12966 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
d30cdd28 | 12967 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
9936bcf6 | 12968 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
57e6983c | 12969 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 12970 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
b703df6f MC |
12971 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
12972 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
321d32a0 MC |
12973 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; |
12974 | ||
12975 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
12976 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
b5d3772c | 12977 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 || |
321d32a0 | 12978 | (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
a4e2b347 | 12979 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
6708e5cc JL |
12980 | tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; |
12981 | ||
1b440c56 JL |
12982 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || |
12983 | (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)) | |
12984 | tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; | |
12985 | ||
027455ad MC |
12986 | /* 5700 B0 chips do not support checksumming correctly due |
12987 | * to hardware bugs. | |
12988 | */ | |
12989 | if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0) | |
12990 | tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS; | |
12991 | else { | |
12992 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | |
12993 | tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
12994 | if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) | |
12995 | tp->dev->features |= NETIF_F_IPV6_CSUM; | |
12996 | } | |
12997 | ||
507399f1 | 12998 | /* Determine TSO capabilities */ |
b703df6f MC |
12999 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13000 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
e849cdc3 MC |
13001 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; |
13002 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | |
13003 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
507399f1 MC |
13004 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; |
13005 | else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { | |
13006 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG; | |
13007 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 && | |
13008 | tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) | |
13009 | tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG; | |
13010 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13011 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13012 | tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) { | |
13013 | tp->tg3_flags2 |= TG3_FLG2_TSO_BUG; | |
13014 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) | |
13015 | tp->fw_needed = FIRMWARE_TG3TSO5; | |
13016 | else | |
13017 | tp->fw_needed = FIRMWARE_TG3TSO; | |
13018 | } | |
13019 | ||
13020 | tp->irq_max = 1; | |
13021 | ||
5a6f3074 | 13022 | if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { |
7544b097 MC |
13023 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI; |
13024 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX || | |
13025 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX || | |
13026 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 && | |
13027 | tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 && | |
13028 | tp->pdev_peer == tp->pdev)) | |
13029 | tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI; | |
13030 | ||
321d32a0 | 13031 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
b5d3772c | 13032 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
fcfa0a32 | 13033 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; |
52c0fd83 | 13034 | } |
4f125f42 | 13035 | |
b703df6f MC |
13036 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13037 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
507399f1 MC |
13038 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; |
13039 | tp->irq_max = TG3_IRQ_MAX_VECS; | |
13040 | } | |
f6eb9b1f | 13041 | } |
0e1406dd | 13042 | |
615774fe MC |
13043 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13044 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
13045 | tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG; | |
13046 | else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) { | |
13047 | tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG; | |
13048 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | |
0e1406dd | 13049 | } |
f6eb9b1f | 13050 | |
b703df6f MC |
13051 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13052 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
13053 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; | |
13054 | ||
f51f3562 | 13055 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
c6cdf436 MC |
13056 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) || |
13057 | (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG)) | |
8f666b07 | 13058 | tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE; |
0f893dc6 | 13059 | |
52f4490c MC |
13060 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, |
13061 | &pci_state_reg); | |
13062 | ||
5e7dfd0f MC |
13063 | tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
13064 | if (tp->pcie_cap != 0) { | |
13065 | u16 lnkctl; | |
13066 | ||
1da177e4 | 13067 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
5f5c51e3 MC |
13068 | |
13069 | pcie_set_readrq(tp->pdev, 4096); | |
13070 | ||
5e7dfd0f MC |
13071 | pci_read_config_word(tp->pdev, |
13072 | tp->pcie_cap + PCI_EXP_LNKCTL, | |
13073 | &lnkctl); | |
13074 | if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) { | |
13075 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
c7835a77 | 13076 | tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; |
5e7dfd0f | 13077 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
321d32a0 | 13078 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
9cf74ebb MC |
13079 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 || |
13080 | tp->pci_chip_rev_id == CHIPREV_ID_57780_A1) | |
5e7dfd0f | 13081 | tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; |
614b0590 MC |
13082 | } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) { |
13083 | tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN; | |
c7835a77 | 13084 | } |
52f4490c | 13085 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { |
fcb389df | 13086 | tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS; |
52f4490c MC |
13087 | } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
13088 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | |
13089 | tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); | |
13090 | if (!tp->pcix_cap) { | |
2445e461 MC |
13091 | dev_err(&tp->pdev->dev, |
13092 | "Cannot find PCI-X capability, aborting\n"); | |
52f4490c MC |
13093 | return -EIO; |
13094 | } | |
13095 | ||
13096 | if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE)) | |
13097 | tp->tg3_flags |= TG3_FLAG_PCIX_MODE; | |
13098 | } | |
1da177e4 | 13099 | |
399de50b MC |
13100 | /* If we have an AMD 762 or VIA K8T800 chipset, write |
13101 | * reordering to the mailbox registers done by the host | |
13102 | * controller can cause major troubles. We read back from | |
13103 | * every mailbox register write to force the writes to be | |
13104 | * posted to the chip in order. | |
13105 | */ | |
13106 | if (pci_dev_present(write_reorder_chipsets) && | |
13107 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
13108 | tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER; | |
13109 | ||
69fc4053 MC |
13110 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, |
13111 | &tp->pci_cacheline_sz); | |
13112 | pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, | |
13113 | &tp->pci_lat_timer); | |
1da177e4 LT |
13114 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && |
13115 | tp->pci_lat_timer < 64) { | |
13116 | tp->pci_lat_timer = 64; | |
69fc4053 MC |
13117 | pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, |
13118 | tp->pci_lat_timer); | |
1da177e4 LT |
13119 | } |
13120 | ||
52f4490c MC |
13121 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { |
13122 | /* 5700 BX chips need to have their TX producer index | |
13123 | * mailboxes written twice to workaround a bug. | |
13124 | */ | |
13125 | tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG; | |
1da177e4 | 13126 | |
52f4490c | 13127 | /* If we are in PCI-X mode, enable register write workaround. |
1da177e4 LT |
13128 | * |
13129 | * The workaround is to use indirect register accesses | |
13130 | * for all chip writes not to mailbox registers. | |
13131 | */ | |
52f4490c | 13132 | if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { |
1da177e4 | 13133 | u32 pm_reg; |
1da177e4 LT |
13134 | |
13135 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13136 | ||
13137 | /* The chip can have it's power management PCI config | |
13138 | * space registers clobbered due to this bug. | |
13139 | * So explicitly force the chip into D0 here. | |
13140 | */ | |
9974a356 MC |
13141 | pci_read_config_dword(tp->pdev, |
13142 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13143 | &pm_reg); |
13144 | pm_reg &= ~PCI_PM_CTRL_STATE_MASK; | |
13145 | pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */; | |
9974a356 MC |
13146 | pci_write_config_dword(tp->pdev, |
13147 | tp->pm_cap + PCI_PM_CTRL, | |
1da177e4 LT |
13148 | pm_reg); |
13149 | ||
13150 | /* Also, force SERR#/PERR# in PCI command. */ | |
13151 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13152 | pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; | |
13153 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13154 | } | |
13155 | } | |
13156 | ||
1da177e4 LT |
13157 | if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0) |
13158 | tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED; | |
13159 | if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0) | |
13160 | tp->tg3_flags |= TG3_FLAG_PCI_32BIT; | |
13161 | ||
13162 | /* Chip-specific fixup from Broadcom driver */ | |
13163 | if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) && | |
13164 | (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) { | |
13165 | pci_state_reg |= PCISTATE_RETRY_SAME_DMA; | |
13166 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); | |
13167 | } | |
13168 | ||
1ee582d8 | 13169 | /* Default fast path register access methods */ |
20094930 | 13170 | tp->read32 = tg3_read32; |
1ee582d8 | 13171 | tp->write32 = tg3_write32; |
09ee929c | 13172 | tp->read32_mbox = tg3_read32; |
20094930 | 13173 | tp->write32_mbox = tg3_write32; |
1ee582d8 MC |
13174 | tp->write32_tx_mbox = tg3_write32; |
13175 | tp->write32_rx_mbox = tg3_write32; | |
13176 | ||
13177 | /* Various workaround register access methods */ | |
13178 | if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) | |
13179 | tp->write32 = tg3_write_indirect_reg32; | |
98efd8a6 MC |
13180 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 || |
13181 | ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | |
13182 | tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) { | |
13183 | /* | |
13184 | * Back to back register writes can cause problems on these | |
13185 | * chips, the workaround is to read back all reg writes | |
13186 | * except those to mailbox regs. | |
13187 | * | |
13188 | * See tg3_write_indirect_reg32(). | |
13189 | */ | |
1ee582d8 | 13190 | tp->write32 = tg3_write_flush_reg32; |
98efd8a6 MC |
13191 | } |
13192 | ||
1ee582d8 MC |
13193 | if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) || |
13194 | (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) { | |
13195 | tp->write32_tx_mbox = tg3_write32_tx_mbox; | |
13196 | if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) | |
13197 | tp->write32_rx_mbox = tg3_write_flush_reg32; | |
13198 | } | |
20094930 | 13199 | |
6892914f MC |
13200 | if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) { |
13201 | tp->read32 = tg3_read_indirect_reg32; | |
13202 | tp->write32 = tg3_write_indirect_reg32; | |
13203 | tp->read32_mbox = tg3_read_indirect_mbox; | |
13204 | tp->write32_mbox = tg3_write_indirect_mbox; | |
13205 | tp->write32_tx_mbox = tg3_write_indirect_mbox; | |
13206 | tp->write32_rx_mbox = tg3_write_indirect_mbox; | |
13207 | ||
13208 | iounmap(tp->regs); | |
22abe310 | 13209 | tp->regs = NULL; |
6892914f MC |
13210 | |
13211 | pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); | |
13212 | pci_cmd &= ~PCI_COMMAND_MEMORY; | |
13213 | pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); | |
13214 | } | |
b5d3772c MC |
13215 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
13216 | tp->read32_mbox = tg3_read32_mbox_5906; | |
13217 | tp->write32_mbox = tg3_write32_mbox_5906; | |
13218 | tp->write32_tx_mbox = tg3_write32_mbox_5906; | |
13219 | tp->write32_rx_mbox = tg3_write32_mbox_5906; | |
13220 | } | |
6892914f | 13221 | |
bbadf503 MC |
13222 | if (tp->write32 == tg3_write_indirect_reg32 || |
13223 | ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13224 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
f49639e6 | 13225 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701))) |
bbadf503 MC |
13226 | tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG; |
13227 | ||
7d0c41ef | 13228 | /* Get eeprom hw config before calling tg3_set_power_state(). |
9d26e213 | 13229 | * In particular, the TG3_FLG2_IS_NIC flag must be |
7d0c41ef MC |
13230 | * determined before calling tg3_set_power_state() so that |
13231 | * we know whether or not to switch out of Vaux power. | |
13232 | * When the flag is set, it means that GPIO1 is used for eeprom | |
13233 | * write protect and also implies that it is a LOM where GPIOs | |
13234 | * are not used to switch power. | |
6aa20a22 | 13235 | */ |
7d0c41ef MC |
13236 | tg3_get_eeprom_hw_cfg(tp); |
13237 | ||
0d3031d9 MC |
13238 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
13239 | /* Allow reads and writes to the | |
13240 | * APE register and memory space. | |
13241 | */ | |
13242 | pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR | | |
13243 | PCISTATE_ALLOW_APE_SHMEM_WR; | |
13244 | pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13245 | pci_state_reg); | |
13246 | } | |
13247 | ||
9936bcf6 | 13248 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
57e6983c | 13249 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
321d32a0 | 13250 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
f6eb9b1f | 13251 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
b703df6f MC |
13252 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13253 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
d30cdd28 MC |
13254 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; |
13255 | ||
314fba34 MC |
13256 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). |
13257 | * GPIO1 driven high will bring 5700's external PHY out of reset. | |
13258 | * It is also used as eeprom write protect on LOMs. | |
13259 | */ | |
13260 | tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; | |
13261 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13262 | (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) | |
13263 | tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | | |
13264 | GRC_LCLCTRL_GPIO_OUTPUT1); | |
3e7d83bc MC |
13265 | /* Unused GPIO3 must be driven as output on 5752 because there |
13266 | * are no pull-up resistors on unused GPIO pins. | |
13267 | */ | |
13268 | else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) | |
13269 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; | |
314fba34 | 13270 | |
321d32a0 | 13271 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
cb4ed1fd MC |
13272 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
13273 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
af36e6b6 MC |
13274 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; |
13275 | ||
8d519ab2 MC |
13276 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || |
13277 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { | |
5f0c4a3c MC |
13278 | /* Turn off the debug UART. */ |
13279 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; | |
13280 | if (tp->tg3_flags2 & TG3_FLG2_IS_NIC) | |
13281 | /* Keep VMain power. */ | |
13282 | tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | | |
13283 | GRC_LCLCTRL_GPIO_OUTPUT0; | |
13284 | } | |
13285 | ||
1da177e4 | 13286 | /* Force the chip into D0. */ |
bc1c7567 | 13287 | err = tg3_set_power_state(tp, PCI_D0); |
1da177e4 | 13288 | if (err) { |
2445e461 | 13289 | dev_err(&tp->pdev->dev, "Transition to D0 failed\n"); |
1da177e4 LT |
13290 | return err; |
13291 | } | |
13292 | ||
1da177e4 LT |
13293 | /* Derive initial jumbo mode from MTU assigned in |
13294 | * ether_setup() via the alloc_etherdev() call | |
13295 | */ | |
0f893dc6 | 13296 | if (tp->dev->mtu > ETH_DATA_LEN && |
a4e2b347 | 13297 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
0f893dc6 | 13298 | tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE; |
1da177e4 LT |
13299 | |
13300 | /* Determine WakeOnLan speed to use. */ | |
13301 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13302 | tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 || | |
13303 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 || | |
13304 | tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) { | |
13305 | tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB); | |
13306 | } else { | |
13307 | tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB; | |
13308 | } | |
13309 | ||
7f97a4bd MC |
13310 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
13311 | tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET; | |
13312 | ||
1da177e4 LT |
13313 | /* A few boards don't want Ethernet@WireSpeed phy feature */ |
13314 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) || | |
13315 | ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) && | |
13316 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) && | |
747e8f8b | 13317 | (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) || |
7f97a4bd | 13318 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) || |
747e8f8b | 13319 | (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) |
1da177e4 LT |
13320 | tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED; |
13321 | ||
13322 | if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX || | |
13323 | GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX) | |
13324 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG; | |
13325 | if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) | |
13326 | tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; | |
13327 | ||
321d32a0 | 13328 | if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && |
7f97a4bd | 13329 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
321d32a0 | 13330 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
f6eb9b1f | 13331 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
b703df6f MC |
13332 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && |
13333 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) { | |
c424cb24 | 13334 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
d30cdd28 | 13335 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
9936bcf6 MC |
13336 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
13337 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) { | |
d4011ada MC |
13338 | if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && |
13339 | tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) | |
13340 | tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; | |
c1d2a196 MC |
13341 | if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) |
13342 | tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM; | |
321d32a0 | 13343 | } else |
c424cb24 MC |
13344 | tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; |
13345 | } | |
1da177e4 | 13346 | |
b2a5c19c MC |
13347 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
13348 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) { | |
13349 | tp->phy_otp = tg3_read_otp_phycfg(tp); | |
13350 | if (tp->phy_otp == 0) | |
13351 | tp->phy_otp = TG3_OTP_DEFAULT; | |
13352 | } | |
13353 | ||
f51f3562 | 13354 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) |
8ef21428 MC |
13355 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
13356 | else | |
13357 | tp->mi_mode = MAC_MI_MODE_BASE; | |
13358 | ||
1da177e4 | 13359 | tp->coalesce_mode = 0; |
1da177e4 LT |
13360 | if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && |
13361 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX) | |
13362 | tp->coalesce_mode |= HOSTCC_MODE_32BYTE; | |
13363 | ||
321d32a0 MC |
13364 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
13365 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) | |
57e6983c MC |
13366 | tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; |
13367 | ||
158d7abd MC |
13368 | err = tg3_mdio_init(tp); |
13369 | if (err) | |
13370 | return err; | |
1da177e4 | 13371 | |
55dffe79 MC |
13372 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 && |
13373 | (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 || | |
13374 | (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))) | |
13375 | return -ENOTSUPP; | |
13376 | ||
1da177e4 LT |
13377 | /* Initialize data/descriptor byte/word swapping. */ |
13378 | val = tr32(GRC_MODE); | |
13379 | val &= GRC_MODE_HOST_STACKUP; | |
13380 | tw32(GRC_MODE, val | tp->grc_mode); | |
13381 | ||
13382 | tg3_switch_clocks(tp); | |
13383 | ||
13384 | /* Clear this out for sanity. */ | |
13385 | tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
13386 | ||
13387 | pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, | |
13388 | &pci_state_reg); | |
13389 | if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 && | |
13390 | (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) { | |
13391 | u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl); | |
13392 | ||
13393 | if (chiprevid == CHIPREV_ID_5701_A0 || | |
13394 | chiprevid == CHIPREV_ID_5701_B0 || | |
13395 | chiprevid == CHIPREV_ID_5701_B2 || | |
13396 | chiprevid == CHIPREV_ID_5701_B5) { | |
13397 | void __iomem *sram_base; | |
13398 | ||
13399 | /* Write some dummy words into the SRAM status block | |
13400 | * area, see if it reads back correctly. If the return | |
13401 | * value is bad, force enable the PCIX workaround. | |
13402 | */ | |
13403 | sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; | |
13404 | ||
13405 | writel(0x00000000, sram_base); | |
13406 | writel(0x00000000, sram_base + 4); | |
13407 | writel(0xffffffff, sram_base + 4); | |
13408 | if (readl(sram_base) != 0x00000000) | |
13409 | tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; | |
13410 | } | |
13411 | } | |
13412 | ||
13413 | udelay(50); | |
13414 | tg3_nvram_init(tp); | |
13415 | ||
13416 | grc_misc_cfg = tr32(GRC_MISC_CFG); | |
13417 | grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK; | |
13418 | ||
1da177e4 LT |
13419 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && |
13420 | (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 || | |
13421 | grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M)) | |
13422 | tp->tg3_flags2 |= TG3_FLG2_IS_5788; | |
13423 | ||
fac9b83e DM |
13424 | if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) && |
13425 | (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)) | |
13426 | tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS; | |
13427 | if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) { | |
13428 | tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | | |
13429 | HOSTCC_MODE_CLRTICK_TXBD); | |
13430 | ||
13431 | tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; | |
13432 | pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, | |
13433 | tp->misc_host_ctrl); | |
13434 | } | |
13435 | ||
3bda1258 MC |
13436 | /* Preserve the APE MAC_MODE bits */ |
13437 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | |
13438 | tp->mac_mode = tr32(MAC_MODE) | | |
13439 | MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | |
13440 | else | |
13441 | tp->mac_mode = TG3_DEF_MAC_MODE; | |
13442 | ||
1da177e4 LT |
13443 | /* these are limited to 10/100 only */ |
13444 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 && | |
13445 | (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) || | |
13446 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && | |
13447 | tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13448 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 || | |
13449 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 || | |
13450 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) || | |
13451 | (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM && | |
13452 | (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F || | |
676917d4 MC |
13453 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F || |
13454 | tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) || | |
321d32a0 | 13455 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 || |
d1101142 MC |
13456 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || |
13457 | tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || | |
7f97a4bd | 13458 | (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) |
1da177e4 LT |
13459 | tp->tg3_flags |= TG3_FLAG_10_100_ONLY; |
13460 | ||
13461 | err = tg3_phy_probe(tp); | |
13462 | if (err) { | |
2445e461 | 13463 | dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); |
1da177e4 | 13464 | /* ... but do not return immediately ... */ |
b02fd9e3 | 13465 | tg3_mdio_fini(tp); |
1da177e4 LT |
13466 | } |
13467 | ||
184b8904 | 13468 | tg3_read_vpd(tp); |
c4e6575c | 13469 | tg3_read_fw_ver(tp); |
1da177e4 LT |
13470 | |
13471 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) { | |
13472 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
13473 | } else { | |
13474 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
13475 | tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT; | |
13476 | else | |
13477 | tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT; | |
13478 | } | |
13479 | ||
13480 | /* 5700 {AX,BX} chips have a broken status block link | |
13481 | * change bit implementation, so we must use the | |
13482 | * status register in those cases. | |
13483 | */ | |
13484 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) | |
13485 | tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG; | |
13486 | else | |
13487 | tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG; | |
13488 | ||
13489 | /* The led_ctrl is set during tg3_phy_probe, here we might | |
13490 | * have to force the link status polling mechanism based | |
13491 | * upon subsystem IDs. | |
13492 | */ | |
13493 | if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && | |
007a880d | 13494 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
1da177e4 LT |
13495 | !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) { |
13496 | tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT | | |
13497 | TG3_FLAG_USE_LINKCHG_REG); | |
13498 | } | |
13499 | ||
13500 | /* For all SERDES we poll the MAC status register. */ | |
13501 | if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) | |
13502 | tp->tg3_flags |= TG3_FLAG_POLL_SERDES; | |
13503 | else | |
13504 | tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES; | |
13505 | ||
9dc7a113 | 13506 | tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM; |
d2757fc4 | 13507 | tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; |
1da177e4 | 13508 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 && |
d2757fc4 | 13509 | (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) { |
9dc7a113 | 13510 | tp->rx_offset -= NET_IP_ALIGN; |
d2757fc4 | 13511 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
9dc7a113 | 13512 | tp->rx_copy_thresh = ~(u16)0; |
d2757fc4 MC |
13513 | #endif |
13514 | } | |
1da177e4 | 13515 | |
f92905de MC |
13516 | tp->rx_std_max_post = TG3_RX_RING_SIZE; |
13517 | ||
13518 | /* Increment the rx prod index on the rx std ring by at most | |
13519 | * 8 for these chips to workaround hw errata. | |
13520 | */ | |
13521 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | |
13522 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 || | |
13523 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) | |
13524 | tp->rx_std_max_post = 8; | |
13525 | ||
8ed5d97e MC |
13526 | if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) |
13527 | tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & | |
13528 | PCIE_PWR_MGMT_L1_THRESH_MSK; | |
13529 | ||
1da177e4 LT |
13530 | return err; |
13531 | } | |
13532 | ||
49b6e95f | 13533 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13534 | static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp) |
13535 | { | |
13536 | struct net_device *dev = tp->dev; | |
13537 | struct pci_dev *pdev = tp->pdev; | |
49b6e95f | 13538 | struct device_node *dp = pci_device_to_OF_node(pdev); |
374d4cac | 13539 | const unsigned char *addr; |
49b6e95f DM |
13540 | int len; |
13541 | ||
13542 | addr = of_get_property(dp, "local-mac-address", &len); | |
13543 | if (addr && len == 6) { | |
13544 | memcpy(dev->dev_addr, addr, 6); | |
13545 | memcpy(dev->perm_addr, dev->dev_addr, 6); | |
13546 | return 0; | |
1da177e4 LT |
13547 | } |
13548 | return -ENODEV; | |
13549 | } | |
13550 | ||
13551 | static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp) | |
13552 | { | |
13553 | struct net_device *dev = tp->dev; | |
13554 | ||
13555 | memcpy(dev->dev_addr, idprom->id_ethaddr, 6); | |
2ff43697 | 13556 | memcpy(dev->perm_addr, idprom->id_ethaddr, 6); |
1da177e4 LT |
13557 | return 0; |
13558 | } | |
13559 | #endif | |
13560 | ||
13561 | static int __devinit tg3_get_device_address(struct tg3 *tp) | |
13562 | { | |
13563 | struct net_device *dev = tp->dev; | |
13564 | u32 hi, lo, mac_offset; | |
008652b3 | 13565 | int addr_ok = 0; |
1da177e4 | 13566 | |
49b6e95f | 13567 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13568 | if (!tg3_get_macaddr_sparc(tp)) |
13569 | return 0; | |
13570 | #endif | |
13571 | ||
13572 | mac_offset = 0x7c; | |
f49639e6 | 13573 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) || |
a4e2b347 | 13574 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { |
1da177e4 LT |
13575 | if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) |
13576 | mac_offset = 0xcc; | |
13577 | if (tg3_nvram_lock(tp)) | |
13578 | tw32_f(NVRAM_CMD, NVRAM_CMD_RESET); | |
13579 | else | |
13580 | tg3_nvram_unlock(tp); | |
a1b950d5 MC |
13581 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { |
13582 | if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC) | |
13583 | mac_offset = 0xcc; | |
13584 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | |
b5d3772c | 13585 | mac_offset = 0x10; |
1da177e4 LT |
13586 | |
13587 | /* First try to get it from MAC address mailbox. */ | |
13588 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); | |
13589 | if ((hi >> 16) == 0x484b) { | |
13590 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
13591 | dev->dev_addr[1] = (hi >> 0) & 0xff; | |
13592 | ||
13593 | tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); | |
13594 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
13595 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
13596 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
13597 | dev->dev_addr[5] = (lo >> 0) & 0xff; | |
1da177e4 | 13598 | |
008652b3 MC |
13599 | /* Some old bootcode may report a 0 MAC address in SRAM */ |
13600 | addr_ok = is_valid_ether_addr(&dev->dev_addr[0]); | |
13601 | } | |
13602 | if (!addr_ok) { | |
13603 | /* Next, try NVRAM. */ | |
df259d8c MC |
13604 | if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) && |
13605 | !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && | |
6d348f2c | 13606 | !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { |
62cedd11 MC |
13607 | memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2); |
13608 | memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo)); | |
008652b3 MC |
13609 | } |
13610 | /* Finally just fetch it out of the MAC control regs. */ | |
13611 | else { | |
13612 | hi = tr32(MAC_ADDR_0_HIGH); | |
13613 | lo = tr32(MAC_ADDR_0_LOW); | |
13614 | ||
13615 | dev->dev_addr[5] = lo & 0xff; | |
13616 | dev->dev_addr[4] = (lo >> 8) & 0xff; | |
13617 | dev->dev_addr[3] = (lo >> 16) & 0xff; | |
13618 | dev->dev_addr[2] = (lo >> 24) & 0xff; | |
13619 | dev->dev_addr[1] = hi & 0xff; | |
13620 | dev->dev_addr[0] = (hi >> 8) & 0xff; | |
13621 | } | |
1da177e4 LT |
13622 | } |
13623 | ||
13624 | if (!is_valid_ether_addr(&dev->dev_addr[0])) { | |
7582a335 | 13625 | #ifdef CONFIG_SPARC |
1da177e4 LT |
13626 | if (!tg3_get_default_macaddr_sparc(tp)) |
13627 | return 0; | |
13628 | #endif | |
13629 | return -EINVAL; | |
13630 | } | |
2ff43697 | 13631 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
13632 | return 0; |
13633 | } | |
13634 | ||
59e6b434 DM |
13635 | #define BOUNDARY_SINGLE_CACHELINE 1 |
13636 | #define BOUNDARY_MULTI_CACHELINE 2 | |
13637 | ||
13638 | static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |
13639 | { | |
13640 | int cacheline_size; | |
13641 | u8 byte; | |
13642 | int goal; | |
13643 | ||
13644 | pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); | |
13645 | if (byte == 0) | |
13646 | cacheline_size = 1024; | |
13647 | else | |
13648 | cacheline_size = (int) byte * 4; | |
13649 | ||
13650 | /* On 5703 and later chips, the boundary bits have no | |
13651 | * effect. | |
13652 | */ | |
13653 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && | |
13654 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 && | |
13655 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) | |
13656 | goto out; | |
13657 | ||
13658 | #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC) | |
13659 | goal = BOUNDARY_MULTI_CACHELINE; | |
13660 | #else | |
13661 | #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA) | |
13662 | goal = BOUNDARY_SINGLE_CACHELINE; | |
13663 | #else | |
13664 | goal = 0; | |
13665 | #endif | |
13666 | #endif | |
13667 | ||
b703df6f MC |
13668 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13669 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
cbf9ca6c MC |
13670 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
13671 | goto out; | |
13672 | } | |
13673 | ||
59e6b434 DM |
13674 | if (!goal) |
13675 | goto out; | |
13676 | ||
13677 | /* PCI controllers on most RISC systems tend to disconnect | |
13678 | * when a device tries to burst across a cache-line boundary. | |
13679 | * Therefore, letting tg3 do so just wastes PCI bandwidth. | |
13680 | * | |
13681 | * Unfortunately, for PCI-E there are only limited | |
13682 | * write-side controls for this, and thus for reads | |
13683 | * we will still get the disconnects. We'll also waste | |
13684 | * these PCI cycles for both read and write for chips | |
13685 | * other than 5700 and 5701 which do not implement the | |
13686 | * boundary bits. | |
13687 | */ | |
13688 | if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) && | |
13689 | !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { | |
13690 | switch (cacheline_size) { | |
13691 | case 16: | |
13692 | case 32: | |
13693 | case 64: | |
13694 | case 128: | |
13695 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13696 | val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX | | |
13697 | DMA_RWCTRL_WRITE_BNDRY_128_PCIX); | |
13698 | } else { | |
13699 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
13700 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
13701 | } | |
13702 | break; | |
13703 | ||
13704 | case 256: | |
13705 | val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX | | |
13706 | DMA_RWCTRL_WRITE_BNDRY_256_PCIX); | |
13707 | break; | |
13708 | ||
13709 | default: | |
13710 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | |
13711 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | |
13712 | break; | |
855e1111 | 13713 | } |
59e6b434 DM |
13714 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
13715 | switch (cacheline_size) { | |
13716 | case 16: | |
13717 | case 32: | |
13718 | case 64: | |
13719 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13720 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
13721 | val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE; | |
13722 | break; | |
13723 | } | |
13724 | /* fallthrough */ | |
13725 | case 128: | |
13726 | default: | |
13727 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | |
13728 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | |
13729 | break; | |
855e1111 | 13730 | } |
59e6b434 DM |
13731 | } else { |
13732 | switch (cacheline_size) { | |
13733 | case 16: | |
13734 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13735 | val |= (DMA_RWCTRL_READ_BNDRY_16 | | |
13736 | DMA_RWCTRL_WRITE_BNDRY_16); | |
13737 | break; | |
13738 | } | |
13739 | /* fallthrough */ | |
13740 | case 32: | |
13741 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13742 | val |= (DMA_RWCTRL_READ_BNDRY_32 | | |
13743 | DMA_RWCTRL_WRITE_BNDRY_32); | |
13744 | break; | |
13745 | } | |
13746 | /* fallthrough */ | |
13747 | case 64: | |
13748 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13749 | val |= (DMA_RWCTRL_READ_BNDRY_64 | | |
13750 | DMA_RWCTRL_WRITE_BNDRY_64); | |
13751 | break; | |
13752 | } | |
13753 | /* fallthrough */ | |
13754 | case 128: | |
13755 | if (goal == BOUNDARY_SINGLE_CACHELINE) { | |
13756 | val |= (DMA_RWCTRL_READ_BNDRY_128 | | |
13757 | DMA_RWCTRL_WRITE_BNDRY_128); | |
13758 | break; | |
13759 | } | |
13760 | /* fallthrough */ | |
13761 | case 256: | |
13762 | val |= (DMA_RWCTRL_READ_BNDRY_256 | | |
13763 | DMA_RWCTRL_WRITE_BNDRY_256); | |
13764 | break; | |
13765 | case 512: | |
13766 | val |= (DMA_RWCTRL_READ_BNDRY_512 | | |
13767 | DMA_RWCTRL_WRITE_BNDRY_512); | |
13768 | break; | |
13769 | case 1024: | |
13770 | default: | |
13771 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | |
13772 | DMA_RWCTRL_WRITE_BNDRY_1024); | |
13773 | break; | |
855e1111 | 13774 | } |
59e6b434 DM |
13775 | } |
13776 | ||
13777 | out: | |
13778 | return val; | |
13779 | } | |
13780 | ||
1da177e4 LT |
13781 | static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device) |
13782 | { | |
13783 | struct tg3_internal_buffer_desc test_desc; | |
13784 | u32 sram_dma_descs; | |
13785 | int i, ret; | |
13786 | ||
13787 | sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE; | |
13788 | ||
13789 | tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0); | |
13790 | tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0); | |
13791 | tw32(RDMAC_STATUS, 0); | |
13792 | tw32(WDMAC_STATUS, 0); | |
13793 | ||
13794 | tw32(BUFMGR_MODE, 0); | |
13795 | tw32(FTQ_RESET, 0); | |
13796 | ||
13797 | test_desc.addr_hi = ((u64) buf_dma) >> 32; | |
13798 | test_desc.addr_lo = buf_dma & 0xffffffff; | |
13799 | test_desc.nic_mbuf = 0x00002100; | |
13800 | test_desc.len = size; | |
13801 | ||
13802 | /* | |
13803 | * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz | |
13804 | * the *second* time the tg3 driver was getting loaded after an | |
13805 | * initial scan. | |
13806 | * | |
13807 | * Broadcom tells me: | |
13808 | * ...the DMA engine is connected to the GRC block and a DMA | |
13809 | * reset may affect the GRC block in some unpredictable way... | |
13810 | * The behavior of resets to individual blocks has not been tested. | |
13811 | * | |
13812 | * Broadcom noted the GRC reset will also reset all sub-components. | |
13813 | */ | |
13814 | if (to_device) { | |
13815 | test_desc.cqid_sqid = (13 << 8) | 2; | |
13816 | ||
13817 | tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE); | |
13818 | udelay(40); | |
13819 | } else { | |
13820 | test_desc.cqid_sqid = (16 << 8) | 7; | |
13821 | ||
13822 | tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE); | |
13823 | udelay(40); | |
13824 | } | |
13825 | test_desc.flags = 0x00000005; | |
13826 | ||
13827 | for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) { | |
13828 | u32 val; | |
13829 | ||
13830 | val = *(((u32 *)&test_desc) + i); | |
13831 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, | |
13832 | sram_dma_descs + (i * sizeof(u32))); | |
13833 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); | |
13834 | } | |
13835 | pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); | |
13836 | ||
859a5887 | 13837 | if (to_device) |
1da177e4 | 13838 | tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs); |
859a5887 | 13839 | else |
1da177e4 | 13840 | tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs); |
1da177e4 LT |
13841 | |
13842 | ret = -ENODEV; | |
13843 | for (i = 0; i < 40; i++) { | |
13844 | u32 val; | |
13845 | ||
13846 | if (to_device) | |
13847 | val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ); | |
13848 | else | |
13849 | val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ); | |
13850 | if ((val & 0xffff) == sram_dma_descs) { | |
13851 | ret = 0; | |
13852 | break; | |
13853 | } | |
13854 | ||
13855 | udelay(100); | |
13856 | } | |
13857 | ||
13858 | return ret; | |
13859 | } | |
13860 | ||
ded7340d | 13861 | #define TEST_BUFFER_SIZE 0x2000 |
1da177e4 LT |
13862 | |
13863 | static int __devinit tg3_test_dma(struct tg3 *tp) | |
13864 | { | |
13865 | dma_addr_t buf_dma; | |
59e6b434 | 13866 | u32 *buf, saved_dma_rwctrl; |
cbf9ca6c | 13867 | int ret = 0; |
1da177e4 LT |
13868 | |
13869 | buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma); | |
13870 | if (!buf) { | |
13871 | ret = -ENOMEM; | |
13872 | goto out_nofree; | |
13873 | } | |
13874 | ||
13875 | tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | | |
13876 | (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT)); | |
13877 | ||
59e6b434 | 13878 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
1da177e4 | 13879 | |
b703df6f MC |
13880 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
13881 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | |
cbf9ca6c MC |
13882 | goto out; |
13883 | ||
1da177e4 LT |
13884 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
13885 | /* DMA read watermark not used on PCIE */ | |
13886 | tp->dma_rwctrl |= 0x00180000; | |
13887 | } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { | |
85e94ced MC |
13888 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || |
13889 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) | |
1da177e4 LT |
13890 | tp->dma_rwctrl |= 0x003f0000; |
13891 | else | |
13892 | tp->dma_rwctrl |= 0x003f000f; | |
13893 | } else { | |
13894 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
13895 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) { | |
13896 | u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f); | |
49afdeb6 | 13897 | u32 read_water = 0x7; |
1da177e4 | 13898 | |
4a29cc2e MC |
13899 | /* If the 5704 is behind the EPB bridge, we can |
13900 | * do the less restrictive ONE_DMA workaround for | |
13901 | * better performance. | |
13902 | */ | |
13903 | if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) && | |
13904 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
13905 | tp->dma_rwctrl |= 0x8000; | |
13906 | else if (ccval == 0x6 || ccval == 0x7) | |
1da177e4 LT |
13907 | tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; |
13908 | ||
49afdeb6 MC |
13909 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) |
13910 | read_water = 4; | |
59e6b434 | 13911 | /* Set bit 23 to enable PCIX hw bug fix */ |
49afdeb6 MC |
13912 | tp->dma_rwctrl |= |
13913 | (read_water << DMA_RWCTRL_READ_WATER_SHIFT) | | |
13914 | (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) | | |
13915 | (1 << 23); | |
4cf78e4f MC |
13916 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) { |
13917 | /* 5780 always in PCIX mode */ | |
13918 | tp->dma_rwctrl |= 0x00144000; | |
a4e2b347 MC |
13919 | } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) { |
13920 | /* 5714 always in PCIX mode */ | |
13921 | tp->dma_rwctrl |= 0x00148000; | |
1da177e4 LT |
13922 | } else { |
13923 | tp->dma_rwctrl |= 0x001b000f; | |
13924 | } | |
13925 | } | |
13926 | ||
13927 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 || | |
13928 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) | |
13929 | tp->dma_rwctrl &= 0xfffffff0; | |
13930 | ||
13931 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | |
13932 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) { | |
13933 | /* Remove this if it causes problems for some boards. */ | |
13934 | tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; | |
13935 | ||
13936 | /* On 5700/5701 chips, we need to set this bit. | |
13937 | * Otherwise the chip will issue cacheline transactions | |
13938 | * to streamable DMA memory with not all the byte | |
13939 | * enables turned on. This is an error on several | |
13940 | * RISC PCI controllers, in particular sparc64. | |
13941 | * | |
13942 | * On 5703/5704 chips, this bit has been reassigned | |
13943 | * a different meaning. In particular, it is used | |
13944 | * on those chips to enable a PCI-X workaround. | |
13945 | */ | |
13946 | tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; | |
13947 | } | |
13948 | ||
13949 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
13950 | ||
13951 | #if 0 | |
13952 | /* Unneeded, already done by tg3_get_invariants. */ | |
13953 | tg3_switch_clocks(tp); | |
13954 | #endif | |
13955 | ||
1da177e4 LT |
13956 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 && |
13957 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) | |
13958 | goto out; | |
13959 | ||
59e6b434 DM |
13960 | /* It is best to perform DMA test with maximum write burst size |
13961 | * to expose the 5700/5701 write DMA bug. | |
13962 | */ | |
13963 | saved_dma_rwctrl = tp->dma_rwctrl; | |
13964 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
13965 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
13966 | ||
1da177e4 LT |
13967 | while (1) { |
13968 | u32 *p = buf, i; | |
13969 | ||
13970 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) | |
13971 | p[i] = i; | |
13972 | ||
13973 | /* Send the buffer to the chip. */ | |
13974 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1); | |
13975 | if (ret) { | |
2445e461 MC |
13976 | dev_err(&tp->pdev->dev, |
13977 | "%s: Buffer write failed. err = %d\n", | |
13978 | __func__, ret); | |
1da177e4 LT |
13979 | break; |
13980 | } | |
13981 | ||
13982 | #if 0 | |
13983 | /* validate data reached card RAM correctly. */ | |
13984 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
13985 | u32 val; | |
13986 | tg3_read_mem(tp, 0x2100 + (i*4), &val); | |
13987 | if (le32_to_cpu(val) != p[i]) { | |
2445e461 MC |
13988 | dev_err(&tp->pdev->dev, |
13989 | "%s: Buffer corrupted on device! " | |
13990 | "(%d != %d)\n", __func__, val, i); | |
1da177e4 LT |
13991 | /* ret = -ENODEV here? */ |
13992 | } | |
13993 | p[i] = 0; | |
13994 | } | |
13995 | #endif | |
13996 | /* Now read it back. */ | |
13997 | ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0); | |
13998 | if (ret) { | |
5129c3a3 MC |
13999 | dev_err(&tp->pdev->dev, "%s: Buffer read failed. " |
14000 | "err = %d\n", __func__, ret); | |
1da177e4 LT |
14001 | break; |
14002 | } | |
14003 | ||
14004 | /* Verify it. */ | |
14005 | for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) { | |
14006 | if (p[i] == i) | |
14007 | continue; | |
14008 | ||
59e6b434 DM |
14009 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14010 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
14011 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
1da177e4 LT |
14012 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; |
14013 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); | |
14014 | break; | |
14015 | } else { | |
2445e461 MC |
14016 | dev_err(&tp->pdev->dev, |
14017 | "%s: Buffer corrupted on read back! " | |
14018 | "(%d != %d)\n", __func__, p[i], i); | |
1da177e4 LT |
14019 | ret = -ENODEV; |
14020 | goto out; | |
14021 | } | |
14022 | } | |
14023 | ||
14024 | if (i == (TEST_BUFFER_SIZE / sizeof(u32))) { | |
14025 | /* Success. */ | |
14026 | ret = 0; | |
14027 | break; | |
14028 | } | |
14029 | } | |
59e6b434 DM |
14030 | if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != |
14031 | DMA_RWCTRL_WRITE_BNDRY_16) { | |
6d1cfbab MC |
14032 | static struct pci_device_id dma_wait_state_chipsets[] = { |
14033 | { PCI_DEVICE(PCI_VENDOR_ID_APPLE, | |
14034 | PCI_DEVICE_ID_APPLE_UNI_N_PCI15) }, | |
14035 | { }, | |
14036 | }; | |
14037 | ||
59e6b434 | 14038 | /* DMA test passed without adjusting DMA boundary, |
6d1cfbab MC |
14039 | * now look for chipsets that are known to expose the |
14040 | * DMA bug without failing the test. | |
59e6b434 | 14041 | */ |
6d1cfbab MC |
14042 | if (pci_dev_present(dma_wait_state_chipsets)) { |
14043 | tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; | |
14044 | tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; | |
859a5887 | 14045 | } else { |
6d1cfbab MC |
14046 | /* Safe to use the calculated DMA boundary. */ |
14047 | tp->dma_rwctrl = saved_dma_rwctrl; | |
859a5887 | 14048 | } |
6d1cfbab | 14049 | |
59e6b434 DM |
14050 | tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); |
14051 | } | |
1da177e4 LT |
14052 | |
14053 | out: | |
14054 | pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma); | |
14055 | out_nofree: | |
14056 | return ret; | |
14057 | } | |
14058 | ||
14059 | static void __devinit tg3_init_link_config(struct tg3 *tp) | |
14060 | { | |
14061 | tp->link_config.advertising = | |
14062 | (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
14063 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
14064 | ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full | | |
14065 | ADVERTISED_Autoneg | ADVERTISED_MII); | |
14066 | tp->link_config.speed = SPEED_INVALID; | |
14067 | tp->link_config.duplex = DUPLEX_INVALID; | |
14068 | tp->link_config.autoneg = AUTONEG_ENABLE; | |
1da177e4 LT |
14069 | tp->link_config.active_speed = SPEED_INVALID; |
14070 | tp->link_config.active_duplex = DUPLEX_INVALID; | |
14071 | tp->link_config.phy_is_low_power = 0; | |
14072 | tp->link_config.orig_speed = SPEED_INVALID; | |
14073 | tp->link_config.orig_duplex = DUPLEX_INVALID; | |
14074 | tp->link_config.orig_autoneg = AUTONEG_INVALID; | |
14075 | } | |
14076 | ||
14077 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) | |
14078 | { | |
666bc831 MC |
14079 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || |
14080 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | |
14081 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14082 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14083 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14084 | DEFAULT_MB_MACRX_LOW_WATER_57765; | |
14085 | tp->bufmgr_config.mbuf_high_water = | |
14086 | DEFAULT_MB_HIGH_WATER_57765; | |
14087 | ||
14088 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14089 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14090 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14091 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765; | |
14092 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14093 | DEFAULT_MB_HIGH_WATER_JUMBO_57765; | |
14094 | } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
fdfec172 MC |
14095 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14096 | DEFAULT_MB_RDMA_LOW_WATER_5705; | |
14097 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14098 | DEFAULT_MB_MACRX_LOW_WATER_5705; | |
14099 | tp->bufmgr_config.mbuf_high_water = | |
14100 | DEFAULT_MB_HIGH_WATER_5705; | |
b5d3772c MC |
14101 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { |
14102 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14103 | DEFAULT_MB_MACRX_LOW_WATER_5906; | |
14104 | tp->bufmgr_config.mbuf_high_water = | |
14105 | DEFAULT_MB_HIGH_WATER_5906; | |
14106 | } | |
fdfec172 MC |
14107 | |
14108 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14109 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780; | |
14110 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14111 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780; | |
14112 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14113 | DEFAULT_MB_HIGH_WATER_JUMBO_5780; | |
14114 | } else { | |
14115 | tp->bufmgr_config.mbuf_read_dma_low_water = | |
14116 | DEFAULT_MB_RDMA_LOW_WATER; | |
14117 | tp->bufmgr_config.mbuf_mac_rx_low_water = | |
14118 | DEFAULT_MB_MACRX_LOW_WATER; | |
14119 | tp->bufmgr_config.mbuf_high_water = | |
14120 | DEFAULT_MB_HIGH_WATER; | |
14121 | ||
14122 | tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = | |
14123 | DEFAULT_MB_RDMA_LOW_WATER_JUMBO; | |
14124 | tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = | |
14125 | DEFAULT_MB_MACRX_LOW_WATER_JUMBO; | |
14126 | tp->bufmgr_config.mbuf_high_water_jumbo = | |
14127 | DEFAULT_MB_HIGH_WATER_JUMBO; | |
14128 | } | |
1da177e4 LT |
14129 | |
14130 | tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; | |
14131 | tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; | |
14132 | } | |
14133 | ||
14134 | static char * __devinit tg3_phy_string(struct tg3 *tp) | |
14135 | { | |
79eb6904 MC |
14136 | switch (tp->phy_id & TG3_PHY_ID_MASK) { |
14137 | case TG3_PHY_ID_BCM5400: return "5400"; | |
14138 | case TG3_PHY_ID_BCM5401: return "5401"; | |
14139 | case TG3_PHY_ID_BCM5411: return "5411"; | |
14140 | case TG3_PHY_ID_BCM5701: return "5701"; | |
14141 | case TG3_PHY_ID_BCM5703: return "5703"; | |
14142 | case TG3_PHY_ID_BCM5704: return "5704"; | |
14143 | case TG3_PHY_ID_BCM5705: return "5705"; | |
14144 | case TG3_PHY_ID_BCM5750: return "5750"; | |
14145 | case TG3_PHY_ID_BCM5752: return "5752"; | |
14146 | case TG3_PHY_ID_BCM5714: return "5714"; | |
14147 | case TG3_PHY_ID_BCM5780: return "5780"; | |
14148 | case TG3_PHY_ID_BCM5755: return "5755"; | |
14149 | case TG3_PHY_ID_BCM5787: return "5787"; | |
14150 | case TG3_PHY_ID_BCM5784: return "5784"; | |
14151 | case TG3_PHY_ID_BCM5756: return "5722/5756"; | |
14152 | case TG3_PHY_ID_BCM5906: return "5906"; | |
14153 | case TG3_PHY_ID_BCM5761: return "5761"; | |
14154 | case TG3_PHY_ID_BCM5718C: return "5718C"; | |
14155 | case TG3_PHY_ID_BCM5718S: return "5718S"; | |
14156 | case TG3_PHY_ID_BCM57765: return "57765"; | |
14157 | case TG3_PHY_ID_BCM8002: return "8002/serdes"; | |
1da177e4 LT |
14158 | case 0: return "serdes"; |
14159 | default: return "unknown"; | |
855e1111 | 14160 | } |
1da177e4 LT |
14161 | } |
14162 | ||
f9804ddb MC |
14163 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |
14164 | { | |
14165 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | |
14166 | strcpy(str, "PCI Express"); | |
14167 | return str; | |
14168 | } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) { | |
14169 | u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f; | |
14170 | ||
14171 | strcpy(str, "PCIX:"); | |
14172 | ||
14173 | if ((clock_ctrl == 7) || | |
14174 | ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) == | |
14175 | GRC_MISC_CFG_BOARD_ID_5704CIOBE)) | |
14176 | strcat(str, "133MHz"); | |
14177 | else if (clock_ctrl == 0) | |
14178 | strcat(str, "33MHz"); | |
14179 | else if (clock_ctrl == 2) | |
14180 | strcat(str, "50MHz"); | |
14181 | else if (clock_ctrl == 4) | |
14182 | strcat(str, "66MHz"); | |
14183 | else if (clock_ctrl == 6) | |
14184 | strcat(str, "100MHz"); | |
f9804ddb MC |
14185 | } else { |
14186 | strcpy(str, "PCI:"); | |
14187 | if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) | |
14188 | strcat(str, "66MHz"); | |
14189 | else | |
14190 | strcat(str, "33MHz"); | |
14191 | } | |
14192 | if (tp->tg3_flags & TG3_FLAG_PCI_32BIT) | |
14193 | strcat(str, ":32-bit"); | |
14194 | else | |
14195 | strcat(str, ":64-bit"); | |
14196 | return str; | |
14197 | } | |
14198 | ||
8c2dc7e1 | 14199 | static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp) |
1da177e4 LT |
14200 | { |
14201 | struct pci_dev *peer; | |
14202 | unsigned int func, devnr = tp->pdev->devfn & ~7; | |
14203 | ||
14204 | for (func = 0; func < 8; func++) { | |
14205 | peer = pci_get_slot(tp->pdev->bus, devnr | func); | |
14206 | if (peer && peer != tp->pdev) | |
14207 | break; | |
14208 | pci_dev_put(peer); | |
14209 | } | |
16fe9d74 MC |
14210 | /* 5704 can be configured in single-port mode, set peer to |
14211 | * tp->pdev in that case. | |
14212 | */ | |
14213 | if (!peer) { | |
14214 | peer = tp->pdev; | |
14215 | return peer; | |
14216 | } | |
1da177e4 LT |
14217 | |
14218 | /* | |
14219 | * We don't need to keep the refcount elevated; there's no way | |
14220 | * to remove one half of this device without removing the other | |
14221 | */ | |
14222 | pci_dev_put(peer); | |
14223 | ||
14224 | return peer; | |
14225 | } | |
14226 | ||
15f9850d DM |
14227 | static void __devinit tg3_init_coal(struct tg3 *tp) |
14228 | { | |
14229 | struct ethtool_coalesce *ec = &tp->coal; | |
14230 | ||
14231 | memset(ec, 0, sizeof(*ec)); | |
14232 | ec->cmd = ETHTOOL_GCOALESCE; | |
14233 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; | |
14234 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; | |
14235 | ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; | |
14236 | ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; | |
14237 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; | |
14238 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; | |
14239 | ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; | |
14240 | ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; | |
14241 | ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; | |
14242 | ||
14243 | if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | | |
14244 | HOSTCC_MODE_CLRTICK_TXBD)) { | |
14245 | ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; | |
14246 | ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; | |
14247 | ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; | |
14248 | ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; | |
14249 | } | |
d244c892 MC |
14250 | |
14251 | if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { | |
14252 | ec->rx_coalesce_usecs_irq = 0; | |
14253 | ec->tx_coalesce_usecs_irq = 0; | |
14254 | ec->stats_block_coalesce_usecs = 0; | |
14255 | } | |
15f9850d DM |
14256 | } |
14257 | ||
7c7d64b8 SH |
14258 | static const struct net_device_ops tg3_netdev_ops = { |
14259 | .ndo_open = tg3_open, | |
14260 | .ndo_stop = tg3_close, | |
00829823 SH |
14261 | .ndo_start_xmit = tg3_start_xmit, |
14262 | .ndo_get_stats = tg3_get_stats, | |
14263 | .ndo_validate_addr = eth_validate_addr, | |
14264 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14265 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14266 | .ndo_do_ioctl = tg3_ioctl, | |
14267 | .ndo_tx_timeout = tg3_tx_timeout, | |
14268 | .ndo_change_mtu = tg3_change_mtu, | |
14269 | #if TG3_VLAN_TAG_USED | |
14270 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
14271 | #endif | |
14272 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
14273 | .ndo_poll_controller = tg3_poll_controller, | |
14274 | #endif | |
14275 | }; | |
14276 | ||
14277 | static const struct net_device_ops tg3_netdev_ops_dma_bug = { | |
14278 | .ndo_open = tg3_open, | |
14279 | .ndo_stop = tg3_close, | |
14280 | .ndo_start_xmit = tg3_start_xmit_dma_bug, | |
7c7d64b8 SH |
14281 | .ndo_get_stats = tg3_get_stats, |
14282 | .ndo_validate_addr = eth_validate_addr, | |
14283 | .ndo_set_multicast_list = tg3_set_rx_mode, | |
14284 | .ndo_set_mac_address = tg3_set_mac_addr, | |
14285 | .ndo_do_ioctl = tg3_ioctl, | |
14286 | .ndo_tx_timeout = tg3_tx_timeout, | |
14287 | .ndo_change_mtu = tg3_change_mtu, | |
14288 | #if TG3_VLAN_TAG_USED | |
14289 | .ndo_vlan_rx_register = tg3_vlan_rx_register, | |
14290 | #endif | |
14291 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
14292 | .ndo_poll_controller = tg3_poll_controller, | |
14293 | #endif | |
14294 | }; | |
14295 | ||
1da177e4 LT |
14296 | static int __devinit tg3_init_one(struct pci_dev *pdev, |
14297 | const struct pci_device_id *ent) | |
14298 | { | |
1da177e4 LT |
14299 | struct net_device *dev; |
14300 | struct tg3 *tp; | |
646c9edd MC |
14301 | int i, err, pm_cap; |
14302 | u32 sndmbx, rcvmbx, intmbx; | |
f9804ddb | 14303 | char str[40]; |
72f2afb8 | 14304 | u64 dma_mask, persist_dma_mask; |
1da177e4 | 14305 | |
05dbe005 | 14306 | printk_once(KERN_INFO "%s\n", version); |
1da177e4 LT |
14307 | |
14308 | err = pci_enable_device(pdev); | |
14309 | if (err) { | |
2445e461 | 14310 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
1da177e4 LT |
14311 | return err; |
14312 | } | |
14313 | ||
1da177e4 LT |
14314 | err = pci_request_regions(pdev, DRV_MODULE_NAME); |
14315 | if (err) { | |
2445e461 | 14316 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
1da177e4 LT |
14317 | goto err_out_disable_pdev; |
14318 | } | |
14319 | ||
14320 | pci_set_master(pdev); | |
14321 | ||
14322 | /* Find power-management capability. */ | |
14323 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
14324 | if (pm_cap == 0) { | |
2445e461 MC |
14325 | dev_err(&pdev->dev, |
14326 | "Cannot find Power Management capability, aborting\n"); | |
1da177e4 LT |
14327 | err = -EIO; |
14328 | goto err_out_free_res; | |
14329 | } | |
14330 | ||
fe5f5787 | 14331 | dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); |
1da177e4 | 14332 | if (!dev) { |
2445e461 | 14333 | dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n"); |
1da177e4 LT |
14334 | err = -ENOMEM; |
14335 | goto err_out_free_res; | |
14336 | } | |
14337 | ||
1da177e4 LT |
14338 | SET_NETDEV_DEV(dev, &pdev->dev); |
14339 | ||
1da177e4 LT |
14340 | #if TG3_VLAN_TAG_USED |
14341 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
1da177e4 LT |
14342 | #endif |
14343 | ||
14344 | tp = netdev_priv(dev); | |
14345 | tp->pdev = pdev; | |
14346 | tp->dev = dev; | |
14347 | tp->pm_cap = pm_cap; | |
1da177e4 LT |
14348 | tp->rx_mode = TG3_DEF_RX_MODE; |
14349 | tp->tx_mode = TG3_DEF_TX_MODE; | |
8ef21428 | 14350 | |
1da177e4 LT |
14351 | if (tg3_debug > 0) |
14352 | tp->msg_enable = tg3_debug; | |
14353 | else | |
14354 | tp->msg_enable = TG3_DEF_MSG_ENABLE; | |
14355 | ||
14356 | /* The word/byte swap controls here control register access byte | |
14357 | * swapping. DMA data byte swapping is controlled in the GRC_MODE | |
14358 | * setting below. | |
14359 | */ | |
14360 | tp->misc_host_ctrl = | |
14361 | MISC_HOST_CTRL_MASK_PCI_INT | | |
14362 | MISC_HOST_CTRL_WORD_SWAP | | |
14363 | MISC_HOST_CTRL_INDIR_ACCESS | | |
14364 | MISC_HOST_CTRL_PCISTATE_RW; | |
14365 | ||
14366 | /* The NONFRM (non-frame) byte/word swap controls take effect | |
14367 | * on descriptor entries, anything which isn't packet data. | |
14368 | * | |
14369 | * The StrongARM chips on the board (one for tx, one for rx) | |
14370 | * are running in big-endian mode. | |
14371 | */ | |
14372 | tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | | |
14373 | GRC_MODE_WSWAP_NONFRM_DATA); | |
14374 | #ifdef __BIG_ENDIAN | |
14375 | tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; | |
14376 | #endif | |
14377 | spin_lock_init(&tp->lock); | |
1da177e4 | 14378 | spin_lock_init(&tp->indirect_lock); |
c4028958 | 14379 | INIT_WORK(&tp->reset_task, tg3_reset_task); |
1da177e4 | 14380 | |
d5fe488a | 14381 | tp->regs = pci_ioremap_bar(pdev, BAR_0); |
ab0049b4 | 14382 | if (!tp->regs) { |
ab96b241 | 14383 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
1da177e4 LT |
14384 | err = -ENOMEM; |
14385 | goto err_out_free_dev; | |
14386 | } | |
14387 | ||
14388 | tg3_init_link_config(tp); | |
14389 | ||
1da177e4 LT |
14390 | tp->rx_pending = TG3_DEF_RX_RING_PENDING; |
14391 | tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; | |
1da177e4 | 14392 | |
1da177e4 | 14393 | dev->ethtool_ops = &tg3_ethtool_ops; |
1da177e4 | 14394 | dev->watchdog_timeo = TG3_TX_TIMEOUT; |
1da177e4 | 14395 | dev->irq = pdev->irq; |
1da177e4 LT |
14396 | |
14397 | err = tg3_get_invariants(tp); | |
14398 | if (err) { | |
ab96b241 MC |
14399 | dev_err(&pdev->dev, |
14400 | "Problem fetching invariants of chip, aborting\n"); | |
1da177e4 LT |
14401 | goto err_out_iounmap; |
14402 | } | |
14403 | ||
615774fe MC |
14404 | if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) && |
14405 | tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) | |
00829823 SH |
14406 | dev->netdev_ops = &tg3_netdev_ops; |
14407 | else | |
14408 | dev->netdev_ops = &tg3_netdev_ops_dma_bug; | |
14409 | ||
14410 | ||
4a29cc2e MC |
14411 | /* The EPB bridge inside 5714, 5715, and 5780 and any |
14412 | * device behind the EPB cannot support DMA addresses > 40-bit. | |
72f2afb8 MC |
14413 | * On 64-bit systems with IOMMU, use 40-bit dma_mask. |
14414 | * On 64-bit systems without IOMMU, use 64-bit dma_mask and | |
14415 | * do DMA address check in tg3_start_xmit(). | |
14416 | */ | |
4a29cc2e | 14417 | if (tp->tg3_flags2 & TG3_FLG2_IS_5788) |
284901a9 | 14418 | persist_dma_mask = dma_mask = DMA_BIT_MASK(32); |
4a29cc2e | 14419 | else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) { |
50cf156a | 14420 | persist_dma_mask = dma_mask = DMA_BIT_MASK(40); |
72f2afb8 | 14421 | #ifdef CONFIG_HIGHMEM |
6a35528a | 14422 | dma_mask = DMA_BIT_MASK(64); |
72f2afb8 | 14423 | #endif |
4a29cc2e | 14424 | } else |
6a35528a | 14425 | persist_dma_mask = dma_mask = DMA_BIT_MASK(64); |
72f2afb8 MC |
14426 | |
14427 | /* Configure DMA attributes. */ | |
284901a9 | 14428 | if (dma_mask > DMA_BIT_MASK(32)) { |
72f2afb8 MC |
14429 | err = pci_set_dma_mask(pdev, dma_mask); |
14430 | if (!err) { | |
14431 | dev->features |= NETIF_F_HIGHDMA; | |
14432 | err = pci_set_consistent_dma_mask(pdev, | |
14433 | persist_dma_mask); | |
14434 | if (err < 0) { | |
ab96b241 MC |
14435 | dev_err(&pdev->dev, "Unable to obtain 64 bit " |
14436 | "DMA for consistent allocations\n"); | |
72f2afb8 MC |
14437 | goto err_out_iounmap; |
14438 | } | |
14439 | } | |
14440 | } | |
284901a9 YH |
14441 | if (err || dma_mask == DMA_BIT_MASK(32)) { |
14442 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
72f2afb8 | 14443 | if (err) { |
ab96b241 MC |
14444 | dev_err(&pdev->dev, |
14445 | "No usable DMA configuration, aborting\n"); | |
72f2afb8 MC |
14446 | goto err_out_iounmap; |
14447 | } | |
14448 | } | |
14449 | ||
fdfec172 | 14450 | tg3_init_bufmgr_config(tp); |
1da177e4 | 14451 | |
507399f1 MC |
14452 | /* Selectively allow TSO based on operating conditions */ |
14453 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) || | |
14454 | (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) | |
1da177e4 | 14455 | tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; |
507399f1 MC |
14456 | else { |
14457 | tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG); | |
14458 | tp->fw_needed = NULL; | |
1da177e4 | 14459 | } |
507399f1 MC |
14460 | |
14461 | if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) | |
14462 | tp->fw_needed = FIRMWARE_TG3; | |
1da177e4 | 14463 | |
4e3a7aaa MC |
14464 | /* TSO is on by default on chips that support hardware TSO. |
14465 | * Firmware TSO on older chips gives lower performance, so it | |
14466 | * is off by default, but can be enabled using ethtool. | |
14467 | */ | |
e849cdc3 MC |
14468 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) && |
14469 | (dev->features & NETIF_F_IP_CSUM)) | |
14470 | dev->features |= NETIF_F_TSO; | |
14471 | ||
14472 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) || | |
14473 | (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) { | |
14474 | if (dev->features & NETIF_F_IPV6_CSUM) | |
b0026624 | 14475 | dev->features |= NETIF_F_TSO6; |
e849cdc3 MC |
14476 | if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) || |
14477 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | |
57e6983c MC |
14478 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 && |
14479 | GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) || | |
321d32a0 | 14480 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
e849cdc3 | 14481 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) |
9936bcf6 | 14482 | dev->features |= NETIF_F_TSO_ECN; |
b0026624 | 14483 | } |
1da177e4 | 14484 | |
1da177e4 LT |
14485 | if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 && |
14486 | !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) && | |
14487 | !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) { | |
14488 | tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64; | |
14489 | tp->rx_pending = 63; | |
14490 | } | |
14491 | ||
1da177e4 LT |
14492 | err = tg3_get_device_address(tp); |
14493 | if (err) { | |
ab96b241 MC |
14494 | dev_err(&pdev->dev, |
14495 | "Could not obtain valid ethernet address, aborting\n"); | |
026a6c21 | 14496 | goto err_out_iounmap; |
1da177e4 LT |
14497 | } |
14498 | ||
c88864df | 14499 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) { |
63532394 | 14500 | tp->aperegs = pci_ioremap_bar(pdev, BAR_2); |
79ea13ce | 14501 | if (!tp->aperegs) { |
ab96b241 MC |
14502 | dev_err(&pdev->dev, |
14503 | "Cannot map APE registers, aborting\n"); | |
c88864df | 14504 | err = -ENOMEM; |
026a6c21 | 14505 | goto err_out_iounmap; |
c88864df MC |
14506 | } |
14507 | ||
14508 | tg3_ape_lock_init(tp); | |
7fd76445 MC |
14509 | |
14510 | if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) | |
14511 | tg3_read_dash_ver(tp); | |
c88864df MC |
14512 | } |
14513 | ||
1da177e4 LT |
14514 | /* |
14515 | * Reset chip in case UNDI or EFI driver did not shutdown | |
14516 | * DMA self test will enable WDMAC and we'll see (spurious) | |
14517 | * pending DMA on the PCI bus at that point. | |
14518 | */ | |
14519 | if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) || | |
14520 | (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) { | |
1da177e4 | 14521 | tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); |
944d980e | 14522 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
1da177e4 LT |
14523 | } |
14524 | ||
14525 | err = tg3_test_dma(tp); | |
14526 | if (err) { | |
ab96b241 | 14527 | dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); |
c88864df | 14528 | goto err_out_apeunmap; |
1da177e4 LT |
14529 | } |
14530 | ||
1da177e4 LT |
14531 | /* flow control autonegotiation is default behavior */ |
14532 | tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG; | |
e18ce346 | 14533 | tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; |
1da177e4 | 14534 | |
78f90dcf MC |
14535 | intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW; |
14536 | rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW; | |
14537 | sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW; | |
14538 | for (i = 0; i < TG3_IRQ_MAX_VECS; i++) { | |
14539 | struct tg3_napi *tnapi = &tp->napi[i]; | |
14540 | ||
14541 | tnapi->tp = tp; | |
14542 | tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; | |
14543 | ||
14544 | tnapi->int_mbox = intmbx; | |
14545 | if (i < 4) | |
14546 | intmbx += 0x8; | |
14547 | else | |
14548 | intmbx += 0x4; | |
14549 | ||
14550 | tnapi->consmbox = rcvmbx; | |
14551 | tnapi->prodmbox = sndmbx; | |
14552 | ||
14553 | if (i) { | |
14554 | tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); | |
14555 | netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64); | |
14556 | } else { | |
14557 | tnapi->coal_now = HOSTCC_MODE_NOW; | |
14558 | netif_napi_add(dev, &tnapi->napi, tg3_poll, 64); | |
14559 | } | |
14560 | ||
14561 | if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX)) | |
14562 | break; | |
14563 | ||
14564 | /* | |
14565 | * If we support MSIX, we'll be using RSS. If we're using | |
14566 | * RSS, the first vector only handles link interrupts and the | |
14567 | * remaining vectors handle rx and tx interrupts. Reuse the | |
14568 | * mailbox values for the next iteration. The values we setup | |
14569 | * above are still useful for the single vectored mode. | |
14570 | */ | |
14571 | if (!i) | |
14572 | continue; | |
14573 | ||
14574 | rcvmbx += 0x8; | |
14575 | ||
14576 | if (sndmbx & 0x4) | |
14577 | sndmbx -= 0x4; | |
14578 | else | |
14579 | sndmbx += 0xc; | |
14580 | } | |
14581 | ||
15f9850d DM |
14582 | tg3_init_coal(tp); |
14583 | ||
c49a1561 MC |
14584 | pci_set_drvdata(pdev, dev); |
14585 | ||
1da177e4 LT |
14586 | err = register_netdev(dev); |
14587 | if (err) { | |
ab96b241 | 14588 | dev_err(&pdev->dev, "Cannot register net device, aborting\n"); |
0d3031d9 | 14589 | goto err_out_apeunmap; |
1da177e4 LT |
14590 | } |
14591 | ||
05dbe005 JP |
14592 | netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n", |
14593 | tp->board_part_number, | |
14594 | tp->pci_chip_rev_id, | |
14595 | tg3_bus_string(tp, str), | |
14596 | dev->dev_addr); | |
1da177e4 | 14597 | |
3f0e3ad7 MC |
14598 | if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) { |
14599 | struct phy_device *phydev; | |
14600 | phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]; | |
5129c3a3 MC |
14601 | netdev_info(dev, |
14602 | "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", | |
05dbe005 | 14603 | phydev->drv->name, dev_name(&phydev->dev)); |
3f0e3ad7 | 14604 | } else |
5129c3a3 MC |
14605 | netdev_info(dev, "attached PHY is %s (%s Ethernet) " |
14606 | "(WireSpeed[%d])\n", tg3_phy_string(tp), | |
05dbe005 JP |
14607 | ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" : |
14608 | ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" : | |
14609 | "10/100/1000Base-T")), | |
14610 | (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0); | |
14611 | ||
14612 | netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n", | |
14613 | (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0, | |
14614 | (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0, | |
14615 | (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0, | |
14616 | (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0, | |
14617 | (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0); | |
14618 | netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", | |
14619 | tp->dma_rwctrl, | |
14620 | pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : | |
14621 | ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); | |
1da177e4 LT |
14622 | |
14623 | return 0; | |
14624 | ||
0d3031d9 MC |
14625 | err_out_apeunmap: |
14626 | if (tp->aperegs) { | |
14627 | iounmap(tp->aperegs); | |
14628 | tp->aperegs = NULL; | |
14629 | } | |
14630 | ||
1da177e4 | 14631 | err_out_iounmap: |
6892914f MC |
14632 | if (tp->regs) { |
14633 | iounmap(tp->regs); | |
22abe310 | 14634 | tp->regs = NULL; |
6892914f | 14635 | } |
1da177e4 LT |
14636 | |
14637 | err_out_free_dev: | |
14638 | free_netdev(dev); | |
14639 | ||
14640 | err_out_free_res: | |
14641 | pci_release_regions(pdev); | |
14642 | ||
14643 | err_out_disable_pdev: | |
14644 | pci_disable_device(pdev); | |
14645 | pci_set_drvdata(pdev, NULL); | |
14646 | return err; | |
14647 | } | |
14648 | ||
14649 | static void __devexit tg3_remove_one(struct pci_dev *pdev) | |
14650 | { | |
14651 | struct net_device *dev = pci_get_drvdata(pdev); | |
14652 | ||
14653 | if (dev) { | |
14654 | struct tg3 *tp = netdev_priv(dev); | |
14655 | ||
077f849d JSR |
14656 | if (tp->fw) |
14657 | release_firmware(tp->fw); | |
14658 | ||
7faa006f | 14659 | flush_scheduled_work(); |
158d7abd | 14660 | |
b02fd9e3 MC |
14661 | if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) { |
14662 | tg3_phy_fini(tp); | |
158d7abd | 14663 | tg3_mdio_fini(tp); |
b02fd9e3 | 14664 | } |
158d7abd | 14665 | |
1da177e4 | 14666 | unregister_netdev(dev); |
0d3031d9 MC |
14667 | if (tp->aperegs) { |
14668 | iounmap(tp->aperegs); | |
14669 | tp->aperegs = NULL; | |
14670 | } | |
6892914f MC |
14671 | if (tp->regs) { |
14672 | iounmap(tp->regs); | |
22abe310 | 14673 | tp->regs = NULL; |
6892914f | 14674 | } |
1da177e4 LT |
14675 | free_netdev(dev); |
14676 | pci_release_regions(pdev); | |
14677 | pci_disable_device(pdev); | |
14678 | pci_set_drvdata(pdev, NULL); | |
14679 | } | |
14680 | } | |
14681 | ||
14682 | static int tg3_suspend(struct pci_dev *pdev, pm_message_t state) | |
14683 | { | |
14684 | struct net_device *dev = pci_get_drvdata(pdev); | |
14685 | struct tg3 *tp = netdev_priv(dev); | |
12dac075 | 14686 | pci_power_t target_state; |
1da177e4 LT |
14687 | int err; |
14688 | ||
3e0c95fd MC |
14689 | /* PCI register 4 needs to be saved whether netif_running() or not. |
14690 | * MSI address and data need to be saved if using MSI and | |
14691 | * netif_running(). | |
14692 | */ | |
14693 | pci_save_state(pdev); | |
14694 | ||
1da177e4 LT |
14695 | if (!netif_running(dev)) |
14696 | return 0; | |
14697 | ||
7faa006f | 14698 | flush_scheduled_work(); |
b02fd9e3 | 14699 | tg3_phy_stop(tp); |
1da177e4 LT |
14700 | tg3_netif_stop(tp); |
14701 | ||
14702 | del_timer_sync(&tp->timer); | |
14703 | ||
f47c11ee | 14704 | tg3_full_lock(tp, 1); |
1da177e4 | 14705 | tg3_disable_ints(tp); |
f47c11ee | 14706 | tg3_full_unlock(tp); |
1da177e4 LT |
14707 | |
14708 | netif_device_detach(dev); | |
14709 | ||
f47c11ee | 14710 | tg3_full_lock(tp, 0); |
944d980e | 14711 | tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); |
6a9eba15 | 14712 | tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE; |
f47c11ee | 14713 | tg3_full_unlock(tp); |
1da177e4 | 14714 | |
12dac075 RW |
14715 | target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot; |
14716 | ||
14717 | err = tg3_set_power_state(tp, target_state); | |
1da177e4 | 14718 | if (err) { |
b02fd9e3 MC |
14719 | int err2; |
14720 | ||
f47c11ee | 14721 | tg3_full_lock(tp, 0); |
1da177e4 | 14722 | |
6a9eba15 | 14723 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b02fd9e3 MC |
14724 | err2 = tg3_restart_hw(tp, 1); |
14725 | if (err2) | |
b9ec6c1b | 14726 | goto out; |
1da177e4 LT |
14727 | |
14728 | tp->timer.expires = jiffies + tp->timer_offset; | |
14729 | add_timer(&tp->timer); | |
14730 | ||
14731 | netif_device_attach(dev); | |
14732 | tg3_netif_start(tp); | |
14733 | ||
b9ec6c1b | 14734 | out: |
f47c11ee | 14735 | tg3_full_unlock(tp); |
b02fd9e3 MC |
14736 | |
14737 | if (!err2) | |
14738 | tg3_phy_start(tp); | |
1da177e4 LT |
14739 | } |
14740 | ||
14741 | return err; | |
14742 | } | |
14743 | ||
14744 | static int tg3_resume(struct pci_dev *pdev) | |
14745 | { | |
14746 | struct net_device *dev = pci_get_drvdata(pdev); | |
14747 | struct tg3 *tp = netdev_priv(dev); | |
14748 | int err; | |
14749 | ||
3e0c95fd MC |
14750 | pci_restore_state(tp->pdev); |
14751 | ||
1da177e4 LT |
14752 | if (!netif_running(dev)) |
14753 | return 0; | |
14754 | ||
bc1c7567 | 14755 | err = tg3_set_power_state(tp, PCI_D0); |
1da177e4 LT |
14756 | if (err) |
14757 | return err; | |
14758 | ||
14759 | netif_device_attach(dev); | |
14760 | ||
f47c11ee | 14761 | tg3_full_lock(tp, 0); |
1da177e4 | 14762 | |
6a9eba15 | 14763 | tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE; |
b9ec6c1b MC |
14764 | err = tg3_restart_hw(tp, 1); |
14765 | if (err) | |
14766 | goto out; | |
1da177e4 LT |
14767 | |
14768 | tp->timer.expires = jiffies + tp->timer_offset; | |
14769 | add_timer(&tp->timer); | |
14770 | ||
1da177e4 LT |
14771 | tg3_netif_start(tp); |
14772 | ||
b9ec6c1b | 14773 | out: |
f47c11ee | 14774 | tg3_full_unlock(tp); |
1da177e4 | 14775 | |
b02fd9e3 MC |
14776 | if (!err) |
14777 | tg3_phy_start(tp); | |
14778 | ||
b9ec6c1b | 14779 | return err; |
1da177e4 LT |
14780 | } |
14781 | ||
14782 | static struct pci_driver tg3_driver = { | |
14783 | .name = DRV_MODULE_NAME, | |
14784 | .id_table = tg3_pci_tbl, | |
14785 | .probe = tg3_init_one, | |
14786 | .remove = __devexit_p(tg3_remove_one), | |
14787 | .suspend = tg3_suspend, | |
14788 | .resume = tg3_resume | |
14789 | }; | |
14790 | ||
14791 | static int __init tg3_init(void) | |
14792 | { | |
29917620 | 14793 | return pci_register_driver(&tg3_driver); |
1da177e4 LT |
14794 | } |
14795 | ||
14796 | static void __exit tg3_cleanup(void) | |
14797 | { | |
14798 | pci_unregister_driver(&tg3_driver); | |
14799 | } | |
14800 | ||
14801 | module_init(tg3_init); | |
14802 | module_exit(tg3_cleanup); |