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5e123b84 ZR |
1 | /* |
2 | * (C) Copyright 2005 Tundra Semiconductor Corp. | |
3 | * Kong Lai, <kong.lai@tundra.com). | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * net/tsi108_eth.h - definitions for Tsi108 GIGE network controller. | |
26 | */ | |
27 | ||
28 | #ifndef __TSI108_ETH_H | |
29 | #define __TSI108_ETH_H | |
30 | ||
31 | #include <linux/types.h> | |
32 | ||
33 | #define TSI_WRITE(offset, val) \ | |
34 | out_be32((data->regs + (offset)), val) | |
35 | ||
36 | #define TSI_READ(offset) \ | |
37 | in_be32((data->regs + (offset))) | |
38 | ||
39 | #define TSI_WRITE_PHY(offset, val) \ | |
40 | out_be32((data->phyregs + (offset)), val) | |
41 | ||
42 | #define TSI_READ_PHY(offset) \ | |
43 | in_be32((data->phyregs + (offset))) | |
44 | ||
5e123b84 ZR |
45 | /* |
46 | * TSI108 GIGE port registers | |
47 | */ | |
48 | ||
49 | #define TSI108_ETH_PORT_NUM 2 | |
50 | #define TSI108_PBM_PORT 2 | |
51 | #define TSI108_SDRAM_PORT 4 | |
52 | ||
53 | #define TSI108_MAC_CFG1 (0x000) | |
54 | #define TSI108_MAC_CFG1_SOFTRST (1 << 31) | |
55 | #define TSI108_MAC_CFG1_LOOPBACK (1 << 8) | |
56 | #define TSI108_MAC_CFG1_RXEN (1 << 2) | |
57 | #define TSI108_MAC_CFG1_TXEN (1 << 0) | |
58 | ||
59 | #define TSI108_MAC_CFG2 (0x004) | |
60 | #define TSI108_MAC_CFG2_DFLT_PREAMBLE (7 << 12) | |
61 | #define TSI108_MAC_CFG2_IFACE_MASK (3 << 8) | |
62 | #define TSI108_MAC_CFG2_NOGIG (1 << 8) | |
63 | #define TSI108_MAC_CFG2_GIG (2 << 8) | |
64 | #define TSI108_MAC_CFG2_PADCRC (1 << 2) | |
65 | #define TSI108_MAC_CFG2_FULLDUPLEX (1 << 0) | |
66 | ||
67 | #define TSI108_MAC_MII_MGMT_CFG (0x020) | |
68 | #define TSI108_MAC_MII_MGMT_CLK (7 << 0) | |
69 | #define TSI108_MAC_MII_MGMT_RST (1 << 31) | |
70 | ||
71 | #define TSI108_MAC_MII_CMD (0x024) | |
72 | #define TSI108_MAC_MII_CMD_READ (1 << 0) | |
73 | ||
74 | #define TSI108_MAC_MII_ADDR (0x028) | |
75 | #define TSI108_MAC_MII_ADDR_REG 0 | |
76 | #define TSI108_MAC_MII_ADDR_PHY 8 | |
77 | ||
78 | #define TSI108_MAC_MII_DATAOUT (0x02c) | |
79 | #define TSI108_MAC_MII_DATAIN (0x030) | |
80 | ||
81 | #define TSI108_MAC_MII_IND (0x034) | |
82 | #define TSI108_MAC_MII_IND_NOTVALID (1 << 2) | |
83 | #define TSI108_MAC_MII_IND_SCANNING (1 << 1) | |
84 | #define TSI108_MAC_MII_IND_BUSY (1 << 0) | |
85 | ||
86 | #define TSI108_MAC_IFCTRL (0x038) | |
87 | #define TSI108_MAC_IFCTRL_PHYMODE (1 << 24) | |
88 | ||
89 | #define TSI108_MAC_ADDR1 (0x040) | |
90 | #define TSI108_MAC_ADDR2 (0x044) | |
91 | ||
92 | #define TSI108_STAT_RXBYTES (0x06c) | |
93 | #define TSI108_STAT_RXBYTES_CARRY (1 << 24) | |
94 | ||
95 | #define TSI108_STAT_RXPKTS (0x070) | |
96 | #define TSI108_STAT_RXPKTS_CARRY (1 << 18) | |
97 | ||
98 | #define TSI108_STAT_RXFCS (0x074) | |
99 | #define TSI108_STAT_RXFCS_CARRY (1 << 12) | |
100 | ||
101 | #define TSI108_STAT_RXMCAST (0x078) | |
102 | #define TSI108_STAT_RXMCAST_CARRY (1 << 18) | |
103 | ||
104 | #define TSI108_STAT_RXALIGN (0x08c) | |
105 | #define TSI108_STAT_RXALIGN_CARRY (1 << 12) | |
106 | ||
107 | #define TSI108_STAT_RXLENGTH (0x090) | |
108 | #define TSI108_STAT_RXLENGTH_CARRY (1 << 12) | |
109 | ||
110 | #define TSI108_STAT_RXRUNT (0x09c) | |
111 | #define TSI108_STAT_RXRUNT_CARRY (1 << 12) | |
112 | ||
113 | #define TSI108_STAT_RXJUMBO (0x0a0) | |
114 | #define TSI108_STAT_RXJUMBO_CARRY (1 << 12) | |
115 | ||
116 | #define TSI108_STAT_RXFRAG (0x0a4) | |
117 | #define TSI108_STAT_RXFRAG_CARRY (1 << 12) | |
118 | ||
119 | #define TSI108_STAT_RXJABBER (0x0a8) | |
120 | #define TSI108_STAT_RXJABBER_CARRY (1 << 12) | |
121 | ||
122 | #define TSI108_STAT_RXDROP (0x0ac) | |
123 | #define TSI108_STAT_RXDROP_CARRY (1 << 12) | |
124 | ||
125 | #define TSI108_STAT_TXBYTES (0x0b0) | |
126 | #define TSI108_STAT_TXBYTES_CARRY (1 << 24) | |
127 | ||
128 | #define TSI108_STAT_TXPKTS (0x0b4) | |
129 | #define TSI108_STAT_TXPKTS_CARRY (1 << 18) | |
130 | ||
131 | #define TSI108_STAT_TXEXDEF (0x0c8) | |
132 | #define TSI108_STAT_TXEXDEF_CARRY (1 << 12) | |
133 | ||
134 | #define TSI108_STAT_TXEXCOL (0x0d8) | |
135 | #define TSI108_STAT_TXEXCOL_CARRY (1 << 12) | |
136 | ||
137 | #define TSI108_STAT_TXTCOL (0x0dc) | |
138 | #define TSI108_STAT_TXTCOL_CARRY (1 << 13) | |
139 | ||
140 | #define TSI108_STAT_TXPAUSEDROP (0x0e4) | |
141 | #define TSI108_STAT_TXPAUSEDROP_CARRY (1 << 12) | |
142 | ||
143 | #define TSI108_STAT_CARRY1 (0x100) | |
144 | #define TSI108_STAT_CARRY1_RXBYTES (1 << 16) | |
145 | #define TSI108_STAT_CARRY1_RXPKTS (1 << 15) | |
146 | #define TSI108_STAT_CARRY1_RXFCS (1 << 14) | |
147 | #define TSI108_STAT_CARRY1_RXMCAST (1 << 13) | |
148 | #define TSI108_STAT_CARRY1_RXALIGN (1 << 8) | |
149 | #define TSI108_STAT_CARRY1_RXLENGTH (1 << 7) | |
150 | #define TSI108_STAT_CARRY1_RXRUNT (1 << 4) | |
151 | #define TSI108_STAT_CARRY1_RXJUMBO (1 << 3) | |
152 | #define TSI108_STAT_CARRY1_RXFRAG (1 << 2) | |
153 | #define TSI108_STAT_CARRY1_RXJABBER (1 << 1) | |
154 | #define TSI108_STAT_CARRY1_RXDROP (1 << 0) | |
155 | ||
156 | #define TSI108_STAT_CARRY2 (0x104) | |
157 | #define TSI108_STAT_CARRY2_TXBYTES (1 << 13) | |
158 | #define TSI108_STAT_CARRY2_TXPKTS (1 << 12) | |
159 | #define TSI108_STAT_CARRY2_TXEXDEF (1 << 7) | |
160 | #define TSI108_STAT_CARRY2_TXEXCOL (1 << 3) | |
161 | #define TSI108_STAT_CARRY2_TXTCOL (1 << 2) | |
162 | #define TSI108_STAT_CARRY2_TXPAUSE (1 << 0) | |
163 | ||
164 | #define TSI108_STAT_CARRYMASK1 (0x108) | |
165 | #define TSI108_STAT_CARRYMASK2 (0x10c) | |
166 | ||
167 | #define TSI108_EC_PORTCTRL (0x200) | |
168 | #define TSI108_EC_PORTCTRL_STATRST (1 << 31) | |
169 | #define TSI108_EC_PORTCTRL_STATEN (1 << 28) | |
170 | #define TSI108_EC_PORTCTRL_NOGIG (1 << 18) | |
171 | #define TSI108_EC_PORTCTRL_HALFDUPLEX (1 << 16) | |
172 | ||
173 | #define TSI108_EC_INTSTAT (0x204) | |
174 | #define TSI108_EC_INTMASK (0x208) | |
175 | ||
176 | #define TSI108_INT_ANY (1 << 31) | |
177 | #define TSI108_INT_SFN (1 << 30) | |
178 | #define TSI108_INT_RXIDLE (1 << 29) | |
179 | #define TSI108_INT_RXABORT (1 << 28) | |
180 | #define TSI108_INT_RXERROR (1 << 27) | |
181 | #define TSI108_INT_RXOVERRUN (1 << 26) | |
182 | #define TSI108_INT_RXTHRESH (1 << 25) | |
183 | #define TSI108_INT_RXWAIT (1 << 24) | |
184 | #define TSI108_INT_RXQUEUE0 (1 << 16) | |
185 | #define TSI108_INT_STATCARRY (1 << 15) | |
186 | #define TSI108_INT_TXIDLE (1 << 13) | |
187 | #define TSI108_INT_TXABORT (1 << 12) | |
188 | #define TSI108_INT_TXERROR (1 << 11) | |
189 | #define TSI108_INT_TXUNDERRUN (1 << 10) | |
190 | #define TSI108_INT_TXTHRESH (1 << 9) | |
191 | #define TSI108_INT_TXWAIT (1 << 8) | |
192 | #define TSI108_INT_TXQUEUE0 (1 << 0) | |
193 | ||
194 | #define TSI108_EC_TXCFG (0x220) | |
195 | #define TSI108_EC_TXCFG_RST (1 << 31) | |
196 | ||
197 | #define TSI108_EC_TXCTRL (0x224) | |
198 | #define TSI108_EC_TXCTRL_IDLEINT (1 << 31) | |
199 | #define TSI108_EC_TXCTRL_ABORT (1 << 30) | |
200 | #define TSI108_EC_TXCTRL_GO (1 << 15) | |
201 | #define TSI108_EC_TXCTRL_QUEUE0 (1 << 0) | |
202 | ||
203 | #define TSI108_EC_TXSTAT (0x228) | |
204 | #define TSI108_EC_TXSTAT_ACTIVE (1 << 15) | |
205 | #define TSI108_EC_TXSTAT_QUEUE0 (1 << 0) | |
206 | ||
207 | #define TSI108_EC_TXESTAT (0x22c) | |
208 | #define TSI108_EC_TXESTAT_Q0_ERR (1 << 24) | |
209 | #define TSI108_EC_TXESTAT_Q0_DESCINT (1 << 16) | |
210 | #define TSI108_EC_TXESTAT_Q0_EOF (1 << 8) | |
211 | #define TSI108_EC_TXESTAT_Q0_EOQ (1 << 0) | |
212 | ||
213 | #define TSI108_EC_TXERR (0x278) | |
214 | ||
215 | #define TSI108_EC_TXQ_CFG (0x280) | |
216 | #define TSI108_EC_TXQ_CFG_DESC_INT (1 << 20) | |
217 | #define TSI108_EC_TXQ_CFG_EOQ_OWN_INT (1 << 19) | |
218 | #define TSI108_EC_TXQ_CFG_WSWP (1 << 11) | |
219 | #define TSI108_EC_TXQ_CFG_BSWP (1 << 10) | |
220 | #define TSI108_EC_TXQ_CFG_SFNPORT 0 | |
221 | ||
222 | #define TSI108_EC_TXQ_BUFCFG (0x284) | |
223 | #define TSI108_EC_TXQ_BUFCFG_BURST8 (0 << 8) | |
224 | #define TSI108_EC_TXQ_BUFCFG_BURST32 (1 << 8) | |
225 | #define TSI108_EC_TXQ_BUFCFG_BURST128 (2 << 8) | |
226 | #define TSI108_EC_TXQ_BUFCFG_BURST256 (3 << 8) | |
227 | #define TSI108_EC_TXQ_BUFCFG_WSWP (1 << 11) | |
228 | #define TSI108_EC_TXQ_BUFCFG_BSWP (1 << 10) | |
229 | #define TSI108_EC_TXQ_BUFCFG_SFNPORT 0 | |
230 | ||
231 | #define TSI108_EC_TXQ_PTRLOW (0x288) | |
232 | ||
233 | #define TSI108_EC_TXQ_PTRHIGH (0x28c) | |
234 | #define TSI108_EC_TXQ_PTRHIGH_VALID (1 << 31) | |
235 | ||
236 | #define TSI108_EC_TXTHRESH (0x230) | |
237 | #define TSI108_EC_TXTHRESH_STARTFILL 0 | |
238 | #define TSI108_EC_TXTHRESH_STOPFILL 16 | |
239 | ||
240 | #define TSI108_EC_RXCFG (0x320) | |
241 | #define TSI108_EC_RXCFG_RST (1 << 31) | |
242 | ||
243 | #define TSI108_EC_RXSTAT (0x328) | |
244 | #define TSI108_EC_RXSTAT_ACTIVE (1 << 15) | |
245 | #define TSI108_EC_RXSTAT_QUEUE0 (1 << 0) | |
246 | ||
247 | #define TSI108_EC_RXESTAT (0x32c) | |
248 | #define TSI108_EC_RXESTAT_Q0_ERR (1 << 24) | |
249 | #define TSI108_EC_RXESTAT_Q0_DESCINT (1 << 16) | |
250 | #define TSI108_EC_RXESTAT_Q0_EOF (1 << 8) | |
251 | #define TSI108_EC_RXESTAT_Q0_EOQ (1 << 0) | |
252 | ||
253 | #define TSI108_EC_HASHADDR (0x360) | |
254 | #define TSI108_EC_HASHADDR_AUTOINC (1 << 31) | |
255 | #define TSI108_EC_HASHADDR_DO1STREAD (1 << 30) | |
256 | #define TSI108_EC_HASHADDR_UNICAST (0 << 4) | |
257 | #define TSI108_EC_HASHADDR_MCAST (1 << 4) | |
258 | ||
259 | #define TSI108_EC_HASHDATA (0x364) | |
260 | ||
261 | #define TSI108_EC_RXQ_PTRLOW (0x388) | |
262 | ||
263 | #define TSI108_EC_RXQ_PTRHIGH (0x38c) | |
264 | #define TSI108_EC_RXQ_PTRHIGH_VALID (1 << 31) | |
265 | ||
266 | /* Station Enable -- accept packets destined for us */ | |
267 | #define TSI108_EC_RXCFG_SE (1 << 13) | |
268 | /* Unicast Frame Enable -- for packets not destined for us */ | |
269 | #define TSI108_EC_RXCFG_UFE (1 << 12) | |
270 | /* Multicast Frame Enable */ | |
271 | #define TSI108_EC_RXCFG_MFE (1 << 11) | |
272 | /* Broadcast Frame Enable */ | |
273 | #define TSI108_EC_RXCFG_BFE (1 << 10) | |
274 | #define TSI108_EC_RXCFG_UC_HASH (1 << 9) | |
275 | #define TSI108_EC_RXCFG_MC_HASH (1 << 8) | |
276 | ||
277 | #define TSI108_EC_RXQ_CFG (0x380) | |
278 | #define TSI108_EC_RXQ_CFG_DESC_INT (1 << 20) | |
279 | #define TSI108_EC_RXQ_CFG_EOQ_OWN_INT (1 << 19) | |
280 | #define TSI108_EC_RXQ_CFG_WSWP (1 << 11) | |
281 | #define TSI108_EC_RXQ_CFG_BSWP (1 << 10) | |
282 | #define TSI108_EC_RXQ_CFG_SFNPORT 0 | |
283 | ||
284 | #define TSI108_EC_RXQ_BUFCFG (0x384) | |
285 | #define TSI108_EC_RXQ_BUFCFG_BURST8 (0 << 8) | |
286 | #define TSI108_EC_RXQ_BUFCFG_BURST32 (1 << 8) | |
287 | #define TSI108_EC_RXQ_BUFCFG_BURST128 (2 << 8) | |
288 | #define TSI108_EC_RXQ_BUFCFG_BURST256 (3 << 8) | |
289 | #define TSI108_EC_RXQ_BUFCFG_WSWP (1 << 11) | |
290 | #define TSI108_EC_RXQ_BUFCFG_BSWP (1 << 10) | |
291 | #define TSI108_EC_RXQ_BUFCFG_SFNPORT 0 | |
292 | ||
293 | #define TSI108_EC_RXCTRL (0x324) | |
294 | #define TSI108_EC_RXCTRL_ABORT (1 << 30) | |
295 | #define TSI108_EC_RXCTRL_GO (1 << 15) | |
296 | #define TSI108_EC_RXCTRL_QUEUE0 (1 << 0) | |
297 | ||
298 | #define TSI108_EC_RXERR (0x378) | |
299 | ||
300 | #define TSI108_TX_EOF (1 << 0) /* End of frame; last fragment of packet */ | |
301 | #define TSI108_TX_SOF (1 << 1) /* Start of frame; first frag. of packet */ | |
302 | #define TSI108_TX_VLAN (1 << 2) /* Per-frame VLAN: enables VLAN override */ | |
303 | #define TSI108_TX_HUGE (1 << 3) /* Huge frame enable */ | |
304 | #define TSI108_TX_PAD (1 << 4) /* Pad the packet if too short */ | |
305 | #define TSI108_TX_CRC (1 << 5) /* Generate CRC for this packet */ | |
306 | #define TSI108_TX_INT (1 << 14) /* Generate an IRQ after frag. processed */ | |
307 | #define TSI108_TX_RETRY (0xf << 16) /* 4 bit field indicating num. of retries */ | |
308 | #define TSI108_TX_COL (1 << 20) /* Set if a collision occured */ | |
309 | #define TSI108_TX_LCOL (1 << 24) /* Set if a late collision occured */ | |
310 | #define TSI108_TX_UNDER (1 << 25) /* Set if a FIFO underrun occured */ | |
311 | #define TSI108_TX_RLIM (1 << 26) /* Set if the retry limit was reached */ | |
312 | #define TSI108_TX_OK (1 << 30) /* Set if the frame TX was successful */ | |
313 | #define TSI108_TX_OWN (1 << 31) /* Set if the device owns the descriptor */ | |
314 | ||
315 | /* Note: the descriptor layouts assume big-endian byte order. */ | |
316 | typedef struct { | |
317 | u32 buf0; | |
318 | u32 buf1; /* Base address of buffer */ | |
319 | u32 next0; /* Address of next descriptor, if any */ | |
320 | u32 next1; | |
321 | u16 vlan; /* VLAN, if override enabled for this packet */ | |
322 | u16 len; /* Length of buffer in bytes */ | |
323 | u32 misc; /* See TSI108_TX_* above */ | |
324 | u32 reserved0; /*reserved0 and reserved1 are added to make the desc */ | |
325 | u32 reserved1; /* 32-byte aligned */ | |
326 | } __attribute__ ((aligned(32))) tx_desc; | |
327 | ||
328 | #define TSI108_RX_EOF (1 << 0) /* End of frame; last fragment of packet */ | |
329 | #define TSI108_RX_SOF (1 << 1) /* Start of frame; first frag. of packet */ | |
330 | #define TSI108_RX_VLAN (1 << 2) /* Set on SOF if packet has a VLAN */ | |
331 | #define TSI108_RX_FTYPE (1 << 3) /* Length/Type field is type, not length */ | |
332 | #define TSI108_RX_RUNT (1 << 4)/* Packet is less than minimum size */ | |
333 | #define TSI108_RX_HASH (1 << 7)/* Hash table match */ | |
334 | #define TSI108_RX_BAD (1 << 8) /* Bad frame */ | |
335 | #define TSI108_RX_OVER (1 << 9) /* FIFO overrun occured */ | |
336 | #define TSI108_RX_TRUNC (1 << 11) /* Packet truncated due to excess length */ | |
337 | #define TSI108_RX_CRC (1 << 12) /* Packet had a CRC error */ | |
338 | #define TSI108_RX_INT (1 << 13) /* Generate an IRQ after frag. processed */ | |
339 | #define TSI108_RX_OWN (1 << 15) /* Set if the device owns the descriptor */ | |
340 | ||
341 | #define TSI108_RX_SKB_SIZE 1536 /* The RX skb length */ | |
342 | ||
343 | typedef struct { | |
344 | u32 buf0; /* Base address of buffer */ | |
345 | u32 buf1; /* Base address of buffer */ | |
346 | u32 next0; /* Address of next descriptor, if any */ | |
347 | u32 next1; /* Address of next descriptor, if any */ | |
348 | u16 vlan; /* VLAN of received packet, first frag only */ | |
349 | u16 len; /* Length of received fragment in bytes */ | |
350 | u16 blen; /* Length of buffer in bytes */ | |
351 | u16 misc; /* See TSI108_RX_* above */ | |
352 | u32 reserved0; /* reserved0 and reserved1 are added to make the desc */ | |
353 | u32 reserved1; /* 32-byte aligned */ | |
354 | } __attribute__ ((aligned(32))) rx_desc; | |
355 | ||
356 | #endif /* __TSI108_ETH_H */ |