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[deliverable/linux.git] / drivers / net / tulip / tulip_core.c
CommitLineData
1da177e4
LT		 1/* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux. */
2
3/*
6b92801b 4 Maintained by Valerie Henson <val_henson@linux.intel.com>
1da177e4
LT		 5 Copyright 2000,2001 The Linux Kernel Team
6 Written/copyright 1994-2001 by Donald Becker.
7
8 This software may be used and distributed according to the terms
9 of the GNU General Public License, incorporated herein by reference.
10
11 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
12 for more information on this driver, or visit the project
13 Web page at http://sourceforge.net/projects/tulip/
14
15*/
16
1da177e4
LT		 17
18#define DRV_NAME "tulip"
19#ifdef CONFIG_TULIP_NAPI
6bab99be 20#define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
1da177e4 21#else
6bab99be 22#define DRV_VERSION "1.1.15"
1da177e4 23#endif
6bab99be 24#define DRV_RELDATE "Feb 27, 2007"
1da177e4
LT		 25
26
27#include <linux/module.h>
28#include <linux/pci.h>
29#include "tulip.h"
30#include <linux/init.h>
31#include <linux/etherdevice.h>
32#include <linux/delay.h>
33#include <linux/mii.h>
34#include <linux/ethtool.h>
35#include <linux/crc32.h>
36#include <asm/unaligned.h>
37#include <asm/uaccess.h>
38
49345103 39#ifdef CONFIG_SPARC
d297c31f 40#include <asm/prom.h>
1da177e4
LT		 41#endif
42
43static char version[] __devinitdata =
44 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
45
46
47/* A few user-configurable values. */
48
49/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
50static unsigned int max_interrupt_work = 25;
51
52#define MAX_UNITS 8
53/* Used to pass the full-duplex flag, etc. */
54static int full_duplex[MAX_UNITS];
55static int options[MAX_UNITS];
56static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
57
58/* The possible media types that can be set in options[] are: */
59const char * const medianame[32] = {
60 "10baseT", "10base2", "AUI", "100baseTx",
61 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
62 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
63 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
64 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
65 "","","","", "","","","", "","","","Transceiver reset",
66};
67
68/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
69#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
49345103 70 || defined(CONFIG_SPARC) || defined(__ia64__) \
1da177e4
LT		 71 || defined(__sh__) || defined(__mips__)
72static int rx_copybreak = 1518;
73#else
74static int rx_copybreak = 100;
75#endif
76
77/*
78 Set the bus performance register.
79 Typical: Set 16 longword cache alignment, no burst limit.
80 Cache alignment bits 15:14 Burst length 13:8
81 0000 No alignment 0x00000000 unlimited 0800 8 longwords
82 4000 8 longwords 0100 1 longword 1000 16 longwords
83 8000 16 longwords 0200 2 longwords 2000 32 longwords
84 C000 32 longwords 0400 4 longwords
85 Warning: many older 486 systems are broken and require setting 0x00A04800
86 8 longword cache alignment, 8 longword burst.
87 ToDo: Non-Intel setting could be better.
88*/
89
90#if defined(__alpha__) || defined(__ia64__)
91static int csr0 = 0x01A00000 | 0xE000;
92#elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
93static int csr0 = 0x01A00000 | 0x8000;
49345103 94#elif defined(CONFIG_SPARC) || defined(__hppa__)
1da177e4
LT		 95/* The UltraSparc PCI controllers will disconnect at every 64-byte
96 * crossing anyways so it makes no sense to tell Tulip to burst
97 * any more than that.
98 */
99static int csr0 = 0x01A00000 | 0x9000;
100#elif defined(__arm__) || defined(__sh__)
101static int csr0 = 0x01A00000 | 0x4800;
102#elif defined(__mips__)
103static int csr0 = 0x00200000 | 0x4000;
104#else
105#warning Processor architecture undefined!
106static int csr0 = 0x00A00000 | 0x4800;
107#endif
108
109/* Operational parameters that usually are not changed. */
110/* Time in jiffies before concluding the transmitter is hung. */
111#define TX_TIMEOUT (4*HZ)
112
113
114MODULE_AUTHOR("The Linux Kernel Team");
115MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
116MODULE_LICENSE("GPL");
117MODULE_VERSION(DRV_VERSION);
118module_param(tulip_debug, int, 0);
119module_param(max_interrupt_work, int, 0);
120module_param(rx_copybreak, int, 0);
121module_param(csr0, int, 0);
122module_param_array(options, int, NULL, 0);
123module_param_array(full_duplex, int, NULL, 0);
124
125#define PFX DRV_NAME ": "
126
127#ifdef TULIP_DEBUG
128int tulip_debug = TULIP_DEBUG;
129#else
130int tulip_debug = 1;
131#endif
132
0bb3cf72
FR		 133static void tulip_timer(unsigned long data)
134{
135 struct net_device *dev = (struct net_device *)data;
136 struct tulip_private *tp = netdev_priv(dev);
1da177e4 137
0bb3cf72
FR		 138 if (netif_running(dev))
139 schedule_work(&tp->media_work);
140}
1da177e4
LT		 141
142/*
143 * This table use during operation for capabilities and media timer.
144 *
145 * It is indexed via the values in 'enum chips'
146 */
147
148struct tulip_chip_table tulip_tbl[] = {
149 { }, /* placeholder for array, slot unused currently */
150 { }, /* placeholder for array, slot unused currently */
151
152 /* DC21140 */
153 { "Digital DS21140 Tulip", 128, 0x0001ebef,
0bb3cf72
FR		 154 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
155 tulip_media_task },
1da177e4
LT		 156
157 /* DC21142, DC21143 */
b892de0b 158 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
1da177e4 159 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
0bb3cf72 160 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
1da177e4
LT		 161
162 /* LC82C168 */
163 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
0bb3cf72 164 HAS_MII | HAS_PNICNWAY, pnic_timer, },
1da177e4
LT		 165
166 /* MX98713 */
167 { "Macronix 98713 PMAC", 128, 0x0001ebef,
0bb3cf72 168 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 169
170 /* MX98715 */
171 { "Macronix 98715 PMAC", 256, 0x0001ebef,
0bb3cf72 172 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 173
174 /* MX98725 */
175 { "Macronix 98725 PMAC", 256, 0x0001ebef,
0bb3cf72 176 HAS_MEDIA_TABLE, mxic_timer, },
1da177e4
LT		 177
178 /* AX88140 */
179 { "ASIX AX88140", 128, 0x0001fbff,
180 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
0bb3cf72 181 | IS_ASIX, tulip_timer, tulip_media_task },
1da177e4
LT		 182
183 /* PNIC2 */
184 { "Lite-On PNIC-II", 256, 0x0801fbff,
0bb3cf72 185 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
1da177e4
LT		 186
187 /* COMET */
188 { "ADMtek Comet", 256, 0x0001abef,
0bb3cf72 189 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
1da177e4
LT		 190
191 /* COMPEX9881 */
192 { "Compex 9881 PMAC", 128, 0x0001ebef,
0bb3cf72 193 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
1da177e4
LT		 194
195 /* I21145 */
196 { "Intel DS21145 Tulip", 128, 0x0801fbff,
197 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
0bb3cf72 198 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
1da177e4
LT		 199
200 /* DM910X */
201 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
202 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
0bb3cf72 203 tulip_timer, tulip_media_task },
1da177e4
LT		 204
205 /* RS7112 */
206 { "Conexant LANfinity", 256, 0x0001ebef,
0bb3cf72 207 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
1da177e4 208
1da177e4
LT		 209};
210
211
212static struct pci_device_id tulip_pci_tbl[] = {
213 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
214 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
215 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
216 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
217 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
218/* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
219 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
220 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
221 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
232 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
233 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
234 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
235 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
236 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
237 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
239 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
242 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
244 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4 246 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
9b25978e 247 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
1a449358 248 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
1da177e4
LT		 249 { } /* terminate list */
250};
251MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
252
253
254/* A full-duplex map for media types. */
255const char tulip_media_cap[32] =
256{0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
257
258static void tulip_tx_timeout(struct net_device *dev);
259static void tulip_init_ring(struct net_device *dev);
260static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev);
261static int tulip_open(struct net_device *dev);
262static int tulip_close(struct net_device *dev);
263static void tulip_up(struct net_device *dev);
264static void tulip_down(struct net_device *dev);
265static struct net_device_stats *tulip_get_stats(struct net_device *dev);
266static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
267static void set_rx_mode(struct net_device *dev);
268#ifdef CONFIG_NET_POLL_CONTROLLER
269static void poll_tulip(struct net_device *dev);
270#endif
271
272static void tulip_set_power_state (struct tulip_private *tp,
273 int sleep, int snooze)
274{
275 if (tp->flags & HAS_ACPI) {
276 u32 tmp, newtmp;
277 pci_read_config_dword (tp->pdev, CFDD, &tmp);
278 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
279 if (sleep)
280 newtmp |= CFDD_Sleep;
281 else if (snooze)
282 newtmp |= CFDD_Snooze;
283 if (tmp != newtmp)
284 pci_write_config_dword (tp->pdev, CFDD, newtmp);
285 }
286
287}
288
289
290static void tulip_up(struct net_device *dev)
291{
292 struct tulip_private *tp = netdev_priv(dev);
293 void __iomem *ioaddr = tp->base_addr;
294 int next_tick = 3*HZ;
b4482a4b 295 u32 reg;
1da177e4
LT		 296 int i;
297
bea3348e
SH		 298#ifdef CONFIG_TULIP_NAPI
299 napi_enable(&tp->napi);
300#endif
301
1da177e4
LT		 302 /* Wake the chip from sleep/snooze mode. */
303 tulip_set_power_state (tp, 0, 0);
304
305 /* On some chip revs we must set the MII/SYM port before the reset!? */
306 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
307 iowrite32(0x00040000, ioaddr + CSR6);
308
309 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
310 iowrite32(0x00000001, ioaddr + CSR0);
b4482a4b 311 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
1da177e4
LT		 312 udelay(100);
313
314 /* Deassert reset.
315 Wait the specified 50 PCI cycles after a reset by initializing
316 Tx and Rx queues and the address filter list. */
317 iowrite32(tp->csr0, ioaddr + CSR0);
b4482a4b 318 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
1da177e4
LT		 319 udelay(100);
320
321 if (tulip_debug > 1)
322 printk(KERN_DEBUG "%s: tulip_up(), irq==%d.\n", dev->name, dev->irq);
323
324 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
325 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
326 tp->cur_rx = tp->cur_tx = 0;
327 tp->dirty_rx = tp->dirty_tx = 0;
328
329 if (tp->flags & MC_HASH_ONLY) {
c559a5bc
AV		 330 u32 addr_low = le32_to_cpu(get_unaligned((__le32 *)dev->dev_addr));
331 u32 addr_high = le16_to_cpu(get_unaligned((__le16 *)(dev->dev_addr+4)));
1da177e4
LT		 332 if (tp->chip_id == AX88140) {
333 iowrite32(0, ioaddr + CSR13);
334 iowrite32(addr_low, ioaddr + CSR14);
335 iowrite32(1, ioaddr + CSR13);
336 iowrite32(addr_high, ioaddr + CSR14);
337 } else if (tp->flags & COMET_MAC_ADDR) {
338 iowrite32(addr_low, ioaddr + 0xA4);
339 iowrite32(addr_high, ioaddr + 0xA8);
340 iowrite32(0, ioaddr + 0xAC);
341 iowrite32(0, ioaddr + 0xB0);
342 }
343 } else {
344 /* This is set_rx_mode(), but without starting the transmitter. */
345 u16 *eaddrs = (u16 *)dev->dev_addr;
346 u16 *setup_frm = &tp->setup_frame[15*6];
347 dma_addr_t mapping;
348
349 /* 21140 bug: you must add the broadcast address. */
350 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
351 /* Fill the final entry of the table with our physical address. */
352 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
353 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
354 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
355
356 mapping = pci_map_single(tp->pdev, tp->setup_frame,
357 sizeof(tp->setup_frame),
358 PCI_DMA_TODEVICE);
359 tp->tx_buffers[tp->cur_tx].skb = NULL;
360 tp->tx_buffers[tp->cur_tx].mapping = mapping;
361
362 /* Put the setup frame on the Tx list. */
363 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
364 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
365 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
366
367 tp->cur_tx++;
368 }
369
370 tp->saved_if_port = dev->if_port;
371 if (dev->if_port == 0)
372 dev->if_port = tp->default_port;
373
374 /* Allow selecting a default media. */
375 i = 0;
376 if (tp->mtable == NULL)
377 goto media_picked;
378 if (dev->if_port) {
379 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
380 (dev->if_port == 12 ? 0 : dev->if_port);
381 for (i = 0; i < tp->mtable->leafcount; i++)
382 if (tp->mtable->mleaf[i].media == looking_for) {
383 printk(KERN_INFO "%s: Using user-specified media %s.\n",
384 dev->name, medianame[dev->if_port]);
385 goto media_picked;
386 }
387 }
388 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
389 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
390 for (i = 0; i < tp->mtable->leafcount; i++)
391 if (tp->mtable->mleaf[i].media == looking_for) {
392 printk(KERN_INFO "%s: Using EEPROM-set media %s.\n",
393 dev->name, medianame[looking_for]);
394 goto media_picked;
395 }
396 }
397 /* Start sensing first non-full-duplex media. */
398 for (i = tp->mtable->leafcount - 1;
399 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
400 ;
401media_picked:
402
403 tp->csr6 = 0;
404 tp->cur_index = i;
405 tp->nwayset = 0;
406
407 if (dev->if_port) {
408 if (tp->chip_id == DC21143 &&
409 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
410 /* We must reset the media CSRs when we force-select MII mode. */
411 iowrite32(0x0000, ioaddr + CSR13);
412 iowrite32(0x0000, ioaddr + CSR14);
413 iowrite32(0x0008, ioaddr + CSR15);
414 }
415 tulip_select_media(dev, 1);
416 } else if (tp->chip_id == DC21142) {
417 if (tp->mii_cnt) {
418 tulip_select_media(dev, 1);
419 if (tulip_debug > 1)
420 printk(KERN_INFO "%s: Using MII transceiver %d, status "
421 "%4.4x.\n",
422 dev->name, tp->phys[0], tulip_mdio_read(dev, tp->phys[0], 1));
423 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
424 tp->csr6 = csr6_mask_hdcap;
425 dev->if_port = 11;
426 iowrite32(0x0000, ioaddr + CSR13);
427 iowrite32(0x0000, ioaddr + CSR14);
428 } else
429 t21142_start_nway(dev);
430 } else if (tp->chip_id == PNIC2) {
431 /* for initial startup advertise 10/100 Full and Half */
432 tp->sym_advertise = 0x01E0;
433 /* enable autonegotiate end interrupt */
434 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
435 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
436 pnic2_start_nway(dev);
437 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
438 if (tp->mii_cnt) {
439 dev->if_port = 11;
440 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
441 iowrite32(0x0001, ioaddr + CSR15);
442 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
443 pnic_do_nway(dev);
444 else {
445 /* Start with 10mbps to do autonegotiation. */
446 iowrite32(0x32, ioaddr + CSR12);
447 tp->csr6 = 0x00420000;
448 iowrite32(0x0001B078, ioaddr + 0xB8);
449 iowrite32(0x0201B078, ioaddr + 0xB8);
450 next_tick = 1*HZ;
451 }
452 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881)
453 && ! tp->medialock) {
454 dev->if_port = 0;
455 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
456 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
457 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
458 /* Provided by BOLO, Macronix - 12/10/1998. */
459 dev->if_port = 0;
460 tp->csr6 = 0x01a80200;
461 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
462 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
463 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
464 /* Enable automatic Tx underrun recovery. */
465 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
466 dev->if_port = tp->mii_cnt ? 11 : 0;
467 tp->csr6 = 0x00040000;
468 } else if (tp->chip_id == AX88140) {
469 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
470 } else
471 tulip_select_media(dev, 1);
472
473 /* Start the chip's Tx to process setup frame. */
474 tulip_stop_rxtx(tp);
475 barrier();
476 udelay(5);
477 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
478
479 /* Enable interrupts by setting the interrupt mask. */
480 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
481 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
482 tulip_start_rxtx(tp);
483 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
484
485 if (tulip_debug > 2) {
486 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n",
487 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5),
488 ioread32(ioaddr + CSR6));
489 }
490
491 /* Set the timer to switch to check for link beat and perhaps switch
492 to an alternate media type. */
493 tp->timer.expires = RUN_AT(next_tick);
494 add_timer(&tp->timer);
495#ifdef CONFIG_TULIP_NAPI
496 init_timer(&tp->oom_timer);
497 tp->oom_timer.data = (unsigned long)dev;
498 tp->oom_timer.function = oom_timer;
499#endif
500}
501
502static int
503tulip_open(struct net_device *dev)
504{
505 int retval;
506
1fb9df5d 507 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev)))
1da177e4
LT		 508 return retval;
509
510 tulip_init_ring (dev);
511
512 tulip_up (dev);
513
514 netif_start_queue (dev);
515
516 return 0;
517}
518
519
520static void tulip_tx_timeout(struct net_device *dev)
521{
522 struct tulip_private *tp = netdev_priv(dev);
523 void __iomem *ioaddr = tp->base_addr;
524 unsigned long flags;
525
526 spin_lock_irqsave (&tp->lock, flags);
527
528 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
529 /* Do nothing -- the media monitor should handle this. */
530 if (tulip_debug > 1)
531 printk(KERN_WARNING "%s: Transmit timeout using MII device.\n",
532 dev->name);
533 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142
534 || tp->chip_id == MX98713 || tp->chip_id == COMPEX9881
ea8f400c 535 || tp->chip_id == DM910X) {
1da177e4
LT		 536 printk(KERN_WARNING "%s: 21140 transmit timed out, status %8.8x, "
537 "SIA %8.8x %8.8x %8.8x %8.8x, resetting...\n",
538 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
539 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14), ioread32(ioaddr + CSR15));
0bb3cf72
FR		 540 tp->timeout_recovery = 1;
541 schedule_work(&tp->media_work);
542 goto out_unlock;
1da177e4
LT		 543 } else if (tp->chip_id == PNIC2) {
544 printk(KERN_WARNING "%s: PNIC2 transmit timed out, status %8.8x, "
545 "CSR6/7 %8.8x / %8.8x CSR12 %8.8x, resetting...\n",
546 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6),
547 (int)ioread32(ioaddr + CSR7), (int)ioread32(ioaddr + CSR12));
548 } else {
549 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x, CSR12 "
550 "%8.8x, resetting...\n",
551 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
552 dev->if_port = 0;
553 }
554
555#if defined(way_too_many_messages)
556 if (tulip_debug > 3) {
557 int i;
558 for (i = 0; i < RX_RING_SIZE; i++) {
559 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
560 int j;
561 printk(KERN_DEBUG "%2d: %8.8x %8.8x %8.8x %8.8x "
562 "%2.2x %2.2x %2.2x.\n",
563 i, (unsigned int)tp->rx_ring[i].status,
564 (unsigned int)tp->rx_ring[i].length,
565 (unsigned int)tp->rx_ring[i].buffer1,
566 (unsigned int)tp->rx_ring[i].buffer2,
567 buf[0], buf[1], buf[2]);
568 for (j = 0; buf[j] != 0xee && j < 1600; j++)
569 if (j < 100) printk(" %2.2x", buf[j]);
570 printk(" j=%d.\n", j);
571 }
572 printk(KERN_DEBUG " Rx ring %8.8x: ", (int)tp->rx_ring);
573 for (i = 0; i < RX_RING_SIZE; i++)
574 printk(" %8.8x", (unsigned int)tp->rx_ring[i].status);
575 printk("\n" KERN_DEBUG " Tx ring %8.8x: ", (int)tp->tx_ring);
576 for (i = 0; i < TX_RING_SIZE; i++)
577 printk(" %8.8x", (unsigned int)tp->tx_ring[i].status);
578 printk("\n");
579 }
580#endif
581
0bb3cf72 582 tulip_tx_timeout_complete(tp, ioaddr);
1da177e4 583
0bb3cf72 584out_unlock:
1da177e4
LT		 585 spin_unlock_irqrestore (&tp->lock, flags);
586 dev->trans_start = jiffies;
587 netif_wake_queue (dev);
588}
589
590
591/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
592static void tulip_init_ring(struct net_device *dev)
593{
594 struct tulip_private *tp = netdev_priv(dev);
595 int i;
596
597 tp->susp_rx = 0;
598 tp->ttimer = 0;
599 tp->nir = 0;
600
601 for (i = 0; i < RX_RING_SIZE; i++) {
602 tp->rx_ring[i].status = 0x00000000;
603 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
604 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
605 tp->rx_buffers[i].skb = NULL;
606 tp->rx_buffers[i].mapping = 0;
607 }
608 /* Mark the last entry as wrapping the ring. */
609 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
610 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
611
612 for (i = 0; i < RX_RING_SIZE; i++) {
613 dma_addr_t mapping;
614
615 /* Note the receive buffer must be longword aligned.
616 dev_alloc_skb() provides 16 byte alignment. But do *not*
617 use skb_reserve() to align the IP header! */
618 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
619 tp->rx_buffers[i].skb = skb;
620 if (skb == NULL)
621 break;
689be439 622 mapping = pci_map_single(tp->pdev, skb->data,
1da177e4
LT		 623 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
624 tp->rx_buffers[i].mapping = mapping;
625 skb->dev = dev; /* Mark as being used by this device. */
626 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
627 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
628 }
629 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
630
631 /* The Tx buffer descriptor is filled in as needed, but we
632 do need to clear the ownership bit. */
633 for (i = 0; i < TX_RING_SIZE; i++) {
634 tp->tx_buffers[i].skb = NULL;
635 tp->tx_buffers[i].mapping = 0;
636 tp->tx_ring[i].status = 0x00000000;
637 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
638 }
639 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
640}
641
642static int
643tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
644{
645 struct tulip_private *tp = netdev_priv(dev);
646 int entry;
647 u32 flag;
648 dma_addr_t mapping;
649
650 spin_lock_irq(&tp->lock);
651
652 /* Calculate the next Tx descriptor entry. */
653 entry = tp->cur_tx % TX_RING_SIZE;
654
655 tp->tx_buffers[entry].skb = skb;
656 mapping = pci_map_single(tp->pdev, skb->data,
657 skb->len, PCI_DMA_TODEVICE);
658 tp->tx_buffers[entry].mapping = mapping;
659 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
660
661 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
662 flag = 0x60000000; /* No interrupt */
663 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
664 flag = 0xe0000000; /* Tx-done intr. */
665 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
666 flag = 0x60000000; /* No Tx-done intr. */
667 } else { /* Leave room for set_rx_mode() to fill entries. */
668 flag = 0xe0000000; /* Tx-done intr. */
669 netif_stop_queue(dev);
670 }
671 if (entry == TX_RING_SIZE-1)
672 flag = 0xe0000000 | DESC_RING_WRAP;
673
674 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
675 /* if we were using Transmit Automatic Polling, we would need a
676 * wmb() here. */
677 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
678 wmb();
679
680 tp->cur_tx++;
681
682 /* Trigger an immediate transmit demand. */
683 iowrite32(0, tp->base_addr + CSR1);
684
685 spin_unlock_irq(&tp->lock);
686
687 dev->trans_start = jiffies;
688
689 return 0;
690}
691
692static void tulip_clean_tx_ring(struct tulip_private *tp)
693{
694 unsigned int dirty_tx;
695
696 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
697 dirty_tx++) {
698 int entry = dirty_tx % TX_RING_SIZE;
699 int status = le32_to_cpu(tp->tx_ring[entry].status);
700
701 if (status < 0) {
702 tp->stats.tx_errors++; /* It wasn't Txed */
703 tp->tx_ring[entry].status = 0;
704 }
705
706 /* Check for Tx filter setup frames. */
707 if (tp->tx_buffers[entry].skb == NULL) {
708 /* test because dummy frames not mapped */
709 if (tp->tx_buffers[entry].mapping)
710 pci_unmap_single(tp->pdev,
711 tp->tx_buffers[entry].mapping,
712 sizeof(tp->setup_frame),
713 PCI_DMA_TODEVICE);
714 continue;
715 }
716
717 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
718 tp->tx_buffers[entry].skb->len,
719 PCI_DMA_TODEVICE);
720
721 /* Free the original skb. */
722 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
723 tp->tx_buffers[entry].skb = NULL;
724 tp->tx_buffers[entry].mapping = 0;
725 }
726}
727
728static void tulip_down (struct net_device *dev)
729{
730 struct tulip_private *tp = netdev_priv(dev);
731 void __iomem *ioaddr = tp->base_addr;
732 unsigned long flags;
733
0bb3cf72
FR		 734 flush_scheduled_work();
735
bea3348e
SH		 736#ifdef CONFIG_TULIP_NAPI
737 napi_disable(&tp->napi);
738#endif
739
1da177e4
LT		 740 del_timer_sync (&tp->timer);
741#ifdef CONFIG_TULIP_NAPI
742 del_timer_sync (&tp->oom_timer);
743#endif
744 spin_lock_irqsave (&tp->lock, flags);
745
746 /* Disable interrupts by clearing the interrupt mask. */
747 iowrite32 (0x00000000, ioaddr + CSR7);
748
749 /* Stop the Tx and Rx processes. */
750 tulip_stop_rxtx(tp);
751
752 /* prepare receive buffers */
753 tulip_refill_rx(dev);
754
755 /* release any unconsumed transmit buffers */
756 tulip_clean_tx_ring(tp);
757
758 if (ioread32 (ioaddr + CSR6) != 0xffffffff)
759 tp->stats.rx_missed_errors += ioread32 (ioaddr + CSR8) & 0xffff;
760
761 spin_unlock_irqrestore (&tp->lock, flags);
762
763 init_timer(&tp->timer);
764 tp->timer.data = (unsigned long)dev;
765 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
766
767 dev->if_port = tp->saved_if_port;
768
769 /* Leave the driver in snooze, not sleep, mode. */
770 tulip_set_power_state (tp, 0, 1);
771}
772
773
774static int tulip_close (struct net_device *dev)
775{
776 struct tulip_private *tp = netdev_priv(dev);
777 void __iomem *ioaddr = tp->base_addr;
778 int i;
779
780 netif_stop_queue (dev);
781
782 tulip_down (dev);
783
784 if (tulip_debug > 1)
785 printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
786 dev->name, ioread32 (ioaddr + CSR5));
787
788 free_irq (dev->irq, dev);
789
790 /* Free all the skbuffs in the Rx queue. */
791 for (i = 0; i < RX_RING_SIZE; i++) {
792 struct sk_buff *skb = tp->rx_buffers[i].skb;
793 dma_addr_t mapping = tp->rx_buffers[i].mapping;
794
795 tp->rx_buffers[i].skb = NULL;
796 tp->rx_buffers[i].mapping = 0;
797
798 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
799 tp->rx_ring[i].length = 0;
76285ee0
AV		 800 /* An invalid address. */
801 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
1da177e4
LT		 802 if (skb) {
803 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
804 PCI_DMA_FROMDEVICE);
805 dev_kfree_skb (skb);
806 }
807 }
808 for (i = 0; i < TX_RING_SIZE; i++) {
809 struct sk_buff *skb = tp->tx_buffers[i].skb;
810
811 if (skb != NULL) {
812 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
813 skb->len, PCI_DMA_TODEVICE);
814 dev_kfree_skb (skb);
815 }
816 tp->tx_buffers[i].skb = NULL;
817 tp->tx_buffers[i].mapping = 0;
818 }
819
820 return 0;
821}
822
823static struct net_device_stats *tulip_get_stats(struct net_device *dev)
824{
825 struct tulip_private *tp = netdev_priv(dev);
826 void __iomem *ioaddr = tp->base_addr;
827
828 if (netif_running(dev)) {
829 unsigned long flags;
830
831 spin_lock_irqsave (&tp->lock, flags);
832
833 tp->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
834
835 spin_unlock_irqrestore(&tp->lock, flags);
836 }
837
838 return &tp->stats;
839}
840
841
842static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
843{
844 struct tulip_private *np = netdev_priv(dev);
845 strcpy(info->driver, DRV_NAME);
846 strcpy(info->version, DRV_VERSION);
847 strcpy(info->bus_info, pci_name(np->pdev));
848}
849
7282d491 850static const struct ethtool_ops ops = {
1da177e4
LT		 851 .get_drvinfo = tulip_get_drvinfo
852};
853
854/* Provide ioctl() calls to examine the MII xcvr state. */
855static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
856{
857 struct tulip_private *tp = netdev_priv(dev);
858 void __iomem *ioaddr = tp->base_addr;
859 struct mii_ioctl_data *data = if_mii(rq);
860 const unsigned int phy_idx = 0;
861 int phy = tp->phys[phy_idx] & 0x1f;
862 unsigned int regnum = data->reg_num;
863
864 switch (cmd) {
865 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
866 if (tp->mii_cnt)
867 data->phy_id = phy;
868 else if (tp->flags & HAS_NWAY)
869 data->phy_id = 32;
870 else if (tp->chip_id == COMET)
871 data->phy_id = 1;
872 else
873 return -ENODEV;
874
875 case SIOCGMIIREG: /* Read MII PHY register. */
876 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
877 int csr12 = ioread32 (ioaddr + CSR12);
878 int csr14 = ioread32 (ioaddr + CSR14);
879 switch (regnum) {
880 case 0:
881 if (((csr14<<5) & 0x1000) ||
882 (dev->if_port == 5 && tp->nwayset))
883 data->val_out = 0x1000;
884 else
885 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
886 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
887 break;
888 case 1:
889 data->val_out =
890 0x1848 +
891 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
892 ((csr12&0x06) == 6 ? 0 : 4);
893 data->val_out |= 0x6048;
894 break;
895 case 4:
896 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
897 data->val_out =
898 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
899 ((csr14 >> 1) & 0x20) + 1;
900 data->val_out |= ((csr14 >> 9) & 0x03C0);
901 break;
902 case 5: data->val_out = tp->lpar; break;
903 default: data->val_out = 0; break;
904 }
905 } else {
906 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
907 }
908 return 0;
909
910 case SIOCSMIIREG: /* Write MII PHY register. */
911 if (!capable (CAP_NET_ADMIN))
912 return -EPERM;
913 if (regnum & ~0x1f)
914 return -EINVAL;
915 if (data->phy_id == phy) {
916 u16 value = data->val_in;
917 switch (regnum) {
918 case 0: /* Check for autonegotiation on or reset. */
919 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
920 if (tp->full_duplex_lock)
921 tp->full_duplex = (value & 0x0100) ? 1 : 0;
922 break;
923 case 4:
924 tp->advertising[phy_idx] =
925 tp->mii_advertise = data->val_in;
926 break;
927 }
928 }
929 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
930 u16 value = data->val_in;
931 if (regnum == 0) {
932 if ((value & 0x1200) == 0x1200) {
933 if (tp->chip_id == PNIC2) {
934 pnic2_start_nway (dev);
935 } else {
936 t21142_start_nway (dev);
937 }
938 }
939 } else if (regnum == 4)
940 tp->sym_advertise = value;
941 } else {
942 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
943 }
944 return 0;
945 default:
946 return -EOPNOTSUPP;
947 }
948
949 return -EOPNOTSUPP;
950}
951
952
953/* Set or clear the multicast filter for this adaptor.
954 Note that we only use exclusion around actually queueing the
955 new frame, not around filling tp->setup_frame. This is non-deterministic
956 when re-entered but still correct. */
957
958#undef set_bit_le
959#define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
960
961static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
962{
963 struct tulip_private *tp = netdev_priv(dev);
964 u16 hash_table[32];
965 struct dev_mc_list *mclist;
966 int i;
967 u16 *eaddrs;
968
969 memset(hash_table, 0, sizeof(hash_table));
970 set_bit_le(255, hash_table); /* Broadcast entry */
971 /* This should work on big-endian machines as well. */
972 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
973 i++, mclist = mclist->next) {
974 int index = ether_crc_le(ETH_ALEN, mclist->dmi_addr) & 0x1ff;
975
976 set_bit_le(index, hash_table);
977
978 }
979 for (i = 0; i < 32; i++) {
980 *setup_frm++ = hash_table[i];
981 *setup_frm++ = hash_table[i];
982 }
983 setup_frm = &tp->setup_frame[13*6];
984
985 /* Fill the final entry with our physical address. */
986 eaddrs = (u16 *)dev->dev_addr;
987 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
988 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
989 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
990}
991
992static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
993{
994 struct tulip_private *tp = netdev_priv(dev);
995 struct dev_mc_list *mclist;
996 int i;
997 u16 *eaddrs;
998
999 /* We have <= 14 addresses so we can use the wonderful
1000 16 address perfect filtering of the Tulip. */
1001 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
1002 i++, mclist = mclist->next) {
1003 eaddrs = (u16 *)mclist->dmi_addr;
1004 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1005 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1006 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1007 }
1008 /* Fill the unused entries with the broadcast address. */
1009 memset(setup_frm, 0xff, (15-i)*12);
1010 setup_frm = &tp->setup_frame[15*6];
1011
1012 /* Fill the final entry with our physical address. */
1013 eaddrs = (u16 *)dev->dev_addr;
1014 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1015 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1016 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1017}
1018
1019
1020static void set_rx_mode(struct net_device *dev)
1021{
1022 struct tulip_private *tp = netdev_priv(dev);
1023 void __iomem *ioaddr = tp->base_addr;
1024 int csr6;
1025
1026 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1027
1028 tp->csr6 &= ~0x00D5;
1029 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1030 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1031 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1da177e4
LT		 1032 } else if ((dev->mc_count > 1000) || (dev->flags & IFF_ALLMULTI)) {
1033 /* Too many to filter well -- accept all multicasts. */
1034 tp->csr6 |= AcceptAllMulticast;
1035 csr6 |= AcceptAllMulticast;
1036 } else if (tp->flags & MC_HASH_ONLY) {
1037 /* Some work-alikes have only a 64-entry hash filter table. */
1038 /* Should verify correctness on big-endian/__powerpc__ */
1039 struct dev_mc_list *mclist;
1040 int i;
1041 if (dev->mc_count > 64) { /* Arbitrary non-effective limit. */
1042 tp->csr6 |= AcceptAllMulticast;
1043 csr6 |= AcceptAllMulticast;
1044 } else {
1045 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1046 int filterbit;
1047 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1048 i++, mclist = mclist->next) {
1049 if (tp->flags & COMET_MAC_ADDR)
1050 filterbit = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1051 else
1052 filterbit = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1053 filterbit &= 0x3f;
1054 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1055 if (tulip_debug > 2) {
0795af57
JP		 1056 DECLARE_MAC_BUF(mac);
1057 printk(KERN_INFO "%s: Added filter for %s"
1058 " %8.8x bit %d.\n",
1059 dev->name, print_mac(mac, mclist->dmi_addr),
1060 ether_crc(ETH_ALEN, mclist->dmi_addr), filterbit);
1da177e4
LT		 1061 }
1062 }
1063 if (mc_filter[0] == tp->mc_filter[0] &&
1064 mc_filter[1] == tp->mc_filter[1])
1065 ; /* No change. */
1066 else if (tp->flags & IS_ASIX) {
1067 iowrite32(2, ioaddr + CSR13);
1068 iowrite32(mc_filter[0], ioaddr + CSR14);
1069 iowrite32(3, ioaddr + CSR13);
1070 iowrite32(mc_filter[1], ioaddr + CSR14);
1071 } else if (tp->flags & COMET_MAC_ADDR) {
1072 iowrite32(mc_filter[0], ioaddr + 0xAC);
1073 iowrite32(mc_filter[1], ioaddr + 0xB0);
1074 }
1075 tp->mc_filter[0] = mc_filter[0];
1076 tp->mc_filter[1] = mc_filter[1];
1077 }
1078 } else {
1079 unsigned long flags;
1080 u32 tx_flags = 0x08000000 | 192;
1081
1082 /* Note that only the low-address shortword of setup_frame is valid!
1083 The values are doubled for big-endian architectures. */
1084 if (dev->mc_count > 14) { /* Must use a multicast hash table. */
1085 build_setup_frame_hash(tp->setup_frame, dev);
1086 tx_flags = 0x08400000 | 192;
1087 } else {
1088 build_setup_frame_perfect(tp->setup_frame, dev);
1089 }
1090
1091 spin_lock_irqsave(&tp->lock, flags);
1092
1093 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1094 /* Same setup recently queued, we need not add it. */
1095 } else {
1096 unsigned int entry;
1097 int dummy = -1;
1098
1099 /* Now add this frame to the Tx list. */
1100
1101 entry = tp->cur_tx++ % TX_RING_SIZE;
1102
1103 if (entry != 0) {
ea8f400c
PC		 1104 /* Avoid a chip errata by prefixing a dummy entry. */
1105 tp->tx_buffers[entry].skb = NULL;
1106 tp->tx_buffers[entry].mapping = 0;
1107 tp->tx_ring[entry].length =
1108 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1109 tp->tx_ring[entry].buffer1 = 0;
1110 /* Must set DescOwned later to avoid race with chip */
1111 dummy = entry;
1112 entry = tp->cur_tx++ % TX_RING_SIZE;
1113
1da177e4
LT		 1114 }
1115
1116 tp->tx_buffers[entry].skb = NULL;
1117 tp->tx_buffers[entry].mapping =
1118 pci_map_single(tp->pdev, tp->setup_frame,
1119 sizeof(tp->setup_frame),
1120 PCI_DMA_TODEVICE);
1121 /* Put the setup frame on the Tx list. */
1122 if (entry == TX_RING_SIZE-1)
1123 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1124 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1125 tp->tx_ring[entry].buffer1 =
1126 cpu_to_le32(tp->tx_buffers[entry].mapping);
1127 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1128 if (dummy >= 0)
1129 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1130 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1131 netif_stop_queue(dev);
1132
1133 /* Trigger an immediate transmit demand. */
1134 iowrite32(0, ioaddr + CSR1);
1135 }
1136
1137 spin_unlock_irqrestore(&tp->lock, flags);
1138 }
1139
1140 iowrite32(csr6, ioaddr + CSR6);
1141}
1142
1143#ifdef CONFIG_TULIP_MWI
1144static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1145 struct net_device *dev)
1146{
1147 struct tulip_private *tp = netdev_priv(dev);
1148 u8 cache;
1149 u16 pci_command;
1150 u32 csr0;
1151
1152 if (tulip_debug > 3)
1153 printk(KERN_DEBUG "%s: tulip_mwi_config()\n", pci_name(pdev));
1154
1155 tp->csr0 = csr0 = 0;
1156
1157 /* if we have any cache line size at all, we can do MRM */
1158 csr0 |= MRM;
1159
1160 /* ...and barring hardware bugs, MWI */
1161 if (!(tp->chip_id == DC21143 && tp->revision == 65))
1162 csr0 |= MWI;
1163
1164 /* set or disable MWI in the standard PCI command bit.
1165 * Check for the case where mwi is desired but not available
1166 */
694625c0 1167 if (csr0 & MWI) pci_try_set_mwi(pdev);
1da177e4
LT		 1168 else pci_clear_mwi(pdev);
1169
1170 /* read result from hardware (in case bit refused to enable) */
1171 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1172 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1173 csr0 &= ~MWI;
1174
1175 /* if cache line size hardwired to zero, no MWI */
1176 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1177 if ((csr0 & MWI) && (cache == 0)) {
1178 csr0 &= ~MWI;
1179 pci_clear_mwi(pdev);
1180 }
1181
1182 /* assign per-cacheline-size cache alignment and
1183 * burst length values
1184 */
1185 switch (cache) {
1186 case 8:
1187 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1188 break;
1189 case 16:
1190 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1191 break;
1192 case 32:
1193 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1194 break;
1195 default:
1196 cache = 0;
1197 break;
1198 }
1199
1200 /* if we have a good cache line size, we by now have a good
1201 * csr0, so save it and exit
1202 */
1203 if (cache)
1204 goto out;
1205
1206 /* we don't have a good csr0 or cache line size, disable MWI */
1207 if (csr0 & MWI) {
1208 pci_clear_mwi(pdev);
1209 csr0 &= ~MWI;
1210 }
1211
1212 /* sane defaults for burst length and cache alignment
1213 * originally from de4x5 driver
1214 */
1215 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1216
1217out:
1218 tp->csr0 = csr0;
1219 if (tulip_debug > 2)
1220 printk(KERN_DEBUG "%s: MWI config cacheline=%d, csr0=%08x\n",
1221 pci_name(pdev), cache, csr0);
1222}
1223#endif
1224
1225/*
1226 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1227 * is the DM910X and the on chip ULi devices
1228 */
f3b197ac 1229
1da177e4
LT		 1230static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1231{
1232 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1233 return 1;
1da177e4
LT		 1234 return 0;
1235}
1236
1237static int __devinit tulip_init_one (struct pci_dev *pdev,
1238 const struct pci_device_id *ent)
1239{
1240 struct tulip_private *tp;
1241 /* See note below on the multiport cards. */
1242 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1243 static struct pci_device_id early_486_chipsets[] = {
1244 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1245 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1246 { },
1247 };
1248 static int last_irq;
1249 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1da177e4
LT		 1250 int i, irq;
1251 unsigned short sum;
1252 unsigned char *ee_data;
1253 struct net_device *dev;
1254 void __iomem *ioaddr;
1255 static int board_idx = -1;
1256 int chip_idx = ent->driver_data;
1257 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1258 unsigned int eeprom_missing = 0;
1259 unsigned int force_csr0 = 0;
0795af57 1260 DECLARE_MAC_BUF(mac);
1da177e4
LT		 1261
1262#ifndef MODULE
1263 static int did_version; /* Already printed version info. */
1264 if (tulip_debug > 0 && did_version++ == 0)
1265 printk (KERN_INFO "%s", version);
1266#endif
1267
1268 board_idx++;
1269
1270 /*
1271 * Lan media wire a tulip chip to a wan interface. Needs a very
1272 * different driver (lmc driver)
1273 */
1274
1275 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1276 printk (KERN_ERR PFX "skipping LMC card.\n");
1277 return -ENODEV;
1278 }
1279
1280 /*
1281 * Early DM9100's need software CRC and the DMFE driver
1282 */
1283
1284 if (pdev->vendor == 0x1282 && pdev->device == 0x9100)
1285 {
1da177e4 1286 /* Read Chip revision */
8ca7ee6b 1287 if (pdev->revision < 0x30)
1da177e4
LT		 1288 {
1289 printk(KERN_ERR PFX "skipping early DM9100 with Crc bug (use dmfe)\n");
1290 return -ENODEV;
1291 }
1292 }
1293
1294 /*
1295 * Looks for early PCI chipsets where people report hangs
1296 * without the workarounds being on.
1297 */
1298
1299 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
f3b197ac 1300 aligned. Aries might need this too. The Saturn errata are not
1da177e4
LT		 1301 pretty reading but thankfully it's an old 486 chipset.
1302
1303 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1304 Saturn.
1305 */
1306
1307 if (pci_dev_present(early_486_chipsets)) {
1308 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1309 force_csr0 = 1;
1310 }
1311
1312 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1313 if (chip_idx == AX88140) {
1314 if ((csr0 & 0x3f00) == 0)
1315 csr0 |= 0x2000;
1316 }
1317
1318 /* PNIC doesn't have MWI/MRL/MRM... */
1319 if (chip_idx == LC82C168)
1320 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1321
1322 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1323 if (tulip_uli_dm_quirk(pdev)) {
1324 csr0 &= ~0x01f100ff;
49345103 1325#if defined(CONFIG_SPARC)
1da177e4
LT		 1326 csr0 = (csr0 & ~0xff00) | 0xe000;
1327#endif
1328 }
1329 /*
1330 * And back to business
1331 */
1332
1333 i = pci_enable_device(pdev);
1334 if (i) {
1335 printk (KERN_ERR PFX
1336 "Cannot enable tulip board #%d, aborting\n",
1337 board_idx);
1338 return i;
1339 }
1340
1341 irq = pdev->irq;
1342
1343 /* alloc_etherdev ensures aligned and zeroed private structures */
1344 dev = alloc_etherdev (sizeof (*tp));
1345 if (!dev) {
1346 printk (KERN_ERR PFX "ether device alloc failed, aborting\n");
1347 return -ENOMEM;
1348 }
1349
1da177e4
LT		 1350 SET_NETDEV_DEV(dev, &pdev->dev);
1351 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
7c7459d1 1352 printk (KERN_ERR PFX "%s: I/O region (0x%llx@0x%llx) too small, "
1da177e4 1353 "aborting\n", pci_name(pdev),
7c7459d1
GKH		 1354 (unsigned long long)pci_resource_len (pdev, 0),
1355 (unsigned long long)pci_resource_start (pdev, 0));
1da177e4
LT		 1356 goto err_out_free_netdev;
1357 }
1358
1359 /* grab all resources from both PIO and MMIO regions, as we
1360 * don't want anyone else messing around with our hardware */
1361 if (pci_request_regions (pdev, "tulip"))
1362 goto err_out_free_netdev;
1363
7f2b1248
GG		 1364 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1365
1da177e4
LT		 1366 if (!ioaddr)
1367 goto err_out_free_res;
1368
1da177e4
LT		 1369 /*
1370 * initialize private data structure 'tp'
1371 * it is zeroed and aligned in alloc_etherdev
1372 */
1373 tp = netdev_priv(dev);
c4028958 1374 tp->dev = dev;
1da177e4
LT		 1375
1376 tp->rx_ring = pci_alloc_consistent(pdev,
1377 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1378 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1379 &tp->rx_ring_dma);
1380 if (!tp->rx_ring)
1381 goto err_out_mtable;
1382 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1383 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1384
1385 tp->chip_id = chip_idx;
1386 tp->flags = tulip_tbl[chip_idx].flags;
1387 tp->pdev = pdev;
1388 tp->base_addr = ioaddr;
44c10138 1389 tp->revision = pdev->revision;
1da177e4
LT		 1390 tp->csr0 = csr0;
1391 spin_lock_init(&tp->lock);
1392 spin_lock_init(&tp->mii_lock);
1393 init_timer(&tp->timer);
1394 tp->timer.data = (unsigned long)dev;
1395 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1396
c4028958 1397 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
0bb3cf72 1398
1da177e4
LT		 1399 dev->base_addr = (unsigned long)ioaddr;
1400
1401#ifdef CONFIG_TULIP_MWI
1402 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1403 tulip_mwi_config (pdev, dev);
1404#else
1405 /* MWI is broken for DC21143 rev 65... */
44c10138 1406 if (chip_idx == DC21143 && pdev->revision == 65)
1da177e4
LT		 1407 tp->csr0 &= ~MWI;
1408#endif
1409
1410 /* Stop the chip's Tx and Rx processes. */
1411 tulip_stop_rxtx(tp);
1412
1413 pci_set_master(pdev);
1414
1415#ifdef CONFIG_GSC
1416 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1417 switch (pdev->subsystem_device) {
1418 default:
1419 break;
1420 case 0x1061:
1421 case 0x1062:
1422 case 0x1063:
1423 case 0x1098:
1424 case 0x1099:
1425 case 0x10EE:
1426 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1427 chip_name = "GSC DS21140 Tulip";
1428 }
1429 }
1430#endif
1431
1432 /* Clear the missed-packet counter. */
1433 ioread32(ioaddr + CSR8);
1434
1435 /* The station address ROM is read byte serially. The register must
1436 be polled, waiting for the value to be read bit serially from the
1437 EEPROM.
1438 */
1439 ee_data = tp->eeprom;
1440 sum = 0;
1441 if (chip_idx == LC82C168) {
1442 for (i = 0; i < 3; i++) {
1443 int value, boguscnt = 100000;
1444 iowrite32(0x600 | i, ioaddr + 0x98);
1445 do
1446 value = ioread32(ioaddr + CSR9);
1447 while (value < 0 && --boguscnt > 0);
c559a5bc 1448 put_unaligned(cpu_to_le16(value), ((__le16*)dev->dev_addr) + i);
1da177e4
LT		 1449 sum += value & 0xffff;
1450 }
1451 } else if (chip_idx == COMET) {
1452 /* No need to read the EEPROM. */
c559a5bc
AV		 1453 put_unaligned(cpu_to_le32(ioread32(ioaddr + 0xA4)), (__le32 *)dev->dev_addr);
1454 put_unaligned(cpu_to_le16(ioread32(ioaddr + 0xA8)), (__le16 *)(dev->dev_addr + 4));
1da177e4
LT		 1455 for (i = 0; i < 6; i ++)
1456 sum += dev->dev_addr[i];
1457 } else {
1458 /* A serial EEPROM interface, we read now and sort it out later. */
1459 int sa_offset = 0;
1460 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1461
1462 for (i = 0; i < sizeof(tp->eeprom); i+=2) {
1463 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1464 ee_data[i] = data & 0xff;
1465 ee_data[i + 1] = data >> 8;
1466 }
1467
1468 /* DEC now has a specification (see Notes) but early board makers
1469 just put the address in the first EEPROM locations. */
1470 /* This does memcmp(ee_data, ee_data+16, 8) */
1471 for (i = 0; i < 8; i ++)
1472 if (ee_data[i] != ee_data[16+i])
1473 sa_offset = 20;
1474 if (chip_idx == CONEXANT) {
1475 /* Check that the tuple type and length is correct. */
1476 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1477 sa_offset = 0x19A;
1478 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1479 ee_data[2] == 0) {
1480 sa_offset = 2; /* Grrr, damn Matrox boards. */
1481 multiport_cnt = 4;
1482 }
1da177e4 1483#ifdef CONFIG_MIPS_COBALT
f3b197ac 1484 if ((pdev->bus->number == 0) &&
1da177e4
LT		 1485 ((PCI_SLOT(pdev->devfn) == 7) ||
1486 (PCI_SLOT(pdev->devfn) == 12))) {
1487 /* Cobalt MAC address in first EEPROM locations. */
1488 sa_offset = 0;
12755c16
RB		 1489 /* Ensure our media table fixup get's applied */
1490 memcpy(ee_data + 16, ee_data, 8);
1da177e4
LT		 1491 }
1492#endif
1493#ifdef CONFIG_GSC
1494 /* Check to see if we have a broken srom */
1495 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1496 /* pci_vendor_id and subsystem_id are swapped */
1497 ee_data[0] = ee_data[2];
1498 ee_data[1] = ee_data[3];
1499 ee_data[2] = 0x61;
1500 ee_data[3] = 0x10;
1501
1502 /* HSC-PCI boards need to be byte-swaped and shifted
1503 * up 1 word. This shift needs to happen at the end
1504 * of the MAC first because of the 2 byte overlap.
1505 */
1506 for (i = 4; i >= 0; i -= 2) {
1507 ee_data[17 + i + 3] = ee_data[17 + i];
1508 ee_data[16 + i + 5] = ee_data[16 + i];
1509 }
1510 }
1511#endif
1512
1513 for (i = 0; i < 6; i ++) {
1514 dev->dev_addr[i] = ee_data[i + sa_offset];
1515 sum += ee_data[i + sa_offset];
1516 }
1517 }
1518 /* Lite-On boards have the address byte-swapped. */
1519 if ((dev->dev_addr[0] == 0xA0 || dev->dev_addr[0] == 0xC0 || dev->dev_addr[0] == 0x02)
1520 && dev->dev_addr[1] == 0x00)
1521 for (i = 0; i < 6; i+=2) {
1522 char tmp = dev->dev_addr[i];
1523 dev->dev_addr[i] = dev->dev_addr[i+1];
1524 dev->dev_addr[i+1] = tmp;
1525 }
1526 /* On the Zynx 315 Etherarray and other multiport boards only the
1527 first Tulip has an EEPROM.
1528 On Sparc systems the mac address is held in the OBP property
1529 "local-mac-address".
1530 The addresses of the subsequent ports are derived from the first.
1531 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1532 that here as well. */
1533 if (sum == 0 || sum == 6*0xff) {
49345103 1534#if defined(CONFIG_SPARC)
d297c31f
DM		 1535 struct device_node *dp = pci_device_to_OF_node(pdev);
1536 const unsigned char *addr;
1537 int len;
1da177e4
LT		 1538#endif
1539 eeprom_missing = 1;
1540 for (i = 0; i < 5; i++)
1541 dev->dev_addr[i] = last_phys_addr[i];
1542 dev->dev_addr[i] = last_phys_addr[i] + 1;
49345103 1543#if defined(CONFIG_SPARC)
d297c31f
DM		 1544 addr = of_get_property(dp, "local-mac-address", &len);
1545 if (addr && len == 6)
1546 memcpy(dev->dev_addr, addr, 6);
1da177e4 1547#endif
b9c4c609 1548#if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1da177e4
LT		 1549 if (last_irq)
1550 irq = last_irq;
1551#endif
1552 }
1553
1554 for (i = 0; i < 6; i++)
1555 last_phys_addr[i] = dev->dev_addr[i];
1556 last_irq = irq;
1557 dev->irq = irq;
1558
1559 /* The lower four bits are the media type. */
1560 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1561 if (options[board_idx] & MEDIA_MASK)
1562 tp->default_port = options[board_idx] & MEDIA_MASK;
1563 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1564 tp->full_duplex = 1;
1565 if (mtu[board_idx] > 0)
1566 dev->mtu = mtu[board_idx];
1567 }
1568 if (dev->mem_start & MEDIA_MASK)
1569 tp->default_port = dev->mem_start & MEDIA_MASK;
1570 if (tp->default_port) {
1571 printk(KERN_INFO "tulip%d: Transceiver selection forced to %s.\n",
1572 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1573 tp->medialock = 1;
1574 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1575 tp->full_duplex = 1;
1576 }
1577 if (tp->full_duplex)
1578 tp->full_duplex_lock = 1;
1579
1580 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1581 u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };
1582 tp->mii_advertise = media2advert[tp->default_port - 9];
1583 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1584 }
1585
1586 if (tp->flags & HAS_MEDIA_TABLE) {
1587 sprintf(dev->name, "tulip%d", board_idx); /* hack */
1588 tulip_parse_eeprom(dev);
1589 strcpy(dev->name, "eth%d"); /* un-hack */
1590 }
1591
1592 if ((tp->flags & ALWAYS_CHECK_MII) ||
1593 (tp->mtable && tp->mtable->has_mii) ||
1594 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1595 if (tp->mtable && tp->mtable->has_mii) {
1596 for (i = 0; i < tp->mtable->leafcount; i++)
1597 if (tp->mtable->mleaf[i].media == 11) {
1598 tp->cur_index = i;
1599 tp->saved_if_port = dev->if_port;
1600 tulip_select_media(dev, 2);
1601 dev->if_port = tp->saved_if_port;
1602 break;
1603 }
1604 }
1605
1606 /* Find the connected MII xcvrs.
1607 Doing this in open() would allow detecting external xcvrs
1608 later, but takes much time. */
1609 tulip_find_mii (dev, board_idx);
1610 }
1611
1612 /* The Tulip-specific entries in the device structure. */
1613 dev->open = tulip_open;
1614 dev->hard_start_xmit = tulip_start_xmit;
1615 dev->tx_timeout = tulip_tx_timeout;
1616 dev->watchdog_timeo = TX_TIMEOUT;
1617#ifdef CONFIG_TULIP_NAPI
bea3348e 1618 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1da177e4
LT		 1619#endif
1620 dev->stop = tulip_close;
1621 dev->get_stats = tulip_get_stats;
1622 dev->do_ioctl = private_ioctl;
1623 dev->set_multicast_list = set_rx_mode;
1624#ifdef CONFIG_NET_POLL_CONTROLLER
1625 dev->poll_controller = &poll_tulip;
1626#endif
1627 SET_ETHTOOL_OPS(dev, &ops);
1628
1629 if (register_netdev(dev))
1630 goto err_out_free_ring;
1631
c69f4122
GG		 1632 printk(KERN_INFO "%s: %s rev %d at "
1633#ifdef CONFIG_TULIP_MMIO
1634 "MMIO"
1635#else
1636 "Port"
1637#endif
44c10138 1638 " %#llx,", dev->name, chip_name, pdev->revision,
c69f4122 1639 (unsigned long long) pci_resource_start(pdev, TULIP_BAR));
1da177e4
LT		 1640 pci_set_drvdata(pdev, dev);
1641
1642 if (eeprom_missing)
1643 printk(" EEPROM not present,");
0795af57 1644 printk(" %s", print_mac(mac, dev->dev_addr));
1da177e4
LT		 1645 printk(", IRQ %d.\n", irq);
1646
1647 if (tp->chip_id == PNIC2)
1648 tp->link_change = pnic2_lnk_change;
1649 else if (tp->flags & HAS_NWAY)
1650 tp->link_change = t21142_lnk_change;
1651 else if (tp->flags & HAS_PNICNWAY)
1652 tp->link_change = pnic_lnk_change;
1653
1654 /* Reset the xcvr interface and turn on heartbeat. */
1655 switch (chip_idx) {
1656 case DC21140:
1657 case DM910X:
1da177e4
LT		 1658 default:
1659 if (tp->mtable)
1660 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1661 break;
1662 case DC21142:
1663 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1664 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1665 iowrite32(0x0000, ioaddr + CSR13);
1666 iowrite32(0x0000, ioaddr + CSR14);
1667 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1668 } else
1669 t21142_start_nway(dev);
1670 break;
1671 case PNIC2:
1672 /* just do a reset for sanity sake */
1673 iowrite32(0x0000, ioaddr + CSR13);
1674 iowrite32(0x0000, ioaddr + CSR14);
1675 break;
1676 case LC82C168:
1677 if ( ! tp->mii_cnt) {
1678 tp->nway = 1;
1679 tp->nwayset = 0;
1680 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1681 iowrite32(0x30, ioaddr + CSR12);
1682 iowrite32(0x0001F078, ioaddr + CSR6);
1683 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1684 }
1685 break;
1686 case MX98713:
1687 case COMPEX9881:
1688 iowrite32(0x00000000, ioaddr + CSR6);
1689 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1690 iowrite32(0x00000001, ioaddr + CSR13);
1691 break;
1692 case MX98715:
1693 case MX98725:
1694 iowrite32(0x01a80000, ioaddr + CSR6);
1695 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1696 iowrite32(0x00001000, ioaddr + CSR12);
1697 break;
1698 case COMET:
1699 /* No initialization necessary. */
1700 break;
1701 }
1702
1703 /* put the chip in snooze mode until opened */
1704 tulip_set_power_state (tp, 0, 1);
1705
1706 return 0;
1707
1708err_out_free_ring:
1709 pci_free_consistent (pdev,
1710 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1711 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1712 tp->rx_ring, tp->rx_ring_dma);
1713
1714err_out_mtable:
b4558ea9 1715 kfree (tp->mtable);
1da177e4
LT		 1716 pci_iounmap(pdev, ioaddr);
1717
1718err_out_free_res:
1719 pci_release_regions (pdev);
1720
1721err_out_free_netdev:
1722 free_netdev (dev);
1723 return -ENODEV;
1724}
1725
1726
1727#ifdef CONFIG_PM
1728
1729static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1730{
1731 struct net_device *dev = pci_get_drvdata(pdev);
1732
1fe2cb32
AB		 1733 if (!dev)
1734 return -EINVAL;
1735
1736 if (netif_running(dev))
1737 tulip_down(dev);
1738
1739 netif_device_detach(dev);
1740 free_irq(dev->irq, dev);
1741
1742 pci_save_state(pdev);
1743 pci_disable_device(pdev);
1744 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1745
1da177e4
LT		 1746 return 0;
1747}
1748
1749
1750static int tulip_resume(struct pci_dev *pdev)
1751{
1752 struct net_device *dev = pci_get_drvdata(pdev);
1fe2cb32 1753 int retval;
1da177e4 1754
1fe2cb32
AB		 1755 if (!dev)
1756 return -EINVAL;
1757
1758 pci_set_power_state(pdev, PCI_D0);
1759 pci_restore_state(pdev);
1760
9f486ae1
VH		 1761 if ((retval = pci_enable_device(pdev))) {
1762 printk (KERN_ERR "tulip: pci_enable_device failed in resume\n");
1763 return retval;
1764 }
1fe2cb32 1765
1fb9df5d 1766 if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1fe2cb32
AB		 1767 printk (KERN_ERR "tulip: request_irq failed in resume\n");
1768 return retval;
1da177e4 1769 }
1fe2cb32
AB		 1770
1771 netif_device_attach(dev);
1772
1773 if (netif_running(dev))
1774 tulip_up(dev);
1775
1da177e4
LT		 1776 return 0;
1777}
1778
1779#endif /* CONFIG_PM */
1780
1781
1782static void __devexit tulip_remove_one (struct pci_dev *pdev)
1783{
1784 struct net_device *dev = pci_get_drvdata (pdev);
1785 struct tulip_private *tp;
1786
1787 if (!dev)
1788 return;
1789
1790 tp = netdev_priv(dev);
1791 unregister_netdev(dev);
1792 pci_free_consistent (pdev,
1793 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1794 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1795 tp->rx_ring, tp->rx_ring_dma);
b4558ea9 1796 kfree (tp->mtable);
1da177e4
LT		 1797 pci_iounmap(pdev, tp->base_addr);
1798 free_netdev (dev);
1799 pci_release_regions (pdev);
1800 pci_set_drvdata (pdev, NULL);
1801
1802 /* pci_power_off (pdev, -1); */
1803}
1804
1805#ifdef CONFIG_NET_POLL_CONTROLLER
1806/*
1807 * Polling 'interrupt' - used by things like netconsole to send skbs
1808 * without having to re-enable interrupts. It's not called while
1809 * the interrupt routine is executing.
1810 */
1811
1812static void poll_tulip (struct net_device *dev)
1813{
1814 /* disable_irq here is not very nice, but with the lockless
1815 interrupt handler we have no other choice. */
1816 disable_irq(dev->irq);
7d12e780 1817 tulip_interrupt (dev->irq, dev);
1da177e4
LT		 1818 enable_irq(dev->irq);
1819}
1820#endif
1821
1822static struct pci_driver tulip_driver = {
1823 .name = DRV_NAME,
1824 .id_table = tulip_pci_tbl,
1825 .probe = tulip_init_one,
1826 .remove = __devexit_p(tulip_remove_one),
1827#ifdef CONFIG_PM
1828 .suspend = tulip_suspend,
1829 .resume = tulip_resume,
1830#endif /* CONFIG_PM */
1831};
1832
1833
1834static int __init tulip_init (void)
1835{
1836#ifdef MODULE
1837 printk (KERN_INFO "%s", version);
1838#endif
1839
1840 /* copy module parms into globals */
1841 tulip_rx_copybreak = rx_copybreak;
1842 tulip_max_interrupt_work = max_interrupt_work;
1843
1844 /* probe for and init boards */
29917620 1845 return pci_register_driver(&tulip_driver);
1da177e4
LT		 1846}
1847
1848
1849static void __exit tulip_cleanup (void)
1850{
1851 pci_unregister_driver (&tulip_driver);
1852}
1853
1854
1855module_init(tulip_init);
1856module_exit(tulip_cleanup);
Linux kernel - Deliverables
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