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smsc75xx: don't call usbnet_resume if usbnet_suspend fails
[deliverable/linux.git] / drivers / net / usb / smsc75xx.c
CommitLineData
d0cad871
SG		 1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2010 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 *****************************************************************************/
20
21#include <linux/module.h>
22#include <linux/kmod.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/mii.h>
28#include <linux/usb.h>
899a391b
SG		 29#include <linux/bitrev.h>
30#include <linux/crc16.h>
d0cad871
SG		 31#include <linux/crc32.h>
32#include <linux/usb/usbnet.h>
5a0e3ad6 33#include <linux/slab.h>
d0cad871
SG		 34#include "smsc75xx.h"
35
36#define SMSC_CHIPNAME "smsc75xx"
37#define SMSC_DRIVER_VERSION "1.0.0"
38#define HS_USB_PKT_SIZE (512)
39#define FS_USB_PKT_SIZE (64)
40#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
41#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
42#define DEFAULT_BULK_IN_DELAY (0x00002000)
43#define MAX_SINGLE_PACKET_SIZE (9000)
44#define LAN75XX_EEPROM_MAGIC (0x7500)
45#define EEPROM_MAC_OFFSET (0x01)
46#define DEFAULT_TX_CSUM_ENABLE (true)
47#define DEFAULT_RX_CSUM_ENABLE (true)
48#define DEFAULT_TSO_ENABLE (true)
49#define SMSC75XX_INTERNAL_PHY_ID (1)
50#define SMSC75XX_TX_OVERHEAD (8)
51#define MAX_RX_FIFO_SIZE (20 * 1024)
52#define MAX_TX_FIFO_SIZE (12 * 1024)
53#define USB_VENDOR_ID_SMSC (0x0424)
54#define USB_PRODUCT_ID_LAN7500 (0x7500)
55#define USB_PRODUCT_ID_LAN7505 (0x7505)
ea1649de 56#define RXW_PADDING 2
f329ccdc 57#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
899a391b 58 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
d0cad871 59
b4cdea9c
SG		 60#define SUSPEND_SUSPEND0 (0x01)
61#define SUSPEND_SUSPEND1 (0x02)
62#define SUSPEND_SUSPEND2 (0x04)
63#define SUSPEND_SUSPEND3 (0x08)
b4cdea9c
SG		 64#define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
65 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
66
d0cad871
SG		 67#define check_warn(ret, fmt, args...) \
68 ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); })
69
70#define check_warn_return(ret, fmt, args...) \
71 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } })
72
73#define check_warn_goto_done(ret, fmt, args...) \
74 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } })
75
76struct smsc75xx_priv {
77 struct usbnet *dev;
78 u32 rfe_ctl;
6c636503 79 u32 wolopts;
d0cad871 80 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
d0cad871
SG		 81 struct mutex dataport_mutex;
82 spinlock_t rfe_ctl_lock;
83 struct work_struct set_multicast;
b4cdea9c 84 u8 suspend_flags;
d0cad871
SG		 85};
86
87struct usb_context {
88 struct usb_ctrlrequest req;
89 struct usbnet *dev;
90};
91
eb939922 92static bool turbo_mode = true;
d0cad871
SG		 93module_param(turbo_mode, bool, 0644);
94MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
95
47bbea41
ML		 96static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
97 u32 *data, int in_pm)
d0cad871 98{
2b2e41e3 99 u32 buf;
d0cad871 100 int ret;
47bbea41 101 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
d0cad871
SG		 102
103 BUG_ON(!dev);
104
47bbea41
ML		 105 if (!in_pm)
106 fn = usbnet_read_cmd;
107 else
108 fn = usbnet_read_cmd_nopm;
109
110 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
111 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
112 0, index, &buf, 4);
d0cad871 113 if (unlikely(ret < 0))
1e1d7412
JP		 114 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
115 index, ret);
d0cad871 116
2b2e41e3
ML		 117 le32_to_cpus(&buf);
118 *data = buf;
d0cad871
SG		 119
120 return ret;
121}
122
47bbea41
ML		 123static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
124 u32 data, int in_pm)
d0cad871 125{
2b2e41e3 126 u32 buf;
d0cad871 127 int ret;
47bbea41 128 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
d0cad871
SG		 129
130 BUG_ON(!dev);
131
47bbea41
ML		 132 if (!in_pm)
133 fn = usbnet_write_cmd;
134 else
135 fn = usbnet_write_cmd_nopm;
136
2b2e41e3
ML		 137 buf = data;
138 cpu_to_le32s(&buf);
d0cad871 139
47bbea41
ML		 140 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
141 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
142 0, index, &buf, 4);
d0cad871 143 if (unlikely(ret < 0))
1e1d7412
JP		 144 netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
145 index, ret);
d0cad871 146
d0cad871
SG		 147 return ret;
148}
149
47bbea41
ML		 150static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
151 u32 *data)
152{
153 return __smsc75xx_read_reg(dev, index, data, 1);
154}
155
156static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
157 u32 data)
158{
159 return __smsc75xx_write_reg(dev, index, data, 1);
160}
161
162static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
163 u32 *data)
164{
165 return __smsc75xx_read_reg(dev, index, data, 0);
166}
167
168static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
169 u32 data)
170{
171 return __smsc75xx_write_reg(dev, index, data, 0);
172}
173
d0cad871
SG		 174/* Loop until the read is completed with timeout
175 * called with phy_mutex held */
f329ccdc
SG		 176static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
177 int in_pm)
d0cad871
SG		 178{
179 unsigned long start_time = jiffies;
180 u32 val;
181 int ret;
182
183 do {
f329ccdc 184 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
1e1d7412 185 check_warn_return(ret, "Error reading MII_ACCESS\n");
d0cad871
SG		 186
187 if (!(val & MII_ACCESS_BUSY))
188 return 0;
189 } while (!time_after(jiffies, start_time + HZ));
190
191 return -EIO;
192}
193
f329ccdc
SG		 194static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
195 int in_pm)
d0cad871
SG		 196{
197 struct usbnet *dev = netdev_priv(netdev);
198 u32 val, addr;
199 int ret;
200
201 mutex_lock(&dev->phy_mutex);
202
203 /* confirm MII not busy */
f329ccdc 204 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 205 check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_read\n");
d0cad871
SG		 206
207 /* set the address, index & direction (read from PHY) */
208 phy_id &= dev->mii.phy_id_mask;
209 idx &= dev->mii.reg_num_mask;
210 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
211 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 212 | MII_ACCESS_READ | MII_ACCESS_BUSY;
f329ccdc 213 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
1e1d7412 214 check_warn_goto_done(ret, "Error writing MII_ACCESS\n");
d0cad871 215
f329ccdc 216 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 217 check_warn_goto_done(ret, "Timed out reading MII reg %02X\n", idx);
d0cad871 218
f329ccdc 219 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
1e1d7412 220 check_warn_goto_done(ret, "Error reading MII_DATA\n");
d0cad871
SG		 221
222 ret = (u16)(val & 0xFFFF);
223
224done:
225 mutex_unlock(&dev->phy_mutex);
226 return ret;
227}
228
f329ccdc
SG		 229static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
230 int idx, int regval, int in_pm)
d0cad871
SG		 231{
232 struct usbnet *dev = netdev_priv(netdev);
233 u32 val, addr;
234 int ret;
235
236 mutex_lock(&dev->phy_mutex);
237
238 /* confirm MII not busy */
f329ccdc 239 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 240 check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_write\n");
d0cad871
SG		 241
242 val = regval;
f329ccdc 243 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
1e1d7412 244 check_warn_goto_done(ret, "Error writing MII_DATA\n");
d0cad871
SG		 245
246 /* set the address, index & direction (write to PHY) */
247 phy_id &= dev->mii.phy_id_mask;
248 idx &= dev->mii.reg_num_mask;
249 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
250 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 251 | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
f329ccdc 252 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
1e1d7412 253 check_warn_goto_done(ret, "Error writing MII_ACCESS\n");
d0cad871 254
f329ccdc 255 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 256 check_warn_goto_done(ret, "Timed out writing MII reg %02X\n", idx);
d0cad871
SG		 257
258done:
259 mutex_unlock(&dev->phy_mutex);
260}
261
f329ccdc
SG		 262static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
263 int idx)
264{
265 return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
266}
267
268static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
269 int idx, int regval)
270{
271 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
272}
273
274static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
275{
276 return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
277}
278
279static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
280 int regval)
281{
282 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
283}
284
d0cad871
SG		 285static int smsc75xx_wait_eeprom(struct usbnet *dev)
286{
287 unsigned long start_time = jiffies;
288 u32 val;
289 int ret;
290
291 do {
292 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
1e1d7412 293 check_warn_return(ret, "Error reading E2P_CMD\n");
d0cad871
SG		 294
295 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
296 break;
297 udelay(40);
298 } while (!time_after(jiffies, start_time + HZ));
299
300 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
1e1d7412 301 netdev_warn(dev->net, "EEPROM read operation timeout\n");
d0cad871
SG		 302 return -EIO;
303 }
304
305 return 0;
306}
307
308static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
309{
310 unsigned long start_time = jiffies;
311 u32 val;
312 int ret;
313
314 do {
315 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
1e1d7412 316 check_warn_return(ret, "Error reading E2P_CMD\n");
d0cad871
SG		 317
318 if (!(val & E2P_CMD_BUSY))
319 return 0;
320
321 udelay(40);
322 } while (!time_after(jiffies, start_time + HZ));
323
1e1d7412 324 netdev_warn(dev->net, "EEPROM is busy\n");
d0cad871
SG		 325 return -EIO;
326}
327
328static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
329 u8 *data)
330{
331 u32 val;
332 int i, ret;
333
334 BUG_ON(!dev);
335 BUG_ON(!data);
336
337 ret = smsc75xx_eeprom_confirm_not_busy(dev);
338 if (ret)
339 return ret;
340
341 for (i = 0; i < length; i++) {
342 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
343 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
1e1d7412 344 check_warn_return(ret, "Error writing E2P_CMD\n");
d0cad871
SG		 345
346 ret = smsc75xx_wait_eeprom(dev);
347 if (ret < 0)
348 return ret;
349
350 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
1e1d7412 351 check_warn_return(ret, "Error reading E2P_DATA\n");
d0cad871
SG		 352
353 data[i] = val & 0xFF;
354 offset++;
355 }
356
357 return 0;
358}
359
360static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
361 u8 *data)
362{
363 u32 val;
364 int i, ret;
365
366 BUG_ON(!dev);
367 BUG_ON(!data);
368
369 ret = smsc75xx_eeprom_confirm_not_busy(dev);
370 if (ret)
371 return ret;
372
373 /* Issue write/erase enable command */
374 val = E2P_CMD_BUSY | E2P_CMD_EWEN;
375 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
1e1d7412 376 check_warn_return(ret, "Error writing E2P_CMD\n");
d0cad871
SG		 377
378 ret = smsc75xx_wait_eeprom(dev);
379 if (ret < 0)
380 return ret;
381
382 for (i = 0; i < length; i++) {
383
384 /* Fill data register */
385 val = data[i];
386 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
1e1d7412 387 check_warn_return(ret, "Error writing E2P_DATA\n");
d0cad871
SG		 388
389 /* Send "write" command */
390 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
391 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
1e1d7412 392 check_warn_return(ret, "Error writing E2P_CMD\n");
d0cad871
SG		 393
394 ret = smsc75xx_wait_eeprom(dev);
395 if (ret < 0)
396 return ret;
397
398 offset++;
399 }
400
401 return 0;
402}
403
404static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
405{
406 int i, ret;
407
408 for (i = 0; i < 100; i++) {
409 u32 dp_sel;
410 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
1e1d7412 411 check_warn_return(ret, "Error reading DP_SEL\n");
d0cad871
SG		 412
413 if (dp_sel & DP_SEL_DPRDY)
414 return 0;
415
416 udelay(40);
417 }
418
1e1d7412 419 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
d0cad871
SG		 420
421 return -EIO;
422}
423
424static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
425 u32 length, u32 *buf)
426{
427 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
428 u32 dp_sel;
429 int i, ret;
430
431 mutex_lock(&pdata->dataport_mutex);
432
433 ret = smsc75xx_dataport_wait_not_busy(dev);
1e1d7412 434 check_warn_goto_done(ret, "smsc75xx_dataport_write busy on entry\n");
d0cad871
SG		 435
436 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
1e1d7412 437 check_warn_goto_done(ret, "Error reading DP_SEL\n");
d0cad871
SG		 438
439 dp_sel &= ~DP_SEL_RSEL;
440 dp_sel |= ram_select;
441 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
1e1d7412 442 check_warn_goto_done(ret, "Error writing DP_SEL\n");
d0cad871
SG		 443
444 for (i = 0; i < length; i++) {
445 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
1e1d7412 446 check_warn_goto_done(ret, "Error writing DP_ADDR\n");
d0cad871
SG		 447
448 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
1e1d7412 449 check_warn_goto_done(ret, "Error writing DP_DATA\n");
d0cad871
SG		 450
451 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
1e1d7412 452 check_warn_goto_done(ret, "Error writing DP_CMD\n");
d0cad871
SG		 453
454 ret = smsc75xx_dataport_wait_not_busy(dev);
1e1d7412 455 check_warn_goto_done(ret, "smsc75xx_dataport_write timeout\n");
d0cad871
SG		 456 }
457
458done:
459 mutex_unlock(&pdata->dataport_mutex);
460 return ret;
461}
462
463/* returns hash bit number for given MAC address */
464static u32 smsc75xx_hash(char addr[ETH_ALEN])
465{
466 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
467}
468
469static void smsc75xx_deferred_multicast_write(struct work_struct *param)
470{
471 struct smsc75xx_priv *pdata =
472 container_of(param, struct smsc75xx_priv, set_multicast);
473 struct usbnet *dev = pdata->dev;
474 int ret;
475
1e1d7412
JP		 476 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
477 pdata->rfe_ctl);
d0cad871
SG		 478
479 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
480 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
481
482 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1e1d7412 483 check_warn(ret, "Error writing RFE_CRL\n");
d0cad871
SG		 484}
485
486static void smsc75xx_set_multicast(struct net_device *netdev)
487{
488 struct usbnet *dev = netdev_priv(netdev);
489 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
490 unsigned long flags;
491 int i;
492
493 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
494
495 pdata->rfe_ctl &=
496 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
497 pdata->rfe_ctl |= RFE_CTL_AB;
498
499 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
500 pdata->multicast_hash_table[i] = 0;
501
502 if (dev->net->flags & IFF_PROMISC) {
1e1d7412 503 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
d0cad871
SG		 504 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
505 } else if (dev->net->flags & IFF_ALLMULTI) {
1e1d7412 506 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
d0cad871
SG		 507 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
508 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 509 struct netdev_hw_addr *ha;
d0cad871 510
1e1d7412 511 netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
d0cad871
SG		 512
513 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
514
22bedad3
JP		 515 netdev_for_each_mc_addr(ha, netdev) {
516 u32 bitnum = smsc75xx_hash(ha->addr);
d0cad871
SG		 517 pdata->multicast_hash_table[bitnum / 32] |=
518 (1 << (bitnum % 32));
519 }
520 } else {
1e1d7412 521 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
d0cad871
SG		 522 pdata->rfe_ctl |= RFE_CTL_DPF;
523 }
524
525 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
526
527 /* defer register writes to a sleepable context */
528 schedule_work(&pdata->set_multicast);
529}
530
531static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
532 u16 lcladv, u16 rmtadv)
533{
534 u32 flow = 0, fct_flow = 0;
535 int ret;
536
537 if (duplex == DUPLEX_FULL) {
538 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
539
540 if (cap & FLOW_CTRL_TX) {
541 flow = (FLOW_TX_FCEN | 0xFFFF);
542 /* set fct_flow thresholds to 20% and 80% */
543 fct_flow = (8 << 8) | 32;
544 }
545
546 if (cap & FLOW_CTRL_RX)
547 flow |= FLOW_RX_FCEN;
548
1e1d7412
JP		 549 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
550 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
551 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
d0cad871 552 } else {
1e1d7412 553 netif_dbg(dev, link, dev->net, "half duplex\n");
d0cad871
SG		 554 }
555
556 ret = smsc75xx_write_reg(dev, FLOW, flow);
1e1d7412 557 check_warn_return(ret, "Error writing FLOW\n");
d0cad871
SG		 558
559 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
1e1d7412 560 check_warn_return(ret, "Error writing FCT_FLOW\n");
d0cad871
SG		 561
562 return 0;
563}
564
565static int smsc75xx_link_reset(struct usbnet *dev)
566{
567 struct mii_if_info *mii = &dev->mii;
8ae6daca 568 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
d0cad871
SG		 569 u16 lcladv, rmtadv;
570 int ret;
571
4f94a929 572 /* write to clear phy interrupt status */
7749622d
SG		 573 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
574 PHY_INT_SRC_CLEAR_ALL);
d0cad871
SG		 575
576 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
1e1d7412 577 check_warn_return(ret, "Error writing INT_STS\n");
d0cad871
SG		 578
579 mii_check_media(mii, 1, 1);
580 mii_ethtool_gset(&dev->mii, &ecmd);
581 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
582 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
583
1e1d7412
JP		 584 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
585 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
d0cad871
SG		 586
587 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
588}
589
590static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
591{
592 u32 intdata;
593
594 if (urb->actual_length != 4) {
1e1d7412
JP		 595 netdev_warn(dev->net, "unexpected urb length %d\n",
596 urb->actual_length);
d0cad871
SG		 597 return;
598 }
599
600 memcpy(&intdata, urb->transfer_buffer, 4);
601 le32_to_cpus(&intdata);
602
1e1d7412 603 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
d0cad871
SG		 604
605 if (intdata & INT_ENP_PHY_INT)
606 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
607 else
1e1d7412
JP		 608 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
609 intdata);
d0cad871
SG		 610}
611
d0cad871
SG		 612static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
613{
614 return MAX_EEPROM_SIZE;
615}
616
617static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
618 struct ethtool_eeprom *ee, u8 *data)
619{
620 struct usbnet *dev = netdev_priv(netdev);
621
622 ee->magic = LAN75XX_EEPROM_MAGIC;
623
624 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
625}
626
627static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
628 struct ethtool_eeprom *ee, u8 *data)
629{
630 struct usbnet *dev = netdev_priv(netdev);
631
632 if (ee->magic != LAN75XX_EEPROM_MAGIC) {
1e1d7412
JP		 633 netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
634 ee->magic);
d0cad871
SG		 635 return -EINVAL;
636 }
637
638 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
639}
640
6c636503
SG		 641static void smsc75xx_ethtool_get_wol(struct net_device *net,
642 struct ethtool_wolinfo *wolinfo)
643{
644 struct usbnet *dev = netdev_priv(net);
645 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
646
647 wolinfo->supported = SUPPORTED_WAKE;
648 wolinfo->wolopts = pdata->wolopts;
649}
650
651static int smsc75xx_ethtool_set_wol(struct net_device *net,
652 struct ethtool_wolinfo *wolinfo)
653{
654 struct usbnet *dev = netdev_priv(net);
655 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
351f33d9 656 int ret;
6c636503
SG		 657
658 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
351f33d9
SG		 659
660 ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
661 check_warn_return(ret, "device_set_wakeup_enable error %d\n", ret);
662
6c636503
SG		 663 return 0;
664}
665
d0cad871
SG		 666static const struct ethtool_ops smsc75xx_ethtool_ops = {
667 .get_link = usbnet_get_link,
668 .nway_reset = usbnet_nway_reset,
669 .get_drvinfo = usbnet_get_drvinfo,
670 .get_msglevel = usbnet_get_msglevel,
671 .set_msglevel = usbnet_set_msglevel,
672 .get_settings = usbnet_get_settings,
673 .set_settings = usbnet_set_settings,
674 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
675 .get_eeprom = smsc75xx_ethtool_get_eeprom,
676 .set_eeprom = smsc75xx_ethtool_set_eeprom,
6c636503
SG		 677 .get_wol = smsc75xx_ethtool_get_wol,
678 .set_wol = smsc75xx_ethtool_set_wol,
d0cad871
SG		 679};
680
681static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
682{
683 struct usbnet *dev = netdev_priv(netdev);
684
685 if (!netif_running(netdev))
686 return -EINVAL;
687
688 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
689}
690
691static void smsc75xx_init_mac_address(struct usbnet *dev)
692{
693 /* try reading mac address from EEPROM */
694 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
695 dev->net->dev_addr) == 0) {
696 if (is_valid_ether_addr(dev->net->dev_addr)) {
697 /* eeprom values are valid so use them */
698 netif_dbg(dev, ifup, dev->net,
1e1d7412 699 "MAC address read from EEPROM\n");
d0cad871
SG		 700 return;
701 }
702 }
703
704 /* no eeprom, or eeprom values are invalid. generate random MAC */
f2cedb63 705 eth_hw_addr_random(dev->net);
1e1d7412 706 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
d0cad871
SG		 707}
708
709static int smsc75xx_set_mac_address(struct usbnet *dev)
710{
711 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
712 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
713 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
714
715 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
1e1d7412 716 check_warn_return(ret, "Failed to write RX_ADDRH: %d\n", ret);
d0cad871
SG		 717
718 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
1e1d7412 719 check_warn_return(ret, "Failed to write RX_ADDRL: %d\n", ret);
d0cad871
SG		 720
721 addr_hi |= ADDR_FILTX_FB_VALID;
722 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
1e1d7412 723 check_warn_return(ret, "Failed to write ADDR_FILTX: %d\n", ret);
d0cad871
SG		 724
725 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
1e1d7412 726 check_warn_return(ret, "Failed to write ADDR_FILTX+4: %d\n", ret);
d0cad871
SG		 727
728 return 0;
729}
730
731static int smsc75xx_phy_initialize(struct usbnet *dev)
732{
b140504a 733 int bmcr, ret, timeout = 0;
d0cad871
SG		 734
735 /* Initialize MII structure */
736 dev->mii.dev = dev->net;
737 dev->mii.mdio_read = smsc75xx_mdio_read;
738 dev->mii.mdio_write = smsc75xx_mdio_write;
739 dev->mii.phy_id_mask = 0x1f;
740 dev->mii.reg_num_mask = 0x1f;
c0b92e4d 741 dev->mii.supports_gmii = 1;
d0cad871
SG		 742 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
743
744 /* reset phy and wait for reset to complete */
745 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
746
747 do {
748 msleep(10);
749 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
1e1d7412 750 check_warn_return(bmcr, "Error reading MII_BMCR\n");
d0cad871 751 timeout++;
8a1d59d7 752 } while ((bmcr & BMCR_RESET) && (timeout < 100));
d0cad871
SG		 753
754 if (timeout >= 100) {
1e1d7412 755 netdev_warn(dev->net, "timeout on PHY Reset\n");
d0cad871
SG		 756 return -EIO;
757 }
758
759 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
760 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
761 ADVERTISE_PAUSE_ASYM);
c0b92e4d
SG		 762 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
763 ADVERTISE_1000FULL);
d0cad871 764
b140504a
SG		 765 /* read and write to clear phy interrupt status */
766 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
1e1d7412 767 check_warn_return(ret, "Error reading PHY_INT_SRC\n");
b140504a 768 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
d0cad871
SG		 769
770 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
771 PHY_INT_MASK_DEFAULT);
772 mii_nway_restart(&dev->mii);
773
1e1d7412 774 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
d0cad871
SG		 775 return 0;
776}
777
778static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
779{
780 int ret = 0;
781 u32 buf;
782 bool rxenabled;
783
784 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
1e1d7412 785 check_warn_return(ret, "Failed to read MAC_RX: %d\n", ret);
d0cad871
SG		 786
787 rxenabled = ((buf & MAC_RX_RXEN) != 0);
788
789 if (rxenabled) {
790 buf &= ~MAC_RX_RXEN;
791 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1e1d7412 792 check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
d0cad871
SG		 793 }
794
795 /* add 4 to size for FCS */
796 buf &= ~MAC_RX_MAX_SIZE;
797 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
798
799 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1e1d7412 800 check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
d0cad871
SG		 801
802 if (rxenabled) {
803 buf |= MAC_RX_RXEN;
804 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1e1d7412 805 check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
d0cad871
SG		 806 }
807
808 return 0;
809}
810
811static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
812{
813 struct usbnet *dev = netdev_priv(netdev);
814
815 int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu);
1e1d7412 816 check_warn_return(ret, "Failed to set mac rx frame length\n");
d0cad871
SG		 817
818 return usbnet_change_mtu(netdev, new_mtu);
819}
820
78e47fe4 821/* Enable or disable Rx checksum offload engine */
c8f44aff
MM		 822static int smsc75xx_set_features(struct net_device *netdev,
823 netdev_features_t features)
78e47fe4
MM		 824{
825 struct usbnet *dev = netdev_priv(netdev);
826 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
827 unsigned long flags;
828 int ret;
829
830 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
831
832 if (features & NETIF_F_RXCSUM)
833 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
834 else
835 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
836
837 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
838 /* it's racing here! */
839
840 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1e1d7412 841 check_warn_return(ret, "Error writing RFE_CTL\n");
78e47fe4
MM		 842
843 return 0;
844}
845
47bbea41 846static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
8762cec8
SG		 847{
848 int timeout = 0;
849
850 do {
851 u32 buf;
47bbea41
ML		 852 int ret;
853
854 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
855
1e1d7412 856 check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
8762cec8
SG		 857
858 if (buf & PMT_CTL_DEV_RDY)
859 return 0;
860
861 msleep(10);
862 timeout++;
863 } while (timeout < 100);
864
1e1d7412 865 netdev_warn(dev->net, "timeout waiting for device ready\n");
8762cec8
SG		 866 return -EIO;
867}
868
d0cad871
SG		 869static int smsc75xx_reset(struct usbnet *dev)
870{
871 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
872 u32 buf;
873 int ret = 0, timeout;
874
1e1d7412 875 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
d0cad871 876
47bbea41 877 ret = smsc75xx_wait_ready(dev, 0);
1e1d7412 878 check_warn_return(ret, "device not ready in smsc75xx_reset\n");
8762cec8 879
d0cad871 880 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 881 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871
SG		 882
883 buf |= HW_CFG_LRST;
884
885 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1e1d7412 886 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
d0cad871
SG		 887
888 timeout = 0;
889 do {
890 msleep(10);
891 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 892 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871
SG		 893 timeout++;
894 } while ((buf & HW_CFG_LRST) && (timeout < 100));
895
896 if (timeout >= 100) {
1e1d7412 897 netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
d0cad871
SG		 898 return -EIO;
899 }
900
1e1d7412 901 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
d0cad871
SG		 902
903 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1e1d7412 904 check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
d0cad871
SG		 905
906 buf |= PMT_CTL_PHY_RST;
907
908 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
1e1d7412 909 check_warn_return(ret, "Failed to write PMT_CTL: %d\n", ret);
d0cad871
SG		 910
911 timeout = 0;
912 do {
913 msleep(10);
914 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1e1d7412 915 check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
d0cad871
SG		 916 timeout++;
917 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
918
919 if (timeout >= 100) {
1e1d7412 920 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
d0cad871
SG		 921 return -EIO;
922 }
923
1e1d7412 924 netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
d0cad871
SG		 925
926 smsc75xx_init_mac_address(dev);
927
928 ret = smsc75xx_set_mac_address(dev);
1e1d7412 929 check_warn_return(ret, "Failed to set mac address\n");
d0cad871 930
1e1d7412
JP		 931 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
932 dev->net->dev_addr);
d0cad871
SG		 933
934 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 935 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871 936
1e1d7412
JP		 937 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
938 buf);
d0cad871
SG		 939
940 buf |= HW_CFG_BIR;
941
942 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1e1d7412 943 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
d0cad871
SG		 944
945 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 946 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871 947
1e1d7412
JP		 948 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
949 buf);
d0cad871
SG		 950
951 if (!turbo_mode) {
952 buf = 0;
953 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
954 } else if (dev->udev->speed == USB_SPEED_HIGH) {
955 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
956 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
957 } else {
958 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
959 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
960 }
961
1e1d7412
JP		 962 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
963 (ulong)dev->rx_urb_size);
d0cad871
SG		 964
965 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
1e1d7412 966 check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret);
d0cad871
SG		 967
968 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
1e1d7412 969 check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret);
d0cad871
SG		 970
971 netif_dbg(dev, ifup, dev->net,
1e1d7412 972 "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
d0cad871
SG		 973
974 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
1e1d7412 975 check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret);
d0cad871
SG		 976
977 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
1e1d7412 978 check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret);
d0cad871
SG		 979
980 netif_dbg(dev, ifup, dev->net,
1e1d7412 981 "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
d0cad871
SG		 982
983 if (turbo_mode) {
984 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 985 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871 986
1e1d7412 987 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG		 988
989 buf |= (HW_CFG_MEF | HW_CFG_BCE);
990
991 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1e1d7412 992 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
d0cad871
SG		 993
994 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 995 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871 996
1e1d7412 997 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG		 998 }
999
1000 /* set FIFO sizes */
1001 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
1002 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
1e1d7412 1003 check_warn_return(ret, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
d0cad871 1004
1e1d7412 1005 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG		 1006
1007 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
1008 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
1e1d7412 1009 check_warn_return(ret, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
d0cad871 1010
1e1d7412 1011 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG		 1012
1013 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
1e1d7412 1014 check_warn_return(ret, "Failed to write INT_STS: %d\n", ret);
d0cad871
SG		 1015
1016 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
1e1d7412 1017 check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
d0cad871 1018
1e1d7412 1019 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
d0cad871 1020
97138a1c 1021 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
1e1d7412 1022 check_warn_return(ret, "Failed to read E2P_CMD: %d\n", ret);
d0cad871 1023
97138a1c
SG		 1024 /* only set default GPIO/LED settings if no EEPROM is detected */
1025 if (!(buf & E2P_CMD_LOADED)) {
1026 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
1e1d7412
JP		 1027 check_warn_return(ret, "Failed to read LED_GPIO_CFG: %d\n",
1028 ret);
d0cad871 1029
97138a1c
SG		 1030 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
1031 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
1032
1033 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
1e1d7412
JP		 1034 check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n",
1035 ret);
97138a1c 1036 }
d0cad871
SG		 1037
1038 ret = smsc75xx_write_reg(dev, FLOW, 0);
1e1d7412 1039 check_warn_return(ret, "Failed to write FLOW: %d\n", ret);
d0cad871
SG		 1040
1041 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
1e1d7412 1042 check_warn_return(ret, "Failed to write FCT_FLOW: %d\n", ret);
d0cad871
SG		 1043
1044 /* Don't need rfe_ctl_lock during initialisation */
1045 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
1e1d7412 1046 check_warn_return(ret, "Failed to read RFE_CTL: %d\n", ret);
d0cad871
SG		 1047
1048 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
1049
1050 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1e1d7412 1051 check_warn_return(ret, "Failed to write RFE_CTL: %d\n", ret);
d0cad871
SG		 1052
1053 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
1e1d7412 1054 check_warn_return(ret, "Failed to read RFE_CTL: %d\n", ret);
d0cad871 1055
1e1d7412
JP		 1056 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
1057 pdata->rfe_ctl);
d0cad871
SG		 1058
1059 /* Enable or disable checksum offload engines */
78e47fe4 1060 smsc75xx_set_features(dev->net, dev->net->features);
d0cad871
SG		 1061
1062 smsc75xx_set_multicast(dev->net);
1063
1064 ret = smsc75xx_phy_initialize(dev);
1e1d7412 1065 check_warn_return(ret, "Failed to initialize PHY: %d\n", ret);
d0cad871
SG		 1066
1067 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
1e1d7412 1068 check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret);
d0cad871
SG		 1069
1070 /* enable PHY interrupts */
1071 buf |= INT_ENP_PHY_INT;
1072
1073 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
1e1d7412 1074 check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret);
d0cad871 1075
2f3a081e
SG		 1076 /* allow mac to detect speed and duplex from phy */
1077 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
1e1d7412 1078 check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret);
2f3a081e
SG		 1079
1080 buf |= (MAC_CR_ADD | MAC_CR_ASD);
1081 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
1e1d7412 1082 check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
2f3a081e 1083
d0cad871 1084 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
1e1d7412 1085 check_warn_return(ret, "Failed to read MAC_TX: %d\n", ret);
d0cad871
SG		 1086
1087 buf |= MAC_TX_TXEN;
1088
1089 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
1e1d7412 1090 check_warn_return(ret, "Failed to write MAC_TX: %d\n", ret);
d0cad871 1091
1e1d7412 1092 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
d0cad871
SG		 1093
1094 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
1e1d7412 1095 check_warn_return(ret, "Failed to read FCT_TX_CTL: %d\n", ret);
d0cad871
SG		 1096
1097 buf |= FCT_TX_CTL_EN;
1098
1099 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
1e1d7412 1100 check_warn_return(ret, "Failed to write FCT_TX_CTL: %d\n", ret);
d0cad871 1101
1e1d7412 1102 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
d0cad871
SG		 1103
1104 ret = smsc75xx_set_rx_max_frame_length(dev, 1514);
1e1d7412 1105 check_warn_return(ret, "Failed to set max rx frame length\n");
d0cad871
SG		 1106
1107 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
1e1d7412 1108 check_warn_return(ret, "Failed to read MAC_RX: %d\n", ret);
d0cad871
SG		 1109
1110 buf |= MAC_RX_RXEN;
1111
1112 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1e1d7412 1113 check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
d0cad871 1114
1e1d7412 1115 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
d0cad871
SG		 1116
1117 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
1e1d7412 1118 check_warn_return(ret, "Failed to read FCT_RX_CTL: %d\n", ret);
d0cad871
SG		 1119
1120 buf |= FCT_RX_CTL_EN;
1121
1122 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
1e1d7412 1123 check_warn_return(ret, "Failed to write FCT_RX_CTL: %d\n", ret);
d0cad871 1124
1e1d7412 1125 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
d0cad871 1126
1e1d7412 1127 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
d0cad871
SG		 1128 return 0;
1129}
1130
1131static const struct net_device_ops smsc75xx_netdev_ops = {
1132 .ndo_open = usbnet_open,
1133 .ndo_stop = usbnet_stop,
1134 .ndo_start_xmit = usbnet_start_xmit,
1135 .ndo_tx_timeout = usbnet_tx_timeout,
1136 .ndo_change_mtu = smsc75xx_change_mtu,
1137 .ndo_set_mac_address = eth_mac_addr,
1138 .ndo_validate_addr = eth_validate_addr,
1139 .ndo_do_ioctl = smsc75xx_ioctl,
afc4b13d 1140 .ndo_set_rx_mode = smsc75xx_set_multicast,
78e47fe4 1141 .ndo_set_features = smsc75xx_set_features,
d0cad871
SG		 1142};
1143
1144static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
1145{
1146 struct smsc75xx_priv *pdata = NULL;
1147 int ret;
1148
1149 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1150
1151 ret = usbnet_get_endpoints(dev, intf);
1e1d7412 1152 check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret);
d0cad871
SG		 1153
1154 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
1155 GFP_KERNEL);
1156
1157 pdata = (struct smsc75xx_priv *)(dev->data[0]);
1158 if (!pdata) {
1e1d7412 1159 netdev_warn(dev->net, "Unable to allocate smsc75xx_priv\n");
d0cad871
SG		 1160 return -ENOMEM;
1161 }
1162
1163 pdata->dev = dev;
1164
1165 spin_lock_init(&pdata->rfe_ctl_lock);
1166 mutex_init(&pdata->dataport_mutex);
1167
1168 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
1169
78e47fe4
MM		 1170 if (DEFAULT_TX_CSUM_ENABLE) {
1171 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1172 if (DEFAULT_TSO_ENABLE)
1173 dev->net->features |= NETIF_F_SG |
1174 NETIF_F_TSO | NETIF_F_TSO6;
1175 }
1176 if (DEFAULT_RX_CSUM_ENABLE)
1177 dev->net->features |= NETIF_F_RXCSUM;
d0cad871 1178
78e47fe4
MM		 1179 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1180 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_RXCSUM;
d0cad871
SG		 1181
1182 /* Init all registers */
1183 ret = smsc75xx_reset(dev);
33763b79 1184 check_warn_return(ret, "smsc75xx_reset error %d\n", ret);
d0cad871
SG		 1185
1186 dev->net->netdev_ops = &smsc75xx_netdev_ops;
1187 dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
1188 dev->net->flags |= IFF_MULTICAST;
1189 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
a99ff7d0 1190 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
d0cad871
SG		 1191 return 0;
1192}
1193
1194static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1195{
1196 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1197 if (pdata) {
1e1d7412 1198 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
d0cad871
SG		 1199 kfree(pdata);
1200 pdata = NULL;
1201 dev->data[0] = 0;
1202 }
1203}
1204
899a391b
SG		 1205static u16 smsc_crc(const u8 *buffer, size_t len)
1206{
1207 return bitrev16(crc16(0xFFFF, buffer, len));
1208}
1209
1210static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
1211 u32 wuf_mask1)
1212{
1213 int cfg_base = WUF_CFGX + filter * 4;
1214 int mask_base = WUF_MASKX + filter * 16;
1215 int ret;
1216
1217 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
1e1d7412 1218 check_warn_return(ret, "Error writing WUF_CFGX\n");
899a391b
SG		 1219
1220 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
1e1d7412 1221 check_warn_return(ret, "Error writing WUF_MASKX\n");
899a391b
SG		 1222
1223 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
1e1d7412 1224 check_warn_return(ret, "Error writing WUF_MASKX\n");
899a391b
SG		 1225
1226 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
1e1d7412 1227 check_warn_return(ret, "Error writing WUF_MASKX\n");
899a391b
SG		 1228
1229 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
1e1d7412 1230 check_warn_return(ret, "Error writing WUF_MASKX\n");
899a391b
SG		 1231
1232 return 0;
1233}
1234
9deb2757
SG		 1235static int smsc75xx_enter_suspend0(struct usbnet *dev)
1236{
b4cdea9c 1237 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG		 1238 u32 val;
1239 int ret;
1240
1241 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1242 check_warn_return(ret, "Error reading PMT_CTL\n");
1243
1244 val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
1245 val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
1246
1247 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1248 check_warn_return(ret, "Error writing PMT_CTL\n");
1249
351f33d9 1250 pdata->suspend_flags |= SUSPEND_SUSPEND0;
b4cdea9c 1251
9deb2757
SG		 1252 return 0;
1253}
1254
f329ccdc
SG		 1255static int smsc75xx_enter_suspend1(struct usbnet *dev)
1256{
b4cdea9c 1257 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc
SG		 1258 u32 val;
1259 int ret;
1260
1261 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1262 check_warn_return(ret, "Error reading PMT_CTL\n");
1263
1264 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1265 val |= PMT_CTL_SUS_MODE_1;
1266
1267 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1268 check_warn_return(ret, "Error writing PMT_CTL\n");
1269
1270 /* clear wol status, enable energy detection */
1271 val &= ~PMT_CTL_WUPS;
1272 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1273
1274 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1275 check_warn_return(ret, "Error writing PMT_CTL\n");
1276
351f33d9 1277 pdata->suspend_flags |= SUSPEND_SUSPEND1;
b4cdea9c 1278
f329ccdc
SG		 1279 return 0;
1280}
1281
9deb2757
SG		 1282static int smsc75xx_enter_suspend2(struct usbnet *dev)
1283{
b4cdea9c 1284 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG		 1285 u32 val;
1286 int ret;
1287
1288 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1289 check_warn_return(ret, "Error reading PMT_CTL\n");
1290
1291 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1292 val |= PMT_CTL_SUS_MODE_2;
1293
1294 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1295 check_warn_return(ret, "Error writing PMT_CTL\n");
1296
b4cdea9c
SG		 1297 pdata->suspend_flags |= SUSPEND_SUSPEND2;
1298
1299 return 0;
1300}
1301
1302static int smsc75xx_enter_suspend3(struct usbnet *dev)
1303{
1304 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1305 u32 val;
1306 int ret;
1307
1308 ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
1309 check_warn_return(ret, "Error reading FCT_RX_CTL\n");
1310
1311 if (val & FCT_RX_CTL_RXUSED) {
1312 netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
1313 return -EBUSY;
1314 }
1315
1316 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1317 check_warn_return(ret, "Error reading PMT_CTL\n");
1318
1319 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1320 val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
1321
1322 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1323 check_warn_return(ret, "Error writing PMT_CTL\n");
1324
1325 /* clear wol status */
1326 val &= ~PMT_CTL_WUPS;
1327 val |= PMT_CTL_WUPS_WOL;
1328
1329 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1330 check_warn_return(ret, "Error writing PMT_CTL\n");
1331
351f33d9 1332 pdata->suspend_flags |= SUSPEND_SUSPEND3;
b4cdea9c 1333
9deb2757
SG		 1334 return 0;
1335}
1336
f329ccdc
SG		 1337static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
1338{
1339 struct mii_if_info *mii = &dev->mii;
1340 int ret;
1341
1342 netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
1343
1344 /* read to clear */
1345 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
1346 check_warn_return(ret, "Error reading PHY_INT_SRC\n");
1347
1348 /* enable interrupt source */
1349 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
1350 check_warn_return(ret, "Error reading PHY_INT_MASK\n");
1351
1352 ret |= mask;
1353
1354 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1355
1356 return 0;
1357}
1358
1359static int smsc75xx_link_ok_nopm(struct usbnet *dev)
1360{
1361 struct mii_if_info *mii = &dev->mii;
1362 int ret;
1363
1364 /* first, a dummy read, needed to latch some MII phys */
1365 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1366 check_warn_return(ret, "Error reading MII_BMSR\n");
1367
1368 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1369 check_warn_return(ret, "Error reading MII_BMSR\n");
1370
1371 return !!(ret & BMSR_LSTATUS);
1372}
1373
b4cdea9c
SG		 1374static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
1375{
1376 int ret;
1377
1378 if (!netif_running(dev->net)) {
1379 /* interface is ifconfig down so fully power down hw */
1380 netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
1381 return smsc75xx_enter_suspend2(dev);
1382 }
1383
1384 if (!link_up) {
1385 /* link is down so enter EDPD mode */
1386 netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
1387
1388 /* enable PHY wakeup events for if cable is attached */
1389 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1390 PHY_INT_MASK_ANEG_COMP);
1391 check_warn_return(ret, "error enabling PHY wakeup ints\n");
1392
1393 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1394 return smsc75xx_enter_suspend1(dev);
1395 }
1396
1397 /* enable PHY wakeup events so we remote wakeup if cable is pulled */
1398 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1399 PHY_INT_MASK_LINK_DOWN);
1400 check_warn_return(ret, "error enabling PHY wakeup ints\n");
1401
1402 netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
1403 return smsc75xx_enter_suspend3(dev);
1404}
1405
16c79a04
SG		 1406static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
1407{
1408 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1409 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc 1410 u32 val, link_up;
16c79a04 1411 int ret;
16c79a04 1412
16c79a04 1413 ret = usbnet_suspend(intf, message);
2305c54f 1414 check_warn_return(ret, "usbnet_suspend error\n");
16c79a04 1415
b4cdea9c
SG		 1416 if (pdata->suspend_flags) {
1417 netdev_warn(dev->net, "error during last resume\n");
1418 pdata->suspend_flags = 0;
1419 }
1420
f329ccdc
SG		 1421 /* determine if link is up using only _nopm functions */
1422 link_up = smsc75xx_link_ok_nopm(dev);
1423
b4cdea9c
SG		 1424 if (message.event == PM_EVENT_AUTO_SUSPEND) {
1425 ret = smsc75xx_autosuspend(dev, link_up);
1426 goto done;
1427 }
1428
1429 /* if we get this far we're not autosuspending */
f329ccdc
SG		 1430 /* if no wol options set, or if link is down and we're not waking on
1431 * PHY activity, enter lowest power SUSPEND2 mode
1432 */
1433 if (!(pdata->wolopts & SUPPORTED_WAKE) ||
1434 !(link_up || (pdata->wolopts & WAKE_PHY))) {
1e1d7412 1435 netdev_info(dev->net, "entering SUSPEND2 mode\n");
6c636503
SG		 1436
1437 /* disable energy detect (link up) & wake up events */
47bbea41 1438 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1439 check_warn_goto_done(ret, "Error reading WUCSR\n");
6c636503
SG		 1440
1441 val &= ~(WUCSR_MPEN | WUCSR_WUEN);
1442
47bbea41 1443 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1444 check_warn_goto_done(ret, "Error writing WUCSR\n");
6c636503 1445
47bbea41 1446 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
eacdd6c2 1447 check_warn_goto_done(ret, "Error reading PMT_CTL\n");
6c636503
SG		 1448
1449 val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
1450
47bbea41 1451 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
eacdd6c2 1452 check_warn_goto_done(ret, "Error writing PMT_CTL\n");
6c636503 1453
eacdd6c2
SG		 1454 ret = smsc75xx_enter_suspend2(dev);
1455 goto done;
6c636503
SG		 1456 }
1457
f329ccdc
SG		 1458 if (pdata->wolopts & WAKE_PHY) {
1459 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1460 (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
eacdd6c2 1461 check_warn_goto_done(ret, "error enabling PHY wakeup ints\n");
f329ccdc
SG		 1462
1463 /* if link is down then configure EDPD and enter SUSPEND1,
1464 * otherwise enter SUSPEND0 below
1465 */
1466 if (!link_up) {
1467 struct mii_if_info *mii = &dev->mii;
1468 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1469
1470 /* enable energy detect power-down mode */
1471 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1472 PHY_MODE_CTRL_STS);
eacdd6c2 1473 check_warn_goto_done(ret, "Error reading PHY_MODE_CTRL_STS\n");
f329ccdc
SG		 1474
1475 ret |= MODE_CTRL_STS_EDPWRDOWN;
1476
1477 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
1478 PHY_MODE_CTRL_STS, ret);
1479
1480 /* enter SUSPEND1 mode */
eacdd6c2
SG		 1481 ret = smsc75xx_enter_suspend1(dev);
1482 goto done;
f329ccdc
SG		 1483 }
1484 }
1485
899a391b
SG		 1486 if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
1487 int i, filter = 0;
1488
1489 /* disable all filters */
1490 for (i = 0; i < WUF_NUM; i++) {
47bbea41 1491 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
eacdd6c2 1492 check_warn_goto_done(ret, "Error writing WUF_CFGX\n");
899a391b
SG		 1493 }
1494
1495 if (pdata->wolopts & WAKE_MCAST) {
1496 const u8 mcast[] = {0x01, 0x00, 0x5E};
1e1d7412 1497 netdev_info(dev->net, "enabling multicast detection\n");
899a391b
SG		 1498
1499 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
1500 | smsc_crc(mcast, 3);
1501 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
eacdd6c2 1502 check_warn_goto_done(ret, "Error writing wakeup filter\n");
899a391b
SG		 1503 }
1504
1505 if (pdata->wolopts & WAKE_ARP) {
1506 const u8 arp[] = {0x08, 0x06};
1e1d7412 1507 netdev_info(dev->net, "enabling ARP detection\n");
899a391b
SG		 1508
1509 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
1510 | smsc_crc(arp, 2);
1511 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
eacdd6c2 1512 check_warn_goto_done(ret, "Error writing wakeup filter\n");
899a391b
SG		 1513 }
1514
1515 /* clear any pending pattern match packet status */
47bbea41 1516 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1517 check_warn_goto_done(ret, "Error reading WUCSR\n");
899a391b
SG		 1518
1519 val |= WUCSR_WUFR;
1520
47bbea41 1521 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1522 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b 1523
1e1d7412 1524 netdev_info(dev->net, "enabling packet match detection\n");
47bbea41 1525 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1526 check_warn_goto_done(ret, "Error reading WUCSR\n");
899a391b
SG		 1527
1528 val |= WUCSR_WUEN;
1529
47bbea41 1530 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1531 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b 1532 } else {
1e1d7412 1533 netdev_info(dev->net, "disabling packet match detection\n");
47bbea41 1534 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1535 check_warn_goto_done(ret, "Error reading WUCSR\n");
6c636503 1536
899a391b 1537 val &= ~WUCSR_WUEN;
16c79a04 1538
47bbea41 1539 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1540 check_warn_goto_done(ret, "Error writing WUCSR\n");
6c636503
SG		 1541 }
1542
899a391b 1543 /* disable magic, bcast & unicast wakeup sources */
47bbea41 1544 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1545 check_warn_goto_done(ret, "Error reading WUCSR\n");
6c636503 1546
899a391b
SG		 1547 val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
1548
47bbea41 1549 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1550 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b 1551
f329ccdc
SG		 1552 if (pdata->wolopts & WAKE_PHY) {
1553 netdev_info(dev->net, "enabling PHY wakeup\n");
1554
1555 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
eacdd6c2 1556 check_warn_goto_done(ret, "Error reading PMT_CTL\n");
f329ccdc
SG		 1557
1558 /* clear wol status, enable energy detection */
1559 val &= ~PMT_CTL_WUPS;
1560 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1561
1562 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
eacdd6c2 1563 check_warn_goto_done(ret, "Error writing PMT_CTL\n");
f329ccdc
SG		 1564 }
1565
6c636503 1566 if (pdata->wolopts & WAKE_MAGIC) {
1e1d7412 1567 netdev_info(dev->net, "enabling magic packet wakeup\n");
47bbea41 1568 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1569 check_warn_goto_done(ret, "Error reading WUCSR\n");
899a391b
SG		 1570
1571 /* clear any pending magic packet status */
1572 val |= WUCSR_MPR | WUCSR_MPEN;
1573
47bbea41 1574 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1575 check_warn_goto_done(ret, "Error writing WUCSR\n");
6c636503
SG		 1576 }
1577
899a391b 1578 if (pdata->wolopts & WAKE_BCAST) {
1e1d7412 1579 netdev_info(dev->net, "enabling broadcast detection\n");
47bbea41 1580 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1581 check_warn_goto_done(ret, "Error reading WUCSR\n");
6c636503 1582
899a391b 1583 val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
16c79a04 1584
47bbea41 1585 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1586 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b 1587 }
6c636503 1588
899a391b 1589 if (pdata->wolopts & WAKE_UCAST) {
1e1d7412 1590 netdev_info(dev->net, "enabling unicast detection\n");
47bbea41 1591 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1592 check_warn_goto_done(ret, "Error reading WUCSR\n");
899a391b
SG		 1593
1594 val |= WUCSR_WUFR | WUCSR_PFDA_EN;
6c636503 1595
47bbea41 1596 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1597 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b
SG		 1598 }
1599
1600 /* enable receiver to enable frame reception */
47bbea41 1601 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
eacdd6c2 1602 check_warn_goto_done(ret, "Failed to read MAC_RX: %d\n", ret);
6c636503
SG		 1603
1604 val |= MAC_RX_RXEN;
1605
47bbea41 1606 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
eacdd6c2 1607 check_warn_goto_done(ret, "Failed to write MAC_RX: %d\n", ret);
6c636503
SG		 1608
1609 /* some wol options are enabled, so enter SUSPEND0 */
1e1d7412 1610 netdev_info(dev->net, "entering SUSPEND0 mode\n");
eacdd6c2
SG		 1611 ret = smsc75xx_enter_suspend0(dev);
1612
1613done:
1614 if (ret)
1615 usbnet_resume(intf);
1616 return ret;
16c79a04
SG		 1617}
1618
1619static int smsc75xx_resume(struct usb_interface *intf)
1620{
1621 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1622 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
b4cdea9c 1623 u8 suspend_flags = pdata->suspend_flags;
16c79a04
SG		 1624 int ret;
1625 u32 val;
1626
b4cdea9c 1627 netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
16c79a04 1628
b4cdea9c
SG		 1629 /* do this first to ensure it's cleared even in error case */
1630 pdata->suspend_flags = 0;
1631
b4cdea9c 1632 if (suspend_flags & SUSPEND_ALLMODES) {
899a391b 1633 /* Disable wakeup sources */
47bbea41 1634 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1e1d7412 1635 check_warn_return(ret, "Error reading WUCSR\n");
16c79a04 1636
899a391b
SG		 1637 val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
1638 | WUCSR_BCST_EN);
16c79a04 1639
47bbea41 1640 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1e1d7412 1641 check_warn_return(ret, "Error writing WUCSR\n");
6c636503
SG		 1642
1643 /* clear wake-up status */
47bbea41 1644 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1e1d7412 1645 check_warn_return(ret, "Error reading PMT_CTL\n");
6c636503
SG		 1646
1647 val &= ~PMT_CTL_WOL_EN;
1648 val |= PMT_CTL_WUPS;
1649
47bbea41 1650 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1e1d7412 1651 check_warn_return(ret, "Error writing PMT_CTL\n");
b4cdea9c
SG		 1652 }
1653
1654 if (suspend_flags & SUSPEND_SUSPEND2) {
1e1d7412 1655 netdev_info(dev->net, "resuming from SUSPEND2\n");
6c636503 1656
47bbea41 1657 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1e1d7412 1658 check_warn_return(ret, "Error reading PMT_CTL\n");
6c636503
SG		 1659
1660 val |= PMT_CTL_PHY_PWRUP;
1661
47bbea41 1662 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1e1d7412 1663 check_warn_return(ret, "Error writing PMT_CTL\n");
6c636503 1664 }
16c79a04 1665
47bbea41 1666 ret = smsc75xx_wait_ready(dev, 1);
1e1d7412 1667 check_warn_return(ret, "device not ready in smsc75xx_resume\n");
16c79a04
SG		 1668
1669 return usbnet_resume(intf);
1670}
1671
78e47fe4
MM		 1672static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
1673 u32 rx_cmd_a, u32 rx_cmd_b)
d0cad871 1674{
78e47fe4
MM		 1675 if (!(dev->net->features & NETIF_F_RXCSUM) ||
1676 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
d0cad871
SG		 1677 skb->ip_summed = CHECKSUM_NONE;
1678 } else {
1679 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
1680 skb->ip_summed = CHECKSUM_COMPLETE;
1681 }
1682}
1683
1684static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
1685{
d0cad871
SG		 1686 while (skb->len > 0) {
1687 u32 rx_cmd_a, rx_cmd_b, align_count, size;
1688 struct sk_buff *ax_skb;
1689 unsigned char *packet;
1690
1691 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
1692 le32_to_cpus(&rx_cmd_a);
1693 skb_pull(skb, 4);
1694
1695 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
1696 le32_to_cpus(&rx_cmd_b);
ea1649de 1697 skb_pull(skb, 4 + RXW_PADDING);
d0cad871
SG		 1698
1699 packet = skb->data;
1700
1701 /* get the packet length */
ea1649de
NE		 1702 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
1703 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
d0cad871
SG		 1704
1705 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
1706 netif_dbg(dev, rx_err, dev->net,
1e1d7412 1707 "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
d0cad871
SG		 1708 dev->net->stats.rx_errors++;
1709 dev->net->stats.rx_dropped++;
1710
1711 if (rx_cmd_a & RX_CMD_A_FCS)
1712 dev->net->stats.rx_crc_errors++;
1713 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
1714 dev->net->stats.rx_frame_errors++;
1715 } else {
1716 /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
1717 if (unlikely(size > (ETH_FRAME_LEN + 12))) {
1718 netif_dbg(dev, rx_err, dev->net,
1e1d7412
JP		 1719 "size err rx_cmd_a=0x%08x\n",
1720 rx_cmd_a);
d0cad871
SG		 1721 return 0;
1722 }
1723
1724 /* last frame in this batch */
1725 if (skb->len == size) {
78e47fe4
MM		 1726 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
1727 rx_cmd_b);
d0cad871
SG		 1728
1729 skb_trim(skb, skb->len - 4); /* remove fcs */
1730 skb->truesize = size + sizeof(struct sk_buff);
1731
1732 return 1;
1733 }
1734
1735 ax_skb = skb_clone(skb, GFP_ATOMIC);
1736 if (unlikely(!ax_skb)) {
1e1d7412 1737 netdev_warn(dev->net, "Error allocating skb\n");
d0cad871
SG		 1738 return 0;
1739 }
1740
1741 ax_skb->len = size;
1742 ax_skb->data = packet;
1743 skb_set_tail_pointer(ax_skb, size);
1744
78e47fe4
MM		 1745 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
1746 rx_cmd_b);
d0cad871
SG		 1747
1748 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
1749 ax_skb->truesize = size + sizeof(struct sk_buff);
1750
1751 usbnet_skb_return(dev, ax_skb);
1752 }
1753
1754 skb_pull(skb, size);
1755
1756 /* padding bytes before the next frame starts */
1757 if (skb->len)
1758 skb_pull(skb, align_count);
1759 }
1760
1761 if (unlikely(skb->len < 0)) {
1e1d7412 1762 netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
d0cad871
SG		 1763 return 0;
1764 }
1765
1766 return 1;
1767}
1768
1769static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
1770 struct sk_buff *skb, gfp_t flags)
1771{
1772 u32 tx_cmd_a, tx_cmd_b;
1773
1774 skb_linearize(skb);
1775
1776 if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
1777 struct sk_buff *skb2 =
1778 skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
1779 dev_kfree_skb_any(skb);
1780 skb = skb2;
1781 if (!skb)
1782 return NULL;
1783 }
1784
1785 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
1786
1787 if (skb->ip_summed == CHECKSUM_PARTIAL)
1788 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
1789
1790 if (skb_is_gso(skb)) {
1791 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
1792 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
1793
1794 tx_cmd_a |= TX_CMD_A_LSO;
1795 } else {
1796 tx_cmd_b = 0;
1797 }
1798
1799 skb_push(skb, 4);
1800 cpu_to_le32s(&tx_cmd_b);
1801 memcpy(skb->data, &tx_cmd_b, 4);
1802
1803 skb_push(skb, 4);
1804 cpu_to_le32s(&tx_cmd_a);
1805 memcpy(skb->data, &tx_cmd_a, 4);
1806
1807 return skb;
1808}
1809
b4cdea9c
SG		 1810static int smsc75xx_manage_power(struct usbnet *dev, int on)
1811{
1812 dev->intf->needs_remote_wakeup = on;
1813 return 0;
1814}
1815
d0cad871
SG		 1816static const struct driver_info smsc75xx_info = {
1817 .description = "smsc75xx USB 2.0 Gigabit Ethernet",
1818 .bind = smsc75xx_bind,
1819 .unbind = smsc75xx_unbind,
1820 .link_reset = smsc75xx_link_reset,
1821 .reset = smsc75xx_reset,
1822 .rx_fixup = smsc75xx_rx_fixup,
1823 .tx_fixup = smsc75xx_tx_fixup,
1824 .status = smsc75xx_status,
b4cdea9c 1825 .manage_power = smsc75xx_manage_power,
7bdd305e 1826 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
d0cad871
SG		 1827};
1828
1829static const struct usb_device_id products[] = {
1830 {
1831 /* SMSC7500 USB Gigabit Ethernet Device */
1832 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
1833 .driver_info = (unsigned long) &smsc75xx_info,
1834 },
1835 {
1836 /* SMSC7500 USB Gigabit Ethernet Device */
1837 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
1838 .driver_info = (unsigned long) &smsc75xx_info,
1839 },
1840 { }, /* END */
1841};
1842MODULE_DEVICE_TABLE(usb, products);
1843
1844static struct usb_driver smsc75xx_driver = {
1845 .name = SMSC_CHIPNAME,
1846 .id_table = products,
1847 .probe = usbnet_probe,
16c79a04
SG		 1848 .suspend = smsc75xx_suspend,
1849 .resume = smsc75xx_resume,
1850 .reset_resume = smsc75xx_resume,
d0cad871 1851 .disconnect = usbnet_disconnect,
e1f12eb6 1852 .disable_hub_initiated_lpm = 1,
b4cdea9c 1853 .supports_autosuspend = 1,
d0cad871
SG		 1854};
1855
d632eb1b 1856module_usb_driver(smsc75xx_driver);
d0cad871
SG		 1857
1858MODULE_AUTHOR("Nancy Lin");
90b24cfb 1859MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
d0cad871
SG		 1860MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
1861MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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