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smsc75xx: fix error handling in suspend failure case
[deliverable/linux.git] / drivers / net / usb / smsc75xx.c
CommitLineData
d0cad871
SG		 1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2010 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 *****************************************************************************/
20
21#include <linux/module.h>
22#include <linux/kmod.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/mii.h>
28#include <linux/usb.h>
899a391b
SG		 29#include <linux/bitrev.h>
30#include <linux/crc16.h>
d0cad871
SG		 31#include <linux/crc32.h>
32#include <linux/usb/usbnet.h>
5a0e3ad6 33#include <linux/slab.h>
d0cad871
SG		 34#include "smsc75xx.h"
35
36#define SMSC_CHIPNAME "smsc75xx"
37#define SMSC_DRIVER_VERSION "1.0.0"
38#define HS_USB_PKT_SIZE (512)
39#define FS_USB_PKT_SIZE (64)
40#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
41#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
42#define DEFAULT_BULK_IN_DELAY (0x00002000)
43#define MAX_SINGLE_PACKET_SIZE (9000)
44#define LAN75XX_EEPROM_MAGIC (0x7500)
45#define EEPROM_MAC_OFFSET (0x01)
46#define DEFAULT_TX_CSUM_ENABLE (true)
47#define DEFAULT_RX_CSUM_ENABLE (true)
48#define DEFAULT_TSO_ENABLE (true)
49#define SMSC75XX_INTERNAL_PHY_ID (1)
50#define SMSC75XX_TX_OVERHEAD (8)
51#define MAX_RX_FIFO_SIZE (20 * 1024)
52#define MAX_TX_FIFO_SIZE (12 * 1024)
53#define USB_VENDOR_ID_SMSC (0x0424)
54#define USB_PRODUCT_ID_LAN7500 (0x7500)
55#define USB_PRODUCT_ID_LAN7505 (0x7505)
ea1649de 56#define RXW_PADDING 2
f329ccdc 57#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
899a391b 58 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
d0cad871
SG		 59
60#define check_warn(ret, fmt, args...) \
61 ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); })
62
63#define check_warn_return(ret, fmt, args...) \
64 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } })
65
66#define check_warn_goto_done(ret, fmt, args...) \
67 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } })
68
69struct smsc75xx_priv {
70 struct usbnet *dev;
71 u32 rfe_ctl;
6c636503 72 u32 wolopts;
d0cad871 73 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
d0cad871
SG		 74 struct mutex dataport_mutex;
75 spinlock_t rfe_ctl_lock;
76 struct work_struct set_multicast;
77};
78
79struct usb_context {
80 struct usb_ctrlrequest req;
81 struct usbnet *dev;
82};
83
eb939922 84static bool turbo_mode = true;
d0cad871
SG		 85module_param(turbo_mode, bool, 0644);
86MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
87
47bbea41
ML		 88static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
89 u32 *data, int in_pm)
d0cad871 90{
2b2e41e3 91 u32 buf;
d0cad871 92 int ret;
47bbea41 93 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
d0cad871
SG		 94
95 BUG_ON(!dev);
96
47bbea41
ML		 97 if (!in_pm)
98 fn = usbnet_read_cmd;
99 else
100 fn = usbnet_read_cmd_nopm;
101
102 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
103 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
104 0, index, &buf, 4);
d0cad871 105 if (unlikely(ret < 0))
1e1d7412
JP		 106 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
107 index, ret);
d0cad871 108
2b2e41e3
ML		 109 le32_to_cpus(&buf);
110 *data = buf;
d0cad871
SG		 111
112 return ret;
113}
114
47bbea41
ML		 115static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
116 u32 data, int in_pm)
d0cad871 117{
2b2e41e3 118 u32 buf;
d0cad871 119 int ret;
47bbea41 120 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
d0cad871
SG		 121
122 BUG_ON(!dev);
123
47bbea41
ML		 124 if (!in_pm)
125 fn = usbnet_write_cmd;
126 else
127 fn = usbnet_write_cmd_nopm;
128
2b2e41e3
ML		 129 buf = data;
130 cpu_to_le32s(&buf);
d0cad871 131
47bbea41
ML		 132 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
133 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
134 0, index, &buf, 4);
d0cad871 135 if (unlikely(ret < 0))
1e1d7412
JP		 136 netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
137 index, ret);
d0cad871 138
d0cad871
SG		 139 return ret;
140}
141
47bbea41
ML		 142static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
143 u32 *data)
144{
145 return __smsc75xx_read_reg(dev, index, data, 1);
146}
147
148static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
149 u32 data)
150{
151 return __smsc75xx_write_reg(dev, index, data, 1);
152}
153
154static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
155 u32 *data)
156{
157 return __smsc75xx_read_reg(dev, index, data, 0);
158}
159
160static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
161 u32 data)
162{
163 return __smsc75xx_write_reg(dev, index, data, 0);
164}
165
6c636503
SG		 166static int smsc75xx_set_feature(struct usbnet *dev, u32 feature)
167{
168 if (WARN_ON_ONCE(!dev))
169 return -EINVAL;
170
47bbea41
ML		 171 return usbnet_write_cmd_nopm(dev, USB_REQ_SET_FEATURE,
172 USB_DIR_OUT | USB_RECIP_DEVICE,
173 feature, 0, NULL, 0);
6c636503
SG		 174}
175
176static int smsc75xx_clear_feature(struct usbnet *dev, u32 feature)
177{
178 if (WARN_ON_ONCE(!dev))
179 return -EINVAL;
180
47bbea41
ML		 181 return usbnet_write_cmd_nopm(dev, USB_REQ_CLEAR_FEATURE,
182 USB_DIR_OUT | USB_RECIP_DEVICE,
183 feature, 0, NULL, 0);
6c636503
SG		 184}
185
d0cad871
SG		 186/* Loop until the read is completed with timeout
187 * called with phy_mutex held */
f329ccdc
SG		 188static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
189 int in_pm)
d0cad871
SG		 190{
191 unsigned long start_time = jiffies;
192 u32 val;
193 int ret;
194
195 do {
f329ccdc 196 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
1e1d7412 197 check_warn_return(ret, "Error reading MII_ACCESS\n");
d0cad871
SG		 198
199 if (!(val & MII_ACCESS_BUSY))
200 return 0;
201 } while (!time_after(jiffies, start_time + HZ));
202
203 return -EIO;
204}
205
f329ccdc
SG		 206static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
207 int in_pm)
d0cad871
SG		 208{
209 struct usbnet *dev = netdev_priv(netdev);
210 u32 val, addr;
211 int ret;
212
213 mutex_lock(&dev->phy_mutex);
214
215 /* confirm MII not busy */
f329ccdc 216 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 217 check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_read\n");
d0cad871
SG		 218
219 /* set the address, index & direction (read from PHY) */
220 phy_id &= dev->mii.phy_id_mask;
221 idx &= dev->mii.reg_num_mask;
222 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
223 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 224 | MII_ACCESS_READ | MII_ACCESS_BUSY;
f329ccdc 225 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
1e1d7412 226 check_warn_goto_done(ret, "Error writing MII_ACCESS\n");
d0cad871 227
f329ccdc 228 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 229 check_warn_goto_done(ret, "Timed out reading MII reg %02X\n", idx);
d0cad871 230
f329ccdc 231 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
1e1d7412 232 check_warn_goto_done(ret, "Error reading MII_DATA\n");
d0cad871
SG		 233
234 ret = (u16)(val & 0xFFFF);
235
236done:
237 mutex_unlock(&dev->phy_mutex);
238 return ret;
239}
240
f329ccdc
SG		 241static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
242 int idx, int regval, int in_pm)
d0cad871
SG		 243{
244 struct usbnet *dev = netdev_priv(netdev);
245 u32 val, addr;
246 int ret;
247
248 mutex_lock(&dev->phy_mutex);
249
250 /* confirm MII not busy */
f329ccdc 251 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 252 check_warn_goto_done(ret, "MII is busy in smsc75xx_mdio_write\n");
d0cad871
SG		 253
254 val = regval;
f329ccdc 255 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
1e1d7412 256 check_warn_goto_done(ret, "Error writing MII_DATA\n");
d0cad871
SG		 257
258 /* set the address, index & direction (write to PHY) */
259 phy_id &= dev->mii.phy_id_mask;
260 idx &= dev->mii.reg_num_mask;
261 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
262 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 263 | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
f329ccdc 264 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
1e1d7412 265 check_warn_goto_done(ret, "Error writing MII_ACCESS\n");
d0cad871 266
f329ccdc 267 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 268 check_warn_goto_done(ret, "Timed out writing MII reg %02X\n", idx);
d0cad871
SG		 269
270done:
271 mutex_unlock(&dev->phy_mutex);
272}
273
f329ccdc
SG		 274static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
275 int idx)
276{
277 return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
278}
279
280static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
281 int idx, int regval)
282{
283 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
284}
285
286static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
287{
288 return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
289}
290
291static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
292 int regval)
293{
294 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
295}
296
d0cad871
SG		 297static int smsc75xx_wait_eeprom(struct usbnet *dev)
298{
299 unsigned long start_time = jiffies;
300 u32 val;
301 int ret;
302
303 do {
304 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
1e1d7412 305 check_warn_return(ret, "Error reading E2P_CMD\n");
d0cad871
SG		 306
307 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
308 break;
309 udelay(40);
310 } while (!time_after(jiffies, start_time + HZ));
311
312 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
1e1d7412 313 netdev_warn(dev->net, "EEPROM read operation timeout\n");
d0cad871
SG		 314 return -EIO;
315 }
316
317 return 0;
318}
319
320static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
321{
322 unsigned long start_time = jiffies;
323 u32 val;
324 int ret;
325
326 do {
327 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
1e1d7412 328 check_warn_return(ret, "Error reading E2P_CMD\n");
d0cad871
SG		 329
330 if (!(val & E2P_CMD_BUSY))
331 return 0;
332
333 udelay(40);
334 } while (!time_after(jiffies, start_time + HZ));
335
1e1d7412 336 netdev_warn(dev->net, "EEPROM is busy\n");
d0cad871
SG		 337 return -EIO;
338}
339
340static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
341 u8 *data)
342{
343 u32 val;
344 int i, ret;
345
346 BUG_ON(!dev);
347 BUG_ON(!data);
348
349 ret = smsc75xx_eeprom_confirm_not_busy(dev);
350 if (ret)
351 return ret;
352
353 for (i = 0; i < length; i++) {
354 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
355 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
1e1d7412 356 check_warn_return(ret, "Error writing E2P_CMD\n");
d0cad871
SG		 357
358 ret = smsc75xx_wait_eeprom(dev);
359 if (ret < 0)
360 return ret;
361
362 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
1e1d7412 363 check_warn_return(ret, "Error reading E2P_DATA\n");
d0cad871
SG		 364
365 data[i] = val & 0xFF;
366 offset++;
367 }
368
369 return 0;
370}
371
372static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
373 u8 *data)
374{
375 u32 val;
376 int i, ret;
377
378 BUG_ON(!dev);
379 BUG_ON(!data);
380
381 ret = smsc75xx_eeprom_confirm_not_busy(dev);
382 if (ret)
383 return ret;
384
385 /* Issue write/erase enable command */
386 val = E2P_CMD_BUSY | E2P_CMD_EWEN;
387 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
1e1d7412 388 check_warn_return(ret, "Error writing E2P_CMD\n");
d0cad871
SG		 389
390 ret = smsc75xx_wait_eeprom(dev);
391 if (ret < 0)
392 return ret;
393
394 for (i = 0; i < length; i++) {
395
396 /* Fill data register */
397 val = data[i];
398 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
1e1d7412 399 check_warn_return(ret, "Error writing E2P_DATA\n");
d0cad871
SG		 400
401 /* Send "write" command */
402 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
403 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
1e1d7412 404 check_warn_return(ret, "Error writing E2P_CMD\n");
d0cad871
SG		 405
406 ret = smsc75xx_wait_eeprom(dev);
407 if (ret < 0)
408 return ret;
409
410 offset++;
411 }
412
413 return 0;
414}
415
416static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
417{
418 int i, ret;
419
420 for (i = 0; i < 100; i++) {
421 u32 dp_sel;
422 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
1e1d7412 423 check_warn_return(ret, "Error reading DP_SEL\n");
d0cad871
SG		 424
425 if (dp_sel & DP_SEL_DPRDY)
426 return 0;
427
428 udelay(40);
429 }
430
1e1d7412 431 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
d0cad871
SG		 432
433 return -EIO;
434}
435
436static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
437 u32 length, u32 *buf)
438{
439 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
440 u32 dp_sel;
441 int i, ret;
442
443 mutex_lock(&pdata->dataport_mutex);
444
445 ret = smsc75xx_dataport_wait_not_busy(dev);
1e1d7412 446 check_warn_goto_done(ret, "smsc75xx_dataport_write busy on entry\n");
d0cad871
SG		 447
448 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
1e1d7412 449 check_warn_goto_done(ret, "Error reading DP_SEL\n");
d0cad871
SG		 450
451 dp_sel &= ~DP_SEL_RSEL;
452 dp_sel |= ram_select;
453 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
1e1d7412 454 check_warn_goto_done(ret, "Error writing DP_SEL\n");
d0cad871
SG		 455
456 for (i = 0; i < length; i++) {
457 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
1e1d7412 458 check_warn_goto_done(ret, "Error writing DP_ADDR\n");
d0cad871
SG		 459
460 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
1e1d7412 461 check_warn_goto_done(ret, "Error writing DP_DATA\n");
d0cad871
SG		 462
463 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
1e1d7412 464 check_warn_goto_done(ret, "Error writing DP_CMD\n");
d0cad871
SG		 465
466 ret = smsc75xx_dataport_wait_not_busy(dev);
1e1d7412 467 check_warn_goto_done(ret, "smsc75xx_dataport_write timeout\n");
d0cad871
SG		 468 }
469
470done:
471 mutex_unlock(&pdata->dataport_mutex);
472 return ret;
473}
474
475/* returns hash bit number for given MAC address */
476static u32 smsc75xx_hash(char addr[ETH_ALEN])
477{
478 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
479}
480
481static void smsc75xx_deferred_multicast_write(struct work_struct *param)
482{
483 struct smsc75xx_priv *pdata =
484 container_of(param, struct smsc75xx_priv, set_multicast);
485 struct usbnet *dev = pdata->dev;
486 int ret;
487
1e1d7412
JP		 488 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
489 pdata->rfe_ctl);
d0cad871
SG		 490
491 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
492 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
493
494 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1e1d7412 495 check_warn(ret, "Error writing RFE_CRL\n");
d0cad871
SG		 496}
497
498static void smsc75xx_set_multicast(struct net_device *netdev)
499{
500 struct usbnet *dev = netdev_priv(netdev);
501 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
502 unsigned long flags;
503 int i;
504
505 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
506
507 pdata->rfe_ctl &=
508 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
509 pdata->rfe_ctl |= RFE_CTL_AB;
510
511 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
512 pdata->multicast_hash_table[i] = 0;
513
514 if (dev->net->flags & IFF_PROMISC) {
1e1d7412 515 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
d0cad871
SG		 516 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
517 } else if (dev->net->flags & IFF_ALLMULTI) {
1e1d7412 518 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
d0cad871
SG		 519 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
520 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 521 struct netdev_hw_addr *ha;
d0cad871 522
1e1d7412 523 netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
d0cad871
SG		 524
525 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
526
22bedad3
JP		 527 netdev_for_each_mc_addr(ha, netdev) {
528 u32 bitnum = smsc75xx_hash(ha->addr);
d0cad871
SG		 529 pdata->multicast_hash_table[bitnum / 32] |=
530 (1 << (bitnum % 32));
531 }
532 } else {
1e1d7412 533 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
d0cad871
SG		 534 pdata->rfe_ctl |= RFE_CTL_DPF;
535 }
536
537 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
538
539 /* defer register writes to a sleepable context */
540 schedule_work(&pdata->set_multicast);
541}
542
543static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
544 u16 lcladv, u16 rmtadv)
545{
546 u32 flow = 0, fct_flow = 0;
547 int ret;
548
549 if (duplex == DUPLEX_FULL) {
550 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
551
552 if (cap & FLOW_CTRL_TX) {
553 flow = (FLOW_TX_FCEN | 0xFFFF);
554 /* set fct_flow thresholds to 20% and 80% */
555 fct_flow = (8 << 8) | 32;
556 }
557
558 if (cap & FLOW_CTRL_RX)
559 flow |= FLOW_RX_FCEN;
560
1e1d7412
JP		 561 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
562 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
563 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
d0cad871 564 } else {
1e1d7412 565 netif_dbg(dev, link, dev->net, "half duplex\n");
d0cad871
SG		 566 }
567
568 ret = smsc75xx_write_reg(dev, FLOW, flow);
1e1d7412 569 check_warn_return(ret, "Error writing FLOW\n");
d0cad871
SG		 570
571 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
1e1d7412 572 check_warn_return(ret, "Error writing FCT_FLOW\n");
d0cad871
SG		 573
574 return 0;
575}
576
577static int smsc75xx_link_reset(struct usbnet *dev)
578{
579 struct mii_if_info *mii = &dev->mii;
8ae6daca 580 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
d0cad871
SG		 581 u16 lcladv, rmtadv;
582 int ret;
583
4f94a929 584 /* write to clear phy interrupt status */
7749622d
SG		 585 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
586 PHY_INT_SRC_CLEAR_ALL);
d0cad871
SG		 587
588 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
1e1d7412 589 check_warn_return(ret, "Error writing INT_STS\n");
d0cad871
SG		 590
591 mii_check_media(mii, 1, 1);
592 mii_ethtool_gset(&dev->mii, &ecmd);
593 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
594 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
595
1e1d7412
JP		 596 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
597 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
d0cad871
SG		 598
599 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
600}
601
602static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
603{
604 u32 intdata;
605
606 if (urb->actual_length != 4) {
1e1d7412
JP		 607 netdev_warn(dev->net, "unexpected urb length %d\n",
608 urb->actual_length);
d0cad871
SG		 609 return;
610 }
611
612 memcpy(&intdata, urb->transfer_buffer, 4);
613 le32_to_cpus(&intdata);
614
1e1d7412 615 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
d0cad871
SG		 616
617 if (intdata & INT_ENP_PHY_INT)
618 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
619 else
1e1d7412
JP		 620 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
621 intdata);
d0cad871
SG		 622}
623
d0cad871
SG		 624static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
625{
626 return MAX_EEPROM_SIZE;
627}
628
629static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
630 struct ethtool_eeprom *ee, u8 *data)
631{
632 struct usbnet *dev = netdev_priv(netdev);
633
634 ee->magic = LAN75XX_EEPROM_MAGIC;
635
636 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
637}
638
639static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
640 struct ethtool_eeprom *ee, u8 *data)
641{
642 struct usbnet *dev = netdev_priv(netdev);
643
644 if (ee->magic != LAN75XX_EEPROM_MAGIC) {
1e1d7412
JP		 645 netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
646 ee->magic);
d0cad871
SG		 647 return -EINVAL;
648 }
649
650 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
651}
652
6c636503
SG		 653static void smsc75xx_ethtool_get_wol(struct net_device *net,
654 struct ethtool_wolinfo *wolinfo)
655{
656 struct usbnet *dev = netdev_priv(net);
657 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
658
659 wolinfo->supported = SUPPORTED_WAKE;
660 wolinfo->wolopts = pdata->wolopts;
661}
662
663static int smsc75xx_ethtool_set_wol(struct net_device *net,
664 struct ethtool_wolinfo *wolinfo)
665{
666 struct usbnet *dev = netdev_priv(net);
667 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
668
669 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
670 return 0;
671}
672
d0cad871
SG		 673static const struct ethtool_ops smsc75xx_ethtool_ops = {
674 .get_link = usbnet_get_link,
675 .nway_reset = usbnet_nway_reset,
676 .get_drvinfo = usbnet_get_drvinfo,
677 .get_msglevel = usbnet_get_msglevel,
678 .set_msglevel = usbnet_set_msglevel,
679 .get_settings = usbnet_get_settings,
680 .set_settings = usbnet_set_settings,
681 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
682 .get_eeprom = smsc75xx_ethtool_get_eeprom,
683 .set_eeprom = smsc75xx_ethtool_set_eeprom,
6c636503
SG		 684 .get_wol = smsc75xx_ethtool_get_wol,
685 .set_wol = smsc75xx_ethtool_set_wol,
d0cad871
SG		 686};
687
688static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
689{
690 struct usbnet *dev = netdev_priv(netdev);
691
692 if (!netif_running(netdev))
693 return -EINVAL;
694
695 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
696}
697
698static void smsc75xx_init_mac_address(struct usbnet *dev)
699{
700 /* try reading mac address from EEPROM */
701 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
702 dev->net->dev_addr) == 0) {
703 if (is_valid_ether_addr(dev->net->dev_addr)) {
704 /* eeprom values are valid so use them */
705 netif_dbg(dev, ifup, dev->net,
1e1d7412 706 "MAC address read from EEPROM\n");
d0cad871
SG		 707 return;
708 }
709 }
710
711 /* no eeprom, or eeprom values are invalid. generate random MAC */
f2cedb63 712 eth_hw_addr_random(dev->net);
1e1d7412 713 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
d0cad871
SG		 714}
715
716static int smsc75xx_set_mac_address(struct usbnet *dev)
717{
718 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
719 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
720 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
721
722 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
1e1d7412 723 check_warn_return(ret, "Failed to write RX_ADDRH: %d\n", ret);
d0cad871
SG		 724
725 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
1e1d7412 726 check_warn_return(ret, "Failed to write RX_ADDRL: %d\n", ret);
d0cad871
SG		 727
728 addr_hi |= ADDR_FILTX_FB_VALID;
729 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
1e1d7412 730 check_warn_return(ret, "Failed to write ADDR_FILTX: %d\n", ret);
d0cad871
SG		 731
732 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
1e1d7412 733 check_warn_return(ret, "Failed to write ADDR_FILTX+4: %d\n", ret);
d0cad871
SG		 734
735 return 0;
736}
737
738static int smsc75xx_phy_initialize(struct usbnet *dev)
739{
b140504a 740 int bmcr, ret, timeout = 0;
d0cad871
SG		 741
742 /* Initialize MII structure */
743 dev->mii.dev = dev->net;
744 dev->mii.mdio_read = smsc75xx_mdio_read;
745 dev->mii.mdio_write = smsc75xx_mdio_write;
746 dev->mii.phy_id_mask = 0x1f;
747 dev->mii.reg_num_mask = 0x1f;
c0b92e4d 748 dev->mii.supports_gmii = 1;
d0cad871
SG		 749 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
750
751 /* reset phy and wait for reset to complete */
752 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
753
754 do {
755 msleep(10);
756 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
1e1d7412 757 check_warn_return(bmcr, "Error reading MII_BMCR\n");
d0cad871 758 timeout++;
8a1d59d7 759 } while ((bmcr & BMCR_RESET) && (timeout < 100));
d0cad871
SG		 760
761 if (timeout >= 100) {
1e1d7412 762 netdev_warn(dev->net, "timeout on PHY Reset\n");
d0cad871
SG		 763 return -EIO;
764 }
765
766 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
767 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
768 ADVERTISE_PAUSE_ASYM);
c0b92e4d
SG		 769 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
770 ADVERTISE_1000FULL);
d0cad871 771
b140504a
SG		 772 /* read and write to clear phy interrupt status */
773 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
1e1d7412 774 check_warn_return(ret, "Error reading PHY_INT_SRC\n");
b140504a 775 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
d0cad871
SG		 776
777 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
778 PHY_INT_MASK_DEFAULT);
779 mii_nway_restart(&dev->mii);
780
1e1d7412 781 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
d0cad871
SG		 782 return 0;
783}
784
785static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
786{
787 int ret = 0;
788 u32 buf;
789 bool rxenabled;
790
791 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
1e1d7412 792 check_warn_return(ret, "Failed to read MAC_RX: %d\n", ret);
d0cad871
SG		 793
794 rxenabled = ((buf & MAC_RX_RXEN) != 0);
795
796 if (rxenabled) {
797 buf &= ~MAC_RX_RXEN;
798 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1e1d7412 799 check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
d0cad871
SG		 800 }
801
802 /* add 4 to size for FCS */
803 buf &= ~MAC_RX_MAX_SIZE;
804 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
805
806 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1e1d7412 807 check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
d0cad871
SG		 808
809 if (rxenabled) {
810 buf |= MAC_RX_RXEN;
811 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1e1d7412 812 check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
d0cad871
SG		 813 }
814
815 return 0;
816}
817
818static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
819{
820 struct usbnet *dev = netdev_priv(netdev);
821
822 int ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu);
1e1d7412 823 check_warn_return(ret, "Failed to set mac rx frame length\n");
d0cad871
SG		 824
825 return usbnet_change_mtu(netdev, new_mtu);
826}
827
78e47fe4 828/* Enable or disable Rx checksum offload engine */
c8f44aff
MM		 829static int smsc75xx_set_features(struct net_device *netdev,
830 netdev_features_t features)
78e47fe4
MM		 831{
832 struct usbnet *dev = netdev_priv(netdev);
833 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
834 unsigned long flags;
835 int ret;
836
837 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
838
839 if (features & NETIF_F_RXCSUM)
840 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
841 else
842 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
843
844 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
845 /* it's racing here! */
846
847 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1e1d7412 848 check_warn_return(ret, "Error writing RFE_CTL\n");
78e47fe4
MM		 849
850 return 0;
851}
852
47bbea41 853static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
8762cec8
SG		 854{
855 int timeout = 0;
856
857 do {
858 u32 buf;
47bbea41
ML		 859 int ret;
860
861 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
862
1e1d7412 863 check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
8762cec8
SG		 864
865 if (buf & PMT_CTL_DEV_RDY)
866 return 0;
867
868 msleep(10);
869 timeout++;
870 } while (timeout < 100);
871
1e1d7412 872 netdev_warn(dev->net, "timeout waiting for device ready\n");
8762cec8
SG		 873 return -EIO;
874}
875
d0cad871
SG		 876static int smsc75xx_reset(struct usbnet *dev)
877{
878 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
879 u32 buf;
880 int ret = 0, timeout;
881
1e1d7412 882 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
d0cad871 883
47bbea41 884 ret = smsc75xx_wait_ready(dev, 0);
1e1d7412 885 check_warn_return(ret, "device not ready in smsc75xx_reset\n");
8762cec8 886
d0cad871 887 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 888 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871
SG		 889
890 buf |= HW_CFG_LRST;
891
892 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1e1d7412 893 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
d0cad871
SG		 894
895 timeout = 0;
896 do {
897 msleep(10);
898 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 899 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871
SG		 900 timeout++;
901 } while ((buf & HW_CFG_LRST) && (timeout < 100));
902
903 if (timeout >= 100) {
1e1d7412 904 netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
d0cad871
SG		 905 return -EIO;
906 }
907
1e1d7412 908 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
d0cad871
SG		 909
910 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1e1d7412 911 check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
d0cad871
SG		 912
913 buf |= PMT_CTL_PHY_RST;
914
915 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
1e1d7412 916 check_warn_return(ret, "Failed to write PMT_CTL: %d\n", ret);
d0cad871
SG		 917
918 timeout = 0;
919 do {
920 msleep(10);
921 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1e1d7412 922 check_warn_return(ret, "Failed to read PMT_CTL: %d\n", ret);
d0cad871
SG		 923 timeout++;
924 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
925
926 if (timeout >= 100) {
1e1d7412 927 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
d0cad871
SG		 928 return -EIO;
929 }
930
1e1d7412 931 netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
d0cad871
SG		 932
933 smsc75xx_init_mac_address(dev);
934
935 ret = smsc75xx_set_mac_address(dev);
1e1d7412 936 check_warn_return(ret, "Failed to set mac address\n");
d0cad871 937
1e1d7412
JP		 938 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
939 dev->net->dev_addr);
d0cad871
SG		 940
941 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 942 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871 943
1e1d7412
JP		 944 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
945 buf);
d0cad871
SG		 946
947 buf |= HW_CFG_BIR;
948
949 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1e1d7412 950 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
d0cad871
SG		 951
952 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 953 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871 954
1e1d7412
JP		 955 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
956 buf);
d0cad871
SG		 957
958 if (!turbo_mode) {
959 buf = 0;
960 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
961 } else if (dev->udev->speed == USB_SPEED_HIGH) {
962 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
963 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
964 } else {
965 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
966 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
967 }
968
1e1d7412
JP		 969 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
970 (ulong)dev->rx_urb_size);
d0cad871
SG		 971
972 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
1e1d7412 973 check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret);
d0cad871
SG		 974
975 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
1e1d7412 976 check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret);
d0cad871
SG		 977
978 netif_dbg(dev, ifup, dev->net,
1e1d7412 979 "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
d0cad871
SG		 980
981 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
1e1d7412 982 check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret);
d0cad871
SG		 983
984 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
1e1d7412 985 check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret);
d0cad871
SG		 986
987 netif_dbg(dev, ifup, dev->net,
1e1d7412 988 "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
d0cad871
SG		 989
990 if (turbo_mode) {
991 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 992 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871 993
1e1d7412 994 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG		 995
996 buf |= (HW_CFG_MEF | HW_CFG_BCE);
997
998 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
1e1d7412 999 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
d0cad871
SG		 1000
1001 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
1e1d7412 1002 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
d0cad871 1003
1e1d7412 1004 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG		 1005 }
1006
1007 /* set FIFO sizes */
1008 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
1009 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
1e1d7412 1010 check_warn_return(ret, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
d0cad871 1011
1e1d7412 1012 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG		 1013
1014 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
1015 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
1e1d7412 1016 check_warn_return(ret, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
d0cad871 1017
1e1d7412 1018 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG		 1019
1020 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
1e1d7412 1021 check_warn_return(ret, "Failed to write INT_STS: %d\n", ret);
d0cad871
SG		 1022
1023 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
1e1d7412 1024 check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
d0cad871 1025
1e1d7412 1026 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
d0cad871 1027
97138a1c 1028 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
1e1d7412 1029 check_warn_return(ret, "Failed to read E2P_CMD: %d\n", ret);
d0cad871 1030
97138a1c
SG		 1031 /* only set default GPIO/LED settings if no EEPROM is detected */
1032 if (!(buf & E2P_CMD_LOADED)) {
1033 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
1e1d7412
JP		 1034 check_warn_return(ret, "Failed to read LED_GPIO_CFG: %d\n",
1035 ret);
d0cad871 1036
97138a1c
SG		 1037 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
1038 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
1039
1040 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
1e1d7412
JP		 1041 check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n",
1042 ret);
97138a1c 1043 }
d0cad871
SG		 1044
1045 ret = smsc75xx_write_reg(dev, FLOW, 0);
1e1d7412 1046 check_warn_return(ret, "Failed to write FLOW: %d\n", ret);
d0cad871
SG		 1047
1048 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
1e1d7412 1049 check_warn_return(ret, "Failed to write FCT_FLOW: %d\n", ret);
d0cad871
SG		 1050
1051 /* Don't need rfe_ctl_lock during initialisation */
1052 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
1e1d7412 1053 check_warn_return(ret, "Failed to read RFE_CTL: %d\n", ret);
d0cad871
SG		 1054
1055 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
1056
1057 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1e1d7412 1058 check_warn_return(ret, "Failed to write RFE_CTL: %d\n", ret);
d0cad871
SG		 1059
1060 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
1e1d7412 1061 check_warn_return(ret, "Failed to read RFE_CTL: %d\n", ret);
d0cad871 1062
1e1d7412
JP		 1063 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
1064 pdata->rfe_ctl);
d0cad871
SG		 1065
1066 /* Enable or disable checksum offload engines */
78e47fe4 1067 smsc75xx_set_features(dev->net, dev->net->features);
d0cad871
SG		 1068
1069 smsc75xx_set_multicast(dev->net);
1070
1071 ret = smsc75xx_phy_initialize(dev);
1e1d7412 1072 check_warn_return(ret, "Failed to initialize PHY: %d\n", ret);
d0cad871
SG		 1073
1074 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
1e1d7412 1075 check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret);
d0cad871
SG		 1076
1077 /* enable PHY interrupts */
1078 buf |= INT_ENP_PHY_INT;
1079
1080 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
1e1d7412 1081 check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret);
d0cad871 1082
2f3a081e
SG		 1083 /* allow mac to detect speed and duplex from phy */
1084 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
1e1d7412 1085 check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret);
2f3a081e
SG		 1086
1087 buf |= (MAC_CR_ADD | MAC_CR_ASD);
1088 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
1e1d7412 1089 check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
2f3a081e 1090
d0cad871 1091 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
1e1d7412 1092 check_warn_return(ret, "Failed to read MAC_TX: %d\n", ret);
d0cad871
SG		 1093
1094 buf |= MAC_TX_TXEN;
1095
1096 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
1e1d7412 1097 check_warn_return(ret, "Failed to write MAC_TX: %d\n", ret);
d0cad871 1098
1e1d7412 1099 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
d0cad871
SG		 1100
1101 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
1e1d7412 1102 check_warn_return(ret, "Failed to read FCT_TX_CTL: %d\n", ret);
d0cad871
SG		 1103
1104 buf |= FCT_TX_CTL_EN;
1105
1106 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
1e1d7412 1107 check_warn_return(ret, "Failed to write FCT_TX_CTL: %d\n", ret);
d0cad871 1108
1e1d7412 1109 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
d0cad871
SG		 1110
1111 ret = smsc75xx_set_rx_max_frame_length(dev, 1514);
1e1d7412 1112 check_warn_return(ret, "Failed to set max rx frame length\n");
d0cad871
SG		 1113
1114 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
1e1d7412 1115 check_warn_return(ret, "Failed to read MAC_RX: %d\n", ret);
d0cad871
SG		 1116
1117 buf |= MAC_RX_RXEN;
1118
1119 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
1e1d7412 1120 check_warn_return(ret, "Failed to write MAC_RX: %d\n", ret);
d0cad871 1121
1e1d7412 1122 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
d0cad871
SG		 1123
1124 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
1e1d7412 1125 check_warn_return(ret, "Failed to read FCT_RX_CTL: %d\n", ret);
d0cad871
SG		 1126
1127 buf |= FCT_RX_CTL_EN;
1128
1129 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
1e1d7412 1130 check_warn_return(ret, "Failed to write FCT_RX_CTL: %d\n", ret);
d0cad871 1131
1e1d7412 1132 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
d0cad871 1133
1e1d7412 1134 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
d0cad871
SG		 1135 return 0;
1136}
1137
1138static const struct net_device_ops smsc75xx_netdev_ops = {
1139 .ndo_open = usbnet_open,
1140 .ndo_stop = usbnet_stop,
1141 .ndo_start_xmit = usbnet_start_xmit,
1142 .ndo_tx_timeout = usbnet_tx_timeout,
1143 .ndo_change_mtu = smsc75xx_change_mtu,
1144 .ndo_set_mac_address = eth_mac_addr,
1145 .ndo_validate_addr = eth_validate_addr,
1146 .ndo_do_ioctl = smsc75xx_ioctl,
afc4b13d 1147 .ndo_set_rx_mode = smsc75xx_set_multicast,
78e47fe4 1148 .ndo_set_features = smsc75xx_set_features,
d0cad871
SG		 1149};
1150
1151static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
1152{
1153 struct smsc75xx_priv *pdata = NULL;
1154 int ret;
1155
1156 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1157
1158 ret = usbnet_get_endpoints(dev, intf);
1e1d7412 1159 check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret);
d0cad871
SG		 1160
1161 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
1162 GFP_KERNEL);
1163
1164 pdata = (struct smsc75xx_priv *)(dev->data[0]);
1165 if (!pdata) {
1e1d7412 1166 netdev_warn(dev->net, "Unable to allocate smsc75xx_priv\n");
d0cad871
SG		 1167 return -ENOMEM;
1168 }
1169
1170 pdata->dev = dev;
1171
1172 spin_lock_init(&pdata->rfe_ctl_lock);
1173 mutex_init(&pdata->dataport_mutex);
1174
1175 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
1176
78e47fe4
MM		 1177 if (DEFAULT_TX_CSUM_ENABLE) {
1178 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1179 if (DEFAULT_TSO_ENABLE)
1180 dev->net->features |= NETIF_F_SG |
1181 NETIF_F_TSO | NETIF_F_TSO6;
1182 }
1183 if (DEFAULT_RX_CSUM_ENABLE)
1184 dev->net->features |= NETIF_F_RXCSUM;
d0cad871 1185
78e47fe4
MM		 1186 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1187 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_RXCSUM;
d0cad871
SG		 1188
1189 /* Init all registers */
1190 ret = smsc75xx_reset(dev);
33763b79 1191 check_warn_return(ret, "smsc75xx_reset error %d\n", ret);
d0cad871
SG		 1192
1193 dev->net->netdev_ops = &smsc75xx_netdev_ops;
1194 dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
1195 dev->net->flags |= IFF_MULTICAST;
1196 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
a99ff7d0 1197 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
d0cad871
SG		 1198 return 0;
1199}
1200
1201static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1202{
1203 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1204 if (pdata) {
1e1d7412 1205 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
d0cad871
SG		 1206 kfree(pdata);
1207 pdata = NULL;
1208 dev->data[0] = 0;
1209 }
1210}
1211
899a391b
SG		 1212static u16 smsc_crc(const u8 *buffer, size_t len)
1213{
1214 return bitrev16(crc16(0xFFFF, buffer, len));
1215}
1216
1217static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
1218 u32 wuf_mask1)
1219{
1220 int cfg_base = WUF_CFGX + filter * 4;
1221 int mask_base = WUF_MASKX + filter * 16;
1222 int ret;
1223
1224 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
1e1d7412 1225 check_warn_return(ret, "Error writing WUF_CFGX\n");
899a391b
SG		 1226
1227 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
1e1d7412 1228 check_warn_return(ret, "Error writing WUF_MASKX\n");
899a391b
SG		 1229
1230 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
1e1d7412 1231 check_warn_return(ret, "Error writing WUF_MASKX\n");
899a391b
SG		 1232
1233 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
1e1d7412 1234 check_warn_return(ret, "Error writing WUF_MASKX\n");
899a391b
SG		 1235
1236 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
1e1d7412 1237 check_warn_return(ret, "Error writing WUF_MASKX\n");
899a391b
SG		 1238
1239 return 0;
1240}
1241
9deb2757
SG		 1242static int smsc75xx_enter_suspend0(struct usbnet *dev)
1243{
1244 u32 val;
1245 int ret;
1246
1247 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1248 check_warn_return(ret, "Error reading PMT_CTL\n");
1249
1250 val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
1251 val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
1252
1253 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1254 check_warn_return(ret, "Error writing PMT_CTL\n");
1255
1256 smsc75xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
1257
1258 return 0;
1259}
1260
f329ccdc
SG		 1261static int smsc75xx_enter_suspend1(struct usbnet *dev)
1262{
1263 u32 val;
1264 int ret;
1265
1266 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1267 check_warn_return(ret, "Error reading PMT_CTL\n");
1268
1269 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1270 val |= PMT_CTL_SUS_MODE_1;
1271
1272 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1273 check_warn_return(ret, "Error writing PMT_CTL\n");
1274
1275 /* clear wol status, enable energy detection */
1276 val &= ~PMT_CTL_WUPS;
1277 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1278
1279 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1280 check_warn_return(ret, "Error writing PMT_CTL\n");
1281
1282 smsc75xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
1283
1284 return 0;
1285}
1286
9deb2757
SG		 1287static int smsc75xx_enter_suspend2(struct usbnet *dev)
1288{
1289 u32 val;
1290 int ret;
1291
1292 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1293 check_warn_return(ret, "Error reading PMT_CTL\n");
1294
1295 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1296 val |= PMT_CTL_SUS_MODE_2;
1297
1298 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1299 check_warn_return(ret, "Error writing PMT_CTL\n");
1300
1301 return 0;
1302}
1303
f329ccdc
SG		 1304static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
1305{
1306 struct mii_if_info *mii = &dev->mii;
1307 int ret;
1308
1309 netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
1310
1311 /* read to clear */
1312 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
1313 check_warn_return(ret, "Error reading PHY_INT_SRC\n");
1314
1315 /* enable interrupt source */
1316 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
1317 check_warn_return(ret, "Error reading PHY_INT_MASK\n");
1318
1319 ret |= mask;
1320
1321 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1322
1323 return 0;
1324}
1325
1326static int smsc75xx_link_ok_nopm(struct usbnet *dev)
1327{
1328 struct mii_if_info *mii = &dev->mii;
1329 int ret;
1330
1331 /* first, a dummy read, needed to latch some MII phys */
1332 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1333 check_warn_return(ret, "Error reading MII_BMSR\n");
1334
1335 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1336 check_warn_return(ret, "Error reading MII_BMSR\n");
1337
1338 return !!(ret & BMSR_LSTATUS);
1339}
1340
16c79a04
SG		 1341static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
1342{
1343 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1344 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc 1345 u32 val, link_up;
16c79a04 1346 int ret;
16c79a04 1347
16c79a04 1348 ret = usbnet_suspend(intf, message);
eacdd6c2 1349 check_warn_goto_done(ret, "usbnet_suspend error\n");
16c79a04 1350
f329ccdc
SG		 1351 /* determine if link is up using only _nopm functions */
1352 link_up = smsc75xx_link_ok_nopm(dev);
1353
1354 /* if no wol options set, or if link is down and we're not waking on
1355 * PHY activity, enter lowest power SUSPEND2 mode
1356 */
1357 if (!(pdata->wolopts & SUPPORTED_WAKE) ||
1358 !(link_up || (pdata->wolopts & WAKE_PHY))) {
1e1d7412 1359 netdev_info(dev->net, "entering SUSPEND2 mode\n");
6c636503
SG		 1360
1361 /* disable energy detect (link up) & wake up events */
47bbea41 1362 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1363 check_warn_goto_done(ret, "Error reading WUCSR\n");
6c636503
SG		 1364
1365 val &= ~(WUCSR_MPEN | WUCSR_WUEN);
1366
47bbea41 1367 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1368 check_warn_goto_done(ret, "Error writing WUCSR\n");
6c636503 1369
47bbea41 1370 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
eacdd6c2 1371 check_warn_goto_done(ret, "Error reading PMT_CTL\n");
6c636503
SG		 1372
1373 val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
1374
47bbea41 1375 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
eacdd6c2 1376 check_warn_goto_done(ret, "Error writing PMT_CTL\n");
6c636503 1377
eacdd6c2
SG		 1378 ret = smsc75xx_enter_suspend2(dev);
1379 goto done;
6c636503
SG		 1380 }
1381
f329ccdc
SG		 1382 if (pdata->wolopts & WAKE_PHY) {
1383 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1384 (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
eacdd6c2 1385 check_warn_goto_done(ret, "error enabling PHY wakeup ints\n");
f329ccdc
SG		 1386
1387 /* if link is down then configure EDPD and enter SUSPEND1,
1388 * otherwise enter SUSPEND0 below
1389 */
1390 if (!link_up) {
1391 struct mii_if_info *mii = &dev->mii;
1392 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1393
1394 /* enable energy detect power-down mode */
1395 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1396 PHY_MODE_CTRL_STS);
eacdd6c2 1397 check_warn_goto_done(ret, "Error reading PHY_MODE_CTRL_STS\n");
f329ccdc
SG		 1398
1399 ret |= MODE_CTRL_STS_EDPWRDOWN;
1400
1401 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
1402 PHY_MODE_CTRL_STS, ret);
1403
1404 /* enter SUSPEND1 mode */
eacdd6c2
SG		 1405 ret = smsc75xx_enter_suspend1(dev);
1406 goto done;
f329ccdc
SG		 1407 }
1408 }
1409
899a391b
SG		 1410 if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
1411 int i, filter = 0;
1412
1413 /* disable all filters */
1414 for (i = 0; i < WUF_NUM; i++) {
47bbea41 1415 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
eacdd6c2 1416 check_warn_goto_done(ret, "Error writing WUF_CFGX\n");
899a391b
SG		 1417 }
1418
1419 if (pdata->wolopts & WAKE_MCAST) {
1420 const u8 mcast[] = {0x01, 0x00, 0x5E};
1e1d7412 1421 netdev_info(dev->net, "enabling multicast detection\n");
899a391b
SG		 1422
1423 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
1424 | smsc_crc(mcast, 3);
1425 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
eacdd6c2 1426 check_warn_goto_done(ret, "Error writing wakeup filter\n");
899a391b
SG		 1427 }
1428
1429 if (pdata->wolopts & WAKE_ARP) {
1430 const u8 arp[] = {0x08, 0x06};
1e1d7412 1431 netdev_info(dev->net, "enabling ARP detection\n");
899a391b
SG		 1432
1433 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
1434 | smsc_crc(arp, 2);
1435 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
eacdd6c2 1436 check_warn_goto_done(ret, "Error writing wakeup filter\n");
899a391b
SG		 1437 }
1438
1439 /* clear any pending pattern match packet status */
47bbea41 1440 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1441 check_warn_goto_done(ret, "Error reading WUCSR\n");
899a391b
SG		 1442
1443 val |= WUCSR_WUFR;
1444
47bbea41 1445 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1446 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b 1447
1e1d7412 1448 netdev_info(dev->net, "enabling packet match detection\n");
47bbea41 1449 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1450 check_warn_goto_done(ret, "Error reading WUCSR\n");
899a391b
SG		 1451
1452 val |= WUCSR_WUEN;
1453
47bbea41 1454 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1455 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b 1456 } else {
1e1d7412 1457 netdev_info(dev->net, "disabling packet match detection\n");
47bbea41 1458 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1459 check_warn_goto_done(ret, "Error reading WUCSR\n");
6c636503 1460
899a391b 1461 val &= ~WUCSR_WUEN;
16c79a04 1462
47bbea41 1463 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1464 check_warn_goto_done(ret, "Error writing WUCSR\n");
6c636503
SG		 1465 }
1466
899a391b 1467 /* disable magic, bcast & unicast wakeup sources */
47bbea41 1468 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1469 check_warn_goto_done(ret, "Error reading WUCSR\n");
6c636503 1470
899a391b
SG		 1471 val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
1472
47bbea41 1473 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1474 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b 1475
f329ccdc
SG		 1476 if (pdata->wolopts & WAKE_PHY) {
1477 netdev_info(dev->net, "enabling PHY wakeup\n");
1478
1479 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
eacdd6c2 1480 check_warn_goto_done(ret, "Error reading PMT_CTL\n");
f329ccdc
SG		 1481
1482 /* clear wol status, enable energy detection */
1483 val &= ~PMT_CTL_WUPS;
1484 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1485
1486 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
eacdd6c2 1487 check_warn_goto_done(ret, "Error writing PMT_CTL\n");
f329ccdc
SG		 1488 }
1489
6c636503 1490 if (pdata->wolopts & WAKE_MAGIC) {
1e1d7412 1491 netdev_info(dev->net, "enabling magic packet wakeup\n");
47bbea41 1492 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1493 check_warn_goto_done(ret, "Error reading WUCSR\n");
899a391b
SG		 1494
1495 /* clear any pending magic packet status */
1496 val |= WUCSR_MPR | WUCSR_MPEN;
1497
47bbea41 1498 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1499 check_warn_goto_done(ret, "Error writing WUCSR\n");
6c636503
SG		 1500 }
1501
899a391b 1502 if (pdata->wolopts & WAKE_BCAST) {
1e1d7412 1503 netdev_info(dev->net, "enabling broadcast detection\n");
47bbea41 1504 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1505 check_warn_goto_done(ret, "Error reading WUCSR\n");
6c636503 1506
899a391b 1507 val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
16c79a04 1508
47bbea41 1509 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1510 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b 1511 }
6c636503 1512
899a391b 1513 if (pdata->wolopts & WAKE_UCAST) {
1e1d7412 1514 netdev_info(dev->net, "enabling unicast detection\n");
47bbea41 1515 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
eacdd6c2 1516 check_warn_goto_done(ret, "Error reading WUCSR\n");
899a391b
SG		 1517
1518 val |= WUCSR_WUFR | WUCSR_PFDA_EN;
6c636503 1519
47bbea41 1520 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
eacdd6c2 1521 check_warn_goto_done(ret, "Error writing WUCSR\n");
899a391b
SG		 1522 }
1523
1524 /* enable receiver to enable frame reception */
47bbea41 1525 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
eacdd6c2 1526 check_warn_goto_done(ret, "Failed to read MAC_RX: %d\n", ret);
6c636503
SG		 1527
1528 val |= MAC_RX_RXEN;
1529
47bbea41 1530 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
eacdd6c2 1531 check_warn_goto_done(ret, "Failed to write MAC_RX: %d\n", ret);
6c636503
SG		 1532
1533 /* some wol options are enabled, so enter SUSPEND0 */
1e1d7412 1534 netdev_info(dev->net, "entering SUSPEND0 mode\n");
eacdd6c2
SG		 1535 ret = smsc75xx_enter_suspend0(dev);
1536
1537done:
1538 if (ret)
1539 usbnet_resume(intf);
1540 return ret;
16c79a04
SG		 1541}
1542
1543static int smsc75xx_resume(struct usb_interface *intf)
1544{
1545 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1546 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
16c79a04
SG		 1547 int ret;
1548 u32 val;
1549
899a391b 1550 if (pdata->wolopts) {
1e1d7412 1551 netdev_info(dev->net, "resuming from SUSPEND0\n");
16c79a04 1552
6c636503 1553 smsc75xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
16c79a04 1554
899a391b 1555 /* Disable wakeup sources */
47bbea41 1556 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
1e1d7412 1557 check_warn_return(ret, "Error reading WUCSR\n");
16c79a04 1558
899a391b
SG		 1559 val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
1560 | WUCSR_BCST_EN);
16c79a04 1561
47bbea41 1562 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
1e1d7412 1563 check_warn_return(ret, "Error writing WUCSR\n");
6c636503
SG		 1564
1565 /* clear wake-up status */
47bbea41 1566 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1e1d7412 1567 check_warn_return(ret, "Error reading PMT_CTL\n");
6c636503
SG		 1568
1569 val &= ~PMT_CTL_WOL_EN;
1570 val |= PMT_CTL_WUPS;
1571
47bbea41 1572 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1e1d7412 1573 check_warn_return(ret, "Error writing PMT_CTL\n");
6c636503 1574 } else {
1e1d7412 1575 netdev_info(dev->net, "resuming from SUSPEND2\n");
6c636503 1576
47bbea41 1577 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
1e1d7412 1578 check_warn_return(ret, "Error reading PMT_CTL\n");
6c636503
SG		 1579
1580 val |= PMT_CTL_PHY_PWRUP;
1581
47bbea41 1582 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
1e1d7412 1583 check_warn_return(ret, "Error writing PMT_CTL\n");
6c636503 1584 }
16c79a04 1585
47bbea41 1586 ret = smsc75xx_wait_ready(dev, 1);
1e1d7412 1587 check_warn_return(ret, "device not ready in smsc75xx_resume\n");
16c79a04
SG		 1588
1589 return usbnet_resume(intf);
1590}
1591
78e47fe4
MM		 1592static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
1593 u32 rx_cmd_a, u32 rx_cmd_b)
d0cad871 1594{
78e47fe4
MM		 1595 if (!(dev->net->features & NETIF_F_RXCSUM) ||
1596 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
d0cad871
SG		 1597 skb->ip_summed = CHECKSUM_NONE;
1598 } else {
1599 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
1600 skb->ip_summed = CHECKSUM_COMPLETE;
1601 }
1602}
1603
1604static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
1605{
d0cad871
SG		 1606 while (skb->len > 0) {
1607 u32 rx_cmd_a, rx_cmd_b, align_count, size;
1608 struct sk_buff *ax_skb;
1609 unsigned char *packet;
1610
1611 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
1612 le32_to_cpus(&rx_cmd_a);
1613 skb_pull(skb, 4);
1614
1615 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
1616 le32_to_cpus(&rx_cmd_b);
ea1649de 1617 skb_pull(skb, 4 + RXW_PADDING);
d0cad871
SG		 1618
1619 packet = skb->data;
1620
1621 /* get the packet length */
ea1649de
NE		 1622 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
1623 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
d0cad871
SG		 1624
1625 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
1626 netif_dbg(dev, rx_err, dev->net,
1e1d7412 1627 "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
d0cad871
SG		 1628 dev->net->stats.rx_errors++;
1629 dev->net->stats.rx_dropped++;
1630
1631 if (rx_cmd_a & RX_CMD_A_FCS)
1632 dev->net->stats.rx_crc_errors++;
1633 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
1634 dev->net->stats.rx_frame_errors++;
1635 } else {
1636 /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
1637 if (unlikely(size > (ETH_FRAME_LEN + 12))) {
1638 netif_dbg(dev, rx_err, dev->net,
1e1d7412
JP		 1639 "size err rx_cmd_a=0x%08x\n",
1640 rx_cmd_a);
d0cad871
SG		 1641 return 0;
1642 }
1643
1644 /* last frame in this batch */
1645 if (skb->len == size) {
78e47fe4
MM		 1646 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
1647 rx_cmd_b);
d0cad871
SG		 1648
1649 skb_trim(skb, skb->len - 4); /* remove fcs */
1650 skb->truesize = size + sizeof(struct sk_buff);
1651
1652 return 1;
1653 }
1654
1655 ax_skb = skb_clone(skb, GFP_ATOMIC);
1656 if (unlikely(!ax_skb)) {
1e1d7412 1657 netdev_warn(dev->net, "Error allocating skb\n");
d0cad871
SG		 1658 return 0;
1659 }
1660
1661 ax_skb->len = size;
1662 ax_skb->data = packet;
1663 skb_set_tail_pointer(ax_skb, size);
1664
78e47fe4
MM		 1665 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
1666 rx_cmd_b);
d0cad871
SG		 1667
1668 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
1669 ax_skb->truesize = size + sizeof(struct sk_buff);
1670
1671 usbnet_skb_return(dev, ax_skb);
1672 }
1673
1674 skb_pull(skb, size);
1675
1676 /* padding bytes before the next frame starts */
1677 if (skb->len)
1678 skb_pull(skb, align_count);
1679 }
1680
1681 if (unlikely(skb->len < 0)) {
1e1d7412 1682 netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
d0cad871
SG		 1683 return 0;
1684 }
1685
1686 return 1;
1687}
1688
1689static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
1690 struct sk_buff *skb, gfp_t flags)
1691{
1692 u32 tx_cmd_a, tx_cmd_b;
1693
1694 skb_linearize(skb);
1695
1696 if (skb_headroom(skb) < SMSC75XX_TX_OVERHEAD) {
1697 struct sk_buff *skb2 =
1698 skb_copy_expand(skb, SMSC75XX_TX_OVERHEAD, 0, flags);
1699 dev_kfree_skb_any(skb);
1700 skb = skb2;
1701 if (!skb)
1702 return NULL;
1703 }
1704
1705 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
1706
1707 if (skb->ip_summed == CHECKSUM_PARTIAL)
1708 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
1709
1710 if (skb_is_gso(skb)) {
1711 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
1712 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
1713
1714 tx_cmd_a |= TX_CMD_A_LSO;
1715 } else {
1716 tx_cmd_b = 0;
1717 }
1718
1719 skb_push(skb, 4);
1720 cpu_to_le32s(&tx_cmd_b);
1721 memcpy(skb->data, &tx_cmd_b, 4);
1722
1723 skb_push(skb, 4);
1724 cpu_to_le32s(&tx_cmd_a);
1725 memcpy(skb->data, &tx_cmd_a, 4);
1726
1727 return skb;
1728}
1729
1730static const struct driver_info smsc75xx_info = {
1731 .description = "smsc75xx USB 2.0 Gigabit Ethernet",
1732 .bind = smsc75xx_bind,
1733 .unbind = smsc75xx_unbind,
1734 .link_reset = smsc75xx_link_reset,
1735 .reset = smsc75xx_reset,
1736 .rx_fixup = smsc75xx_rx_fixup,
1737 .tx_fixup = smsc75xx_tx_fixup,
1738 .status = smsc75xx_status,
7bdd305e 1739 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
d0cad871
SG		 1740};
1741
1742static const struct usb_device_id products[] = {
1743 {
1744 /* SMSC7500 USB Gigabit Ethernet Device */
1745 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
1746 .driver_info = (unsigned long) &smsc75xx_info,
1747 },
1748 {
1749 /* SMSC7500 USB Gigabit Ethernet Device */
1750 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
1751 .driver_info = (unsigned long) &smsc75xx_info,
1752 },
1753 { }, /* END */
1754};
1755MODULE_DEVICE_TABLE(usb, products);
1756
1757static struct usb_driver smsc75xx_driver = {
1758 .name = SMSC_CHIPNAME,
1759 .id_table = products,
1760 .probe = usbnet_probe,
16c79a04
SG		 1761 .suspend = smsc75xx_suspend,
1762 .resume = smsc75xx_resume,
1763 .reset_resume = smsc75xx_resume,
d0cad871 1764 .disconnect = usbnet_disconnect,
e1f12eb6 1765 .disable_hub_initiated_lpm = 1,
d0cad871
SG		 1766};
1767
d632eb1b 1768module_usb_driver(smsc75xx_driver);
d0cad871
SG		 1769
1770MODULE_AUTHOR("Nancy Lin");
90b24cfb 1771MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
d0cad871
SG		 1772MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
1773MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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