[deliverable/linux.git] / drivers / net / usb / sr9700.h

/*
 * CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices
 *
 * Author : Liu Junliang <liujunliang_ljl@163.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 */

#ifndef _SR9700_H
#define	_SR9700_H

/* sr9700 spec. register table on Linux platform */

/* Network Control Reg */
#define	SR_NCR			0x00
#define		NCR_RST			(1 << 0)
#define		NCR_LBK			(3 << 1)
#define		NCR_FDX			(1 << 3)
#define		NCR_WAKEEN		(1 << 6)
/* Network Status Reg */
#define	SR_NSR			0x01
#define		NSR_RXRDY		(1 << 0)
#define		NSR_RXOV		(1 << 1)
#define		NSR_TX1END		(1 << 2)
#define		NSR_TX2END		(1 << 3)
#define		NSR_TXFULL		(1 << 4)
#define		NSR_WAKEST		(1 << 5)
#define		NSR_LINKST		(1 << 6)
#define		NSR_SPEED		(1 << 7)
/* Tx Control Reg */
#define	SR_TCR			0x02
#define		TCR_CRC_DIS		(1 << 1)
#define		TCR_PAD_DIS		(1 << 2)
#define		TCR_LC_CARE		(1 << 3)
#define		TCR_CRS_CARE	(1 << 4)
#define		TCR_EXCECM		(1 << 5)
#define		TCR_LF_EN		(1 << 6)
/* Tx Status Reg for Packet Index 1 */
#define	SR_TSR1		0x03
#define		TSR1_EC			(1 << 2)
#define		TSR1_COL		(1 << 3)
#define		TSR1_LC			(1 << 4)
#define		TSR1_NC			(1 << 5)
#define		TSR1_LOC		(1 << 6)
#define		TSR1_TLF		(1 << 7)
/* Tx Status Reg for Packet Index 2 */
#define	SR_TSR2		0x04
#define		TSR2_EC			(1 << 2)
#define		TSR2_COL		(1 << 3)
#define		TSR2_LC			(1 << 4)
#define		TSR2_NC			(1 << 5)
#define		TSR2_LOC		(1 << 6)
#define		TSR2_TLF		(1 << 7)
/* Rx Control Reg*/
#define	SR_RCR			0x05
#define		RCR_RXEN		(1 << 0)
#define		RCR_PRMSC		(1 << 1)
#define		RCR_RUNT		(1 << 2)
#define		RCR_ALL			(1 << 3)
#define		RCR_DIS_CRC		(1 << 4)
#define		RCR_DIS_LONG	(1 << 5)
/* Rx Status Reg */
#define	SR_RSR			0x06
#define		RSR_AE			(1 << 2)
#define		RSR_MF			(1 << 6)
#define		RSR_RF			(1 << 7)
/* Rx Overflow Counter Reg */
#define	SR_ROCR		0x07
#define		ROCR_ROC		(0x7F << 0)
#define		ROCR_RXFU		(1 << 7)
/* Back Pressure Threshold Reg */
#define	SR_BPTR		0x08
#define		BPTR_JPT		(0x0F << 0)
#define		BPTR_BPHW		(0x0F << 4)
/* Flow Control Threshold Reg */
#define	SR_FCTR		0x09
#define		FCTR_LWOT		(0x0F << 0)
#define		FCTR_HWOT		(0x0F << 4)
/* rx/tx Flow Control Reg */
#define	SR_FCR			0x0A
#define		FCR_FLCE		(1 << 0)
#define		FCR_BKPA		(1 << 4)
#define		FCR_TXPEN		(1 << 5)
#define		FCR_TXPF		(1 << 6)
#define		FCR_TXP0		(1 << 7)
/* Eeprom & Phy Control Reg */
#define	SR_EPCR		0x0B
#define		EPCR_ERRE		(1 << 0)
#define		EPCR_ERPRW		(1 << 1)
#define		EPCR_ERPRR		(1 << 2)
#define		EPCR_EPOS		(1 << 3)
#define		EPCR_WEP		(1 << 4)
/* Eeprom & Phy Address Reg */
#define	SR_EPAR		0x0C
#define		EPAR_EROA		(0x3F << 0)
#define		EPAR_PHY_ADR_MASK	(0x03 << 6)
#define		EPAR_PHY_ADR		(0x01 << 6)
/* Eeprom &	Phy Data Reg */
#define	SR_EPDR		0x0D	/* 0x0D ~ 0x0E for Data Reg Low & High */
/* Wakeup Control Reg */
#define	SR_WCR			0x0F
#define		WCR_MAGICST		(1 << 0)
#define		WCR_LINKST		(1 << 2)
#define		WCR_MAGICEN		(1 << 3)
#define		WCR_LINKEN		(1 << 5)
/* Physical Address Reg */
#define	SR_PAR			0x10	/* 0x10 ~ 0x15 6 bytes for PAR */
/* Multicast Address Reg */
#define	SR_MAR			0x16	/* 0x16 ~ 0x1D 8 bytes for MAR */
/* 0x1e unused */
/* Phy Reset Reg */
#define	SR_PRR			0x1F
#define		PRR_PHY_RST		(1 << 0)
/* Tx sdram Write Pointer Address Low */
#define	SR_TWPAL		0x20
/* Tx sdram Write Pointer Address High */
#define	SR_TWPAH		0x21
/* Tx sdram Read Pointer Address Low */
#define	SR_TRPAL		0x22
/* Tx sdram Read Pointer Address High */
#define	SR_TRPAH		0x23
/* Rx sdram Write Pointer Address Low */
#define	SR_RWPAL		0x24
/* Rx sdram Write Pointer Address High */
#define	SR_RWPAH		0x25
/* Rx sdram Read Pointer Address Low */
#define	SR_RRPAL		0x26
/* Rx sdram Read Pointer Address High */
#define	SR_RRPAH		0x27
/* Vendor ID register */
#define	SR_VID			0x28	/* 0x28 ~ 0x29 2 bytes for VID */
/* Product ID register */
#define	SR_PID			0x2A	/* 0x2A ~ 0x2B 2 bytes for PID */
/* CHIP Revision register */
#define	SR_CHIPR		0x2C
/* 0x2D --> 0xEF unused */
/* USB Device Address */
#define	SR_USBDA		0xF0
#define		USBDA_USBFA		(0x7F << 0)
/* RX packet Counter Reg */
#define	SR_RXC			0xF1
/* Tx packet Counter & USB Status Reg */
#define	SR_TXC_USBS		0xF2
#define		TXC_USBS_TXC0		(1 << 0)
#define		TXC_USBS_TXC1		(1 << 1)
#define		TXC_USBS_TXC2		(1 << 2)
#define		TXC_USBS_EP1RDY		(1 << 5)
#define		TXC_USBS_SUSFLAG	(1 << 6)
#define		TXC_USBS_RXFAULT	(1 << 7)
/* USB Control register */
#define	SR_USBC			0xF4
#define		USBC_EP3NAK		(1 << 4)
#define		USBC_EP3ACK		(1 << 5)

/* Register access commands and flags */
#define	SR_RD_REGS		0x00
#define	SR_WR_REGS		0x01
#define	SR_WR_REG		0x03
#define	SR_REQ_RD_REG	(USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
#define	SR_REQ_WR_REG	(USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)

/* parameters */
#define	SR_SHARE_TIMEOUT	1000
#define	SR_EEPROM_LEN		256
#define	SR_MCAST_SIZE		8
#define	SR_MCAST_ADDR_FLAG	0x80
#define	SR_MCAST_MAX		64
#define	SR_TX_OVERHEAD		2	/* 2bytes header */
#define	SR_RX_OVERHEAD		7	/* 3bytes header + 4crc tail */

#endif	/* _SR9700_H */
Commit	Line	Data
c9b37458 LJ	1	/*
	2	* CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices
	3	*
	4	* Author : Liu Junliang <liujunliang_ljl@163.com>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* version 2 as published by the Free Software Foundation.
	9	*/
	10
	11	#ifndef _SR9700_H
	12	#define _SR9700_H
	13
	14	/* sr9700 spec. register table on Linux platform */
	15
	16	/* Network Control Reg */
06b19b1b	17	#define SR_NCR 0x00
c9b37458 LJ	18	#define NCR_RST (1 << 0)
	19	#define NCR_LBK (3 << 1)
	20	#define NCR_FDX (1 << 3)
	21	#define NCR_WAKEEN (1 << 6)
	22	/* Network Status Reg */
06b19b1b	23	#define SR_NSR 0x01
c9b37458 LJ	24	#define NSR_RXRDY (1 << 0)
	25	#define NSR_RXOV (1 << 1)
	26	#define NSR_TX1END (1 << 2)
	27	#define NSR_TX2END (1 << 3)
	28	#define NSR_TXFULL (1 << 4)
	29	#define NSR_WAKEST (1 << 5)
	30	#define NSR_LINKST (1 << 6)
	31	#define NSR_SPEED (1 << 7)
	32	/* Tx Control Reg */
06b19b1b	33	#define SR_TCR 0x02
c9b37458 LJ	34	#define TCR_CRC_DIS (1 << 1)
	35	#define TCR_PAD_DIS (1 << 2)
	36	#define TCR_LC_CARE (1 << 3)
	37	#define TCR_CRS_CARE (1 << 4)
	38	#define TCR_EXCECM (1 << 5)
	39	#define TCR_LF_EN (1 << 6)
	40	/* Tx Status Reg for Packet Index 1 */
06b19b1b	41	#define SR_TSR1 0x03
c9b37458 LJ	42	#define TSR1_EC (1 << 2)
	43	#define TSR1_COL (1 << 3)
	44	#define TSR1_LC (1 << 4)
	45	#define TSR1_NC (1 << 5)
	46	#define TSR1_LOC (1 << 6)
	47	#define TSR1_TLF (1 << 7)
	48	/* Tx Status Reg for Packet Index 2 */
06b19b1b	49	#define SR_TSR2 0x04
c9b37458 LJ	50	#define TSR2_EC (1 << 2)
	51	#define TSR2_COL (1 << 3)
	52	#define TSR2_LC (1 << 4)
	53	#define TSR2_NC (1 << 5)
	54	#define TSR2_LOC (1 << 6)
	55	#define TSR2_TLF (1 << 7)
	56	/* Rx Control Reg*/
06b19b1b	57	#define SR_RCR 0x05
c9b37458 LJ	58	#define RCR_RXEN (1 << 0)
	59	#define RCR_PRMSC (1 << 1)
	60	#define RCR_RUNT (1 << 2)
	61	#define RCR_ALL (1 << 3)
	62	#define RCR_DIS_CRC (1 << 4)
	63	#define RCR_DIS_LONG (1 << 5)
	64	/* Rx Status Reg */
06b19b1b	65	#define SR_RSR 0x06
c9b37458 LJ	66	#define RSR_AE (1 << 2)
	67	#define RSR_MF (1 << 6)
	68	#define RSR_RF (1 << 7)
	69	/* Rx Overflow Counter Reg */
06b19b1b	70	#define SR_ROCR 0x07
c9b37458 LJ	71	#define ROCR_ROC (0x7F << 0)
	72	#define ROCR_RXFU (1 << 7)
	73	/* Back Pressure Threshold Reg */
06b19b1b	74	#define SR_BPTR 0x08
c9b37458 LJ	75	#define BPTR_JPT (0x0F << 0)
	76	#define BPTR_BPHW (0x0F << 4)
	77	/* Flow Control Threshold Reg */
06b19b1b	78	#define SR_FCTR 0x09
c9b37458 LJ	79	#define FCTR_LWOT (0x0F << 0)
	80	#define FCTR_HWOT (0x0F << 4)
	81	/* rx/tx Flow Control Reg */
06b19b1b	82	#define SR_FCR 0x0A
c9b37458 LJ	83	#define FCR_FLCE (1 << 0)
	84	#define FCR_BKPA (1 << 4)
	85	#define FCR_TXPEN (1 << 5)
	86	#define FCR_TXPF (1 << 6)
	87	#define FCR_TXP0 (1 << 7)
	88	/* Eeprom & Phy Control Reg */
06b19b1b	89	#define SR_EPCR 0x0B
c9b37458 LJ	90	#define EPCR_ERRE (1 << 0)
	91	#define EPCR_ERPRW (1 << 1)
	92	#define EPCR_ERPRR (1 << 2)
	93	#define EPCR_EPOS (1 << 3)
	94	#define EPCR_WEP (1 << 4)
	95	/* Eeprom & Phy Address Reg */
06b19b1b	96	#define SR_EPAR 0x0C
c9b37458 LJ	97	#define EPAR_EROA (0x3F << 0)
	98	#define EPAR_PHY_ADR_MASK (0x03 << 6)
	99	#define EPAR_PHY_ADR (0x01 << 6)
	100	/* Eeprom & Phy Data Reg */
06b19b1b	101	#define SR_EPDR 0x0D /* 0x0D ~ 0x0E for Data Reg Low & High */
c9b37458	102	/* Wakeup Control Reg */
06b19b1b	103	#define SR_WCR 0x0F
c9b37458 LJ	104	#define WCR_MAGICST (1 << 0)
	105	#define WCR_LINKST (1 << 2)
	106	#define WCR_MAGICEN (1 << 3)
	107	#define WCR_LINKEN (1 << 5)
	108	/* Physical Address Reg */
06b19b1b	109	#define SR_PAR 0x10 /* 0x10 ~ 0x15 6 bytes for PAR */
c9b37458	110	/* Multicast Address Reg */
06b19b1b	111	#define SR_MAR 0x16 /* 0x16 ~ 0x1D 8 bytes for MAR */
c9b37458 LJ	112	/* 0x1e unused */
c9b37458 LJ	113	/* Phy Reset Reg */
06b19b1b	114	#define SR_PRR 0x1F
c9b37458 LJ	115	#define PRR_PHY_RST (1 << 0)
c9b37458 LJ	116	/* Tx sdram Write Pointer Address Low */
06b19b1b	117	#define SR_TWPAL 0x20
c9b37458	118	/* Tx sdram Write Pointer Address High */
06b19b1b	119	#define SR_TWPAH 0x21
c9b37458	120	/* Tx sdram Read Pointer Address Low */
06b19b1b	121	#define SR_TRPAL 0x22
c9b37458	122	/* Tx sdram Read Pointer Address High */
06b19b1b	123	#define SR_TRPAH 0x23
c9b37458	124	/* Rx sdram Write Pointer Address Low */
06b19b1b	125	#define SR_RWPAL 0x24
c9b37458	126	/* Rx sdram Write Pointer Address High */
06b19b1b	127	#define SR_RWPAH 0x25
c9b37458	128	/* Rx sdram Read Pointer Address Low */
06b19b1b	129	#define SR_RRPAL 0x26
c9b37458	130	/* Rx sdram Read Pointer Address High */
06b19b1b	131	#define SR_RRPAH 0x27
c9b37458	132	/* Vendor ID register */
06b19b1b	133	#define SR_VID 0x28 /* 0x28 ~ 0x29 2 bytes for VID */
c9b37458	134	/* Product ID register */
06b19b1b	135	#define SR_PID 0x2A /* 0x2A ~ 0x2B 2 bytes for PID */
c9b37458	136	/* CHIP Revision register */
06b19b1b	137	#define SR_CHIPR 0x2C
c9b37458 LJ	138	/* 0x2D --> 0xEF unused */
c9b37458 LJ	139	/* USB Device Address */
06b19b1b	140	#define SR_USBDA 0xF0
c9b37458 LJ	141	#define USBDA_USBFA (0x7F << 0)
c9b37458 LJ	142	/* RX packet Counter Reg */
06b19b1b	143	#define SR_RXC 0xF1
c9b37458	144	/* Tx packet Counter & USB Status Reg */
06b19b1b	145	#define SR_TXC_USBS 0xF2
c9b37458 LJ	146	#define TXC_USBS_TXC0 (1 << 0)
	147	#define TXC_USBS_TXC1 (1 << 1)
	148	#define TXC_USBS_TXC2 (1 << 2)
	149	#define TXC_USBS_EP1RDY (1 << 5)
	150	#define TXC_USBS_SUSFLAG (1 << 6)
	151	#define TXC_USBS_RXFAULT (1 << 7)
	152	/* USB Control register */
06b19b1b	153	#define SR_USBC 0xF4
c9b37458 LJ	154	#define USBC_EP3NAK (1 << 4)
	155	#define USBC_EP3ACK (1 << 5)
	156
	157	/* Register access commands and flags */
	158	#define SR_RD_REGS 0x00
	159	#define SR_WR_REGS 0x01
	160	#define SR_WR_REG 0x03
	161	#define SR_REQ_RD_REG (USB_DIR_IN \| USB_TYPE_VENDOR \| USB_RECIP_DEVICE)
	162	#define SR_REQ_WR_REG (USB_DIR_OUT \| USB_TYPE_VENDOR \| USB_RECIP_DEVICE)
	163
	164	/* parameters */
	165	#define SR_SHARE_TIMEOUT 1000
	166	#define SR_EEPROM_LEN 256
	167	#define SR_MCAST_SIZE 8
	168	#define SR_MCAST_ADDR_FLAG 0x80
	169	#define SR_MCAST_MAX 64
	170	#define SR_TX_OVERHEAD 2 /* 2bytes header */
	171	#define SR_RX_OVERHEAD 7 /* 3bytes header + 4crc tail */
	172
	173	#endif /* _SR9700_H */