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1da177e4 LT |
1 | /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */ |
2 | /* | |
3 | Written 1998-2001 by Donald Becker. | |
4 | ||
5 | Current Maintainer: Roger Luethi <rl@hellgate.ch> | |
6 | ||
7 | This software may be used and distributed according to the terms of | |
8 | the GNU General Public License (GPL), incorporated herein by reference. | |
9 | Drivers based on or derived from this code fall under the GPL and must | |
10 | retain the authorship, copyright and license notice. This file is not | |
11 | a complete program and may only be used when the entire operating | |
12 | system is licensed under the GPL. | |
13 | ||
14 | This driver is designed for the VIA VT86C100A Rhine-I. | |
15 | It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM | |
16 | and management NIC 6105M). | |
17 | ||
18 | The author may be reached as becker@scyld.com, or C/O | |
19 | Scyld Computing Corporation | |
20 | 410 Severn Ave., Suite 210 | |
21 | Annapolis MD 21403 | |
22 | ||
23 | ||
24 | This driver contains some changes from the original Donald Becker | |
25 | version. He may or may not be interested in bug reports on this | |
26 | code. You can find his versions at: | |
27 | http://www.scyld.com/network/via-rhine.html | |
03a8c661 | 28 | [link no longer provides useful info -jgarzik] |
1da177e4 LT |
29 | |
30 | */ | |
31 | ||
32 | #define DRV_NAME "via-rhine" | |
e84df485 RL |
33 | #define DRV_VERSION "1.4.3" |
34 | #define DRV_RELDATE "2007-03-06" | |
1da177e4 LT |
35 | |
36 | ||
37 | /* A few user-configurable values. | |
38 | These may be modified when a driver module is loaded. */ | |
39 | ||
40 | static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ | |
41 | static int max_interrupt_work = 20; | |
42 | ||
43 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. | |
44 | Setting to > 1518 effectively disables this feature. */ | |
b47157f0 DM |
45 | #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \ |
46 | || defined(CONFIG_SPARC) || defined(__ia64__) \ | |
47 | || defined(__sh__) || defined(__mips__) | |
48 | static int rx_copybreak = 1518; | |
49 | #else | |
1da177e4 | 50 | static int rx_copybreak; |
b47157f0 | 51 | #endif |
1da177e4 | 52 | |
b933b4d9 RL |
53 | /* Work-around for broken BIOSes: they are unable to get the chip back out of |
54 | power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */ | |
55 | static int avoid_D3; | |
56 | ||
1da177e4 LT |
57 | /* |
58 | * In case you are looking for 'options[]' or 'full_duplex[]', they | |
59 | * are gone. Use ethtool(8) instead. | |
60 | */ | |
61 | ||
62 | /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). | |
63 | The Rhine has a 64 element 8390-like hash table. */ | |
64 | static const int multicast_filter_limit = 32; | |
65 | ||
66 | ||
67 | /* Operational parameters that are set at compile time. */ | |
68 | ||
69 | /* Keep the ring sizes a power of two for compile efficiency. | |
70 | The compiler will convert <unsigned>'%'<2^N> into a bit mask. | |
71 | Making the Tx ring too large decreases the effectiveness of channel | |
72 | bonding and packet priority. | |
73 | There are no ill effects from too-large receive rings. */ | |
74 | #define TX_RING_SIZE 16 | |
75 | #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ | |
633949a1 | 76 | #define RX_RING_SIZE 64 |
1da177e4 LT |
77 | |
78 | /* Operational parameters that usually are not changed. */ | |
79 | ||
80 | /* Time in jiffies before concluding the transmitter is hung. */ | |
81 | #define TX_TIMEOUT (2*HZ) | |
82 | ||
83 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ | |
84 | ||
85 | #include <linux/module.h> | |
86 | #include <linux/moduleparam.h> | |
87 | #include <linux/kernel.h> | |
88 | #include <linux/string.h> | |
89 | #include <linux/timer.h> | |
90 | #include <linux/errno.h> | |
91 | #include <linux/ioport.h> | |
92 | #include <linux/slab.h> | |
93 | #include <linux/interrupt.h> | |
94 | #include <linux/pci.h> | |
1e7f0bd8 | 95 | #include <linux/dma-mapping.h> |
1da177e4 LT |
96 | #include <linux/netdevice.h> |
97 | #include <linux/etherdevice.h> | |
98 | #include <linux/skbuff.h> | |
99 | #include <linux/init.h> | |
100 | #include <linux/delay.h> | |
101 | #include <linux/mii.h> | |
102 | #include <linux/ethtool.h> | |
103 | #include <linux/crc32.h> | |
104 | #include <linux/bitops.h> | |
105 | #include <asm/processor.h> /* Processor type for cache alignment. */ | |
106 | #include <asm/io.h> | |
107 | #include <asm/irq.h> | |
108 | #include <asm/uaccess.h> | |
e84df485 | 109 | #include <linux/dmi.h> |
1da177e4 LT |
110 | |
111 | /* These identify the driver base version and may not be removed. */ | |
112 | static char version[] __devinitdata = | |
113 | KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n"; | |
114 | ||
115 | /* This driver was written to use PCI memory space. Some early versions | |
116 | of the Rhine may only work correctly with I/O space accesses. */ | |
117 | #ifdef CONFIG_VIA_RHINE_MMIO | |
118 | #define USE_MMIO | |
119 | #else | |
120 | #endif | |
121 | ||
122 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); | |
123 | MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver"); | |
124 | MODULE_LICENSE("GPL"); | |
125 | ||
126 | module_param(max_interrupt_work, int, 0); | |
127 | module_param(debug, int, 0); | |
128 | module_param(rx_copybreak, int, 0); | |
b933b4d9 | 129 | module_param(avoid_D3, bool, 0); |
1da177e4 LT |
130 | MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt"); |
131 | MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)"); | |
132 | MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames"); | |
b933b4d9 | 133 | MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)"); |
1da177e4 LT |
134 | |
135 | /* | |
136 | Theory of Operation | |
137 | ||
138 | I. Board Compatibility | |
139 | ||
140 | This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet | |
141 | controller. | |
142 | ||
143 | II. Board-specific settings | |
144 | ||
145 | Boards with this chip are functional only in a bus-master PCI slot. | |
146 | ||
147 | Many operational settings are loaded from the EEPROM to the Config word at | |
148 | offset 0x78. For most of these settings, this driver assumes that they are | |
149 | correct. | |
150 | If this driver is compiled to use PCI memory space operations the EEPROM | |
151 | must be configured to enable memory ops. | |
152 | ||
153 | III. Driver operation | |
154 | ||
155 | IIIa. Ring buffers | |
156 | ||
157 | This driver uses two statically allocated fixed-size descriptor lists | |
158 | formed into rings by a branch from the final descriptor to the beginning of | |
159 | the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. | |
160 | ||
161 | IIIb/c. Transmit/Receive Structure | |
162 | ||
163 | This driver attempts to use a zero-copy receive and transmit scheme. | |
164 | ||
165 | Alas, all data buffers are required to start on a 32 bit boundary, so | |
166 | the driver must often copy transmit packets into bounce buffers. | |
167 | ||
168 | The driver allocates full frame size skbuffs for the Rx ring buffers at | |
169 | open() time and passes the skb->data field to the chip as receive data | |
170 | buffers. When an incoming frame is less than RX_COPYBREAK bytes long, | |
171 | a fresh skbuff is allocated and the frame is copied to the new skbuff. | |
172 | When the incoming frame is larger, the skbuff is passed directly up the | |
173 | protocol stack. Buffers consumed this way are replaced by newly allocated | |
174 | skbuffs in the last phase of rhine_rx(). | |
175 | ||
176 | The RX_COPYBREAK value is chosen to trade-off the memory wasted by | |
177 | using a full-sized skbuff for small frames vs. the copying costs of larger | |
178 | frames. New boards are typically used in generously configured machines | |
179 | and the underfilled buffers have negligible impact compared to the benefit of | |
180 | a single allocation size, so the default value of zero results in never | |
181 | copying packets. When copying is done, the cost is usually mitigated by using | |
182 | a combined copy/checksum routine. Copying also preloads the cache, which is | |
183 | most useful with small frames. | |
184 | ||
185 | Since the VIA chips are only able to transfer data to buffers on 32 bit | |
186 | boundaries, the IP header at offset 14 in an ethernet frame isn't | |
187 | longword aligned for further processing. Copying these unaligned buffers | |
188 | has the beneficial effect of 16-byte aligning the IP header. | |
189 | ||
190 | IIId. Synchronization | |
191 | ||
192 | The driver runs as two independent, single-threaded flows of control. One | |
193 | is the send-packet routine, which enforces single-threaded use by the | |
194 | dev->priv->lock spinlock. The other thread is the interrupt handler, which | |
195 | is single threaded by the hardware and interrupt handling software. | |
196 | ||
197 | The send packet thread has partial control over the Tx ring. It locks the | |
198 | dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring | |
199 | is not available it stops the transmit queue by calling netif_stop_queue. | |
200 | ||
201 | The interrupt handler has exclusive control over the Rx ring and records stats | |
202 | from the Tx ring. After reaping the stats, it marks the Tx queue entry as | |
203 | empty by incrementing the dirty_tx mark. If at least half of the entries in | |
204 | the Rx ring are available the transmit queue is woken up if it was stopped. | |
205 | ||
206 | IV. Notes | |
207 | ||
208 | IVb. References | |
209 | ||
210 | Preliminary VT86C100A manual from http://www.via.com.tw/ | |
211 | http://www.scyld.com/expert/100mbps.html | |
212 | http://www.scyld.com/expert/NWay.html | |
213 | ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf | |
214 | ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF | |
215 | ||
216 | ||
217 | IVc. Errata | |
218 | ||
219 | The VT86C100A manual is not reliable information. | |
220 | The 3043 chip does not handle unaligned transmit or receive buffers, resulting | |
221 | in significant performance degradation for bounce buffer copies on transmit | |
222 | and unaligned IP headers on receive. | |
223 | The chip does not pad to minimum transmit length. | |
224 | ||
225 | */ | |
226 | ||
227 | ||
228 | /* This table drives the PCI probe routines. It's mostly boilerplate in all | |
229 | of the drivers, and will likely be provided by some future kernel. | |
230 | Note the matching code -- the first table entry matchs all 56** cards but | |
231 | second only the 1234 card. | |
232 | */ | |
233 | ||
234 | enum rhine_revs { | |
235 | VT86C100A = 0x00, | |
236 | VTunknown0 = 0x20, | |
237 | VT6102 = 0x40, | |
238 | VT8231 = 0x50, /* Integrated MAC */ | |
239 | VT8233 = 0x60, /* Integrated MAC */ | |
240 | VT8235 = 0x74, /* Integrated MAC */ | |
241 | VT8237 = 0x78, /* Integrated MAC */ | |
242 | VTunknown1 = 0x7C, | |
243 | VT6105 = 0x80, | |
244 | VT6105_B0 = 0x83, | |
245 | VT6105L = 0x8A, | |
246 | VT6107 = 0x8C, | |
247 | VTunknown2 = 0x8E, | |
248 | VT6105M = 0x90, /* Management adapter */ | |
249 | }; | |
250 | ||
251 | enum rhine_quirks { | |
252 | rqWOL = 0x0001, /* Wake-On-LAN support */ | |
253 | rqForceReset = 0x0002, | |
254 | rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */ | |
255 | rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */ | |
256 | rqRhineI = 0x0100, /* See comment below */ | |
257 | }; | |
258 | /* | |
259 | * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable | |
260 | * MMIO as well as for the collision counter and the Tx FIFO underflow | |
261 | * indicator. In addition, Tx and Rx buffers need to 4 byte aligned. | |
262 | */ | |
263 | ||
264 | /* Beware of PCI posted writes */ | |
265 | #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0) | |
266 | ||
46009c8b JG |
267 | static const struct pci_device_id rhine_pci_tbl[] = { |
268 | { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */ | |
269 | { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */ | |
270 | { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */ | |
271 | { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */ | |
1da177e4 LT |
272 | { } /* terminate list */ |
273 | }; | |
274 | MODULE_DEVICE_TABLE(pci, rhine_pci_tbl); | |
275 | ||
276 | ||
277 | /* Offsets to the device registers. */ | |
278 | enum register_offsets { | |
279 | StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08, | |
280 | ChipCmd1=0x09, | |
281 | IntrStatus=0x0C, IntrEnable=0x0E, | |
282 | MulticastFilter0=0x10, MulticastFilter1=0x14, | |
283 | RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54, | |
284 | MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, | |
285 | MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74, | |
286 | ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B, | |
287 | RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81, | |
288 | StickyHW=0x83, IntrStatus2=0x84, | |
289 | WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4, | |
290 | WOLcrClr1=0xA6, WOLcgClr=0xA7, | |
291 | PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD, | |
292 | }; | |
293 | ||
294 | /* Bits in ConfigD */ | |
295 | enum backoff_bits { | |
296 | BackOptional=0x01, BackModify=0x02, | |
297 | BackCaptureEffect=0x04, BackRandom=0x08 | |
298 | }; | |
299 | ||
300 | #ifdef USE_MMIO | |
301 | /* Registers we check that mmio and reg are the same. */ | |
302 | static const int mmio_verify_registers[] = { | |
303 | RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD, | |
304 | 0 | |
305 | }; | |
306 | #endif | |
307 | ||
308 | /* Bits in the interrupt status/mask registers. */ | |
309 | enum intr_status_bits { | |
310 | IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020, | |
311 | IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210, | |
312 | IntrPCIErr=0x0040, | |
313 | IntrStatsMax=0x0080, IntrRxEarly=0x0100, | |
314 | IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000, | |
315 | IntrTxAborted=0x2000, IntrLinkChange=0x4000, | |
316 | IntrRxWakeUp=0x8000, | |
317 | IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260, | |
318 | IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */ | |
319 | IntrTxErrSummary=0x082218, | |
320 | }; | |
321 | ||
322 | /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */ | |
323 | enum wol_bits { | |
324 | WOLucast = 0x10, | |
325 | WOLmagic = 0x20, | |
326 | WOLbmcast = 0x30, | |
327 | WOLlnkon = 0x40, | |
328 | WOLlnkoff = 0x80, | |
329 | }; | |
330 | ||
331 | /* The Rx and Tx buffer descriptors. */ | |
332 | struct rx_desc { | |
53c03f5c AV |
333 | __le32 rx_status; |
334 | __le32 desc_length; /* Chain flag, Buffer/frame length */ | |
335 | __le32 addr; | |
336 | __le32 next_desc; | |
1da177e4 LT |
337 | }; |
338 | struct tx_desc { | |
53c03f5c AV |
339 | __le32 tx_status; |
340 | __le32 desc_length; /* Chain flag, Tx Config, Frame length */ | |
341 | __le32 addr; | |
342 | __le32 next_desc; | |
1da177e4 LT |
343 | }; |
344 | ||
345 | /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */ | |
346 | #define TXDESC 0x00e08000 | |
347 | ||
348 | enum rx_status_bits { | |
349 | RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F | |
350 | }; | |
351 | ||
352 | /* Bits in *_desc.*_status */ | |
353 | enum desc_status_bits { | |
354 | DescOwn=0x80000000 | |
355 | }; | |
356 | ||
357 | /* Bits in ChipCmd. */ | |
358 | enum chip_cmd_bits { | |
359 | CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08, | |
360 | CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40, | |
361 | Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04, | |
362 | Cmd1NoTxPoll=0x08, Cmd1Reset=0x80, | |
363 | }; | |
364 | ||
365 | struct rhine_private { | |
366 | /* Descriptor rings */ | |
367 | struct rx_desc *rx_ring; | |
368 | struct tx_desc *tx_ring; | |
369 | dma_addr_t rx_ring_dma; | |
370 | dma_addr_t tx_ring_dma; | |
371 | ||
372 | /* The addresses of receive-in-place skbuffs. */ | |
373 | struct sk_buff *rx_skbuff[RX_RING_SIZE]; | |
374 | dma_addr_t rx_skbuff_dma[RX_RING_SIZE]; | |
375 | ||
376 | /* The saved address of a sent-in-place packet/buffer, for later free(). */ | |
377 | struct sk_buff *tx_skbuff[TX_RING_SIZE]; | |
378 | dma_addr_t tx_skbuff_dma[TX_RING_SIZE]; | |
379 | ||
4be5de25 | 380 | /* Tx bounce buffers (Rhine-I only) */ |
1da177e4 LT |
381 | unsigned char *tx_buf[TX_RING_SIZE]; |
382 | unsigned char *tx_bufs; | |
383 | dma_addr_t tx_bufs_dma; | |
384 | ||
385 | struct pci_dev *pdev; | |
386 | long pioaddr; | |
bea3348e SH |
387 | struct net_device *dev; |
388 | struct napi_struct napi; | |
1da177e4 LT |
389 | struct net_device_stats stats; |
390 | spinlock_t lock; | |
391 | ||
392 | /* Frequently used values: keep some adjacent for cache effect. */ | |
393 | u32 quirks; | |
394 | struct rx_desc *rx_head_desc; | |
395 | unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */ | |
396 | unsigned int cur_tx, dirty_tx; | |
397 | unsigned int rx_buf_sz; /* Based on MTU+slack. */ | |
398 | u8 wolopts; | |
399 | ||
400 | u8 tx_thresh, rx_thresh; | |
401 | ||
402 | struct mii_if_info mii_if; | |
403 | void __iomem *base; | |
404 | }; | |
405 | ||
406 | static int mdio_read(struct net_device *dev, int phy_id, int location); | |
407 | static void mdio_write(struct net_device *dev, int phy_id, int location, int value); | |
408 | static int rhine_open(struct net_device *dev); | |
409 | static void rhine_tx_timeout(struct net_device *dev); | |
410 | static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev); | |
7d12e780 | 411 | static irqreturn_t rhine_interrupt(int irq, void *dev_instance); |
1da177e4 | 412 | static void rhine_tx(struct net_device *dev); |
633949a1 | 413 | static int rhine_rx(struct net_device *dev, int limit); |
1da177e4 LT |
414 | static void rhine_error(struct net_device *dev, int intr_status); |
415 | static void rhine_set_rx_mode(struct net_device *dev); | |
416 | static struct net_device_stats *rhine_get_stats(struct net_device *dev); | |
417 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
7282d491 | 418 | static const struct ethtool_ops netdev_ethtool_ops; |
1da177e4 | 419 | static int rhine_close(struct net_device *dev); |
d18c3db5 | 420 | static void rhine_shutdown (struct pci_dev *pdev); |
1da177e4 LT |
421 | |
422 | #define RHINE_WAIT_FOR(condition) do { \ | |
423 | int i=1024; \ | |
424 | while (!(condition) && --i) \ | |
425 | ; \ | |
426 | if (debug > 1 && i < 512) \ | |
427 | printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \ | |
428 | DRV_NAME, 1024-i, __func__, __LINE__); \ | |
429 | } while(0) | |
430 | ||
431 | static inline u32 get_intr_status(struct net_device *dev) | |
432 | { | |
433 | struct rhine_private *rp = netdev_priv(dev); | |
434 | void __iomem *ioaddr = rp->base; | |
435 | u32 intr_status; | |
436 | ||
437 | intr_status = ioread16(ioaddr + IntrStatus); | |
438 | /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */ | |
439 | if (rp->quirks & rqStatusWBRace) | |
440 | intr_status |= ioread8(ioaddr + IntrStatus2) << 16; | |
441 | return intr_status; | |
442 | } | |
443 | ||
444 | /* | |
445 | * Get power related registers into sane state. | |
446 | * Notify user about past WOL event. | |
447 | */ | |
448 | static void rhine_power_init(struct net_device *dev) | |
449 | { | |
450 | struct rhine_private *rp = netdev_priv(dev); | |
451 | void __iomem *ioaddr = rp->base; | |
452 | u16 wolstat; | |
453 | ||
454 | if (rp->quirks & rqWOL) { | |
455 | /* Make sure chip is in power state D0 */ | |
456 | iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW); | |
457 | ||
458 | /* Disable "force PME-enable" */ | |
459 | iowrite8(0x80, ioaddr + WOLcgClr); | |
460 | ||
461 | /* Clear power-event config bits (WOL) */ | |
462 | iowrite8(0xFF, ioaddr + WOLcrClr); | |
463 | /* More recent cards can manage two additional patterns */ | |
464 | if (rp->quirks & rq6patterns) | |
465 | iowrite8(0x03, ioaddr + WOLcrClr1); | |
466 | ||
467 | /* Save power-event status bits */ | |
468 | wolstat = ioread8(ioaddr + PwrcsrSet); | |
469 | if (rp->quirks & rq6patterns) | |
470 | wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8; | |
471 | ||
472 | /* Clear power-event status bits */ | |
473 | iowrite8(0xFF, ioaddr + PwrcsrClr); | |
474 | if (rp->quirks & rq6patterns) | |
475 | iowrite8(0x03, ioaddr + PwrcsrClr1); | |
476 | ||
477 | if (wolstat) { | |
478 | char *reason; | |
479 | switch (wolstat) { | |
480 | case WOLmagic: | |
481 | reason = "Magic packet"; | |
482 | break; | |
483 | case WOLlnkon: | |
484 | reason = "Link went up"; | |
485 | break; | |
486 | case WOLlnkoff: | |
487 | reason = "Link went down"; | |
488 | break; | |
489 | case WOLucast: | |
490 | reason = "Unicast packet"; | |
491 | break; | |
492 | case WOLbmcast: | |
493 | reason = "Multicast/broadcast packet"; | |
494 | break; | |
495 | default: | |
496 | reason = "Unknown"; | |
497 | } | |
498 | printk(KERN_INFO "%s: Woke system up. Reason: %s.\n", | |
499 | DRV_NAME, reason); | |
500 | } | |
501 | } | |
502 | } | |
503 | ||
504 | static void rhine_chip_reset(struct net_device *dev) | |
505 | { | |
506 | struct rhine_private *rp = netdev_priv(dev); | |
507 | void __iomem *ioaddr = rp->base; | |
508 | ||
509 | iowrite8(Cmd1Reset, ioaddr + ChipCmd1); | |
510 | IOSYNC; | |
511 | ||
512 | if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) { | |
513 | printk(KERN_INFO "%s: Reset not complete yet. " | |
514 | "Trying harder.\n", DRV_NAME); | |
515 | ||
516 | /* Force reset */ | |
517 | if (rp->quirks & rqForceReset) | |
518 | iowrite8(0x40, ioaddr + MiscCmd); | |
519 | ||
520 | /* Reset can take somewhat longer (rare) */ | |
521 | RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset)); | |
522 | } | |
523 | ||
524 | if (debug > 1) | |
525 | printk(KERN_INFO "%s: Reset %s.\n", dev->name, | |
526 | (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ? | |
527 | "failed" : "succeeded"); | |
528 | } | |
529 | ||
530 | #ifdef USE_MMIO | |
531 | static void enable_mmio(long pioaddr, u32 quirks) | |
532 | { | |
533 | int n; | |
534 | if (quirks & rqRhineI) { | |
535 | /* More recent docs say that this bit is reserved ... */ | |
536 | n = inb(pioaddr + ConfigA) | 0x20; | |
537 | outb(n, pioaddr + ConfigA); | |
538 | } else { | |
539 | n = inb(pioaddr + ConfigD) | 0x80; | |
540 | outb(n, pioaddr + ConfigD); | |
541 | } | |
542 | } | |
543 | #endif | |
544 | ||
545 | /* | |
546 | * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM | |
547 | * (plus 0x6C for Rhine-I/II) | |
548 | */ | |
549 | static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev) | |
550 | { | |
551 | struct rhine_private *rp = netdev_priv(dev); | |
552 | void __iomem *ioaddr = rp->base; | |
553 | ||
554 | outb(0x20, pioaddr + MACRegEEcsr); | |
555 | RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20)); | |
556 | ||
557 | #ifdef USE_MMIO | |
558 | /* | |
559 | * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable | |
560 | * MMIO. If reloading EEPROM was done first this could be avoided, but | |
561 | * it is not known if that still works with the "win98-reboot" problem. | |
562 | */ | |
563 | enable_mmio(pioaddr, rp->quirks); | |
564 | #endif | |
565 | ||
566 | /* Turn off EEPROM-controlled wake-up (magic packet) */ | |
567 | if (rp->quirks & rqWOL) | |
568 | iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA); | |
569 | ||
570 | } | |
571 | ||
572 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
573 | static void rhine_poll(struct net_device *dev) | |
574 | { | |
575 | disable_irq(dev->irq); | |
7d12e780 | 576 | rhine_interrupt(dev->irq, (void *)dev); |
1da177e4 LT |
577 | enable_irq(dev->irq); |
578 | } | |
579 | #endif | |
580 | ||
bea3348e | 581 | static int rhine_napipoll(struct napi_struct *napi, int budget) |
633949a1 | 582 | { |
bea3348e SH |
583 | struct rhine_private *rp = container_of(napi, struct rhine_private, napi); |
584 | struct net_device *dev = rp->dev; | |
633949a1 | 585 | void __iomem *ioaddr = rp->base; |
bea3348e | 586 | int work_done; |
633949a1 | 587 | |
bea3348e | 588 | work_done = rhine_rx(dev, budget); |
633949a1 | 589 | |
bea3348e SH |
590 | if (work_done < budget) { |
591 | netif_rx_complete(dev, napi); | |
633949a1 RL |
592 | |
593 | iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | | |
594 | IntrRxDropped | IntrRxNoBuf | IntrTxAborted | | |
595 | IntrTxDone | IntrTxError | IntrTxUnderrun | | |
596 | IntrPCIErr | IntrStatsMax | IntrLinkChange, | |
597 | ioaddr + IntrEnable); | |
633949a1 | 598 | } |
bea3348e | 599 | return work_done; |
633949a1 | 600 | } |
633949a1 | 601 | |
de4e7c88 | 602 | static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr) |
1da177e4 LT |
603 | { |
604 | struct rhine_private *rp = netdev_priv(dev); | |
605 | ||
606 | /* Reset the chip to erase previous misconfiguration. */ | |
607 | rhine_chip_reset(dev); | |
608 | ||
609 | /* Rhine-I needs extra time to recuperate before EEPROM reload */ | |
610 | if (rp->quirks & rqRhineI) | |
611 | msleep(5); | |
612 | ||
613 | /* Reload EEPROM controlled bytes cleared by soft reset */ | |
614 | rhine_reload_eeprom(pioaddr, dev); | |
615 | } | |
616 | ||
5d1d07d8 SH |
617 | static const struct net_device_ops rhine_netdev_ops = { |
618 | .ndo_open = rhine_open, | |
619 | .ndo_stop = rhine_close, | |
620 | .ndo_start_xmit = rhine_start_tx, | |
621 | .ndo_get_stats = rhine_get_stats, | |
622 | .ndo_set_multicast_list = rhine_set_rx_mode, | |
623 | .ndo_validate_addr = eth_validate_addr, | |
624 | .ndo_do_ioctl = netdev_ioctl, | |
625 | .ndo_tx_timeout = rhine_tx_timeout, | |
626 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
627 | .ndo_poll_controller = rhine_poll, | |
628 | #endif | |
629 | }; | |
630 | ||
1da177e4 LT |
631 | static int __devinit rhine_init_one(struct pci_dev *pdev, |
632 | const struct pci_device_id *ent) | |
633 | { | |
634 | struct net_device *dev; | |
635 | struct rhine_private *rp; | |
636 | int i, rc; | |
1da177e4 LT |
637 | u32 quirks; |
638 | long pioaddr; | |
639 | long memaddr; | |
640 | void __iomem *ioaddr; | |
641 | int io_size, phy_id; | |
642 | const char *name; | |
643 | #ifdef USE_MMIO | |
644 | int bar = 1; | |
645 | #else | |
646 | int bar = 0; | |
647 | #endif | |
648 | ||
649 | /* when built into the kernel, we only print version if device is found */ | |
650 | #ifndef MODULE | |
651 | static int printed_version; | |
652 | if (!printed_version++) | |
653 | printk(version); | |
654 | #endif | |
655 | ||
1da177e4 LT |
656 | io_size = 256; |
657 | phy_id = 0; | |
658 | quirks = 0; | |
659 | name = "Rhine"; | |
44c10138 | 660 | if (pdev->revision < VTunknown0) { |
1da177e4 LT |
661 | quirks = rqRhineI; |
662 | io_size = 128; | |
663 | } | |
44c10138 | 664 | else if (pdev->revision >= VT6102) { |
1da177e4 | 665 | quirks = rqWOL | rqForceReset; |
44c10138 | 666 | if (pdev->revision < VT6105) { |
1da177e4 LT |
667 | name = "Rhine II"; |
668 | quirks |= rqStatusWBRace; /* Rhine-II exclusive */ | |
669 | } | |
670 | else { | |
671 | phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */ | |
44c10138 | 672 | if (pdev->revision >= VT6105_B0) |
1da177e4 | 673 | quirks |= rq6patterns; |
44c10138 | 674 | if (pdev->revision < VT6105M) |
1da177e4 LT |
675 | name = "Rhine III"; |
676 | else | |
677 | name = "Rhine III (Management Adapter)"; | |
678 | } | |
679 | } | |
680 | ||
681 | rc = pci_enable_device(pdev); | |
682 | if (rc) | |
683 | goto err_out; | |
684 | ||
685 | /* this should always be supported */ | |
1e7f0bd8 | 686 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
1da177e4 LT |
687 | if (rc) { |
688 | printk(KERN_ERR "32-bit PCI DMA addresses not supported by " | |
689 | "the card!?\n"); | |
690 | goto err_out; | |
691 | } | |
692 | ||
693 | /* sanity check */ | |
694 | if ((pci_resource_len(pdev, 0) < io_size) || | |
695 | (pci_resource_len(pdev, 1) < io_size)) { | |
696 | rc = -EIO; | |
697 | printk(KERN_ERR "Insufficient PCI resources, aborting\n"); | |
698 | goto err_out; | |
699 | } | |
700 | ||
701 | pioaddr = pci_resource_start(pdev, 0); | |
702 | memaddr = pci_resource_start(pdev, 1); | |
703 | ||
704 | pci_set_master(pdev); | |
705 | ||
706 | dev = alloc_etherdev(sizeof(struct rhine_private)); | |
707 | if (!dev) { | |
708 | rc = -ENOMEM; | |
709 | printk(KERN_ERR "alloc_etherdev failed\n"); | |
710 | goto err_out; | |
711 | } | |
1da177e4 LT |
712 | SET_NETDEV_DEV(dev, &pdev->dev); |
713 | ||
714 | rp = netdev_priv(dev); | |
bea3348e | 715 | rp->dev = dev; |
1da177e4 LT |
716 | rp->quirks = quirks; |
717 | rp->pioaddr = pioaddr; | |
718 | rp->pdev = pdev; | |
719 | ||
720 | rc = pci_request_regions(pdev, DRV_NAME); | |
721 | if (rc) | |
722 | goto err_out_free_netdev; | |
723 | ||
724 | ioaddr = pci_iomap(pdev, bar, io_size); | |
725 | if (!ioaddr) { | |
726 | rc = -EIO; | |
727 | printk(KERN_ERR "ioremap failed for device %s, region 0x%X " | |
728 | "@ 0x%lX\n", pci_name(pdev), io_size, memaddr); | |
729 | goto err_out_free_res; | |
730 | } | |
731 | ||
732 | #ifdef USE_MMIO | |
733 | enable_mmio(pioaddr, quirks); | |
734 | ||
735 | /* Check that selected MMIO registers match the PIO ones */ | |
736 | i = 0; | |
737 | while (mmio_verify_registers[i]) { | |
738 | int reg = mmio_verify_registers[i++]; | |
739 | unsigned char a = inb(pioaddr+reg); | |
740 | unsigned char b = readb(ioaddr+reg); | |
741 | if (a != b) { | |
742 | rc = -EIO; | |
743 | printk(KERN_ERR "MMIO do not match PIO [%02x] " | |
744 | "(%02x != %02x)\n", reg, a, b); | |
745 | goto err_out_unmap; | |
746 | } | |
747 | } | |
748 | #endif /* USE_MMIO */ | |
749 | ||
750 | dev->base_addr = (unsigned long)ioaddr; | |
751 | rp->base = ioaddr; | |
752 | ||
753 | /* Get chip registers into a sane state */ | |
754 | rhine_power_init(dev); | |
755 | rhine_hw_init(dev, pioaddr); | |
756 | ||
757 | for (i = 0; i < 6; i++) | |
758 | dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i); | |
b81e8e1f | 759 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 760 | |
b81e8e1f | 761 | if (!is_valid_ether_addr(dev->perm_addr)) { |
1da177e4 LT |
762 | rc = -EIO; |
763 | printk(KERN_ERR "Invalid MAC address\n"); | |
764 | goto err_out_unmap; | |
765 | } | |
766 | ||
767 | /* For Rhine-I/II, phy_id is loaded from EEPROM */ | |
768 | if (!phy_id) | |
769 | phy_id = ioread8(ioaddr + 0x6C); | |
770 | ||
771 | dev->irq = pdev->irq; | |
772 | ||
773 | spin_lock_init(&rp->lock); | |
774 | rp->mii_if.dev = dev; | |
775 | rp->mii_if.mdio_read = mdio_read; | |
776 | rp->mii_if.mdio_write = mdio_write; | |
777 | rp->mii_if.phy_id_mask = 0x1f; | |
778 | rp->mii_if.reg_num_mask = 0x1f; | |
779 | ||
780 | /* The chip-specific entries in the device structure. */ | |
5d1d07d8 SH |
781 | dev->netdev_ops = &rhine_netdev_ops; |
782 | dev->ethtool_ops = &netdev_ethtool_ops, | |
1da177e4 | 783 | dev->watchdog_timeo = TX_TIMEOUT; |
5d1d07d8 | 784 | |
bea3348e | 785 | netif_napi_add(dev, &rp->napi, rhine_napipoll, 64); |
32b0f53e | 786 | |
1da177e4 LT |
787 | if (rp->quirks & rqRhineI) |
788 | dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM; | |
789 | ||
790 | /* dev->name not defined before register_netdev()! */ | |
791 | rc = register_netdev(dev); | |
792 | if (rc) | |
793 | goto err_out_unmap; | |
794 | ||
e174961c | 795 | printk(KERN_INFO "%s: VIA %s at 0x%lx, %pM, IRQ %d.\n", |
1da177e4 LT |
796 | dev->name, name, |
797 | #ifdef USE_MMIO | |
0795af57 | 798 | memaddr, |
1da177e4 | 799 | #else |
0795af57 | 800 | (long)ioaddr, |
1da177e4 | 801 | #endif |
e174961c | 802 | dev->dev_addr, pdev->irq); |
1da177e4 LT |
803 | |
804 | pci_set_drvdata(pdev, dev); | |
805 | ||
806 | { | |
807 | u16 mii_cmd; | |
808 | int mii_status = mdio_read(dev, phy_id, 1); | |
809 | mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE; | |
810 | mdio_write(dev, phy_id, MII_BMCR, mii_cmd); | |
811 | if (mii_status != 0xffff && mii_status != 0x0000) { | |
812 | rp->mii_if.advertising = mdio_read(dev, phy_id, 4); | |
813 | printk(KERN_INFO "%s: MII PHY found at address " | |
814 | "%d, status 0x%4.4x advertising %4.4x " | |
815 | "Link %4.4x.\n", dev->name, phy_id, | |
816 | mii_status, rp->mii_if.advertising, | |
817 | mdio_read(dev, phy_id, 5)); | |
818 | ||
819 | /* set IFF_RUNNING */ | |
820 | if (mii_status & BMSR_LSTATUS) | |
821 | netif_carrier_on(dev); | |
822 | else | |
823 | netif_carrier_off(dev); | |
824 | ||
825 | } | |
826 | } | |
827 | rp->mii_if.phy_id = phy_id; | |
b933b4d9 RL |
828 | if (debug > 1 && avoid_D3) |
829 | printk(KERN_INFO "%s: No D3 power state at shutdown.\n", | |
830 | dev->name); | |
1da177e4 LT |
831 | |
832 | return 0; | |
833 | ||
834 | err_out_unmap: | |
835 | pci_iounmap(pdev, ioaddr); | |
836 | err_out_free_res: | |
837 | pci_release_regions(pdev); | |
838 | err_out_free_netdev: | |
839 | free_netdev(dev); | |
840 | err_out: | |
841 | return rc; | |
842 | } | |
843 | ||
844 | static int alloc_ring(struct net_device* dev) | |
845 | { | |
846 | struct rhine_private *rp = netdev_priv(dev); | |
847 | void *ring; | |
848 | dma_addr_t ring_dma; | |
849 | ||
850 | ring = pci_alloc_consistent(rp->pdev, | |
851 | RX_RING_SIZE * sizeof(struct rx_desc) + | |
852 | TX_RING_SIZE * sizeof(struct tx_desc), | |
853 | &ring_dma); | |
854 | if (!ring) { | |
855 | printk(KERN_ERR "Could not allocate DMA memory.\n"); | |
856 | return -ENOMEM; | |
857 | } | |
858 | if (rp->quirks & rqRhineI) { | |
859 | rp->tx_bufs = pci_alloc_consistent(rp->pdev, | |
860 | PKT_BUF_SZ * TX_RING_SIZE, | |
861 | &rp->tx_bufs_dma); | |
862 | if (rp->tx_bufs == NULL) { | |
863 | pci_free_consistent(rp->pdev, | |
864 | RX_RING_SIZE * sizeof(struct rx_desc) + | |
865 | TX_RING_SIZE * sizeof(struct tx_desc), | |
866 | ring, ring_dma); | |
867 | return -ENOMEM; | |
868 | } | |
869 | } | |
870 | ||
871 | rp->rx_ring = ring; | |
872 | rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc); | |
873 | rp->rx_ring_dma = ring_dma; | |
874 | rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc); | |
875 | ||
876 | return 0; | |
877 | } | |
878 | ||
879 | static void free_ring(struct net_device* dev) | |
880 | { | |
881 | struct rhine_private *rp = netdev_priv(dev); | |
882 | ||
883 | pci_free_consistent(rp->pdev, | |
884 | RX_RING_SIZE * sizeof(struct rx_desc) + | |
885 | TX_RING_SIZE * sizeof(struct tx_desc), | |
886 | rp->rx_ring, rp->rx_ring_dma); | |
887 | rp->tx_ring = NULL; | |
888 | ||
889 | if (rp->tx_bufs) | |
890 | pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE, | |
891 | rp->tx_bufs, rp->tx_bufs_dma); | |
892 | ||
893 | rp->tx_bufs = NULL; | |
894 | ||
895 | } | |
896 | ||
897 | static void alloc_rbufs(struct net_device *dev) | |
898 | { | |
899 | struct rhine_private *rp = netdev_priv(dev); | |
900 | dma_addr_t next; | |
901 | int i; | |
902 | ||
903 | rp->dirty_rx = rp->cur_rx = 0; | |
904 | ||
905 | rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); | |
906 | rp->rx_head_desc = &rp->rx_ring[0]; | |
907 | next = rp->rx_ring_dma; | |
908 | ||
909 | /* Init the ring entries */ | |
910 | for (i = 0; i < RX_RING_SIZE; i++) { | |
911 | rp->rx_ring[i].rx_status = 0; | |
912 | rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz); | |
913 | next += sizeof(struct rx_desc); | |
914 | rp->rx_ring[i].next_desc = cpu_to_le32(next); | |
915 | rp->rx_skbuff[i] = NULL; | |
916 | } | |
917 | /* Mark the last entry as wrapping the ring. */ | |
918 | rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma); | |
919 | ||
920 | /* Fill in the Rx buffers. Handle allocation failure gracefully. */ | |
921 | for (i = 0; i < RX_RING_SIZE; i++) { | |
b26b555a | 922 | struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz); |
1da177e4 LT |
923 | rp->rx_skbuff[i] = skb; |
924 | if (skb == NULL) | |
925 | break; | |
926 | skb->dev = dev; /* Mark as being used by this device. */ | |
927 | ||
928 | rp->rx_skbuff_dma[i] = | |
689be439 | 929 | pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz, |
1da177e4 LT |
930 | PCI_DMA_FROMDEVICE); |
931 | ||
932 | rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]); | |
933 | rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn); | |
934 | } | |
935 | rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE); | |
936 | } | |
937 | ||
938 | static void free_rbufs(struct net_device* dev) | |
939 | { | |
940 | struct rhine_private *rp = netdev_priv(dev); | |
941 | int i; | |
942 | ||
943 | /* Free all the skbuffs in the Rx queue. */ | |
944 | for (i = 0; i < RX_RING_SIZE; i++) { | |
945 | rp->rx_ring[i].rx_status = 0; | |
946 | rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ | |
947 | if (rp->rx_skbuff[i]) { | |
948 | pci_unmap_single(rp->pdev, | |
949 | rp->rx_skbuff_dma[i], | |
950 | rp->rx_buf_sz, PCI_DMA_FROMDEVICE); | |
951 | dev_kfree_skb(rp->rx_skbuff[i]); | |
952 | } | |
953 | rp->rx_skbuff[i] = NULL; | |
954 | } | |
955 | } | |
956 | ||
957 | static void alloc_tbufs(struct net_device* dev) | |
958 | { | |
959 | struct rhine_private *rp = netdev_priv(dev); | |
960 | dma_addr_t next; | |
961 | int i; | |
962 | ||
963 | rp->dirty_tx = rp->cur_tx = 0; | |
964 | next = rp->tx_ring_dma; | |
965 | for (i = 0; i < TX_RING_SIZE; i++) { | |
966 | rp->tx_skbuff[i] = NULL; | |
967 | rp->tx_ring[i].tx_status = 0; | |
968 | rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); | |
969 | next += sizeof(struct tx_desc); | |
970 | rp->tx_ring[i].next_desc = cpu_to_le32(next); | |
4be5de25 RL |
971 | if (rp->quirks & rqRhineI) |
972 | rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ]; | |
1da177e4 LT |
973 | } |
974 | rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma); | |
975 | ||
976 | } | |
977 | ||
978 | static void free_tbufs(struct net_device* dev) | |
979 | { | |
980 | struct rhine_private *rp = netdev_priv(dev); | |
981 | int i; | |
982 | ||
983 | for (i = 0; i < TX_RING_SIZE; i++) { | |
984 | rp->tx_ring[i].tx_status = 0; | |
985 | rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); | |
986 | rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ | |
987 | if (rp->tx_skbuff[i]) { | |
988 | if (rp->tx_skbuff_dma[i]) { | |
989 | pci_unmap_single(rp->pdev, | |
990 | rp->tx_skbuff_dma[i], | |
991 | rp->tx_skbuff[i]->len, | |
992 | PCI_DMA_TODEVICE); | |
993 | } | |
994 | dev_kfree_skb(rp->tx_skbuff[i]); | |
995 | } | |
996 | rp->tx_skbuff[i] = NULL; | |
997 | rp->tx_buf[i] = NULL; | |
998 | } | |
999 | } | |
1000 | ||
1001 | static void rhine_check_media(struct net_device *dev, unsigned int init_media) | |
1002 | { | |
1003 | struct rhine_private *rp = netdev_priv(dev); | |
1004 | void __iomem *ioaddr = rp->base; | |
1005 | ||
1006 | mii_check_media(&rp->mii_if, debug, init_media); | |
1007 | ||
1008 | if (rp->mii_if.full_duplex) | |
1009 | iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex, | |
1010 | ioaddr + ChipCmd1); | |
1011 | else | |
1012 | iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex, | |
1013 | ioaddr + ChipCmd1); | |
00b428c2 RL |
1014 | if (debug > 1) |
1015 | printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name, | |
1016 | rp->mii_if.force_media, netif_carrier_ok(dev)); | |
1017 | } | |
1018 | ||
1019 | /* Called after status of force_media possibly changed */ | |
0761be4f | 1020 | static void rhine_set_carrier(struct mii_if_info *mii) |
00b428c2 RL |
1021 | { |
1022 | if (mii->force_media) { | |
1023 | /* autoneg is off: Link is always assumed to be up */ | |
1024 | if (!netif_carrier_ok(mii->dev)) | |
1025 | netif_carrier_on(mii->dev); | |
1026 | } | |
1027 | else /* Let MMI library update carrier status */ | |
1028 | rhine_check_media(mii->dev, 0); | |
1029 | if (debug > 1) | |
1030 | printk(KERN_INFO "%s: force_media %d, carrier %d\n", | |
1031 | mii->dev->name, mii->force_media, | |
1032 | netif_carrier_ok(mii->dev)); | |
1da177e4 LT |
1033 | } |
1034 | ||
1035 | static void init_registers(struct net_device *dev) | |
1036 | { | |
1037 | struct rhine_private *rp = netdev_priv(dev); | |
1038 | void __iomem *ioaddr = rp->base; | |
1039 | int i; | |
1040 | ||
1041 | for (i = 0; i < 6; i++) | |
1042 | iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); | |
1043 | ||
1044 | /* Initialize other registers. */ | |
1045 | iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */ | |
1046 | /* Configure initial FIFO thresholds. */ | |
1047 | iowrite8(0x20, ioaddr + TxConfig); | |
1048 | rp->tx_thresh = 0x20; | |
1049 | rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */ | |
1050 | ||
1051 | iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr); | |
1052 | iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr); | |
1053 | ||
1054 | rhine_set_rx_mode(dev); | |
1055 | ||
bea3348e | 1056 | napi_enable(&rp->napi); |
ab197668 | 1057 | |
1da177e4 LT |
1058 | /* Enable interrupts by setting the interrupt mask. */ |
1059 | iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | | |
1060 | IntrRxDropped | IntrRxNoBuf | IntrTxAborted | | |
1061 | IntrTxDone | IntrTxError | IntrTxUnderrun | | |
1062 | IntrPCIErr | IntrStatsMax | IntrLinkChange, | |
1063 | ioaddr + IntrEnable); | |
1064 | ||
1065 | iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8), | |
1066 | ioaddr + ChipCmd); | |
1067 | rhine_check_media(dev, 1); | |
1068 | } | |
1069 | ||
1070 | /* Enable MII link status auto-polling (required for IntrLinkChange) */ | |
1071 | static void rhine_enable_linkmon(void __iomem *ioaddr) | |
1072 | { | |
1073 | iowrite8(0, ioaddr + MIICmd); | |
1074 | iowrite8(MII_BMSR, ioaddr + MIIRegAddr); | |
1075 | iowrite8(0x80, ioaddr + MIICmd); | |
1076 | ||
1077 | RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20)); | |
1078 | ||
1079 | iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr); | |
1080 | } | |
1081 | ||
1082 | /* Disable MII link status auto-polling (required for MDIO access) */ | |
1083 | static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks) | |
1084 | { | |
1085 | iowrite8(0, ioaddr + MIICmd); | |
1086 | ||
1087 | if (quirks & rqRhineI) { | |
1088 | iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR | |
1089 | ||
38bb6b28 JL |
1090 | /* Can be called from ISR. Evil. */ |
1091 | mdelay(1); | |
1da177e4 LT |
1092 | |
1093 | /* 0x80 must be set immediately before turning it off */ | |
1094 | iowrite8(0x80, ioaddr + MIICmd); | |
1095 | ||
1096 | RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20); | |
1097 | ||
1098 | /* Heh. Now clear 0x80 again. */ | |
1099 | iowrite8(0, ioaddr + MIICmd); | |
1100 | } | |
1101 | else | |
1102 | RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80); | |
1103 | } | |
1104 | ||
1105 | /* Read and write over the MII Management Data I/O (MDIO) interface. */ | |
1106 | ||
1107 | static int mdio_read(struct net_device *dev, int phy_id, int regnum) | |
1108 | { | |
1109 | struct rhine_private *rp = netdev_priv(dev); | |
1110 | void __iomem *ioaddr = rp->base; | |
1111 | int result; | |
1112 | ||
1113 | rhine_disable_linkmon(ioaddr, rp->quirks); | |
1114 | ||
1115 | /* rhine_disable_linkmon already cleared MIICmd */ | |
1116 | iowrite8(phy_id, ioaddr + MIIPhyAddr); | |
1117 | iowrite8(regnum, ioaddr + MIIRegAddr); | |
1118 | iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */ | |
1119 | RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40)); | |
1120 | result = ioread16(ioaddr + MIIData); | |
1121 | ||
1122 | rhine_enable_linkmon(ioaddr); | |
1123 | return result; | |
1124 | } | |
1125 | ||
1126 | static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value) | |
1127 | { | |
1128 | struct rhine_private *rp = netdev_priv(dev); | |
1129 | void __iomem *ioaddr = rp->base; | |
1130 | ||
1131 | rhine_disable_linkmon(ioaddr, rp->quirks); | |
1132 | ||
1133 | /* rhine_disable_linkmon already cleared MIICmd */ | |
1134 | iowrite8(phy_id, ioaddr + MIIPhyAddr); | |
1135 | iowrite8(regnum, ioaddr + MIIRegAddr); | |
1136 | iowrite16(value, ioaddr + MIIData); | |
1137 | iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */ | |
1138 | RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20)); | |
1139 | ||
1140 | rhine_enable_linkmon(ioaddr); | |
1141 | } | |
1142 | ||
1143 | static int rhine_open(struct net_device *dev) | |
1144 | { | |
1145 | struct rhine_private *rp = netdev_priv(dev); | |
1146 | void __iomem *ioaddr = rp->base; | |
1147 | int rc; | |
1148 | ||
1fb9df5d | 1149 | rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name, |
1da177e4 LT |
1150 | dev); |
1151 | if (rc) | |
1152 | return rc; | |
1153 | ||
1154 | if (debug > 1) | |
1155 | printk(KERN_DEBUG "%s: rhine_open() irq %d.\n", | |
1156 | dev->name, rp->pdev->irq); | |
1157 | ||
1158 | rc = alloc_ring(dev); | |
1159 | if (rc) { | |
1160 | free_irq(rp->pdev->irq, dev); | |
1161 | return rc; | |
1162 | } | |
1163 | alloc_rbufs(dev); | |
1164 | alloc_tbufs(dev); | |
1165 | rhine_chip_reset(dev); | |
1166 | init_registers(dev); | |
1167 | if (debug > 2) | |
1168 | printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x " | |
1169 | "MII status: %4.4x.\n", | |
1170 | dev->name, ioread16(ioaddr + ChipCmd), | |
1171 | mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); | |
1172 | ||
1173 | netif_start_queue(dev); | |
1174 | ||
1175 | return 0; | |
1176 | } | |
1177 | ||
1178 | static void rhine_tx_timeout(struct net_device *dev) | |
1179 | { | |
1180 | struct rhine_private *rp = netdev_priv(dev); | |
1181 | void __iomem *ioaddr = rp->base; | |
1182 | ||
1183 | printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status " | |
1184 | "%4.4x, resetting...\n", | |
1185 | dev->name, ioread16(ioaddr + IntrStatus), | |
1186 | mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); | |
1187 | ||
1188 | /* protect against concurrent rx interrupts */ | |
1189 | disable_irq(rp->pdev->irq); | |
1190 | ||
bea3348e | 1191 | napi_disable(&rp->napi); |
bea3348e | 1192 | |
1da177e4 LT |
1193 | spin_lock(&rp->lock); |
1194 | ||
1195 | /* clear all descriptors */ | |
1196 | free_tbufs(dev); | |
1197 | free_rbufs(dev); | |
1198 | alloc_tbufs(dev); | |
1199 | alloc_rbufs(dev); | |
1200 | ||
1201 | /* Reinitialize the hardware. */ | |
1202 | rhine_chip_reset(dev); | |
1203 | init_registers(dev); | |
1204 | ||
1205 | spin_unlock(&rp->lock); | |
1206 | enable_irq(rp->pdev->irq); | |
1207 | ||
1208 | dev->trans_start = jiffies; | |
1209 | rp->stats.tx_errors++; | |
1210 | netif_wake_queue(dev); | |
1211 | } | |
1212 | ||
1213 | static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev) | |
1214 | { | |
1215 | struct rhine_private *rp = netdev_priv(dev); | |
1216 | void __iomem *ioaddr = rp->base; | |
1217 | unsigned entry; | |
1218 | ||
1219 | /* Caution: the write order is important here, set the field | |
1220 | with the "ownership" bits last. */ | |
1221 | ||
1222 | /* Calculate the next Tx descriptor entry. */ | |
1223 | entry = rp->cur_tx % TX_RING_SIZE; | |
1224 | ||
5b057c6b HX |
1225 | if (skb_padto(skb, ETH_ZLEN)) |
1226 | return 0; | |
1da177e4 LT |
1227 | |
1228 | rp->tx_skbuff[entry] = skb; | |
1229 | ||
1230 | if ((rp->quirks & rqRhineI) && | |
84fa7933 | 1231 | (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) { |
1da177e4 LT |
1232 | /* Must use alignment buffer. */ |
1233 | if (skb->len > PKT_BUF_SZ) { | |
1234 | /* packet too long, drop it */ | |
1235 | dev_kfree_skb(skb); | |
1236 | rp->tx_skbuff[entry] = NULL; | |
1237 | rp->stats.tx_dropped++; | |
1238 | return 0; | |
1239 | } | |
3e0d167a CB |
1240 | |
1241 | /* Padding is not copied and so must be redone. */ | |
1da177e4 | 1242 | skb_copy_and_csum_dev(skb, rp->tx_buf[entry]); |
3e0d167a CB |
1243 | if (skb->len < ETH_ZLEN) |
1244 | memset(rp->tx_buf[entry] + skb->len, 0, | |
1245 | ETH_ZLEN - skb->len); | |
1da177e4 LT |
1246 | rp->tx_skbuff_dma[entry] = 0; |
1247 | rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma + | |
1248 | (rp->tx_buf[entry] - | |
1249 | rp->tx_bufs)); | |
1250 | } else { | |
1251 | rp->tx_skbuff_dma[entry] = | |
1252 | pci_map_single(rp->pdev, skb->data, skb->len, | |
1253 | PCI_DMA_TODEVICE); | |
1254 | rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]); | |
1255 | } | |
1256 | ||
1257 | rp->tx_ring[entry].desc_length = | |
1258 | cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN)); | |
1259 | ||
1260 | /* lock eth irq */ | |
1261 | spin_lock_irq(&rp->lock); | |
1262 | wmb(); | |
1263 | rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn); | |
1264 | wmb(); | |
1265 | ||
1266 | rp->cur_tx++; | |
1267 | ||
1268 | /* Non-x86 Todo: explicitly flush cache lines here. */ | |
1269 | ||
1270 | /* Wake the potentially-idle transmit channel */ | |
1271 | iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, | |
1272 | ioaddr + ChipCmd1); | |
1273 | IOSYNC; | |
1274 | ||
1275 | if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN) | |
1276 | netif_stop_queue(dev); | |
1277 | ||
1278 | dev->trans_start = jiffies; | |
1279 | ||
1280 | spin_unlock_irq(&rp->lock); | |
1281 | ||
1282 | if (debug > 4) { | |
1283 | printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n", | |
1284 | dev->name, rp->cur_tx-1, entry); | |
1285 | } | |
1286 | return 0; | |
1287 | } | |
1288 | ||
1289 | /* The interrupt handler does all of the Rx thread work and cleans up | |
1290 | after the Tx thread. */ | |
7d12e780 | 1291 | static irqreturn_t rhine_interrupt(int irq, void *dev_instance) |
1da177e4 LT |
1292 | { |
1293 | struct net_device *dev = dev_instance; | |
1294 | struct rhine_private *rp = netdev_priv(dev); | |
1295 | void __iomem *ioaddr = rp->base; | |
1296 | u32 intr_status; | |
1297 | int boguscnt = max_interrupt_work; | |
1298 | int handled = 0; | |
1299 | ||
1300 | while ((intr_status = get_intr_status(dev))) { | |
1301 | handled = 1; | |
1302 | ||
1303 | /* Acknowledge all of the current interrupt sources ASAP. */ | |
1304 | if (intr_status & IntrTxDescRace) | |
1305 | iowrite8(0x08, ioaddr + IntrStatus2); | |
1306 | iowrite16(intr_status & 0xffff, ioaddr + IntrStatus); | |
1307 | IOSYNC; | |
1308 | ||
1309 | if (debug > 4) | |
1310 | printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n", | |
1311 | dev->name, intr_status); | |
1312 | ||
1313 | if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped | | |
633949a1 | 1314 | IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) { |
633949a1 RL |
1315 | iowrite16(IntrTxAborted | |
1316 | IntrTxDone | IntrTxError | IntrTxUnderrun | | |
1317 | IntrPCIErr | IntrStatsMax | IntrLinkChange, | |
1318 | ioaddr + IntrEnable); | |
1319 | ||
bea3348e | 1320 | netif_rx_schedule(dev, &rp->napi); |
633949a1 | 1321 | } |
1da177e4 LT |
1322 | |
1323 | if (intr_status & (IntrTxErrSummary | IntrTxDone)) { | |
1324 | if (intr_status & IntrTxErrSummary) { | |
1325 | /* Avoid scavenging before Tx engine turned off */ | |
1326 | RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn)); | |
1327 | if (debug > 2 && | |
1328 | ioread8(ioaddr+ChipCmd) & CmdTxOn) | |
1329 | printk(KERN_WARNING "%s: " | |
2450022a | 1330 | "rhine_interrupt() Tx engine " |
1da177e4 LT |
1331 | "still on.\n", dev->name); |
1332 | } | |
1333 | rhine_tx(dev); | |
1334 | } | |
1335 | ||
1336 | /* Abnormal error summary/uncommon events handlers. */ | |
1337 | if (intr_status & (IntrPCIErr | IntrLinkChange | | |
1338 | IntrStatsMax | IntrTxError | IntrTxAborted | | |
1339 | IntrTxUnderrun | IntrTxDescRace)) | |
1340 | rhine_error(dev, intr_status); | |
1341 | ||
1342 | if (--boguscnt < 0) { | |
1343 | printk(KERN_WARNING "%s: Too much work at interrupt, " | |
1344 | "status=%#8.8x.\n", | |
1345 | dev->name, intr_status); | |
1346 | break; | |
1347 | } | |
1348 | } | |
1349 | ||
1350 | if (debug > 3) | |
1351 | printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n", | |
1352 | dev->name, ioread16(ioaddr + IntrStatus)); | |
1353 | return IRQ_RETVAL(handled); | |
1354 | } | |
1355 | ||
1356 | /* This routine is logically part of the interrupt handler, but isolated | |
1357 | for clarity. */ | |
1358 | static void rhine_tx(struct net_device *dev) | |
1359 | { | |
1360 | struct rhine_private *rp = netdev_priv(dev); | |
1361 | int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE; | |
1362 | ||
1363 | spin_lock(&rp->lock); | |
1364 | ||
1365 | /* find and cleanup dirty tx descriptors */ | |
1366 | while (rp->dirty_tx != rp->cur_tx) { | |
1367 | txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status); | |
1368 | if (debug > 6) | |
ed4030d1 | 1369 | printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n", |
1da177e4 LT |
1370 | entry, txstatus); |
1371 | if (txstatus & DescOwn) | |
1372 | break; | |
1373 | if (txstatus & 0x8000) { | |
1374 | if (debug > 1) | |
1375 | printk(KERN_DEBUG "%s: Transmit error, " | |
1376 | "Tx status %8.8x.\n", | |
1377 | dev->name, txstatus); | |
1378 | rp->stats.tx_errors++; | |
1379 | if (txstatus & 0x0400) rp->stats.tx_carrier_errors++; | |
1380 | if (txstatus & 0x0200) rp->stats.tx_window_errors++; | |
1381 | if (txstatus & 0x0100) rp->stats.tx_aborted_errors++; | |
1382 | if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++; | |
1383 | if (((rp->quirks & rqRhineI) && txstatus & 0x0002) || | |
1384 | (txstatus & 0x0800) || (txstatus & 0x1000)) { | |
1385 | rp->stats.tx_fifo_errors++; | |
1386 | rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn); | |
1387 | break; /* Keep the skb - we try again */ | |
1388 | } | |
1389 | /* Transmitter restarted in 'abnormal' handler. */ | |
1390 | } else { | |
1391 | if (rp->quirks & rqRhineI) | |
1392 | rp->stats.collisions += (txstatus >> 3) & 0x0F; | |
1393 | else | |
1394 | rp->stats.collisions += txstatus & 0x0F; | |
1395 | if (debug > 6) | |
1396 | printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n", | |
1397 | (txstatus >> 3) & 0xF, | |
1398 | txstatus & 0xF); | |
1399 | rp->stats.tx_bytes += rp->tx_skbuff[entry]->len; | |
1400 | rp->stats.tx_packets++; | |
1401 | } | |
1402 | /* Free the original skb. */ | |
1403 | if (rp->tx_skbuff_dma[entry]) { | |
1404 | pci_unmap_single(rp->pdev, | |
1405 | rp->tx_skbuff_dma[entry], | |
1406 | rp->tx_skbuff[entry]->len, | |
1407 | PCI_DMA_TODEVICE); | |
1408 | } | |
1409 | dev_kfree_skb_irq(rp->tx_skbuff[entry]); | |
1410 | rp->tx_skbuff[entry] = NULL; | |
1411 | entry = (++rp->dirty_tx) % TX_RING_SIZE; | |
1412 | } | |
1413 | if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4) | |
1414 | netif_wake_queue(dev); | |
1415 | ||
1416 | spin_unlock(&rp->lock); | |
1417 | } | |
1418 | ||
633949a1 RL |
1419 | /* Process up to limit frames from receive ring */ |
1420 | static int rhine_rx(struct net_device *dev, int limit) | |
1da177e4 LT |
1421 | { |
1422 | struct rhine_private *rp = netdev_priv(dev); | |
633949a1 | 1423 | int count; |
1da177e4 | 1424 | int entry = rp->cur_rx % RX_RING_SIZE; |
1da177e4 LT |
1425 | |
1426 | if (debug > 4) { | |
1427 | printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n", | |
1428 | dev->name, entry, | |
1429 | le32_to_cpu(rp->rx_head_desc->rx_status)); | |
1430 | } | |
1431 | ||
1432 | /* If EOP is set on the next entry, it's a new packet. Send it up. */ | |
633949a1 | 1433 | for (count = 0; count < limit; ++count) { |
1da177e4 LT |
1434 | struct rx_desc *desc = rp->rx_head_desc; |
1435 | u32 desc_status = le32_to_cpu(desc->rx_status); | |
1436 | int data_size = desc_status >> 16; | |
1437 | ||
633949a1 RL |
1438 | if (desc_status & DescOwn) |
1439 | break; | |
1440 | ||
1da177e4 | 1441 | if (debug > 4) |
ed4030d1 | 1442 | printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n", |
1da177e4 | 1443 | desc_status); |
633949a1 | 1444 | |
1da177e4 LT |
1445 | if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) { |
1446 | if ((desc_status & RxWholePkt) != RxWholePkt) { | |
1447 | printk(KERN_WARNING "%s: Oversized Ethernet " | |
1448 | "frame spanned multiple buffers, entry " | |
1449 | "%#x length %d status %8.8x!\n", | |
1450 | dev->name, entry, data_size, | |
1451 | desc_status); | |
1452 | printk(KERN_WARNING "%s: Oversized Ethernet " | |
1453 | "frame %p vs %p.\n", dev->name, | |
1454 | rp->rx_head_desc, &rp->rx_ring[entry]); | |
1455 | rp->stats.rx_length_errors++; | |
1456 | } else if (desc_status & RxErr) { | |
1457 | /* There was a error. */ | |
1458 | if (debug > 2) | |
ed4030d1 | 1459 | printk(KERN_DEBUG "rhine_rx() Rx " |
1da177e4 LT |
1460 | "error was %8.8x.\n", |
1461 | desc_status); | |
1462 | rp->stats.rx_errors++; | |
1463 | if (desc_status & 0x0030) rp->stats.rx_length_errors++; | |
1464 | if (desc_status & 0x0048) rp->stats.rx_fifo_errors++; | |
1465 | if (desc_status & 0x0004) rp->stats.rx_frame_errors++; | |
1466 | if (desc_status & 0x0002) { | |
1467 | /* this can also be updated outside the interrupt handler */ | |
1468 | spin_lock(&rp->lock); | |
1469 | rp->stats.rx_crc_errors++; | |
1470 | spin_unlock(&rp->lock); | |
1471 | } | |
1472 | } | |
1473 | } else { | |
1474 | struct sk_buff *skb; | |
1475 | /* Length should omit the CRC */ | |
1476 | int pkt_len = data_size - 4; | |
1477 | ||
1478 | /* Check if the packet is long enough to accept without | |
1479 | copying to a minimally-sized skbuff. */ | |
1480 | if (pkt_len < rx_copybreak && | |
b26b555a KL |
1481 | (skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN)) != NULL) { |
1482 | skb_reserve(skb, NET_IP_ALIGN); /* 16 byte align the IP header */ | |
1da177e4 LT |
1483 | pci_dma_sync_single_for_cpu(rp->pdev, |
1484 | rp->rx_skbuff_dma[entry], | |
1485 | rp->rx_buf_sz, | |
1486 | PCI_DMA_FROMDEVICE); | |
1487 | ||
8c7b7faa | 1488 | skb_copy_to_linear_data(skb, |
689be439 | 1489 | rp->rx_skbuff[entry]->data, |
8c7b7faa | 1490 | pkt_len); |
1da177e4 LT |
1491 | skb_put(skb, pkt_len); |
1492 | pci_dma_sync_single_for_device(rp->pdev, | |
1493 | rp->rx_skbuff_dma[entry], | |
1494 | rp->rx_buf_sz, | |
1495 | PCI_DMA_FROMDEVICE); | |
1496 | } else { | |
1497 | skb = rp->rx_skbuff[entry]; | |
1498 | if (skb == NULL) { | |
1499 | printk(KERN_ERR "%s: Inconsistent Rx " | |
1500 | "descriptor chain.\n", | |
1501 | dev->name); | |
1502 | break; | |
1503 | } | |
1504 | rp->rx_skbuff[entry] = NULL; | |
1505 | skb_put(skb, pkt_len); | |
1506 | pci_unmap_single(rp->pdev, | |
1507 | rp->rx_skbuff_dma[entry], | |
1508 | rp->rx_buf_sz, | |
1509 | PCI_DMA_FROMDEVICE); | |
1510 | } | |
1511 | skb->protocol = eth_type_trans(skb, dev); | |
633949a1 | 1512 | netif_receive_skb(skb); |
1da177e4 LT |
1513 | rp->stats.rx_bytes += pkt_len; |
1514 | rp->stats.rx_packets++; | |
1515 | } | |
1516 | entry = (++rp->cur_rx) % RX_RING_SIZE; | |
1517 | rp->rx_head_desc = &rp->rx_ring[entry]; | |
1518 | } | |
1519 | ||
1520 | /* Refill the Rx ring buffers. */ | |
1521 | for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) { | |
1522 | struct sk_buff *skb; | |
1523 | entry = rp->dirty_rx % RX_RING_SIZE; | |
1524 | if (rp->rx_skbuff[entry] == NULL) { | |
b26b555a | 1525 | skb = netdev_alloc_skb(dev, rp->rx_buf_sz); |
1da177e4 LT |
1526 | rp->rx_skbuff[entry] = skb; |
1527 | if (skb == NULL) | |
1528 | break; /* Better luck next round. */ | |
1529 | skb->dev = dev; /* Mark as being used by this device. */ | |
1530 | rp->rx_skbuff_dma[entry] = | |
689be439 | 1531 | pci_map_single(rp->pdev, skb->data, |
1da177e4 LT |
1532 | rp->rx_buf_sz, |
1533 | PCI_DMA_FROMDEVICE); | |
1534 | rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]); | |
1535 | } | |
1536 | rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn); | |
1537 | } | |
633949a1 RL |
1538 | |
1539 | return count; | |
1da177e4 LT |
1540 | } |
1541 | ||
1542 | /* | |
1543 | * Clears the "tally counters" for CRC errors and missed frames(?). | |
1544 | * It has been reported that some chips need a write of 0 to clear | |
1545 | * these, for others the counters are set to 1 when written to and | |
1546 | * instead cleared when read. So we clear them both ways ... | |
1547 | */ | |
1548 | static inline void clear_tally_counters(void __iomem *ioaddr) | |
1549 | { | |
1550 | iowrite32(0, ioaddr + RxMissed); | |
1551 | ioread16(ioaddr + RxCRCErrs); | |
1552 | ioread16(ioaddr + RxMissed); | |
1553 | } | |
1554 | ||
1555 | static void rhine_restart_tx(struct net_device *dev) { | |
1556 | struct rhine_private *rp = netdev_priv(dev); | |
1557 | void __iomem *ioaddr = rp->base; | |
1558 | int entry = rp->dirty_tx % TX_RING_SIZE; | |
1559 | u32 intr_status; | |
1560 | ||
1561 | /* | |
1562 | * If new errors occured, we need to sort them out before doing Tx. | |
1563 | * In that case the ISR will be back here RSN anyway. | |
1564 | */ | |
1565 | intr_status = get_intr_status(dev); | |
1566 | ||
1567 | if ((intr_status & IntrTxErrSummary) == 0) { | |
1568 | ||
1569 | /* We know better than the chip where it should continue. */ | |
1570 | iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc), | |
1571 | ioaddr + TxRingPtr); | |
1572 | ||
1573 | iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn, | |
1574 | ioaddr + ChipCmd); | |
1575 | iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, | |
1576 | ioaddr + ChipCmd1); | |
1577 | IOSYNC; | |
1578 | } | |
1579 | else { | |
1580 | /* This should never happen */ | |
1581 | if (debug > 1) | |
1582 | printk(KERN_WARNING "%s: rhine_restart_tx() " | |
1583 | "Another error occured %8.8x.\n", | |
1584 | dev->name, intr_status); | |
1585 | } | |
1586 | ||
1587 | } | |
1588 | ||
1589 | static void rhine_error(struct net_device *dev, int intr_status) | |
1590 | { | |
1591 | struct rhine_private *rp = netdev_priv(dev); | |
1592 | void __iomem *ioaddr = rp->base; | |
1593 | ||
1594 | spin_lock(&rp->lock); | |
1595 | ||
1596 | if (intr_status & IntrLinkChange) | |
38bb6b28 | 1597 | rhine_check_media(dev, 0); |
1da177e4 LT |
1598 | if (intr_status & IntrStatsMax) { |
1599 | rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs); | |
1600 | rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed); | |
1601 | clear_tally_counters(ioaddr); | |
1602 | } | |
1603 | if (intr_status & IntrTxAborted) { | |
1604 | if (debug > 1) | |
1605 | printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n", | |
1606 | dev->name, intr_status); | |
1607 | } | |
1608 | if (intr_status & IntrTxUnderrun) { | |
1609 | if (rp->tx_thresh < 0xE0) | |
1610 | iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig); | |
1611 | if (debug > 1) | |
1612 | printk(KERN_INFO "%s: Transmitter underrun, Tx " | |
1613 | "threshold now %2.2x.\n", | |
1614 | dev->name, rp->tx_thresh); | |
1615 | } | |
1616 | if (intr_status & IntrTxDescRace) { | |
1617 | if (debug > 2) | |
1618 | printk(KERN_INFO "%s: Tx descriptor write-back race.\n", | |
1619 | dev->name); | |
1620 | } | |
1621 | if ((intr_status & IntrTxError) && | |
1622 | (intr_status & (IntrTxAborted | | |
1623 | IntrTxUnderrun | IntrTxDescRace)) == 0) { | |
1624 | if (rp->tx_thresh < 0xE0) { | |
1625 | iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig); | |
1626 | } | |
1627 | if (debug > 1) | |
1628 | printk(KERN_INFO "%s: Unspecified error. Tx " | |
1629 | "threshold now %2.2x.\n", | |
1630 | dev->name, rp->tx_thresh); | |
1631 | } | |
1632 | if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace | | |
1633 | IntrTxError)) | |
1634 | rhine_restart_tx(dev); | |
1635 | ||
1636 | if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun | | |
1637 | IntrTxError | IntrTxAborted | IntrNormalSummary | | |
1638 | IntrTxDescRace)) { | |
1639 | if (debug > 1) | |
1640 | printk(KERN_ERR "%s: Something Wicked happened! " | |
1641 | "%8.8x.\n", dev->name, intr_status); | |
1642 | } | |
1643 | ||
1644 | spin_unlock(&rp->lock); | |
1645 | } | |
1646 | ||
1647 | static struct net_device_stats *rhine_get_stats(struct net_device *dev) | |
1648 | { | |
1649 | struct rhine_private *rp = netdev_priv(dev); | |
1650 | void __iomem *ioaddr = rp->base; | |
1651 | unsigned long flags; | |
1652 | ||
1653 | spin_lock_irqsave(&rp->lock, flags); | |
1654 | rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs); | |
1655 | rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed); | |
1656 | clear_tally_counters(ioaddr); | |
1657 | spin_unlock_irqrestore(&rp->lock, flags); | |
1658 | ||
1659 | return &rp->stats; | |
1660 | } | |
1661 | ||
1662 | static void rhine_set_rx_mode(struct net_device *dev) | |
1663 | { | |
1664 | struct rhine_private *rp = netdev_priv(dev); | |
1665 | void __iomem *ioaddr = rp->base; | |
1666 | u32 mc_filter[2]; /* Multicast hash filter */ | |
1667 | u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */ | |
1668 | ||
1669 | if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ | |
1da177e4 LT |
1670 | rx_mode = 0x1C; |
1671 | iowrite32(0xffffffff, ioaddr + MulticastFilter0); | |
1672 | iowrite32(0xffffffff, ioaddr + MulticastFilter1); | |
1673 | } else if ((dev->mc_count > multicast_filter_limit) | |
1674 | || (dev->flags & IFF_ALLMULTI)) { | |
1675 | /* Too many to match, or accept all multicasts. */ | |
1676 | iowrite32(0xffffffff, ioaddr + MulticastFilter0); | |
1677 | iowrite32(0xffffffff, ioaddr + MulticastFilter1); | |
1678 | rx_mode = 0x0C; | |
1679 | } else { | |
1680 | struct dev_mc_list *mclist; | |
1681 | int i; | |
1682 | memset(mc_filter, 0, sizeof(mc_filter)); | |
1683 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
1684 | i++, mclist = mclist->next) { | |
1685 | int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; | |
1686 | ||
1687 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1688 | } | |
1689 | iowrite32(mc_filter[0], ioaddr + MulticastFilter0); | |
1690 | iowrite32(mc_filter[1], ioaddr + MulticastFilter1); | |
1691 | rx_mode = 0x0C; | |
1692 | } | |
1693 | iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig); | |
1694 | } | |
1695 | ||
1696 | static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | |
1697 | { | |
1698 | struct rhine_private *rp = netdev_priv(dev); | |
1699 | ||
1700 | strcpy(info->driver, DRV_NAME); | |
1701 | strcpy(info->version, DRV_VERSION); | |
1702 | strcpy(info->bus_info, pci_name(rp->pdev)); | |
1703 | } | |
1704 | ||
1705 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1706 | { | |
1707 | struct rhine_private *rp = netdev_priv(dev); | |
1708 | int rc; | |
1709 | ||
1710 | spin_lock_irq(&rp->lock); | |
1711 | rc = mii_ethtool_gset(&rp->mii_if, cmd); | |
1712 | spin_unlock_irq(&rp->lock); | |
1713 | ||
1714 | return rc; | |
1715 | } | |
1716 | ||
1717 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1718 | { | |
1719 | struct rhine_private *rp = netdev_priv(dev); | |
1720 | int rc; | |
1721 | ||
1722 | spin_lock_irq(&rp->lock); | |
1723 | rc = mii_ethtool_sset(&rp->mii_if, cmd); | |
1724 | spin_unlock_irq(&rp->lock); | |
00b428c2 | 1725 | rhine_set_carrier(&rp->mii_if); |
1da177e4 LT |
1726 | |
1727 | return rc; | |
1728 | } | |
1729 | ||
1730 | static int netdev_nway_reset(struct net_device *dev) | |
1731 | { | |
1732 | struct rhine_private *rp = netdev_priv(dev); | |
1733 | ||
1734 | return mii_nway_restart(&rp->mii_if); | |
1735 | } | |
1736 | ||
1737 | static u32 netdev_get_link(struct net_device *dev) | |
1738 | { | |
1739 | struct rhine_private *rp = netdev_priv(dev); | |
1740 | ||
1741 | return mii_link_ok(&rp->mii_if); | |
1742 | } | |
1743 | ||
1744 | static u32 netdev_get_msglevel(struct net_device *dev) | |
1745 | { | |
1746 | return debug; | |
1747 | } | |
1748 | ||
1749 | static void netdev_set_msglevel(struct net_device *dev, u32 value) | |
1750 | { | |
1751 | debug = value; | |
1752 | } | |
1753 | ||
1754 | static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1755 | { | |
1756 | struct rhine_private *rp = netdev_priv(dev); | |
1757 | ||
1758 | if (!(rp->quirks & rqWOL)) | |
1759 | return; | |
1760 | ||
1761 | spin_lock_irq(&rp->lock); | |
1762 | wol->supported = WAKE_PHY | WAKE_MAGIC | | |
1763 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */ | |
1764 | wol->wolopts = rp->wolopts; | |
1765 | spin_unlock_irq(&rp->lock); | |
1766 | } | |
1767 | ||
1768 | static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1769 | { | |
1770 | struct rhine_private *rp = netdev_priv(dev); | |
1771 | u32 support = WAKE_PHY | WAKE_MAGIC | | |
1772 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */ | |
1773 | ||
1774 | if (!(rp->quirks & rqWOL)) | |
1775 | return -EINVAL; | |
1776 | ||
1777 | if (wol->wolopts & ~support) | |
1778 | return -EINVAL; | |
1779 | ||
1780 | spin_lock_irq(&rp->lock); | |
1781 | rp->wolopts = wol->wolopts; | |
1782 | spin_unlock_irq(&rp->lock); | |
1783 | ||
1784 | return 0; | |
1785 | } | |
1786 | ||
7282d491 | 1787 | static const struct ethtool_ops netdev_ethtool_ops = { |
1da177e4 LT |
1788 | .get_drvinfo = netdev_get_drvinfo, |
1789 | .get_settings = netdev_get_settings, | |
1790 | .set_settings = netdev_set_settings, | |
1791 | .nway_reset = netdev_nway_reset, | |
1792 | .get_link = netdev_get_link, | |
1793 | .get_msglevel = netdev_get_msglevel, | |
1794 | .set_msglevel = netdev_set_msglevel, | |
1795 | .get_wol = rhine_get_wol, | |
1796 | .set_wol = rhine_set_wol, | |
1da177e4 LT |
1797 | }; |
1798 | ||
1799 | static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
1800 | { | |
1801 | struct rhine_private *rp = netdev_priv(dev); | |
1802 | int rc; | |
1803 | ||
1804 | if (!netif_running(dev)) | |
1805 | return -EINVAL; | |
1806 | ||
1807 | spin_lock_irq(&rp->lock); | |
1808 | rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL); | |
1809 | spin_unlock_irq(&rp->lock); | |
00b428c2 | 1810 | rhine_set_carrier(&rp->mii_if); |
1da177e4 LT |
1811 | |
1812 | return rc; | |
1813 | } | |
1814 | ||
1815 | static int rhine_close(struct net_device *dev) | |
1816 | { | |
1817 | struct rhine_private *rp = netdev_priv(dev); | |
1818 | void __iomem *ioaddr = rp->base; | |
1819 | ||
1820 | spin_lock_irq(&rp->lock); | |
1821 | ||
1822 | netif_stop_queue(dev); | |
bea3348e | 1823 | napi_disable(&rp->napi); |
1da177e4 LT |
1824 | |
1825 | if (debug > 1) | |
1826 | printk(KERN_DEBUG "%s: Shutting down ethercard, " | |
1827 | "status was %4.4x.\n", | |
1828 | dev->name, ioread16(ioaddr + ChipCmd)); | |
1829 | ||
1830 | /* Switch to loopback mode to avoid hardware races. */ | |
1831 | iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig); | |
1832 | ||
1833 | /* Disable interrupts by clearing the interrupt mask. */ | |
1834 | iowrite16(0x0000, ioaddr + IntrEnable); | |
1835 | ||
1836 | /* Stop the chip's Tx and Rx processes. */ | |
1837 | iowrite16(CmdStop, ioaddr + ChipCmd); | |
1838 | ||
1839 | spin_unlock_irq(&rp->lock); | |
1840 | ||
1841 | free_irq(rp->pdev->irq, dev); | |
1842 | free_rbufs(dev); | |
1843 | free_tbufs(dev); | |
1844 | free_ring(dev); | |
1845 | ||
1846 | return 0; | |
1847 | } | |
1848 | ||
1849 | ||
1850 | static void __devexit rhine_remove_one(struct pci_dev *pdev) | |
1851 | { | |
1852 | struct net_device *dev = pci_get_drvdata(pdev); | |
1853 | struct rhine_private *rp = netdev_priv(dev); | |
1854 | ||
1855 | unregister_netdev(dev); | |
1856 | ||
1857 | pci_iounmap(pdev, rp->base); | |
1858 | pci_release_regions(pdev); | |
1859 | ||
1860 | free_netdev(dev); | |
1861 | pci_disable_device(pdev); | |
1862 | pci_set_drvdata(pdev, NULL); | |
1863 | } | |
1864 | ||
d18c3db5 | 1865 | static void rhine_shutdown (struct pci_dev *pdev) |
1da177e4 | 1866 | { |
1da177e4 LT |
1867 | struct net_device *dev = pci_get_drvdata(pdev); |
1868 | struct rhine_private *rp = netdev_priv(dev); | |
1869 | void __iomem *ioaddr = rp->base; | |
1870 | ||
1871 | if (!(rp->quirks & rqWOL)) | |
1872 | return; /* Nothing to do for non-WOL adapters */ | |
1873 | ||
1874 | rhine_power_init(dev); | |
1875 | ||
1876 | /* Make sure we use pattern 0, 1 and not 4, 5 */ | |
1877 | if (rp->quirks & rq6patterns) | |
f11cf25e | 1878 | iowrite8(0x04, ioaddr + WOLcgClr); |
1da177e4 LT |
1879 | |
1880 | if (rp->wolopts & WAKE_MAGIC) { | |
1881 | iowrite8(WOLmagic, ioaddr + WOLcrSet); | |
1882 | /* | |
1883 | * Turn EEPROM-controlled wake-up back on -- some hardware may | |
1884 | * not cooperate otherwise. | |
1885 | */ | |
1886 | iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA); | |
1887 | } | |
1888 | ||
1889 | if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST)) | |
1890 | iowrite8(WOLbmcast, ioaddr + WOLcgSet); | |
1891 | ||
1892 | if (rp->wolopts & WAKE_PHY) | |
1893 | iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet); | |
1894 | ||
1895 | if (rp->wolopts & WAKE_UCAST) | |
1896 | iowrite8(WOLucast, ioaddr + WOLcrSet); | |
1897 | ||
1898 | if (rp->wolopts) { | |
1899 | /* Enable legacy WOL (for old motherboards) */ | |
1900 | iowrite8(0x01, ioaddr + PwcfgSet); | |
1901 | iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW); | |
1902 | } | |
1903 | ||
1904 | /* Hit power state D3 (sleep) */ | |
b933b4d9 RL |
1905 | if (!avoid_D3) |
1906 | iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW); | |
1da177e4 LT |
1907 | |
1908 | /* TODO: Check use of pci_enable_wake() */ | |
1909 | ||
1910 | } | |
1911 | ||
1912 | #ifdef CONFIG_PM | |
1913 | static int rhine_suspend(struct pci_dev *pdev, pm_message_t state) | |
1914 | { | |
1915 | struct net_device *dev = pci_get_drvdata(pdev); | |
1916 | struct rhine_private *rp = netdev_priv(dev); | |
1917 | unsigned long flags; | |
1918 | ||
1919 | if (!netif_running(dev)) | |
1920 | return 0; | |
1921 | ||
bea3348e | 1922 | napi_disable(&rp->napi); |
32b0f53e | 1923 | |
1da177e4 LT |
1924 | netif_device_detach(dev); |
1925 | pci_save_state(pdev); | |
1926 | ||
1927 | spin_lock_irqsave(&rp->lock, flags); | |
d18c3db5 | 1928 | rhine_shutdown(pdev); |
1da177e4 LT |
1929 | spin_unlock_irqrestore(&rp->lock, flags); |
1930 | ||
1931 | free_irq(dev->irq, dev); | |
1932 | return 0; | |
1933 | } | |
1934 | ||
1935 | static int rhine_resume(struct pci_dev *pdev) | |
1936 | { | |
1937 | struct net_device *dev = pci_get_drvdata(pdev); | |
1938 | struct rhine_private *rp = netdev_priv(dev); | |
1939 | unsigned long flags; | |
1940 | int ret; | |
1941 | ||
1942 | if (!netif_running(dev)) | |
1943 | return 0; | |
1944 | ||
1fb9df5d | 1945 | if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev)) |
1da177e4 LT |
1946 | printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name); |
1947 | ||
1948 | ret = pci_set_power_state(pdev, PCI_D0); | |
1949 | if (debug > 1) | |
1950 | printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n", | |
1951 | dev->name, ret ? "failed" : "succeeded", ret); | |
1952 | ||
1953 | pci_restore_state(pdev); | |
1954 | ||
1955 | spin_lock_irqsave(&rp->lock, flags); | |
1956 | #ifdef USE_MMIO | |
1957 | enable_mmio(rp->pioaddr, rp->quirks); | |
1958 | #endif | |
1959 | rhine_power_init(dev); | |
1960 | free_tbufs(dev); | |
1961 | free_rbufs(dev); | |
1962 | alloc_tbufs(dev); | |
1963 | alloc_rbufs(dev); | |
1964 | init_registers(dev); | |
1965 | spin_unlock_irqrestore(&rp->lock, flags); | |
1966 | ||
1967 | netif_device_attach(dev); | |
1968 | ||
1969 | return 0; | |
1970 | } | |
1971 | #endif /* CONFIG_PM */ | |
1972 | ||
1973 | static struct pci_driver rhine_driver = { | |
1974 | .name = DRV_NAME, | |
1975 | .id_table = rhine_pci_tbl, | |
1976 | .probe = rhine_init_one, | |
1977 | .remove = __devexit_p(rhine_remove_one), | |
1978 | #ifdef CONFIG_PM | |
1979 | .suspend = rhine_suspend, | |
1980 | .resume = rhine_resume, | |
1981 | #endif /* CONFIG_PM */ | |
d18c3db5 | 1982 | .shutdown = rhine_shutdown, |
1da177e4 LT |
1983 | }; |
1984 | ||
e84df485 RL |
1985 | static struct dmi_system_id __initdata rhine_dmi_table[] = { |
1986 | { | |
1987 | .ident = "EPIA-M", | |
1988 | .matches = { | |
1989 | DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."), | |
1990 | DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"), | |
1991 | }, | |
1992 | }, | |
1993 | { | |
1994 | .ident = "KV7", | |
1995 | .matches = { | |
1996 | DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"), | |
1997 | DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"), | |
1998 | }, | |
1999 | }, | |
2000 | { NULL } | |
2001 | }; | |
1da177e4 LT |
2002 | |
2003 | static int __init rhine_init(void) | |
2004 | { | |
2005 | /* when a module, this is printed whether or not devices are found in probe */ | |
2006 | #ifdef MODULE | |
2007 | printk(version); | |
2008 | #endif | |
e84df485 RL |
2009 | if (dmi_check_system(rhine_dmi_table)) { |
2010 | /* these BIOSes fail at PXE boot if chip is in D3 */ | |
2011 | avoid_D3 = 1; | |
2012 | printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 " | |
2013 | "enabled.\n", | |
2014 | DRV_NAME); | |
2015 | } | |
2016 | else if (avoid_D3) | |
2017 | printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME); | |
2018 | ||
29917620 | 2019 | return pci_register_driver(&rhine_driver); |
1da177e4 LT |
2020 | } |
2021 | ||
2022 | ||
2023 | static void __exit rhine_cleanup(void) | |
2024 | { | |
2025 | pci_unregister_driver(&rhine_driver); | |
2026 | } | |
2027 | ||
2028 | ||
2029 | module_init(rhine_init); | |
2030 | module_exit(rhine_cleanup); |