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d1a890fa SB |
1 | /* |
2 | * Linux driver for VMware's vmxnet3 ethernet NIC. | |
3 | * | |
45dac1d6 | 4 | * Copyright (C) 2008-2015, VMware, Inc. All Rights Reserved. |
d1a890fa SB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; version 2 of the License and no later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
13 | * NON INFRINGEMENT. See the GNU General Public License for more | |
14 | * details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution in | |
21 | * the file called "COPYING". | |
22 | * | |
23 | * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com> | |
24 | * | |
25 | */ | |
26 | ||
27 | #ifndef _VMXNET3_DEFS_H_ | |
28 | #define _VMXNET3_DEFS_H_ | |
29 | ||
30 | #include "upt1_defs.h" | |
31 | ||
32 | /* all registers are 32 bit wide */ | |
33 | /* BAR 1 */ | |
34 | enum { | |
35 | VMXNET3_REG_VRRS = 0x0, /* Vmxnet3 Revision Report Selection */ | |
36 | VMXNET3_REG_UVRS = 0x8, /* UPT Version Report Selection */ | |
37 | VMXNET3_REG_DSAL = 0x10, /* Driver Shared Address Low */ | |
38 | VMXNET3_REG_DSAH = 0x18, /* Driver Shared Address High */ | |
39 | VMXNET3_REG_CMD = 0x20, /* Command */ | |
40 | VMXNET3_REG_MACL = 0x28, /* MAC Address Low */ | |
41 | VMXNET3_REG_MACH = 0x30, /* MAC Address High */ | |
42 | VMXNET3_REG_ICR = 0x38, /* Interrupt Cause Register */ | |
43 | VMXNET3_REG_ECR = 0x40 /* Event Cause Register */ | |
44 | }; | |
45 | ||
46 | /* BAR 0 */ | |
47 | enum { | |
48 | VMXNET3_REG_IMR = 0x0, /* Interrupt Mask Register */ | |
49 | VMXNET3_REG_TXPROD = 0x600, /* Tx Producer Index */ | |
50 | VMXNET3_REG_RXPROD = 0x800, /* Rx Producer Index for ring 1 */ | |
51 | VMXNET3_REG_RXPROD2 = 0xA00 /* Rx Producer Index for ring 2 */ | |
52 | }; | |
53 | ||
54 | #define VMXNET3_PT_REG_SIZE 4096 /* BAR 0 */ | |
55 | #define VMXNET3_VD_REG_SIZE 4096 /* BAR 1 */ | |
56 | ||
57 | #define VMXNET3_REG_ALIGN 8 /* All registers are 8-byte aligned. */ | |
58 | #define VMXNET3_REG_ALIGN_MASK 0x7 | |
59 | ||
60 | /* I/O Mapped access to registers */ | |
61 | #define VMXNET3_IO_TYPE_PT 0 | |
62 | #define VMXNET3_IO_TYPE_VD 1 | |
63 | #define VMXNET3_IO_ADDR(type, reg) (((type) << 24) | ((reg) & 0xFFFFFF)) | |
64 | #define VMXNET3_IO_TYPE(addr) ((addr) >> 24) | |
65 | #define VMXNET3_IO_REG(addr) ((addr) & 0xFFFFFF) | |
66 | ||
67 | enum { | |
68 | VMXNET3_CMD_FIRST_SET = 0xCAFE0000, | |
69 | VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET, | |
70 | VMXNET3_CMD_QUIESCE_DEV, | |
71 | VMXNET3_CMD_RESET_DEV, | |
72 | VMXNET3_CMD_UPDATE_RX_MODE, | |
73 | VMXNET3_CMD_UPDATE_MAC_FILTERS, | |
74 | VMXNET3_CMD_UPDATE_VLAN_FILTERS, | |
75 | VMXNET3_CMD_UPDATE_RSSIDT, | |
76 | VMXNET3_CMD_UPDATE_IML, | |
77 | VMXNET3_CMD_UPDATE_PMCFG, | |
78 | VMXNET3_CMD_UPDATE_FEATURE, | |
79 | VMXNET3_CMD_LOAD_PLUGIN, | |
80 | ||
81 | VMXNET3_CMD_FIRST_GET = 0xF00D0000, | |
82 | VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET, | |
83 | VMXNET3_CMD_GET_STATS, | |
84 | VMXNET3_CMD_GET_LINK, | |
85 | VMXNET3_CMD_GET_PERM_MAC_LO, | |
86 | VMXNET3_CMD_GET_PERM_MAC_HI, | |
87 | VMXNET3_CMD_GET_DID_LO, | |
88 | VMXNET3_CMD_GET_DID_HI, | |
89 | VMXNET3_CMD_GET_DEV_EXTRA_INFO, | |
90 | VMXNET3_CMD_GET_CONF_INTR | |
91 | }; | |
92 | ||
115924b6 SB |
93 | /* |
94 | * Little Endian layout of bitfields - | |
95 | * Byte 0 : 7.....len.....0 | |
96 | * Byte 1 : rsvd gen 13.len.8 | |
97 | * Byte 2 : 5.msscof.0 ext1 dtype | |
98 | * Byte 3 : 13...msscof...6 | |
99 | * | |
100 | * Big Endian layout of bitfields - | |
101 | * Byte 0: 13...msscof...6 | |
102 | * Byte 1 : 5.msscof.0 ext1 dtype | |
103 | * Byte 2 : rsvd gen 13.len.8 | |
104 | * Byte 3 : 7.....len.....0 | |
105 | * | |
106 | * Thus, le32_to_cpu on the dword will allow the big endian driver to read | |
107 | * the bit fields correctly. And cpu_to_le32 will convert bitfields | |
108 | * bit fields written by big endian driver to format required by device. | |
109 | */ | |
d1a890fa | 110 | |
115924b6 SB |
111 | struct Vmxnet3_TxDesc { |
112 | __le64 addr; | |
113 | ||
114 | #ifdef __BIG_ENDIAN_BITFIELD | |
115 | u32 msscof:14; /* MSS, checksum offset, flags */ | |
116 | u32 ext1:1; | |
117 | u32 dtype:1; /* descriptor type */ | |
118 | u32 rsvd:1; | |
119 | u32 gen:1; /* generation bit */ | |
120 | u32 len:14; | |
121 | #else | |
122 | u32 len:14; | |
123 | u32 gen:1; /* generation bit */ | |
124 | u32 rsvd:1; | |
125 | u32 dtype:1; /* descriptor type */ | |
126 | u32 ext1:1; | |
127 | u32 msscof:14; /* MSS, checksum offset, flags */ | |
128 | #endif /* __BIG_ENDIAN_BITFIELD */ | |
129 | ||
130 | #ifdef __BIG_ENDIAN_BITFIELD | |
131 | u32 tci:16; /* Tag to Insert */ | |
132 | u32 ti:1; /* VLAN Tag Insertion */ | |
133 | u32 ext2:1; | |
134 | u32 cq:1; /* completion request */ | |
135 | u32 eop:1; /* End Of Packet */ | |
136 | u32 om:2; /* offload mode */ | |
137 | u32 hlen:10; /* header len */ | |
138 | #else | |
139 | u32 hlen:10; /* header len */ | |
140 | u32 om:2; /* offload mode */ | |
141 | u32 eop:1; /* End Of Packet */ | |
142 | u32 cq:1; /* completion request */ | |
143 | u32 ext2:1; | |
144 | u32 ti:1; /* VLAN Tag Insertion */ | |
145 | u32 tci:16; /* Tag to Insert */ | |
146 | #endif /* __BIG_ENDIAN_BITFIELD */ | |
d1a890fa SB |
147 | }; |
148 | ||
149 | /* TxDesc.OM values */ | |
150 | #define VMXNET3_OM_NONE 0 | |
151 | #define VMXNET3_OM_CSUM 2 | |
152 | #define VMXNET3_OM_TSO 3 | |
153 | ||
154 | /* fields in TxDesc we access w/o using bit fields */ | |
155 | #define VMXNET3_TXD_EOP_SHIFT 12 | |
156 | #define VMXNET3_TXD_CQ_SHIFT 13 | |
157 | #define VMXNET3_TXD_GEN_SHIFT 14 | |
115924b6 SB |
158 | #define VMXNET3_TXD_EOP_DWORD_SHIFT 3 |
159 | #define VMXNET3_TXD_GEN_DWORD_SHIFT 2 | |
d1a890fa SB |
160 | |
161 | #define VMXNET3_TXD_CQ (1 << VMXNET3_TXD_CQ_SHIFT) | |
162 | #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT) | |
163 | #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT) | |
164 | ||
165 | #define VMXNET3_HDR_COPY_SIZE 128 | |
166 | ||
167 | ||
168 | struct Vmxnet3_TxDataDesc { | |
169 | u8 data[VMXNET3_HDR_COPY_SIZE]; | |
170 | }; | |
171 | ||
115924b6 SB |
172 | #define VMXNET3_TCD_GEN_SHIFT 31 |
173 | #define VMXNET3_TCD_GEN_SIZE 1 | |
174 | #define VMXNET3_TCD_TXIDX_SHIFT 0 | |
175 | #define VMXNET3_TCD_TXIDX_SIZE 12 | |
176 | #define VMXNET3_TCD_GEN_DWORD_SHIFT 3 | |
d1a890fa SB |
177 | |
178 | struct Vmxnet3_TxCompDesc { | |
179 | u32 txdIdx:12; /* Index of the EOP TxDesc */ | |
180 | u32 ext1:20; | |
181 | ||
115924b6 SB |
182 | __le32 ext2; |
183 | __le32 ext3; | |
d1a890fa SB |
184 | |
185 | u32 rsvd:24; | |
186 | u32 type:7; /* completion type */ | |
187 | u32 gen:1; /* generation bit */ | |
188 | }; | |
189 | ||
d1a890fa | 190 | struct Vmxnet3_RxDesc { |
115924b6 | 191 | __le64 addr; |
d1a890fa | 192 | |
115924b6 SB |
193 | #ifdef __BIG_ENDIAN_BITFIELD |
194 | u32 gen:1; /* Generation bit */ | |
195 | u32 rsvd:15; | |
196 | u32 dtype:1; /* Descriptor type */ | |
197 | u32 btype:1; /* Buffer Type */ | |
198 | u32 len:14; | |
199 | #else | |
d1a890fa SB |
200 | u32 len:14; |
201 | u32 btype:1; /* Buffer Type */ | |
202 | u32 dtype:1; /* Descriptor type */ | |
203 | u32 rsvd:15; | |
204 | u32 gen:1; /* Generation bit */ | |
115924b6 | 205 | #endif |
d1a890fa SB |
206 | u32 ext1; |
207 | }; | |
208 | ||
209 | /* values of RXD.BTYPE */ | |
210 | #define VMXNET3_RXD_BTYPE_HEAD 0 /* head only */ | |
211 | #define VMXNET3_RXD_BTYPE_BODY 1 /* body only */ | |
212 | ||
213 | /* fields in RxDesc we access w/o using bit fields */ | |
214 | #define VMXNET3_RXD_BTYPE_SHIFT 14 | |
215 | #define VMXNET3_RXD_GEN_SHIFT 31 | |
216 | ||
d1a890fa | 217 | struct Vmxnet3_RxCompDesc { |
115924b6 SB |
218 | #ifdef __BIG_ENDIAN_BITFIELD |
219 | u32 ext2:1; | |
220 | u32 cnc:1; /* Checksum Not Calculated */ | |
221 | u32 rssType:4; /* RSS hash type used */ | |
222 | u32 rqID:10; /* rx queue/ring ID */ | |
223 | u32 sop:1; /* Start of Packet */ | |
224 | u32 eop:1; /* End of Packet */ | |
225 | u32 ext1:2; | |
226 | u32 rxdIdx:12; /* Index of the RxDesc */ | |
227 | #else | |
d1a890fa SB |
228 | u32 rxdIdx:12; /* Index of the RxDesc */ |
229 | u32 ext1:2; | |
230 | u32 eop:1; /* End of Packet */ | |
231 | u32 sop:1; /* Start of Packet */ | |
232 | u32 rqID:10; /* rx queue/ring ID */ | |
233 | u32 rssType:4; /* RSS hash type used */ | |
234 | u32 cnc:1; /* Checksum Not Calculated */ | |
235 | u32 ext2:1; | |
115924b6 | 236 | #endif /* __BIG_ENDIAN_BITFIELD */ |
d1a890fa | 237 | |
115924b6 | 238 | __le32 rssHash; /* RSS hash value */ |
d1a890fa | 239 | |
115924b6 SB |
240 | #ifdef __BIG_ENDIAN_BITFIELD |
241 | u32 tci:16; /* Tag stripped */ | |
242 | u32 ts:1; /* Tag is stripped */ | |
243 | u32 err:1; /* Error */ | |
244 | u32 len:14; /* data length */ | |
245 | #else | |
d1a890fa SB |
246 | u32 len:14; /* data length */ |
247 | u32 err:1; /* Error */ | |
248 | u32 ts:1; /* Tag is stripped */ | |
249 | u32 tci:16; /* Tag stripped */ | |
115924b6 SB |
250 | #endif /* __BIG_ENDIAN_BITFIELD */ |
251 | ||
d1a890fa | 252 | |
115924b6 SB |
253 | #ifdef __BIG_ENDIAN_BITFIELD |
254 | u32 gen:1; /* generation bit */ | |
255 | u32 type:7; /* completion type */ | |
256 | u32 fcs:1; /* Frame CRC correct */ | |
257 | u32 frg:1; /* IP Fragment */ | |
258 | u32 v4:1; /* IPv4 */ | |
259 | u32 v6:1; /* IPv6 */ | |
260 | u32 ipc:1; /* IP Checksum Correct */ | |
261 | u32 tcp:1; /* TCP packet */ | |
262 | u32 udp:1; /* UDP packet */ | |
263 | u32 tuc:1; /* TCP/UDP Checksum Correct */ | |
264 | u32 csum:16; | |
265 | #else | |
d1a890fa SB |
266 | u32 csum:16; |
267 | u32 tuc:1; /* TCP/UDP Checksum Correct */ | |
268 | u32 udp:1; /* UDP packet */ | |
269 | u32 tcp:1; /* TCP packet */ | |
270 | u32 ipc:1; /* IP Checksum Correct */ | |
271 | u32 v6:1; /* IPv6 */ | |
272 | u32 v4:1; /* IPv4 */ | |
273 | u32 frg:1; /* IP Fragment */ | |
274 | u32 fcs:1; /* Frame CRC correct */ | |
275 | u32 type:7; /* completion type */ | |
276 | u32 gen:1; /* generation bit */ | |
115924b6 | 277 | #endif /* __BIG_ENDIAN_BITFIELD */ |
d1a890fa SB |
278 | }; |
279 | ||
45dac1d6 SB |
280 | struct Vmxnet3_RxCompDescExt { |
281 | __le32 dword1; | |
282 | u8 segCnt; /* Number of aggregated packets */ | |
283 | u8 dupAckCnt; /* Number of duplicate Acks */ | |
284 | __le16 tsDelta; /* TCP timestamp difference */ | |
285 | __le32 dword2; | |
286 | #ifdef __BIG_ENDIAN_BITFIELD | |
287 | u32 gen:1; /* generation bit */ | |
288 | u32 type:7; /* completion type */ | |
289 | u32 fcs:1; /* Frame CRC correct */ | |
290 | u32 frg:1; /* IP Fragment */ | |
291 | u32 v4:1; /* IPv4 */ | |
292 | u32 v6:1; /* IPv6 */ | |
293 | u32 ipc:1; /* IP Checksum Correct */ | |
294 | u32 tcp:1; /* TCP packet */ | |
295 | u32 udp:1; /* UDP packet */ | |
296 | u32 tuc:1; /* TCP/UDP Checksum Correct */ | |
297 | u32 mss:16; | |
298 | #else | |
299 | u32 mss:16; | |
300 | u32 tuc:1; /* TCP/UDP Checksum Correct */ | |
301 | u32 udp:1; /* UDP packet */ | |
302 | u32 tcp:1; /* TCP packet */ | |
303 | u32 ipc:1; /* IP Checksum Correct */ | |
304 | u32 v6:1; /* IPv6 */ | |
305 | u32 v4:1; /* IPv4 */ | |
306 | u32 frg:1; /* IP Fragment */ | |
307 | u32 fcs:1; /* Frame CRC correct */ | |
308 | u32 type:7; /* completion type */ | |
309 | u32 gen:1; /* generation bit */ | |
310 | #endif /* __BIG_ENDIAN_BITFIELD */ | |
311 | }; | |
312 | ||
313 | ||
d1a890fa SB |
314 | /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */ |
315 | #define VMXNET3_RCD_TUC_SHIFT 16 | |
316 | #define VMXNET3_RCD_IPC_SHIFT 19 | |
317 | ||
318 | /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */ | |
319 | #define VMXNET3_RCD_TYPE_SHIFT 56 | |
320 | #define VMXNET3_RCD_GEN_SHIFT 63 | |
321 | ||
322 | /* csum OK for TCP/UDP pkts over IP */ | |
323 | #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \ | |
324 | 1 << VMXNET3_RCD_IPC_SHIFT) | |
115924b6 SB |
325 | #define VMXNET3_TXD_GEN_SIZE 1 |
326 | #define VMXNET3_TXD_EOP_SIZE 1 | |
d1a890fa SB |
327 | |
328 | /* value of RxCompDesc.rssType */ | |
329 | enum { | |
330 | VMXNET3_RCD_RSS_TYPE_NONE = 0, | |
331 | VMXNET3_RCD_RSS_TYPE_IPV4 = 1, | |
332 | VMXNET3_RCD_RSS_TYPE_TCPIPV4 = 2, | |
333 | VMXNET3_RCD_RSS_TYPE_IPV6 = 3, | |
334 | VMXNET3_RCD_RSS_TYPE_TCPIPV6 = 4, | |
335 | }; | |
336 | ||
337 | ||
338 | /* a union for accessing all cmd/completion descriptors */ | |
339 | union Vmxnet3_GenericDesc { | |
115924b6 SB |
340 | __le64 qword[2]; |
341 | __le32 dword[4]; | |
342 | __le16 word[8]; | |
d1a890fa SB |
343 | struct Vmxnet3_TxDesc txd; |
344 | struct Vmxnet3_RxDesc rxd; | |
345 | struct Vmxnet3_TxCompDesc tcd; | |
346 | struct Vmxnet3_RxCompDesc rcd; | |
45dac1d6 | 347 | struct Vmxnet3_RxCompDescExt rcdExt; |
d1a890fa SB |
348 | }; |
349 | ||
350 | #define VMXNET3_INIT_GEN 1 | |
351 | ||
352 | /* Max size of a single tx buffer */ | |
353 | #define VMXNET3_MAX_TX_BUF_SIZE (1 << 14) | |
354 | ||
355 | /* # of tx desc needed for a tx buffer size */ | |
356 | #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \ | |
357 | VMXNET3_MAX_TX_BUF_SIZE) | |
358 | ||
359 | /* max # of tx descs for a non-tso pkt */ | |
360 | #define VMXNET3_MAX_TXD_PER_PKT 16 | |
361 | ||
362 | /* Max size of a single rx buffer */ | |
363 | #define VMXNET3_MAX_RX_BUF_SIZE ((1 << 14) - 1) | |
364 | /* Minimum size of a type 0 buffer */ | |
365 | #define VMXNET3_MIN_T0_BUF_SIZE 128 | |
366 | #define VMXNET3_MAX_CSUM_OFFSET 1024 | |
367 | ||
368 | /* Ring base address alignment */ | |
369 | #define VMXNET3_RING_BA_ALIGN 512 | |
370 | #define VMXNET3_RING_BA_MASK (VMXNET3_RING_BA_ALIGN - 1) | |
371 | ||
372 | /* Ring size must be a multiple of 32 */ | |
373 | #define VMXNET3_RING_SIZE_ALIGN 32 | |
374 | #define VMXNET3_RING_SIZE_MASK (VMXNET3_RING_SIZE_ALIGN - 1) | |
375 | ||
376 | /* Max ring size */ | |
377 | #define VMXNET3_TX_RING_MAX_SIZE 4096 | |
378 | #define VMXNET3_TC_RING_MAX_SIZE 4096 | |
379 | #define VMXNET3_RX_RING_MAX_SIZE 4096 | |
14112ca5 | 380 | #define VMXNET3_RX_RING2_MAX_SIZE 4096 |
d1a890fa SB |
381 | #define VMXNET3_RC_RING_MAX_SIZE 8192 |
382 | ||
383 | /* a list of reasons for queue stop */ | |
384 | ||
385 | enum { | |
386 | VMXNET3_ERR_NOEOP = 0x80000000, /* cannot find the EOP desc of a pkt */ | |
387 | VMXNET3_ERR_TXD_REUSE = 0x80000001, /* reuse TxDesc before tx completion */ | |
388 | VMXNET3_ERR_BIG_PKT = 0x80000002, /* too many TxDesc for a pkt */ | |
389 | VMXNET3_ERR_DESC_NOT_SPT = 0x80000003, /* descriptor type not supported */ | |
390 | VMXNET3_ERR_SMALL_BUF = 0x80000004, /* type 0 buffer too small */ | |
391 | VMXNET3_ERR_STRESS = 0x80000005, /* stress option firing in vmkernel */ | |
392 | VMXNET3_ERR_SWITCH = 0x80000006, /* mode switch failure */ | |
393 | VMXNET3_ERR_TXD_INVALID = 0x80000007, /* invalid TxDesc */ | |
394 | }; | |
395 | ||
396 | /* completion descriptor types */ | |
397 | #define VMXNET3_CDTYPE_TXCOMP 0 /* Tx Completion Descriptor */ | |
398 | #define VMXNET3_CDTYPE_RXCOMP 3 /* Rx Completion Descriptor */ | |
45dac1d6 | 399 | #define VMXNET3_CDTYPE_RXCOMP_LRO 4 /* Rx Completion Descriptor for LRO */ |
d1a890fa SB |
400 | |
401 | enum { | |
402 | VMXNET3_GOS_BITS_UNK = 0, /* unknown */ | |
403 | VMXNET3_GOS_BITS_32 = 1, | |
404 | VMXNET3_GOS_BITS_64 = 2, | |
405 | }; | |
406 | ||
407 | #define VMXNET3_GOS_TYPE_LINUX 1 | |
408 | ||
409 | ||
410 | struct Vmxnet3_GOSInfo { | |
115924b6 SB |
411 | #ifdef __BIG_ENDIAN_BITFIELD |
412 | u32 gosMisc:10; /* other info about gos */ | |
413 | u32 gosVer:16; /* gos version */ | |
414 | u32 gosType:4; /* which guest */ | |
415 | u32 gosBits:2; /* 32-bit or 64-bit? */ | |
416 | #else | |
417 | u32 gosBits:2; /* 32-bit or 64-bit? */ | |
418 | u32 gosType:4; /* which guest */ | |
419 | u32 gosVer:16; /* gos version */ | |
420 | u32 gosMisc:10; /* other info about gos */ | |
421 | #endif /* __BIG_ENDIAN_BITFIELD */ | |
d1a890fa SB |
422 | }; |
423 | ||
d1a890fa | 424 | struct Vmxnet3_DriverInfo { |
115924b6 | 425 | __le32 version; |
d1a890fa | 426 | struct Vmxnet3_GOSInfo gos; |
115924b6 SB |
427 | __le32 vmxnet3RevSpt; |
428 | __le32 uptVerSpt; | |
d1a890fa SB |
429 | }; |
430 | ||
431 | ||
dd83829e | 432 | #define VMXNET3_REV1_MAGIC 3133079265u |
d1a890fa SB |
433 | |
434 | /* | |
435 | * QueueDescPA must be 128 bytes aligned. It points to an array of | |
436 | * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc. | |
437 | * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by | |
438 | * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively. | |
439 | */ | |
440 | #define VMXNET3_QUEUE_DESC_ALIGN 128 | |
441 | ||
442 | ||
443 | struct Vmxnet3_MiscConf { | |
444 | struct Vmxnet3_DriverInfo driverInfo; | |
115924b6 SB |
445 | __le64 uptFeatures; |
446 | __le64 ddPA; /* driver data PA */ | |
447 | __le64 queueDescPA; /* queue descriptor table PA */ | |
448 | __le32 ddLen; /* driver data len */ | |
449 | __le32 queueDescLen; /* queue desc. table len in bytes */ | |
450 | __le32 mtu; | |
451 | __le16 maxNumRxSG; | |
d1a890fa SB |
452 | u8 numTxQueues; |
453 | u8 numRxQueues; | |
115924b6 | 454 | __le32 reserved[4]; |
d1a890fa SB |
455 | }; |
456 | ||
457 | ||
458 | struct Vmxnet3_TxQueueConf { | |
115924b6 SB |
459 | __le64 txRingBasePA; |
460 | __le64 dataRingBasePA; | |
461 | __le64 compRingBasePA; | |
462 | __le64 ddPA; /* driver data */ | |
463 | __le64 reserved; | |
464 | __le32 txRingSize; /* # of tx desc */ | |
465 | __le32 dataRingSize; /* # of data desc */ | |
466 | __le32 compRingSize; /* # of comp desc */ | |
467 | __le32 ddLen; /* size of driver data */ | |
d1a890fa SB |
468 | u8 intrIdx; |
469 | u8 _pad[7]; | |
470 | }; | |
471 | ||
472 | ||
473 | struct Vmxnet3_RxQueueConf { | |
115924b6 SB |
474 | __le64 rxRingBasePA[2]; |
475 | __le64 compRingBasePA; | |
476 | __le64 ddPA; /* driver data */ | |
477 | __le64 reserved; | |
478 | __le32 rxRingSize[2]; /* # of rx desc */ | |
479 | __le32 compRingSize; /* # of rx comp desc */ | |
480 | __le32 ddLen; /* size of driver data */ | |
d1a890fa SB |
481 | u8 intrIdx; |
482 | u8 _pad[7]; | |
483 | }; | |
484 | ||
485 | ||
486 | enum vmxnet3_intr_mask_mode { | |
487 | VMXNET3_IMM_AUTO = 0, | |
488 | VMXNET3_IMM_ACTIVE = 1, | |
489 | VMXNET3_IMM_LAZY = 2 | |
490 | }; | |
491 | ||
492 | enum vmxnet3_intr_type { | |
493 | VMXNET3_IT_AUTO = 0, | |
494 | VMXNET3_IT_INTX = 1, | |
495 | VMXNET3_IT_MSI = 2, | |
496 | VMXNET3_IT_MSIX = 3 | |
497 | }; | |
498 | ||
499 | #define VMXNET3_MAX_TX_QUEUES 8 | |
500 | #define VMXNET3_MAX_RX_QUEUES 16 | |
501 | /* addition 1 for events */ | |
502 | #define VMXNET3_MAX_INTRS 25 | |
503 | ||
6929fe8a RZ |
504 | /* value of intrCtrl */ |
505 | #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */ | |
506 | ||
d1a890fa SB |
507 | |
508 | struct Vmxnet3_IntrConf { | |
509 | bool autoMask; | |
510 | u8 numIntrs; /* # of interrupts */ | |
511 | u8 eventIntrIdx; | |
512 | u8 modLevels[VMXNET3_MAX_INTRS]; /* moderation level for | |
513 | * each intr */ | |
6929fe8a RZ |
514 | __le32 intrCtrl; |
515 | __le32 reserved[2]; | |
d1a890fa SB |
516 | }; |
517 | ||
518 | /* one bit per VLAN ID, the size is in the units of u32 */ | |
519 | #define VMXNET3_VFT_SIZE (4096 / (sizeof(u32) * 8)) | |
520 | ||
521 | ||
522 | struct Vmxnet3_QueueStatus { | |
523 | bool stopped; | |
524 | u8 _pad[3]; | |
115924b6 | 525 | __le32 error; |
d1a890fa SB |
526 | }; |
527 | ||
528 | ||
529 | struct Vmxnet3_TxQueueCtrl { | |
115924b6 SB |
530 | __le32 txNumDeferred; |
531 | __le32 txThreshold; | |
532 | __le64 reserved; | |
d1a890fa SB |
533 | }; |
534 | ||
535 | ||
536 | struct Vmxnet3_RxQueueCtrl { | |
537 | bool updateRxProd; | |
538 | u8 _pad[7]; | |
115924b6 | 539 | __le64 reserved; |
d1a890fa SB |
540 | }; |
541 | ||
542 | enum { | |
543 | VMXNET3_RXM_UCAST = 0x01, /* unicast only */ | |
544 | VMXNET3_RXM_MCAST = 0x02, /* multicast passing the filters */ | |
545 | VMXNET3_RXM_BCAST = 0x04, /* broadcast only */ | |
546 | VMXNET3_RXM_ALL_MULTI = 0x08, /* all multicast */ | |
547 | VMXNET3_RXM_PROMISC = 0x10 /* promiscuous */ | |
548 | }; | |
549 | ||
550 | struct Vmxnet3_RxFilterConf { | |
115924b6 SB |
551 | __le32 rxMode; /* VMXNET3_RXM_xxx */ |
552 | __le16 mfTableLen; /* size of the multicast filter table */ | |
553 | __le16 _pad1; | |
554 | __le64 mfTablePA; /* PA of the multicast filters table */ | |
555 | __le32 vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */ | |
d1a890fa SB |
556 | }; |
557 | ||
558 | ||
559 | #define VMXNET3_PM_MAX_FILTERS 6 | |
560 | #define VMXNET3_PM_MAX_PATTERN_SIZE 128 | |
561 | #define VMXNET3_PM_MAX_MASK_SIZE (VMXNET3_PM_MAX_PATTERN_SIZE / 8) | |
562 | ||
3843e515 HH |
563 | #define VMXNET3_PM_WAKEUP_MAGIC cpu_to_le16(0x01) /* wake up on magic pkts */ |
564 | #define VMXNET3_PM_WAKEUP_FILTER cpu_to_le16(0x02) /* wake up on pkts matching | |
565 | * filters */ | |
d1a890fa SB |
566 | |
567 | ||
568 | struct Vmxnet3_PM_PktFilter { | |
569 | u8 maskSize; | |
570 | u8 patternSize; | |
571 | u8 mask[VMXNET3_PM_MAX_MASK_SIZE]; | |
572 | u8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE]; | |
573 | u8 pad[6]; | |
574 | }; | |
575 | ||
576 | ||
577 | struct Vmxnet3_PMConf { | |
115924b6 | 578 | __le16 wakeUpEvents; /* VMXNET3_PM_WAKEUP_xxx */ |
d1a890fa SB |
579 | u8 numFilters; |
580 | u8 pad[5]; | |
581 | struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS]; | |
582 | }; | |
583 | ||
584 | ||
585 | struct Vmxnet3_VariableLenConfDesc { | |
115924b6 SB |
586 | __le32 confVer; |
587 | __le32 confLen; | |
588 | __le64 confPA; | |
d1a890fa SB |
589 | }; |
590 | ||
591 | ||
592 | struct Vmxnet3_TxQueueDesc { | |
593 | struct Vmxnet3_TxQueueCtrl ctrl; | |
594 | struct Vmxnet3_TxQueueConf conf; | |
595 | ||
596 | /* Driver read after a GET command */ | |
597 | struct Vmxnet3_QueueStatus status; | |
598 | struct UPT1_TxStats stats; | |
599 | u8 _pad[88]; /* 128 aligned */ | |
600 | }; | |
601 | ||
602 | ||
603 | struct Vmxnet3_RxQueueDesc { | |
604 | struct Vmxnet3_RxQueueCtrl ctrl; | |
605 | struct Vmxnet3_RxQueueConf conf; | |
606 | /* Driver read after a GET commad */ | |
607 | struct Vmxnet3_QueueStatus status; | |
608 | struct UPT1_RxStats stats; | |
609 | u8 __pad[88]; /* 128 aligned */ | |
610 | }; | |
611 | ||
612 | ||
613 | struct Vmxnet3_DSDevRead { | |
614 | /* read-only region for device, read by dev in response to a SET cmd */ | |
615 | struct Vmxnet3_MiscConf misc; | |
616 | struct Vmxnet3_IntrConf intrConf; | |
617 | struct Vmxnet3_RxFilterConf rxFilterConf; | |
618 | struct Vmxnet3_VariableLenConfDesc rssConfDesc; | |
619 | struct Vmxnet3_VariableLenConfDesc pmConfDesc; | |
620 | struct Vmxnet3_VariableLenConfDesc pluginConfDesc; | |
621 | }; | |
622 | ||
623 | /* All structures in DriverShared are padded to multiples of 8 bytes */ | |
624 | struct Vmxnet3_DriverShared { | |
115924b6 | 625 | __le32 magic; |
d1a890fa | 626 | /* make devRead start at 64bit boundaries */ |
115924b6 SB |
627 | __le32 pad; |
628 | struct Vmxnet3_DSDevRead devRead; | |
629 | __le32 ecr; | |
630 | __le32 reserved[5]; | |
d1a890fa SB |
631 | }; |
632 | ||
633 | ||
634 | #define VMXNET3_ECR_RQERR (1 << 0) | |
635 | #define VMXNET3_ECR_TQERR (1 << 1) | |
636 | #define VMXNET3_ECR_LINK (1 << 2) | |
637 | #define VMXNET3_ECR_DIC (1 << 3) | |
638 | #define VMXNET3_ECR_DEBUG (1 << 4) | |
639 | ||
640 | /* flip the gen bit of a ring */ | |
641 | #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1) | |
642 | ||
643 | /* only use this if moving the idx won't affect the gen bit */ | |
644 | #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \ | |
645 | do {\ | |
646 | (idx)++;\ | |
647 | if (unlikely((idx) == (ring_size))) {\ | |
648 | (idx) = 0;\ | |
649 | } \ | |
650 | } while (0) | |
651 | ||
652 | #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \ | |
653 | (vfTable[vid >> 5] |= (1 << (vid & 31))) | |
654 | #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \ | |
655 | (vfTable[vid >> 5] &= ~(1 << (vid & 31))) | |
656 | ||
657 | #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \ | |
658 | ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0) | |
659 | ||
660 | #define VMXNET3_MAX_MTU 9000 | |
661 | #define VMXNET3_MIN_MTU 60 | |
662 | ||
663 | #define VMXNET3_LINK_UP (10000 << 16 | 1) /* 10 Gbps, up */ | |
664 | #define VMXNET3_LINK_DOWN 0 | |
665 | ||
666 | #endif /* _VMXNET3_DEFS_H_ */ |