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40a3a915 RV |
1 | /****************************************************************************** |
2 | * This software may be used and distributed according to the terms of | |
3 | * the GNU General Public License (GPL), incorporated herein by reference. | |
4 | * Drivers based on or derived from this code fall under the GPL and must | |
5 | * retain the authorship, copyright and license notice. This file is not | |
6 | * a complete program and may only be used when the entire operating | |
7 | * system is licensed under the GPL. | |
8 | * See the file COPYING in this distribution for more information. | |
9 | * | |
10 | * vxge-config.c: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O | |
11 | * Virtualized Server Adapter. | |
12 | * Copyright(c) 2002-2009 Neterion Inc. | |
13 | ******************************************************************************/ | |
14 | #include <linux/vmalloc.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/pci_hotplug.h> | |
5a0e3ad6 | 18 | #include <linux/slab.h> |
40a3a915 RV |
19 | |
20 | #include "vxge-traffic.h" | |
21 | #include "vxge-config.h" | |
22 | ||
23 | /* | |
24 | * __vxge_hw_channel_allocate - Allocate memory for channel | |
25 | * This function allocates required memory for the channel and various arrays | |
26 | * in the channel | |
27 | */ | |
28 | struct __vxge_hw_channel* | |
29 | __vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph, | |
30 | enum __vxge_hw_channel_type type, | |
31 | u32 length, u32 per_dtr_space, void *userdata) | |
32 | { | |
33 | struct __vxge_hw_channel *channel; | |
34 | struct __vxge_hw_device *hldev; | |
35 | int size = 0; | |
36 | u32 vp_id; | |
37 | ||
38 | hldev = vph->vpath->hldev; | |
39 | vp_id = vph->vpath->vp_id; | |
40 | ||
41 | switch (type) { | |
42 | case VXGE_HW_CHANNEL_TYPE_FIFO: | |
43 | size = sizeof(struct __vxge_hw_fifo); | |
44 | break; | |
45 | case VXGE_HW_CHANNEL_TYPE_RING: | |
46 | size = sizeof(struct __vxge_hw_ring); | |
47 | break; | |
48 | default: | |
49 | break; | |
50 | } | |
51 | ||
52 | channel = kzalloc(size, GFP_KERNEL); | |
53 | if (channel == NULL) | |
54 | goto exit0; | |
55 | INIT_LIST_HEAD(&channel->item); | |
56 | ||
57 | channel->common_reg = hldev->common_reg; | |
58 | channel->first_vp_id = hldev->first_vp_id; | |
59 | channel->type = type; | |
60 | channel->devh = hldev; | |
61 | channel->vph = vph; | |
62 | channel->userdata = userdata; | |
63 | channel->per_dtr_space = per_dtr_space; | |
64 | channel->length = length; | |
65 | channel->vp_id = vp_id; | |
66 | ||
67 | channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL); | |
68 | if (channel->work_arr == NULL) | |
69 | goto exit1; | |
70 | ||
71 | channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL); | |
72 | if (channel->free_arr == NULL) | |
73 | goto exit1; | |
74 | channel->free_ptr = length; | |
75 | ||
76 | channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL); | |
77 | if (channel->reserve_arr == NULL) | |
78 | goto exit1; | |
79 | channel->reserve_ptr = length; | |
80 | channel->reserve_top = 0; | |
81 | ||
82 | channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL); | |
83 | if (channel->orig_arr == NULL) | |
84 | goto exit1; | |
85 | ||
86 | return channel; | |
87 | exit1: | |
88 | __vxge_hw_channel_free(channel); | |
89 | ||
90 | exit0: | |
91 | return NULL; | |
92 | } | |
93 | ||
94 | /* | |
95 | * __vxge_hw_channel_free - Free memory allocated for channel | |
96 | * This function deallocates memory from the channel and various arrays | |
97 | * in the channel | |
98 | */ | |
99 | void __vxge_hw_channel_free(struct __vxge_hw_channel *channel) | |
100 | { | |
101 | kfree(channel->work_arr); | |
102 | kfree(channel->free_arr); | |
103 | kfree(channel->reserve_arr); | |
104 | kfree(channel->orig_arr); | |
105 | kfree(channel); | |
106 | } | |
107 | ||
108 | /* | |
109 | * __vxge_hw_channel_initialize - Initialize a channel | |
110 | * This function initializes a channel by properly setting the | |
111 | * various references | |
112 | */ | |
113 | enum vxge_hw_status | |
114 | __vxge_hw_channel_initialize(struct __vxge_hw_channel *channel) | |
115 | { | |
116 | u32 i; | |
117 | struct __vxge_hw_virtualpath *vpath; | |
118 | ||
119 | vpath = channel->vph->vpath; | |
120 | ||
121 | if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) { | |
122 | for (i = 0; i < channel->length; i++) | |
123 | channel->orig_arr[i] = channel->reserve_arr[i]; | |
124 | } | |
125 | ||
126 | switch (channel->type) { | |
127 | case VXGE_HW_CHANNEL_TYPE_FIFO: | |
128 | vpath->fifoh = (struct __vxge_hw_fifo *)channel; | |
129 | channel->stats = &((struct __vxge_hw_fifo *) | |
130 | channel)->stats->common_stats; | |
131 | break; | |
132 | case VXGE_HW_CHANNEL_TYPE_RING: | |
133 | vpath->ringh = (struct __vxge_hw_ring *)channel; | |
134 | channel->stats = &((struct __vxge_hw_ring *) | |
135 | channel)->stats->common_stats; | |
136 | break; | |
137 | default: | |
138 | break; | |
139 | } | |
140 | ||
141 | return VXGE_HW_OK; | |
142 | } | |
143 | ||
144 | /* | |
145 | * __vxge_hw_channel_reset - Resets a channel | |
146 | * This function resets a channel by properly setting the various references | |
147 | */ | |
148 | enum vxge_hw_status | |
149 | __vxge_hw_channel_reset(struct __vxge_hw_channel *channel) | |
150 | { | |
151 | u32 i; | |
152 | ||
153 | for (i = 0; i < channel->length; i++) { | |
154 | if (channel->reserve_arr != NULL) | |
155 | channel->reserve_arr[i] = channel->orig_arr[i]; | |
156 | if (channel->free_arr != NULL) | |
157 | channel->free_arr[i] = NULL; | |
158 | if (channel->work_arr != NULL) | |
159 | channel->work_arr[i] = NULL; | |
160 | } | |
161 | channel->free_ptr = channel->length; | |
162 | channel->reserve_ptr = channel->length; | |
163 | channel->reserve_top = 0; | |
164 | channel->post_index = 0; | |
165 | channel->compl_index = 0; | |
166 | ||
167 | return VXGE_HW_OK; | |
168 | } | |
169 | ||
170 | /* | |
171 | * __vxge_hw_device_pci_e_init | |
172 | * Initialize certain PCI/PCI-X configuration registers | |
173 | * with recommended values. Save config space for future hw resets. | |
174 | */ | |
175 | void | |
176 | __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev) | |
177 | { | |
178 | u16 cmd = 0; | |
179 | ||
180 | /* Set the PErr Repconse bit and SERR in PCI command register. */ | |
181 | pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd); | |
182 | cmd |= 0x140; | |
183 | pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd); | |
184 | ||
185 | pci_save_state(hldev->pdev); | |
40a3a915 RV |
186 | } |
187 | ||
188 | /* | |
189 | * __vxge_hw_device_register_poll | |
190 | * Will poll certain register for specified amount of time. | |
191 | * Will poll until masked bit is not cleared. | |
192 | */ | |
193 | enum vxge_hw_status | |
194 | __vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis) | |
195 | { | |
196 | u64 val64; | |
197 | u32 i = 0; | |
198 | enum vxge_hw_status ret = VXGE_HW_FAIL; | |
199 | ||
200 | udelay(10); | |
201 | ||
202 | do { | |
203 | val64 = readq(reg); | |
204 | if (!(val64 & mask)) | |
205 | return VXGE_HW_OK; | |
206 | udelay(100); | |
207 | } while (++i <= 9); | |
208 | ||
209 | i = 0; | |
210 | do { | |
211 | val64 = readq(reg); | |
212 | if (!(val64 & mask)) | |
213 | return VXGE_HW_OK; | |
214 | mdelay(1); | |
215 | } while (++i <= max_millis); | |
216 | ||
217 | return ret; | |
218 | } | |
219 | ||
220 | /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset | |
221 | * in progress | |
222 | * This routine checks the vpath reset in progress register is turned zero | |
223 | */ | |
224 | enum vxge_hw_status | |
225 | __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog) | |
226 | { | |
227 | enum vxge_hw_status status; | |
228 | status = __vxge_hw_device_register_poll(vpath_rst_in_prog, | |
229 | VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff), | |
230 | VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
231 | return status; | |
232 | } | |
233 | ||
234 | /* | |
235 | * __vxge_hw_device_toc_get | |
236 | * This routine sets the swapper and reads the toc pointer and returns the | |
237 | * memory mapped address of the toc | |
238 | */ | |
239 | struct vxge_hw_toc_reg __iomem * | |
240 | __vxge_hw_device_toc_get(void __iomem *bar0) | |
241 | { | |
242 | u64 val64; | |
243 | struct vxge_hw_toc_reg __iomem *toc = NULL; | |
244 | enum vxge_hw_status status; | |
245 | ||
246 | struct vxge_hw_legacy_reg __iomem *legacy_reg = | |
247 | (struct vxge_hw_legacy_reg __iomem *)bar0; | |
248 | ||
249 | status = __vxge_hw_legacy_swapper_set(legacy_reg); | |
250 | if (status != VXGE_HW_OK) | |
251 | goto exit; | |
252 | ||
253 | val64 = readq(&legacy_reg->toc_first_pointer); | |
254 | toc = (struct vxge_hw_toc_reg __iomem *)(bar0+val64); | |
255 | exit: | |
256 | return toc; | |
257 | } | |
258 | ||
259 | /* | |
260 | * __vxge_hw_device_reg_addr_get | |
261 | * This routine sets the swapper and reads the toc pointer and initializes the | |
262 | * register location pointers in the device object. It waits until the ric is | |
263 | * completed initializing registers. | |
264 | */ | |
265 | enum vxge_hw_status | |
266 | __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev) | |
267 | { | |
268 | u64 val64; | |
269 | u32 i; | |
270 | enum vxge_hw_status status = VXGE_HW_OK; | |
271 | ||
272 | hldev->legacy_reg = (struct vxge_hw_legacy_reg __iomem *)hldev->bar0; | |
273 | ||
274 | hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0); | |
275 | if (hldev->toc_reg == NULL) { | |
276 | status = VXGE_HW_FAIL; | |
277 | goto exit; | |
278 | } | |
279 | ||
280 | val64 = readq(&hldev->toc_reg->toc_common_pointer); | |
281 | hldev->common_reg = | |
282 | (struct vxge_hw_common_reg __iomem *)(hldev->bar0 + val64); | |
283 | ||
284 | val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer); | |
285 | hldev->mrpcim_reg = | |
286 | (struct vxge_hw_mrpcim_reg __iomem *)(hldev->bar0 + val64); | |
287 | ||
288 | for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) { | |
289 | val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]); | |
290 | hldev->srpcim_reg[i] = | |
291 | (struct vxge_hw_srpcim_reg __iomem *) | |
292 | (hldev->bar0 + val64); | |
293 | } | |
294 | ||
295 | for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) { | |
296 | val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]); | |
297 | hldev->vpmgmt_reg[i] = | |
298 | (struct vxge_hw_vpmgmt_reg __iomem *)(hldev->bar0 + val64); | |
299 | } | |
300 | ||
301 | for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) { | |
302 | val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]); | |
303 | hldev->vpath_reg[i] = | |
304 | (struct vxge_hw_vpath_reg __iomem *) | |
305 | (hldev->bar0 + val64); | |
306 | } | |
307 | ||
308 | val64 = readq(&hldev->toc_reg->toc_kdfc); | |
309 | ||
310 | switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) { | |
311 | case 0: | |
312 | hldev->kdfc = (u8 __iomem *)(hldev->bar0 + | |
313 | VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64)); | |
314 | break; | |
40a3a915 RV |
315 | default: |
316 | break; | |
317 | } | |
318 | ||
319 | status = __vxge_hw_device_vpath_reset_in_prog_check( | |
320 | (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog); | |
321 | exit: | |
322 | return status; | |
323 | } | |
324 | ||
325 | /* | |
326 | * __vxge_hw_device_id_get | |
327 | * This routine returns sets the device id and revision numbers into the device | |
328 | * structure | |
329 | */ | |
330 | void __vxge_hw_device_id_get(struct __vxge_hw_device *hldev) | |
331 | { | |
332 | u64 val64; | |
333 | ||
334 | val64 = readq(&hldev->common_reg->titan_asic_id); | |
335 | hldev->device_id = | |
336 | (u16)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(val64); | |
337 | ||
338 | hldev->major_revision = | |
339 | (u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(val64); | |
340 | ||
341 | hldev->minor_revision = | |
342 | (u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(val64); | |
40a3a915 RV |
343 | } |
344 | ||
345 | /* | |
346 | * __vxge_hw_device_access_rights_get: Get Access Rights of the driver | |
347 | * This routine returns the Access Rights of the driver | |
348 | */ | |
349 | static u32 | |
350 | __vxge_hw_device_access_rights_get(u32 host_type, u32 func_id) | |
351 | { | |
352 | u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH; | |
353 | ||
354 | switch (host_type) { | |
355 | case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION: | |
1dc47a9b SH |
356 | if (func_id == 0) { |
357 | access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | | |
358 | VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; | |
359 | } | |
40a3a915 RV |
360 | break; |
361 | case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION: | |
362 | access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | | |
363 | VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; | |
364 | break; | |
365 | case VXGE_HW_NO_MR_SR_VH0_FUNCTION0: | |
366 | access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM | | |
367 | VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; | |
368 | break; | |
369 | case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION: | |
370 | case VXGE_HW_SR_VH_VIRTUAL_FUNCTION: | |
371 | case VXGE_HW_MR_SR_VH0_INVALID_CONFIG: | |
372 | break; | |
373 | case VXGE_HW_SR_VH_FUNCTION0: | |
374 | case VXGE_HW_VH_NORMAL_FUNCTION: | |
375 | access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM; | |
376 | break; | |
377 | } | |
378 | ||
379 | return access_rights; | |
380 | } | |
92cdd7c3 SH |
381 | /* |
382 | * __vxge_hw_device_is_privilaged | |
383 | * This routine checks if the device function is privilaged or not | |
384 | */ | |
385 | ||
386 | enum vxge_hw_status | |
387 | __vxge_hw_device_is_privilaged(u32 host_type, u32 func_id) | |
388 | { | |
389 | if (__vxge_hw_device_access_rights_get(host_type, | |
390 | func_id) & | |
391 | VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) | |
392 | return VXGE_HW_OK; | |
393 | else | |
394 | return VXGE_HW_ERR_PRIVILAGED_OPEARATION; | |
395 | } | |
396 | ||
40a3a915 RV |
397 | /* |
398 | * __vxge_hw_device_host_info_get | |
399 | * This routine returns the host type assignments | |
400 | */ | |
401 | void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev) | |
402 | { | |
403 | u64 val64; | |
404 | u32 i; | |
405 | ||
406 | val64 = readq(&hldev->common_reg->host_type_assignments); | |
407 | ||
408 | hldev->host_type = | |
409 | (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64); | |
410 | ||
411 | hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments); | |
412 | ||
413 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
414 | ||
415 | if (!(hldev->vpath_assignments & vxge_mBIT(i))) | |
416 | continue; | |
417 | ||
418 | hldev->func_id = | |
419 | __vxge_hw_vpath_func_id_get(i, hldev->vpmgmt_reg[i]); | |
420 | ||
421 | hldev->access_rights = __vxge_hw_device_access_rights_get( | |
422 | hldev->host_type, hldev->func_id); | |
423 | ||
424 | hldev->first_vp_id = i; | |
425 | break; | |
426 | } | |
40a3a915 RV |
427 | } |
428 | ||
429 | /* | |
430 | * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as | |
431 | * link width and signalling rate. | |
432 | */ | |
433 | static enum vxge_hw_status | |
434 | __vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev) | |
435 | { | |
436 | int exp_cap; | |
437 | u16 lnk; | |
438 | ||
439 | /* Get the negotiated link width and speed from PCI config space */ | |
440 | exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP); | |
441 | pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk); | |
442 | ||
443 | if ((lnk & PCI_EXP_LNKSTA_CLS) != 1) | |
444 | return VXGE_HW_ERR_INVALID_PCI_INFO; | |
445 | ||
446 | switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) { | |
447 | case PCIE_LNK_WIDTH_RESRV: | |
448 | case PCIE_LNK_X1: | |
449 | case PCIE_LNK_X2: | |
450 | case PCIE_LNK_X4: | |
451 | case PCIE_LNK_X8: | |
452 | break; | |
453 | default: | |
454 | return VXGE_HW_ERR_INVALID_PCI_INFO; | |
455 | } | |
456 | ||
457 | return VXGE_HW_OK; | |
458 | } | |
459 | ||
40a3a915 RV |
460 | /* |
461 | * __vxge_hw_device_initialize | |
462 | * Initialize Titan-V hardware. | |
463 | */ | |
464 | enum vxge_hw_status __vxge_hw_device_initialize(struct __vxge_hw_device *hldev) | |
465 | { | |
466 | enum vxge_hw_status status = VXGE_HW_OK; | |
467 | ||
92cdd7c3 SH |
468 | if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type, |
469 | hldev->func_id)) { | |
5dbc9011 SS |
470 | /* Validate the pci-e link width and speed */ |
471 | status = __vxge_hw_verify_pci_e_info(hldev); | |
472 | if (status != VXGE_HW_OK) | |
473 | goto exit; | |
474 | } | |
40a3a915 | 475 | |
40a3a915 RV |
476 | exit: |
477 | return status; | |
478 | } | |
479 | ||
480 | /** | |
481 | * vxge_hw_device_hw_info_get - Get the hw information | |
482 | * Returns the vpath mask that has the bits set for each vpath allocated | |
483 | * for the driver, FW version information and the first mac addresse for | |
484 | * each vpath | |
485 | */ | |
486 | enum vxge_hw_status __devinit | |
487 | vxge_hw_device_hw_info_get(void __iomem *bar0, | |
488 | struct vxge_hw_device_hw_info *hw_info) | |
489 | { | |
490 | u32 i; | |
491 | u64 val64; | |
492 | struct vxge_hw_toc_reg __iomem *toc; | |
493 | struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg; | |
494 | struct vxge_hw_common_reg __iomem *common_reg; | |
495 | struct vxge_hw_vpath_reg __iomem *vpath_reg; | |
496 | struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; | |
497 | enum vxge_hw_status status; | |
498 | ||
499 | memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info)); | |
500 | ||
501 | toc = __vxge_hw_device_toc_get(bar0); | |
502 | if (toc == NULL) { | |
503 | status = VXGE_HW_ERR_CRITICAL; | |
504 | goto exit; | |
505 | } | |
506 | ||
507 | val64 = readq(&toc->toc_common_pointer); | |
508 | common_reg = (struct vxge_hw_common_reg __iomem *)(bar0 + val64); | |
509 | ||
510 | status = __vxge_hw_device_vpath_reset_in_prog_check( | |
511 | (u64 __iomem *)&common_reg->vpath_rst_in_prog); | |
512 | if (status != VXGE_HW_OK) | |
513 | goto exit; | |
514 | ||
515 | hw_info->vpath_mask = readq(&common_reg->vpath_assignments); | |
516 | ||
517 | val64 = readq(&common_reg->host_type_assignments); | |
518 | ||
519 | hw_info->host_type = | |
520 | (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64); | |
521 | ||
522 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
523 | ||
524 | if (!((hw_info->vpath_mask) & vxge_mBIT(i))) | |
525 | continue; | |
526 | ||
527 | val64 = readq(&toc->toc_vpmgmt_pointer[i]); | |
528 | ||
529 | vpmgmt_reg = (struct vxge_hw_vpmgmt_reg __iomem *) | |
530 | (bar0 + val64); | |
531 | ||
532 | hw_info->func_id = __vxge_hw_vpath_func_id_get(i, vpmgmt_reg); | |
533 | if (__vxge_hw_device_access_rights_get(hw_info->host_type, | |
534 | hw_info->func_id) & | |
535 | VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) { | |
536 | ||
537 | val64 = readq(&toc->toc_mrpcim_pointer); | |
538 | ||
539 | mrpcim_reg = (struct vxge_hw_mrpcim_reg __iomem *) | |
540 | (bar0 + val64); | |
541 | ||
542 | writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask); | |
543 | wmb(); | |
544 | } | |
545 | ||
546 | val64 = readq(&toc->toc_vpath_pointer[i]); | |
547 | ||
548 | vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64); | |
549 | ||
550 | hw_info->function_mode = | |
551 | __vxge_hw_vpath_pci_func_mode_get(i, vpath_reg); | |
552 | ||
553 | status = __vxge_hw_vpath_fw_ver_get(i, vpath_reg, hw_info); | |
554 | if (status != VXGE_HW_OK) | |
555 | goto exit; | |
556 | ||
557 | status = __vxge_hw_vpath_card_info_get(i, vpath_reg, hw_info); | |
558 | if (status != VXGE_HW_OK) | |
559 | goto exit; | |
560 | ||
561 | break; | |
562 | } | |
563 | ||
564 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
565 | ||
566 | if (!((hw_info->vpath_mask) & vxge_mBIT(i))) | |
567 | continue; | |
568 | ||
569 | val64 = readq(&toc->toc_vpath_pointer[i]); | |
570 | vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64); | |
571 | ||
572 | status = __vxge_hw_vpath_addr_get(i, vpath_reg, | |
573 | hw_info->mac_addrs[i], | |
574 | hw_info->mac_addr_masks[i]); | |
575 | if (status != VXGE_HW_OK) | |
576 | goto exit; | |
577 | } | |
578 | exit: | |
579 | return status; | |
580 | } | |
581 | ||
582 | /* | |
583 | * vxge_hw_device_initialize - Initialize Titan device. | |
584 | * Initialize Titan device. Note that all the arguments of this public API | |
585 | * are 'IN', including @hldev. Driver cooperates with | |
586 | * OS to find new Titan device, locate its PCI and memory spaces. | |
587 | * | |
588 | * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW | |
589 | * to enable the latter to perform Titan hardware initialization. | |
590 | */ | |
591 | enum vxge_hw_status __devinit | |
592 | vxge_hw_device_initialize( | |
593 | struct __vxge_hw_device **devh, | |
594 | struct vxge_hw_device_attr *attr, | |
595 | struct vxge_hw_device_config *device_config) | |
596 | { | |
597 | u32 i; | |
598 | u32 nblocks = 0; | |
599 | struct __vxge_hw_device *hldev = NULL; | |
600 | enum vxge_hw_status status = VXGE_HW_OK; | |
601 | ||
602 | status = __vxge_hw_device_config_check(device_config); | |
603 | if (status != VXGE_HW_OK) | |
604 | goto exit; | |
605 | ||
606 | hldev = (struct __vxge_hw_device *) | |
607 | vmalloc(sizeof(struct __vxge_hw_device)); | |
608 | if (hldev == NULL) { | |
609 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
610 | goto exit; | |
611 | } | |
612 | ||
613 | memset(hldev, 0, sizeof(struct __vxge_hw_device)); | |
614 | hldev->magic = VXGE_HW_DEVICE_MAGIC; | |
615 | ||
616 | vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL); | |
617 | ||
618 | /* apply config */ | |
619 | memcpy(&hldev->config, device_config, | |
620 | sizeof(struct vxge_hw_device_config)); | |
621 | ||
622 | hldev->bar0 = attr->bar0; | |
40a3a915 RV |
623 | hldev->pdev = attr->pdev; |
624 | ||
625 | hldev->uld_callbacks.link_up = attr->uld_callbacks.link_up; | |
626 | hldev->uld_callbacks.link_down = attr->uld_callbacks.link_down; | |
627 | hldev->uld_callbacks.crit_err = attr->uld_callbacks.crit_err; | |
628 | ||
629 | __vxge_hw_device_pci_e_init(hldev); | |
630 | ||
631 | status = __vxge_hw_device_reg_addr_get(hldev); | |
aaffbd9f SH |
632 | if (status != VXGE_HW_OK) { |
633 | vfree(hldev); | |
40a3a915 | 634 | goto exit; |
aaffbd9f | 635 | } |
40a3a915 RV |
636 | __vxge_hw_device_id_get(hldev); |
637 | ||
638 | __vxge_hw_device_host_info_get(hldev); | |
639 | ||
640 | /* Incrementing for stats blocks */ | |
641 | nblocks++; | |
642 | ||
643 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
644 | ||
645 | if (!(hldev->vpath_assignments & vxge_mBIT(i))) | |
646 | continue; | |
647 | ||
648 | if (device_config->vp_config[i].ring.enable == | |
649 | VXGE_HW_RING_ENABLE) | |
650 | nblocks += device_config->vp_config[i].ring.ring_blocks; | |
651 | ||
652 | if (device_config->vp_config[i].fifo.enable == | |
653 | VXGE_HW_FIFO_ENABLE) | |
654 | nblocks += device_config->vp_config[i].fifo.fifo_blocks; | |
655 | nblocks++; | |
656 | } | |
657 | ||
658 | if (__vxge_hw_blockpool_create(hldev, | |
659 | &hldev->block_pool, | |
660 | device_config->dma_blockpool_initial + nblocks, | |
661 | device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) { | |
662 | ||
663 | vxge_hw_device_terminate(hldev); | |
664 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
665 | goto exit; | |
666 | } | |
667 | ||
668 | status = __vxge_hw_device_initialize(hldev); | |
669 | ||
670 | if (status != VXGE_HW_OK) { | |
671 | vxge_hw_device_terminate(hldev); | |
672 | goto exit; | |
673 | } | |
674 | ||
675 | *devh = hldev; | |
676 | exit: | |
677 | return status; | |
678 | } | |
679 | ||
680 | /* | |
681 | * vxge_hw_device_terminate - Terminate Titan device. | |
682 | * Terminate HW device. | |
683 | */ | |
684 | void | |
685 | vxge_hw_device_terminate(struct __vxge_hw_device *hldev) | |
686 | { | |
687 | vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC); | |
688 | ||
689 | hldev->magic = VXGE_HW_DEVICE_DEAD; | |
690 | __vxge_hw_blockpool_destroy(&hldev->block_pool); | |
691 | vfree(hldev); | |
692 | } | |
693 | ||
694 | /* | |
695 | * vxge_hw_device_stats_get - Get the device hw statistics. | |
696 | * Returns the vpath h/w stats for the device. | |
697 | */ | |
698 | enum vxge_hw_status | |
699 | vxge_hw_device_stats_get(struct __vxge_hw_device *hldev, | |
700 | struct vxge_hw_device_stats_hw_info *hw_stats) | |
701 | { | |
702 | u32 i; | |
703 | enum vxge_hw_status status = VXGE_HW_OK; | |
704 | ||
705 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
706 | ||
707 | if (!(hldev->vpaths_deployed & vxge_mBIT(i)) || | |
708 | (hldev->virtual_paths[i].vp_open == | |
709 | VXGE_HW_VP_NOT_OPEN)) | |
710 | continue; | |
711 | ||
712 | memcpy(hldev->virtual_paths[i].hw_stats_sav, | |
713 | hldev->virtual_paths[i].hw_stats, | |
714 | sizeof(struct vxge_hw_vpath_stats_hw_info)); | |
715 | ||
716 | status = __vxge_hw_vpath_stats_get( | |
717 | &hldev->virtual_paths[i], | |
718 | hldev->virtual_paths[i].hw_stats); | |
719 | } | |
720 | ||
721 | memcpy(hw_stats, &hldev->stats.hw_dev_info_stats, | |
722 | sizeof(struct vxge_hw_device_stats_hw_info)); | |
723 | ||
724 | return status; | |
725 | } | |
726 | ||
727 | /* | |
728 | * vxge_hw_driver_stats_get - Get the device sw statistics. | |
729 | * Returns the vpath s/w stats for the device. | |
730 | */ | |
731 | enum vxge_hw_status vxge_hw_driver_stats_get( | |
732 | struct __vxge_hw_device *hldev, | |
733 | struct vxge_hw_device_stats_sw_info *sw_stats) | |
734 | { | |
735 | enum vxge_hw_status status = VXGE_HW_OK; | |
736 | ||
737 | memcpy(sw_stats, &hldev->stats.sw_dev_info_stats, | |
738 | sizeof(struct vxge_hw_device_stats_sw_info)); | |
739 | ||
740 | return status; | |
741 | } | |
742 | ||
743 | /* | |
744 | * vxge_hw_mrpcim_stats_access - Access the statistics from the given location | |
745 | * and offset and perform an operation | |
746 | * Get the statistics from the given location and offset. | |
747 | */ | |
748 | enum vxge_hw_status | |
749 | vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev, | |
750 | u32 operation, u32 location, u32 offset, u64 *stat) | |
751 | { | |
752 | u64 val64; | |
753 | enum vxge_hw_status status = VXGE_HW_OK; | |
754 | ||
92cdd7c3 SH |
755 | status = __vxge_hw_device_is_privilaged(hldev->host_type, |
756 | hldev->func_id); | |
40a3a915 RV |
757 | if (status != VXGE_HW_OK) |
758 | goto exit; | |
759 | ||
760 | val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) | | |
761 | VXGE_HW_XMAC_STATS_SYS_CMD_STROBE | | |
762 | VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) | | |
763 | VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset); | |
764 | ||
765 | status = __vxge_hw_pio_mem_write64(val64, | |
766 | &hldev->mrpcim_reg->xmac_stats_sys_cmd, | |
767 | VXGE_HW_XMAC_STATS_SYS_CMD_STROBE, | |
768 | hldev->config.device_poll_millis); | |
769 | ||
770 | if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ)) | |
771 | *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data); | |
772 | else | |
773 | *stat = 0; | |
774 | exit: | |
775 | return status; | |
776 | } | |
777 | ||
778 | /* | |
779 | * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port | |
780 | * Get the Statistics on aggregate port | |
781 | */ | |
782 | enum vxge_hw_status | |
783 | vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port, | |
784 | struct vxge_hw_xmac_aggr_stats *aggr_stats) | |
785 | { | |
786 | u64 *val64; | |
787 | int i; | |
788 | u32 offset = VXGE_HW_STATS_AGGRn_OFFSET; | |
789 | enum vxge_hw_status status = VXGE_HW_OK; | |
790 | ||
791 | val64 = (u64 *)aggr_stats; | |
792 | ||
92cdd7c3 SH |
793 | status = __vxge_hw_device_is_privilaged(hldev->host_type, |
794 | hldev->func_id); | |
40a3a915 RV |
795 | if (status != VXGE_HW_OK) |
796 | goto exit; | |
797 | ||
798 | for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) { | |
799 | status = vxge_hw_mrpcim_stats_access(hldev, | |
800 | VXGE_HW_STATS_OP_READ, | |
801 | VXGE_HW_STATS_LOC_AGGR, | |
802 | ((offset + (104 * port)) >> 3), val64); | |
803 | if (status != VXGE_HW_OK) | |
804 | goto exit; | |
805 | ||
806 | offset += 8; | |
807 | val64++; | |
808 | } | |
809 | exit: | |
810 | return status; | |
811 | } | |
812 | ||
813 | /* | |
814 | * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port | |
815 | * Get the Statistics on port | |
816 | */ | |
817 | enum vxge_hw_status | |
818 | vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port, | |
819 | struct vxge_hw_xmac_port_stats *port_stats) | |
820 | { | |
821 | u64 *val64; | |
822 | enum vxge_hw_status status = VXGE_HW_OK; | |
823 | int i; | |
824 | u32 offset = 0x0; | |
825 | val64 = (u64 *) port_stats; | |
826 | ||
92cdd7c3 SH |
827 | status = __vxge_hw_device_is_privilaged(hldev->host_type, |
828 | hldev->func_id); | |
40a3a915 RV |
829 | if (status != VXGE_HW_OK) |
830 | goto exit; | |
831 | ||
832 | for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) { | |
833 | status = vxge_hw_mrpcim_stats_access(hldev, | |
834 | VXGE_HW_STATS_OP_READ, | |
835 | VXGE_HW_STATS_LOC_AGGR, | |
836 | ((offset + (608 * port)) >> 3), val64); | |
837 | if (status != VXGE_HW_OK) | |
838 | goto exit; | |
839 | ||
840 | offset += 8; | |
841 | val64++; | |
842 | } | |
843 | ||
844 | exit: | |
845 | return status; | |
846 | } | |
847 | ||
848 | /* | |
849 | * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics | |
850 | * Get the XMAC Statistics | |
851 | */ | |
852 | enum vxge_hw_status | |
853 | vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev, | |
854 | struct vxge_hw_xmac_stats *xmac_stats) | |
855 | { | |
856 | enum vxge_hw_status status = VXGE_HW_OK; | |
857 | u32 i; | |
858 | ||
859 | status = vxge_hw_device_xmac_aggr_stats_get(hldev, | |
860 | 0, &xmac_stats->aggr_stats[0]); | |
861 | ||
862 | if (status != VXGE_HW_OK) | |
863 | goto exit; | |
864 | ||
865 | status = vxge_hw_device_xmac_aggr_stats_get(hldev, | |
866 | 1, &xmac_stats->aggr_stats[1]); | |
867 | if (status != VXGE_HW_OK) | |
868 | goto exit; | |
869 | ||
870 | for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) { | |
871 | ||
872 | status = vxge_hw_device_xmac_port_stats_get(hldev, | |
873 | i, &xmac_stats->port_stats[i]); | |
874 | if (status != VXGE_HW_OK) | |
875 | goto exit; | |
876 | } | |
877 | ||
878 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
879 | ||
880 | if (!(hldev->vpaths_deployed & vxge_mBIT(i))) | |
881 | continue; | |
882 | ||
883 | status = __vxge_hw_vpath_xmac_tx_stats_get( | |
884 | &hldev->virtual_paths[i], | |
885 | &xmac_stats->vpath_tx_stats[i]); | |
886 | if (status != VXGE_HW_OK) | |
887 | goto exit; | |
888 | ||
889 | status = __vxge_hw_vpath_xmac_rx_stats_get( | |
890 | &hldev->virtual_paths[i], | |
891 | &xmac_stats->vpath_rx_stats[i]); | |
892 | if (status != VXGE_HW_OK) | |
893 | goto exit; | |
894 | } | |
895 | exit: | |
896 | return status; | |
897 | } | |
898 | ||
899 | /* | |
900 | * vxge_hw_device_debug_set - Set the debug module, level and timestamp | |
901 | * This routine is used to dynamically change the debug output | |
902 | */ | |
903 | void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev, | |
904 | enum vxge_debug_level level, u32 mask) | |
905 | { | |
906 | if (hldev == NULL) | |
907 | return; | |
908 | ||
909 | #if defined(VXGE_DEBUG_TRACE_MASK) || \ | |
910 | defined(VXGE_DEBUG_ERR_MASK) | |
911 | hldev->debug_module_mask = mask; | |
912 | hldev->debug_level = level; | |
913 | #endif | |
914 | ||
915 | #if defined(VXGE_DEBUG_ERR_MASK) | |
916 | hldev->level_err = level & VXGE_ERR; | |
917 | #endif | |
918 | ||
919 | #if defined(VXGE_DEBUG_TRACE_MASK) | |
920 | hldev->level_trace = level & VXGE_TRACE; | |
921 | #endif | |
922 | } | |
923 | ||
924 | /* | |
925 | * vxge_hw_device_error_level_get - Get the error level | |
926 | * This routine returns the current error level set | |
927 | */ | |
928 | u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev) | |
929 | { | |
930 | #if defined(VXGE_DEBUG_ERR_MASK) | |
931 | if (hldev == NULL) | |
932 | return VXGE_ERR; | |
933 | else | |
934 | return hldev->level_err; | |
935 | #else | |
936 | return 0; | |
937 | #endif | |
938 | } | |
939 | ||
940 | /* | |
941 | * vxge_hw_device_trace_level_get - Get the trace level | |
942 | * This routine returns the current trace level set | |
943 | */ | |
944 | u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev) | |
945 | { | |
946 | #if defined(VXGE_DEBUG_TRACE_MASK) | |
947 | if (hldev == NULL) | |
948 | return VXGE_TRACE; | |
949 | else | |
950 | return hldev->level_trace; | |
951 | #else | |
952 | return 0; | |
953 | #endif | |
954 | } | |
955 | /* | |
956 | * vxge_hw_device_debug_mask_get - Get the debug mask | |
957 | * This routine returns the current debug mask set | |
958 | */ | |
959 | u32 vxge_hw_device_debug_mask_get(struct __vxge_hw_device *hldev) | |
960 | { | |
961 | #if defined(VXGE_DEBUG_TRACE_MASK) || defined(VXGE_DEBUG_ERR_MASK) | |
962 | if (hldev == NULL) | |
963 | return 0; | |
964 | return hldev->debug_module_mask; | |
965 | #else | |
966 | return 0; | |
967 | #endif | |
968 | } | |
969 | ||
970 | /* | |
971 | * vxge_hw_getpause_data -Pause frame frame generation and reception. | |
972 | * Returns the Pause frame generation and reception capability of the NIC. | |
973 | */ | |
974 | enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev, | |
975 | u32 port, u32 *tx, u32 *rx) | |
976 | { | |
977 | u64 val64; | |
978 | enum vxge_hw_status status = VXGE_HW_OK; | |
979 | ||
980 | if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) { | |
981 | status = VXGE_HW_ERR_INVALID_DEVICE; | |
982 | goto exit; | |
983 | } | |
984 | ||
985 | if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) { | |
986 | status = VXGE_HW_ERR_INVALID_PORT; | |
987 | goto exit; | |
988 | } | |
989 | ||
990 | if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) { | |
991 | status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; | |
992 | goto exit; | |
993 | } | |
994 | ||
995 | val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); | |
996 | if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN) | |
997 | *tx = 1; | |
998 | if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN) | |
999 | *rx = 1; | |
1000 | exit: | |
1001 | return status; | |
1002 | } | |
1003 | ||
1004 | /* | |
1005 | * vxge_hw_device_setpause_data - set/reset pause frame generation. | |
1006 | * It can be used to set or reset Pause frame generation or reception | |
1007 | * support of the NIC. | |
1008 | */ | |
1009 | ||
1010 | enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev, | |
1011 | u32 port, u32 tx, u32 rx) | |
1012 | { | |
1013 | u64 val64; | |
1014 | enum vxge_hw_status status = VXGE_HW_OK; | |
1015 | ||
1016 | if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) { | |
1017 | status = VXGE_HW_ERR_INVALID_DEVICE; | |
1018 | goto exit; | |
1019 | } | |
1020 | ||
1021 | if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) { | |
1022 | status = VXGE_HW_ERR_INVALID_PORT; | |
1023 | goto exit; | |
1024 | } | |
1025 | ||
92cdd7c3 SH |
1026 | status = __vxge_hw_device_is_privilaged(hldev->host_type, |
1027 | hldev->func_id); | |
40a3a915 RV |
1028 | if (status != VXGE_HW_OK) |
1029 | goto exit; | |
1030 | ||
1031 | val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); | |
1032 | if (tx) | |
1033 | val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN; | |
1034 | else | |
1035 | val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN; | |
1036 | if (rx) | |
1037 | val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN; | |
1038 | else | |
1039 | val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN; | |
1040 | ||
1041 | writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]); | |
1042 | exit: | |
1043 | return status; | |
1044 | } | |
1045 | ||
1046 | u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev) | |
1047 | { | |
1048 | int link_width, exp_cap; | |
1049 | u16 lnk; | |
1050 | ||
1051 | exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP); | |
1052 | pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk); | |
1053 | link_width = (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4; | |
1054 | return link_width; | |
1055 | } | |
1056 | ||
1057 | /* | |
1058 | * __vxge_hw_ring_block_memblock_idx - Return the memblock index | |
1059 | * This function returns the index of memory block | |
1060 | */ | |
1061 | static inline u32 | |
1062 | __vxge_hw_ring_block_memblock_idx(u8 *block) | |
1063 | { | |
1064 | return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)); | |
1065 | } | |
1066 | ||
1067 | /* | |
1068 | * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index | |
1069 | * This function sets index to a memory block | |
1070 | */ | |
1071 | static inline void | |
1072 | __vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx) | |
1073 | { | |
1074 | *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx; | |
1075 | } | |
1076 | ||
1077 | /* | |
1078 | * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer | |
1079 | * in RxD block | |
1080 | * Sets the next block pointer in RxD block | |
1081 | */ | |
1082 | static inline void | |
1083 | __vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next) | |
1084 | { | |
1085 | *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next; | |
1086 | } | |
1087 | ||
1088 | /* | |
1089 | * __vxge_hw_ring_first_block_address_get - Returns the dma address of the | |
1090 | * first block | |
1091 | * Returns the dma address of the first RxD block | |
1092 | */ | |
1093 | u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring) | |
1094 | { | |
1095 | struct vxge_hw_mempool_dma *dma_object; | |
1096 | ||
1097 | dma_object = ring->mempool->memblocks_dma_arr; | |
1098 | vxge_assert(dma_object != NULL); | |
1099 | ||
1100 | return dma_object->addr; | |
1101 | } | |
1102 | ||
1103 | /* | |
1104 | * __vxge_hw_ring_item_dma_addr - Return the dma address of an item | |
1105 | * This function returns the dma address of a given item | |
1106 | */ | |
1107 | static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh, | |
1108 | void *item) | |
1109 | { | |
1110 | u32 memblock_idx; | |
1111 | void *memblock; | |
1112 | struct vxge_hw_mempool_dma *memblock_dma_object; | |
1113 | ptrdiff_t dma_item_offset; | |
1114 | ||
1115 | /* get owner memblock index */ | |
1116 | memblock_idx = __vxge_hw_ring_block_memblock_idx(item); | |
1117 | ||
1118 | /* get owner memblock by memblock index */ | |
1119 | memblock = mempoolh->memblocks_arr[memblock_idx]; | |
1120 | ||
1121 | /* get memblock DMA object by memblock index */ | |
1122 | memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx; | |
1123 | ||
1124 | /* calculate offset in the memblock of this item */ | |
1125 | dma_item_offset = (u8 *)item - (u8 *)memblock; | |
1126 | ||
1127 | return memblock_dma_object->addr + dma_item_offset; | |
1128 | } | |
1129 | ||
1130 | /* | |
1131 | * __vxge_hw_ring_rxdblock_link - Link the RxD blocks | |
1132 | * This function returns the dma address of a given item | |
1133 | */ | |
1134 | static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh, | |
1135 | struct __vxge_hw_ring *ring, u32 from, | |
1136 | u32 to) | |
1137 | { | |
1138 | u8 *to_item , *from_item; | |
1139 | dma_addr_t to_dma; | |
1140 | ||
1141 | /* get "from" RxD block */ | |
1142 | from_item = mempoolh->items_arr[from]; | |
1143 | vxge_assert(from_item); | |
1144 | ||
1145 | /* get "to" RxD block */ | |
1146 | to_item = mempoolh->items_arr[to]; | |
1147 | vxge_assert(to_item); | |
1148 | ||
1149 | /* return address of the beginning of previous RxD block */ | |
1150 | to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item); | |
1151 | ||
1152 | /* set next pointer for this RxD block to point on | |
1153 | * previous item's DMA start address */ | |
1154 | __vxge_hw_ring_block_next_pointer_set(from_item, to_dma); | |
1155 | } | |
1156 | ||
1157 | /* | |
1158 | * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD | |
1159 | * block callback | |
1160 | * This function is callback passed to __vxge_hw_mempool_create to create memory | |
1161 | * pool for RxD block | |
1162 | */ | |
1163 | static void | |
1164 | __vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh, | |
1165 | u32 memblock_index, | |
1166 | struct vxge_hw_mempool_dma *dma_object, | |
1167 | u32 index, u32 is_last) | |
1168 | { | |
1169 | u32 i; | |
1170 | void *item = mempoolh->items_arr[index]; | |
1171 | struct __vxge_hw_ring *ring = | |
1172 | (struct __vxge_hw_ring *)mempoolh->userdata; | |
1173 | ||
1174 | /* format rxds array */ | |
1175 | for (i = 0; i < ring->rxds_per_block; i++) { | |
1176 | void *rxdblock_priv; | |
1177 | void *uld_priv; | |
1178 | struct vxge_hw_ring_rxd_1 *rxdp; | |
1179 | ||
1180 | u32 reserve_index = ring->channel.reserve_ptr - | |
1181 | (index * ring->rxds_per_block + i + 1); | |
1182 | u32 memblock_item_idx; | |
1183 | ||
1184 | ring->channel.reserve_arr[reserve_index] = ((u8 *)item) + | |
1185 | i * ring->rxd_size; | |
1186 | ||
1187 | /* Note: memblock_item_idx is index of the item within | |
1188 | * the memblock. For instance, in case of three RxD-blocks | |
1189 | * per memblock this value can be 0, 1 or 2. */ | |
1190 | rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh, | |
1191 | memblock_index, item, | |
1192 | &memblock_item_idx); | |
1193 | ||
1194 | rxdp = (struct vxge_hw_ring_rxd_1 *) | |
1195 | ring->channel.reserve_arr[reserve_index]; | |
1196 | ||
1197 | uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i); | |
1198 | ||
1199 | /* pre-format Host_Control */ | |
1200 | rxdp->host_control = (u64)(size_t)uld_priv; | |
1201 | } | |
1202 | ||
1203 | __vxge_hw_ring_block_memblock_idx_set(item, memblock_index); | |
1204 | ||
1205 | if (is_last) { | |
1206 | /* link last one with first one */ | |
1207 | __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0); | |
1208 | } | |
1209 | ||
1210 | if (index > 0) { | |
1211 | /* link this RxD block with previous one */ | |
1212 | __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index); | |
1213 | } | |
40a3a915 RV |
1214 | } |
1215 | ||
1216 | /* | |
3363276f | 1217 | * __vxge_hw_ring_replenish - Initial replenish of RxDs |
40a3a915 RV |
1218 | * This function replenishes the RxDs from reserve array to work array |
1219 | */ | |
1220 | enum vxge_hw_status | |
3363276f | 1221 | vxge_hw_ring_replenish(struct __vxge_hw_ring *ring) |
40a3a915 RV |
1222 | { |
1223 | void *rxd; | |
40a3a915 RV |
1224 | struct __vxge_hw_channel *channel; |
1225 | enum vxge_hw_status status = VXGE_HW_OK; | |
1226 | ||
1227 | channel = &ring->channel; | |
1228 | ||
1229 | while (vxge_hw_channel_dtr_count(channel) > 0) { | |
1230 | ||
1231 | status = vxge_hw_ring_rxd_reserve(ring, &rxd); | |
1232 | ||
1233 | vxge_assert(status == VXGE_HW_OK); | |
1234 | ||
1235 | if (ring->rxd_init) { | |
1236 | status = ring->rxd_init(rxd, channel->userdata); | |
1237 | if (status != VXGE_HW_OK) { | |
1238 | vxge_hw_ring_rxd_free(ring, rxd); | |
1239 | goto exit; | |
1240 | } | |
1241 | } | |
1242 | ||
1243 | vxge_hw_ring_rxd_post(ring, rxd); | |
40a3a915 RV |
1244 | } |
1245 | status = VXGE_HW_OK; | |
1246 | exit: | |
1247 | return status; | |
1248 | } | |
1249 | ||
1250 | /* | |
1251 | * __vxge_hw_ring_create - Create a Ring | |
1252 | * This function creates Ring and initializes it. | |
1253 | * | |
1254 | */ | |
1255 | enum vxge_hw_status | |
1256 | __vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp, | |
1257 | struct vxge_hw_ring_attr *attr) | |
1258 | { | |
1259 | enum vxge_hw_status status = VXGE_HW_OK; | |
1260 | struct __vxge_hw_ring *ring; | |
1261 | u32 ring_length; | |
1262 | struct vxge_hw_ring_config *config; | |
1263 | struct __vxge_hw_device *hldev; | |
1264 | u32 vp_id; | |
1265 | struct vxge_hw_mempool_cbs ring_mp_callback; | |
1266 | ||
1267 | if ((vp == NULL) || (attr == NULL)) { | |
1268 | status = VXGE_HW_FAIL; | |
1269 | goto exit; | |
1270 | } | |
1271 | ||
1272 | hldev = vp->vpath->hldev; | |
1273 | vp_id = vp->vpath->vp_id; | |
1274 | ||
1275 | config = &hldev->config.vp_config[vp_id].ring; | |
1276 | ||
1277 | ring_length = config->ring_blocks * | |
1278 | vxge_hw_ring_rxds_per_block_get(config->buffer_mode); | |
1279 | ||
1280 | ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp, | |
1281 | VXGE_HW_CHANNEL_TYPE_RING, | |
1282 | ring_length, | |
1283 | attr->per_rxd_space, | |
1284 | attr->userdata); | |
1285 | ||
1286 | if (ring == NULL) { | |
1287 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1288 | goto exit; | |
1289 | } | |
1290 | ||
1291 | vp->vpath->ringh = ring; | |
1292 | ring->vp_id = vp_id; | |
1293 | ring->vp_reg = vp->vpath->vp_reg; | |
1294 | ring->common_reg = hldev->common_reg; | |
1295 | ring->stats = &vp->vpath->sw_stats->ring_stats; | |
1296 | ring->config = config; | |
1297 | ring->callback = attr->callback; | |
1298 | ring->rxd_init = attr->rxd_init; | |
1299 | ring->rxd_term = attr->rxd_term; | |
1300 | ring->buffer_mode = config->buffer_mode; | |
1301 | ring->rxds_limit = config->rxds_limit; | |
1302 | ||
1303 | ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode); | |
1304 | ring->rxd_priv_size = | |
1305 | sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space; | |
1306 | ring->per_rxd_space = attr->per_rxd_space; | |
1307 | ||
1308 | ring->rxd_priv_size = | |
1309 | ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) / | |
1310 | VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE; | |
1311 | ||
1312 | /* how many RxDs can fit into one block. Depends on configured | |
1313 | * buffer_mode. */ | |
1314 | ring->rxds_per_block = | |
1315 | vxge_hw_ring_rxds_per_block_get(config->buffer_mode); | |
1316 | ||
1317 | /* calculate actual RxD block private size */ | |
1318 | ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block; | |
1319 | ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc; | |
1320 | ring->mempool = __vxge_hw_mempool_create(hldev, | |
1321 | VXGE_HW_BLOCK_SIZE, | |
1322 | VXGE_HW_BLOCK_SIZE, | |
1323 | ring->rxdblock_priv_size, | |
1324 | ring->config->ring_blocks, | |
1325 | ring->config->ring_blocks, | |
1326 | &ring_mp_callback, | |
1327 | ring); | |
1328 | ||
1329 | if (ring->mempool == NULL) { | |
1330 | __vxge_hw_ring_delete(vp); | |
1331 | return VXGE_HW_ERR_OUT_OF_MEMORY; | |
1332 | } | |
1333 | ||
1334 | status = __vxge_hw_channel_initialize(&ring->channel); | |
1335 | if (status != VXGE_HW_OK) { | |
1336 | __vxge_hw_ring_delete(vp); | |
1337 | goto exit; | |
1338 | } | |
1339 | ||
1340 | /* Note: | |
1341 | * Specifying rxd_init callback means two things: | |
1342 | * 1) rxds need to be initialized by driver at channel-open time; | |
1343 | * 2) rxds need to be posted at channel-open time | |
1344 | * (that's what the initial_replenish() below does) | |
1345 | * Currently we don't have a case when the 1) is done without the 2). | |
1346 | */ | |
1347 | if (ring->rxd_init) { | |
3363276f | 1348 | status = vxge_hw_ring_replenish(ring); |
40a3a915 RV |
1349 | if (status != VXGE_HW_OK) { |
1350 | __vxge_hw_ring_delete(vp); | |
1351 | goto exit; | |
1352 | } | |
1353 | } | |
1354 | ||
1355 | /* initial replenish will increment the counter in its post() routine, | |
1356 | * we have to reset it */ | |
1357 | ring->stats->common_stats.usage_cnt = 0; | |
1358 | exit: | |
1359 | return status; | |
1360 | } | |
1361 | ||
1362 | /* | |
1363 | * __vxge_hw_ring_abort - Returns the RxD | |
1364 | * This function terminates the RxDs of ring | |
1365 | */ | |
1366 | enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring) | |
1367 | { | |
1368 | void *rxdh; | |
1369 | struct __vxge_hw_channel *channel; | |
1370 | ||
1371 | channel = &ring->channel; | |
1372 | ||
1373 | for (;;) { | |
1374 | vxge_hw_channel_dtr_try_complete(channel, &rxdh); | |
1375 | ||
1376 | if (rxdh == NULL) | |
1377 | break; | |
1378 | ||
1379 | vxge_hw_channel_dtr_complete(channel); | |
1380 | ||
1381 | if (ring->rxd_term) | |
1382 | ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED, | |
1383 | channel->userdata); | |
1384 | ||
1385 | vxge_hw_channel_dtr_free(channel, rxdh); | |
1386 | } | |
1387 | ||
1388 | return VXGE_HW_OK; | |
1389 | } | |
1390 | ||
1391 | /* | |
1392 | * __vxge_hw_ring_reset - Resets the ring | |
1393 | * This function resets the ring during vpath reset operation | |
1394 | */ | |
1395 | enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring) | |
1396 | { | |
1397 | enum vxge_hw_status status = VXGE_HW_OK; | |
1398 | struct __vxge_hw_channel *channel; | |
1399 | ||
1400 | channel = &ring->channel; | |
1401 | ||
1402 | __vxge_hw_ring_abort(ring); | |
1403 | ||
1404 | status = __vxge_hw_channel_reset(channel); | |
1405 | ||
1406 | if (status != VXGE_HW_OK) | |
1407 | goto exit; | |
1408 | ||
1409 | if (ring->rxd_init) { | |
3363276f | 1410 | status = vxge_hw_ring_replenish(ring); |
40a3a915 RV |
1411 | if (status != VXGE_HW_OK) |
1412 | goto exit; | |
1413 | } | |
1414 | exit: | |
1415 | return status; | |
1416 | } | |
1417 | ||
1418 | /* | |
1419 | * __vxge_hw_ring_delete - Removes the ring | |
1420 | * This function freeup the memory pool and removes the ring | |
1421 | */ | |
1422 | enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp) | |
1423 | { | |
1424 | struct __vxge_hw_ring *ring = vp->vpath->ringh; | |
1425 | ||
1426 | __vxge_hw_ring_abort(ring); | |
1427 | ||
1428 | if (ring->mempool) | |
1429 | __vxge_hw_mempool_destroy(ring->mempool); | |
1430 | ||
1431 | vp->vpath->ringh = NULL; | |
1432 | __vxge_hw_channel_free(&ring->channel); | |
1433 | ||
1434 | return VXGE_HW_OK; | |
1435 | } | |
1436 | ||
1437 | /* | |
1438 | * __vxge_hw_mempool_grow | |
1439 | * Will resize mempool up to %num_allocate value. | |
1440 | */ | |
1441 | enum vxge_hw_status | |
1442 | __vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate, | |
1443 | u32 *num_allocated) | |
1444 | { | |
1445 | u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0; | |
1446 | u32 n_items = mempool->items_per_memblock; | |
1447 | u32 start_block_idx = mempool->memblocks_allocated; | |
1448 | u32 end_block_idx = mempool->memblocks_allocated + num_allocate; | |
1449 | enum vxge_hw_status status = VXGE_HW_OK; | |
1450 | ||
1451 | *num_allocated = 0; | |
1452 | ||
1453 | if (end_block_idx > mempool->memblocks_max) { | |
1454 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1455 | goto exit; | |
1456 | } | |
1457 | ||
1458 | for (i = start_block_idx; i < end_block_idx; i++) { | |
1459 | u32 j; | |
1460 | u32 is_last = ((end_block_idx - 1) == i); | |
1461 | struct vxge_hw_mempool_dma *dma_object = | |
1462 | mempool->memblocks_dma_arr + i; | |
1463 | void *the_memblock; | |
1464 | ||
1465 | /* allocate memblock's private part. Each DMA memblock | |
1466 | * has a space allocated for item's private usage upon | |
1467 | * mempool's user request. Each time mempool grows, it will | |
1468 | * allocate new memblock and its private part at once. | |
1469 | * This helps to minimize memory usage a lot. */ | |
1470 | mempool->memblocks_priv_arr[i] = | |
1471 | vmalloc(mempool->items_priv_size * n_items); | |
1472 | if (mempool->memblocks_priv_arr[i] == NULL) { | |
1473 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1474 | goto exit; | |
1475 | } | |
1476 | ||
1477 | memset(mempool->memblocks_priv_arr[i], 0, | |
1478 | mempool->items_priv_size * n_items); | |
1479 | ||
1480 | /* allocate DMA-capable memblock */ | |
1481 | mempool->memblocks_arr[i] = | |
1482 | __vxge_hw_blockpool_malloc(mempool->devh, | |
1483 | mempool->memblock_size, dma_object); | |
1484 | if (mempool->memblocks_arr[i] == NULL) { | |
1485 | vfree(mempool->memblocks_priv_arr[i]); | |
1486 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1487 | goto exit; | |
1488 | } | |
1489 | ||
1490 | (*num_allocated)++; | |
1491 | mempool->memblocks_allocated++; | |
1492 | ||
1493 | memset(mempool->memblocks_arr[i], 0, mempool->memblock_size); | |
1494 | ||
1495 | the_memblock = mempool->memblocks_arr[i]; | |
1496 | ||
1497 | /* fill the items hash array */ | |
1498 | for (j = 0; j < n_items; j++) { | |
1499 | u32 index = i * n_items + j; | |
1500 | ||
1501 | if (first_time && index >= mempool->items_initial) | |
1502 | break; | |
1503 | ||
1504 | mempool->items_arr[index] = | |
1505 | ((char *)the_memblock + j*mempool->item_size); | |
1506 | ||
1507 | /* let caller to do more job on each item */ | |
1508 | if (mempool->item_func_alloc != NULL) | |
1509 | mempool->item_func_alloc(mempool, i, | |
1510 | dma_object, index, is_last); | |
1511 | ||
1512 | mempool->items_current = index + 1; | |
1513 | } | |
1514 | ||
1515 | if (first_time && mempool->items_current == | |
1516 | mempool->items_initial) | |
1517 | break; | |
1518 | } | |
1519 | exit: | |
1520 | return status; | |
1521 | } | |
1522 | ||
1523 | /* | |
1524 | * vxge_hw_mempool_create | |
1525 | * This function will create memory pool object. Pool may grow but will | |
1526 | * never shrink. Pool consists of number of dynamically allocated blocks | |
1527 | * with size enough to hold %items_initial number of items. Memory is | |
1528 | * DMA-able but client must map/unmap before interoperating with the device. | |
1529 | */ | |
1530 | struct vxge_hw_mempool* | |
1531 | __vxge_hw_mempool_create( | |
1532 | struct __vxge_hw_device *devh, | |
1533 | u32 memblock_size, | |
1534 | u32 item_size, | |
1535 | u32 items_priv_size, | |
1536 | u32 items_initial, | |
1537 | u32 items_max, | |
1538 | struct vxge_hw_mempool_cbs *mp_callback, | |
1539 | void *userdata) | |
1540 | { | |
1541 | enum vxge_hw_status status = VXGE_HW_OK; | |
1542 | u32 memblocks_to_allocate; | |
1543 | struct vxge_hw_mempool *mempool = NULL; | |
1544 | u32 allocated; | |
1545 | ||
1546 | if (memblock_size < item_size) { | |
1547 | status = VXGE_HW_FAIL; | |
1548 | goto exit; | |
1549 | } | |
1550 | ||
1551 | mempool = (struct vxge_hw_mempool *) | |
1552 | vmalloc(sizeof(struct vxge_hw_mempool)); | |
1553 | if (mempool == NULL) { | |
1554 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1555 | goto exit; | |
1556 | } | |
1557 | memset(mempool, 0, sizeof(struct vxge_hw_mempool)); | |
1558 | ||
1559 | mempool->devh = devh; | |
1560 | mempool->memblock_size = memblock_size; | |
1561 | mempool->items_max = items_max; | |
1562 | mempool->items_initial = items_initial; | |
1563 | mempool->item_size = item_size; | |
1564 | mempool->items_priv_size = items_priv_size; | |
1565 | mempool->item_func_alloc = mp_callback->item_func_alloc; | |
1566 | mempool->userdata = userdata; | |
1567 | ||
1568 | mempool->memblocks_allocated = 0; | |
1569 | ||
1570 | mempool->items_per_memblock = memblock_size / item_size; | |
1571 | ||
1572 | mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) / | |
1573 | mempool->items_per_memblock; | |
1574 | ||
1575 | /* allocate array of memblocks */ | |
1576 | mempool->memblocks_arr = | |
1577 | (void **) vmalloc(sizeof(void *) * mempool->memblocks_max); | |
1578 | if (mempool->memblocks_arr == NULL) { | |
1579 | __vxge_hw_mempool_destroy(mempool); | |
1580 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1581 | mempool = NULL; | |
1582 | goto exit; | |
1583 | } | |
1584 | memset(mempool->memblocks_arr, 0, | |
1585 | sizeof(void *) * mempool->memblocks_max); | |
1586 | ||
1587 | /* allocate array of private parts of items per memblocks */ | |
1588 | mempool->memblocks_priv_arr = | |
1589 | (void **) vmalloc(sizeof(void *) * mempool->memblocks_max); | |
1590 | if (mempool->memblocks_priv_arr == NULL) { | |
1591 | __vxge_hw_mempool_destroy(mempool); | |
1592 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1593 | mempool = NULL; | |
1594 | goto exit; | |
1595 | } | |
1596 | memset(mempool->memblocks_priv_arr, 0, | |
1597 | sizeof(void *) * mempool->memblocks_max); | |
1598 | ||
1599 | /* allocate array of memblocks DMA objects */ | |
1600 | mempool->memblocks_dma_arr = (struct vxge_hw_mempool_dma *) | |
1601 | vmalloc(sizeof(struct vxge_hw_mempool_dma) * | |
1602 | mempool->memblocks_max); | |
1603 | ||
1604 | if (mempool->memblocks_dma_arr == NULL) { | |
1605 | __vxge_hw_mempool_destroy(mempool); | |
1606 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1607 | mempool = NULL; | |
1608 | goto exit; | |
1609 | } | |
1610 | memset(mempool->memblocks_dma_arr, 0, | |
1611 | sizeof(struct vxge_hw_mempool_dma) * | |
1612 | mempool->memblocks_max); | |
1613 | ||
1614 | /* allocate hash array of items */ | |
1615 | mempool->items_arr = | |
1616 | (void **) vmalloc(sizeof(void *) * mempool->items_max); | |
1617 | if (mempool->items_arr == NULL) { | |
1618 | __vxge_hw_mempool_destroy(mempool); | |
1619 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1620 | mempool = NULL; | |
1621 | goto exit; | |
1622 | } | |
1623 | memset(mempool->items_arr, 0, sizeof(void *) * mempool->items_max); | |
1624 | ||
1625 | /* calculate initial number of memblocks */ | |
1626 | memblocks_to_allocate = (mempool->items_initial + | |
1627 | mempool->items_per_memblock - 1) / | |
1628 | mempool->items_per_memblock; | |
1629 | ||
1630 | /* pre-allocate the mempool */ | |
1631 | status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate, | |
1632 | &allocated); | |
1633 | if (status != VXGE_HW_OK) { | |
1634 | __vxge_hw_mempool_destroy(mempool); | |
1635 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
1636 | mempool = NULL; | |
1637 | goto exit; | |
1638 | } | |
1639 | ||
1640 | exit: | |
1641 | return mempool; | |
1642 | } | |
1643 | ||
1644 | /* | |
1645 | * vxge_hw_mempool_destroy | |
1646 | */ | |
1647 | void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool) | |
1648 | { | |
1649 | u32 i, j; | |
1650 | struct __vxge_hw_device *devh = mempool->devh; | |
1651 | ||
1652 | for (i = 0; i < mempool->memblocks_allocated; i++) { | |
1653 | struct vxge_hw_mempool_dma *dma_object; | |
1654 | ||
1655 | vxge_assert(mempool->memblocks_arr[i]); | |
1656 | vxge_assert(mempool->memblocks_dma_arr + i); | |
1657 | ||
1658 | dma_object = mempool->memblocks_dma_arr + i; | |
1659 | ||
1660 | for (j = 0; j < mempool->items_per_memblock; j++) { | |
1661 | u32 index = i * mempool->items_per_memblock + j; | |
1662 | ||
1663 | /* to skip last partially filled(if any) memblock */ | |
1664 | if (index >= mempool->items_current) | |
1665 | break; | |
1666 | } | |
1667 | ||
1668 | vfree(mempool->memblocks_priv_arr[i]); | |
1669 | ||
1670 | __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i], | |
1671 | mempool->memblock_size, dma_object); | |
1672 | } | |
1673 | ||
50d36a93 | 1674 | vfree(mempool->items_arr); |
40a3a915 | 1675 | |
50d36a93 | 1676 | vfree(mempool->memblocks_dma_arr); |
40a3a915 | 1677 | |
50d36a93 | 1678 | vfree(mempool->memblocks_priv_arr); |
40a3a915 | 1679 | |
50d36a93 | 1680 | vfree(mempool->memblocks_arr); |
40a3a915 RV |
1681 | |
1682 | vfree(mempool); | |
1683 | } | |
1684 | ||
1685 | /* | |
1686 | * __vxge_hw_device_fifo_config_check - Check fifo configuration. | |
1687 | * Check the fifo configuration | |
1688 | */ | |
1689 | enum vxge_hw_status | |
1690 | __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config) | |
1691 | { | |
1692 | if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) || | |
1693 | (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS)) | |
1694 | return VXGE_HW_BADCFG_FIFO_BLOCKS; | |
1695 | ||
1696 | return VXGE_HW_OK; | |
1697 | } | |
1698 | ||
1699 | /* | |
1700 | * __vxge_hw_device_vpath_config_check - Check vpath configuration. | |
1701 | * Check the vpath configuration | |
1702 | */ | |
1703 | enum vxge_hw_status | |
1704 | __vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config) | |
1705 | { | |
1706 | enum vxge_hw_status status; | |
1707 | ||
1708 | if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) || | |
1709 | (vp_config->min_bandwidth > | |
1710 | VXGE_HW_VPATH_BANDWIDTH_MAX)) | |
1711 | return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH; | |
1712 | ||
1713 | status = __vxge_hw_device_fifo_config_check(&vp_config->fifo); | |
1714 | if (status != VXGE_HW_OK) | |
1715 | return status; | |
1716 | ||
1717 | if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) && | |
1718 | ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) || | |
1719 | (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU))) | |
1720 | return VXGE_HW_BADCFG_VPATH_MTU; | |
1721 | ||
1722 | if ((vp_config->rpa_strip_vlan_tag != | |
1723 | VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) && | |
1724 | (vp_config->rpa_strip_vlan_tag != | |
1725 | VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) && | |
1726 | (vp_config->rpa_strip_vlan_tag != | |
1727 | VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE)) | |
1728 | return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG; | |
1729 | ||
1730 | return VXGE_HW_OK; | |
1731 | } | |
1732 | ||
1733 | /* | |
1734 | * __vxge_hw_device_config_check - Check device configuration. | |
1735 | * Check the device configuration | |
1736 | */ | |
1737 | enum vxge_hw_status | |
1738 | __vxge_hw_device_config_check(struct vxge_hw_device_config *new_config) | |
1739 | { | |
1740 | u32 i; | |
1741 | enum vxge_hw_status status; | |
1742 | ||
1743 | if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) && | |
1744 | (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) && | |
1745 | (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) && | |
1746 | (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF)) | |
1747 | return VXGE_HW_BADCFG_INTR_MODE; | |
1748 | ||
1749 | if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) && | |
1750 | (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE)) | |
1751 | return VXGE_HW_BADCFG_RTS_MAC_EN; | |
1752 | ||
1753 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
1754 | status = __vxge_hw_device_vpath_config_check( | |
1755 | &new_config->vp_config[i]); | |
1756 | if (status != VXGE_HW_OK) | |
1757 | return status; | |
1758 | } | |
1759 | ||
1760 | return VXGE_HW_OK; | |
1761 | } | |
1762 | ||
1763 | /* | |
1764 | * vxge_hw_device_config_default_get - Initialize device config with defaults. | |
1765 | * Initialize Titan device config with default values. | |
1766 | */ | |
1767 | enum vxge_hw_status __devinit | |
1768 | vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config) | |
1769 | { | |
1770 | u32 i; | |
1771 | ||
1772 | device_config->dma_blockpool_initial = | |
1773 | VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE; | |
1774 | device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE; | |
1775 | device_config->intr_mode = VXGE_HW_INTR_MODE_DEF; | |
1776 | device_config->rth_en = VXGE_HW_RTH_DEFAULT; | |
1777 | device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT; | |
1778 | device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS; | |
1779 | device_config->rts_mac_en = VXGE_HW_RTS_MAC_DEFAULT; | |
1780 | ||
1781 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
1782 | ||
1783 | device_config->vp_config[i].vp_id = i; | |
1784 | ||
1785 | device_config->vp_config[i].min_bandwidth = | |
1786 | VXGE_HW_VPATH_BANDWIDTH_DEFAULT; | |
1787 | ||
1788 | device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT; | |
1789 | ||
1790 | device_config->vp_config[i].ring.ring_blocks = | |
1791 | VXGE_HW_DEF_RING_BLOCKS; | |
1792 | ||
1793 | device_config->vp_config[i].ring.buffer_mode = | |
1794 | VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT; | |
1795 | ||
1796 | device_config->vp_config[i].ring.scatter_mode = | |
1797 | VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT; | |
1798 | ||
1799 | device_config->vp_config[i].ring.rxds_limit = | |
1800 | VXGE_HW_DEF_RING_RXDS_LIMIT; | |
1801 | ||
1802 | device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE; | |
1803 | ||
1804 | device_config->vp_config[i].fifo.fifo_blocks = | |
1805 | VXGE_HW_MIN_FIFO_BLOCKS; | |
1806 | ||
1807 | device_config->vp_config[i].fifo.max_frags = | |
1808 | VXGE_HW_MAX_FIFO_FRAGS; | |
1809 | ||
1810 | device_config->vp_config[i].fifo.memblock_size = | |
1811 | VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE; | |
1812 | ||
1813 | device_config->vp_config[i].fifo.alignment_size = | |
1814 | VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE; | |
1815 | ||
1816 | device_config->vp_config[i].fifo.intr = | |
1817 | VXGE_HW_FIFO_QUEUE_INTR_DEFAULT; | |
1818 | ||
1819 | device_config->vp_config[i].fifo.no_snoop_bits = | |
1820 | VXGE_HW_FIFO_NO_SNOOP_DEFAULT; | |
1821 | device_config->vp_config[i].tti.intr_enable = | |
1822 | VXGE_HW_TIM_INTR_DEFAULT; | |
1823 | ||
1824 | device_config->vp_config[i].tti.btimer_val = | |
1825 | VXGE_HW_USE_FLASH_DEFAULT; | |
1826 | ||
1827 | device_config->vp_config[i].tti.timer_ac_en = | |
1828 | VXGE_HW_USE_FLASH_DEFAULT; | |
1829 | ||
1830 | device_config->vp_config[i].tti.timer_ci_en = | |
1831 | VXGE_HW_USE_FLASH_DEFAULT; | |
1832 | ||
1833 | device_config->vp_config[i].tti.timer_ri_en = | |
1834 | VXGE_HW_USE_FLASH_DEFAULT; | |
1835 | ||
1836 | device_config->vp_config[i].tti.rtimer_val = | |
1837 | VXGE_HW_USE_FLASH_DEFAULT; | |
1838 | ||
1839 | device_config->vp_config[i].tti.util_sel = | |
1840 | VXGE_HW_USE_FLASH_DEFAULT; | |
1841 | ||
1842 | device_config->vp_config[i].tti.ltimer_val = | |
1843 | VXGE_HW_USE_FLASH_DEFAULT; | |
1844 | ||
1845 | device_config->vp_config[i].tti.urange_a = | |
1846 | VXGE_HW_USE_FLASH_DEFAULT; | |
1847 | ||
1848 | device_config->vp_config[i].tti.uec_a = | |
1849 | VXGE_HW_USE_FLASH_DEFAULT; | |
1850 | ||
1851 | device_config->vp_config[i].tti.urange_b = | |
1852 | VXGE_HW_USE_FLASH_DEFAULT; | |
1853 | ||
1854 | device_config->vp_config[i].tti.uec_b = | |
1855 | VXGE_HW_USE_FLASH_DEFAULT; | |
1856 | ||
1857 | device_config->vp_config[i].tti.urange_c = | |
1858 | VXGE_HW_USE_FLASH_DEFAULT; | |
1859 | ||
1860 | device_config->vp_config[i].tti.uec_c = | |
1861 | VXGE_HW_USE_FLASH_DEFAULT; | |
1862 | ||
1863 | device_config->vp_config[i].tti.uec_d = | |
1864 | VXGE_HW_USE_FLASH_DEFAULT; | |
1865 | ||
1866 | device_config->vp_config[i].rti.intr_enable = | |
1867 | VXGE_HW_TIM_INTR_DEFAULT; | |
1868 | ||
1869 | device_config->vp_config[i].rti.btimer_val = | |
1870 | VXGE_HW_USE_FLASH_DEFAULT; | |
1871 | ||
1872 | device_config->vp_config[i].rti.timer_ac_en = | |
1873 | VXGE_HW_USE_FLASH_DEFAULT; | |
1874 | ||
1875 | device_config->vp_config[i].rti.timer_ci_en = | |
1876 | VXGE_HW_USE_FLASH_DEFAULT; | |
1877 | ||
1878 | device_config->vp_config[i].rti.timer_ri_en = | |
1879 | VXGE_HW_USE_FLASH_DEFAULT; | |
1880 | ||
1881 | device_config->vp_config[i].rti.rtimer_val = | |
1882 | VXGE_HW_USE_FLASH_DEFAULT; | |
1883 | ||
1884 | device_config->vp_config[i].rti.util_sel = | |
1885 | VXGE_HW_USE_FLASH_DEFAULT; | |
1886 | ||
1887 | device_config->vp_config[i].rti.ltimer_val = | |
1888 | VXGE_HW_USE_FLASH_DEFAULT; | |
1889 | ||
1890 | device_config->vp_config[i].rti.urange_a = | |
1891 | VXGE_HW_USE_FLASH_DEFAULT; | |
1892 | ||
1893 | device_config->vp_config[i].rti.uec_a = | |
1894 | VXGE_HW_USE_FLASH_DEFAULT; | |
1895 | ||
1896 | device_config->vp_config[i].rti.urange_b = | |
1897 | VXGE_HW_USE_FLASH_DEFAULT; | |
1898 | ||
1899 | device_config->vp_config[i].rti.uec_b = | |
1900 | VXGE_HW_USE_FLASH_DEFAULT; | |
1901 | ||
1902 | device_config->vp_config[i].rti.urange_c = | |
1903 | VXGE_HW_USE_FLASH_DEFAULT; | |
1904 | ||
1905 | device_config->vp_config[i].rti.uec_c = | |
1906 | VXGE_HW_USE_FLASH_DEFAULT; | |
1907 | ||
1908 | device_config->vp_config[i].rti.uec_d = | |
1909 | VXGE_HW_USE_FLASH_DEFAULT; | |
1910 | ||
1911 | device_config->vp_config[i].mtu = | |
1912 | VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU; | |
1913 | ||
1914 | device_config->vp_config[i].rpa_strip_vlan_tag = | |
1915 | VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT; | |
1916 | } | |
1917 | ||
1918 | return VXGE_HW_OK; | |
1919 | } | |
1920 | ||
1921 | /* | |
1922 | * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion. | |
1923 | * Set the swapper bits appropriately for the lagacy section. | |
1924 | */ | |
1925 | enum vxge_hw_status | |
1926 | __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg) | |
1927 | { | |
1928 | u64 val64; | |
1929 | enum vxge_hw_status status = VXGE_HW_OK; | |
1930 | ||
1931 | val64 = readq(&legacy_reg->toc_swapper_fb); | |
1932 | ||
1933 | wmb(); | |
1934 | ||
1935 | switch (val64) { | |
1936 | ||
1937 | case VXGE_HW_SWAPPER_INITIAL_VALUE: | |
1938 | return status; | |
1939 | ||
1940 | case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED: | |
1941 | writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, | |
1942 | &legacy_reg->pifm_rd_swap_en); | |
1943 | writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, | |
1944 | &legacy_reg->pifm_rd_flip_en); | |
1945 | writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, | |
1946 | &legacy_reg->pifm_wr_swap_en); | |
1947 | writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, | |
1948 | &legacy_reg->pifm_wr_flip_en); | |
1949 | break; | |
1950 | ||
1951 | case VXGE_HW_SWAPPER_BYTE_SWAPPED: | |
1952 | writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE, | |
1953 | &legacy_reg->pifm_rd_swap_en); | |
1954 | writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE, | |
1955 | &legacy_reg->pifm_wr_swap_en); | |
1956 | break; | |
1957 | ||
1958 | case VXGE_HW_SWAPPER_BIT_FLIPPED: | |
1959 | writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE, | |
1960 | &legacy_reg->pifm_rd_flip_en); | |
1961 | writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE, | |
1962 | &legacy_reg->pifm_wr_flip_en); | |
1963 | break; | |
1964 | } | |
1965 | ||
1966 | wmb(); | |
1967 | ||
1968 | val64 = readq(&legacy_reg->toc_swapper_fb); | |
1969 | ||
1970 | if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE) | |
1971 | status = VXGE_HW_ERR_SWAPPER_CTRL; | |
1972 | ||
1973 | return status; | |
1974 | } | |
1975 | ||
1976 | /* | |
1977 | * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath. | |
1978 | * Set the swapper bits appropriately for the vpath. | |
1979 | */ | |
1980 | enum vxge_hw_status | |
1981 | __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg) | |
1982 | { | |
1983 | #ifndef __BIG_ENDIAN | |
1984 | u64 val64; | |
1985 | ||
1986 | val64 = readq(&vpath_reg->vpath_general_cfg1); | |
1987 | wmb(); | |
1988 | val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN; | |
1989 | writeq(val64, &vpath_reg->vpath_general_cfg1); | |
1990 | wmb(); | |
1991 | #endif | |
1992 | return VXGE_HW_OK; | |
1993 | } | |
1994 | ||
1995 | /* | |
1996 | * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc. | |
1997 | * Set the swapper bits appropriately for the vpath. | |
1998 | */ | |
1999 | enum vxge_hw_status | |
2000 | __vxge_hw_kdfc_swapper_set( | |
2001 | struct vxge_hw_legacy_reg __iomem *legacy_reg, | |
2002 | struct vxge_hw_vpath_reg __iomem *vpath_reg) | |
2003 | { | |
2004 | u64 val64; | |
2005 | ||
2006 | val64 = readq(&legacy_reg->pifm_wr_swap_en); | |
2007 | ||
2008 | if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) { | |
2009 | val64 = readq(&vpath_reg->kdfcctl_cfg0); | |
2010 | wmb(); | |
2011 | ||
2012 | val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 | | |
2013 | VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 | | |
2014 | VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2; | |
2015 | ||
2016 | writeq(val64, &vpath_reg->kdfcctl_cfg0); | |
2017 | wmb(); | |
2018 | } | |
2019 | ||
2020 | return VXGE_HW_OK; | |
2021 | } | |
2022 | ||
2023 | /* | |
2024 | * vxge_hw_mgmt_device_config - Retrieve device configuration. | |
2025 | * Get device configuration. Permits to retrieve at run-time configuration | |
2026 | * values that were used to initialize and configure the device. | |
2027 | */ | |
2028 | enum vxge_hw_status | |
2029 | vxge_hw_mgmt_device_config(struct __vxge_hw_device *hldev, | |
2030 | struct vxge_hw_device_config *dev_config, int size) | |
2031 | { | |
2032 | ||
2033 | if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) | |
2034 | return VXGE_HW_ERR_INVALID_DEVICE; | |
2035 | ||
2036 | if (size != sizeof(struct vxge_hw_device_config)) | |
2037 | return VXGE_HW_ERR_VERSION_CONFLICT; | |
2038 | ||
2039 | memcpy(dev_config, &hldev->config, | |
2040 | sizeof(struct vxge_hw_device_config)); | |
2041 | ||
2042 | return VXGE_HW_OK; | |
2043 | } | |
2044 | ||
2045 | /* | |
2046 | * vxge_hw_mgmt_reg_read - Read Titan register. | |
2047 | */ | |
2048 | enum vxge_hw_status | |
2049 | vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev, | |
2050 | enum vxge_hw_mgmt_reg_type type, | |
2051 | u32 index, u32 offset, u64 *value) | |
2052 | { | |
2053 | enum vxge_hw_status status = VXGE_HW_OK; | |
2054 | ||
2055 | if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) { | |
2056 | status = VXGE_HW_ERR_INVALID_DEVICE; | |
2057 | goto exit; | |
2058 | } | |
2059 | ||
2060 | switch (type) { | |
2061 | case vxge_hw_mgmt_reg_type_legacy: | |
2062 | if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) { | |
2063 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2064 | break; | |
2065 | } | |
2066 | *value = readq((void __iomem *)hldev->legacy_reg + offset); | |
2067 | break; | |
2068 | case vxge_hw_mgmt_reg_type_toc: | |
2069 | if (offset > sizeof(struct vxge_hw_toc_reg) - 8) { | |
2070 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2071 | break; | |
2072 | } | |
2073 | *value = readq((void __iomem *)hldev->toc_reg + offset); | |
2074 | break; | |
2075 | case vxge_hw_mgmt_reg_type_common: | |
2076 | if (offset > sizeof(struct vxge_hw_common_reg) - 8) { | |
2077 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2078 | break; | |
2079 | } | |
2080 | *value = readq((void __iomem *)hldev->common_reg + offset); | |
2081 | break; | |
2082 | case vxge_hw_mgmt_reg_type_mrpcim: | |
2083 | if (!(hldev->access_rights & | |
2084 | VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) { | |
2085 | status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; | |
2086 | break; | |
2087 | } | |
2088 | if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) { | |
2089 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2090 | break; | |
2091 | } | |
2092 | *value = readq((void __iomem *)hldev->mrpcim_reg + offset); | |
2093 | break; | |
2094 | case vxge_hw_mgmt_reg_type_srpcim: | |
2095 | if (!(hldev->access_rights & | |
2096 | VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) { | |
2097 | status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; | |
2098 | break; | |
2099 | } | |
2100 | if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) { | |
2101 | status = VXGE_HW_ERR_INVALID_INDEX; | |
2102 | break; | |
2103 | } | |
2104 | if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) { | |
2105 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2106 | break; | |
2107 | } | |
2108 | *value = readq((void __iomem *)hldev->srpcim_reg[index] + | |
2109 | offset); | |
2110 | break; | |
2111 | case vxge_hw_mgmt_reg_type_vpmgmt: | |
2112 | if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) || | |
2113 | (!(hldev->vpath_assignments & vxge_mBIT(index)))) { | |
2114 | status = VXGE_HW_ERR_INVALID_INDEX; | |
2115 | break; | |
2116 | } | |
2117 | if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) { | |
2118 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2119 | break; | |
2120 | } | |
2121 | *value = readq((void __iomem *)hldev->vpmgmt_reg[index] + | |
2122 | offset); | |
2123 | break; | |
2124 | case vxge_hw_mgmt_reg_type_vpath: | |
2125 | if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) || | |
2126 | (!(hldev->vpath_assignments & vxge_mBIT(index)))) { | |
2127 | status = VXGE_HW_ERR_INVALID_INDEX; | |
2128 | break; | |
2129 | } | |
2130 | if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) { | |
2131 | status = VXGE_HW_ERR_INVALID_INDEX; | |
2132 | break; | |
2133 | } | |
2134 | if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) { | |
2135 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2136 | break; | |
2137 | } | |
2138 | *value = readq((void __iomem *)hldev->vpath_reg[index] + | |
2139 | offset); | |
2140 | break; | |
2141 | default: | |
2142 | status = VXGE_HW_ERR_INVALID_TYPE; | |
2143 | break; | |
2144 | } | |
2145 | ||
2146 | exit: | |
2147 | return status; | |
2148 | } | |
2149 | ||
fa41fd10 SH |
2150 | /* |
2151 | * vxge_hw_vpath_strip_fcs_check - Check for FCS strip. | |
2152 | */ | |
2153 | enum vxge_hw_status | |
2154 | vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask) | |
2155 | { | |
2156 | struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; | |
2157 | enum vxge_hw_status status = VXGE_HW_OK; | |
2158 | int i = 0, j = 0; | |
2159 | ||
2160 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
2161 | if (!((vpath_mask) & vxge_mBIT(i))) | |
2162 | continue; | |
2163 | vpmgmt_reg = hldev->vpmgmt_reg[i]; | |
2164 | for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) { | |
2165 | if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j]) | |
2166 | & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS) | |
2167 | return VXGE_HW_FAIL; | |
2168 | } | |
2169 | } | |
2170 | return status; | |
2171 | } | |
40a3a915 RV |
2172 | /* |
2173 | * vxge_hw_mgmt_reg_Write - Write Titan register. | |
2174 | */ | |
2175 | enum vxge_hw_status | |
2176 | vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev, | |
2177 | enum vxge_hw_mgmt_reg_type type, | |
2178 | u32 index, u32 offset, u64 value) | |
2179 | { | |
2180 | enum vxge_hw_status status = VXGE_HW_OK; | |
2181 | ||
2182 | if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) { | |
2183 | status = VXGE_HW_ERR_INVALID_DEVICE; | |
2184 | goto exit; | |
2185 | } | |
2186 | ||
2187 | switch (type) { | |
2188 | case vxge_hw_mgmt_reg_type_legacy: | |
2189 | if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) { | |
2190 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2191 | break; | |
2192 | } | |
2193 | writeq(value, (void __iomem *)hldev->legacy_reg + offset); | |
2194 | break; | |
2195 | case vxge_hw_mgmt_reg_type_toc: | |
2196 | if (offset > sizeof(struct vxge_hw_toc_reg) - 8) { | |
2197 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2198 | break; | |
2199 | } | |
2200 | writeq(value, (void __iomem *)hldev->toc_reg + offset); | |
2201 | break; | |
2202 | case vxge_hw_mgmt_reg_type_common: | |
2203 | if (offset > sizeof(struct vxge_hw_common_reg) - 8) { | |
2204 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2205 | break; | |
2206 | } | |
2207 | writeq(value, (void __iomem *)hldev->common_reg + offset); | |
2208 | break; | |
2209 | case vxge_hw_mgmt_reg_type_mrpcim: | |
2210 | if (!(hldev->access_rights & | |
2211 | VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) { | |
2212 | status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; | |
2213 | break; | |
2214 | } | |
2215 | if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) { | |
2216 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2217 | break; | |
2218 | } | |
2219 | writeq(value, (void __iomem *)hldev->mrpcim_reg + offset); | |
2220 | break; | |
2221 | case vxge_hw_mgmt_reg_type_srpcim: | |
2222 | if (!(hldev->access_rights & | |
2223 | VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) { | |
2224 | status = VXGE_HW_ERR_PRIVILAGED_OPEARATION; | |
2225 | break; | |
2226 | } | |
2227 | if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) { | |
2228 | status = VXGE_HW_ERR_INVALID_INDEX; | |
2229 | break; | |
2230 | } | |
2231 | if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) { | |
2232 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2233 | break; | |
2234 | } | |
2235 | writeq(value, (void __iomem *)hldev->srpcim_reg[index] + | |
2236 | offset); | |
2237 | ||
2238 | break; | |
2239 | case vxge_hw_mgmt_reg_type_vpmgmt: | |
2240 | if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) || | |
2241 | (!(hldev->vpath_assignments & vxge_mBIT(index)))) { | |
2242 | status = VXGE_HW_ERR_INVALID_INDEX; | |
2243 | break; | |
2244 | } | |
2245 | if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) { | |
2246 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2247 | break; | |
2248 | } | |
2249 | writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] + | |
2250 | offset); | |
2251 | break; | |
2252 | case vxge_hw_mgmt_reg_type_vpath: | |
2253 | if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) || | |
2254 | (!(hldev->vpath_assignments & vxge_mBIT(index)))) { | |
2255 | status = VXGE_HW_ERR_INVALID_INDEX; | |
2256 | break; | |
2257 | } | |
2258 | if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) { | |
2259 | status = VXGE_HW_ERR_INVALID_OFFSET; | |
2260 | break; | |
2261 | } | |
2262 | writeq(value, (void __iomem *)hldev->vpath_reg[index] + | |
2263 | offset); | |
2264 | break; | |
2265 | default: | |
2266 | status = VXGE_HW_ERR_INVALID_TYPE; | |
2267 | break; | |
2268 | } | |
2269 | exit: | |
2270 | return status; | |
2271 | } | |
2272 | ||
2273 | /* | |
2274 | * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD | |
2275 | * list callback | |
2276 | * This function is callback passed to __vxge_hw_mempool_create to create memory | |
2277 | * pool for TxD list | |
2278 | */ | |
2279 | static void | |
2280 | __vxge_hw_fifo_mempool_item_alloc( | |
2281 | struct vxge_hw_mempool *mempoolh, | |
2282 | u32 memblock_index, struct vxge_hw_mempool_dma *dma_object, | |
2283 | u32 index, u32 is_last) | |
2284 | { | |
2285 | u32 memblock_item_idx; | |
2286 | struct __vxge_hw_fifo_txdl_priv *txdl_priv; | |
2287 | struct vxge_hw_fifo_txd *txdp = | |
2288 | (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index]; | |
2289 | struct __vxge_hw_fifo *fifo = | |
2290 | (struct __vxge_hw_fifo *)mempoolh->userdata; | |
2291 | void *memblock = mempoolh->memblocks_arr[memblock_index]; | |
2292 | ||
2293 | vxge_assert(txdp); | |
2294 | ||
2295 | txdp->host_control = (u64) (size_t) | |
2296 | __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp, | |
2297 | &memblock_item_idx); | |
2298 | ||
2299 | txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp); | |
2300 | ||
2301 | vxge_assert(txdl_priv); | |
2302 | ||
2303 | fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp; | |
2304 | ||
2305 | /* pre-format HW's TxDL's private */ | |
2306 | txdl_priv->dma_offset = (char *)txdp - (char *)memblock; | |
2307 | txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset; | |
2308 | txdl_priv->dma_handle = dma_object->handle; | |
2309 | txdl_priv->memblock = memblock; | |
2310 | txdl_priv->first_txdp = txdp; | |
2311 | txdl_priv->next_txdl_priv = NULL; | |
2312 | txdl_priv->alloc_frags = 0; | |
40a3a915 RV |
2313 | } |
2314 | ||
2315 | /* | |
2316 | * __vxge_hw_fifo_create - Create a FIFO | |
2317 | * This function creates FIFO and initializes it. | |
2318 | */ | |
2319 | enum vxge_hw_status | |
2320 | __vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp, | |
2321 | struct vxge_hw_fifo_attr *attr) | |
2322 | { | |
2323 | enum vxge_hw_status status = VXGE_HW_OK; | |
2324 | struct __vxge_hw_fifo *fifo; | |
2325 | struct vxge_hw_fifo_config *config; | |
2326 | u32 txdl_size, txdl_per_memblock; | |
2327 | struct vxge_hw_mempool_cbs fifo_mp_callback; | |
2328 | struct __vxge_hw_virtualpath *vpath; | |
2329 | ||
2330 | if ((vp == NULL) || (attr == NULL)) { | |
2331 | status = VXGE_HW_ERR_INVALID_HANDLE; | |
2332 | goto exit; | |
2333 | } | |
2334 | vpath = vp->vpath; | |
2335 | config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo; | |
2336 | ||
2337 | txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd); | |
2338 | ||
2339 | txdl_per_memblock = config->memblock_size / txdl_size; | |
2340 | ||
2341 | fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp, | |
2342 | VXGE_HW_CHANNEL_TYPE_FIFO, | |
2343 | config->fifo_blocks * txdl_per_memblock, | |
2344 | attr->per_txdl_space, attr->userdata); | |
2345 | ||
2346 | if (fifo == NULL) { | |
2347 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
2348 | goto exit; | |
2349 | } | |
2350 | ||
2351 | vpath->fifoh = fifo; | |
2352 | fifo->nofl_db = vpath->nofl_db; | |
2353 | ||
2354 | fifo->vp_id = vpath->vp_id; | |
2355 | fifo->vp_reg = vpath->vp_reg; | |
2356 | fifo->stats = &vpath->sw_stats->fifo_stats; | |
2357 | ||
2358 | fifo->config = config; | |
2359 | ||
2360 | /* apply "interrupts per txdl" attribute */ | |
2361 | fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ; | |
2362 | ||
2363 | if (fifo->config->intr) | |
2364 | fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST; | |
2365 | ||
2366 | fifo->no_snoop_bits = config->no_snoop_bits; | |
2367 | ||
2368 | /* | |
2369 | * FIFO memory management strategy: | |
2370 | * | |
2371 | * TxDL split into three independent parts: | |
2372 | * - set of TxD's | |
2373 | * - TxD HW private part | |
2374 | * - driver private part | |
2375 | * | |
2376 | * Adaptative memory allocation used. i.e. Memory allocated on | |
2377 | * demand with the size which will fit into one memory block. | |
2378 | * One memory block may contain more than one TxDL. | |
2379 | * | |
2380 | * During "reserve" operations more memory can be allocated on demand | |
2381 | * for example due to FIFO full condition. | |
2382 | * | |
2383 | * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close | |
2384 | * routine which will essentially stop the channel and free resources. | |
2385 | */ | |
2386 | ||
2387 | /* TxDL common private size == TxDL private + driver private */ | |
2388 | fifo->priv_size = | |
2389 | sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space; | |
2390 | fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) / | |
2391 | VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE; | |
2392 | ||
2393 | fifo->per_txdl_space = attr->per_txdl_space; | |
2394 | ||
2395 | /* recompute txdl size to be cacheline aligned */ | |
2396 | fifo->txdl_size = txdl_size; | |
2397 | fifo->txdl_per_memblock = txdl_per_memblock; | |
2398 | ||
2399 | fifo->txdl_term = attr->txdl_term; | |
2400 | fifo->callback = attr->callback; | |
2401 | ||
2402 | if (fifo->txdl_per_memblock == 0) { | |
2403 | __vxge_hw_fifo_delete(vp); | |
2404 | status = VXGE_HW_ERR_INVALID_BLOCK_SIZE; | |
2405 | goto exit; | |
2406 | } | |
2407 | ||
2408 | fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc; | |
2409 | ||
2410 | fifo->mempool = | |
2411 | __vxge_hw_mempool_create(vpath->hldev, | |
2412 | fifo->config->memblock_size, | |
2413 | fifo->txdl_size, | |
2414 | fifo->priv_size, | |
2415 | (fifo->config->fifo_blocks * fifo->txdl_per_memblock), | |
2416 | (fifo->config->fifo_blocks * fifo->txdl_per_memblock), | |
2417 | &fifo_mp_callback, | |
2418 | fifo); | |
2419 | ||
2420 | if (fifo->mempool == NULL) { | |
2421 | __vxge_hw_fifo_delete(vp); | |
2422 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
2423 | goto exit; | |
2424 | } | |
2425 | ||
2426 | status = __vxge_hw_channel_initialize(&fifo->channel); | |
2427 | if (status != VXGE_HW_OK) { | |
2428 | __vxge_hw_fifo_delete(vp); | |
2429 | goto exit; | |
2430 | } | |
2431 | ||
2432 | vxge_assert(fifo->channel.reserve_ptr); | |
2433 | exit: | |
2434 | return status; | |
2435 | } | |
2436 | ||
2437 | /* | |
2438 | * __vxge_hw_fifo_abort - Returns the TxD | |
2439 | * This function terminates the TxDs of fifo | |
2440 | */ | |
2441 | enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo) | |
2442 | { | |
2443 | void *txdlh; | |
2444 | ||
2445 | for (;;) { | |
2446 | vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh); | |
2447 | ||
2448 | if (txdlh == NULL) | |
2449 | break; | |
2450 | ||
2451 | vxge_hw_channel_dtr_complete(&fifo->channel); | |
2452 | ||
2453 | if (fifo->txdl_term) { | |
2454 | fifo->txdl_term(txdlh, | |
2455 | VXGE_HW_TXDL_STATE_POSTED, | |
2456 | fifo->channel.userdata); | |
2457 | } | |
2458 | ||
2459 | vxge_hw_channel_dtr_free(&fifo->channel, txdlh); | |
2460 | } | |
2461 | ||
2462 | return VXGE_HW_OK; | |
2463 | } | |
2464 | ||
2465 | /* | |
2466 | * __vxge_hw_fifo_reset - Resets the fifo | |
2467 | * This function resets the fifo during vpath reset operation | |
2468 | */ | |
2469 | enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo) | |
2470 | { | |
2471 | enum vxge_hw_status status = VXGE_HW_OK; | |
2472 | ||
2473 | __vxge_hw_fifo_abort(fifo); | |
2474 | status = __vxge_hw_channel_reset(&fifo->channel); | |
2475 | ||
2476 | return status; | |
2477 | } | |
2478 | ||
2479 | /* | |
2480 | * __vxge_hw_fifo_delete - Removes the FIFO | |
2481 | * This function freeup the memory pool and removes the FIFO | |
2482 | */ | |
2483 | enum vxge_hw_status __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp) | |
2484 | { | |
2485 | struct __vxge_hw_fifo *fifo = vp->vpath->fifoh; | |
2486 | ||
2487 | __vxge_hw_fifo_abort(fifo); | |
2488 | ||
2489 | if (fifo->mempool) | |
2490 | __vxge_hw_mempool_destroy(fifo->mempool); | |
2491 | ||
2492 | vp->vpath->fifoh = NULL; | |
2493 | ||
2494 | __vxge_hw_channel_free(&fifo->channel); | |
2495 | ||
2496 | return VXGE_HW_OK; | |
2497 | } | |
2498 | ||
2499 | /* | |
2500 | * __vxge_hw_vpath_pci_read - Read the content of given address | |
2501 | * in pci config space. | |
2502 | * Read from the vpath pci config space. | |
2503 | */ | |
2504 | enum vxge_hw_status | |
2505 | __vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath, | |
2506 | u32 phy_func_0, u32 offset, u32 *val) | |
2507 | { | |
2508 | u64 val64; | |
2509 | enum vxge_hw_status status = VXGE_HW_OK; | |
2510 | struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg; | |
2511 | ||
2512 | val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset); | |
2513 | ||
2514 | if (phy_func_0) | |
2515 | val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0; | |
2516 | ||
2517 | writeq(val64, &vp_reg->pci_config_access_cfg1); | |
2518 | wmb(); | |
2519 | writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ, | |
2520 | &vp_reg->pci_config_access_cfg2); | |
2521 | wmb(); | |
2522 | ||
2523 | status = __vxge_hw_device_register_poll( | |
2524 | &vp_reg->pci_config_access_cfg2, | |
2525 | VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
2526 | ||
2527 | if (status != VXGE_HW_OK) | |
2528 | goto exit; | |
2529 | ||
2530 | val64 = readq(&vp_reg->pci_config_access_status); | |
2531 | ||
2532 | if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) { | |
2533 | status = VXGE_HW_FAIL; | |
2534 | *val = 0; | |
2535 | } else | |
2536 | *val = (u32)vxge_bVALn(val64, 32, 32); | |
2537 | exit: | |
2538 | return status; | |
2539 | } | |
2540 | ||
2541 | /* | |
2542 | * __vxge_hw_vpath_func_id_get - Get the function id of the vpath. | |
2543 | * Returns the function number of the vpath. | |
2544 | */ | |
2545 | u32 | |
2546 | __vxge_hw_vpath_func_id_get(u32 vp_id, | |
2547 | struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg) | |
2548 | { | |
2549 | u64 val64; | |
2550 | ||
2551 | val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1); | |
2552 | ||
2553 | return | |
2554 | (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64); | |
2555 | } | |
2556 | ||
2557 | /* | |
2558 | * __vxge_hw_read_rts_ds - Program RTS steering critieria | |
2559 | */ | |
2560 | static inline void | |
2561 | __vxge_hw_read_rts_ds(struct vxge_hw_vpath_reg __iomem *vpath_reg, | |
2562 | u64 dta_struct_sel) | |
2563 | { | |
2564 | writeq(0, &vpath_reg->rts_access_steer_ctrl); | |
2565 | wmb(); | |
2566 | writeq(dta_struct_sel, &vpath_reg->rts_access_steer_data0); | |
2567 | writeq(0, &vpath_reg->rts_access_steer_data1); | |
2568 | wmb(); | |
40a3a915 RV |
2569 | } |
2570 | ||
2571 | ||
2572 | /* | |
2573 | * __vxge_hw_vpath_card_info_get - Get the serial numbers, | |
2574 | * part number and product description. | |
2575 | */ | |
2576 | enum vxge_hw_status | |
2577 | __vxge_hw_vpath_card_info_get( | |
2578 | u32 vp_id, | |
2579 | struct vxge_hw_vpath_reg __iomem *vpath_reg, | |
2580 | struct vxge_hw_device_hw_info *hw_info) | |
2581 | { | |
2582 | u32 i, j; | |
2583 | u64 val64; | |
2584 | u64 data1 = 0ULL; | |
2585 | u64 data2 = 0ULL; | |
2586 | enum vxge_hw_status status = VXGE_HW_OK; | |
2587 | u8 *serial_number = hw_info->serial_number; | |
2588 | u8 *part_number = hw_info->part_number; | |
2589 | u8 *product_desc = hw_info->product_desc; | |
2590 | ||
2591 | __vxge_hw_read_rts_ds(vpath_reg, | |
2592 | VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER); | |
2593 | ||
2594 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( | |
2595 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | | |
2596 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( | |
2597 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | | |
2598 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
2599 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); | |
2600 | ||
2601 | status = __vxge_hw_pio_mem_write64(val64, | |
2602 | &vpath_reg->rts_access_steer_ctrl, | |
2603 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
2604 | VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
2605 | ||
2606 | if (status != VXGE_HW_OK) | |
2607 | return status; | |
2608 | ||
2609 | val64 = readq(&vpath_reg->rts_access_steer_ctrl); | |
2610 | ||
2611 | if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { | |
2612 | data1 = readq(&vpath_reg->rts_access_steer_data0); | |
2613 | ((u64 *)serial_number)[0] = be64_to_cpu(data1); | |
2614 | ||
2615 | data2 = readq(&vpath_reg->rts_access_steer_data1); | |
2616 | ((u64 *)serial_number)[1] = be64_to_cpu(data2); | |
2617 | status = VXGE_HW_OK; | |
2618 | } else | |
2619 | *serial_number = 0; | |
2620 | ||
2621 | __vxge_hw_read_rts_ds(vpath_reg, | |
2622 | VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER); | |
2623 | ||
2624 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( | |
2625 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | | |
2626 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( | |
2627 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | | |
2628 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
2629 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); | |
2630 | ||
2631 | status = __vxge_hw_pio_mem_write64(val64, | |
2632 | &vpath_reg->rts_access_steer_ctrl, | |
2633 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
2634 | VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
2635 | ||
2636 | if (status != VXGE_HW_OK) | |
2637 | return status; | |
2638 | ||
2639 | val64 = readq(&vpath_reg->rts_access_steer_ctrl); | |
2640 | ||
2641 | if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { | |
2642 | ||
2643 | data1 = readq(&vpath_reg->rts_access_steer_data0); | |
2644 | ((u64 *)part_number)[0] = be64_to_cpu(data1); | |
2645 | ||
2646 | data2 = readq(&vpath_reg->rts_access_steer_data1); | |
2647 | ((u64 *)part_number)[1] = be64_to_cpu(data2); | |
2648 | ||
2649 | status = VXGE_HW_OK; | |
2650 | ||
2651 | } else | |
2652 | *part_number = 0; | |
2653 | ||
2654 | j = 0; | |
2655 | ||
2656 | for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0; | |
2657 | i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) { | |
2658 | ||
2659 | __vxge_hw_read_rts_ds(vpath_reg, i); | |
2660 | ||
2661 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( | |
2662 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | | |
2663 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( | |
2664 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | | |
2665 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
2666 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); | |
2667 | ||
2668 | status = __vxge_hw_pio_mem_write64(val64, | |
2669 | &vpath_reg->rts_access_steer_ctrl, | |
2670 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
2671 | VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
2672 | ||
2673 | if (status != VXGE_HW_OK) | |
2674 | return status; | |
2675 | ||
2676 | val64 = readq(&vpath_reg->rts_access_steer_ctrl); | |
2677 | ||
2678 | if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { | |
2679 | ||
2680 | data1 = readq(&vpath_reg->rts_access_steer_data0); | |
2681 | ((u64 *)product_desc)[j++] = be64_to_cpu(data1); | |
2682 | ||
2683 | data2 = readq(&vpath_reg->rts_access_steer_data1); | |
2684 | ((u64 *)product_desc)[j++] = be64_to_cpu(data2); | |
2685 | ||
2686 | status = VXGE_HW_OK; | |
2687 | } else | |
2688 | *product_desc = 0; | |
2689 | } | |
2690 | ||
2691 | return status; | |
2692 | } | |
2693 | ||
2694 | /* | |
2695 | * __vxge_hw_vpath_fw_ver_get - Get the fw version | |
2696 | * Returns FW Version | |
2697 | */ | |
2698 | enum vxge_hw_status | |
2699 | __vxge_hw_vpath_fw_ver_get( | |
2700 | u32 vp_id, | |
2701 | struct vxge_hw_vpath_reg __iomem *vpath_reg, | |
2702 | struct vxge_hw_device_hw_info *hw_info) | |
2703 | { | |
2704 | u64 val64; | |
2705 | u64 data1 = 0ULL; | |
2706 | u64 data2 = 0ULL; | |
2707 | struct vxge_hw_device_version *fw_version = &hw_info->fw_version; | |
2708 | struct vxge_hw_device_date *fw_date = &hw_info->fw_date; | |
2709 | struct vxge_hw_device_version *flash_version = &hw_info->flash_version; | |
2710 | struct vxge_hw_device_date *flash_date = &hw_info->flash_date; | |
2711 | enum vxge_hw_status status = VXGE_HW_OK; | |
2712 | ||
2713 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( | |
2714 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY) | | |
2715 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( | |
2716 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | | |
2717 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
2718 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); | |
2719 | ||
2720 | status = __vxge_hw_pio_mem_write64(val64, | |
2721 | &vpath_reg->rts_access_steer_ctrl, | |
2722 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
2723 | VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
2724 | ||
2725 | if (status != VXGE_HW_OK) | |
2726 | goto exit; | |
2727 | ||
2728 | val64 = readq(&vpath_reg->rts_access_steer_ctrl); | |
2729 | ||
2730 | if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { | |
2731 | ||
2732 | data1 = readq(&vpath_reg->rts_access_steer_data0); | |
2733 | data2 = readq(&vpath_reg->rts_access_steer_data1); | |
2734 | ||
2735 | fw_date->day = | |
2736 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY( | |
2737 | data1); | |
2738 | fw_date->month = | |
2739 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH( | |
2740 | data1); | |
2741 | fw_date->year = | |
2742 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR( | |
2743 | data1); | |
2744 | ||
2745 | snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d", | |
2746 | fw_date->month, fw_date->day, fw_date->year); | |
2747 | ||
2748 | fw_version->major = | |
2749 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1); | |
2750 | fw_version->minor = | |
2751 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1); | |
2752 | fw_version->build = | |
2753 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1); | |
2754 | ||
2755 | snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d", | |
2756 | fw_version->major, fw_version->minor, fw_version->build); | |
2757 | ||
2758 | flash_date->day = | |
2759 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data2); | |
2760 | flash_date->month = | |
2761 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data2); | |
2762 | flash_date->year = | |
2763 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data2); | |
2764 | ||
2765 | snprintf(flash_date->date, VXGE_HW_FW_STRLEN, | |
2766 | "%2.2d/%2.2d/%4.4d", | |
2767 | flash_date->month, flash_date->day, flash_date->year); | |
2768 | ||
2769 | flash_version->major = | |
2770 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data2); | |
2771 | flash_version->minor = | |
2772 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data2); | |
2773 | flash_version->build = | |
2774 | (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data2); | |
2775 | ||
2776 | snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d", | |
2777 | flash_version->major, flash_version->minor, | |
2778 | flash_version->build); | |
2779 | ||
2780 | status = VXGE_HW_OK; | |
2781 | ||
2782 | } else | |
2783 | status = VXGE_HW_FAIL; | |
2784 | exit: | |
2785 | return status; | |
2786 | } | |
2787 | ||
2788 | /* | |
2789 | * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode | |
2790 | * Returns pci function mode | |
2791 | */ | |
2792 | u64 | |
2793 | __vxge_hw_vpath_pci_func_mode_get( | |
2794 | u32 vp_id, | |
2795 | struct vxge_hw_vpath_reg __iomem *vpath_reg) | |
2796 | { | |
2797 | u64 val64; | |
2798 | u64 data1 = 0ULL; | |
2799 | enum vxge_hw_status status = VXGE_HW_OK; | |
2800 | ||
2801 | __vxge_hw_read_rts_ds(vpath_reg, | |
2802 | VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE); | |
2803 | ||
2804 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( | |
2805 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) | | |
2806 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( | |
2807 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | | |
2808 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
2809 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); | |
2810 | ||
2811 | status = __vxge_hw_pio_mem_write64(val64, | |
2812 | &vpath_reg->rts_access_steer_ctrl, | |
2813 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
2814 | VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
2815 | ||
2816 | if (status != VXGE_HW_OK) | |
2817 | goto exit; | |
2818 | ||
2819 | val64 = readq(&vpath_reg->rts_access_steer_ctrl); | |
2820 | ||
2821 | if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { | |
2822 | data1 = readq(&vpath_reg->rts_access_steer_data0); | |
2823 | status = VXGE_HW_OK; | |
2824 | } else { | |
2825 | data1 = 0; | |
2826 | status = VXGE_HW_FAIL; | |
2827 | } | |
2828 | exit: | |
2829 | return data1; | |
2830 | } | |
2831 | ||
2832 | /** | |
2833 | * vxge_hw_device_flick_link_led - Flick (blink) link LED. | |
2834 | * @hldev: HW device. | |
2835 | * @on_off: TRUE if flickering to be on, FALSE to be off | |
2836 | * | |
2837 | * Flicker the link LED. | |
2838 | */ | |
2839 | enum vxge_hw_status | |
2840 | vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, | |
2841 | u64 on_off) | |
2842 | { | |
2843 | u64 val64; | |
2844 | enum vxge_hw_status status = VXGE_HW_OK; | |
2845 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
2846 | ||
2847 | if (hldev == NULL) { | |
2848 | status = VXGE_HW_ERR_INVALID_DEVICE; | |
2849 | goto exit; | |
2850 | } | |
2851 | ||
2852 | vp_reg = hldev->vpath_reg[hldev->first_vp_id]; | |
2853 | ||
2854 | writeq(0, &vp_reg->rts_access_steer_ctrl); | |
2855 | wmb(); | |
2856 | writeq(on_off, &vp_reg->rts_access_steer_data0); | |
2857 | writeq(0, &vp_reg->rts_access_steer_data1); | |
2858 | wmb(); | |
2859 | ||
2860 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( | |
2861 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL) | | |
2862 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( | |
2863 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) | | |
2864 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
2865 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); | |
2866 | ||
2867 | status = __vxge_hw_pio_mem_write64(val64, | |
2868 | &vp_reg->rts_access_steer_ctrl, | |
2869 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
2870 | VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
2871 | exit: | |
2872 | return status; | |
2873 | } | |
2874 | ||
2875 | /* | |
2876 | * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables | |
2877 | */ | |
2878 | enum vxge_hw_status | |
2879 | __vxge_hw_vpath_rts_table_get( | |
2880 | struct __vxge_hw_vpath_handle *vp, | |
2881 | u32 action, u32 rts_table, u32 offset, u64 *data1, u64 *data2) | |
2882 | { | |
2883 | u64 val64; | |
2884 | struct __vxge_hw_virtualpath *vpath; | |
2885 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
2886 | ||
2887 | enum vxge_hw_status status = VXGE_HW_OK; | |
2888 | ||
2889 | if (vp == NULL) { | |
2890 | status = VXGE_HW_ERR_INVALID_HANDLE; | |
2891 | goto exit; | |
2892 | } | |
2893 | ||
2894 | vpath = vp->vpath; | |
2895 | vp_reg = vpath->vp_reg; | |
2896 | ||
2897 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | | |
2898 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) | | |
2899 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
2900 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset); | |
2901 | ||
2902 | if ((rts_table == | |
2903 | VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) || | |
2904 | (rts_table == | |
2905 | VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) || | |
2906 | (rts_table == | |
2907 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) || | |
2908 | (rts_table == | |
2909 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) { | |
2910 | val64 = val64 | VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL; | |
2911 | } | |
2912 | ||
2913 | status = __vxge_hw_pio_mem_write64(val64, | |
2914 | &vp_reg->rts_access_steer_ctrl, | |
2915 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
2916 | vpath->hldev->config.device_poll_millis); | |
2917 | ||
2918 | if (status != VXGE_HW_OK) | |
2919 | goto exit; | |
2920 | ||
2921 | val64 = readq(&vp_reg->rts_access_steer_ctrl); | |
2922 | ||
2923 | if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { | |
2924 | ||
2925 | *data1 = readq(&vp_reg->rts_access_steer_data0); | |
2926 | ||
2927 | if ((rts_table == | |
2928 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) || | |
2929 | (rts_table == | |
2930 | VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) { | |
2931 | *data2 = readq(&vp_reg->rts_access_steer_data1); | |
2932 | } | |
2933 | status = VXGE_HW_OK; | |
2934 | } else | |
2935 | status = VXGE_HW_FAIL; | |
2936 | exit: | |
2937 | return status; | |
2938 | } | |
2939 | ||
2940 | /* | |
2941 | * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables | |
2942 | */ | |
2943 | enum vxge_hw_status | |
2944 | __vxge_hw_vpath_rts_table_set( | |
2945 | struct __vxge_hw_vpath_handle *vp, u32 action, u32 rts_table, | |
2946 | u32 offset, u64 data1, u64 data2) | |
2947 | { | |
2948 | u64 val64; | |
2949 | struct __vxge_hw_virtualpath *vpath; | |
2950 | enum vxge_hw_status status = VXGE_HW_OK; | |
2951 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
2952 | ||
2953 | if (vp == NULL) { | |
2954 | status = VXGE_HW_ERR_INVALID_HANDLE; | |
2955 | goto exit; | |
2956 | } | |
2957 | ||
2958 | vpath = vp->vpath; | |
2959 | vp_reg = vpath->vp_reg; | |
2960 | ||
2961 | writeq(data1, &vp_reg->rts_access_steer_data0); | |
2962 | wmb(); | |
2963 | ||
2964 | if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) || | |
2965 | (rts_table == | |
2966 | VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) { | |
2967 | writeq(data2, &vp_reg->rts_access_steer_data1); | |
2968 | wmb(); | |
2969 | } | |
2970 | ||
2971 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) | | |
2972 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) | | |
2973 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
2974 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset); | |
2975 | ||
2976 | status = __vxge_hw_pio_mem_write64(val64, | |
2977 | &vp_reg->rts_access_steer_ctrl, | |
2978 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
2979 | vpath->hldev->config.device_poll_millis); | |
2980 | ||
2981 | if (status != VXGE_HW_OK) | |
2982 | goto exit; | |
2983 | ||
2984 | val64 = readq(&vp_reg->rts_access_steer_ctrl); | |
2985 | ||
2986 | if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) | |
2987 | status = VXGE_HW_OK; | |
2988 | else | |
2989 | status = VXGE_HW_FAIL; | |
2990 | exit: | |
2991 | return status; | |
2992 | } | |
2993 | ||
2994 | /* | |
2995 | * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath | |
2996 | * from MAC address table. | |
2997 | */ | |
2998 | enum vxge_hw_status | |
2999 | __vxge_hw_vpath_addr_get( | |
3000 | u32 vp_id, struct vxge_hw_vpath_reg __iomem *vpath_reg, | |
3001 | u8 (macaddr)[ETH_ALEN], u8 (macaddr_mask)[ETH_ALEN]) | |
3002 | { | |
3003 | u32 i; | |
3004 | u64 val64; | |
3005 | u64 data1 = 0ULL; | |
3006 | u64 data2 = 0ULL; | |
3007 | enum vxge_hw_status status = VXGE_HW_OK; | |
3008 | ||
3009 | val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION( | |
3010 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY) | | |
3011 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL( | |
3012 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) | | |
3013 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE | | |
3014 | VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0); | |
3015 | ||
3016 | status = __vxge_hw_pio_mem_write64(val64, | |
3017 | &vpath_reg->rts_access_steer_ctrl, | |
3018 | VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE, | |
3019 | VXGE_HW_DEF_DEVICE_POLL_MILLIS); | |
3020 | ||
3021 | if (status != VXGE_HW_OK) | |
3022 | goto exit; | |
3023 | ||
3024 | val64 = readq(&vpath_reg->rts_access_steer_ctrl); | |
3025 | ||
3026 | if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) { | |
3027 | ||
3028 | data1 = readq(&vpath_reg->rts_access_steer_data0); | |
3029 | data2 = readq(&vpath_reg->rts_access_steer_data1); | |
3030 | ||
3031 | data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1); | |
3032 | data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK( | |
3033 | data2); | |
3034 | ||
3035 | for (i = ETH_ALEN; i > 0; i--) { | |
3036 | macaddr[i-1] = (u8)(data1 & 0xFF); | |
3037 | data1 >>= 8; | |
3038 | ||
3039 | macaddr_mask[i-1] = (u8)(data2 & 0xFF); | |
3040 | data2 >>= 8; | |
3041 | } | |
3042 | status = VXGE_HW_OK; | |
3043 | } else | |
3044 | status = VXGE_HW_FAIL; | |
3045 | exit: | |
3046 | return status; | |
3047 | } | |
3048 | ||
3049 | /* | |
3050 | * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing. | |
3051 | */ | |
3052 | enum vxge_hw_status vxge_hw_vpath_rts_rth_set( | |
3053 | struct __vxge_hw_vpath_handle *vp, | |
3054 | enum vxge_hw_rth_algoritms algorithm, | |
3055 | struct vxge_hw_rth_hash_types *hash_type, | |
3056 | u16 bucket_size) | |
3057 | { | |
3058 | u64 data0, data1; | |
3059 | enum vxge_hw_status status = VXGE_HW_OK; | |
3060 | ||
3061 | if (vp == NULL) { | |
3062 | status = VXGE_HW_ERR_INVALID_HANDLE; | |
3063 | goto exit; | |
3064 | } | |
3065 | ||
3066 | status = __vxge_hw_vpath_rts_table_get(vp, | |
3067 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY, | |
3068 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG, | |
3069 | 0, &data0, &data1); | |
3070 | ||
3071 | data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) | | |
3072 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3)); | |
3073 | ||
3074 | data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN | | |
3075 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) | | |
3076 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm); | |
3077 | ||
3078 | if (hash_type->hash_type_tcpipv4_en) | |
3079 | data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN; | |
3080 | ||
3081 | if (hash_type->hash_type_ipv4_en) | |
3082 | data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN; | |
3083 | ||
3084 | if (hash_type->hash_type_tcpipv6_en) | |
3085 | data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN; | |
3086 | ||
3087 | if (hash_type->hash_type_ipv6_en) | |
3088 | data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN; | |
3089 | ||
3090 | if (hash_type->hash_type_tcpipv6ex_en) | |
3091 | data0 |= | |
3092 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN; | |
3093 | ||
3094 | if (hash_type->hash_type_ipv6ex_en) | |
3095 | data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN; | |
3096 | ||
3097 | if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0)) | |
3098 | data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE; | |
3099 | else | |
3100 | data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE; | |
3101 | ||
3102 | status = __vxge_hw_vpath_rts_table_set(vp, | |
3103 | VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY, | |
3104 | VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG, | |
3105 | 0, data0, 0); | |
3106 | exit: | |
3107 | return status; | |
3108 | } | |
3109 | ||
3110 | static void | |
3111 | vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1, | |
3112 | u16 flag, u8 *itable) | |
3113 | { | |
3114 | switch (flag) { | |
3115 | case 1: | |
3116 | *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)| | |
3117 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN | | |
3118 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA( | |
3119 | itable[j]); | |
3120 | case 2: | |
3121 | *data0 |= | |
3122 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)| | |
3123 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN | | |
3124 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA( | |
3125 | itable[j]); | |
3126 | case 3: | |
3127 | *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)| | |
3128 | VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN | | |
3129 | VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA( | |
3130 | itable[j]); | |
3131 | case 4: | |
3132 | *data1 |= | |
3133 | VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)| | |
3134 | VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN | | |
3135 | VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA( | |
3136 | itable[j]); | |
3137 | default: | |
3138 | return; | |
3139 | } | |
3140 | } | |
3141 | /* | |
3142 | * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT). | |
3143 | */ | |
3144 | enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set( | |
3145 | struct __vxge_hw_vpath_handle **vpath_handles, | |
3146 | u32 vpath_count, | |
3147 | u8 *mtable, | |
3148 | u8 *itable, | |
3149 | u32 itable_size) | |
3150 | { | |
3151 | u32 i, j, action, rts_table; | |
3152 | u64 data0; | |
3153 | u64 data1; | |
3154 | u32 max_entries; | |
3155 | enum vxge_hw_status status = VXGE_HW_OK; | |
3156 | struct __vxge_hw_vpath_handle *vp = vpath_handles[0]; | |
3157 | ||
3158 | if (vp == NULL) { | |
3159 | status = VXGE_HW_ERR_INVALID_HANDLE; | |
3160 | goto exit; | |
3161 | } | |
3162 | ||
3163 | max_entries = (((u32)1) << itable_size); | |
3164 | ||
3165 | if (vp->vpath->hldev->config.rth_it_type | |
3166 | == VXGE_HW_RTH_IT_TYPE_SOLO_IT) { | |
3167 | action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY; | |
3168 | rts_table = | |
3169 | VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT; | |
3170 | ||
3171 | for (j = 0; j < max_entries; j++) { | |
3172 | ||
3173 | data1 = 0; | |
3174 | ||
3175 | data0 = | |
3176 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA( | |
3177 | itable[j]); | |
3178 | ||
3179 | status = __vxge_hw_vpath_rts_table_set(vpath_handles[0], | |
3180 | action, rts_table, j, data0, data1); | |
3181 | ||
3182 | if (status != VXGE_HW_OK) | |
3183 | goto exit; | |
3184 | } | |
3185 | ||
3186 | for (j = 0; j < max_entries; j++) { | |
3187 | ||
3188 | data1 = 0; | |
3189 | ||
3190 | data0 = | |
3191 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN | | |
3192 | VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA( | |
3193 | itable[j]); | |
3194 | ||
3195 | status = __vxge_hw_vpath_rts_table_set( | |
3196 | vpath_handles[mtable[itable[j]]], action, | |
3197 | rts_table, j, data0, data1); | |
3198 | ||
3199 | if (status != VXGE_HW_OK) | |
3200 | goto exit; | |
3201 | } | |
3202 | } else { | |
3203 | action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY; | |
3204 | rts_table = | |
3205 | VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT; | |
3206 | for (i = 0; i < vpath_count; i++) { | |
3207 | ||
3208 | for (j = 0; j < max_entries;) { | |
3209 | ||
3210 | data0 = 0; | |
3211 | data1 = 0; | |
3212 | ||
3213 | while (j < max_entries) { | |
3214 | if (mtable[itable[j]] != i) { | |
3215 | j++; | |
3216 | continue; | |
3217 | } | |
3218 | vxge_hw_rts_rth_data0_data1_get(j, | |
3219 | &data0, &data1, 1, itable); | |
3220 | j++; | |
3221 | break; | |
3222 | } | |
3223 | ||
3224 | while (j < max_entries) { | |
3225 | if (mtable[itable[j]] != i) { | |
3226 | j++; | |
3227 | continue; | |
3228 | } | |
3229 | vxge_hw_rts_rth_data0_data1_get(j, | |
3230 | &data0, &data1, 2, itable); | |
3231 | j++; | |
3232 | break; | |
3233 | } | |
3234 | ||
3235 | while (j < max_entries) { | |
3236 | if (mtable[itable[j]] != i) { | |
3237 | j++; | |
3238 | continue; | |
3239 | } | |
3240 | vxge_hw_rts_rth_data0_data1_get(j, | |
3241 | &data0, &data1, 3, itable); | |
3242 | j++; | |
3243 | break; | |
3244 | } | |
3245 | ||
3246 | while (j < max_entries) { | |
3247 | if (mtable[itable[j]] != i) { | |
3248 | j++; | |
3249 | continue; | |
3250 | } | |
3251 | vxge_hw_rts_rth_data0_data1_get(j, | |
3252 | &data0, &data1, 4, itable); | |
3253 | j++; | |
3254 | break; | |
3255 | } | |
3256 | ||
3257 | if (data0 != 0) { | |
3258 | status = __vxge_hw_vpath_rts_table_set( | |
3259 | vpath_handles[i], | |
3260 | action, rts_table, | |
3261 | 0, data0, data1); | |
3262 | ||
3263 | if (status != VXGE_HW_OK) | |
3264 | goto exit; | |
3265 | } | |
3266 | } | |
3267 | } | |
3268 | } | |
3269 | exit: | |
3270 | return status; | |
3271 | } | |
3272 | ||
3273 | /** | |
3274 | * vxge_hw_vpath_check_leak - Check for memory leak | |
3275 | * @ringh: Handle to the ring object used for receive | |
3276 | * | |
3277 | * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to | |
3278 | * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred. | |
3279 | * Returns: VXGE_HW_FAIL, if leak has occurred. | |
3280 | * | |
3281 | */ | |
3282 | enum vxge_hw_status | |
3283 | vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring) | |
3284 | { | |
3285 | enum vxge_hw_status status = VXGE_HW_OK; | |
3286 | u64 rxd_new_count, rxd_spat; | |
3287 | ||
3288 | if (ring == NULL) | |
3289 | return status; | |
3290 | ||
3291 | rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell); | |
3292 | rxd_spat = readq(&ring->vp_reg->prc_cfg6); | |
3293 | rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat); | |
3294 | ||
3295 | if (rxd_new_count >= rxd_spat) | |
3296 | status = VXGE_HW_FAIL; | |
3297 | ||
3298 | return status; | |
3299 | } | |
3300 | ||
3301 | /* | |
3302 | * __vxge_hw_vpath_mgmt_read | |
3303 | * This routine reads the vpath_mgmt registers | |
3304 | */ | |
3305 | static enum vxge_hw_status | |
3306 | __vxge_hw_vpath_mgmt_read( | |
3307 | struct __vxge_hw_device *hldev, | |
3308 | struct __vxge_hw_virtualpath *vpath) | |
3309 | { | |
3310 | u32 i, mtu = 0, max_pyld = 0; | |
3311 | u64 val64; | |
3312 | enum vxge_hw_status status = VXGE_HW_OK; | |
3313 | ||
3314 | for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) { | |
3315 | ||
3316 | val64 = readq(&vpath->vpmgmt_reg-> | |
3317 | rxmac_cfg0_port_vpmgmt_clone[i]); | |
3318 | max_pyld = | |
3319 | (u32) | |
3320 | VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN | |
3321 | (val64); | |
3322 | if (mtu < max_pyld) | |
3323 | mtu = max_pyld; | |
3324 | } | |
3325 | ||
3326 | vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE; | |
3327 | ||
3328 | val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp); | |
3329 | ||
3330 | for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) { | |
3331 | if (val64 & vxge_mBIT(i)) | |
3332 | vpath->vsport_number = i; | |
3333 | } | |
3334 | ||
3335 | val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone); | |
3336 | ||
3337 | if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK) | |
3338 | VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP); | |
3339 | else | |
3340 | VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN); | |
3341 | ||
3342 | return status; | |
3343 | } | |
3344 | ||
3345 | /* | |
3346 | * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed | |
3347 | * This routine checks the vpath_rst_in_prog register to see if | |
3348 | * adapter completed the reset process for the vpath | |
3349 | */ | |
3350 | enum vxge_hw_status | |
3351 | __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath) | |
3352 | { | |
3353 | enum vxge_hw_status status; | |
3354 | ||
3355 | status = __vxge_hw_device_register_poll( | |
3356 | &vpath->hldev->common_reg->vpath_rst_in_prog, | |
3357 | VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG( | |
3358 | 1 << (16 - vpath->vp_id)), | |
3359 | vpath->hldev->config.device_poll_millis); | |
3360 | ||
3361 | return status; | |
3362 | } | |
3363 | ||
3364 | /* | |
3365 | * __vxge_hw_vpath_reset | |
3366 | * This routine resets the vpath on the device | |
3367 | */ | |
3368 | enum vxge_hw_status | |
3369 | __vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id) | |
3370 | { | |
3371 | u64 val64; | |
3372 | enum vxge_hw_status status = VXGE_HW_OK; | |
3373 | ||
3374 | val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id)); | |
3375 | ||
3376 | __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), | |
3377 | &hldev->common_reg->cmn_rsthdlr_cfg0); | |
3378 | ||
3379 | return status; | |
3380 | } | |
3381 | ||
3382 | /* | |
3383 | * __vxge_hw_vpath_sw_reset | |
3384 | * This routine resets the vpath structures | |
3385 | */ | |
3386 | enum vxge_hw_status | |
3387 | __vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id) | |
3388 | { | |
3389 | enum vxge_hw_status status = VXGE_HW_OK; | |
3390 | struct __vxge_hw_virtualpath *vpath; | |
3391 | ||
3392 | vpath = (struct __vxge_hw_virtualpath *)&hldev->virtual_paths[vp_id]; | |
3393 | ||
3394 | if (vpath->ringh) { | |
3395 | status = __vxge_hw_ring_reset(vpath->ringh); | |
3396 | if (status != VXGE_HW_OK) | |
3397 | goto exit; | |
3398 | } | |
3399 | ||
3400 | if (vpath->fifoh) | |
3401 | status = __vxge_hw_fifo_reset(vpath->fifoh); | |
3402 | exit: | |
3403 | return status; | |
3404 | } | |
3405 | ||
3406 | /* | |
3407 | * __vxge_hw_vpath_prc_configure | |
3408 | * This routine configures the prc registers of virtual path using the config | |
3409 | * passed | |
3410 | */ | |
3411 | void | |
3412 | __vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id) | |
3413 | { | |
3414 | u64 val64; | |
3415 | struct __vxge_hw_virtualpath *vpath; | |
3416 | struct vxge_hw_vp_config *vp_config; | |
3417 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
3418 | ||
3419 | vpath = &hldev->virtual_paths[vp_id]; | |
3420 | vp_reg = vpath->vp_reg; | |
3421 | vp_config = vpath->vp_config; | |
3422 | ||
3423 | if (vp_config->ring.enable == VXGE_HW_RING_DISABLE) | |
3424 | return; | |
3425 | ||
3426 | val64 = readq(&vp_reg->prc_cfg1); | |
3427 | val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE; | |
3428 | writeq(val64, &vp_reg->prc_cfg1); | |
3429 | ||
3430 | val64 = readq(&vpath->vp_reg->prc_cfg6); | |
3431 | val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN; | |
3432 | writeq(val64, &vpath->vp_reg->prc_cfg6); | |
3433 | ||
3434 | val64 = readq(&vp_reg->prc_cfg7); | |
3435 | ||
3436 | if (vpath->vp_config->ring.scatter_mode != | |
3437 | VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) { | |
3438 | ||
3439 | val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3); | |
3440 | ||
3441 | switch (vpath->vp_config->ring.scatter_mode) { | |
3442 | case VXGE_HW_RING_SCATTER_MODE_A: | |
3443 | val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE( | |
3444 | VXGE_HW_PRC_CFG7_SCATTER_MODE_A); | |
3445 | break; | |
3446 | case VXGE_HW_RING_SCATTER_MODE_B: | |
3447 | val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE( | |
3448 | VXGE_HW_PRC_CFG7_SCATTER_MODE_B); | |
3449 | break; | |
3450 | case VXGE_HW_RING_SCATTER_MODE_C: | |
3451 | val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE( | |
3452 | VXGE_HW_PRC_CFG7_SCATTER_MODE_C); | |
3453 | break; | |
3454 | } | |
3455 | } | |
3456 | ||
3457 | writeq(val64, &vp_reg->prc_cfg7); | |
3458 | ||
3459 | writeq(VXGE_HW_PRC_CFG5_RXD0_ADD( | |
3460 | __vxge_hw_ring_first_block_address_get( | |
3461 | vpath->ringh) >> 3), &vp_reg->prc_cfg5); | |
3462 | ||
3463 | val64 = readq(&vp_reg->prc_cfg4); | |
3464 | val64 |= VXGE_HW_PRC_CFG4_IN_SVC; | |
3465 | val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3); | |
3466 | ||
3467 | val64 |= VXGE_HW_PRC_CFG4_RING_MODE( | |
3468 | VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER); | |
3469 | ||
3470 | if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE) | |
3471 | val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE; | |
3472 | else | |
3473 | val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE; | |
3474 | ||
3475 | writeq(val64, &vp_reg->prc_cfg4); | |
40a3a915 RV |
3476 | } |
3477 | ||
3478 | /* | |
3479 | * __vxge_hw_vpath_kdfc_configure | |
3480 | * This routine configures the kdfc registers of virtual path using the | |
3481 | * config passed | |
3482 | */ | |
3483 | enum vxge_hw_status | |
3484 | __vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id) | |
3485 | { | |
3486 | u64 val64; | |
3487 | u64 vpath_stride; | |
3488 | enum vxge_hw_status status = VXGE_HW_OK; | |
3489 | struct __vxge_hw_virtualpath *vpath; | |
3490 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
3491 | ||
3492 | vpath = &hldev->virtual_paths[vp_id]; | |
3493 | vp_reg = vpath->vp_reg; | |
3494 | status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg); | |
3495 | ||
3496 | if (status != VXGE_HW_OK) | |
3497 | goto exit; | |
3498 | ||
3499 | val64 = readq(&vp_reg->kdfc_drbl_triplet_total); | |
3500 | ||
3501 | vpath->max_kdfc_db = | |
3502 | (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE( | |
3503 | val64+1)/2; | |
3504 | ||
3505 | if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) { | |
3506 | ||
3507 | vpath->max_nofl_db = vpath->max_kdfc_db; | |
3508 | ||
3509 | if (vpath->max_nofl_db < | |
3510 | ((vpath->vp_config->fifo.memblock_size / | |
3511 | (vpath->vp_config->fifo.max_frags * | |
3512 | sizeof(struct vxge_hw_fifo_txd))) * | |
3513 | vpath->vp_config->fifo.fifo_blocks)) { | |
3514 | ||
3515 | return VXGE_HW_BADCFG_FIFO_BLOCKS; | |
3516 | } | |
3517 | val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0( | |
3518 | (vpath->max_nofl_db*2)-1); | |
3519 | } | |
3520 | ||
3521 | writeq(val64, &vp_reg->kdfc_fifo_trpl_partition); | |
3522 | ||
3523 | writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE, | |
3524 | &vp_reg->kdfc_fifo_trpl_ctrl); | |
3525 | ||
3526 | val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl); | |
3527 | ||
3528 | val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) | | |
3529 | VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF)); | |
3530 | ||
3531 | val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE( | |
3532 | VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) | | |
3533 | #ifndef __BIG_ENDIAN | |
3534 | VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN | | |
3535 | #endif | |
3536 | VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0); | |
3537 | ||
3538 | writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl); | |
3539 | writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address); | |
3540 | wmb(); | |
3541 | vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride); | |
3542 | ||
3543 | vpath->nofl_db = | |
3544 | (struct __vxge_hw_non_offload_db_wrapper __iomem *) | |
3545 | (hldev->kdfc + (vp_id * | |
3546 | VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE( | |
3547 | vpath_stride))); | |
3548 | exit: | |
3549 | return status; | |
3550 | } | |
3551 | ||
3552 | /* | |
3553 | * __vxge_hw_vpath_mac_configure | |
3554 | * This routine configures the mac of virtual path using the config passed | |
3555 | */ | |
3556 | enum vxge_hw_status | |
3557 | __vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id) | |
3558 | { | |
3559 | u64 val64; | |
3560 | enum vxge_hw_status status = VXGE_HW_OK; | |
3561 | struct __vxge_hw_virtualpath *vpath; | |
3562 | struct vxge_hw_vp_config *vp_config; | |
3563 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
3564 | ||
3565 | vpath = &hldev->virtual_paths[vp_id]; | |
3566 | vp_reg = vpath->vp_reg; | |
3567 | vp_config = vpath->vp_config; | |
3568 | ||
3569 | writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER( | |
3570 | vpath->vsport_number), &vp_reg->xmac_vsport_choice); | |
3571 | ||
3572 | if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) { | |
3573 | ||
3574 | val64 = readq(&vp_reg->xmac_rpa_vcfg); | |
3575 | ||
3576 | if (vp_config->rpa_strip_vlan_tag != | |
3577 | VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) { | |
3578 | if (vp_config->rpa_strip_vlan_tag) | |
3579 | val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG; | |
3580 | else | |
3581 | val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG; | |
3582 | } | |
3583 | ||
3584 | writeq(val64, &vp_reg->xmac_rpa_vcfg); | |
3585 | val64 = readq(&vp_reg->rxmac_vcfg0); | |
3586 | ||
3587 | if (vp_config->mtu != | |
3588 | VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) { | |
3589 | val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff); | |
3590 | if ((vp_config->mtu + | |
3591 | VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu) | |
3592 | val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN( | |
3593 | vp_config->mtu + | |
3594 | VXGE_HW_MAC_HEADER_MAX_SIZE); | |
3595 | else | |
3596 | val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN( | |
3597 | vpath->max_mtu); | |
3598 | } | |
3599 | ||
3600 | writeq(val64, &vp_reg->rxmac_vcfg0); | |
3601 | ||
3602 | val64 = readq(&vp_reg->rxmac_vcfg1); | |
3603 | ||
3604 | val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) | | |
3605 | VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE); | |
3606 | ||
3607 | if (hldev->config.rth_it_type == | |
3608 | VXGE_HW_RTH_IT_TYPE_MULTI_IT) { | |
3609 | val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE( | |
3610 | 0x2) | | |
3611 | VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE; | |
3612 | } | |
3613 | ||
3614 | writeq(val64, &vp_reg->rxmac_vcfg1); | |
3615 | } | |
3616 | return status; | |
3617 | } | |
3618 | ||
3619 | /* | |
3620 | * __vxge_hw_vpath_tim_configure | |
3621 | * This routine configures the tim registers of virtual path using the config | |
3622 | * passed | |
3623 | */ | |
3624 | enum vxge_hw_status | |
3625 | __vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id) | |
3626 | { | |
3627 | u64 val64; | |
3628 | enum vxge_hw_status status = VXGE_HW_OK; | |
3629 | struct __vxge_hw_virtualpath *vpath; | |
3630 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
3631 | struct vxge_hw_vp_config *config; | |
3632 | ||
3633 | vpath = &hldev->virtual_paths[vp_id]; | |
3634 | vp_reg = vpath->vp_reg; | |
3635 | config = vpath->vp_config; | |
3636 | ||
3637 | writeq((u64)0, &vp_reg->tim_dest_addr); | |
3638 | writeq((u64)0, &vp_reg->tim_vpath_map); | |
3639 | writeq((u64)0, &vp_reg->tim_bitmap); | |
3640 | writeq((u64)0, &vp_reg->tim_remap); | |
3641 | ||
3642 | if (config->ring.enable == VXGE_HW_RING_ENABLE) | |
3643 | writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM( | |
3644 | (vp_id * VXGE_HW_MAX_INTR_PER_VP) + | |
3645 | VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn); | |
3646 | ||
3647 | val64 = readq(&vp_reg->tim_pci_cfg); | |
3648 | val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD; | |
3649 | writeq(val64, &vp_reg->tim_pci_cfg); | |
3650 | ||
3651 | if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) { | |
3652 | ||
3653 | val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); | |
3654 | ||
3655 | if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) { | |
3656 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( | |
3657 | 0x3ffffff); | |
3658 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( | |
3659 | config->tti.btimer_val); | |
3660 | } | |
3661 | ||
3662 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN; | |
3663 | ||
3664 | if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) { | |
3665 | if (config->tti.timer_ac_en) | |
3666 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; | |
3667 | else | |
3668 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; | |
3669 | } | |
3670 | ||
3671 | if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) { | |
3672 | if (config->tti.timer_ci_en) | |
3673 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; | |
3674 | else | |
3675 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; | |
3676 | } | |
3677 | ||
3678 | if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) { | |
3679 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f); | |
3680 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A( | |
3681 | config->tti.urange_a); | |
3682 | } | |
3683 | ||
3684 | if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) { | |
3685 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f); | |
3686 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B( | |
3687 | config->tti.urange_b); | |
3688 | } | |
3689 | ||
3690 | if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) { | |
3691 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f); | |
3692 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C( | |
3693 | config->tti.urange_c); | |
3694 | } | |
3695 | ||
3696 | writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); | |
3697 | val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]); | |
3698 | ||
3699 | if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) { | |
3700 | val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff); | |
3701 | val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A( | |
3702 | config->tti.uec_a); | |
3703 | } | |
3704 | ||
3705 | if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) { | |
3706 | val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff); | |
3707 | val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B( | |
3708 | config->tti.uec_b); | |
3709 | } | |
3710 | ||
3711 | if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) { | |
3712 | val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff); | |
3713 | val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C( | |
3714 | config->tti.uec_c); | |
3715 | } | |
3716 | ||
3717 | if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) { | |
3718 | val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff); | |
3719 | val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D( | |
3720 | config->tti.uec_d); | |
3721 | } | |
3722 | ||
3723 | writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]); | |
3724 | val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); | |
3725 | ||
3726 | if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) { | |
3727 | if (config->tti.timer_ri_en) | |
3728 | val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI; | |
3729 | else | |
3730 | val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI; | |
3731 | } | |
3732 | ||
3733 | if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) { | |
3734 | val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( | |
3735 | 0x3ffffff); | |
3736 | val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( | |
3737 | config->tti.rtimer_val); | |
3738 | } | |
3739 | ||
3740 | if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) { | |
3741 | val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f); | |
3742 | val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL( | |
3743 | config->tti.util_sel); | |
3744 | } | |
3745 | ||
3746 | if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) { | |
3747 | val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( | |
3748 | 0x3ffffff); | |
3749 | val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( | |
3750 | config->tti.ltimer_val); | |
3751 | } | |
3752 | ||
3753 | writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]); | |
3754 | } | |
3755 | ||
3756 | if (config->ring.enable == VXGE_HW_RING_ENABLE) { | |
3757 | ||
3758 | val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); | |
3759 | ||
3760 | if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) { | |
3761 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( | |
3762 | 0x3ffffff); | |
3763 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL( | |
3764 | config->rti.btimer_val); | |
3765 | } | |
3766 | ||
3767 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN; | |
3768 | ||
3769 | if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) { | |
3770 | if (config->rti.timer_ac_en) | |
3771 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; | |
3772 | else | |
3773 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC; | |
3774 | } | |
3775 | ||
3776 | if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) { | |
3777 | if (config->rti.timer_ci_en) | |
3778 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; | |
3779 | else | |
3780 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; | |
3781 | } | |
3782 | ||
3783 | if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) { | |
3784 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f); | |
3785 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A( | |
3786 | config->rti.urange_a); | |
3787 | } | |
3788 | ||
3789 | if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) { | |
3790 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f); | |
3791 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B( | |
3792 | config->rti.urange_b); | |
3793 | } | |
3794 | ||
3795 | if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) { | |
3796 | val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f); | |
3797 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C( | |
3798 | config->rti.urange_c); | |
3799 | } | |
3800 | ||
3801 | writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]); | |
3802 | val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]); | |
3803 | ||
3804 | if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) { | |
3805 | val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff); | |
3806 | val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A( | |
3807 | config->rti.uec_a); | |
3808 | } | |
3809 | ||
3810 | if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) { | |
3811 | val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff); | |
3812 | val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B( | |
3813 | config->rti.uec_b); | |
3814 | } | |
3815 | ||
3816 | if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) { | |
3817 | val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff); | |
3818 | val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C( | |
3819 | config->rti.uec_c); | |
3820 | } | |
3821 | ||
3822 | if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) { | |
3823 | val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff); | |
3824 | val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D( | |
3825 | config->rti.uec_d); | |
3826 | } | |
3827 | ||
3828 | writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]); | |
3829 | val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); | |
3830 | ||
3831 | if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) { | |
3832 | if (config->rti.timer_ri_en) | |
3833 | val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI; | |
3834 | else | |
3835 | val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI; | |
3836 | } | |
3837 | ||
3838 | if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) { | |
3839 | val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( | |
3840 | 0x3ffffff); | |
3841 | val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL( | |
3842 | config->rti.rtimer_val); | |
3843 | } | |
3844 | ||
3845 | if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) { | |
3846 | val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f); | |
3847 | val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL( | |
3848 | config->rti.util_sel); | |
3849 | } | |
3850 | ||
3851 | if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) { | |
3852 | val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( | |
3853 | 0x3ffffff); | |
3854 | val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL( | |
3855 | config->rti.ltimer_val); | |
3856 | } | |
3857 | ||
3858 | writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]); | |
3859 | } | |
3860 | ||
3861 | val64 = 0; | |
3862 | writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]); | |
3863 | writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]); | |
3864 | writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]); | |
3865 | writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]); | |
3866 | writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]); | |
3867 | writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]); | |
3868 | ||
3869 | return status; | |
3870 | } | |
3871 | ||
eb5f10c2 SH |
3872 | void |
3873 | vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id) | |
3874 | { | |
3875 | struct __vxge_hw_virtualpath *vpath; | |
3876 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
3877 | struct vxge_hw_vp_config *config; | |
3878 | u64 val64; | |
3879 | ||
3880 | vpath = &hldev->virtual_paths[vp_id]; | |
3881 | vp_reg = vpath->vp_reg; | |
3882 | config = vpath->vp_config; | |
3883 | ||
3884 | if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) { | |
3885 | val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); | |
3886 | ||
3887 | if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) { | |
3888 | config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE; | |
3889 | val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI; | |
3890 | writeq(val64, | |
3891 | &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]); | |
3892 | } | |
3893 | } | |
eb5f10c2 | 3894 | } |
40a3a915 RV |
3895 | /* |
3896 | * __vxge_hw_vpath_initialize | |
3897 | * This routine is the final phase of init which initializes the | |
3898 | * registers of the vpath using the configuration passed. | |
3899 | */ | |
3900 | enum vxge_hw_status | |
3901 | __vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id) | |
3902 | { | |
3903 | u64 val64; | |
3904 | u32 val32; | |
3905 | enum vxge_hw_status status = VXGE_HW_OK; | |
3906 | struct __vxge_hw_virtualpath *vpath; | |
3907 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
3908 | ||
3909 | vpath = &hldev->virtual_paths[vp_id]; | |
3910 | ||
3911 | if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) { | |
3912 | status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; | |
3913 | goto exit; | |
3914 | } | |
3915 | vp_reg = vpath->vp_reg; | |
3916 | ||
3917 | status = __vxge_hw_vpath_swapper_set(vpath->vp_reg); | |
3918 | ||
3919 | if (status != VXGE_HW_OK) | |
3920 | goto exit; | |
3921 | ||
3922 | status = __vxge_hw_vpath_mac_configure(hldev, vp_id); | |
3923 | ||
3924 | if (status != VXGE_HW_OK) | |
3925 | goto exit; | |
3926 | ||
3927 | status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id); | |
3928 | ||
3929 | if (status != VXGE_HW_OK) | |
3930 | goto exit; | |
3931 | ||
3932 | status = __vxge_hw_vpath_tim_configure(hldev, vp_id); | |
3933 | ||
3934 | if (status != VXGE_HW_OK) | |
3935 | goto exit; | |
3936 | ||
40a3a915 RV |
3937 | val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl); |
3938 | ||
3939 | /* Get MRRS value from device control */ | |
3940 | status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32); | |
3941 | ||
3942 | if (status == VXGE_HW_OK) { | |
3943 | val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12; | |
3944 | val64 &= | |
3945 | ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7)); | |
3946 | val64 |= | |
3947 | VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32); | |
3948 | ||
3949 | val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE; | |
3950 | } | |
3951 | ||
3952 | val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7)); | |
3953 | val64 |= | |
3954 | VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY( | |
3955 | VXGE_HW_MAX_PAYLOAD_SIZE_512); | |
3956 | ||
3957 | val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN; | |
3958 | writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl); | |
3959 | ||
3960 | exit: | |
3961 | return status; | |
3962 | } | |
3963 | ||
3964 | /* | |
3965 | * __vxge_hw_vp_initialize - Initialize Virtual Path structure | |
3966 | * This routine is the initial phase of init which resets the vpath and | |
3967 | * initializes the software support structures. | |
3968 | */ | |
3969 | enum vxge_hw_status | |
3970 | __vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id, | |
3971 | struct vxge_hw_vp_config *config) | |
3972 | { | |
3973 | struct __vxge_hw_virtualpath *vpath; | |
3974 | enum vxge_hw_status status = VXGE_HW_OK; | |
3975 | ||
3976 | if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) { | |
3977 | status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE; | |
3978 | goto exit; | |
3979 | } | |
3980 | ||
3981 | vpath = &hldev->virtual_paths[vp_id]; | |
3982 | ||
3983 | vpath->vp_id = vp_id; | |
3984 | vpath->vp_open = VXGE_HW_VP_OPEN; | |
3985 | vpath->hldev = hldev; | |
3986 | vpath->vp_config = config; | |
3987 | vpath->vp_reg = hldev->vpath_reg[vp_id]; | |
3988 | vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id]; | |
3989 | ||
3990 | __vxge_hw_vpath_reset(hldev, vp_id); | |
3991 | ||
3992 | status = __vxge_hw_vpath_reset_check(vpath); | |
3993 | ||
3994 | if (status != VXGE_HW_OK) { | |
3995 | memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); | |
3996 | goto exit; | |
3997 | } | |
3998 | ||
3999 | status = __vxge_hw_vpath_mgmt_read(hldev, vpath); | |
4000 | ||
4001 | if (status != VXGE_HW_OK) { | |
4002 | memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); | |
4003 | goto exit; | |
4004 | } | |
4005 | ||
4006 | INIT_LIST_HEAD(&vpath->vpath_handles); | |
4007 | ||
4008 | vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id]; | |
4009 | ||
4010 | VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0, | |
4011 | hldev->tim_int_mask1, vp_id); | |
4012 | ||
4013 | status = __vxge_hw_vpath_initialize(hldev, vp_id); | |
4014 | ||
4015 | if (status != VXGE_HW_OK) | |
4016 | __vxge_hw_vp_terminate(hldev, vp_id); | |
4017 | exit: | |
4018 | return status; | |
4019 | } | |
4020 | ||
4021 | /* | |
4022 | * __vxge_hw_vp_terminate - Terminate Virtual Path structure | |
4023 | * This routine closes all channels it opened and freeup memory | |
4024 | */ | |
4025 | void | |
4026 | __vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id) | |
4027 | { | |
4028 | struct __vxge_hw_virtualpath *vpath; | |
4029 | ||
4030 | vpath = &hldev->virtual_paths[vp_id]; | |
4031 | ||
4032 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) | |
4033 | goto exit; | |
4034 | ||
4035 | VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0, | |
4036 | vpath->hldev->tim_int_mask1, vpath->vp_id); | |
4037 | hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL; | |
4038 | ||
4039 | memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath)); | |
4040 | exit: | |
4041 | return; | |
4042 | } | |
4043 | ||
4044 | /* | |
4045 | * vxge_hw_vpath_mtu_set - Set MTU. | |
4046 | * Set new MTU value. Example, to use jumbo frames: | |
4047 | * vxge_hw_vpath_mtu_set(my_device, 9600); | |
4048 | */ | |
4049 | enum vxge_hw_status | |
4050 | vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu) | |
4051 | { | |
4052 | u64 val64; | |
4053 | enum vxge_hw_status status = VXGE_HW_OK; | |
4054 | struct __vxge_hw_virtualpath *vpath; | |
4055 | ||
4056 | if (vp == NULL) { | |
4057 | status = VXGE_HW_ERR_INVALID_HANDLE; | |
4058 | goto exit; | |
4059 | } | |
4060 | vpath = vp->vpath; | |
4061 | ||
4062 | new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE; | |
4063 | ||
4064 | if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu)) | |
4065 | status = VXGE_HW_ERR_INVALID_MTU_SIZE; | |
4066 | ||
4067 | val64 = readq(&vpath->vp_reg->rxmac_vcfg0); | |
4068 | ||
4069 | val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff); | |
4070 | val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu); | |
4071 | ||
4072 | writeq(val64, &vpath->vp_reg->rxmac_vcfg0); | |
4073 | ||
4074 | vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE; | |
4075 | ||
4076 | exit: | |
4077 | return status; | |
4078 | } | |
4079 | ||
4080 | /* | |
4081 | * vxge_hw_vpath_open - Open a virtual path on a given adapter | |
4082 | * This function is used to open access to virtual path of an | |
4083 | * adapter for offload, GRO operations. This function returns | |
4084 | * synchronously. | |
4085 | */ | |
4086 | enum vxge_hw_status | |
4087 | vxge_hw_vpath_open(struct __vxge_hw_device *hldev, | |
4088 | struct vxge_hw_vpath_attr *attr, | |
4089 | struct __vxge_hw_vpath_handle **vpath_handle) | |
4090 | { | |
4091 | struct __vxge_hw_virtualpath *vpath; | |
4092 | struct __vxge_hw_vpath_handle *vp; | |
4093 | enum vxge_hw_status status; | |
4094 | ||
4095 | vpath = &hldev->virtual_paths[attr->vp_id]; | |
4096 | ||
4097 | if (vpath->vp_open == VXGE_HW_VP_OPEN) { | |
4098 | status = VXGE_HW_ERR_INVALID_STATE; | |
4099 | goto vpath_open_exit1; | |
4100 | } | |
4101 | ||
4102 | status = __vxge_hw_vp_initialize(hldev, attr->vp_id, | |
4103 | &hldev->config.vp_config[attr->vp_id]); | |
4104 | ||
4105 | if (status != VXGE_HW_OK) | |
4106 | goto vpath_open_exit1; | |
4107 | ||
4108 | vp = (struct __vxge_hw_vpath_handle *) | |
4109 | vmalloc(sizeof(struct __vxge_hw_vpath_handle)); | |
4110 | if (vp == NULL) { | |
4111 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4112 | goto vpath_open_exit2; | |
4113 | } | |
4114 | ||
4115 | memset(vp, 0, sizeof(struct __vxge_hw_vpath_handle)); | |
4116 | ||
4117 | vp->vpath = vpath; | |
4118 | ||
4119 | if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) { | |
4120 | status = __vxge_hw_fifo_create(vp, &attr->fifo_attr); | |
4121 | if (status != VXGE_HW_OK) | |
4122 | goto vpath_open_exit6; | |
4123 | } | |
4124 | ||
4125 | if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) { | |
4126 | status = __vxge_hw_ring_create(vp, &attr->ring_attr); | |
4127 | if (status != VXGE_HW_OK) | |
4128 | goto vpath_open_exit7; | |
4129 | ||
4130 | __vxge_hw_vpath_prc_configure(hldev, attr->vp_id); | |
4131 | } | |
4132 | ||
4133 | vpath->fifoh->tx_intr_num = | |
4134 | (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) + | |
4135 | VXGE_HW_VPATH_INTR_TX; | |
4136 | ||
4137 | vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev, | |
4138 | VXGE_HW_BLOCK_SIZE); | |
4139 | ||
4140 | if (vpath->stats_block == NULL) { | |
4141 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4142 | goto vpath_open_exit8; | |
4143 | } | |
4144 | ||
4145 | vpath->hw_stats = (struct vxge_hw_vpath_stats_hw_info *)vpath-> | |
4146 | stats_block->memblock; | |
4147 | memset(vpath->hw_stats, 0, | |
4148 | sizeof(struct vxge_hw_vpath_stats_hw_info)); | |
4149 | ||
4150 | hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] = | |
4151 | vpath->hw_stats; | |
4152 | ||
4153 | vpath->hw_stats_sav = | |
4154 | &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id]; | |
4155 | memset(vpath->hw_stats_sav, 0, | |
4156 | sizeof(struct vxge_hw_vpath_stats_hw_info)); | |
4157 | ||
4158 | writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg); | |
4159 | ||
4160 | status = vxge_hw_vpath_stats_enable(vp); | |
4161 | if (status != VXGE_HW_OK) | |
4162 | goto vpath_open_exit8; | |
4163 | ||
4164 | list_add(&vp->item, &vpath->vpath_handles); | |
4165 | ||
4166 | hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id); | |
4167 | ||
4168 | *vpath_handle = vp; | |
4169 | ||
4170 | attr->fifo_attr.userdata = vpath->fifoh; | |
4171 | attr->ring_attr.userdata = vpath->ringh; | |
4172 | ||
4173 | return VXGE_HW_OK; | |
4174 | ||
4175 | vpath_open_exit8: | |
4176 | if (vpath->ringh != NULL) | |
4177 | __vxge_hw_ring_delete(vp); | |
4178 | vpath_open_exit7: | |
4179 | if (vpath->fifoh != NULL) | |
4180 | __vxge_hw_fifo_delete(vp); | |
4181 | vpath_open_exit6: | |
4182 | vfree(vp); | |
4183 | vpath_open_exit2: | |
4184 | __vxge_hw_vp_terminate(hldev, attr->vp_id); | |
4185 | vpath_open_exit1: | |
4186 | ||
4187 | return status; | |
4188 | } | |
4189 | ||
4190 | /** | |
4191 | * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath | |
4192 | * (vpath) open | |
4193 | * @vp: Handle got from previous vpath open | |
4194 | * | |
4195 | * This function is used to close access to virtual path opened | |
4196 | * earlier. | |
4197 | */ | |
4198 | void | |
4199 | vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp) | |
4200 | { | |
4201 | struct __vxge_hw_virtualpath *vpath = NULL; | |
4202 | u64 new_count, val64, val164; | |
4203 | struct __vxge_hw_ring *ring; | |
4204 | ||
4205 | vpath = vp->vpath; | |
4206 | ring = vpath->ringh; | |
4207 | ||
4208 | new_count = readq(&vpath->vp_reg->rxdmem_size); | |
4209 | new_count &= 0x1fff; | |
4210 | val164 = (VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count)); | |
4211 | ||
4212 | writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164), | |
4213 | &vpath->vp_reg->prc_rxd_doorbell); | |
4214 | readl(&vpath->vp_reg->prc_rxd_doorbell); | |
4215 | ||
4216 | val164 /= 2; | |
4217 | val64 = readq(&vpath->vp_reg->prc_cfg6); | |
4218 | val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64); | |
4219 | val64 &= 0x1ff; | |
4220 | ||
4221 | /* | |
4222 | * Each RxD is of 4 qwords | |
4223 | */ | |
4224 | new_count -= (val64 + 1); | |
4225 | val64 = min(val164, new_count) / 4; | |
4226 | ||
4227 | ring->rxds_limit = min(ring->rxds_limit, val64); | |
4228 | if (ring->rxds_limit < 4) | |
4229 | ring->rxds_limit = 4; | |
4230 | } | |
4231 | ||
4232 | /* | |
4233 | * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open | |
4234 | * This function is used to close access to virtual path opened | |
4235 | * earlier. | |
4236 | */ | |
4237 | enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp) | |
4238 | { | |
4239 | struct __vxge_hw_virtualpath *vpath = NULL; | |
4240 | struct __vxge_hw_device *devh = NULL; | |
4241 | u32 vp_id = vp->vpath->vp_id; | |
4242 | u32 is_empty = TRUE; | |
4243 | enum vxge_hw_status status = VXGE_HW_OK; | |
4244 | ||
4245 | vpath = vp->vpath; | |
4246 | devh = vpath->hldev; | |
4247 | ||
4248 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { | |
4249 | status = VXGE_HW_ERR_VPATH_NOT_OPEN; | |
4250 | goto vpath_close_exit; | |
4251 | } | |
4252 | ||
4253 | list_del(&vp->item); | |
4254 | ||
4255 | if (!list_empty(&vpath->vpath_handles)) { | |
4256 | list_add(&vp->item, &vpath->vpath_handles); | |
4257 | is_empty = FALSE; | |
4258 | } | |
4259 | ||
4260 | if (!is_empty) { | |
4261 | status = VXGE_HW_FAIL; | |
4262 | goto vpath_close_exit; | |
4263 | } | |
4264 | ||
4265 | devh->vpaths_deployed &= ~vxge_mBIT(vp_id); | |
4266 | ||
4267 | if (vpath->ringh != NULL) | |
4268 | __vxge_hw_ring_delete(vp); | |
4269 | ||
4270 | if (vpath->fifoh != NULL) | |
4271 | __vxge_hw_fifo_delete(vp); | |
4272 | ||
4273 | if (vpath->stats_block != NULL) | |
4274 | __vxge_hw_blockpool_block_free(devh, vpath->stats_block); | |
4275 | ||
4276 | vfree(vp); | |
4277 | ||
4278 | __vxge_hw_vp_terminate(devh, vp_id); | |
4279 | ||
4280 | vpath->vp_open = VXGE_HW_VP_NOT_OPEN; | |
4281 | ||
4282 | vpath_close_exit: | |
4283 | return status; | |
4284 | } | |
4285 | ||
4286 | /* | |
4287 | * vxge_hw_vpath_reset - Resets vpath | |
4288 | * This function is used to request a reset of vpath | |
4289 | */ | |
4290 | enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp) | |
4291 | { | |
4292 | enum vxge_hw_status status; | |
4293 | u32 vp_id; | |
4294 | struct __vxge_hw_virtualpath *vpath = vp->vpath; | |
4295 | ||
4296 | vp_id = vpath->vp_id; | |
4297 | ||
4298 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { | |
4299 | status = VXGE_HW_ERR_VPATH_NOT_OPEN; | |
4300 | goto exit; | |
4301 | } | |
4302 | ||
4303 | status = __vxge_hw_vpath_reset(vpath->hldev, vp_id); | |
4304 | if (status == VXGE_HW_OK) | |
4305 | vpath->sw_stats->soft_reset_cnt++; | |
4306 | exit: | |
4307 | return status; | |
4308 | } | |
4309 | ||
4310 | /* | |
4311 | * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize. | |
4312 | * This function poll's for the vpath reset completion and re initializes | |
4313 | * the vpath. | |
4314 | */ | |
4315 | enum vxge_hw_status | |
4316 | vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp) | |
4317 | { | |
4318 | struct __vxge_hw_virtualpath *vpath = NULL; | |
4319 | enum vxge_hw_status status; | |
4320 | struct __vxge_hw_device *hldev; | |
4321 | u32 vp_id; | |
4322 | ||
4323 | vp_id = vp->vpath->vp_id; | |
4324 | vpath = vp->vpath; | |
4325 | hldev = vpath->hldev; | |
4326 | ||
4327 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { | |
4328 | status = VXGE_HW_ERR_VPATH_NOT_OPEN; | |
4329 | goto exit; | |
4330 | } | |
4331 | ||
4332 | status = __vxge_hw_vpath_reset_check(vpath); | |
4333 | if (status != VXGE_HW_OK) | |
4334 | goto exit; | |
4335 | ||
4336 | status = __vxge_hw_vpath_sw_reset(hldev, vp_id); | |
4337 | if (status != VXGE_HW_OK) | |
4338 | goto exit; | |
4339 | ||
4340 | status = __vxge_hw_vpath_initialize(hldev, vp_id); | |
4341 | if (status != VXGE_HW_OK) | |
4342 | goto exit; | |
4343 | ||
4344 | if (vpath->ringh != NULL) | |
4345 | __vxge_hw_vpath_prc_configure(hldev, vp_id); | |
4346 | ||
4347 | memset(vpath->hw_stats, 0, | |
4348 | sizeof(struct vxge_hw_vpath_stats_hw_info)); | |
4349 | ||
4350 | memset(vpath->hw_stats_sav, 0, | |
4351 | sizeof(struct vxge_hw_vpath_stats_hw_info)); | |
4352 | ||
4353 | writeq(vpath->stats_block->dma_addr, | |
4354 | &vpath->vp_reg->stats_cfg); | |
4355 | ||
4356 | status = vxge_hw_vpath_stats_enable(vp); | |
4357 | ||
4358 | exit: | |
4359 | return status; | |
4360 | } | |
4361 | ||
4362 | /* | |
4363 | * vxge_hw_vpath_enable - Enable vpath. | |
4364 | * This routine clears the vpath reset thereby enabling a vpath | |
4365 | * to start forwarding frames and generating interrupts. | |
4366 | */ | |
4367 | void | |
4368 | vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp) | |
4369 | { | |
4370 | struct __vxge_hw_device *hldev; | |
4371 | u64 val64; | |
4372 | ||
4373 | hldev = vp->vpath->hldev; | |
4374 | ||
4375 | val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET( | |
4376 | 1 << (16 - vp->vpath->vp_id)); | |
4377 | ||
4378 | __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), | |
4379 | &hldev->common_reg->cmn_rsthdlr_cfg1); | |
4380 | } | |
4381 | ||
4382 | /* | |
4383 | * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics. | |
4384 | * Enable the DMA vpath statistics. The function is to be called to re-enable | |
4385 | * the adapter to update stats into the host memory | |
4386 | */ | |
4387 | enum vxge_hw_status | |
4388 | vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp) | |
4389 | { | |
4390 | enum vxge_hw_status status = VXGE_HW_OK; | |
4391 | struct __vxge_hw_virtualpath *vpath; | |
4392 | ||
4393 | vpath = vp->vpath; | |
4394 | ||
4395 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { | |
4396 | status = VXGE_HW_ERR_VPATH_NOT_OPEN; | |
4397 | goto exit; | |
4398 | } | |
4399 | ||
4400 | memcpy(vpath->hw_stats_sav, vpath->hw_stats, | |
4401 | sizeof(struct vxge_hw_vpath_stats_hw_info)); | |
4402 | ||
4403 | status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats); | |
4404 | exit: | |
4405 | return status; | |
4406 | } | |
4407 | ||
4408 | /* | |
4409 | * __vxge_hw_vpath_stats_access - Get the statistics from the given location | |
4410 | * and offset and perform an operation | |
4411 | */ | |
4412 | enum vxge_hw_status | |
4413 | __vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath, | |
4414 | u32 operation, u32 offset, u64 *stat) | |
4415 | { | |
4416 | u64 val64; | |
4417 | enum vxge_hw_status status = VXGE_HW_OK; | |
4418 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
4419 | ||
4420 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { | |
4421 | status = VXGE_HW_ERR_VPATH_NOT_OPEN; | |
4422 | goto vpath_stats_access_exit; | |
4423 | } | |
4424 | ||
4425 | vp_reg = vpath->vp_reg; | |
4426 | ||
4427 | val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) | | |
4428 | VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE | | |
4429 | VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset); | |
4430 | ||
4431 | status = __vxge_hw_pio_mem_write64(val64, | |
4432 | &vp_reg->xmac_stats_access_cmd, | |
4433 | VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE, | |
4434 | vpath->hldev->config.device_poll_millis); | |
4435 | ||
4436 | if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ)) | |
4437 | *stat = readq(&vp_reg->xmac_stats_access_data); | |
4438 | else | |
4439 | *stat = 0; | |
4440 | ||
4441 | vpath_stats_access_exit: | |
4442 | return status; | |
4443 | } | |
4444 | ||
4445 | /* | |
4446 | * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath | |
4447 | */ | |
4448 | enum vxge_hw_status | |
4449 | __vxge_hw_vpath_xmac_tx_stats_get( | |
4450 | struct __vxge_hw_virtualpath *vpath, | |
4451 | struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats) | |
4452 | { | |
4453 | u64 *val64; | |
4454 | int i; | |
4455 | u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET; | |
4456 | enum vxge_hw_status status = VXGE_HW_OK; | |
4457 | ||
4458 | val64 = (u64 *) vpath_tx_stats; | |
4459 | ||
4460 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { | |
4461 | status = VXGE_HW_ERR_VPATH_NOT_OPEN; | |
4462 | goto exit; | |
4463 | } | |
4464 | ||
4465 | for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) { | |
4466 | status = __vxge_hw_vpath_stats_access(vpath, | |
4467 | VXGE_HW_STATS_OP_READ, | |
4468 | offset, val64); | |
4469 | if (status != VXGE_HW_OK) | |
4470 | goto exit; | |
4471 | offset++; | |
4472 | val64++; | |
4473 | } | |
4474 | exit: | |
4475 | return status; | |
4476 | } | |
4477 | ||
4478 | /* | |
4479 | * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath | |
4480 | */ | |
4481 | enum vxge_hw_status | |
4482 | __vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath, | |
4483 | struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats) | |
4484 | { | |
4485 | u64 *val64; | |
4486 | enum vxge_hw_status status = VXGE_HW_OK; | |
4487 | int i; | |
4488 | u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET; | |
4489 | val64 = (u64 *) vpath_rx_stats; | |
4490 | ||
4491 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { | |
4492 | status = VXGE_HW_ERR_VPATH_NOT_OPEN; | |
4493 | goto exit; | |
4494 | } | |
4495 | for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) { | |
4496 | status = __vxge_hw_vpath_stats_access(vpath, | |
4497 | VXGE_HW_STATS_OP_READ, | |
4498 | offset >> 3, val64); | |
4499 | if (status != VXGE_HW_OK) | |
4500 | goto exit; | |
4501 | ||
4502 | offset += 8; | |
4503 | val64++; | |
4504 | } | |
4505 | exit: | |
4506 | return status; | |
4507 | } | |
4508 | ||
4509 | /* | |
4510 | * __vxge_hw_vpath_stats_get - Get the vpath hw statistics. | |
4511 | */ | |
4512 | enum vxge_hw_status __vxge_hw_vpath_stats_get( | |
4513 | struct __vxge_hw_virtualpath *vpath, | |
4514 | struct vxge_hw_vpath_stats_hw_info *hw_stats) | |
4515 | { | |
4516 | u64 val64; | |
4517 | enum vxge_hw_status status = VXGE_HW_OK; | |
4518 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
4519 | ||
4520 | if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) { | |
4521 | status = VXGE_HW_ERR_VPATH_NOT_OPEN; | |
4522 | goto exit; | |
4523 | } | |
4524 | vp_reg = vpath->vp_reg; | |
4525 | ||
4526 | val64 = readq(&vp_reg->vpath_debug_stats0); | |
4527 | hw_stats->ini_num_mwr_sent = | |
4528 | (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64); | |
4529 | ||
4530 | val64 = readq(&vp_reg->vpath_debug_stats1); | |
4531 | hw_stats->ini_num_mrd_sent = | |
4532 | (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64); | |
4533 | ||
4534 | val64 = readq(&vp_reg->vpath_debug_stats2); | |
4535 | hw_stats->ini_num_cpl_rcvd = | |
4536 | (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64); | |
4537 | ||
4538 | val64 = readq(&vp_reg->vpath_debug_stats3); | |
4539 | hw_stats->ini_num_mwr_byte_sent = | |
4540 | VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64); | |
4541 | ||
4542 | val64 = readq(&vp_reg->vpath_debug_stats4); | |
4543 | hw_stats->ini_num_cpl_byte_rcvd = | |
4544 | VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64); | |
4545 | ||
4546 | val64 = readq(&vp_reg->vpath_debug_stats5); | |
4547 | hw_stats->wrcrdtarb_xoff = | |
4548 | (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64); | |
4549 | ||
4550 | val64 = readq(&vp_reg->vpath_debug_stats6); | |
4551 | hw_stats->rdcrdtarb_xoff = | |
4552 | (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64); | |
4553 | ||
4554 | val64 = readq(&vp_reg->vpath_genstats_count01); | |
4555 | hw_stats->vpath_genstats_count0 = | |
4556 | (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0( | |
4557 | val64); | |
4558 | ||
4559 | val64 = readq(&vp_reg->vpath_genstats_count01); | |
4560 | hw_stats->vpath_genstats_count1 = | |
4561 | (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1( | |
4562 | val64); | |
4563 | ||
4564 | val64 = readq(&vp_reg->vpath_genstats_count23); | |
4565 | hw_stats->vpath_genstats_count2 = | |
4566 | (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2( | |
4567 | val64); | |
4568 | ||
4569 | val64 = readq(&vp_reg->vpath_genstats_count01); | |
4570 | hw_stats->vpath_genstats_count3 = | |
4571 | (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3( | |
4572 | val64); | |
4573 | ||
4574 | val64 = readq(&vp_reg->vpath_genstats_count4); | |
4575 | hw_stats->vpath_genstats_count4 = | |
4576 | (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4( | |
4577 | val64); | |
4578 | ||
4579 | val64 = readq(&vp_reg->vpath_genstats_count5); | |
4580 | hw_stats->vpath_genstats_count5 = | |
4581 | (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5( | |
4582 | val64); | |
4583 | ||
4584 | status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats); | |
4585 | if (status != VXGE_HW_OK) | |
4586 | goto exit; | |
4587 | ||
4588 | status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats); | |
4589 | if (status != VXGE_HW_OK) | |
4590 | goto exit; | |
4591 | ||
4592 | VXGE_HW_VPATH_STATS_PIO_READ( | |
4593 | VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET); | |
4594 | ||
4595 | hw_stats->prog_event_vnum0 = | |
4596 | (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64); | |
4597 | ||
4598 | hw_stats->prog_event_vnum1 = | |
4599 | (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64); | |
4600 | ||
4601 | VXGE_HW_VPATH_STATS_PIO_READ( | |
4602 | VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET); | |
4603 | ||
4604 | hw_stats->prog_event_vnum2 = | |
4605 | (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64); | |
4606 | ||
4607 | hw_stats->prog_event_vnum3 = | |
4608 | (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64); | |
4609 | ||
4610 | val64 = readq(&vp_reg->rx_multi_cast_stats); | |
4611 | hw_stats->rx_multi_cast_frame_discard = | |
4612 | (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64); | |
4613 | ||
4614 | val64 = readq(&vp_reg->rx_frm_transferred); | |
4615 | hw_stats->rx_frm_transferred = | |
4616 | (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64); | |
4617 | ||
4618 | val64 = readq(&vp_reg->rxd_returned); | |
4619 | hw_stats->rxd_returned = | |
4620 | (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64); | |
4621 | ||
4622 | val64 = readq(&vp_reg->dbg_stats_rx_mpa); | |
4623 | hw_stats->rx_mpa_len_fail_frms = | |
4624 | (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64); | |
4625 | hw_stats->rx_mpa_mrk_fail_frms = | |
4626 | (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64); | |
4627 | hw_stats->rx_mpa_crc_fail_frms = | |
4628 | (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64); | |
4629 | ||
4630 | val64 = readq(&vp_reg->dbg_stats_rx_fau); | |
4631 | hw_stats->rx_permitted_frms = | |
4632 | (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64); | |
4633 | hw_stats->rx_vp_reset_discarded_frms = | |
4634 | (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64); | |
4635 | hw_stats->rx_wol_frms = | |
4636 | (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64); | |
4637 | ||
4638 | val64 = readq(&vp_reg->tx_vp_reset_discarded_frms); | |
4639 | hw_stats->tx_vp_reset_discarded_frms = | |
4640 | (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS( | |
4641 | val64); | |
4642 | exit: | |
4643 | return status; | |
4644 | } | |
4645 | ||
4646 | /* | |
4647 | * __vxge_hw_blockpool_create - Create block pool | |
4648 | */ | |
4649 | ||
4650 | enum vxge_hw_status | |
4651 | __vxge_hw_blockpool_create(struct __vxge_hw_device *hldev, | |
4652 | struct __vxge_hw_blockpool *blockpool, | |
4653 | u32 pool_size, | |
4654 | u32 pool_max) | |
4655 | { | |
4656 | u32 i; | |
4657 | struct __vxge_hw_blockpool_entry *entry = NULL; | |
4658 | void *memblock; | |
4659 | dma_addr_t dma_addr; | |
4660 | struct pci_dev *dma_handle; | |
4661 | struct pci_dev *acc_handle; | |
4662 | enum vxge_hw_status status = VXGE_HW_OK; | |
4663 | ||
4664 | if (blockpool == NULL) { | |
4665 | status = VXGE_HW_FAIL; | |
4666 | goto blockpool_create_exit; | |
4667 | } | |
4668 | ||
4669 | blockpool->hldev = hldev; | |
4670 | blockpool->block_size = VXGE_HW_BLOCK_SIZE; | |
4671 | blockpool->pool_size = 0; | |
4672 | blockpool->pool_max = pool_max; | |
4673 | blockpool->req_out = 0; | |
4674 | ||
4675 | INIT_LIST_HEAD(&blockpool->free_block_list); | |
4676 | INIT_LIST_HEAD(&blockpool->free_entry_list); | |
4677 | ||
4678 | for (i = 0; i < pool_size + pool_max; i++) { | |
4679 | entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry), | |
4680 | GFP_KERNEL); | |
4681 | if (entry == NULL) { | |
4682 | __vxge_hw_blockpool_destroy(blockpool); | |
4683 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4684 | goto blockpool_create_exit; | |
4685 | } | |
4686 | list_add(&entry->item, &blockpool->free_entry_list); | |
4687 | } | |
4688 | ||
4689 | for (i = 0; i < pool_size; i++) { | |
4690 | ||
4691 | memblock = vxge_os_dma_malloc( | |
4692 | hldev->pdev, | |
4693 | VXGE_HW_BLOCK_SIZE, | |
4694 | &dma_handle, | |
4695 | &acc_handle); | |
4696 | ||
4697 | if (memblock == NULL) { | |
4698 | __vxge_hw_blockpool_destroy(blockpool); | |
4699 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4700 | goto blockpool_create_exit; | |
4701 | } | |
4702 | ||
4703 | dma_addr = pci_map_single(hldev->pdev, memblock, | |
4704 | VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL); | |
4705 | ||
4706 | if (unlikely(pci_dma_mapping_error(hldev->pdev, | |
4707 | dma_addr))) { | |
4708 | ||
4709 | vxge_os_dma_free(hldev->pdev, memblock, &acc_handle); | |
4710 | __vxge_hw_blockpool_destroy(blockpool); | |
4711 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4712 | goto blockpool_create_exit; | |
4713 | } | |
4714 | ||
4715 | if (!list_empty(&blockpool->free_entry_list)) | |
4716 | entry = (struct __vxge_hw_blockpool_entry *) | |
4717 | list_first_entry(&blockpool->free_entry_list, | |
4718 | struct __vxge_hw_blockpool_entry, | |
4719 | item); | |
4720 | ||
4721 | if (entry == NULL) | |
4722 | entry = | |
4723 | kzalloc(sizeof(struct __vxge_hw_blockpool_entry), | |
4724 | GFP_KERNEL); | |
4725 | if (entry != NULL) { | |
4726 | list_del(&entry->item); | |
4727 | entry->length = VXGE_HW_BLOCK_SIZE; | |
4728 | entry->memblock = memblock; | |
4729 | entry->dma_addr = dma_addr; | |
4730 | entry->acc_handle = acc_handle; | |
4731 | entry->dma_handle = dma_handle; | |
4732 | list_add(&entry->item, | |
4733 | &blockpool->free_block_list); | |
4734 | blockpool->pool_size++; | |
4735 | } else { | |
4736 | __vxge_hw_blockpool_destroy(blockpool); | |
4737 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4738 | goto blockpool_create_exit; | |
4739 | } | |
4740 | } | |
4741 | ||
4742 | blockpool_create_exit: | |
4743 | return status; | |
4744 | } | |
4745 | ||
4746 | /* | |
4747 | * __vxge_hw_blockpool_destroy - Deallocates the block pool | |
4748 | */ | |
4749 | ||
4750 | void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool) | |
4751 | { | |
4752 | ||
4753 | struct __vxge_hw_device *hldev; | |
4754 | struct list_head *p, *n; | |
4755 | u16 ret; | |
4756 | ||
4757 | if (blockpool == NULL) { | |
4758 | ret = 1; | |
4759 | goto exit; | |
4760 | } | |
4761 | ||
4762 | hldev = blockpool->hldev; | |
4763 | ||
4764 | list_for_each_safe(p, n, &blockpool->free_block_list) { | |
4765 | ||
4766 | pci_unmap_single(hldev->pdev, | |
4767 | ((struct __vxge_hw_blockpool_entry *)p)->dma_addr, | |
4768 | ((struct __vxge_hw_blockpool_entry *)p)->length, | |
4769 | PCI_DMA_BIDIRECTIONAL); | |
4770 | ||
4771 | vxge_os_dma_free(hldev->pdev, | |
4772 | ((struct __vxge_hw_blockpool_entry *)p)->memblock, | |
4773 | &((struct __vxge_hw_blockpool_entry *) p)->acc_handle); | |
4774 | ||
4775 | list_del( | |
4776 | &((struct __vxge_hw_blockpool_entry *)p)->item); | |
4777 | kfree(p); | |
4778 | blockpool->pool_size--; | |
4779 | } | |
4780 | ||
4781 | list_for_each_safe(p, n, &blockpool->free_entry_list) { | |
4782 | list_del( | |
4783 | &((struct __vxge_hw_blockpool_entry *)p)->item); | |
4784 | kfree((void *)p); | |
4785 | } | |
4786 | ret = 0; | |
4787 | exit: | |
4788 | return; | |
4789 | } | |
4790 | ||
4791 | /* | |
4792 | * __vxge_hw_blockpool_blocks_add - Request additional blocks | |
4793 | */ | |
4794 | static | |
4795 | void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool) | |
4796 | { | |
4797 | u32 nreq = 0, i; | |
4798 | ||
4799 | if ((blockpool->pool_size + blockpool->req_out) < | |
4800 | VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) { | |
4801 | nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE; | |
4802 | blockpool->req_out += nreq; | |
4803 | } | |
4804 | ||
4805 | for (i = 0; i < nreq; i++) | |
4806 | vxge_os_dma_malloc_async( | |
4807 | ((struct __vxge_hw_device *)blockpool->hldev)->pdev, | |
4808 | blockpool->hldev, VXGE_HW_BLOCK_SIZE); | |
4809 | } | |
4810 | ||
4811 | /* | |
4812 | * __vxge_hw_blockpool_blocks_remove - Free additional blocks | |
4813 | */ | |
4814 | static | |
4815 | void __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool) | |
4816 | { | |
4817 | struct list_head *p, *n; | |
4818 | ||
4819 | list_for_each_safe(p, n, &blockpool->free_block_list) { | |
4820 | ||
4821 | if (blockpool->pool_size < blockpool->pool_max) | |
4822 | break; | |
4823 | ||
4824 | pci_unmap_single( | |
4825 | ((struct __vxge_hw_device *)blockpool->hldev)->pdev, | |
4826 | ((struct __vxge_hw_blockpool_entry *)p)->dma_addr, | |
4827 | ((struct __vxge_hw_blockpool_entry *)p)->length, | |
4828 | PCI_DMA_BIDIRECTIONAL); | |
4829 | ||
4830 | vxge_os_dma_free( | |
4831 | ((struct __vxge_hw_device *)blockpool->hldev)->pdev, | |
4832 | ((struct __vxge_hw_blockpool_entry *)p)->memblock, | |
4833 | &((struct __vxge_hw_blockpool_entry *)p)->acc_handle); | |
4834 | ||
4835 | list_del(&((struct __vxge_hw_blockpool_entry *)p)->item); | |
4836 | ||
4837 | list_add(p, &blockpool->free_entry_list); | |
4838 | ||
4839 | blockpool->pool_size--; | |
4840 | ||
4841 | } | |
4842 | } | |
4843 | ||
4844 | /* | |
4845 | * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async | |
4846 | * Adds a block to block pool | |
4847 | */ | |
4848 | void vxge_hw_blockpool_block_add( | |
4849 | struct __vxge_hw_device *devh, | |
4850 | void *block_addr, | |
4851 | u32 length, | |
4852 | struct pci_dev *dma_h, | |
4853 | struct pci_dev *acc_handle) | |
4854 | { | |
4855 | struct __vxge_hw_blockpool *blockpool; | |
4856 | struct __vxge_hw_blockpool_entry *entry = NULL; | |
4857 | dma_addr_t dma_addr; | |
4858 | enum vxge_hw_status status = VXGE_HW_OK; | |
4859 | u32 req_out; | |
4860 | ||
4861 | blockpool = &devh->block_pool; | |
4862 | ||
4863 | if (block_addr == NULL) { | |
4864 | blockpool->req_out--; | |
4865 | status = VXGE_HW_FAIL; | |
4866 | goto exit; | |
4867 | } | |
4868 | ||
4869 | dma_addr = pci_map_single(devh->pdev, block_addr, length, | |
4870 | PCI_DMA_BIDIRECTIONAL); | |
4871 | ||
4872 | if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) { | |
4873 | ||
4874 | vxge_os_dma_free(devh->pdev, block_addr, &acc_handle); | |
4875 | blockpool->req_out--; | |
4876 | status = VXGE_HW_FAIL; | |
4877 | goto exit; | |
4878 | } | |
4879 | ||
4880 | ||
4881 | if (!list_empty(&blockpool->free_entry_list)) | |
4882 | entry = (struct __vxge_hw_blockpool_entry *) | |
4883 | list_first_entry(&blockpool->free_entry_list, | |
4884 | struct __vxge_hw_blockpool_entry, | |
4885 | item); | |
4886 | ||
4887 | if (entry == NULL) | |
4888 | entry = (struct __vxge_hw_blockpool_entry *) | |
4889 | vmalloc(sizeof(struct __vxge_hw_blockpool_entry)); | |
4890 | else | |
4891 | list_del(&entry->item); | |
4892 | ||
4893 | if (entry != NULL) { | |
4894 | entry->length = length; | |
4895 | entry->memblock = block_addr; | |
4896 | entry->dma_addr = dma_addr; | |
4897 | entry->acc_handle = acc_handle; | |
4898 | entry->dma_handle = dma_h; | |
4899 | list_add(&entry->item, &blockpool->free_block_list); | |
4900 | blockpool->pool_size++; | |
4901 | status = VXGE_HW_OK; | |
4902 | } else | |
4903 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4904 | ||
4905 | blockpool->req_out--; | |
4906 | ||
4907 | req_out = blockpool->req_out; | |
4908 | exit: | |
4909 | return; | |
4910 | } | |
4911 | ||
4912 | /* | |
4913 | * __vxge_hw_blockpool_malloc - Allocate a memory block from pool | |
4914 | * Allocates a block of memory of given size, either from block pool | |
4915 | * or by calling vxge_os_dma_malloc() | |
4916 | */ | |
4917 | void * | |
4918 | __vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size, | |
4919 | struct vxge_hw_mempool_dma *dma_object) | |
4920 | { | |
4921 | struct __vxge_hw_blockpool_entry *entry = NULL; | |
4922 | struct __vxge_hw_blockpool *blockpool; | |
4923 | void *memblock = NULL; | |
4924 | enum vxge_hw_status status = VXGE_HW_OK; | |
4925 | ||
4926 | blockpool = &devh->block_pool; | |
4927 | ||
4928 | if (size != blockpool->block_size) { | |
4929 | ||
4930 | memblock = vxge_os_dma_malloc(devh->pdev, size, | |
4931 | &dma_object->handle, | |
4932 | &dma_object->acc_handle); | |
4933 | ||
4934 | if (memblock == NULL) { | |
4935 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4936 | goto exit; | |
4937 | } | |
4938 | ||
4939 | dma_object->addr = pci_map_single(devh->pdev, memblock, size, | |
4940 | PCI_DMA_BIDIRECTIONAL); | |
4941 | ||
4942 | if (unlikely(pci_dma_mapping_error(devh->pdev, | |
4943 | dma_object->addr))) { | |
4944 | vxge_os_dma_free(devh->pdev, memblock, | |
4945 | &dma_object->acc_handle); | |
4946 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
4947 | goto exit; | |
4948 | } | |
4949 | ||
4950 | } else { | |
4951 | ||
4952 | if (!list_empty(&blockpool->free_block_list)) | |
4953 | entry = (struct __vxge_hw_blockpool_entry *) | |
4954 | list_first_entry(&blockpool->free_block_list, | |
4955 | struct __vxge_hw_blockpool_entry, | |
4956 | item); | |
4957 | ||
4958 | if (entry != NULL) { | |
4959 | list_del(&entry->item); | |
4960 | dma_object->addr = entry->dma_addr; | |
4961 | dma_object->handle = entry->dma_handle; | |
4962 | dma_object->acc_handle = entry->acc_handle; | |
4963 | memblock = entry->memblock; | |
4964 | ||
4965 | list_add(&entry->item, | |
4966 | &blockpool->free_entry_list); | |
4967 | blockpool->pool_size--; | |
4968 | } | |
4969 | ||
4970 | if (memblock != NULL) | |
4971 | __vxge_hw_blockpool_blocks_add(blockpool); | |
4972 | } | |
4973 | exit: | |
4974 | return memblock; | |
4975 | } | |
4976 | ||
4977 | /* | |
4978 | * __vxge_hw_blockpool_free - Frees the memory allcoated with | |
4979 | __vxge_hw_blockpool_malloc | |
4980 | */ | |
4981 | void | |
4982 | __vxge_hw_blockpool_free(struct __vxge_hw_device *devh, | |
4983 | void *memblock, u32 size, | |
4984 | struct vxge_hw_mempool_dma *dma_object) | |
4985 | { | |
4986 | struct __vxge_hw_blockpool_entry *entry = NULL; | |
4987 | struct __vxge_hw_blockpool *blockpool; | |
4988 | enum vxge_hw_status status = VXGE_HW_OK; | |
4989 | ||
4990 | blockpool = &devh->block_pool; | |
4991 | ||
4992 | if (size != blockpool->block_size) { | |
4993 | pci_unmap_single(devh->pdev, dma_object->addr, size, | |
4994 | PCI_DMA_BIDIRECTIONAL); | |
4995 | vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle); | |
4996 | } else { | |
4997 | ||
4998 | if (!list_empty(&blockpool->free_entry_list)) | |
4999 | entry = (struct __vxge_hw_blockpool_entry *) | |
5000 | list_first_entry(&blockpool->free_entry_list, | |
5001 | struct __vxge_hw_blockpool_entry, | |
5002 | item); | |
5003 | ||
5004 | if (entry == NULL) | |
5005 | entry = (struct __vxge_hw_blockpool_entry *) | |
5006 | vmalloc(sizeof( | |
5007 | struct __vxge_hw_blockpool_entry)); | |
5008 | else | |
5009 | list_del(&entry->item); | |
5010 | ||
5011 | if (entry != NULL) { | |
5012 | entry->length = size; | |
5013 | entry->memblock = memblock; | |
5014 | entry->dma_addr = dma_object->addr; | |
5015 | entry->acc_handle = dma_object->acc_handle; | |
5016 | entry->dma_handle = dma_object->handle; | |
5017 | list_add(&entry->item, | |
5018 | &blockpool->free_block_list); | |
5019 | blockpool->pool_size++; | |
5020 | status = VXGE_HW_OK; | |
5021 | } else | |
5022 | status = VXGE_HW_ERR_OUT_OF_MEMORY; | |
5023 | ||
5024 | if (status == VXGE_HW_OK) | |
5025 | __vxge_hw_blockpool_blocks_remove(blockpool); | |
5026 | } | |
40a3a915 RV |
5027 | } |
5028 | ||
5029 | /* | |
5030 | * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool | |
5031 | * This function allocates a block from block pool or from the system | |
5032 | */ | |
5033 | struct __vxge_hw_blockpool_entry * | |
5034 | __vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size) | |
5035 | { | |
5036 | struct __vxge_hw_blockpool_entry *entry = NULL; | |
5037 | struct __vxge_hw_blockpool *blockpool; | |
5038 | ||
5039 | blockpool = &devh->block_pool; | |
5040 | ||
5041 | if (size == blockpool->block_size) { | |
5042 | ||
5043 | if (!list_empty(&blockpool->free_block_list)) | |
5044 | entry = (struct __vxge_hw_blockpool_entry *) | |
5045 | list_first_entry(&blockpool->free_block_list, | |
5046 | struct __vxge_hw_blockpool_entry, | |
5047 | item); | |
5048 | ||
5049 | if (entry != NULL) { | |
5050 | list_del(&entry->item); | |
5051 | blockpool->pool_size--; | |
5052 | } | |
5053 | } | |
5054 | ||
5055 | if (entry != NULL) | |
5056 | __vxge_hw_blockpool_blocks_add(blockpool); | |
5057 | ||
5058 | return entry; | |
5059 | } | |
5060 | ||
5061 | /* | |
5062 | * __vxge_hw_blockpool_block_free - Frees a block from block pool | |
5063 | * @devh: Hal device | |
5064 | * @entry: Entry of block to be freed | |
5065 | * | |
5066 | * This function frees a block from block pool | |
5067 | */ | |
5068 | void | |
5069 | __vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh, | |
5070 | struct __vxge_hw_blockpool_entry *entry) | |
5071 | { | |
5072 | struct __vxge_hw_blockpool *blockpool; | |
5073 | ||
5074 | blockpool = &devh->block_pool; | |
5075 | ||
5076 | if (entry->length == blockpool->block_size) { | |
5077 | list_add(&entry->item, &blockpool->free_block_list); | |
5078 | blockpool->pool_size++; | |
5079 | } | |
5080 | ||
5081 | __vxge_hw_blockpool_blocks_remove(blockpool); | |
40a3a915 | 5082 | } |