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1 | /****************************************************************************** |
2 | * This software may be used and distributed according to the terms of | |
3 | * the GNU General Public License (GPL), incorporated herein by reference. | |
4 | * Drivers based on or derived from this code fall under the GPL and must | |
5 | * retain the authorship, copyright and license notice. This file is not | |
6 | * a complete program and may only be used when the entire operating | |
7 | * system is licensed under the GPL. | |
8 | * See the file COPYING in this distribution for more information. | |
9 | * | |
10 | * vxge-config.h: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O | |
11 | * Virtualized Server Adapter. | |
12 | * Copyright(c) 2002-2009 Neterion Inc. | |
13 | ******************************************************************************/ | |
14 | #ifndef VXGE_CONFIG_H | |
15 | #define VXGE_CONFIG_H | |
16 | #include <linux/list.h> | |
17 | ||
18 | #ifndef VXGE_CACHE_LINE_SIZE | |
19 | #define VXGE_CACHE_LINE_SIZE 128 | |
20 | #endif | |
21 | ||
22 | #define vxge_os_vaprintf(level, mask, fmt, ...) { \ | |
23 | char buff[255]; \ | |
24 | snprintf(buff, 255, fmt, __VA_ARGS__); \ | |
25 | printk(buff); \ | |
26 | printk("\n"); \ | |
27 | } | |
28 | ||
29 | #ifndef VXGE_ALIGN | |
30 | #define VXGE_ALIGN(adrs, size) \ | |
31 | (((size) - (((u64)adrs) & ((size)-1))) & ((size)-1)) | |
32 | #endif | |
33 | ||
34 | #define VXGE_HW_MIN_MTU 68 | |
35 | #define VXGE_HW_MAX_MTU 9600 | |
36 | #define VXGE_HW_DEFAULT_MTU 1500 | |
37 | ||
38 | #ifdef VXGE_DEBUG_ASSERT | |
39 | ||
40 | /** | |
41 | * vxge_assert | |
42 | * @test: C-condition to check | |
43 | * @fmt: printf like format string | |
44 | * | |
45 | * This function implements traditional assert. By default assertions | |
46 | * are enabled. It can be disabled by undefining VXGE_DEBUG_ASSERT macro in | |
47 | * compilation | |
48 | * time. | |
49 | */ | |
50 | #define vxge_assert(test) { \ | |
51 | if (!(test)) \ | |
52 | vxge_os_bug("bad cond: "#test" at %s:%d\n", \ | |
53 | __FILE__, __LINE__); } | |
54 | #else | |
55 | #define vxge_assert(test) | |
56 | #endif /* end of VXGE_DEBUG_ASSERT */ | |
57 | ||
58 | /** | |
59 | * enum enum vxge_debug_level | |
60 | * @VXGE_NONE: debug disabled | |
61 | * @VXGE_ERR: all errors going to be logged out | |
62 | * @VXGE_TRACE: all errors plus all kind of verbose tracing print outs | |
63 | * going to be logged out. Very noisy. | |
64 | * | |
65 | * This enumeration going to be used to switch between different | |
66 | * debug levels during runtime if DEBUG macro defined during | |
67 | * compilation. If DEBUG macro not defined than code will be | |
68 | * compiled out. | |
69 | */ | |
70 | enum vxge_debug_level { | |
71 | VXGE_NONE = 0, | |
72 | VXGE_TRACE = 1, | |
73 | VXGE_ERR = 2 | |
74 | }; | |
75 | ||
76 | #define NULL_VPID 0xFFFFFFFF | |
77 | #ifdef CONFIG_VXGE_DEBUG_TRACE_ALL | |
78 | #define VXGE_DEBUG_MODULE_MASK 0xffffffff | |
79 | #define VXGE_DEBUG_TRACE_MASK 0xffffffff | |
80 | #define VXGE_DEBUG_ERR_MASK 0xffffffff | |
81 | #define VXGE_DEBUG_MASK 0x000001ff | |
82 | #else | |
83 | #define VXGE_DEBUG_MODULE_MASK 0x20000000 | |
84 | #define VXGE_DEBUG_TRACE_MASK 0x20000000 | |
85 | #define VXGE_DEBUG_ERR_MASK 0x20000000 | |
86 | #define VXGE_DEBUG_MASK 0x00000001 | |
87 | #endif | |
88 | ||
89 | /* | |
90 | * @VXGE_COMPONENT_LL: do debug for vxge link layer module | |
91 | * @VXGE_COMPONENT_ALL: activate debug for all modules with no exceptions | |
92 | * | |
93 | * This enumeration going to be used to distinguish modules | |
94 | * or libraries during compilation and runtime. Makefile must declare | |
95 | * VXGE_DEBUG_MODULE_MASK macro and set it to proper value. | |
96 | */ | |
97 | #define VXGE_COMPONENT_LL 0x20000000 | |
98 | #define VXGE_COMPONENT_ALL 0xffffffff | |
99 | ||
100 | #define VXGE_HW_BASE_INF 100 | |
101 | #define VXGE_HW_BASE_ERR 200 | |
102 | #define VXGE_HW_BASE_BADCFG 300 | |
103 | ||
104 | enum vxge_hw_status { | |
105 | VXGE_HW_OK = 0, | |
106 | VXGE_HW_FAIL = 1, | |
107 | VXGE_HW_PENDING = 2, | |
108 | VXGE_HW_COMPLETIONS_REMAIN = 3, | |
109 | ||
110 | VXGE_HW_INF_NO_MORE_COMPLETED_DESCRIPTORS = VXGE_HW_BASE_INF + 1, | |
111 | VXGE_HW_INF_OUT_OF_DESCRIPTORS = VXGE_HW_BASE_INF + 2, | |
112 | ||
113 | VXGE_HW_ERR_INVALID_HANDLE = VXGE_HW_BASE_ERR + 1, | |
114 | VXGE_HW_ERR_OUT_OF_MEMORY = VXGE_HW_BASE_ERR + 2, | |
115 | VXGE_HW_ERR_VPATH_NOT_AVAILABLE = VXGE_HW_BASE_ERR + 3, | |
116 | VXGE_HW_ERR_VPATH_NOT_OPEN = VXGE_HW_BASE_ERR + 4, | |
117 | VXGE_HW_ERR_WRONG_IRQ = VXGE_HW_BASE_ERR + 5, | |
118 | VXGE_HW_ERR_SWAPPER_CTRL = VXGE_HW_BASE_ERR + 6, | |
119 | VXGE_HW_ERR_INVALID_MTU_SIZE = VXGE_HW_BASE_ERR + 7, | |
120 | VXGE_HW_ERR_INVALID_INDEX = VXGE_HW_BASE_ERR + 8, | |
121 | VXGE_HW_ERR_INVALID_TYPE = VXGE_HW_BASE_ERR + 9, | |
122 | VXGE_HW_ERR_INVALID_OFFSET = VXGE_HW_BASE_ERR + 10, | |
123 | VXGE_HW_ERR_INVALID_DEVICE = VXGE_HW_BASE_ERR + 11, | |
124 | VXGE_HW_ERR_VERSION_CONFLICT = VXGE_HW_BASE_ERR + 12, | |
125 | VXGE_HW_ERR_INVALID_PCI_INFO = VXGE_HW_BASE_ERR + 13, | |
126 | VXGE_HW_ERR_INVALID_TCODE = VXGE_HW_BASE_ERR + 14, | |
127 | VXGE_HW_ERR_INVALID_BLOCK_SIZE = VXGE_HW_BASE_ERR + 15, | |
128 | VXGE_HW_ERR_INVALID_STATE = VXGE_HW_BASE_ERR + 16, | |
129 | VXGE_HW_ERR_PRIVILAGED_OPEARATION = VXGE_HW_BASE_ERR + 17, | |
130 | VXGE_HW_ERR_INVALID_PORT = VXGE_HW_BASE_ERR + 18, | |
131 | VXGE_HW_ERR_FIFO = VXGE_HW_BASE_ERR + 19, | |
132 | VXGE_HW_ERR_VPATH = VXGE_HW_BASE_ERR + 20, | |
133 | VXGE_HW_ERR_CRITICAL = VXGE_HW_BASE_ERR + 21, | |
134 | VXGE_HW_ERR_SLOT_FREEZE = VXGE_HW_BASE_ERR + 22, | |
135 | ||
136 | VXGE_HW_BADCFG_RING_INDICATE_MAX_PKTS = VXGE_HW_BASE_BADCFG + 1, | |
137 | VXGE_HW_BADCFG_FIFO_BLOCKS = VXGE_HW_BASE_BADCFG + 2, | |
138 | VXGE_HW_BADCFG_VPATH_MTU = VXGE_HW_BASE_BADCFG + 3, | |
139 | VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG = VXGE_HW_BASE_BADCFG + 4, | |
140 | VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH = VXGE_HW_BASE_BADCFG + 5, | |
141 | VXGE_HW_BADCFG_INTR_MODE = VXGE_HW_BASE_BADCFG + 6, | |
142 | VXGE_HW_BADCFG_RTS_MAC_EN = VXGE_HW_BASE_BADCFG + 7, | |
143 | ||
144 | VXGE_HW_EOF_TRACE_BUF = -1 | |
145 | }; | |
146 | ||
147 | /** | |
148 | * enum enum vxge_hw_device_link_state - Link state enumeration. | |
149 | * @VXGE_HW_LINK_NONE: Invalid link state. | |
150 | * @VXGE_HW_LINK_DOWN: Link is down. | |
151 | * @VXGE_HW_LINK_UP: Link is up. | |
152 | * | |
153 | */ | |
154 | enum vxge_hw_device_link_state { | |
155 | VXGE_HW_LINK_NONE, | |
156 | VXGE_HW_LINK_DOWN, | |
157 | VXGE_HW_LINK_UP | |
158 | }; | |
159 | ||
160 | /** | |
161 | * struct vxge_hw_device_date - Date Format | |
162 | * @day: Day | |
163 | * @month: Month | |
164 | * @year: Year | |
165 | * @date: Date in string format | |
166 | * | |
167 | * Structure for returning date | |
168 | */ | |
169 | ||
170 | #define VXGE_HW_FW_STRLEN 32 | |
171 | struct vxge_hw_device_date { | |
172 | u32 day; | |
173 | u32 month; | |
174 | u32 year; | |
175 | char date[VXGE_HW_FW_STRLEN]; | |
176 | }; | |
177 | ||
178 | struct vxge_hw_device_version { | |
179 | u32 major; | |
180 | u32 minor; | |
181 | u32 build; | |
182 | char version[VXGE_HW_FW_STRLEN]; | |
183 | }; | |
184 | ||
185 | u64 | |
186 | __vxge_hw_vpath_pci_func_mode_get( | |
187 | u32 vp_id, | |
188 | struct vxge_hw_vpath_reg __iomem *vpath_reg); | |
189 | ||
190 | /** | |
191 | * struct vxge_hw_fifo_config - Configuration of fifo. | |
192 | * @enable: Is this fifo to be commissioned | |
193 | * @fifo_blocks: Numbers of TxDL (that is, lists of Tx descriptors) | |
194 | * blocks per queue. | |
195 | * @max_frags: Max number of Tx buffers per TxDL (that is, per single | |
196 | * transmit operation). | |
197 | * No more than 256 transmit buffers can be specified. | |
198 | * @memblock_size: Fifo descriptors are allocated in blocks of @mem_block_size | |
199 | * bytes. Setting @memblock_size to page size ensures | |
200 | * by-page allocation of descriptors. 128K bytes is the | |
201 | * maximum supported block size. | |
202 | * @alignment_size: per Tx fragment DMA-able memory used to align transmit data | |
203 | * (e.g., to align on a cache line). | |
204 | * @intr: Boolean. Use 1 to generate interrupt for each completed TxDL. | |
205 | * Use 0 otherwise. | |
206 | * @no_snoop_bits: If non-zero, specifies no-snoop PCI operation, | |
207 | * which generally improves latency of the host bridge operation | |
208 | * (see PCI specification). For valid values please refer | |
209 | * to struct vxge_hw_fifo_config{} in the driver sources. | |
210 | * Configuration of all Titan fifos. | |
211 | * Note: Valid (min, max) range for each attribute is specified in the body of | |
212 | * the struct vxge_hw_fifo_config{} structure. | |
213 | */ | |
214 | struct vxge_hw_fifo_config { | |
215 | u32 enable; | |
216 | #define VXGE_HW_FIFO_ENABLE 1 | |
217 | #define VXGE_HW_FIFO_DISABLE 0 | |
218 | ||
219 | u32 fifo_blocks; | |
220 | #define VXGE_HW_MIN_FIFO_BLOCKS 2 | |
221 | #define VXGE_HW_MAX_FIFO_BLOCKS 128 | |
222 | ||
223 | u32 max_frags; | |
224 | #define VXGE_HW_MIN_FIFO_FRAGS 1 | |
225 | #define VXGE_HW_MAX_FIFO_FRAGS 256 | |
226 | ||
227 | u32 memblock_size; | |
228 | #define VXGE_HW_MIN_FIFO_MEMBLOCK_SIZE VXGE_HW_BLOCK_SIZE | |
229 | #define VXGE_HW_MAX_FIFO_MEMBLOCK_SIZE 131072 | |
230 | #define VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE 8096 | |
231 | ||
232 | u32 alignment_size; | |
233 | #define VXGE_HW_MIN_FIFO_ALIGNMENT_SIZE 0 | |
234 | #define VXGE_HW_MAX_FIFO_ALIGNMENT_SIZE 65536 | |
235 | #define VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE VXGE_CACHE_LINE_SIZE | |
236 | ||
237 | u32 intr; | |
238 | #define VXGE_HW_FIFO_QUEUE_INTR_ENABLE 1 | |
239 | #define VXGE_HW_FIFO_QUEUE_INTR_DISABLE 0 | |
240 | #define VXGE_HW_FIFO_QUEUE_INTR_DEFAULT 0 | |
241 | ||
242 | u32 no_snoop_bits; | |
243 | #define VXGE_HW_FIFO_NO_SNOOP_DISABLED 0 | |
244 | #define VXGE_HW_FIFO_NO_SNOOP_TXD 1 | |
245 | #define VXGE_HW_FIFO_NO_SNOOP_FRM 2 | |
246 | #define VXGE_HW_FIFO_NO_SNOOP_ALL 3 | |
247 | #define VXGE_HW_FIFO_NO_SNOOP_DEFAULT 0 | |
248 | ||
249 | }; | |
250 | /** | |
251 | * struct vxge_hw_ring_config - Ring configurations. | |
252 | * @enable: Is this ring to be commissioned | |
253 | * @ring_blocks: Numbers of RxD blocks in the ring | |
254 | * @buffer_mode: Receive buffer mode (1, 2, 3, or 5); for details please refer | |
255 | * to Titan User Guide. | |
256 | * @scatter_mode: Titan supports two receive scatter modes: A and B. | |
257 | * For details please refer to Titan User Guide. | |
258 | * @rx_timer_val: The number of 32ns periods that would be counted between two | |
259 | * timer interrupts. | |
260 | * @greedy_return: If Set it forces the device to return absolutely all RxD | |
261 | * that are consumed and still on board when a timer interrupt | |
262 | * triggers. If Clear, then if the device has already returned | |
263 | * RxD before current timer interrupt trigerred and after the | |
264 | * previous timer interrupt triggered, then the device is not | |
265 | * forced to returned the rest of the consumed RxD that it has | |
266 | * on board which account for a byte count less than the one | |
267 | * programmed into PRC_CFG6.RXD_CRXDT field | |
268 | * @rx_timer_ci: TBD | |
269 | * @backoff_interval_us: Time (in microseconds), after which Titan | |
270 | * tries to download RxDs posted by the host. | |
271 | * Note that the "backoff" does not happen if host posts receive | |
272 | * descriptors in the timely fashion. | |
273 | * Ring configuration. | |
274 | */ | |
275 | struct vxge_hw_ring_config { | |
276 | u32 enable; | |
277 | #define VXGE_HW_RING_ENABLE 1 | |
278 | #define VXGE_HW_RING_DISABLE 0 | |
279 | #define VXGE_HW_RING_DEFAULT 1 | |
280 | ||
281 | u32 ring_blocks; | |
282 | #define VXGE_HW_MIN_RING_BLOCKS 1 | |
283 | #define VXGE_HW_MAX_RING_BLOCKS 128 | |
284 | #define VXGE_HW_DEF_RING_BLOCKS 2 | |
285 | ||
286 | u32 buffer_mode; | |
287 | #define VXGE_HW_RING_RXD_BUFFER_MODE_1 1 | |
288 | #define VXGE_HW_RING_RXD_BUFFER_MODE_3 3 | |
289 | #define VXGE_HW_RING_RXD_BUFFER_MODE_5 5 | |
290 | #define VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT 1 | |
291 | ||
292 | u32 scatter_mode; | |
293 | #define VXGE_HW_RING_SCATTER_MODE_A 0 | |
294 | #define VXGE_HW_RING_SCATTER_MODE_B 1 | |
295 | #define VXGE_HW_RING_SCATTER_MODE_C 2 | |
296 | #define VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT 0xffffffff | |
297 | ||
298 | u64 rxds_limit; | |
299 | #define VXGE_HW_DEF_RING_RXDS_LIMIT 44 | |
300 | }; | |
301 | ||
302 | /** | |
303 | * struct vxge_hw_vp_config - Configuration of virtual path | |
304 | * @vp_id: Virtual Path Id | |
305 | * @min_bandwidth: Minimum Guaranteed bandwidth | |
306 | * @ring: See struct vxge_hw_ring_config{}. | |
307 | * @fifo: See struct vxge_hw_fifo_config{}. | |
308 | * @tti: Configuration of interrupt associated with Transmit. | |
309 | * see struct vxge_hw_tim_intr_config(); | |
310 | * @rti: Configuration of interrupt associated with Receive. | |
311 | * see struct vxge_hw_tim_intr_config(); | |
312 | * @mtu: mtu size used on this port. | |
313 | * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to | |
314 | * remove the VLAN tag from all received tagged frames that are not | |
315 | * replicated at the internal L2 switch. | |
316 | * 0 - Do not strip the VLAN tag. | |
317 | * 1 - Strip the VLAN tag. Regardless of this setting, VLAN tags are | |
318 | * always placed into the RxDMA descriptor. | |
319 | * | |
320 | * This structure is used by the driver to pass the configuration parameters to | |
321 | * configure Virtual Path. | |
322 | */ | |
323 | struct vxge_hw_vp_config { | |
324 | u32 vp_id; | |
325 | ||
326 | #define VXGE_HW_VPATH_PRIORITY_MIN 0 | |
327 | #define VXGE_HW_VPATH_PRIORITY_MAX 16 | |
328 | #define VXGE_HW_VPATH_PRIORITY_DEFAULT 0 | |
329 | ||
330 | u32 min_bandwidth; | |
331 | #define VXGE_HW_VPATH_BANDWIDTH_MIN 0 | |
332 | #define VXGE_HW_VPATH_BANDWIDTH_MAX 100 | |
333 | #define VXGE_HW_VPATH_BANDWIDTH_DEFAULT 0 | |
334 | ||
335 | struct vxge_hw_ring_config ring; | |
336 | struct vxge_hw_fifo_config fifo; | |
337 | struct vxge_hw_tim_intr_config tti; | |
338 | struct vxge_hw_tim_intr_config rti; | |
339 | ||
340 | u32 mtu; | |
341 | #define VXGE_HW_VPATH_MIN_INITIAL_MTU VXGE_HW_MIN_MTU | |
342 | #define VXGE_HW_VPATH_MAX_INITIAL_MTU VXGE_HW_MAX_MTU | |
343 | #define VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU 0xffffffff | |
344 | ||
345 | u32 rpa_strip_vlan_tag; | |
346 | #define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE 1 | |
347 | #define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE 0 | |
348 | #define VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT 0xffffffff | |
349 | ||
350 | }; | |
351 | /** | |
352 | * struct vxge_hw_device_config - Device configuration. | |
353 | * @dma_blockpool_initial: Initial size of DMA Pool | |
354 | * @dma_blockpool_max: Maximum blocks in DMA pool | |
355 | * @intr_mode: Line, or MSI-X interrupt. | |
356 | * | |
357 | * @rth_en: Enable Receive Traffic Hashing(RTH) using IT(Indirection Table). | |
358 | * @rth_it_type: RTH IT table programming type | |
359 | * @rts_mac_en: Enable Receive Traffic Steering using MAC destination address | |
360 | * @vp_config: Configuration for virtual paths | |
361 | * @device_poll_millis: Specify the interval (in mulliseconds) | |
362 | * to wait for register reads | |
363 | * | |
364 | * Titan configuration. | |
365 | * Contains per-device configuration parameters, including: | |
366 | * - stats sampling interval, etc. | |
367 | * | |
368 | * In addition, struct vxge_hw_device_config{} includes "subordinate" | |
369 | * configurations, including: | |
370 | * - fifos and rings; | |
371 | * - MAC (done at firmware level). | |
372 | * | |
373 | * See Titan User Guide for more details. | |
374 | * Note: Valid (min, max) range for each attribute is specified in the body of | |
375 | * the struct vxge_hw_device_config{} structure. Please refer to the | |
376 | * corresponding include file. | |
377 | * See also: struct vxge_hw_tim_intr_config{}. | |
378 | */ | |
379 | struct vxge_hw_device_config { | |
380 | u32 dma_blockpool_initial; | |
381 | u32 dma_blockpool_max; | |
382 | #define VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE 0 | |
383 | #define VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE 0 | |
384 | #define VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE 4 | |
385 | #define VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE 4096 | |
386 | ||
387 | #define VXGE_HW_MAX_PAYLOAD_SIZE_512 2 | |
388 | ||
389 | u32 intr_mode; | |
390 | #define VXGE_HW_INTR_MODE_IRQLINE 0 | |
391 | #define VXGE_HW_INTR_MODE_MSIX 1 | |
392 | #define VXGE_HW_INTR_MODE_MSIX_ONE_SHOT 2 | |
393 | ||
394 | #define VXGE_HW_INTR_MODE_DEF 0 | |
395 | ||
396 | u32 rth_en; | |
397 | #define VXGE_HW_RTH_DISABLE 0 | |
398 | #define VXGE_HW_RTH_ENABLE 1 | |
399 | #define VXGE_HW_RTH_DEFAULT 0 | |
400 | ||
401 | u32 rth_it_type; | |
402 | #define VXGE_HW_RTH_IT_TYPE_SOLO_IT 0 | |
403 | #define VXGE_HW_RTH_IT_TYPE_MULTI_IT 1 | |
404 | #define VXGE_HW_RTH_IT_TYPE_DEFAULT 0 | |
405 | ||
406 | u32 rts_mac_en; | |
407 | #define VXGE_HW_RTS_MAC_DISABLE 0 | |
408 | #define VXGE_HW_RTS_MAC_ENABLE 1 | |
409 | #define VXGE_HW_RTS_MAC_DEFAULT 0 | |
410 | ||
411 | struct vxge_hw_vp_config vp_config[VXGE_HW_MAX_VIRTUAL_PATHS]; | |
412 | ||
413 | u32 device_poll_millis; | |
414 | #define VXGE_HW_MIN_DEVICE_POLL_MILLIS 1 | |
415 | #define VXGE_HW_MAX_DEVICE_POLL_MILLIS 100000 | |
416 | #define VXGE_HW_DEF_DEVICE_POLL_MILLIS 1000 | |
417 | ||
418 | }; | |
419 | ||
420 | /** | |
421 | * function vxge_uld_link_up_f - Link-Up callback provided by driver. | |
422 | * @devh: HW device handle. | |
423 | * Link-up notification callback provided by the driver. | |
424 | * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. | |
425 | * | |
426 | * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_down_f{}, | |
427 | * vxge_hw_driver_initialize(). | |
428 | */ | |
429 | ||
430 | /** | |
431 | * function vxge_uld_link_down_f - Link-Down callback provided by | |
432 | * driver. | |
433 | * @devh: HW device handle. | |
434 | * | |
435 | * Link-Down notification callback provided by the driver. | |
436 | * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. | |
437 | * | |
438 | * See also: struct vxge_hw_uld_cbs{}, vxge_uld_link_up_f{}, | |
439 | * vxge_hw_driver_initialize(). | |
440 | */ | |
441 | ||
442 | /** | |
443 | * function vxge_uld_crit_err_f - Critical Error notification callback. | |
444 | * @devh: HW device handle. | |
445 | * (typically - at HW device iinitialization time). | |
446 | * @type: Enumerated hw error, e.g.: double ECC. | |
447 | * @serr_data: Titan status. | |
448 | * @ext_data: Extended data. The contents depends on the @type. | |
449 | * | |
450 | * Link-Down notification callback provided by the driver. | |
451 | * This is one of the per-driver callbacks, see struct vxge_hw_uld_cbs{}. | |
452 | * | |
453 | * See also: struct vxge_hw_uld_cbs{}, enum vxge_hw_event{}, | |
454 | * vxge_hw_driver_initialize(). | |
455 | */ | |
456 | ||
457 | /** | |
458 | * struct vxge_hw_uld_cbs - driver "slow-path" callbacks. | |
459 | * @link_up: See vxge_uld_link_up_f{}. | |
460 | * @link_down: See vxge_uld_link_down_f{}. | |
461 | * @crit_err: See vxge_uld_crit_err_f{}. | |
462 | * | |
463 | * Driver slow-path (per-driver) callbacks. | |
464 | * Implemented by driver and provided to HW via | |
465 | * vxge_hw_driver_initialize(). | |
466 | * Note that these callbacks are not mandatory: HW will not invoke | |
467 | * a callback if NULL is specified. | |
468 | * | |
469 | * See also: vxge_hw_driver_initialize(). | |
470 | */ | |
471 | struct vxge_hw_uld_cbs { | |
472 | ||
473 | void (*link_up)(struct __vxge_hw_device *devh); | |
474 | void (*link_down)(struct __vxge_hw_device *devh); | |
475 | void (*crit_err)(struct __vxge_hw_device *devh, | |
476 | enum vxge_hw_event type, u64 ext_data); | |
477 | }; | |
478 | ||
479 | /* | |
480 | * struct __vxge_hw_blockpool_entry - Block private data structure | |
481 | * @item: List header used to link. | |
482 | * @length: Length of the block | |
483 | * @memblock: Virtual address block | |
484 | * @dma_addr: DMA Address of the block. | |
485 | * @dma_handle: DMA handle of the block. | |
486 | * @acc_handle: DMA acc handle | |
487 | * | |
488 | * Block is allocated with a header to put the blocks into list. | |
489 | * | |
490 | */ | |
491 | struct __vxge_hw_blockpool_entry { | |
492 | struct list_head item; | |
493 | u32 length; | |
494 | void *memblock; | |
495 | dma_addr_t dma_addr; | |
496 | struct pci_dev *dma_handle; | |
497 | struct pci_dev *acc_handle; | |
498 | }; | |
499 | ||
500 | /* | |
501 | * struct __vxge_hw_blockpool - Block Pool | |
502 | * @hldev: HW device | |
503 | * @block_size: size of each block. | |
504 | * @Pool_size: Number of blocks in the pool | |
505 | * @pool_max: Maximum number of blocks above which to free additional blocks | |
506 | * @req_out: Number of block requests with OS out standing | |
507 | * @free_block_list: List of free blocks | |
508 | * | |
509 | * Block pool contains the DMA blocks preallocated. | |
510 | * | |
511 | */ | |
512 | struct __vxge_hw_blockpool { | |
513 | struct __vxge_hw_device *hldev; | |
514 | u32 block_size; | |
515 | u32 pool_size; | |
516 | u32 pool_max; | |
517 | u32 req_out; | |
518 | struct list_head free_block_list; | |
519 | struct list_head free_entry_list; | |
520 | }; | |
521 | ||
522 | /* | |
523 | * enum enum __vxge_hw_channel_type - Enumerated channel types. | |
524 | * @VXGE_HW_CHANNEL_TYPE_UNKNOWN: Unknown channel. | |
525 | * @VXGE_HW_CHANNEL_TYPE_FIFO: fifo. | |
526 | * @VXGE_HW_CHANNEL_TYPE_RING: ring. | |
527 | * @VXGE_HW_CHANNEL_TYPE_MAX: Maximum number of HW-supported | |
528 | * (and recognized) channel types. Currently: 2. | |
529 | * | |
530 | * Enumerated channel types. Currently there are only two link-layer | |
531 | * channels - Titan fifo and Titan ring. In the future the list will grow. | |
532 | */ | |
533 | enum __vxge_hw_channel_type { | |
534 | VXGE_HW_CHANNEL_TYPE_UNKNOWN = 0, | |
535 | VXGE_HW_CHANNEL_TYPE_FIFO = 1, | |
536 | VXGE_HW_CHANNEL_TYPE_RING = 2, | |
537 | VXGE_HW_CHANNEL_TYPE_MAX = 3 | |
538 | }; | |
539 | ||
540 | /* | |
541 | * struct __vxge_hw_channel | |
542 | * @item: List item; used to maintain a list of open channels. | |
543 | * @type: Channel type. See enum vxge_hw_channel_type{}. | |
544 | * @devh: Device handle. HW device object that contains _this_ channel. | |
545 | * @vph: Virtual path handle. Virtual Path Object that contains _this_ channel. | |
546 | * @length: Channel length. Currently allocated number of descriptors. | |
547 | * The channel length "grows" when more descriptors get allocated. | |
548 | * See _hw_mempool_grow. | |
549 | * @reserve_arr: Reserve array. Contains descriptors that can be reserved | |
550 | * by driver for the subsequent send or receive operation. | |
551 | * See vxge_hw_fifo_txdl_reserve(), | |
552 | * vxge_hw_ring_rxd_reserve(). | |
553 | * @reserve_ptr: Current pointer in the resrve array | |
554 | * @reserve_top: Reserve top gives the maximum number of dtrs available in | |
555 | * reserve array. | |
556 | * @work_arr: Work array. Contains descriptors posted to the channel. | |
557 | * Note that at any point in time @work_arr contains 3 types of | |
558 | * descriptors: | |
559 | * 1) posted but not yet consumed by Titan device; | |
560 | * 2) consumed but not yet completed; | |
561 | * 3) completed but not yet freed | |
562 | * (via vxge_hw_fifo_txdl_free() or vxge_hw_ring_rxd_free()) | |
563 | * @post_index: Post index. At any point in time points on the | |
564 | * position in the channel, which'll contain next to-be-posted | |
565 | * descriptor. | |
566 | * @compl_index: Completion index. At any point in time points on the | |
567 | * position in the channel, which will contain next | |
568 | * to-be-completed descriptor. | |
569 | * @free_arr: Free array. Contains completed descriptors that were freed | |
570 | * (i.e., handed over back to HW) by driver. | |
571 | * See vxge_hw_fifo_txdl_free(), vxge_hw_ring_rxd_free(). | |
572 | * @free_ptr: current pointer in free array | |
573 | * @per_dtr_space: Per-descriptor space (in bytes) that channel user can utilize | |
574 | * to store per-operation control information. | |
575 | * @stats: Pointer to common statistics | |
576 | * @userdata: Per-channel opaque (void*) user-defined context, which may be | |
577 | * driver object, ULP connection, etc. | |
578 | * Once channel is open, @userdata is passed back to user via | |
579 | * vxge_hw_channel_callback_f. | |
580 | * | |
581 | * HW channel object. | |
582 | * | |
583 | * See also: enum vxge_hw_channel_type{}, enum vxge_hw_channel_flag | |
584 | */ | |
585 | struct __vxge_hw_channel { | |
586 | struct list_head item; | |
587 | enum __vxge_hw_channel_type type; | |
588 | struct __vxge_hw_device *devh; | |
589 | struct __vxge_hw_vpath_handle *vph; | |
590 | u32 length; | |
591 | u32 vp_id; | |
592 | void **reserve_arr; | |
593 | u32 reserve_ptr; | |
594 | u32 reserve_top; | |
595 | void **work_arr; | |
596 | u32 post_index ____cacheline_aligned; | |
597 | u32 compl_index ____cacheline_aligned; | |
598 | void **free_arr; | |
599 | u32 free_ptr; | |
600 | void **orig_arr; | |
601 | u32 per_dtr_space; | |
602 | void *userdata; | |
603 | struct vxge_hw_common_reg __iomem *common_reg; | |
604 | u32 first_vp_id; | |
605 | struct vxge_hw_vpath_stats_sw_common_info *stats; | |
606 | ||
607 | } ____cacheline_aligned; | |
608 | ||
609 | /* | |
610 | * struct __vxge_hw_virtualpath - Virtual Path | |
611 | * | |
612 | * @vp_id: Virtual path id | |
613 | * @vp_open: This flag specifies if vxge_hw_vp_open is called from LL Driver | |
614 | * @hldev: Hal device | |
615 | * @vp_config: Virtual Path Config | |
616 | * @vp_reg: VPATH Register map address in BAR0 | |
617 | * @vpmgmt_reg: VPATH_MGMT register map address | |
618 | * @max_mtu: Max mtu that can be supported | |
619 | * @vsport_number: vsport attached to this vpath | |
620 | * @max_kdfc_db: Maximum kernel mode doorbells | |
621 | * @max_nofl_db: Maximum non offload doorbells | |
622 | * @tx_intr_num: Interrupt Number associated with the TX | |
623 | ||
624 | * @ringh: Ring Queue | |
625 | * @fifoh: FIFO Queue | |
626 | * @vpath_handles: Virtual Path handles list | |
627 | * @stats_block: Memory for DMAing stats | |
628 | * @stats: Vpath statistics | |
629 | * | |
630 | * Virtual path structure to encapsulate the data related to a virtual path. | |
631 | * Virtual paths are allocated by the HW upon getting configuration from the | |
632 | * driver and inserted into the list of virtual paths. | |
633 | */ | |
634 | struct __vxge_hw_virtualpath { | |
635 | u32 vp_id; | |
636 | ||
637 | u32 vp_open; | |
638 | #define VXGE_HW_VP_NOT_OPEN 0 | |
639 | #define VXGE_HW_VP_OPEN 1 | |
640 | ||
641 | struct __vxge_hw_device *hldev; | |
642 | struct vxge_hw_vp_config *vp_config; | |
643 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
644 | struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg; | |
645 | struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db; | |
646 | ||
647 | u32 max_mtu; | |
648 | u32 vsport_number; | |
649 | u32 max_kdfc_db; | |
650 | u32 max_nofl_db; | |
651 | ||
652 | struct __vxge_hw_ring *____cacheline_aligned ringh; | |
653 | struct __vxge_hw_fifo *____cacheline_aligned fifoh; | |
654 | struct list_head vpath_handles; | |
655 | struct __vxge_hw_blockpool_entry *stats_block; | |
656 | struct vxge_hw_vpath_stats_hw_info *hw_stats; | |
657 | struct vxge_hw_vpath_stats_hw_info *hw_stats_sav; | |
658 | struct vxge_hw_vpath_stats_sw_info *sw_stats; | |
659 | }; | |
660 | ||
661 | /* | |
662 | * struct __vxge_hw_vpath_handle - List item to store callback information | |
663 | * @item: List head to keep the item in linked list | |
664 | * @vpath: Virtual path to which this item belongs | |
665 | * | |
666 | * This structure is used to store the callback information. | |
667 | */ | |
668 | struct __vxge_hw_vpath_handle{ | |
669 | struct list_head item; | |
670 | struct __vxge_hw_virtualpath *vpath; | |
671 | }; | |
672 | ||
673 | /* | |
674 | * struct __vxge_hw_device | |
675 | * | |
676 | * HW device object. | |
677 | */ | |
678 | /** | |
679 | * struct __vxge_hw_device - Hal device object | |
680 | * @magic: Magic Number | |
681 | * @device_id: PCI Device Id of the adapter | |
682 | * @major_revision: PCI Device major revision | |
683 | * @minor_revision: PCI Device minor revision | |
684 | * @bar0: BAR0 virtual address. | |
685 | * @bar1: BAR1 virtual address. | |
686 | * @bar2: BAR2 virtual address. | |
687 | * @pdev: Physical device handle | |
688 | * @config: Confguration passed by the LL driver at initialization | |
689 | * @link_state: Link state | |
690 | * | |
691 | * HW device object. Represents Titan adapter | |
692 | */ | |
693 | struct __vxge_hw_device { | |
694 | u32 magic; | |
695 | #define VXGE_HW_DEVICE_MAGIC 0x12345678 | |
696 | #define VXGE_HW_DEVICE_DEAD 0xDEADDEAD | |
697 | u16 device_id; | |
698 | u8 major_revision; | |
699 | u8 minor_revision; | |
700 | void __iomem *bar0; | |
701 | void __iomem *bar1; | |
702 | void __iomem *bar2; | |
703 | struct pci_dev *pdev; | |
704 | struct net_device *ndev; | |
705 | struct vxge_hw_device_config config; | |
706 | enum vxge_hw_device_link_state link_state; | |
707 | ||
708 | struct vxge_hw_uld_cbs uld_callbacks; | |
709 | ||
710 | u32 host_type; | |
711 | u32 func_id; | |
712 | u32 access_rights; | |
713 | #define VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH 0x1 | |
714 | #define VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM 0x2 | |
715 | #define VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM 0x4 | |
716 | struct vxge_hw_legacy_reg __iomem *legacy_reg; | |
717 | struct vxge_hw_toc_reg __iomem *toc_reg; | |
718 | struct vxge_hw_common_reg __iomem *common_reg; | |
719 | struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg; | |
720 | struct vxge_hw_srpcim_reg __iomem *srpcim_reg \ | |
721 | [VXGE_HW_TITAN_SRPCIM_REG_SPACES]; | |
722 | struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg \ | |
723 | [VXGE_HW_TITAN_VPMGMT_REG_SPACES]; | |
724 | struct vxge_hw_vpath_reg __iomem *vpath_reg \ | |
725 | [VXGE_HW_TITAN_VPATH_REG_SPACES]; | |
726 | u8 __iomem *kdfc; | |
727 | u8 __iomem *usdc; | |
728 | struct __vxge_hw_virtualpath virtual_paths \ | |
729 | [VXGE_HW_MAX_VIRTUAL_PATHS]; | |
730 | u64 vpath_assignments; | |
731 | u64 vpaths_deployed; | |
732 | u32 first_vp_id; | |
733 | u64 tim_int_mask0[4]; | |
734 | u32 tim_int_mask1[4]; | |
735 | ||
736 | struct __vxge_hw_blockpool block_pool; | |
737 | struct vxge_hw_device_stats stats; | |
738 | u32 debug_module_mask; | |
739 | u32 debug_level; | |
740 | u32 level_err; | |
741 | u32 level_trace; | |
742 | }; | |
743 | ||
744 | #define VXGE_HW_INFO_LEN 64 | |
745 | /** | |
746 | * struct vxge_hw_device_hw_info - Device information | |
747 | * @host_type: Host Type | |
748 | * @func_id: Function Id | |
749 | * @vpath_mask: vpath bit mask | |
750 | * @fw_version: Firmware version | |
751 | * @fw_date: Firmware Date | |
752 | * @flash_version: Firmware version | |
753 | * @flash_date: Firmware Date | |
754 | * @mac_addrs: Mac addresses for each vpath | |
755 | * @mac_addr_masks: Mac address masks for each vpath | |
756 | * | |
757 | * Returns the vpath mask that has the bits set for each vpath allocated | |
758 | * for the driver and the first mac address for each vpath | |
759 | */ | |
760 | struct vxge_hw_device_hw_info { | |
761 | u32 host_type; | |
762 | #define VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION 0 | |
763 | #define VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION 1 | |
764 | #define VXGE_HW_NO_MR_SR_VH0_FUNCTION0 2 | |
765 | #define VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION 3 | |
766 | #define VXGE_HW_MR_SR_VH0_INVALID_CONFIG 4 | |
767 | #define VXGE_HW_SR_VH_FUNCTION0 5 | |
768 | #define VXGE_HW_SR_VH_VIRTUAL_FUNCTION 6 | |
769 | #define VXGE_HW_VH_NORMAL_FUNCTION 7 | |
770 | u64 function_mode; | |
771 | #define VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION 0 | |
772 | #define VXGE_HW_FUNCTION_MODE_SINGLE_FUNCTION 1 | |
773 | #define VXGE_HW_FUNCTION_MODE_SRIOV 2 | |
774 | #define VXGE_HW_FUNCTION_MODE_MRIOV 3 | |
775 | u32 func_id; | |
776 | u64 vpath_mask; | |
777 | struct vxge_hw_device_version fw_version; | |
778 | struct vxge_hw_device_date fw_date; | |
779 | struct vxge_hw_device_version flash_version; | |
780 | struct vxge_hw_device_date flash_date; | |
781 | u8 serial_number[VXGE_HW_INFO_LEN]; | |
782 | u8 part_number[VXGE_HW_INFO_LEN]; | |
783 | u8 product_desc[VXGE_HW_INFO_LEN]; | |
784 | u8 (mac_addrs)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN]; | |
785 | u8 (mac_addr_masks)[VXGE_HW_MAX_VIRTUAL_PATHS][ETH_ALEN]; | |
786 | }; | |
787 | ||
788 | /** | |
789 | * struct vxge_hw_device_attr - Device memory spaces. | |
790 | * @bar0: BAR0 virtual address. | |
791 | * @bar1: BAR1 virtual address. | |
792 | * @bar2: BAR2 virtual address. | |
793 | * @pdev: PCI device object. | |
794 | * | |
795 | * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device | |
796 | * mapped memories. Also, includes a pointer to OS-specific PCI device object. | |
797 | */ | |
798 | struct vxge_hw_device_attr { | |
799 | void __iomem *bar0; | |
800 | void __iomem *bar1; | |
801 | void __iomem *bar2; | |
802 | struct pci_dev *pdev; | |
803 | struct vxge_hw_uld_cbs uld_callbacks; | |
804 | }; | |
805 | ||
806 | #define VXGE_HW_DEVICE_LINK_STATE_SET(hldev, ls) (hldev->link_state = ls) | |
807 | ||
808 | #define VXGE_HW_DEVICE_TIM_INT_MASK_SET(m0, m1, i) { \ | |
809 | if (i < 16) { \ | |
810 | m0[0] |= vxge_vBIT(0x8, (i*4), 4); \ | |
811 | m0[1] |= vxge_vBIT(0x4, (i*4), 4); \ | |
812 | } \ | |
813 | else { \ | |
814 | m1[0] = 0x80000000; \ | |
815 | m1[1] = 0x40000000; \ | |
816 | } \ | |
817 | } | |
818 | ||
819 | #define VXGE_HW_DEVICE_TIM_INT_MASK_RESET(m0, m1, i) { \ | |
820 | if (i < 16) { \ | |
821 | m0[0] &= ~vxge_vBIT(0x8, (i*4), 4); \ | |
822 | m0[1] &= ~vxge_vBIT(0x4, (i*4), 4); \ | |
823 | } \ | |
824 | else { \ | |
825 | m1[0] = 0; \ | |
826 | m1[1] = 0; \ | |
827 | } \ | |
828 | } | |
829 | ||
830 | #define VXGE_HW_DEVICE_STATS_PIO_READ(loc, offset) { \ | |
831 | status = vxge_hw_mrpcim_stats_access(hldev, \ | |
832 | VXGE_HW_STATS_OP_READ, \ | |
833 | loc, \ | |
834 | offset, \ | |
835 | &val64); \ | |
836 | \ | |
837 | if (status != VXGE_HW_OK) \ | |
838 | return status; \ | |
839 | } | |
840 | ||
841 | #define VXGE_HW_VPATH_STATS_PIO_READ(offset) { \ | |
842 | status = __vxge_hw_vpath_stats_access(vpath, \ | |
843 | VXGE_HW_STATS_OP_READ, \ | |
844 | offset, \ | |
845 | &val64); \ | |
846 | if (status != VXGE_HW_OK) \ | |
847 | return status; \ | |
848 | } | |
849 | ||
850 | /* | |
851 | * struct __vxge_hw_ring - Ring channel. | |
852 | * @channel: Channel "base" of this ring, the common part of all HW | |
853 | * channels. | |
854 | * @mempool: Memory pool, the pool from which descriptors get allocated. | |
855 | * (See vxge_hw_mm.h). | |
856 | * @config: Ring configuration, part of device configuration | |
857 | * (see struct vxge_hw_device_config{}). | |
858 | * @ring_length: Length of the ring | |
859 | * @buffer_mode: 1, 3, or 5. The value specifies a receive buffer mode, | |
860 | * as per Titan User Guide. | |
861 | * @rxd_size: RxD sizes for 1-, 3- or 5- buffer modes. As per Titan spec, | |
862 | * 1-buffer mode descriptor is 32 byte long, etc. | |
863 | * @rxd_priv_size: Per RxD size reserved (by HW) for driver to keep | |
864 | * per-descriptor data (e.g., DMA handle for Solaris) | |
865 | * @per_rxd_space: Per rxd space requested by driver | |
866 | * @rxds_per_block: Number of descriptors per hardware-defined RxD | |
867 | * block. Depends on the (1-, 3-, 5-) buffer mode. | |
868 | * @rxdblock_priv_size: Reserved at the end of each RxD block. HW internal | |
869 | * usage. Not to confuse with @rxd_priv_size. | |
870 | * @cmpl_cnt: Completion counter. Is reset to zero upon entering the ISR. | |
871 | * @callback: Channel completion callback. HW invokes the callback when there | |
872 | * are new completions on that channel. In many implementations | |
873 | * the @callback executes in the hw interrupt context. | |
874 | * @rxd_init: Channel's descriptor-initialize callback. | |
875 | * See vxge_hw_ring_rxd_init_f{}. | |
876 | * If not NULL, HW invokes the callback when opening | |
877 | * the ring. | |
878 | * @rxd_term: Channel's descriptor-terminate callback. If not NULL, | |
879 | * HW invokes the callback when closing the corresponding channel. | |
880 | * See also vxge_hw_channel_rxd_term_f{}. | |
881 | * @stats: Statistics for ring | |
882 | * Ring channel. | |
883 | * | |
884 | * Note: The structure is cache line aligned to better utilize | |
885 | * CPU cache performance. | |
886 | */ | |
887 | struct __vxge_hw_ring { | |
888 | struct __vxge_hw_channel channel; | |
889 | struct vxge_hw_mempool *mempool; | |
890 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
891 | struct vxge_hw_common_reg __iomem *common_reg; | |
892 | u32 ring_length; | |
893 | u32 buffer_mode; | |
894 | u32 rxd_size; | |
895 | u32 rxd_priv_size; | |
896 | u32 per_rxd_space; | |
897 | u32 rxds_per_block; | |
898 | u32 rxdblock_priv_size; | |
899 | u32 cmpl_cnt; | |
900 | u32 vp_id; | |
901 | u32 doorbell_cnt; | |
902 | u32 total_db_cnt; | |
903 | u64 rxds_limit; | |
904 | ||
905 | enum vxge_hw_status (*callback)( | |
906 | struct __vxge_hw_ring *ringh, | |
907 | void *rxdh, | |
908 | u8 t_code, | |
909 | void *userdata); | |
910 | ||
911 | enum vxge_hw_status (*rxd_init)( | |
912 | void *rxdh, | |
913 | void *userdata); | |
914 | ||
915 | void (*rxd_term)( | |
916 | void *rxdh, | |
917 | enum vxge_hw_rxd_state state, | |
918 | void *userdata); | |
919 | ||
920 | struct vxge_hw_vpath_stats_sw_ring_info *stats ____cacheline_aligned; | |
921 | struct vxge_hw_ring_config *config; | |
922 | } ____cacheline_aligned; | |
923 | ||
924 | /** | |
925 | * enum enum vxge_hw_txdl_state - Descriptor (TXDL) state. | |
926 | * @VXGE_HW_TXDL_STATE_NONE: Invalid state. | |
927 | * @VXGE_HW_TXDL_STATE_AVAIL: Descriptor is available for reservation. | |
928 | * @VXGE_HW_TXDL_STATE_POSTED: Descriptor is posted for processing by the | |
929 | * device. | |
930 | * @VXGE_HW_TXDL_STATE_FREED: Descriptor is free and can be reused for | |
931 | * filling-in and posting later. | |
932 | * | |
933 | * Titan/HW descriptor states. | |
934 | * | |
935 | */ | |
936 | enum vxge_hw_txdl_state { | |
937 | VXGE_HW_TXDL_STATE_NONE = 0, | |
938 | VXGE_HW_TXDL_STATE_AVAIL = 1, | |
939 | VXGE_HW_TXDL_STATE_POSTED = 2, | |
940 | VXGE_HW_TXDL_STATE_FREED = 3 | |
941 | }; | |
942 | /* | |
943 | * struct __vxge_hw_fifo - Fifo. | |
944 | * @channel: Channel "base" of this fifo, the common part of all HW | |
945 | * channels. | |
946 | * @mempool: Memory pool, from which descriptors get allocated. | |
947 | * @config: Fifo configuration, part of device configuration | |
948 | * (see struct vxge_hw_device_config{}). | |
949 | * @interrupt_type: Interrupt type to be used | |
950 | * @no_snoop_bits: See struct vxge_hw_fifo_config{}. | |
951 | * @txdl_per_memblock: Number of TxDLs (TxD lists) per memblock. | |
952 | * on TxDL please refer to Titan UG. | |
953 | * @txdl_size: Configured TxDL size (i.e., number of TxDs in a list), plus | |
954 | * per-TxDL HW private space (struct __vxge_hw_fifo_txdl_priv). | |
955 | * @priv_size: Per-Tx descriptor space reserved for driver | |
956 | * usage. | |
957 | * @per_txdl_space: Per txdl private space for the driver | |
958 | * @callback: Fifo completion callback. HW invokes the callback when there | |
959 | * are new completions on that fifo. In many implementations | |
960 | * the @callback executes in the hw interrupt context. | |
961 | * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, | |
962 | * HW invokes the callback when closing the corresponding fifo. | |
963 | * See also vxge_hw_fifo_txdl_term_f{}. | |
964 | * @stats: Statistics of this fifo | |
965 | * | |
966 | * Fifo channel. | |
967 | * Note: The structure is cache line aligned. | |
968 | */ | |
969 | struct __vxge_hw_fifo { | |
970 | struct __vxge_hw_channel channel; | |
971 | struct vxge_hw_mempool *mempool; | |
972 | struct vxge_hw_fifo_config *config; | |
973 | struct vxge_hw_vpath_reg __iomem *vp_reg; | |
974 | struct __vxge_hw_non_offload_db_wrapper __iomem *nofl_db; | |
975 | u64 interrupt_type; | |
976 | u32 no_snoop_bits; | |
977 | u32 txdl_per_memblock; | |
978 | u32 txdl_size; | |
979 | u32 priv_size; | |
980 | u32 per_txdl_space; | |
981 | u32 vp_id; | |
982 | u32 tx_intr_num; | |
983 | ||
984 | enum vxge_hw_status (*callback)( | |
985 | struct __vxge_hw_fifo *fifo_handle, | |
986 | void *txdlh, | |
987 | enum vxge_hw_fifo_tcode t_code, | |
988 | void *userdata, | |
989 | void **skb_ptr); | |
990 | ||
991 | void (*txdl_term)( | |
992 | void *txdlh, | |
993 | enum vxge_hw_txdl_state state, | |
994 | void *userdata); | |
995 | ||
996 | struct vxge_hw_vpath_stats_sw_fifo_info *stats ____cacheline_aligned; | |
997 | } ____cacheline_aligned; | |
998 | ||
999 | /* | |
1000 | * struct __vxge_hw_fifo_txdl_priv - Transmit descriptor HW-private data. | |
1001 | * @dma_addr: DMA (mapped) address of _this_ descriptor. | |
1002 | * @dma_handle: DMA handle used to map the descriptor onto device. | |
1003 | * @dma_offset: Descriptor's offset in the memory block. HW allocates | |
1004 | * descriptors in memory blocks (see struct vxge_hw_fifo_config{}) | |
1005 | * Each memblock is a contiguous block of DMA-able memory. | |
1006 | * @frags: Total number of fragments (that is, contiguous data buffers) | |
1007 | * carried by this TxDL. | |
1008 | * @align_vaddr_start: Aligned virtual address start | |
1009 | * @align_vaddr: Virtual address of the per-TxDL area in memory used for | |
1010 | * alignement. Used to place one or more mis-aligned fragments | |
1011 | * @align_dma_addr: DMA address translated from the @align_vaddr. | |
1012 | * @align_dma_handle: DMA handle that corresponds to @align_dma_addr. | |
1013 | * @align_dma_acch: DMA access handle corresponds to @align_dma_addr. | |
1014 | * @align_dma_offset: The current offset into the @align_vaddr area. | |
1015 | * Grows while filling the descriptor, gets reset. | |
1016 | * @align_used_frags: Number of fragments used. | |
1017 | * @alloc_frags: Total number of fragments allocated. | |
1018 | * @unused: TODO | |
1019 | * @next_txdl_priv: (TODO). | |
1020 | * @first_txdp: (TODO). | |
1021 | * @linked_txdl_priv: Pointer to any linked TxDL for creating contiguous | |
1022 | * TxDL list. | |
1023 | * @txdlh: Corresponding txdlh to this TxDL. | |
1024 | * @memblock: Pointer to the TxDL memory block or memory page. | |
1025 | * on the next send operation. | |
1026 | * @dma_object: DMA address and handle of the memory block that contains | |
1027 | * the descriptor. This member is used only in the "checked" | |
1028 | * version of the HW (to enforce certain assertions); | |
1029 | * otherwise it gets compiled out. | |
1030 | * @allocated: True if the descriptor is reserved, 0 otherwise. Internal usage. | |
1031 | * | |
1032 | * Per-transmit decsriptor HW-private data. HW uses the space to keep DMA | |
1033 | * information associated with the descriptor. Note that driver can ask HW | |
1034 | * to allocate additional per-descriptor space for its own (driver-specific) | |
1035 | * purposes. | |
1036 | * | |
1037 | * See also: struct vxge_hw_ring_rxd_priv{}. | |
1038 | */ | |
1039 | struct __vxge_hw_fifo_txdl_priv { | |
1040 | dma_addr_t dma_addr; | |
1041 | struct pci_dev *dma_handle; | |
1042 | ptrdiff_t dma_offset; | |
1043 | u32 frags; | |
1044 | u8 *align_vaddr_start; | |
1045 | u8 *align_vaddr; | |
1046 | dma_addr_t align_dma_addr; | |
1047 | struct pci_dev *align_dma_handle; | |
1048 | struct pci_dev *align_dma_acch; | |
1049 | ptrdiff_t align_dma_offset; | |
1050 | u32 align_used_frags; | |
1051 | u32 alloc_frags; | |
1052 | u32 unused; | |
1053 | struct __vxge_hw_fifo_txdl_priv *next_txdl_priv; | |
1054 | struct vxge_hw_fifo_txd *first_txdp; | |
1055 | void *memblock; | |
1056 | }; | |
1057 | ||
1058 | /* | |
1059 | * struct __vxge_hw_non_offload_db_wrapper - Non-offload Doorbell Wrapper | |
1060 | * @control_0: Bits 0 to 7 - Doorbell type. | |
1061 | * Bits 8 to 31 - Reserved. | |
1062 | * Bits 32 to 39 - The highest TxD in this TxDL. | |
1063 | * Bits 40 to 47 - Reserved. | |
1064 | * Bits 48 to 55 - Reserved. | |
1065 | * Bits 56 to 63 - No snoop flags. | |
1066 | * @txdl_ptr: The starting location of the TxDL in host memory. | |
1067 | * | |
1068 | * Created by the host and written to the adapter via PIO to a Kernel Doorbell | |
1069 | * FIFO. All non-offload doorbell wrapper fields must be written by the host as | |
1070 | * part of a doorbell write. Consumed by the adapter but is not written by the | |
1071 | * adapter. | |
1072 | */ | |
1073 | struct __vxge_hw_non_offload_db_wrapper { | |
1074 | u64 control_0; | |
1075 | #define VXGE_HW_NODBW_GET_TYPE(ctrl0) vxge_bVALn(ctrl0, 0, 8) | |
1076 | #define VXGE_HW_NODBW_TYPE(val) vxge_vBIT(val, 0, 8) | |
1077 | #define VXGE_HW_NODBW_TYPE_NODBW 0 | |
1078 | ||
1079 | #define VXGE_HW_NODBW_GET_LAST_TXD_NUMBER(ctrl0) vxge_bVALn(ctrl0, 32, 8) | |
1080 | #define VXGE_HW_NODBW_LAST_TXD_NUMBER(val) vxge_vBIT(val, 32, 8) | |
1081 | ||
1082 | #define VXGE_HW_NODBW_GET_NO_SNOOP(ctrl0) vxge_bVALn(ctrl0, 56, 8) | |
1083 | #define VXGE_HW_NODBW_LIST_NO_SNOOP(val) vxge_vBIT(val, 56, 8) | |
1084 | #define VXGE_HW_NODBW_LIST_NO_SNOOP_TXD_READ_TXD0_WRITE 0x2 | |
1085 | #define VXGE_HW_NODBW_LIST_NO_SNOOP_TX_FRAME_DATA_READ 0x1 | |
1086 | ||
1087 | u64 txdl_ptr; | |
1088 | }; | |
1089 | ||
1090 | /* | |
1091 | * TX Descriptor | |
1092 | */ | |
1093 | ||
1094 | /** | |
1095 | * struct vxge_hw_fifo_txd - Transmit Descriptor | |
1096 | * @control_0: Bits 0 to 6 - Reserved. | |
1097 | * Bit 7 - List Ownership. This field should be initialized | |
1098 | * to '1' by the driver before the transmit list pointer is | |
1099 | * written to the adapter. This field will be set to '0' by the | |
1100 | * adapter once it has completed transmitting the frame or frames in | |
1101 | * the list. Note - This field is only valid in TxD0. Additionally, | |
1102 | * for multi-list sequences, the driver should not release any | |
1103 | * buffers until the ownership of the last list in the multi-list | |
1104 | * sequence has been returned to the host. | |
1105 | * Bits 8 to 11 - Reserved | |
1106 | * Bits 12 to 15 - Transfer_Code. This field is only valid in | |
1107 | * TxD0. It is used to describe the status of the transmit data | |
1108 | * buffer transfer. This field is always overwritten by the | |
1109 | * adapter, so this field may be initialized to any value. | |
1110 | * Bits 16 to 17 - Host steering. This field allows the host to | |
1111 | * override the selection of the physical transmit port. | |
1112 | * Attention: | |
1113 | * Normal sounds as if learned from the switch rather than from | |
1114 | * the aggregation algorythms. | |
1115 | * 00: Normal. Use Destination/MAC Address | |
1116 | * lookup to determine the transmit port. | |
1117 | * 01: Send on physical Port1. | |
1118 | * 10: Send on physical Port0. | |
1119 | * 11: Send on both ports. | |
1120 | * Bits 18 to 21 - Reserved | |
1121 | * Bits 22 to 23 - Gather_Code. This field is set by the host and | |
1122 | * is used to describe how individual buffers comprise a frame. | |
1123 | * 10: First descriptor of a frame. | |
1124 | * 00: Middle of a multi-descriptor frame. | |
1125 | * 01: Last descriptor of a frame. | |
1126 | * 11: First and last descriptor of a frame (the entire frame | |
1127 | * resides in a single buffer). | |
1128 | * For multi-descriptor frames, the only valid gather code sequence | |
1129 | * is {10, [00], 01}. In other words, the descriptors must be placed | |
1130 | * in the list in the correct order. | |
1131 | * Bits 24 to 27 - Reserved | |
1132 | * Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation | |
1133 | * definition. Only valid in TxD0. This field allows the host to | |
1134 | * indicate the Ethernet encapsulation of an outbound LSO packet. | |
1135 | * 00 - classic mode (best guess) | |
1136 | * 01 - LLC | |
1137 | * 10 - SNAP | |
1138 | * 11 - DIX | |
1139 | * If "classic mode" is selected, the adapter will attempt to | |
1140 | * decode the frame's Ethernet encapsulation by examining the L/T | |
1141 | * field as follows: | |
1142 | * <= 0x05DC LLC/SNAP encoding; must examine DSAP/SSAP to determine | |
1143 | * if packet is IPv4 or IPv6. | |
1144 | * 0x8870 Jumbo-SNAP encoding. | |
1145 | * 0x0800 IPv4 DIX encoding | |
1146 | * 0x86DD IPv6 DIX encoding | |
1147 | * others illegal encapsulation | |
1148 | * Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag. | |
1149 | * Set to 1 to perform segmentation offload for TCP/UDP. | |
1150 | * This field is valid only in TxD0. | |
1151 | * Bits 31 to 33 - Reserved. | |
1152 | * Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size | |
1153 | * This field is meaningful only when LSO_Control is non-zero. | |
1154 | * When LSO_Control is set to TCP_LSO, the single (possibly large) | |
1155 | * TCP segment described by this TxDL will be sent as a series of | |
1156 | * TCP segments each of which contains no more than LSO_MSS | |
1157 | * payload bytes. | |
1158 | * When LSO_Control is set to UDP_LSO, the single (possibly large) | |
1159 | * UDP datagram described by this TxDL will be sent as a series of | |
1160 | * UDP datagrams each of which contains no more than LSO_MSS | |
1161 | * payload bytes. | |
1162 | * All outgoing frames from this TxDL will have LSO_MSS bytes of UDP | |
1163 | * or TCP payload, with the exception of the last, which will have | |
1164 | * <= LSO_MSS bytes of payload. | |
1165 | * Bits 48 to 63 - Buffer_Size. Number of valid bytes in the | |
1166 | * buffer to be read by the adapter. This field is written by the | |
1167 | * host. A value of 0 is illegal. | |
1168 | * Bits 32 to 63 - This value is written by the adapter upon | |
1169 | * completion of a UDP or TCP LSO operation and indicates the number | |
1170 | * of UDP or TCP payload bytes that were transmitted. 0x0000 will be | |
1171 | * returned for any non-LSO operation. | |
1172 | * @control_1: Bits 0 to 4 - Reserved. | |
1173 | * Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum | |
1174 | * offload. This field is only valid in the first TxD of a frame. | |
1175 | * Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload. | |
1176 | * This field is only valid in the first TxD of a frame (the TxD's | |
1177 | * gather code must be 10 or 11). The driver should only set this | |
1178 | * bit if it can guarantee that TCP is present. | |
1179 | * Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload. | |
1180 | * This field is only valid in the first TxD of a frame (the TxD's | |
1181 | * gather code must be 10 or 11). The driver should only set this | |
1182 | * bit if it can guarantee that UDP is present. | |
1183 | * Bits 8 to 14 - Reserved. | |
1184 | * Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to | |
1185 | * instruct the adapter to insert the VLAN tag specified by the | |
1186 | * Tx_VLAN_Tag field. This field is only valid in the first TxD of | |
1187 | * a frame. | |
1188 | * Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag | |
1189 | * to be inserted into the frame by the adapter (the first two bytes | |
1190 | * of a VLAN tag are always 0x8100). This field is only valid if the | |
1191 | * Tx_VLAN_Enable field is set to '1'. | |
1192 | * Bits 32 to 33 - Reserved. | |
1193 | * Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt | |
1194 | * number the frame associated with. This field is written by the | |
1195 | * host. It is only valid in the first TxD of a frame. | |
1196 | * Bits 40 to 42 - Reserved. | |
1197 | * Bit 43 - Set to 1 to exclude the frame from bandwidth metering | |
1198 | * functions. This field is valid only in the first TxD | |
1199 | * of a frame. | |
1200 | * Bits 44 to 45 - Reserved. | |
1201 | * Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to | |
1202 | * generate an interrupt as soon as all of the frames in the list | |
1203 | * have been transmitted. In order to have per-frame interrupts, | |
1204 | * the driver should place a maximum of one frame per list. This | |
1205 | * field is only valid in the first TxD of a frame. | |
1206 | * Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter | |
1207 | * to count the frame toward the utilization interrupt specified in | |
1208 | * the Tx_Int_Number field. This field is only valid in the first | |
1209 | * TxD of a frame. | |
1210 | * Bits 48 to 63 - Reserved. | |
1211 | * @buffer_pointer: Buffer start address. | |
1212 | * @host_control: Host_Control.Opaque 64bit data stored by driver inside the | |
1213 | * Titan descriptor prior to posting the latter on the fifo | |
1214 | * via vxge_hw_fifo_txdl_post().The %host_control is returned as is | |
1215 | * to the driver with each completed descriptor. | |
1216 | * | |
1217 | * Transmit descriptor (TxD).Fifo descriptor contains configured number | |
1218 | * (list) of TxDs. * For more details please refer to Titan User Guide, | |
1219 | * Section 5.4.2 "Transmit Descriptor (TxD) Format". | |
1220 | */ | |
1221 | struct vxge_hw_fifo_txd { | |
1222 | u64 control_0; | |
1223 | #define VXGE_HW_FIFO_TXD_LIST_OWN_ADAPTER vxge_mBIT(7) | |
1224 | ||
1225 | #define VXGE_HW_FIFO_TXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) | |
1226 | #define VXGE_HW_FIFO_TXD_T_CODE(val) vxge_vBIT(val, 12, 4) | |
1227 | #define VXGE_HW_FIFO_TXD_T_CODE_UNUSED VXGE_HW_FIFO_T_CODE_UNUSED | |
1228 | ||
1229 | ||
1230 | #define VXGE_HW_FIFO_TXD_GATHER_CODE(val) vxge_vBIT(val, 22, 2) | |
1231 | #define VXGE_HW_FIFO_TXD_GATHER_CODE_FIRST VXGE_HW_FIFO_GATHER_CODE_FIRST | |
1232 | #define VXGE_HW_FIFO_TXD_GATHER_CODE_LAST VXGE_HW_FIFO_GATHER_CODE_LAST | |
1233 | ||
1234 | ||
1235 | #define VXGE_HW_FIFO_TXD_LSO_EN vxge_mBIT(30) | |
1236 | ||
1237 | #define VXGE_HW_FIFO_TXD_LSO_MSS(val) vxge_vBIT(val, 34, 14) | |
1238 | ||
1239 | #define VXGE_HW_FIFO_TXD_BUFFER_SIZE(val) vxge_vBIT(val, 48, 16) | |
1240 | ||
1241 | u64 control_1; | |
1242 | #define VXGE_HW_FIFO_TXD_TX_CKO_IPV4_EN vxge_mBIT(5) | |
1243 | #define VXGE_HW_FIFO_TXD_TX_CKO_TCP_EN vxge_mBIT(6) | |
1244 | #define VXGE_HW_FIFO_TXD_TX_CKO_UDP_EN vxge_mBIT(7) | |
1245 | #define VXGE_HW_FIFO_TXD_VLAN_ENABLE vxge_mBIT(15) | |
1246 | ||
1247 | #define VXGE_HW_FIFO_TXD_VLAN_TAG(val) vxge_vBIT(val, 16, 16) | |
1248 | ||
1249 | #define VXGE_HW_FIFO_TXD_INT_NUMBER(val) vxge_vBIT(val, 34, 6) | |
1250 | ||
1251 | #define VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST vxge_mBIT(46) | |
1252 | #define VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ vxge_mBIT(47) | |
1253 | ||
1254 | u64 buffer_pointer; | |
1255 | ||
1256 | u64 host_control; | |
1257 | }; | |
1258 | ||
1259 | /** | |
1260 | * struct vxge_hw_ring_rxd_1 - One buffer mode RxD for ring | |
1261 | * @host_control: This field is exclusively for host use and is "readonly" | |
1262 | * from the adapter's perspective. | |
1263 | * @control_0:Bits 0 to 6 - RTH_Bucket get | |
1264 | * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 | |
1265 | * by the host, and is set to 0 by the adapter. | |
1266 | * 0 - Host owns RxD and buffer. | |
1267 | * 1 - The adapter owns RxD and buffer. | |
1268 | * Bit 8 - Fast_Path_Eligible When set, indicates that the | |
1269 | * received frame meets all of the criteria for fast path processing. | |
1270 | * The required criteria are as follows: | |
1271 | * !SYN & | |
1272 | * (Transfer_Code == "Transfer OK") & | |
1273 | * (!Is_IP_Fragment) & | |
1274 | * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | | |
1275 | * (Is_IPv6)) & | |
1276 | * ((Is_TCP & computed_L4_checksum == 0xFFFF) | | |
1277 | * (Is_UDP & (computed_L4_checksum == 0xFFFF | | |
1278 | * computed _L4_checksum == 0x0000))) | |
1279 | * (same meaning for all RxD buffer modes) | |
1280 | * Bit 9 - L3 Checksum Correct | |
1281 | * Bit 10 - L4 Checksum Correct | |
1282 | * Bit 11 - Reserved | |
1283 | * Bit 12 to 15 - This field is written by the adapter. It is | |
1284 | * used to report the status of the frame transfer to the host. | |
1285 | * 0x0 - Transfer OK | |
1286 | * 0x4 - RDA Failure During Transfer | |
1287 | * 0x5 - Unparseable Packet, such as unknown IPv6 header. | |
1288 | * 0x6 - Frame integrity error (FCS or ECC). | |
1289 | * 0x7 - Buffer Size Error. The provided buffer(s) were not | |
1290 | * appropriately sized and data loss occurred. | |
1291 | * 0x8 - Internal ECC Error. RxD corrupted. | |
1292 | * 0x9 - IPv4 Checksum error | |
1293 | * 0xA - TCP/UDP Checksum error | |
1294 | * 0xF - Unknown Error or Multiple Error. Indicates an | |
1295 | * unknown problem or that more than one of transfer codes is set. | |
1296 | * Bit 16 - SYN The adapter sets this field to indicate that | |
1297 | * the incoming frame contained a TCP segment with its SYN bit | |
1298 | * set and its ACK bit NOT set. (same meaning for all RxD buffer | |
1299 | * modes) | |
1300 | * Bit 17 - Is ICMP | |
1301 | * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the | |
1302 | * Socket Pair Direct Match Table and the frame was steered based | |
1303 | * on SPDM. | |
1304 | * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the | |
1305 | * Indirection Table and the frame was steered based on hash | |
1306 | * indirection. | |
1307 | * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash | |
1308 | * type) that was used to calculate the hash. | |
1309 | * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN | |
1310 | * tagged. | |
1311 | * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation | |
1312 | * of the received frame. | |
1313 | * 0x0 - Ethernet DIX | |
1314 | * 0x1 - LLC | |
1315 | * 0x2 - SNAP (includes Jumbo-SNAP) | |
1316 | * 0x3 - IPX | |
1317 | * Bit 27 - IS_IPV4 Set to '1' if the frame contains an IPv4 packet. | |
1318 | * Bit 28 - IS_IPV6 Set to '1' if the frame contains an IPv6 packet. | |
1319 | * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a fragmented | |
1320 | * IP packet. | |
1321 | * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. | |
1322 | * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. | |
1323 | * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that | |
1324 | * arrived with the frame. If the resulting computed IPv4 header | |
1325 | * checksum for the frame did not produce the expected 0xFFFF value, | |
1326 | * then the transfer code would be set to 0x9. | |
1327 | * Bit 48 to 63 - L4_Checksum[0:15] The TCP/UDP checksum value that | |
1328 | * arrived with the frame. If the resulting computed TCP/UDP checksum | |
1329 | * for the frame did not produce the expected 0xFFFF value, then the | |
1330 | * transfer code would be set to 0xA. | |
1331 | * @control_1:Bits 0 to 1 - Reserved | |
1332 | * Bits 2 to 15 - Buffer0_Size.This field is set by the host and | |
1333 | * eventually overwritten by the adapter. The host writes the | |
1334 | * available buffer size in bytes when it passes the descriptor to | |
1335 | * the adapter. When a frame is delivered the host, the adapter | |
1336 | * populates this field with the number of bytes written into the | |
1337 | * buffer. The largest supported buffer is 16, 383 bytes. | |
1338 | * Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid if | |
1339 | * RTH_HASH_TYPE (Control_0, bits 20:23) is nonzero. | |
1340 | * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable portion | |
1341 | * of the VLAN tag, if one was detected by the adapter. This field is | |
1342 | * populated even if VLAN-tag stripping is enabled. | |
1343 | * @buffer0_ptr: Pointer to buffer. This field is populated by the driver. | |
1344 | * | |
1345 | * One buffer mode RxD for ring structure | |
1346 | */ | |
1347 | struct vxge_hw_ring_rxd_1 { | |
1348 | u64 host_control; | |
1349 | u64 control_0; | |
1350 | #define VXGE_HW_RING_RXD_RTH_BUCKET_GET(ctrl0) vxge_bVALn(ctrl0, 0, 7) | |
1351 | ||
1352 | #define VXGE_HW_RING_RXD_LIST_OWN_ADAPTER vxge_mBIT(7) | |
1353 | ||
1354 | #define VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) vxge_bVALn(ctrl0, 8, 1) | |
1355 | ||
1356 | #define VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 9, 1) | |
1357 | ||
1358 | #define VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) vxge_bVALn(ctrl0, 10, 1) | |
1359 | ||
1360 | #define VXGE_HW_RING_RXD_T_CODE_GET(ctrl0) vxge_bVALn(ctrl0, 12, 4) | |
1361 | #define VXGE_HW_RING_RXD_T_CODE(val) vxge_vBIT(val, 12, 4) | |
1362 | ||
1363 | #define VXGE_HW_RING_RXD_T_CODE_UNUSED VXGE_HW_RING_T_CODE_UNUSED | |
1364 | ||
1365 | #define VXGE_HW_RING_RXD_SYN_GET(ctrl0) vxge_bVALn(ctrl0, 16, 1) | |
1366 | ||
1367 | #define VXGE_HW_RING_RXD_IS_ICMP_GET(ctrl0) vxge_bVALn(ctrl0, 17, 1) | |
1368 | ||
1369 | #define VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 18, 1) | |
1370 | ||
1371 | #define VXGE_HW_RING_RXD_RTH_IT_HIT_GET(ctrl0) vxge_bVALn(ctrl0, 19, 1) | |
1372 | ||
1373 | #define VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) vxge_bVALn(ctrl0, 20, 4) | |
1374 | ||
1375 | #define VXGE_HW_RING_RXD_IS_VLAN_GET(ctrl0) vxge_bVALn(ctrl0, 24, 1) | |
1376 | ||
1377 | #define VXGE_HW_RING_RXD_ETHER_ENCAP_GET(ctrl0) vxge_bVALn(ctrl0, 25, 2) | |
1378 | ||
1379 | #define VXGE_HW_RING_RXD_FRAME_PROTO_GET(ctrl0) vxge_bVALn(ctrl0, 27, 5) | |
1380 | ||
1381 | #define VXGE_HW_RING_RXD_L3_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 32, 16) | |
1382 | ||
1383 | #define VXGE_HW_RING_RXD_L4_CKSUM_GET(ctrl0) vxge_bVALn(ctrl0, 48, 16) | |
1384 | ||
1385 | u64 control_1; | |
1386 | ||
1387 | #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) vxge_bVALn(ctrl1, 2, 14) | |
1388 | #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE(val) vxge_vBIT(val, 2, 14) | |
1389 | #define VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK vxge_vBIT(0x3FFF, 2, 14) | |
1390 | ||
1391 | #define VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) vxge_bVALn(ctrl1, 16, 32) | |
1392 | ||
1393 | #define VXGE_HW_RING_RXD_VLAN_TAG_GET(ctrl1) vxge_bVALn(ctrl1, 48, 16) | |
1394 | ||
1395 | u64 buffer0_ptr; | |
1396 | }; | |
1397 | ||
1398 | enum vxge_hw_rth_algoritms { | |
1399 | RTH_ALG_JENKINS = 0, | |
1400 | RTH_ALG_MS_RSS = 1, | |
1401 | RTH_ALG_CRC32C = 2 | |
1402 | }; | |
1403 | ||
1404 | /** | |
1405 | * struct vxge_hw_rth_hash_types - RTH hash types. | |
1406 | * @hash_type_tcpipv4_en: Enables RTH field type HashTypeTcpIPv4 | |
1407 | * @hash_type_ipv4_en: Enables RTH field type HashTypeIPv4 | |
1408 | * @hash_type_tcpipv6_en: Enables RTH field type HashTypeTcpIPv6 | |
1409 | * @hash_type_ipv6_en: Enables RTH field type HashTypeIPv6 | |
1410 | * @hash_type_tcpipv6ex_en: Enables RTH field type HashTypeTcpIPv6Ex | |
1411 | * @hash_type_ipv6ex_en: Enables RTH field type HashTypeIPv6Ex | |
1412 | * | |
1413 | * Used to pass RTH hash types to rts_rts_set. | |
1414 | * | |
1415 | * See also: vxge_hw_vpath_rts_rth_set(), vxge_hw_vpath_rts_rth_get(). | |
1416 | */ | |
1417 | struct vxge_hw_rth_hash_types { | |
1418 | u8 hash_type_tcpipv4_en; | |
1419 | u8 hash_type_ipv4_en; | |
1420 | u8 hash_type_tcpipv6_en; | |
1421 | u8 hash_type_ipv6_en; | |
1422 | u8 hash_type_tcpipv6ex_en; | |
1423 | u8 hash_type_ipv6ex_en; | |
1424 | }; | |
1425 | ||
1426 | u32 | |
1427 | vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh); | |
1428 | ||
1429 | void vxge_hw_device_debug_set( | |
1430 | struct __vxge_hw_device *devh, | |
1431 | enum vxge_debug_level level, | |
1432 | u32 mask); | |
1433 | ||
1434 | u32 | |
1435 | vxge_hw_device_error_level_get(struct __vxge_hw_device *devh); | |
1436 | ||
1437 | u32 | |
1438 | vxge_hw_device_trace_level_get(struct __vxge_hw_device *devh); | |
1439 | ||
1440 | u32 | |
1441 | vxge_hw_device_debug_mask_get(struct __vxge_hw_device *devh); | |
1442 | ||
1443 | /** | |
1444 | * vxge_hw_ring_rxd_size_get - Get the size of ring descriptor. | |
1445 | * @buf_mode: Buffer mode (1, 3 or 5) | |
1446 | * | |
1447 | * This function returns the size of RxD for given buffer mode | |
1448 | */ | |
1449 | static inline u32 vxge_hw_ring_rxd_size_get(u32 buf_mode) | |
1450 | { | |
1451 | return sizeof(struct vxge_hw_ring_rxd_1); | |
1452 | } | |
1453 | ||
1454 | /** | |
1455 | * vxge_hw_ring_rxds_per_block_get - Get the number of rxds per block. | |
1456 | * @buf_mode: Buffer mode (1 buffer mode only) | |
1457 | * | |
1458 | * This function returns the number of RxD for RxD block for given buffer mode | |
1459 | */ | |
1460 | static inline u32 vxge_hw_ring_rxds_per_block_get(u32 buf_mode) | |
1461 | { | |
1462 | return (u32)((VXGE_HW_BLOCK_SIZE-16) / | |
1463 | sizeof(struct vxge_hw_ring_rxd_1)); | |
1464 | } | |
1465 | ||
1466 | /** | |
1467 | * vxge_hw_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor. | |
1468 | * @rxdh: Descriptor handle. | |
1469 | * @dma_pointer: DMA address of a single receive buffer this descriptor | |
1470 | * should carry. Note that by the time vxge_hw_ring_rxd_1b_set is called, | |
1471 | * the receive buffer should be already mapped to the device | |
1472 | * @size: Size of the receive @dma_pointer buffer. | |
1473 | * | |
1474 | * Prepare 1-buffer-mode Rx descriptor for posting | |
1475 | * (via vxge_hw_ring_rxd_post()). | |
1476 | * | |
1477 | * This inline helper-function does not return any parameters and always | |
1478 | * succeeds. | |
1479 | * | |
1480 | */ | |
1481 | static inline | |
1482 | void vxge_hw_ring_rxd_1b_set( | |
1483 | void *rxdh, | |
1484 | dma_addr_t dma_pointer, | |
1485 | u32 size) | |
1486 | { | |
1487 | struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; | |
1488 | rxdp->buffer0_ptr = dma_pointer; | |
1489 | rxdp->control_1 &= ~VXGE_HW_RING_RXD_1_BUFFER0_SIZE_MASK; | |
1490 | rxdp->control_1 |= VXGE_HW_RING_RXD_1_BUFFER0_SIZE(size); | |
1491 | } | |
1492 | ||
1493 | /** | |
1494 | * vxge_hw_ring_rxd_1b_get - Get data from the completed 1-buf | |
1495 | * descriptor. | |
1496 | * @vpath_handle: Virtual Path handle. | |
1497 | * @rxdh: Descriptor handle. | |
1498 | * @dma_pointer: DMA address of a single receive buffer this descriptor | |
1499 | * carries. Returned by HW. | |
1500 | * @pkt_length: Length (in bytes) of the data in the buffer pointed by | |
1501 | * | |
1502 | * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor. | |
1503 | * This inline helper-function uses completed descriptor to populate receive | |
1504 | * buffer pointer and other "out" parameters. The function always succeeds. | |
1505 | * | |
1506 | */ | |
1507 | static inline | |
1508 | void vxge_hw_ring_rxd_1b_get( | |
1509 | struct __vxge_hw_ring *ring_handle, | |
1510 | void *rxdh, | |
1511 | u32 *pkt_length) | |
1512 | { | |
1513 | struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; | |
1514 | ||
1515 | *pkt_length = | |
1516 | (u32)VXGE_HW_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1); | |
1517 | } | |
1518 | ||
1519 | /** | |
1520 | * vxge_hw_ring_rxd_1b_info_get - Get extended information associated with | |
1521 | * a completed receive descriptor for 1b mode. | |
1522 | * @vpath_handle: Virtual Path handle. | |
1523 | * @rxdh: Descriptor handle. | |
1524 | * @rxd_info: Descriptor information | |
1525 | * | |
1526 | * Retrieve extended information associated with a completed receive descriptor. | |
1527 | * | |
1528 | */ | |
1529 | static inline | |
1530 | void vxge_hw_ring_rxd_1b_info_get( | |
1531 | struct __vxge_hw_ring *ring_handle, | |
1532 | void *rxdh, | |
1533 | struct vxge_hw_ring_rxd_info *rxd_info) | |
1534 | { | |
1535 | ||
1536 | struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; | |
1537 | rxd_info->syn_flag = | |
1538 | (u32)VXGE_HW_RING_RXD_SYN_GET(rxdp->control_0); | |
1539 | rxd_info->is_icmp = | |
1540 | (u32)VXGE_HW_RING_RXD_IS_ICMP_GET(rxdp->control_0); | |
1541 | rxd_info->fast_path_eligible = | |
1542 | (u32)VXGE_HW_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0); | |
1543 | rxd_info->l3_cksum_valid = | |
1544 | (u32)VXGE_HW_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0); | |
1545 | rxd_info->l3_cksum = | |
1546 | (u32)VXGE_HW_RING_RXD_L3_CKSUM_GET(rxdp->control_0); | |
1547 | rxd_info->l4_cksum_valid = | |
1548 | (u32)VXGE_HW_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0); | |
1549 | rxd_info->l4_cksum = | |
1550 | (u32)VXGE_HW_RING_RXD_L4_CKSUM_GET(rxdp->control_0);; | |
1551 | rxd_info->frame = | |
1552 | (u32)VXGE_HW_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0); | |
1553 | rxd_info->proto = | |
1554 | (u32)VXGE_HW_RING_RXD_FRAME_PROTO_GET(rxdp->control_0); | |
1555 | rxd_info->is_vlan = | |
1556 | (u32)VXGE_HW_RING_RXD_IS_VLAN_GET(rxdp->control_0); | |
1557 | rxd_info->vlan = | |
1558 | (u32)VXGE_HW_RING_RXD_VLAN_TAG_GET(rxdp->control_1); | |
1559 | rxd_info->rth_bucket = | |
1560 | (u32)VXGE_HW_RING_RXD_RTH_BUCKET_GET(rxdp->control_0); | |
1561 | rxd_info->rth_it_hit = | |
1562 | (u32)VXGE_HW_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0); | |
1563 | rxd_info->rth_spdm_hit = | |
1564 | (u32)VXGE_HW_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0); | |
1565 | rxd_info->rth_hash_type = | |
1566 | (u32)VXGE_HW_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0); | |
1567 | rxd_info->rth_value = | |
1568 | (u32)VXGE_HW_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1); | |
1569 | } | |
1570 | ||
1571 | /** | |
1572 | * vxge_hw_ring_rxd_private_get - Get driver private per-descriptor data | |
1573 | * of 1b mode 3b mode ring. | |
1574 | * @rxdh: Descriptor handle. | |
1575 | * | |
1576 | * Returns: private driver info associated with the descriptor. | |
1577 | * driver requests per-descriptor space via vxge_hw_ring_attr. | |
1578 | * | |
1579 | */ | |
1580 | static inline void *vxge_hw_ring_rxd_private_get(void *rxdh) | |
1581 | { | |
1582 | struct vxge_hw_ring_rxd_1 *rxdp = (struct vxge_hw_ring_rxd_1 *)rxdh; | |
1583 | return (void *)(size_t)rxdp->host_control; | |
1584 | } | |
1585 | ||
1586 | /** | |
1587 | * vxge_hw_fifo_txdl_cksum_set_bits - Offload checksum. | |
1588 | * @txdlh: Descriptor handle. | |
1589 | * @cksum_bits: Specifies which checksums are to be offloaded: IPv4, | |
1590 | * and/or TCP and/or UDP. | |
1591 | * | |
1592 | * Ask Titan to calculate IPv4 & transport checksums for _this_ transmit | |
1593 | * descriptor. | |
1594 | * This API is part of the preparation of the transmit descriptor for posting | |
1595 | * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include | |
1596 | * vxge_hw_fifo_txdl_mss_set(), vxge_hw_fifo_txdl_buffer_set_aligned(), | |
1597 | * and vxge_hw_fifo_txdl_buffer_set(). | |
1598 | * All these APIs fill in the fields of the fifo descriptor, | |
1599 | * in accordance with the Titan specification. | |
1600 | * | |
1601 | */ | |
1602 | static inline void vxge_hw_fifo_txdl_cksum_set_bits(void *txdlh, u64 cksum_bits) | |
1603 | { | |
1604 | struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; | |
1605 | txdp->control_1 |= cksum_bits; | |
1606 | } | |
1607 | ||
1608 | /** | |
1609 | * vxge_hw_fifo_txdl_mss_set - Set MSS. | |
1610 | * @txdlh: Descriptor handle. | |
1611 | * @mss: MSS size for _this_ TCP connection. Passed by TCP stack down to the | |
1612 | * driver, which in turn inserts the MSS into the @txdlh. | |
1613 | * | |
1614 | * This API is part of the preparation of the transmit descriptor for posting | |
1615 | * (via vxge_hw_fifo_txdl_post()). The related "preparation" APIs include | |
1616 | * vxge_hw_fifo_txdl_buffer_set(), vxge_hw_fifo_txdl_buffer_set_aligned(), | |
1617 | * and vxge_hw_fifo_txdl_cksum_set_bits(). | |
1618 | * All these APIs fill in the fields of the fifo descriptor, | |
1619 | * in accordance with the Titan specification. | |
1620 | * | |
1621 | */ | |
1622 | static inline void vxge_hw_fifo_txdl_mss_set(void *txdlh, int mss) | |
1623 | { | |
1624 | struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; | |
1625 | ||
1626 | txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_EN; | |
1627 | txdp->control_0 |= VXGE_HW_FIFO_TXD_LSO_MSS(mss); | |
1628 | } | |
1629 | ||
1630 | /** | |
1631 | * vxge_hw_fifo_txdl_vlan_set - Set VLAN tag. | |
1632 | * @txdlh: Descriptor handle. | |
1633 | * @vlan_tag: 16bit VLAN tag. | |
1634 | * | |
1635 | * Insert VLAN tag into specified transmit descriptor. | |
1636 | * The actual insertion of the tag into outgoing frame is done by the hardware. | |
1637 | */ | |
1638 | static inline void vxge_hw_fifo_txdl_vlan_set(void *txdlh, u16 vlan_tag) | |
1639 | { | |
1640 | struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; | |
1641 | ||
1642 | txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_ENABLE; | |
1643 | txdp->control_1 |= VXGE_HW_FIFO_TXD_VLAN_TAG(vlan_tag); | |
1644 | } | |
1645 | ||
1646 | /** | |
1647 | * vxge_hw_fifo_txdl_private_get - Retrieve per-descriptor private data. | |
1648 | * @txdlh: Descriptor handle. | |
1649 | * | |
1650 | * Retrieve per-descriptor private data. | |
1651 | * Note that driver requests per-descriptor space via | |
1652 | * struct vxge_hw_fifo_attr passed to | |
1653 | * vxge_hw_vpath_open(). | |
1654 | * | |
1655 | * Returns: private driver data associated with the descriptor. | |
1656 | */ | |
1657 | static inline void *vxge_hw_fifo_txdl_private_get(void *txdlh) | |
1658 | { | |
1659 | struct vxge_hw_fifo_txd *txdp = (struct vxge_hw_fifo_txd *)txdlh; | |
1660 | ||
1661 | return (void *)(size_t)txdp->host_control; | |
1662 | } | |
1663 | ||
1664 | /** | |
1665 | * struct vxge_hw_ring_attr - Ring open "template". | |
1666 | * @callback: Ring completion callback. HW invokes the callback when there | |
1667 | * are new completions on that ring. In many implementations | |
1668 | * the @callback executes in the hw interrupt context. | |
1669 | * @rxd_init: Ring's descriptor-initialize callback. | |
1670 | * See vxge_hw_ring_rxd_init_f{}. | |
1671 | * If not NULL, HW invokes the callback when opening | |
1672 | * the ring. | |
1673 | * @rxd_term: Ring's descriptor-terminate callback. If not NULL, | |
1674 | * HW invokes the callback when closing the corresponding ring. | |
1675 | * See also vxge_hw_ring_rxd_term_f{}. | |
1676 | * @userdata: User-defined "context" of _that_ ring. Passed back to the | |
1677 | * user as one of the @callback, @rxd_init, and @rxd_term arguments. | |
1678 | * @per_rxd_space: If specified (i.e., greater than zero): extra space | |
1679 | * reserved by HW per each receive descriptor. | |
1680 | * Can be used to store | |
1681 | * and retrieve on completion, information specific | |
1682 | * to the driver. | |
1683 | * | |
1684 | * Ring open "template". User fills the structure with ring | |
1685 | * attributes and passes it to vxge_hw_vpath_open(). | |
1686 | */ | |
1687 | struct vxge_hw_ring_attr { | |
1688 | enum vxge_hw_status (*callback)( | |
1689 | struct __vxge_hw_ring *ringh, | |
1690 | void *rxdh, | |
1691 | u8 t_code, | |
1692 | void *userdata); | |
1693 | ||
1694 | enum vxge_hw_status (*rxd_init)( | |
1695 | void *rxdh, | |
1696 | void *userdata); | |
1697 | ||
1698 | void (*rxd_term)( | |
1699 | void *rxdh, | |
1700 | enum vxge_hw_rxd_state state, | |
1701 | void *userdata); | |
1702 | ||
1703 | void *userdata; | |
1704 | u32 per_rxd_space; | |
1705 | }; | |
1706 | ||
1707 | /** | |
1708 | * function vxge_hw_fifo_callback_f - FIFO callback. | |
1709 | * @vpath_handle: Virtual path whose Fifo "containing" 1 or more completed | |
1710 | * descriptors. | |
1711 | * @txdlh: First completed descriptor. | |
1712 | * @txdl_priv: Pointer to per txdl space allocated | |
1713 | * @t_code: Transfer code, as per Titan User Guide. | |
1714 | * Returned by HW. | |
1715 | * @host_control: Opaque 64bit data stored by driver inside the Titan | |
1716 | * descriptor prior to posting the latter on the fifo | |
1717 | * via vxge_hw_fifo_txdl_post(). The @host_control is returned | |
1718 | * as is to the driver with each completed descriptor. | |
1719 | * @userdata: Opaque per-fifo data specified at fifo open | |
1720 | * time, via vxge_hw_vpath_open(). | |
1721 | * | |
1722 | * Fifo completion callback (type declaration). A single per-fifo | |
1723 | * callback is specified at fifo open time, via | |
1724 | * vxge_hw_vpath_open(). Typically gets called as part of the processing | |
1725 | * of the Interrupt Service Routine. | |
1726 | * | |
1727 | * Fifo callback gets called by HW if, and only if, there is at least | |
1728 | * one new completion on a given fifo. Upon processing the first @txdlh driver | |
1729 | * is _supposed_ to continue consuming completions using: | |
1730 | * - vxge_hw_fifo_txdl_next_completed() | |
1731 | * | |
1732 | * Note that failure to process new completions in a timely fashion | |
1733 | * leads to VXGE_HW_INF_OUT_OF_DESCRIPTORS condition. | |
1734 | * | |
1735 | * Non-zero @t_code means failure to process transmit descriptor. | |
1736 | * | |
1737 | * In the "transmit" case the failure could happen, for instance, when the | |
1738 | * link is down, in which case Titan completes the descriptor because it | |
1739 | * is not able to send the data out. | |
1740 | * | |
1741 | * For details please refer to Titan User Guide. | |
1742 | * | |
1743 | * See also: vxge_hw_fifo_txdl_next_completed(), vxge_hw_fifo_txdl_term_f{}. | |
1744 | */ | |
1745 | /** | |
1746 | * function vxge_hw_fifo_txdl_term_f - Terminate descriptor callback. | |
1747 | * @txdlh: First completed descriptor. | |
1748 | * @txdl_priv: Pointer to per txdl space allocated | |
1749 | * @state: One of the enum vxge_hw_txdl_state{} enumerated states. | |
1750 | * @userdata: Per-fifo user data (a.k.a. context) specified at | |
1751 | * fifo open time, via vxge_hw_vpath_open(). | |
1752 | * | |
1753 | * Terminate descriptor callback. Unless NULL is specified in the | |
1754 | * struct vxge_hw_fifo_attr{} structure passed to vxge_hw_vpath_open()), | |
1755 | * HW invokes the callback as part of closing fifo, prior to | |
1756 | * de-allocating the ring and associated data structures | |
1757 | * (including descriptors). | |
1758 | * driver should utilize the callback to (for instance) unmap | |
1759 | * and free DMA data buffers associated with the posted (state = | |
1760 | * VXGE_HW_TXDL_STATE_POSTED) descriptors, | |
1761 | * as well as other relevant cleanup functions. | |
1762 | * | |
1763 | * See also: struct vxge_hw_fifo_attr{} | |
1764 | */ | |
1765 | /** | |
1766 | * struct vxge_hw_fifo_attr - Fifo open "template". | |
1767 | * @callback: Fifo completion callback. HW invokes the callback when there | |
1768 | * are new completions on that fifo. In many implementations | |
1769 | * the @callback executes in the hw interrupt context. | |
1770 | * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, | |
1771 | * HW invokes the callback when closing the corresponding fifo. | |
1772 | * See also vxge_hw_fifo_txdl_term_f{}. | |
1773 | * @userdata: User-defined "context" of _that_ fifo. Passed back to the | |
1774 | * user as one of the @callback, and @txdl_term arguments. | |
1775 | * @per_txdl_space: If specified (i.e., greater than zero): extra space | |
1776 | * reserved by HW per each transmit descriptor. Can be used to | |
1777 | * store, and retrieve on completion, information specific | |
1778 | * to the driver. | |
1779 | * | |
1780 | * Fifo open "template". User fills the structure with fifo | |
1781 | * attributes and passes it to vxge_hw_vpath_open(). | |
1782 | */ | |
1783 | struct vxge_hw_fifo_attr { | |
1784 | ||
1785 | enum vxge_hw_status (*callback)( | |
1786 | struct __vxge_hw_fifo *fifo_handle, | |
1787 | void *txdlh, | |
1788 | enum vxge_hw_fifo_tcode t_code, | |
1789 | void *userdata, | |
1790 | void **skb_ptr); | |
1791 | ||
1792 | void (*txdl_term)( | |
1793 | void *txdlh, | |
1794 | enum vxge_hw_txdl_state state, | |
1795 | void *userdata); | |
1796 | ||
1797 | void *userdata; | |
1798 | u32 per_txdl_space; | |
1799 | }; | |
1800 | ||
1801 | /** | |
1802 | * struct vxge_hw_vpath_attr - Attributes of virtual path | |
1803 | * @vp_id: Identifier of Virtual Path | |
1804 | * @ring_attr: Attributes of ring for non-offload receive | |
1805 | * @fifo_attr: Attributes of fifo for non-offload transmit | |
1806 | * | |
1807 | * Attributes of virtual path. This structure is passed as parameter | |
1808 | * to the vxge_hw_vpath_open() routine to set the attributes of ring and fifo. | |
1809 | */ | |
1810 | struct vxge_hw_vpath_attr { | |
1811 | u32 vp_id; | |
1812 | struct vxge_hw_ring_attr ring_attr; | |
1813 | struct vxge_hw_fifo_attr fifo_attr; | |
1814 | }; | |
1815 | ||
1816 | enum vxge_hw_status | |
1817 | __vxge_hw_blockpool_create(struct __vxge_hw_device *hldev, | |
1818 | struct __vxge_hw_blockpool *blockpool, | |
1819 | u32 pool_size, | |
1820 | u32 pool_max); | |
1821 | ||
1822 | void | |
1823 | __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool); | |
1824 | ||
1825 | struct __vxge_hw_blockpool_entry * | |
1826 | __vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *hldev, | |
1827 | u32 size); | |
1828 | ||
1829 | void | |
1830 | __vxge_hw_blockpool_block_free(struct __vxge_hw_device *hldev, | |
1831 | struct __vxge_hw_blockpool_entry *entry); | |
1832 | ||
1833 | void * | |
1834 | __vxge_hw_blockpool_malloc(struct __vxge_hw_device *hldev, | |
1835 | u32 size, | |
1836 | struct vxge_hw_mempool_dma *dma_object); | |
1837 | ||
1838 | void | |
1839 | __vxge_hw_blockpool_free(struct __vxge_hw_device *hldev, | |
1840 | void *memblock, | |
1841 | u32 size, | |
1842 | struct vxge_hw_mempool_dma *dma_object); | |
1843 | ||
1844 | enum vxge_hw_status | |
1845 | __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config); | |
1846 | ||
1847 | enum vxge_hw_status | |
1848 | __vxge_hw_device_config_check(struct vxge_hw_device_config *new_config); | |
1849 | ||
1850 | enum vxge_hw_status | |
1851 | vxge_hw_mgmt_device_config(struct __vxge_hw_device *devh, | |
1852 | struct vxge_hw_device_config *dev_config, int size); | |
1853 | ||
1854 | enum vxge_hw_status __devinit vxge_hw_device_hw_info_get( | |
1855 | void __iomem *bar0, | |
1856 | struct vxge_hw_device_hw_info *hw_info); | |
1857 | ||
1858 | enum vxge_hw_status | |
1859 | __vxge_hw_vpath_fw_ver_get( | |
1860 | u32 vp_id, | |
1861 | struct vxge_hw_vpath_reg __iomem *vpath_reg, | |
1862 | struct vxge_hw_device_hw_info *hw_info); | |
1863 | ||
1864 | enum vxge_hw_status | |
1865 | __vxge_hw_vpath_card_info_get( | |
1866 | u32 vp_id, | |
1867 | struct vxge_hw_vpath_reg __iomem *vpath_reg, | |
1868 | struct vxge_hw_device_hw_info *hw_info); | |
1869 | ||
1870 | enum vxge_hw_status __devinit vxge_hw_device_config_default_get( | |
1871 | struct vxge_hw_device_config *device_config); | |
1872 | ||
1873 | /** | |
1874 | * vxge_hw_device_link_state_get - Get link state. | |
1875 | * @devh: HW device handle. | |
1876 | * | |
1877 | * Get link state. | |
1878 | * Returns: link state. | |
1879 | */ | |
1880 | static inline | |
1881 | enum vxge_hw_device_link_state vxge_hw_device_link_state_get( | |
1882 | struct __vxge_hw_device *devh) | |
1883 | { | |
1884 | return devh->link_state; | |
1885 | } | |
1886 | ||
1887 | void vxge_hw_device_terminate(struct __vxge_hw_device *devh); | |
1888 | ||
1889 | const u8 * | |
1890 | vxge_hw_device_serial_number_get(struct __vxge_hw_device *devh); | |
1891 | ||
1892 | u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *devh); | |
1893 | ||
1894 | const u8 * | |
1895 | vxge_hw_device_product_name_get(struct __vxge_hw_device *devh); | |
1896 | ||
1897 | enum vxge_hw_status __devinit vxge_hw_device_initialize( | |
1898 | struct __vxge_hw_device **devh, | |
1899 | struct vxge_hw_device_attr *attr, | |
1900 | struct vxge_hw_device_config *device_config); | |
1901 | ||
1902 | enum vxge_hw_status vxge_hw_device_getpause_data( | |
1903 | struct __vxge_hw_device *devh, | |
1904 | u32 port, | |
1905 | u32 *tx, | |
1906 | u32 *rx); | |
1907 | ||
1908 | enum vxge_hw_status vxge_hw_device_setpause_data( | |
1909 | struct __vxge_hw_device *devh, | |
1910 | u32 port, | |
1911 | u32 tx, | |
1912 | u32 rx); | |
1913 | ||
1914 | static inline void *vxge_os_dma_malloc(struct pci_dev *pdev, | |
1915 | unsigned long size, | |
1916 | struct pci_dev **p_dmah, | |
1917 | struct pci_dev **p_dma_acch) | |
1918 | { | |
1919 | gfp_t flags; | |
1920 | void *vaddr; | |
1921 | unsigned long misaligned = 0; | |
1922 | *p_dma_acch = *p_dmah = NULL; | |
1923 | ||
1924 | if (in_interrupt()) | |
1925 | flags = GFP_ATOMIC | GFP_DMA; | |
1926 | else | |
1927 | flags = GFP_KERNEL | GFP_DMA; | |
1928 | ||
1929 | size += VXGE_CACHE_LINE_SIZE; | |
1930 | ||
1931 | vaddr = kmalloc((size), flags); | |
1932 | if (vaddr == NULL) | |
1933 | return vaddr; | |
1934 | misaligned = (unsigned long)VXGE_ALIGN(*((u64 *)&vaddr), | |
1935 | VXGE_CACHE_LINE_SIZE); | |
1936 | *(unsigned long *)p_dma_acch = misaligned; | |
1937 | vaddr = (void *)((u8 *)vaddr + misaligned); | |
1938 | return vaddr; | |
1939 | } | |
1940 | ||
1941 | extern void vxge_hw_blockpool_block_add( | |
1942 | struct __vxge_hw_device *devh, | |
1943 | void *block_addr, | |
1944 | u32 length, | |
1945 | struct pci_dev *dma_h, | |
1946 | struct pci_dev *acc_handle); | |
1947 | ||
1948 | static inline void vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh, | |
1949 | unsigned long size) | |
1950 | { | |
1951 | gfp_t flags; | |
1952 | void *vaddr; | |
1953 | ||
1954 | if (in_interrupt()) | |
1955 | flags = GFP_ATOMIC | GFP_DMA; | |
1956 | else | |
1957 | flags = GFP_KERNEL | GFP_DMA; | |
1958 | ||
1959 | vaddr = kmalloc((size), flags); | |
1960 | ||
1961 | vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev); | |
1962 | } | |
1963 | ||
1964 | static inline void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr, | |
1965 | struct pci_dev **p_dma_acch) | |
1966 | { | |
1967 | unsigned long misaligned = *(unsigned long *)p_dma_acch; | |
1968 | u8 *tmp = (u8 *)vaddr; | |
1969 | tmp -= misaligned; | |
1970 | kfree((void *)tmp); | |
1971 | } | |
1972 | ||
1973 | /* | |
1974 | * __vxge_hw_mempool_item_priv - will return pointer on per item private space | |
1975 | */ | |
1976 | static inline void* | |
1977 | __vxge_hw_mempool_item_priv( | |
1978 | struct vxge_hw_mempool *mempool, | |
1979 | u32 memblock_idx, | |
1980 | void *item, | |
1981 | u32 *memblock_item_idx) | |
1982 | { | |
1983 | ptrdiff_t offset; | |
1984 | void *memblock = mempool->memblocks_arr[memblock_idx]; | |
1985 | ||
1986 | ||
1987 | offset = (u32)((u8 *)item - (u8 *)memblock); | |
1988 | vxge_assert(offset >= 0 && (u32)offset < mempool->memblock_size); | |
1989 | ||
1990 | (*memblock_item_idx) = (u32) offset / mempool->item_size; | |
1991 | vxge_assert((*memblock_item_idx) < mempool->items_per_memblock); | |
1992 | ||
1993 | return (u8 *)mempool->memblocks_priv_arr[memblock_idx] + | |
1994 | (*memblock_item_idx) * mempool->items_priv_size; | |
1995 | } | |
1996 | ||
1997 | enum vxge_hw_status | |
1998 | __vxge_hw_mempool_grow( | |
1999 | struct vxge_hw_mempool *mempool, | |
2000 | u32 num_allocate, | |
2001 | u32 *num_allocated); | |
2002 | ||
2003 | struct vxge_hw_mempool* | |
2004 | __vxge_hw_mempool_create( | |
2005 | struct __vxge_hw_device *devh, | |
2006 | u32 memblock_size, | |
2007 | u32 item_size, | |
2008 | u32 private_size, | |
2009 | u32 items_initial, | |
2010 | u32 items_max, | |
2011 | struct vxge_hw_mempool_cbs *mp_callback, | |
2012 | void *userdata); | |
2013 | ||
2014 | struct __vxge_hw_channel* | |
2015 | __vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph, | |
2016 | enum __vxge_hw_channel_type type, u32 length, | |
2017 | u32 per_dtr_space, void *userdata); | |
2018 | ||
2019 | void | |
2020 | __vxge_hw_channel_free( | |
2021 | struct __vxge_hw_channel *channel); | |
2022 | ||
2023 | enum vxge_hw_status | |
2024 | __vxge_hw_channel_initialize( | |
2025 | struct __vxge_hw_channel *channel); | |
2026 | ||
2027 | enum vxge_hw_status | |
2028 | __vxge_hw_channel_reset( | |
2029 | struct __vxge_hw_channel *channel); | |
2030 | ||
2031 | /* | |
2032 | * __vxge_hw_fifo_txdl_priv - Return the max fragments allocated | |
2033 | * for the fifo. | |
2034 | * @fifo: Fifo | |
2035 | * @txdp: Poniter to a TxD | |
2036 | */ | |
2037 | static inline struct __vxge_hw_fifo_txdl_priv * | |
2038 | __vxge_hw_fifo_txdl_priv( | |
2039 | struct __vxge_hw_fifo *fifo, | |
2040 | struct vxge_hw_fifo_txd *txdp) | |
2041 | { | |
2042 | return (struct __vxge_hw_fifo_txdl_priv *) | |
2043 | (((char *)((ulong)txdp->host_control)) + | |
2044 | fifo->per_txdl_space); | |
2045 | } | |
2046 | ||
2047 | enum vxge_hw_status vxge_hw_vpath_open( | |
2048 | struct __vxge_hw_device *devh, | |
2049 | struct vxge_hw_vpath_attr *attr, | |
2050 | struct __vxge_hw_vpath_handle **vpath_handle); | |
2051 | ||
2052 | enum vxge_hw_status | |
2053 | __vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog); | |
2054 | ||
2055 | enum vxge_hw_status vxge_hw_vpath_close( | |
2056 | struct __vxge_hw_vpath_handle *vpath_handle); | |
2057 | ||
2058 | enum vxge_hw_status | |
2059 | vxge_hw_vpath_reset( | |
2060 | struct __vxge_hw_vpath_handle *vpath_handle); | |
2061 | ||
2062 | enum vxge_hw_status | |
2063 | vxge_hw_vpath_recover_from_reset( | |
2064 | struct __vxge_hw_vpath_handle *vpath_handle); | |
2065 | ||
2066 | void | |
2067 | vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp); | |
2068 | ||
2069 | enum vxge_hw_status | |
2070 | vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ringh); | |
2071 | ||
2072 | enum vxge_hw_status vxge_hw_vpath_mtu_set( | |
2073 | struct __vxge_hw_vpath_handle *vpath_handle, | |
2074 | u32 new_mtu); | |
2075 | ||
2076 | enum vxge_hw_status vxge_hw_vpath_stats_enable( | |
2077 | struct __vxge_hw_vpath_handle *vpath_handle); | |
2078 | ||
2079 | enum vxge_hw_status | |
2080 | __vxge_hw_vpath_stats_access( | |
2081 | struct __vxge_hw_virtualpath *vpath, | |
2082 | u32 operation, | |
2083 | u32 offset, | |
2084 | u64 *stat); | |
2085 | ||
2086 | enum vxge_hw_status | |
2087 | __vxge_hw_vpath_xmac_tx_stats_get( | |
2088 | struct __vxge_hw_virtualpath *vpath, | |
2089 | struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats); | |
2090 | ||
2091 | enum vxge_hw_status | |
2092 | __vxge_hw_vpath_xmac_rx_stats_get( | |
2093 | struct __vxge_hw_virtualpath *vpath, | |
2094 | struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats); | |
2095 | ||
2096 | enum vxge_hw_status | |
2097 | __vxge_hw_vpath_stats_get( | |
2098 | struct __vxge_hw_virtualpath *vpath, | |
2099 | struct vxge_hw_vpath_stats_hw_info *hw_stats); | |
2100 | ||
2101 | void | |
2102 | vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp); | |
2103 | ||
2104 | enum vxge_hw_status | |
2105 | __vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config); | |
2106 | ||
2107 | void | |
2108 | __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev); | |
2109 | ||
2110 | enum vxge_hw_status | |
2111 | __vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg); | |
2112 | ||
2113 | enum vxge_hw_status | |
2114 | __vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg); | |
2115 | ||
2116 | enum vxge_hw_status | |
2117 | __vxge_hw_kdfc_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg, | |
2118 | struct vxge_hw_vpath_reg __iomem *vpath_reg); | |
2119 | ||
2120 | enum vxge_hw_status | |
2121 | __vxge_hw_device_register_poll( | |
2122 | void __iomem *reg, | |
2123 | u64 mask, u32 max_millis); | |
2124 | ||
2125 | #ifndef readq | |
2126 | static inline u64 readq(void __iomem *addr) | |
2127 | { | |
2128 | u64 ret = 0; | |
2129 | ret = readl(addr + 4); | |
2130 | ret <<= 32; | |
2131 | ret |= readl(addr); | |
2132 | ||
2133 | return ret; | |
2134 | } | |
2135 | #endif | |
2136 | ||
2137 | #ifndef writeq | |
2138 | static inline void writeq(u64 val, void __iomem *addr) | |
2139 | { | |
2140 | writel((u32) (val), addr); | |
2141 | writel((u32) (val >> 32), (addr + 4)); | |
2142 | } | |
2143 | #endif | |
2144 | ||
2145 | static inline void __vxge_hw_pio_mem_write32_upper(u32 val, void __iomem *addr) | |
2146 | { | |
2147 | writel(val, addr + 4); | |
2148 | } | |
2149 | ||
2150 | static inline void __vxge_hw_pio_mem_write32_lower(u32 val, void __iomem *addr) | |
2151 | { | |
2152 | writel(val, addr); | |
2153 | } | |
2154 | ||
2155 | static inline enum vxge_hw_status | |
2156 | __vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr, | |
2157 | u64 mask, u32 max_millis) | |
2158 | { | |
2159 | enum vxge_hw_status status = VXGE_HW_OK; | |
2160 | ||
2161 | __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr); | |
2162 | wmb(); | |
2163 | __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr); | |
2164 | wmb(); | |
2165 | ||
2166 | status = __vxge_hw_device_register_poll(addr, mask, max_millis); | |
2167 | return status; | |
2168 | } | |
2169 | ||
2170 | struct vxge_hw_toc_reg __iomem * | |
2171 | __vxge_hw_device_toc_get(void __iomem *bar0); | |
2172 | ||
2173 | enum vxge_hw_status | |
2174 | __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev); | |
2175 | ||
2176 | void | |
2177 | __vxge_hw_device_id_get(struct __vxge_hw_device *hldev); | |
2178 | ||
2179 | void | |
2180 | __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev); | |
2181 | ||
2182 | enum vxge_hw_status | |
2183 | vxge_hw_device_flick_link_led(struct __vxge_hw_device *devh, u64 on_off); | |
2184 | ||
2185 | enum vxge_hw_status | |
2186 | __vxge_hw_device_initialize(struct __vxge_hw_device *hldev); | |
2187 | ||
2188 | enum vxge_hw_status | |
2189 | __vxge_hw_vpath_pci_read( | |
2190 | struct __vxge_hw_virtualpath *vpath, | |
2191 | u32 phy_func_0, | |
2192 | u32 offset, | |
2193 | u32 *val); | |
2194 | ||
2195 | enum vxge_hw_status | |
2196 | __vxge_hw_vpath_addr_get( | |
2197 | u32 vp_id, | |
2198 | struct vxge_hw_vpath_reg __iomem *vpath_reg, | |
2199 | u8 (macaddr)[ETH_ALEN], | |
2200 | u8 (macaddr_mask)[ETH_ALEN]); | |
2201 | ||
2202 | u32 | |
2203 | __vxge_hw_vpath_func_id_get( | |
2204 | u32 vp_id, struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg); | |
2205 | ||
2206 | enum vxge_hw_status | |
2207 | __vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath); | |
2208 | ||
2209 | /** | |
2210 | * vxge_debug | |
2211 | * @level: level of debug verbosity. | |
2212 | * @mask: mask for the debug | |
2213 | * @buf: Circular buffer for tracing | |
2214 | * @fmt: printf like format string | |
2215 | * | |
2216 | * Provides logging facilities. Can be customized on per-module | |
2217 | * basis or/and with debug levels. Input parameters, except | |
2218 | * module and level, are the same as posix printf. This function | |
2219 | * may be compiled out if DEBUG macro was never defined. | |
2220 | * See also: enum vxge_debug_level{}. | |
2221 | */ | |
2222 | ||
2223 | #define vxge_trace_aux(level, mask, fmt, ...) \ | |
2224 | {\ | |
2225 | vxge_os_vaprintf(level, mask, fmt, __VA_ARGS__);\ | |
2226 | } | |
2227 | ||
2228 | #define vxge_debug(module, level, mask, fmt, ...) { \ | |
2229 | if ((level >= VXGE_TRACE && ((module & VXGE_DEBUG_TRACE_MASK) == module)) || \ | |
2230 | (level >= VXGE_ERR && ((module & VXGE_DEBUG_ERR_MASK) == module))) {\ | |
2231 | if ((mask & VXGE_DEBUG_MASK) == mask)\ | |
2232 | vxge_trace_aux(level, mask, fmt, __VA_ARGS__); \ | |
2233 | } \ | |
2234 | } | |
2235 | ||
2236 | #if (VXGE_COMPONENT_LL & VXGE_DEBUG_MODULE_MASK) | |
2237 | #define vxge_debug_ll(level, mask, fmt, ...) \ | |
2238 | {\ | |
2239 | vxge_debug(VXGE_COMPONENT_LL, level, mask, fmt, __VA_ARGS__);\ | |
2240 | } | |
2241 | ||
2242 | #else | |
2243 | #define vxge_debug_ll(level, mask, fmt, ...) | |
2244 | #endif | |
2245 | ||
2246 | enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set( | |
2247 | struct __vxge_hw_vpath_handle **vpath_handles, | |
2248 | u32 vpath_count, | |
2249 | u8 *mtable, | |
2250 | u8 *itable, | |
2251 | u32 itable_size); | |
2252 | ||
2253 | enum vxge_hw_status vxge_hw_vpath_rts_rth_set( | |
2254 | struct __vxge_hw_vpath_handle *vpath_handle, | |
2255 | enum vxge_hw_rth_algoritms algorithm, | |
2256 | struct vxge_hw_rth_hash_types *hash_type, | |
2257 | u16 bucket_size); | |
2258 | ||
2259 | #endif |