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1da177e4 LT |
1 | /* |
2 | * FarSync WAN driver for Linux (2.6.x kernel version) | |
3 | * | |
4 | * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards | |
5 | * | |
6 | * Copyright (C) 2001-2004 FarSite Communications Ltd. | |
7 | * www.farsite.co.uk | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> | |
15 | * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk> | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/kernel.h> | |
20 | #include <linux/version.h> | |
21 | #include <linux/pci.h> | |
d43c36dc | 22 | #include <linux/sched.h> |
1da177e4 LT |
23 | #include <linux/ioport.h> |
24 | #include <linux/init.h> | |
25 | #include <linux/if.h> | |
26 | #include <linux/hdlc.h> | |
27 | #include <asm/io.h> | |
28 | #include <asm/uaccess.h> | |
29 | ||
30 | #include "farsync.h" | |
31 | ||
32 | /* | |
33 | * Module info | |
34 | */ | |
35 | MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>"); | |
36 | MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd."); | |
37 | MODULE_LICENSE("GPL"); | |
38 | ||
39 | /* Driver configuration and global parameters | |
40 | * ========================================== | |
41 | */ | |
42 | ||
43 | /* Number of ports (per card) and cards supported | |
44 | */ | |
45 | #define FST_MAX_PORTS 4 | |
46 | #define FST_MAX_CARDS 32 | |
47 | ||
48 | /* Default parameters for the link | |
49 | */ | |
50 | #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is | |
0bee8db8 | 51 | * useful */ |
1da177e4 LT |
52 | #define FST_TXQ_DEPTH 16 /* This one is for the buffering |
53 | * of frames on the way down to the card | |
54 | * so that we can keep the card busy | |
55 | * and maximise throughput | |
56 | */ | |
57 | #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control | |
58 | * network layer */ | |
59 | #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow | |
60 | * control from network layer */ | |
61 | #define FST_MAX_MTU 8000 /* Huge but possible */ | |
62 | #define FST_DEF_MTU 1500 /* Common sane value */ | |
63 | ||
64 | #define FST_TX_TIMEOUT (2*HZ) | |
65 | ||
66 | #ifdef ARPHRD_RAWHDLC | |
67 | #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */ | |
68 | #else | |
69 | #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */ | |
70 | #endif | |
71 | ||
72 | /* | |
3a070ad1 | 73 | * Modules parameters and associated variables |
1da177e4 | 74 | */ |
7665a089 AB |
75 | static int fst_txq_low = FST_LOW_WATER_MARK; |
76 | static int fst_txq_high = FST_HIGH_WATER_MARK; | |
77 | static int fst_max_reads = 7; | |
78 | static int fst_excluded_cards = 0; | |
79 | static int fst_excluded_list[FST_MAX_CARDS]; | |
1da177e4 LT |
80 | |
81 | module_param(fst_txq_low, int, 0); | |
82 | module_param(fst_txq_high, int, 0); | |
83 | module_param(fst_max_reads, int, 0); | |
84 | module_param(fst_excluded_cards, int, 0); | |
85 | module_param_array(fst_excluded_list, int, NULL, 0); | |
86 | ||
87 | /* Card shared memory layout | |
88 | * ========================= | |
89 | */ | |
90 | #pragma pack(1) | |
91 | ||
92 | /* This information is derived in part from the FarSite FarSync Smc.h | |
93 | * file. Unfortunately various name clashes and the non-portability of the | |
94 | * bit field declarations in that file have meant that I have chosen to | |
95 | * recreate the information here. | |
96 | * | |
97 | * The SMC (Shared Memory Configuration) has a version number that is | |
98 | * incremented every time there is a significant change. This number can | |
99 | * be used to check that we have not got out of step with the firmware | |
100 | * contained in the .CDE files. | |
101 | */ | |
102 | #define SMC_VERSION 24 | |
103 | ||
104 | #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */ | |
105 | ||
106 | #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main | |
107 | * configuration structure */ | |
108 | #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA | |
109 | * buffers */ | |
110 | ||
111 | #define LEN_TX_BUFFER 8192 /* Size of packet buffers */ | |
112 | #define LEN_RX_BUFFER 8192 | |
113 | ||
114 | #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */ | |
115 | #define LEN_SMALL_RX_BUFFER 256 | |
116 | ||
117 | #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */ | |
118 | #define NUM_RX_BUFFER 8 | |
119 | ||
120 | /* Interrupt retry time in milliseconds */ | |
121 | #define INT_RETRY_TIME 2 | |
122 | ||
123 | /* The Am186CH/CC processors support a SmartDMA mode using circular pools | |
124 | * of buffer descriptors. The structure is almost identical to that used | |
125 | * in the LANCE Ethernet controllers. Details available as PDF from the | |
126 | * AMD web site: http://www.amd.com/products/epd/processors/\ | |
127 | * 2.16bitcont/3.am186cxfa/a21914/21914.pdf | |
128 | */ | |
129 | struct txdesc { /* Transmit descriptor */ | |
130 | volatile u16 ladr; /* Low order address of packet. This is a | |
131 | * linear address in the Am186 memory space | |
132 | */ | |
133 | volatile u8 hadr; /* High order address. Low 4 bits only, high 4 | |
134 | * bits must be zero | |
135 | */ | |
136 | volatile u8 bits; /* Status and config */ | |
137 | volatile u16 bcnt; /* 2s complement of packet size in low 15 bits. | |
138 | * Transmit terminal count interrupt enable in | |
139 | * top bit. | |
140 | */ | |
141 | u16 unused; /* Not used in Tx */ | |
142 | }; | |
143 | ||
144 | struct rxdesc { /* Receive descriptor */ | |
145 | volatile u16 ladr; /* Low order address of packet */ | |
146 | volatile u8 hadr; /* High order address */ | |
147 | volatile u8 bits; /* Status and config */ | |
148 | volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits. | |
149 | * Receive terminal count interrupt enable in | |
150 | * top bit. | |
151 | */ | |
152 | volatile u16 mcnt; /* Message byte count (15 bits) */ | |
153 | }; | |
154 | ||
155 | /* Convert a length into the 15 bit 2's complement */ | |
156 | /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */ | |
157 | /* Since we need to set the high bit to enable the completion interrupt this | |
158 | * can be made a lot simpler | |
159 | */ | |
160 | #define cnv_bcnt(len) (-(len)) | |
161 | ||
162 | /* Status and config bits for the above */ | |
163 | #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */ | |
164 | #define TX_STP 0x02 /* Tx: start of packet */ | |
165 | #define TX_ENP 0x01 /* Tx: end of packet */ | |
166 | #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */ | |
167 | #define RX_FRAM 0x20 /* Rx: framing error */ | |
168 | #define RX_OFLO 0x10 /* Rx: overflow error */ | |
169 | #define RX_CRC 0x08 /* Rx: CRC error */ | |
170 | #define RX_HBUF 0x04 /* Rx: buffer error */ | |
171 | #define RX_STP 0x02 /* Rx: start of packet */ | |
172 | #define RX_ENP 0x01 /* Rx: end of packet */ | |
173 | ||
174 | /* Interrupts from the card are caused by various events which are presented | |
175 | * in a circular buffer as several events may be processed on one physical int | |
176 | */ | |
177 | #define MAX_CIRBUFF 32 | |
178 | ||
179 | struct cirbuff { | |
180 | u8 rdindex; /* read, then increment and wrap */ | |
181 | u8 wrindex; /* write, then increment and wrap */ | |
182 | u8 evntbuff[MAX_CIRBUFF]; | |
183 | }; | |
184 | ||
185 | /* Interrupt event codes. | |
186 | * Where appropriate the two low order bits indicate the port number | |
187 | */ | |
188 | #define CTLA_CHG 0x18 /* Control signal changed */ | |
189 | #define CTLB_CHG 0x19 | |
190 | #define CTLC_CHG 0x1A | |
191 | #define CTLD_CHG 0x1B | |
192 | ||
193 | #define INIT_CPLT 0x20 /* Initialisation complete */ | |
194 | #define INIT_FAIL 0x21 /* Initialisation failed */ | |
195 | ||
196 | #define ABTA_SENT 0x24 /* Abort sent */ | |
197 | #define ABTB_SENT 0x25 | |
198 | #define ABTC_SENT 0x26 | |
199 | #define ABTD_SENT 0x27 | |
200 | ||
201 | #define TXA_UNDF 0x28 /* Transmission underflow */ | |
202 | #define TXB_UNDF 0x29 | |
203 | #define TXC_UNDF 0x2A | |
204 | #define TXD_UNDF 0x2B | |
205 | ||
206 | #define F56_INT 0x2C | |
207 | #define M32_INT 0x2D | |
208 | ||
209 | #define TE1_ALMA 0x30 | |
210 | ||
211 | /* Port physical configuration. See farsync.h for field values */ | |
212 | struct port_cfg { | |
213 | u16 lineInterface; /* Physical interface type */ | |
214 | u8 x25op; /* Unused at present */ | |
215 | u8 internalClock; /* 1 => internal clock, 0 => external */ | |
216 | u8 transparentMode; /* 1 => on, 0 => off */ | |
217 | u8 invertClock; /* 0 => normal, 1 => inverted */ | |
218 | u8 padBytes[6]; /* Padding */ | |
219 | u32 lineSpeed; /* Speed in bps */ | |
220 | }; | |
221 | ||
222 | /* TE1 port physical configuration */ | |
223 | struct su_config { | |
224 | u32 dataRate; | |
225 | u8 clocking; | |
226 | u8 framing; | |
227 | u8 structure; | |
228 | u8 interface; | |
229 | u8 coding; | |
230 | u8 lineBuildOut; | |
231 | u8 equalizer; | |
232 | u8 transparentMode; | |
233 | u8 loopMode; | |
234 | u8 range; | |
235 | u8 txBufferMode; | |
236 | u8 rxBufferMode; | |
237 | u8 startingSlot; | |
238 | u8 losThreshold; | |
239 | u8 enableIdleCode; | |
240 | u8 idleCode; | |
241 | u8 spare[44]; | |
242 | }; | |
243 | ||
244 | /* TE1 Status */ | |
245 | struct su_status { | |
246 | u32 receiveBufferDelay; | |
247 | u32 framingErrorCount; | |
248 | u32 codeViolationCount; | |
249 | u32 crcErrorCount; | |
250 | u32 lineAttenuation; | |
251 | u8 portStarted; | |
252 | u8 lossOfSignal; | |
253 | u8 receiveRemoteAlarm; | |
254 | u8 alarmIndicationSignal; | |
255 | u8 spare[40]; | |
256 | }; | |
257 | ||
258 | /* Finally sling all the above together into the shared memory structure. | |
259 | * Sorry it's a hodge podge of arrays, structures and unused bits, it's been | |
260 | * evolving under NT for some time so I guess we're stuck with it. | |
261 | * The structure starts at offset SMC_BASE. | |
262 | * See farsync.h for some field values. | |
263 | */ | |
264 | struct fst_shared { | |
265 | /* DMA descriptor rings */ | |
266 | struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER]; | |
267 | struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER]; | |
268 | ||
269 | /* Obsolete small buffers */ | |
270 | u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER]; | |
271 | u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER]; | |
272 | ||
273 | u8 taskStatus; /* 0x00 => initialising, 0x01 => running, | |
274 | * 0xFF => halted | |
275 | */ | |
276 | ||
277 | u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt, | |
278 | * set to 0xEE by host to acknowledge interrupt | |
279 | */ | |
280 | ||
281 | u16 smcVersion; /* Must match SMC_VERSION */ | |
282 | ||
283 | u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major | |
284 | * version, RR = revision and BB = build | |
285 | */ | |
286 | ||
287 | u16 txa_done; /* Obsolete completion flags */ | |
288 | u16 rxa_done; | |
289 | u16 txb_done; | |
290 | u16 rxb_done; | |
291 | u16 txc_done; | |
292 | u16 rxc_done; | |
293 | u16 txd_done; | |
294 | u16 rxd_done; | |
295 | ||
296 | u16 mailbox[4]; /* Diagnostics mailbox. Not used */ | |
297 | ||
298 | struct cirbuff interruptEvent; /* interrupt causes */ | |
299 | ||
300 | u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */ | |
301 | u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */ | |
302 | ||
303 | struct port_cfg portConfig[FST_MAX_PORTS]; | |
304 | ||
305 | u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */ | |
306 | ||
307 | u16 cableStatus; /* lsb: 0=> present, 1=> absent */ | |
308 | ||
309 | u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */ | |
310 | u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */ | |
311 | ||
312 | u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */ | |
313 | u16 cardMailbox[4]; /* Not used */ | |
314 | ||
315 | /* Number of times the card thinks the host has | |
316 | * missed an interrupt by not acknowledging | |
317 | * within 2mS (I guess NT has problems) | |
318 | */ | |
319 | u32 interruptRetryCount; | |
320 | ||
321 | /* Driver private data used as an ID. We'll not | |
322 | * use this as I'd rather keep such things | |
323 | * in main memory rather than on the PCI bus | |
324 | */ | |
325 | u32 portHandle[FST_MAX_PORTS]; | |
326 | ||
327 | /* Count of Tx underflows for stats */ | |
328 | u32 transmitBufferUnderflow[FST_MAX_PORTS]; | |
329 | ||
330 | /* Debounced V.24 control input status */ | |
331 | u32 v24DebouncedSts[FST_MAX_PORTS]; | |
332 | ||
333 | /* Adapter debounce timers. Don't touch */ | |
334 | u32 ctsTimer[FST_MAX_PORTS]; | |
335 | u32 ctsTimerRun[FST_MAX_PORTS]; | |
336 | u32 dcdTimer[FST_MAX_PORTS]; | |
337 | u32 dcdTimerRun[FST_MAX_PORTS]; | |
338 | ||
339 | u32 numberOfPorts; /* Number of ports detected at startup */ | |
340 | ||
341 | u16 _reserved[64]; | |
342 | ||
343 | u16 cardMode; /* Bit-mask to enable features: | |
344 | * Bit 0: 1 enables LED identify mode | |
345 | */ | |
346 | ||
347 | u16 portScheduleOffset; | |
348 | ||
349 | struct su_config suConfig; /* TE1 Bits */ | |
350 | struct su_status suStatus; | |
351 | ||
352 | u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of | |
353 | * the structure and marks the end of shared | |
354 | * memory. Adapter code initializes it as | |
355 | * END_SIG. | |
356 | */ | |
357 | }; | |
358 | ||
359 | /* endOfSmcSignature value */ | |
360 | #define END_SIG 0x12345678 | |
361 | ||
362 | /* Mailbox values. (portMailbox) */ | |
363 | #define NOP 0 /* No operation */ | |
364 | #define ACK 1 /* Positive acknowledgement to PC driver */ | |
365 | #define NAK 2 /* Negative acknowledgement to PC driver */ | |
366 | #define STARTPORT 3 /* Start an HDLC port */ | |
367 | #define STOPPORT 4 /* Stop an HDLC port */ | |
368 | #define ABORTTX 5 /* Abort the transmitter for a port */ | |
369 | #define SETV24O 6 /* Set V24 outputs */ | |
370 | ||
371 | /* PLX Chip Register Offsets */ | |
372 | #define CNTRL_9052 0x50 /* Control Register */ | |
373 | #define CNTRL_9054 0x6c /* Control Register */ | |
374 | ||
375 | #define INTCSR_9052 0x4c /* Interrupt control/status register */ | |
376 | #define INTCSR_9054 0x68 /* Interrupt control/status register */ | |
377 | ||
378 | /* 9054 DMA Registers */ | |
379 | /* | |
380 | * Note that we will be using DMA Channel 0 for copying rx data | |
381 | * and Channel 1 for copying tx data | |
382 | */ | |
383 | #define DMAMODE0 0x80 | |
384 | #define DMAPADR0 0x84 | |
385 | #define DMALADR0 0x88 | |
386 | #define DMASIZ0 0x8c | |
387 | #define DMADPR0 0x90 | |
388 | #define DMAMODE1 0x94 | |
389 | #define DMAPADR1 0x98 | |
390 | #define DMALADR1 0x9c | |
391 | #define DMASIZ1 0xa0 | |
392 | #define DMADPR1 0xa4 | |
393 | #define DMACSR0 0xa8 | |
394 | #define DMACSR1 0xa9 | |
395 | #define DMAARB 0xac | |
396 | #define DMATHR 0xb0 | |
397 | #define DMADAC0 0xb4 | |
398 | #define DMADAC1 0xb8 | |
399 | #define DMAMARBR 0xac | |
400 | ||
401 | #define FST_MIN_DMA_LEN 64 | |
402 | #define FST_RX_DMA_INT 0x01 | |
403 | #define FST_TX_DMA_INT 0x02 | |
404 | #define FST_CARD_INT 0x04 | |
405 | ||
406 | /* Larger buffers are positioned in memory at offset BFM_BASE */ | |
407 | struct buf_window { | |
408 | u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER]; | |
409 | u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER]; | |
410 | }; | |
411 | ||
412 | /* Calculate offset of a buffer object within the shared memory window */ | |
413 | #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X)) | |
414 | ||
415 | #pragma pack() | |
416 | ||
417 | /* Device driver private information | |
418 | * ================================= | |
419 | */ | |
420 | /* Per port (line or channel) information | |
421 | */ | |
422 | struct fst_port_info { | |
423 | struct net_device *dev; /* Device struct - must be first */ | |
424 | struct fst_card_info *card; /* Card we're associated with */ | |
425 | int index; /* Port index on the card */ | |
426 | int hwif; /* Line hardware (lineInterface copy) */ | |
427 | int run; /* Port is running */ | |
428 | int mode; /* Normal or FarSync raw */ | |
429 | int rxpos; /* Next Rx buffer to use */ | |
430 | int txpos; /* Next Tx buffer to use */ | |
431 | int txipos; /* Next Tx buffer to check for free */ | |
432 | int start; /* Indication of start/stop to network */ | |
433 | /* | |
434 | * A sixteen entry transmit queue | |
435 | */ | |
436 | int txqs; /* index to get next buffer to tx */ | |
437 | int txqe; /* index to queue next packet */ | |
438 | struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */ | |
439 | int rxqdepth; | |
440 | }; | |
441 | ||
442 | /* Per card information | |
443 | */ | |
444 | struct fst_card_info { | |
445 | char __iomem *mem; /* Card memory mapped to kernel space */ | |
446 | char __iomem *ctlmem; /* Control memory for PCI cards */ | |
447 | unsigned int phys_mem; /* Physical memory window address */ | |
448 | unsigned int phys_ctlmem; /* Physical control memory address */ | |
449 | unsigned int irq; /* Interrupt request line number */ | |
450 | unsigned int nports; /* Number of serial ports */ | |
451 | unsigned int type; /* Type index of card */ | |
452 | unsigned int state; /* State of card */ | |
453 | spinlock_t card_lock; /* Lock for SMP access */ | |
454 | unsigned short pci_conf; /* PCI card config in I/O space */ | |
455 | /* Per port info */ | |
456 | struct fst_port_info ports[FST_MAX_PORTS]; | |
457 | struct pci_dev *device; /* Information about the pci device */ | |
458 | int card_no; /* Inst of the card on the system */ | |
459 | int family; /* TxP or TxU */ | |
460 | int dmarx_in_progress; | |
461 | int dmatx_in_progress; | |
462 | unsigned long int_count; | |
463 | unsigned long int_time_ave; | |
464 | void *rx_dma_handle_host; | |
465 | dma_addr_t rx_dma_handle_card; | |
466 | void *tx_dma_handle_host; | |
467 | dma_addr_t tx_dma_handle_card; | |
468 | struct sk_buff *dma_skb_rx; | |
469 | struct fst_port_info *dma_port_rx; | |
470 | struct fst_port_info *dma_port_tx; | |
471 | int dma_len_rx; | |
472 | int dma_len_tx; | |
473 | int dma_txpos; | |
474 | int dma_rxpos; | |
475 | }; | |
476 | ||
477 | /* Convert an HDLC device pointer into a port info pointer and similar */ | |
478 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) | |
479 | #define port_to_dev(P) ((P)->dev) | |
480 | ||
481 | ||
482 | /* | |
483 | * Shared memory window access macros | |
484 | * | |
485 | * We have a nice memory based structure above, which could be directly | |
486 | * mapped on i386 but might not work on other architectures unless we use | |
487 | * the readb,w,l and writeb,w,l macros. Unfortunately these macros take | |
488 | * physical offsets so we have to convert. The only saving grace is that | |
489 | * this should all collapse back to a simple indirection eventually. | |
490 | */ | |
491 | #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X)) | |
492 | ||
493 | #define FST_RDB(C,E) readb ((C)->mem + WIN_OFFSET(E)) | |
494 | #define FST_RDW(C,E) readw ((C)->mem + WIN_OFFSET(E)) | |
495 | #define FST_RDL(C,E) readl ((C)->mem + WIN_OFFSET(E)) | |
496 | ||
497 | #define FST_WRB(C,E,B) writeb ((B), (C)->mem + WIN_OFFSET(E)) | |
498 | #define FST_WRW(C,E,W) writew ((W), (C)->mem + WIN_OFFSET(E)) | |
499 | #define FST_WRL(C,E,L) writel ((L), (C)->mem + WIN_OFFSET(E)) | |
500 | ||
501 | /* | |
502 | * Debug support | |
503 | */ | |
504 | #if FST_DEBUG | |
505 | ||
506 | static int fst_debug_mask = { FST_DEBUG }; | |
507 | ||
508 | /* Most common debug activity is to print something if the corresponding bit | |
509 | * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to | |
510 | * support variable numbers of macro parameters. The inverted if prevents us | |
511 | * eating someone else's else clause. | |
512 | */ | |
513 | #define dbg(F,fmt,A...) if ( ! ( fst_debug_mask & (F))) \ | |
514 | ; \ | |
515 | else \ | |
516 | printk ( KERN_DEBUG FST_NAME ": " fmt, ## A ) | |
517 | ||
518 | #else | |
519 | #define dbg(X...) /* NOP */ | |
520 | #endif | |
521 | ||
522 | /* Printing short cuts | |
523 | */ | |
524 | #define printk_err(fmt,A...) printk ( KERN_ERR FST_NAME ": " fmt, ## A ) | |
525 | #define printk_warn(fmt,A...) printk ( KERN_WARNING FST_NAME ": " fmt, ## A ) | |
526 | #define printk_info(fmt,A...) printk ( KERN_INFO FST_NAME ": " fmt, ## A ) | |
527 | ||
528 | /* | |
529 | * PCI ID lookup table | |
530 | */ | |
531 | static struct pci_device_id fst_pci_dev_id[] __devinitdata = { | |
532 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID, | |
533 | PCI_ANY_ID, 0, 0, FST_TYPE_T2P}, | |
534 | ||
535 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID, | |
536 | PCI_ANY_ID, 0, 0, FST_TYPE_T4P}, | |
537 | ||
538 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID, | |
539 | PCI_ANY_ID, 0, 0, FST_TYPE_T1U}, | |
540 | ||
541 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID, | |
542 | PCI_ANY_ID, 0, 0, FST_TYPE_T2U}, | |
543 | ||
544 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID, | |
545 | PCI_ANY_ID, 0, 0, FST_TYPE_T4U}, | |
546 | ||
547 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID, | |
548 | PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, | |
549 | ||
550 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID, | |
551 | PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, | |
552 | {0,} /* End */ | |
553 | }; | |
554 | ||
555 | MODULE_DEVICE_TABLE(pci, fst_pci_dev_id); | |
556 | ||
557 | /* | |
558 | * Device Driver Work Queues | |
559 | * | |
560 | * So that we don't spend too much time processing events in the | |
561 | * Interrupt Service routine, we will declare a work queue per Card | |
562 | * and make the ISR schedule a task in the queue for later execution. | |
563 | * In the 2.4 Kernel we used to use the immediate queue for BH's | |
564 | * Now that they are gone, tasklets seem to be much better than work | |
565 | * queues. | |
566 | */ | |
567 | ||
568 | static void do_bottom_half_tx(struct fst_card_info *card); | |
569 | static void do_bottom_half_rx(struct fst_card_info *card); | |
570 | static void fst_process_tx_work_q(unsigned long work_q); | |
571 | static void fst_process_int_work_q(unsigned long work_q); | |
572 | ||
7665a089 AB |
573 | static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q, 0); |
574 | static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q, 0); | |
1da177e4 | 575 | |
7665a089 AB |
576 | static struct fst_card_info *fst_card_array[FST_MAX_CARDS]; |
577 | static spinlock_t fst_work_q_lock; | |
578 | static u64 fst_work_txq; | |
579 | static u64 fst_work_intq; | |
1da177e4 LT |
580 | |
581 | static void | |
582 | fst_q_work_item(u64 * queue, int card_index) | |
583 | { | |
584 | unsigned long flags; | |
585 | u64 mask; | |
586 | ||
587 | /* | |
588 | * Grab the queue exclusively | |
589 | */ | |
590 | spin_lock_irqsave(&fst_work_q_lock, flags); | |
591 | ||
592 | /* | |
593 | * Making an entry in the queue is simply a matter of setting | |
594 | * a bit for the card indicating that there is work to do in the | |
595 | * bottom half for the card. Note the limitation of 64 cards. | |
596 | * That ought to be enough | |
597 | */ | |
598 | mask = 1 << card_index; | |
599 | *queue |= mask; | |
600 | spin_unlock_irqrestore(&fst_work_q_lock, flags); | |
601 | } | |
602 | ||
603 | static void | |
604 | fst_process_tx_work_q(unsigned long /*void **/work_q) | |
605 | { | |
606 | unsigned long flags; | |
607 | u64 work_txq; | |
608 | int i; | |
609 | ||
610 | /* | |
611 | * Grab the queue exclusively | |
612 | */ | |
613 | dbg(DBG_TX, "fst_process_tx_work_q\n"); | |
614 | spin_lock_irqsave(&fst_work_q_lock, flags); | |
615 | work_txq = fst_work_txq; | |
616 | fst_work_txq = 0; | |
617 | spin_unlock_irqrestore(&fst_work_q_lock, flags); | |
618 | ||
619 | /* | |
620 | * Call the bottom half for each card with work waiting | |
621 | */ | |
622 | for (i = 0; i < FST_MAX_CARDS; i++) { | |
623 | if (work_txq & 0x01) { | |
624 | if (fst_card_array[i] != NULL) { | |
625 | dbg(DBG_TX, "Calling tx bh for card %d\n", i); | |
626 | do_bottom_half_tx(fst_card_array[i]); | |
627 | } | |
628 | } | |
629 | work_txq = work_txq >> 1; | |
630 | } | |
631 | } | |
632 | ||
633 | static void | |
634 | fst_process_int_work_q(unsigned long /*void **/work_q) | |
635 | { | |
636 | unsigned long flags; | |
637 | u64 work_intq; | |
638 | int i; | |
639 | ||
640 | /* | |
641 | * Grab the queue exclusively | |
642 | */ | |
643 | dbg(DBG_INTR, "fst_process_int_work_q\n"); | |
644 | spin_lock_irqsave(&fst_work_q_lock, flags); | |
645 | work_intq = fst_work_intq; | |
646 | fst_work_intq = 0; | |
647 | spin_unlock_irqrestore(&fst_work_q_lock, flags); | |
648 | ||
649 | /* | |
650 | * Call the bottom half for each card with work waiting | |
651 | */ | |
652 | for (i = 0; i < FST_MAX_CARDS; i++) { | |
653 | if (work_intq & 0x01) { | |
654 | if (fst_card_array[i] != NULL) { | |
655 | dbg(DBG_INTR, | |
656 | "Calling rx & tx bh for card %d\n", i); | |
657 | do_bottom_half_rx(fst_card_array[i]); | |
658 | do_bottom_half_tx(fst_card_array[i]); | |
659 | } | |
660 | } | |
661 | work_intq = work_intq >> 1; | |
662 | } | |
663 | } | |
664 | ||
665 | /* Card control functions | |
666 | * ====================== | |
667 | */ | |
668 | /* Place the processor in reset state | |
669 | * | |
670 | * Used to be a simple write to card control space but a glitch in the latest | |
671 | * AMD Am186CH processor means that we now have to do it by asserting and de- | |
672 | * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register | |
673 | * at offset 9052_CNTRL. Note the updates for the TXU. | |
674 | */ | |
675 | static inline void | |
676 | fst_cpureset(struct fst_card_info *card) | |
677 | { | |
678 | unsigned char interrupt_line_register; | |
679 | unsigned long j = jiffies + 1; | |
680 | unsigned int regval; | |
681 | ||
682 | if (card->family == FST_FAMILY_TXU) { | |
683 | if (pci_read_config_byte | |
684 | (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) { | |
685 | dbg(DBG_ASS, | |
686 | "Error in reading interrupt line register\n"); | |
687 | } | |
688 | /* | |
689 | * Assert PLX software reset and Am186 hardware reset | |
690 | * and then deassert the PLX software reset but 186 still in reset | |
691 | */ | |
692 | outw(0x440f, card->pci_conf + CNTRL_9054 + 2); | |
693 | outw(0x040f, card->pci_conf + CNTRL_9054 + 2); | |
694 | /* | |
695 | * We are delaying here to allow the 9054 to reset itself | |
696 | */ | |
697 | j = jiffies + 1; | |
698 | while (jiffies < j) | |
699 | /* Do nothing */ ; | |
700 | outw(0x240f, card->pci_conf + CNTRL_9054 + 2); | |
701 | /* | |
702 | * We are delaying here to allow the 9054 to reload its eeprom | |
703 | */ | |
704 | j = jiffies + 1; | |
705 | while (jiffies < j) | |
706 | /* Do nothing */ ; | |
707 | outw(0x040f, card->pci_conf + CNTRL_9054 + 2); | |
708 | ||
709 | if (pci_write_config_byte | |
710 | (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) { | |
711 | dbg(DBG_ASS, | |
712 | "Error in writing interrupt line register\n"); | |
713 | } | |
714 | ||
715 | } else { | |
716 | regval = inl(card->pci_conf + CNTRL_9052); | |
717 | ||
718 | outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); | |
719 | outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); | |
720 | } | |
721 | } | |
722 | ||
723 | /* Release the processor from reset | |
724 | */ | |
725 | static inline void | |
726 | fst_cpurelease(struct fst_card_info *card) | |
727 | { | |
728 | if (card->family == FST_FAMILY_TXU) { | |
729 | /* | |
730 | * Force posted writes to complete | |
731 | */ | |
732 | (void) readb(card->mem); | |
733 | ||
734 | /* | |
735 | * Release LRESET DO = 1 | |
736 | * Then release Local Hold, DO = 1 | |
737 | */ | |
738 | outw(0x040e, card->pci_conf + CNTRL_9054 + 2); | |
739 | outw(0x040f, card->pci_conf + CNTRL_9054 + 2); | |
740 | } else { | |
741 | (void) readb(card->ctlmem); | |
742 | } | |
743 | } | |
744 | ||
745 | /* Clear the cards interrupt flag | |
746 | */ | |
747 | static inline void | |
748 | fst_clear_intr(struct fst_card_info *card) | |
749 | { | |
750 | if (card->family == FST_FAMILY_TXU) { | |
751 | (void) readb(card->ctlmem); | |
752 | } else { | |
753 | /* Poke the appropriate PLX chip register (same as enabling interrupts) | |
754 | */ | |
755 | outw(0x0543, card->pci_conf + INTCSR_9052); | |
756 | } | |
757 | } | |
758 | ||
759 | /* Enable card interrupts | |
760 | */ | |
761 | static inline void | |
762 | fst_enable_intr(struct fst_card_info *card) | |
763 | { | |
764 | if (card->family == FST_FAMILY_TXU) { | |
765 | outl(0x0f0c0900, card->pci_conf + INTCSR_9054); | |
766 | } else { | |
767 | outw(0x0543, card->pci_conf + INTCSR_9052); | |
768 | } | |
769 | } | |
770 | ||
771 | /* Disable card interrupts | |
772 | */ | |
773 | static inline void | |
774 | fst_disable_intr(struct fst_card_info *card) | |
775 | { | |
776 | if (card->family == FST_FAMILY_TXU) { | |
777 | outl(0x00000000, card->pci_conf + INTCSR_9054); | |
778 | } else { | |
779 | outw(0x0000, card->pci_conf + INTCSR_9052); | |
780 | } | |
781 | } | |
782 | ||
783 | /* Process the result of trying to pass a received frame up the stack | |
784 | */ | |
785 | static void | |
786 | fst_process_rx_status(int rx_status, char *name) | |
787 | { | |
788 | switch (rx_status) { | |
789 | case NET_RX_SUCCESS: | |
790 | { | |
791 | /* | |
792 | * Nothing to do here | |
793 | */ | |
794 | break; | |
795 | } | |
1da177e4 LT |
796 | case NET_RX_DROP: |
797 | { | |
798 | dbg(DBG_ASS, "%s: Received packet dropped\n", name); | |
799 | break; | |
800 | } | |
801 | } | |
802 | } | |
803 | ||
804 | /* Initilaise DMA for PLX 9054 | |
805 | */ | |
806 | static inline void | |
807 | fst_init_dma(struct fst_card_info *card) | |
808 | { | |
809 | /* | |
810 | * This is only required for the PLX 9054 | |
811 | */ | |
812 | if (card->family == FST_FAMILY_TXU) { | |
813 | pci_set_master(card->device); | |
814 | outl(0x00020441, card->pci_conf + DMAMODE0); | |
815 | outl(0x00020441, card->pci_conf + DMAMODE1); | |
816 | outl(0x0, card->pci_conf + DMATHR); | |
817 | } | |
818 | } | |
819 | ||
820 | /* Tx dma complete interrupt | |
821 | */ | |
822 | static void | |
823 | fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, | |
824 | int len, int txpos) | |
825 | { | |
826 | struct net_device *dev = port_to_dev(port); | |
1da177e4 LT |
827 | |
828 | /* | |
829 | * Everything is now set, just tell the card to go | |
830 | */ | |
831 | dbg(DBG_TX, "fst_tx_dma_complete\n"); | |
832 | FST_WRB(card, txDescrRing[port->index][txpos].bits, | |
833 | DMA_OWN | TX_STP | TX_ENP); | |
198191c4 KH |
834 | dev->stats.tx_packets++; |
835 | dev->stats.tx_bytes += len; | |
1da177e4 LT |
836 | dev->trans_start = jiffies; |
837 | } | |
838 | ||
839 | /* | |
840 | * Mark it for our own raw sockets interface | |
841 | */ | |
ab611487 | 842 | static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
843 | { |
844 | skb->dev = dev; | |
459a98ed | 845 | skb_reset_mac_header(skb); |
1da177e4 LT |
846 | skb->pkt_type = PACKET_HOST; |
847 | return htons(ETH_P_CUST); | |
848 | } | |
849 | ||
850 | /* Rx dma complete interrupt | |
851 | */ | |
852 | static void | |
853 | fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, | |
854 | int len, struct sk_buff *skb, int rxp) | |
855 | { | |
856 | struct net_device *dev = port_to_dev(port); | |
1da177e4 LT |
857 | int pi; |
858 | int rx_status; | |
859 | ||
860 | dbg(DBG_TX, "fst_rx_dma_complete\n"); | |
861 | pi = port->index; | |
862 | memcpy(skb_put(skb, len), card->rx_dma_handle_host, len); | |
863 | ||
864 | /* Reset buffer descriptor */ | |
865 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
866 | ||
867 | /* Update stats */ | |
198191c4 KH |
868 | dev->stats.rx_packets++; |
869 | dev->stats.rx_bytes += len; | |
1da177e4 LT |
870 | |
871 | /* Push upstream */ | |
872 | dbg(DBG_RX, "Pushing the frame up the stack\n"); | |
873 | if (port->mode == FST_RAW) | |
874 | skb->protocol = farsync_type_trans(skb, dev); | |
875 | else | |
876 | skb->protocol = hdlc_type_trans(skb, dev); | |
877 | rx_status = netif_rx(skb); | |
878 | fst_process_rx_status(rx_status, port_to_dev(port)->name); | |
879 | if (rx_status == NET_RX_DROP) | |
198191c4 | 880 | dev->stats.rx_dropped++; |
1da177e4 LT |
881 | } |
882 | ||
883 | /* | |
884 | * Receive a frame through the DMA | |
885 | */ | |
886 | static inline void | |
887 | fst_rx_dma(struct fst_card_info *card, unsigned char *skb, | |
888 | unsigned char *mem, int len) | |
889 | { | |
890 | /* | |
891 | * This routine will setup the DMA and start it | |
892 | */ | |
893 | ||
894 | dbg(DBG_RX, "In fst_rx_dma %p %p %d\n", skb, mem, len); | |
895 | if (card->dmarx_in_progress) { | |
896 | dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n"); | |
897 | } | |
898 | ||
899 | outl((unsigned long) skb, card->pci_conf + DMAPADR0); /* Copy to here */ | |
900 | outl((unsigned long) mem, card->pci_conf + DMALADR0); /* from here */ | |
901 | outl(len, card->pci_conf + DMASIZ0); /* for this length */ | |
902 | outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */ | |
903 | ||
904 | /* | |
905 | * We use the dmarx_in_progress flag to flag the channel as busy | |
906 | */ | |
907 | card->dmarx_in_progress = 1; | |
908 | outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */ | |
909 | } | |
910 | ||
911 | /* | |
912 | * Send a frame through the DMA | |
913 | */ | |
914 | static inline void | |
915 | fst_tx_dma(struct fst_card_info *card, unsigned char *skb, | |
916 | unsigned char *mem, int len) | |
917 | { | |
918 | /* | |
919 | * This routine will setup the DMA and start it. | |
920 | */ | |
921 | ||
922 | dbg(DBG_TX, "In fst_tx_dma %p %p %d\n", skb, mem, len); | |
923 | if (card->dmatx_in_progress) { | |
924 | dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n"); | |
925 | } | |
926 | ||
927 | outl((unsigned long) skb, card->pci_conf + DMAPADR1); /* Copy from here */ | |
928 | outl((unsigned long) mem, card->pci_conf + DMALADR1); /* to here */ | |
929 | outl(len, card->pci_conf + DMASIZ1); /* for this length */ | |
930 | outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */ | |
931 | ||
932 | /* | |
933 | * We use the dmatx_in_progress to flag the channel as busy | |
934 | */ | |
935 | card->dmatx_in_progress = 1; | |
936 | outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */ | |
937 | } | |
938 | ||
939 | /* Issue a Mailbox command for a port. | |
940 | * Note we issue them on a fire and forget basis, not expecting to see an | |
941 | * error and not waiting for completion. | |
942 | */ | |
943 | static void | |
944 | fst_issue_cmd(struct fst_port_info *port, unsigned short cmd) | |
945 | { | |
946 | struct fst_card_info *card; | |
947 | unsigned short mbval; | |
948 | unsigned long flags; | |
949 | int safety; | |
950 | ||
951 | card = port->card; | |
952 | spin_lock_irqsave(&card->card_lock, flags); | |
953 | mbval = FST_RDW(card, portMailbox[port->index][0]); | |
954 | ||
955 | safety = 0; | |
956 | /* Wait for any previous command to complete */ | |
957 | while (mbval > NAK) { | |
958 | spin_unlock_irqrestore(&card->card_lock, flags); | |
3173c890 | 959 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
960 | spin_lock_irqsave(&card->card_lock, flags); |
961 | ||
962 | if (++safety > 2000) { | |
963 | printk_err("Mailbox safety timeout\n"); | |
964 | break; | |
965 | } | |
966 | ||
967 | mbval = FST_RDW(card, portMailbox[port->index][0]); | |
968 | } | |
969 | if (safety > 0) { | |
970 | dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety); | |
971 | } | |
972 | if (mbval == NAK) { | |
973 | dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n"); | |
974 | } | |
975 | ||
976 | FST_WRW(card, portMailbox[port->index][0], cmd); | |
977 | ||
978 | if (cmd == ABORTTX || cmd == STARTPORT) { | |
979 | port->txpos = 0; | |
980 | port->txipos = 0; | |
981 | port->start = 0; | |
982 | } | |
983 | ||
984 | spin_unlock_irqrestore(&card->card_lock, flags); | |
985 | } | |
986 | ||
987 | /* Port output signals control | |
988 | */ | |
989 | static inline void | |
990 | fst_op_raise(struct fst_port_info *port, unsigned int outputs) | |
991 | { | |
992 | outputs |= FST_RDL(port->card, v24OpSts[port->index]); | |
993 | FST_WRL(port->card, v24OpSts[port->index], outputs); | |
994 | ||
995 | if (port->run) | |
996 | fst_issue_cmd(port, SETV24O); | |
997 | } | |
998 | ||
999 | static inline void | |
1000 | fst_op_lower(struct fst_port_info *port, unsigned int outputs) | |
1001 | { | |
1002 | outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]); | |
1003 | FST_WRL(port->card, v24OpSts[port->index], outputs); | |
1004 | ||
1005 | if (port->run) | |
1006 | fst_issue_cmd(port, SETV24O); | |
1007 | } | |
1008 | ||
1009 | /* | |
1010 | * Setup port Rx buffers | |
1011 | */ | |
1012 | static void | |
1013 | fst_rx_config(struct fst_port_info *port) | |
1014 | { | |
1015 | int i; | |
1016 | int pi; | |
1017 | unsigned int offset; | |
1018 | unsigned long flags; | |
1019 | struct fst_card_info *card; | |
1020 | ||
1021 | pi = port->index; | |
1022 | card = port->card; | |
1023 | spin_lock_irqsave(&card->card_lock, flags); | |
1024 | for (i = 0; i < NUM_RX_BUFFER; i++) { | |
1025 | offset = BUF_OFFSET(rxBuffer[pi][i][0]); | |
1026 | ||
1027 | FST_WRW(card, rxDescrRing[pi][i].ladr, (u16) offset); | |
1028 | FST_WRB(card, rxDescrRing[pi][i].hadr, (u8) (offset >> 16)); | |
1029 | FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER)); | |
1030 | FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER); | |
1031 | FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN); | |
1032 | } | |
1033 | port->rxpos = 0; | |
1034 | spin_unlock_irqrestore(&card->card_lock, flags); | |
1035 | } | |
1036 | ||
1037 | /* | |
1038 | * Setup port Tx buffers | |
1039 | */ | |
1040 | static void | |
1041 | fst_tx_config(struct fst_port_info *port) | |
1042 | { | |
1043 | int i; | |
1044 | int pi; | |
1045 | unsigned int offset; | |
1046 | unsigned long flags; | |
1047 | struct fst_card_info *card; | |
1048 | ||
1049 | pi = port->index; | |
1050 | card = port->card; | |
1051 | spin_lock_irqsave(&card->card_lock, flags); | |
1052 | for (i = 0; i < NUM_TX_BUFFER; i++) { | |
1053 | offset = BUF_OFFSET(txBuffer[pi][i][0]); | |
1054 | ||
1055 | FST_WRW(card, txDescrRing[pi][i].ladr, (u16) offset); | |
1056 | FST_WRB(card, txDescrRing[pi][i].hadr, (u8) (offset >> 16)); | |
1057 | FST_WRW(card, txDescrRing[pi][i].bcnt, 0); | |
1058 | FST_WRB(card, txDescrRing[pi][i].bits, 0); | |
1059 | } | |
1060 | port->txpos = 0; | |
1061 | port->txipos = 0; | |
1062 | port->start = 0; | |
1063 | spin_unlock_irqrestore(&card->card_lock, flags); | |
1064 | } | |
1065 | ||
1066 | /* TE1 Alarm change interrupt event | |
1067 | */ | |
1068 | static void | |
1069 | fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port) | |
1070 | { | |
1071 | u8 los; | |
1072 | u8 rra; | |
1073 | u8 ais; | |
1074 | ||
1075 | los = FST_RDB(card, suStatus.lossOfSignal); | |
1076 | rra = FST_RDB(card, suStatus.receiveRemoteAlarm); | |
1077 | ais = FST_RDB(card, suStatus.alarmIndicationSignal); | |
1078 | ||
1079 | if (los) { | |
1080 | /* | |
1081 | * Lost the link | |
1082 | */ | |
1083 | if (netif_carrier_ok(port_to_dev(port))) { | |
1084 | dbg(DBG_INTR, "Net carrier off\n"); | |
1085 | netif_carrier_off(port_to_dev(port)); | |
1086 | } | |
1087 | } else { | |
1088 | /* | |
1089 | * Link available | |
1090 | */ | |
1091 | if (!netif_carrier_ok(port_to_dev(port))) { | |
1092 | dbg(DBG_INTR, "Net carrier on\n"); | |
1093 | netif_carrier_on(port_to_dev(port)); | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | if (los) | |
1098 | dbg(DBG_INTR, "Assert LOS Alarm\n"); | |
1099 | else | |
1100 | dbg(DBG_INTR, "De-assert LOS Alarm\n"); | |
1101 | if (rra) | |
1102 | dbg(DBG_INTR, "Assert RRA Alarm\n"); | |
1103 | else | |
1104 | dbg(DBG_INTR, "De-assert RRA Alarm\n"); | |
1105 | ||
1106 | if (ais) | |
1107 | dbg(DBG_INTR, "Assert AIS Alarm\n"); | |
1108 | else | |
1109 | dbg(DBG_INTR, "De-assert AIS Alarm\n"); | |
1110 | } | |
1111 | ||
1112 | /* Control signal change interrupt event | |
1113 | */ | |
1114 | static void | |
1115 | fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port) | |
1116 | { | |
1117 | int signals; | |
1118 | ||
1119 | signals = FST_RDL(card, v24DebouncedSts[port->index]); | |
1120 | ||
1121 | if (signals & (((port->hwif == X21) || (port->hwif == X21D)) | |
1122 | ? IPSTS_INDICATE : IPSTS_DCD)) { | |
1123 | if (!netif_carrier_ok(port_to_dev(port))) { | |
1124 | dbg(DBG_INTR, "DCD active\n"); | |
1125 | netif_carrier_on(port_to_dev(port)); | |
1126 | } | |
1127 | } else { | |
1128 | if (netif_carrier_ok(port_to_dev(port))) { | |
1129 | dbg(DBG_INTR, "DCD lost\n"); | |
1130 | netif_carrier_off(port_to_dev(port)); | |
1131 | } | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | /* Log Rx Errors | |
1136 | */ | |
1137 | static void | |
1138 | fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port, | |
1139 | unsigned char dmabits, int rxp, unsigned short len) | |
1140 | { | |
1141 | struct net_device *dev = port_to_dev(port); | |
1da177e4 | 1142 | |
198191c4 | 1143 | /* |
1da177e4 LT |
1144 | * Increment the appropriate error counter |
1145 | */ | |
198191c4 | 1146 | dev->stats.rx_errors++; |
1da177e4 | 1147 | if (dmabits & RX_OFLO) { |
198191c4 | 1148 | dev->stats.rx_fifo_errors++; |
1da177e4 LT |
1149 | dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n", |
1150 | card->card_no, port->index, rxp); | |
1151 | } | |
1152 | if (dmabits & RX_CRC) { | |
198191c4 | 1153 | dev->stats.rx_crc_errors++; |
1da177e4 LT |
1154 | dbg(DBG_ASS, "Rx crc error on card %d port %d\n", |
1155 | card->card_no, port->index); | |
1156 | } | |
1157 | if (dmabits & RX_FRAM) { | |
198191c4 | 1158 | dev->stats.rx_frame_errors++; |
1da177e4 LT |
1159 | dbg(DBG_ASS, "Rx frame error on card %d port %d\n", |
1160 | card->card_no, port->index); | |
1161 | } | |
1162 | if (dmabits == (RX_STP | RX_ENP)) { | |
198191c4 | 1163 | dev->stats.rx_length_errors++; |
1da177e4 LT |
1164 | dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n", |
1165 | len, card->card_no, port->index); | |
1166 | } | |
1167 | } | |
1168 | ||
1169 | /* Rx Error Recovery | |
1170 | */ | |
1171 | static void | |
1172 | fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port, | |
1173 | unsigned char dmabits, int rxp, unsigned short len) | |
1174 | { | |
1175 | int i; | |
1176 | int pi; | |
1177 | ||
1178 | pi = port->index; | |
1179 | /* | |
1180 | * Discard buffer descriptors until we see the start of the | |
1181 | * next frame. Note that for long frames this could be in | |
1182 | * a subsequent interrupt. | |
1183 | */ | |
1184 | i = 0; | |
1185 | while ((dmabits & (DMA_OWN | RX_STP)) == 0) { | |
1186 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
1187 | rxp = (rxp+1) % NUM_RX_BUFFER; | |
1188 | if (++i > NUM_RX_BUFFER) { | |
1189 | dbg(DBG_ASS, "intr_rx: Discarding more bufs" | |
1190 | " than we have\n"); | |
1191 | break; | |
1192 | } | |
1193 | dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); | |
1194 | dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits); | |
1195 | } | |
1196 | dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i); | |
1197 | ||
1198 | /* Discard the terminal buffer */ | |
1199 | if (!(dmabits & DMA_OWN)) { | |
1200 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
1201 | rxp = (rxp+1) % NUM_RX_BUFFER; | |
1202 | } | |
1203 | port->rxpos = rxp; | |
1204 | return; | |
1205 | ||
1206 | } | |
1207 | ||
1208 | /* Rx complete interrupt | |
1209 | */ | |
1210 | static void | |
1211 | fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port) | |
1212 | { | |
1213 | unsigned char dmabits; | |
1214 | int pi; | |
1215 | int rxp; | |
1216 | int rx_status; | |
1217 | unsigned short len; | |
1218 | struct sk_buff *skb; | |
1219 | struct net_device *dev = port_to_dev(port); | |
1da177e4 LT |
1220 | |
1221 | /* Check we have a buffer to process */ | |
1222 | pi = port->index; | |
1223 | rxp = port->rxpos; | |
1224 | dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); | |
1225 | if (dmabits & DMA_OWN) { | |
1226 | dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n", | |
1227 | pi, rxp); | |
1228 | return; | |
1229 | } | |
1230 | if (card->dmarx_in_progress) { | |
1231 | return; | |
1232 | } | |
1233 | ||
1234 | /* Get buffer length */ | |
1235 | len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt); | |
1236 | /* Discard the CRC */ | |
1237 | len -= 2; | |
1238 | if (len == 0) { | |
1239 | /* | |
1240 | * This seems to happen on the TE1 interface sometimes | |
1241 | * so throw the frame away and log the event. | |
1242 | */ | |
1243 | printk_err("Frame received with 0 length. Card %d Port %d\n", | |
1244 | card->card_no, port->index); | |
1245 | /* Return descriptor to card */ | |
1246 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
1247 | ||
1248 | rxp = (rxp+1) % NUM_RX_BUFFER; | |
1249 | port->rxpos = rxp; | |
1250 | return; | |
1251 | } | |
1252 | ||
1253 | /* Check buffer length and for other errors. We insist on one packet | |
1254 | * in one buffer. This simplifies things greatly and since we've | |
1255 | * allocated 8K it shouldn't be a real world limitation | |
1256 | */ | |
1257 | dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len); | |
1258 | if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) { | |
1259 | fst_log_rx_error(card, port, dmabits, rxp, len); | |
1260 | fst_recover_rx_error(card, port, dmabits, rxp, len); | |
1261 | return; | |
1262 | } | |
1263 | ||
1264 | /* Allocate SKB */ | |
1265 | if ((skb = dev_alloc_skb(len)) == NULL) { | |
1266 | dbg(DBG_RX, "intr_rx: can't allocate buffer\n"); | |
1267 | ||
198191c4 | 1268 | dev->stats.rx_dropped++; |
1da177e4 LT |
1269 | |
1270 | /* Return descriptor to card */ | |
1271 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
1272 | ||
1273 | rxp = (rxp+1) % NUM_RX_BUFFER; | |
1274 | port->rxpos = rxp; | |
1275 | return; | |
1276 | } | |
1277 | ||
1278 | /* | |
1279 | * We know the length we need to receive, len. | |
1280 | * It's not worth using the DMA for reads of less than | |
1281 | * FST_MIN_DMA_LEN | |
1282 | */ | |
1283 | ||
1284 | if ((len < FST_MIN_DMA_LEN) || (card->family == FST_FAMILY_TXP)) { | |
1285 | memcpy_fromio(skb_put(skb, len), | |
1286 | card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]), | |
1287 | len); | |
1288 | ||
1289 | /* Reset buffer descriptor */ | |
1290 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
1291 | ||
1292 | /* Update stats */ | |
198191c4 KH |
1293 | dev->stats.rx_packets++; |
1294 | dev->stats.rx_bytes += len; | |
1da177e4 LT |
1295 | |
1296 | /* Push upstream */ | |
1297 | dbg(DBG_RX, "Pushing frame up the stack\n"); | |
1298 | if (port->mode == FST_RAW) | |
1299 | skb->protocol = farsync_type_trans(skb, dev); | |
1300 | else | |
1301 | skb->protocol = hdlc_type_trans(skb, dev); | |
1302 | rx_status = netif_rx(skb); | |
1303 | fst_process_rx_status(rx_status, port_to_dev(port)->name); | |
198191c4 KH |
1304 | if (rx_status == NET_RX_DROP) |
1305 | dev->stats.rx_dropped++; | |
1da177e4 LT |
1306 | } else { |
1307 | card->dma_skb_rx = skb; | |
1308 | card->dma_port_rx = port; | |
1309 | card->dma_len_rx = len; | |
1310 | card->dma_rxpos = rxp; | |
1311 | fst_rx_dma(card, (char *) card->rx_dma_handle_card, | |
1312 | (char *) BUF_OFFSET(rxBuffer[pi][rxp][0]), len); | |
1313 | } | |
1314 | if (rxp != port->rxpos) { | |
1315 | dbg(DBG_ASS, "About to increment rxpos by more than 1\n"); | |
1316 | dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos); | |
1317 | } | |
1318 | rxp = (rxp+1) % NUM_RX_BUFFER; | |
1319 | port->rxpos = rxp; | |
1320 | } | |
1321 | ||
1322 | /* | |
1323 | * The bottom halfs to the ISR | |
1324 | * | |
1325 | */ | |
1326 | ||
1327 | static void | |
1328 | do_bottom_half_tx(struct fst_card_info *card) | |
1329 | { | |
1330 | struct fst_port_info *port; | |
1331 | int pi; | |
1332 | int txq_length; | |
1333 | struct sk_buff *skb; | |
1334 | unsigned long flags; | |
1335 | struct net_device *dev; | |
1da177e4 LT |
1336 | |
1337 | /* | |
1338 | * Find a free buffer for the transmit | |
1339 | * Step through each port on this card | |
1340 | */ | |
1341 | ||
1342 | dbg(DBG_TX, "do_bottom_half_tx\n"); | |
1343 | for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { | |
1344 | if (!port->run) | |
1345 | continue; | |
1346 | ||
198191c4 KH |
1347 | dev = port_to_dev(port); |
1348 | while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) & | |
1349 | DMA_OWN) | |
1350 | && !(card->dmatx_in_progress)) { | |
1da177e4 LT |
1351 | /* |
1352 | * There doesn't seem to be a txdone event per-se | |
1353 | * We seem to have to deduce it, by checking the DMA_OWN | |
1354 | * bit on the next buffer we think we can use | |
1355 | */ | |
1356 | spin_lock_irqsave(&card->card_lock, flags); | |
1357 | if ((txq_length = port->txqe - port->txqs) < 0) { | |
1358 | /* | |
1359 | * This is the case where one has wrapped and the | |
1360 | * maths gives us a negative number | |
1361 | */ | |
1362 | txq_length = txq_length + FST_TXQ_DEPTH; | |
1363 | } | |
1364 | spin_unlock_irqrestore(&card->card_lock, flags); | |
1365 | if (txq_length > 0) { | |
1366 | /* | |
1367 | * There is something to send | |
1368 | */ | |
1369 | spin_lock_irqsave(&card->card_lock, flags); | |
1370 | skb = port->txq[port->txqs]; | |
1371 | port->txqs++; | |
1372 | if (port->txqs == FST_TXQ_DEPTH) { | |
1373 | port->txqs = 0; | |
1374 | } | |
1375 | spin_unlock_irqrestore(&card->card_lock, flags); | |
1376 | /* | |
1377 | * copy the data and set the required indicators on the | |
1378 | * card. | |
1379 | */ | |
1380 | FST_WRW(card, txDescrRing[pi][port->txpos].bcnt, | |
1381 | cnv_bcnt(skb->len)); | |
1382 | if ((skb->len < FST_MIN_DMA_LEN) | |
1383 | || (card->family == FST_FAMILY_TXP)) { | |
1384 | /* Enqueue the packet with normal io */ | |
1385 | memcpy_toio(card->mem + | |
1386 | BUF_OFFSET(txBuffer[pi] | |
1387 | [port-> | |
1388 | txpos][0]), | |
1389 | skb->data, skb->len); | |
1390 | FST_WRB(card, | |
1391 | txDescrRing[pi][port->txpos]. | |
1392 | bits, | |
1393 | DMA_OWN | TX_STP | TX_ENP); | |
198191c4 KH |
1394 | dev->stats.tx_packets++; |
1395 | dev->stats.tx_bytes += skb->len; | |
1da177e4 LT |
1396 | dev->trans_start = jiffies; |
1397 | } else { | |
1398 | /* Or do it through dma */ | |
1399 | memcpy(card->tx_dma_handle_host, | |
1400 | skb->data, skb->len); | |
1401 | card->dma_port_tx = port; | |
1402 | card->dma_len_tx = skb->len; | |
1403 | card->dma_txpos = port->txpos; | |
1404 | fst_tx_dma(card, | |
1405 | (char *) card-> | |
1406 | tx_dma_handle_card, | |
1407 | (char *) | |
1408 | BUF_OFFSET(txBuffer[pi] | |
1409 | [port->txpos][0]), | |
1410 | skb->len); | |
1411 | } | |
1412 | if (++port->txpos >= NUM_TX_BUFFER) | |
1413 | port->txpos = 0; | |
1414 | /* | |
1415 | * If we have flow control on, can we now release it? | |
1416 | */ | |
1417 | if (port->start) { | |
1418 | if (txq_length < fst_txq_low) { | |
1419 | netif_wake_queue(port_to_dev | |
1420 | (port)); | |
1421 | port->start = 0; | |
1422 | } | |
1423 | } | |
1424 | dev_kfree_skb(skb); | |
1425 | } else { | |
1426 | /* | |
1427 | * Nothing to send so break out of the while loop | |
1428 | */ | |
1429 | break; | |
1430 | } | |
1431 | } | |
1432 | } | |
1433 | } | |
1434 | ||
1435 | static void | |
1436 | do_bottom_half_rx(struct fst_card_info *card) | |
1437 | { | |
1438 | struct fst_port_info *port; | |
1439 | int pi; | |
1440 | int rx_count = 0; | |
1441 | ||
1442 | /* Check for rx completions on all ports on this card */ | |
1443 | dbg(DBG_RX, "do_bottom_half_rx\n"); | |
1444 | for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { | |
1445 | if (!port->run) | |
1446 | continue; | |
1447 | ||
1448 | while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits) | |
1449 | & DMA_OWN) && !(card->dmarx_in_progress)) { | |
1450 | if (rx_count > fst_max_reads) { | |
1451 | /* | |
1452 | * Don't spend forever in receive processing | |
1453 | * Schedule another event | |
1454 | */ | |
1455 | fst_q_work_item(&fst_work_intq, card->card_no); | |
1456 | tasklet_schedule(&fst_int_task); | |
1457 | break; /* Leave the loop */ | |
1458 | } | |
1459 | fst_intr_rx(card, port); | |
1460 | rx_count++; | |
1461 | } | |
1462 | } | |
1463 | } | |
1464 | ||
1465 | /* | |
1466 | * The interrupt service routine | |
1467 | * Dev_id is our fst_card_info pointer | |
1468 | */ | |
7665a089 | 1469 | static irqreturn_t |
28fc1f5a | 1470 | fst_intr(int dummy, void *dev_id) |
1da177e4 | 1471 | { |
28fc1f5a | 1472 | struct fst_card_info *card = dev_id; |
1da177e4 LT |
1473 | struct fst_port_info *port; |
1474 | int rdidx; /* Event buffer indices */ | |
1475 | int wridx; | |
1476 | int event; /* Actual event for processing */ | |
1477 | unsigned int dma_intcsr = 0; | |
1478 | unsigned int do_card_interrupt; | |
1479 | unsigned int int_retry_count; | |
1480 | ||
1da177e4 LT |
1481 | /* |
1482 | * Check to see if the interrupt was for this card | |
1483 | * return if not | |
1484 | * Note that the call to clear the interrupt is important | |
1485 | */ | |
28fc1f5a | 1486 | dbg(DBG_INTR, "intr: %d %p\n", card->irq, card); |
1da177e4 LT |
1487 | if (card->state != FST_RUNNING) { |
1488 | printk_err | |
1489 | ("Interrupt received for card %d in a non running state (%d)\n", | |
1490 | card->card_no, card->state); | |
1491 | ||
1492 | /* | |
1493 | * It is possible to really be running, i.e. we have re-loaded | |
1494 | * a running card | |
1495 | * Clear and reprime the interrupt source | |
1496 | */ | |
1497 | fst_clear_intr(card); | |
1498 | return IRQ_HANDLED; | |
1499 | } | |
1500 | ||
1501 | /* Clear and reprime the interrupt source */ | |
1502 | fst_clear_intr(card); | |
1503 | ||
1504 | /* | |
1505 | * Is the interrupt for this card (handshake == 1) | |
1506 | */ | |
1507 | do_card_interrupt = 0; | |
1508 | if (FST_RDB(card, interruptHandshake) == 1) { | |
1509 | do_card_interrupt += FST_CARD_INT; | |
1510 | /* Set the software acknowledge */ | |
1511 | FST_WRB(card, interruptHandshake, 0xEE); | |
1512 | } | |
1513 | if (card->family == FST_FAMILY_TXU) { | |
1514 | /* | |
1515 | * Is it a DMA Interrupt | |
1516 | */ | |
1517 | dma_intcsr = inl(card->pci_conf + INTCSR_9054); | |
1518 | if (dma_intcsr & 0x00200000) { | |
1519 | /* | |
1520 | * DMA Channel 0 (Rx transfer complete) | |
1521 | */ | |
1522 | dbg(DBG_RX, "DMA Rx xfer complete\n"); | |
1523 | outb(0x8, card->pci_conf + DMACSR0); | |
1524 | fst_rx_dma_complete(card, card->dma_port_rx, | |
1525 | card->dma_len_rx, card->dma_skb_rx, | |
1526 | card->dma_rxpos); | |
1527 | card->dmarx_in_progress = 0; | |
1528 | do_card_interrupt += FST_RX_DMA_INT; | |
1529 | } | |
1530 | if (dma_intcsr & 0x00400000) { | |
1531 | /* | |
1532 | * DMA Channel 1 (Tx transfer complete) | |
1533 | */ | |
1534 | dbg(DBG_TX, "DMA Tx xfer complete\n"); | |
1535 | outb(0x8, card->pci_conf + DMACSR1); | |
1536 | fst_tx_dma_complete(card, card->dma_port_tx, | |
1537 | card->dma_len_tx, card->dma_txpos); | |
1538 | card->dmatx_in_progress = 0; | |
1539 | do_card_interrupt += FST_TX_DMA_INT; | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | /* | |
1544 | * Have we been missing Interrupts | |
1545 | */ | |
1546 | int_retry_count = FST_RDL(card, interruptRetryCount); | |
1547 | if (int_retry_count) { | |
1548 | dbg(DBG_ASS, "Card %d int_retry_count is %d\n", | |
1549 | card->card_no, int_retry_count); | |
1550 | FST_WRL(card, interruptRetryCount, 0); | |
1551 | } | |
1552 | ||
1553 | if (!do_card_interrupt) { | |
1554 | return IRQ_HANDLED; | |
1555 | } | |
1556 | ||
1557 | /* Scehdule the bottom half of the ISR */ | |
1558 | fst_q_work_item(&fst_work_intq, card->card_no); | |
1559 | tasklet_schedule(&fst_int_task); | |
1560 | ||
1561 | /* Drain the event queue */ | |
1562 | rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f; | |
1563 | wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f; | |
1564 | while (rdidx != wridx) { | |
1565 | event = FST_RDB(card, interruptEvent.evntbuff[rdidx]); | |
1566 | port = &card->ports[event & 0x03]; | |
1567 | ||
1568 | dbg(DBG_INTR, "Processing Interrupt event: %x\n", event); | |
1569 | ||
1570 | switch (event) { | |
1571 | case TE1_ALMA: | |
1572 | dbg(DBG_INTR, "TE1 Alarm intr\n"); | |
1573 | if (port->run) | |
1574 | fst_intr_te1_alarm(card, port); | |
1575 | break; | |
1576 | ||
1577 | case CTLA_CHG: | |
1578 | case CTLB_CHG: | |
1579 | case CTLC_CHG: | |
1580 | case CTLD_CHG: | |
1581 | if (port->run) | |
1582 | fst_intr_ctlchg(card, port); | |
1583 | break; | |
1584 | ||
1585 | case ABTA_SENT: | |
1586 | case ABTB_SENT: | |
1587 | case ABTC_SENT: | |
1588 | case ABTD_SENT: | |
1589 | dbg(DBG_TX, "Abort complete port %d\n", port->index); | |
1590 | break; | |
1591 | ||
1592 | case TXA_UNDF: | |
1593 | case TXB_UNDF: | |
1594 | case TXC_UNDF: | |
1595 | case TXD_UNDF: | |
1596 | /* Difficult to see how we'd get this given that we | |
1597 | * always load up the entire packet for DMA. | |
1598 | */ | |
1599 | dbg(DBG_TX, "Tx underflow port %d\n", port->index); | |
198191c4 KH |
1600 | port_to_dev(port)->stats.tx_errors++; |
1601 | port_to_dev(port)->stats.tx_fifo_errors++; | |
1da177e4 LT |
1602 | dbg(DBG_ASS, "Tx underflow on card %d port %d\n", |
1603 | card->card_no, port->index); | |
1604 | break; | |
1605 | ||
1606 | case INIT_CPLT: | |
1607 | dbg(DBG_INIT, "Card init OK intr\n"); | |
1608 | break; | |
1609 | ||
1610 | case INIT_FAIL: | |
1611 | dbg(DBG_INIT, "Card init FAILED intr\n"); | |
1612 | card->state = FST_IFAILED; | |
1613 | break; | |
1614 | ||
1615 | default: | |
1616 | printk_err("intr: unknown card event %d. ignored\n", | |
1617 | event); | |
1618 | break; | |
1619 | } | |
1620 | ||
1621 | /* Bump and wrap the index */ | |
1622 | if (++rdidx >= MAX_CIRBUFF) | |
1623 | rdidx = 0; | |
1624 | } | |
1625 | FST_WRB(card, interruptEvent.rdindex, rdidx); | |
1626 | return IRQ_HANDLED; | |
1627 | } | |
1628 | ||
1629 | /* Check that the shared memory configuration is one that we can handle | |
1630 | * and that some basic parameters are correct | |
1631 | */ | |
1632 | static void | |
1633 | check_started_ok(struct fst_card_info *card) | |
1634 | { | |
1635 | int i; | |
1636 | ||
1637 | /* Check structure version and end marker */ | |
1638 | if (FST_RDW(card, smcVersion) != SMC_VERSION) { | |
1639 | printk_err("Bad shared memory version %d expected %d\n", | |
1640 | FST_RDW(card, smcVersion), SMC_VERSION); | |
1641 | card->state = FST_BADVERSION; | |
1642 | return; | |
1643 | } | |
1644 | if (FST_RDL(card, endOfSmcSignature) != END_SIG) { | |
1645 | printk_err("Missing shared memory signature\n"); | |
1646 | card->state = FST_BADVERSION; | |
1647 | return; | |
1648 | } | |
1649 | /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */ | |
1650 | if ((i = FST_RDB(card, taskStatus)) == 0x01) { | |
1651 | card->state = FST_RUNNING; | |
1652 | } else if (i == 0xFF) { | |
1653 | printk_err("Firmware initialisation failed. Card halted\n"); | |
1654 | card->state = FST_HALTED; | |
1655 | return; | |
1656 | } else if (i != 0x00) { | |
1657 | printk_err("Unknown firmware status 0x%x\n", i); | |
1658 | card->state = FST_HALTED; | |
1659 | return; | |
1660 | } | |
1661 | ||
1662 | /* Finally check the number of ports reported by firmware against the | |
1663 | * number we assumed at card detection. Should never happen with | |
1664 | * existing firmware etc so we just report it for the moment. | |
1665 | */ | |
1666 | if (FST_RDL(card, numberOfPorts) != card->nports) { | |
1667 | printk_warn("Port count mismatch on card %d." | |
1668 | " Firmware thinks %d we say %d\n", card->card_no, | |
1669 | FST_RDL(card, numberOfPorts), card->nports); | |
1670 | } | |
1671 | } | |
1672 | ||
1673 | static int | |
1674 | set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port, | |
1675 | struct fstioc_info *info) | |
1676 | { | |
1677 | int err; | |
1678 | unsigned char my_framing; | |
1679 | ||
1680 | /* Set things according to the user set valid flags | |
1681 | * Several of the old options have been invalidated/replaced by the | |
1682 | * generic hdlc package. | |
1683 | */ | |
1684 | err = 0; | |
1685 | if (info->valid & FSTVAL_PROTO) { | |
1686 | if (info->proto == FST_RAW) | |
1687 | port->mode = FST_RAW; | |
1688 | else | |
1689 | port->mode = FST_GEN_HDLC; | |
1690 | } | |
1691 | ||
1692 | if (info->valid & FSTVAL_CABLE) | |
1693 | err = -EINVAL; | |
1694 | ||
1695 | if (info->valid & FSTVAL_SPEED) | |
1696 | err = -EINVAL; | |
1697 | ||
1698 | if (info->valid & FSTVAL_PHASE) | |
1699 | FST_WRB(card, portConfig[port->index].invertClock, | |
1700 | info->invertClock); | |
1701 | if (info->valid & FSTVAL_MODE) | |
1702 | FST_WRW(card, cardMode, info->cardMode); | |
1703 | if (info->valid & FSTVAL_TE1) { | |
1704 | FST_WRL(card, suConfig.dataRate, info->lineSpeed); | |
1705 | FST_WRB(card, suConfig.clocking, info->clockSource); | |
1706 | my_framing = FRAMING_E1; | |
1707 | if (info->framing == E1) | |
1708 | my_framing = FRAMING_E1; | |
1709 | if (info->framing == T1) | |
1710 | my_framing = FRAMING_T1; | |
1711 | if (info->framing == J1) | |
1712 | my_framing = FRAMING_J1; | |
1713 | FST_WRB(card, suConfig.framing, my_framing); | |
1714 | FST_WRB(card, suConfig.structure, info->structure); | |
1715 | FST_WRB(card, suConfig.interface, info->interface); | |
1716 | FST_WRB(card, suConfig.coding, info->coding); | |
1717 | FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut); | |
1718 | FST_WRB(card, suConfig.equalizer, info->equalizer); | |
1719 | FST_WRB(card, suConfig.transparentMode, info->transparentMode); | |
1720 | FST_WRB(card, suConfig.loopMode, info->loopMode); | |
1721 | FST_WRB(card, suConfig.range, info->range); | |
1722 | FST_WRB(card, suConfig.txBufferMode, info->txBufferMode); | |
1723 | FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode); | |
1724 | FST_WRB(card, suConfig.startingSlot, info->startingSlot); | |
1725 | FST_WRB(card, suConfig.losThreshold, info->losThreshold); | |
1726 | if (info->idleCode) | |
1727 | FST_WRB(card, suConfig.enableIdleCode, 1); | |
1728 | else | |
1729 | FST_WRB(card, suConfig.enableIdleCode, 0); | |
1730 | FST_WRB(card, suConfig.idleCode, info->idleCode); | |
1731 | #if FST_DEBUG | |
1732 | if (info->valid & FSTVAL_TE1) { | |
1733 | printk("Setting TE1 data\n"); | |
1734 | printk("Line Speed = %d\n", info->lineSpeed); | |
1735 | printk("Start slot = %d\n", info->startingSlot); | |
1736 | printk("Clock source = %d\n", info->clockSource); | |
1737 | printk("Framing = %d\n", my_framing); | |
1738 | printk("Structure = %d\n", info->structure); | |
1739 | printk("interface = %d\n", info->interface); | |
1740 | printk("Coding = %d\n", info->coding); | |
1741 | printk("Line build out = %d\n", info->lineBuildOut); | |
1742 | printk("Equaliser = %d\n", info->equalizer); | |
1743 | printk("Transparent mode = %d\n", | |
1744 | info->transparentMode); | |
1745 | printk("Loop mode = %d\n", info->loopMode); | |
1746 | printk("Range = %d\n", info->range); | |
1747 | printk("Tx Buffer mode = %d\n", info->txBufferMode); | |
1748 | printk("Rx Buffer mode = %d\n", info->rxBufferMode); | |
1749 | printk("LOS Threshold = %d\n", info->losThreshold); | |
1750 | printk("Idle Code = %d\n", info->idleCode); | |
1751 | } | |
1752 | #endif | |
1753 | } | |
1754 | #if FST_DEBUG | |
1755 | if (info->valid & FSTVAL_DEBUG) { | |
1756 | fst_debug_mask = info->debug; | |
1757 | } | |
1758 | #endif | |
1759 | ||
1760 | return err; | |
1761 | } | |
1762 | ||
1763 | static void | |
1764 | gather_conf_info(struct fst_card_info *card, struct fst_port_info *port, | |
1765 | struct fstioc_info *info) | |
1766 | { | |
1767 | int i; | |
1768 | ||
1769 | memset(info, 0, sizeof (struct fstioc_info)); | |
1770 | ||
1771 | i = port->index; | |
1772 | info->kernelVersion = LINUX_VERSION_CODE; | |
1773 | info->nports = card->nports; | |
1774 | info->type = card->type; | |
1775 | info->state = card->state; | |
1776 | info->proto = FST_GEN_HDLC; | |
1777 | info->index = i; | |
1778 | #if FST_DEBUG | |
1779 | info->debug = fst_debug_mask; | |
1780 | #endif | |
1781 | ||
1782 | /* Only mark information as valid if card is running. | |
1783 | * Copy the data anyway in case it is useful for diagnostics | |
1784 | */ | |
1785 | info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD) | |
1786 | #if FST_DEBUG | |
1787 | | FSTVAL_DEBUG | |
1788 | #endif | |
1789 | ; | |
1790 | ||
1791 | info->lineInterface = FST_RDW(card, portConfig[i].lineInterface); | |
1792 | info->internalClock = FST_RDB(card, portConfig[i].internalClock); | |
1793 | info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed); | |
1794 | info->invertClock = FST_RDB(card, portConfig[i].invertClock); | |
1795 | info->v24IpSts = FST_RDL(card, v24IpSts[i]); | |
1796 | info->v24OpSts = FST_RDL(card, v24OpSts[i]); | |
1797 | info->clockStatus = FST_RDW(card, clockStatus[i]); | |
1798 | info->cableStatus = FST_RDW(card, cableStatus); | |
1799 | info->cardMode = FST_RDW(card, cardMode); | |
1800 | info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion); | |
1801 | ||
1802 | /* | |
1803 | * The T2U can report cable presence for both A or B | |
1804 | * in bits 0 and 1 of cableStatus. See which port we are and | |
1805 | * do the mapping. | |
1806 | */ | |
1807 | if (card->family == FST_FAMILY_TXU) { | |
1808 | if (port->index == 0) { | |
1809 | /* | |
1810 | * Port A | |
1811 | */ | |
1812 | info->cableStatus = info->cableStatus & 1; | |
1813 | } else { | |
1814 | /* | |
1815 | * Port B | |
1816 | */ | |
1817 | info->cableStatus = info->cableStatus >> 1; | |
1818 | info->cableStatus = info->cableStatus & 1; | |
1819 | } | |
1820 | } | |
1821 | /* | |
1822 | * Some additional bits if we are TE1 | |
1823 | */ | |
1824 | if (card->type == FST_TYPE_TE1) { | |
1825 | info->lineSpeed = FST_RDL(card, suConfig.dataRate); | |
1826 | info->clockSource = FST_RDB(card, suConfig.clocking); | |
1827 | info->framing = FST_RDB(card, suConfig.framing); | |
1828 | info->structure = FST_RDB(card, suConfig.structure); | |
1829 | info->interface = FST_RDB(card, suConfig.interface); | |
1830 | info->coding = FST_RDB(card, suConfig.coding); | |
1831 | info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut); | |
1832 | info->equalizer = FST_RDB(card, suConfig.equalizer); | |
1833 | info->loopMode = FST_RDB(card, suConfig.loopMode); | |
1834 | info->range = FST_RDB(card, suConfig.range); | |
1835 | info->txBufferMode = FST_RDB(card, suConfig.txBufferMode); | |
1836 | info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode); | |
1837 | info->startingSlot = FST_RDB(card, suConfig.startingSlot); | |
1838 | info->losThreshold = FST_RDB(card, suConfig.losThreshold); | |
1839 | if (FST_RDB(card, suConfig.enableIdleCode)) | |
1840 | info->idleCode = FST_RDB(card, suConfig.idleCode); | |
1841 | else | |
1842 | info->idleCode = 0; | |
1843 | info->receiveBufferDelay = | |
1844 | FST_RDL(card, suStatus.receiveBufferDelay); | |
1845 | info->framingErrorCount = | |
1846 | FST_RDL(card, suStatus.framingErrorCount); | |
1847 | info->codeViolationCount = | |
1848 | FST_RDL(card, suStatus.codeViolationCount); | |
1849 | info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount); | |
1850 | info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation); | |
1851 | info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal); | |
1852 | info->receiveRemoteAlarm = | |
1853 | FST_RDB(card, suStatus.receiveRemoteAlarm); | |
1854 | info->alarmIndicationSignal = | |
1855 | FST_RDB(card, suStatus.alarmIndicationSignal); | |
1856 | } | |
1857 | } | |
1858 | ||
1859 | static int | |
1860 | fst_set_iface(struct fst_card_info *card, struct fst_port_info *port, | |
1861 | struct ifreq *ifr) | |
1862 | { | |
1863 | sync_serial_settings sync; | |
1864 | int i; | |
1865 | ||
1866 | if (ifr->ifr_settings.size != sizeof (sync)) { | |
1867 | return -ENOMEM; | |
1868 | } | |
1869 | ||
1870 | if (copy_from_user | |
1871 | (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof (sync))) { | |
1872 | return -EFAULT; | |
1873 | } | |
1874 | ||
1875 | if (sync.loopback) | |
1876 | return -EINVAL; | |
1877 | ||
1878 | i = port->index; | |
1879 | ||
1880 | switch (ifr->ifr_settings.type) { | |
1881 | case IF_IFACE_V35: | |
1882 | FST_WRW(card, portConfig[i].lineInterface, V35); | |
1883 | port->hwif = V35; | |
1884 | break; | |
1885 | ||
1886 | case IF_IFACE_V24: | |
1887 | FST_WRW(card, portConfig[i].lineInterface, V24); | |
1888 | port->hwif = V24; | |
1889 | break; | |
1890 | ||
1891 | case IF_IFACE_X21: | |
1892 | FST_WRW(card, portConfig[i].lineInterface, X21); | |
1893 | port->hwif = X21; | |
1894 | break; | |
1895 | ||
1896 | case IF_IFACE_X21D: | |
1897 | FST_WRW(card, portConfig[i].lineInterface, X21D); | |
1898 | port->hwif = X21D; | |
1899 | break; | |
1900 | ||
1901 | case IF_IFACE_T1: | |
1902 | FST_WRW(card, portConfig[i].lineInterface, T1); | |
1903 | port->hwif = T1; | |
1904 | break; | |
1905 | ||
1906 | case IF_IFACE_E1: | |
1907 | FST_WRW(card, portConfig[i].lineInterface, E1); | |
1908 | port->hwif = E1; | |
1909 | break; | |
1910 | ||
1911 | case IF_IFACE_SYNC_SERIAL: | |
1912 | break; | |
1913 | ||
1914 | default: | |
1915 | return -EINVAL; | |
1916 | } | |
1917 | ||
1918 | switch (sync.clock_type) { | |
1919 | case CLOCK_EXT: | |
1920 | FST_WRB(card, portConfig[i].internalClock, EXTCLK); | |
1921 | break; | |
1922 | ||
1923 | case CLOCK_INT: | |
1924 | FST_WRB(card, portConfig[i].internalClock, INTCLK); | |
1925 | break; | |
1926 | ||
1927 | default: | |
1928 | return -EINVAL; | |
1929 | } | |
1930 | FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate); | |
1931 | return 0; | |
1932 | } | |
1933 | ||
1934 | static int | |
1935 | fst_get_iface(struct fst_card_info *card, struct fst_port_info *port, | |
1936 | struct ifreq *ifr) | |
1937 | { | |
1938 | sync_serial_settings sync; | |
1939 | int i; | |
1940 | ||
1941 | /* First check what line type is set, we'll default to reporting X.21 | |
1942 | * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be | |
1943 | * changed | |
1944 | */ | |
1945 | switch (port->hwif) { | |
1946 | case E1: | |
1947 | ifr->ifr_settings.type = IF_IFACE_E1; | |
1948 | break; | |
1949 | case T1: | |
1950 | ifr->ifr_settings.type = IF_IFACE_T1; | |
1951 | break; | |
1952 | case V35: | |
1953 | ifr->ifr_settings.type = IF_IFACE_V35; | |
1954 | break; | |
1955 | case V24: | |
1956 | ifr->ifr_settings.type = IF_IFACE_V24; | |
1957 | break; | |
1958 | case X21D: | |
1959 | ifr->ifr_settings.type = IF_IFACE_X21D; | |
1960 | break; | |
1961 | case X21: | |
1962 | default: | |
1963 | ifr->ifr_settings.type = IF_IFACE_X21; | |
1964 | break; | |
1965 | } | |
1966 | if (ifr->ifr_settings.size == 0) { | |
1967 | return 0; /* only type requested */ | |
1968 | } | |
1969 | if (ifr->ifr_settings.size < sizeof (sync)) { | |
1970 | return -ENOMEM; | |
1971 | } | |
1972 | ||
1973 | i = port->index; | |
1974 | sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed); | |
1975 | /* Lucky card and linux use same encoding here */ | |
1976 | sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == | |
1977 | INTCLK ? CLOCK_INT : CLOCK_EXT; | |
1978 | sync.loopback = 0; | |
1979 | ||
1980 | if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof (sync))) { | |
1981 | return -EFAULT; | |
1982 | } | |
1983 | ||
1984 | ifr->ifr_settings.size = sizeof (sync); | |
1985 | return 0; | |
1986 | } | |
1987 | ||
1988 | static int | |
1989 | fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1990 | { | |
1991 | struct fst_card_info *card; | |
1992 | struct fst_port_info *port; | |
1993 | struct fstioc_write wrthdr; | |
1994 | struct fstioc_info info; | |
1995 | unsigned long flags; | |
5ffa6d7f | 1996 | void *buf; |
1da177e4 LT |
1997 | |
1998 | dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, ifr->ifr_data); | |
1999 | ||
2000 | port = dev_to_port(dev); | |
2001 | card = port->card; | |
2002 | ||
2003 | if (!capable(CAP_NET_ADMIN)) | |
2004 | return -EPERM; | |
2005 | ||
2006 | switch (cmd) { | |
2007 | case FSTCPURESET: | |
2008 | fst_cpureset(card); | |
2009 | card->state = FST_RESET; | |
2010 | return 0; | |
2011 | ||
2012 | case FSTCPURELEASE: | |
2013 | fst_cpurelease(card); | |
2014 | card->state = FST_STARTING; | |
2015 | return 0; | |
2016 | ||
2017 | case FSTWRITE: /* Code write (download) */ | |
2018 | ||
2019 | /* First copy in the header with the length and offset of data | |
2020 | * to write | |
2021 | */ | |
2022 | if (ifr->ifr_data == NULL) { | |
2023 | return -EINVAL; | |
2024 | } | |
2025 | if (copy_from_user(&wrthdr, ifr->ifr_data, | |
2026 | sizeof (struct fstioc_write))) { | |
2027 | return -EFAULT; | |
2028 | } | |
2029 | ||
2030 | /* Sanity check the parameters. We don't support partial writes | |
2031 | * when going over the top | |
2032 | */ | |
2033 | if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE | |
2034 | || wrthdr.size + wrthdr.offset > FST_MEMSIZE) { | |
2035 | return -ENXIO; | |
2036 | } | |
2037 | ||
5ffa6d7f AV |
2038 | /* Now copy the data to the card. */ |
2039 | ||
2040 | buf = kmalloc(wrthdr.size, GFP_KERNEL); | |
2041 | if (!buf) | |
2042 | return -ENOMEM; | |
2043 | ||
2044 | if (copy_from_user(buf, | |
1da177e4 LT |
2045 | ifr->ifr_data + sizeof (struct fstioc_write), |
2046 | wrthdr.size)) { | |
5ffa6d7f | 2047 | kfree(buf); |
1da177e4 LT |
2048 | return -EFAULT; |
2049 | } | |
2050 | ||
5ffa6d7f AV |
2051 | memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size); |
2052 | kfree(buf); | |
2053 | ||
1da177e4 LT |
2054 | /* Writes to the memory of a card in the reset state constitute |
2055 | * a download | |
2056 | */ | |
2057 | if (card->state == FST_RESET) { | |
2058 | card->state = FST_DOWNLOAD; | |
2059 | } | |
2060 | return 0; | |
2061 | ||
2062 | case FSTGETCONF: | |
2063 | ||
2064 | /* If card has just been started check the shared memory config | |
2065 | * version and marker | |
2066 | */ | |
2067 | if (card->state == FST_STARTING) { | |
2068 | check_started_ok(card); | |
2069 | ||
2070 | /* If everything checked out enable card interrupts */ | |
2071 | if (card->state == FST_RUNNING) { | |
2072 | spin_lock_irqsave(&card->card_lock, flags); | |
2073 | fst_enable_intr(card); | |
2074 | FST_WRB(card, interruptHandshake, 0xEE); | |
2075 | spin_unlock_irqrestore(&card->card_lock, flags); | |
2076 | } | |
2077 | } | |
2078 | ||
2079 | if (ifr->ifr_data == NULL) { | |
2080 | return -EINVAL; | |
2081 | } | |
2082 | ||
2083 | gather_conf_info(card, port, &info); | |
2084 | ||
2085 | if (copy_to_user(ifr->ifr_data, &info, sizeof (info))) { | |
2086 | return -EFAULT; | |
2087 | } | |
2088 | return 0; | |
2089 | ||
2090 | case FSTSETCONF: | |
2091 | ||
2092 | /* | |
2093 | * Most of the settings have been moved to the generic ioctls | |
2094 | * this just covers debug and board ident now | |
2095 | */ | |
2096 | ||
2097 | if (card->state != FST_RUNNING) { | |
2098 | printk_err | |
2099 | ("Attempt to configure card %d in non-running state (%d)\n", | |
2100 | card->card_no, card->state); | |
2101 | return -EIO; | |
2102 | } | |
2103 | if (copy_from_user(&info, ifr->ifr_data, sizeof (info))) { | |
2104 | return -EFAULT; | |
2105 | } | |
2106 | ||
2107 | return set_conf_from_info(card, port, &info); | |
2108 | ||
2109 | case SIOCWANDEV: | |
2110 | switch (ifr->ifr_settings.type) { | |
2111 | case IF_GET_IFACE: | |
2112 | return fst_get_iface(card, port, ifr); | |
2113 | ||
2114 | case IF_IFACE_SYNC_SERIAL: | |
2115 | case IF_IFACE_V35: | |
2116 | case IF_IFACE_V24: | |
2117 | case IF_IFACE_X21: | |
2118 | case IF_IFACE_X21D: | |
2119 | case IF_IFACE_T1: | |
2120 | case IF_IFACE_E1: | |
2121 | return fst_set_iface(card, port, ifr); | |
2122 | ||
2123 | case IF_PROTO_RAW: | |
2124 | port->mode = FST_RAW; | |
2125 | return 0; | |
2126 | ||
2127 | case IF_GET_PROTO: | |
2128 | if (port->mode == FST_RAW) { | |
2129 | ifr->ifr_settings.type = IF_PROTO_RAW; | |
2130 | return 0; | |
2131 | } | |
2132 | return hdlc_ioctl(dev, ifr, cmd); | |
2133 | ||
2134 | default: | |
2135 | port->mode = FST_GEN_HDLC; | |
2136 | dbg(DBG_IOCTL, "Passing this type to hdlc %x\n", | |
2137 | ifr->ifr_settings.type); | |
2138 | return hdlc_ioctl(dev, ifr, cmd); | |
2139 | } | |
2140 | ||
2141 | default: | |
2142 | /* Not one of ours. Pass through to HDLC package */ | |
2143 | return hdlc_ioctl(dev, ifr, cmd); | |
2144 | } | |
2145 | } | |
2146 | ||
2147 | static void | |
2148 | fst_openport(struct fst_port_info *port) | |
2149 | { | |
2150 | int signals; | |
2151 | int txq_length; | |
2152 | ||
2153 | /* Only init things if card is actually running. This allows open to | |
2154 | * succeed for downloads etc. | |
2155 | */ | |
2156 | if (port->card->state == FST_RUNNING) { | |
2157 | if (port->run) { | |
2158 | dbg(DBG_OPEN, "open: found port already running\n"); | |
2159 | ||
2160 | fst_issue_cmd(port, STOPPORT); | |
2161 | port->run = 0; | |
2162 | } | |
2163 | ||
2164 | fst_rx_config(port); | |
2165 | fst_tx_config(port); | |
2166 | fst_op_raise(port, OPSTS_RTS | OPSTS_DTR); | |
2167 | ||
2168 | fst_issue_cmd(port, STARTPORT); | |
2169 | port->run = 1; | |
2170 | ||
2171 | signals = FST_RDL(port->card, v24DebouncedSts[port->index]); | |
2172 | if (signals & (((port->hwif == X21) || (port->hwif == X21D)) | |
2173 | ? IPSTS_INDICATE : IPSTS_DCD)) | |
2174 | netif_carrier_on(port_to_dev(port)); | |
2175 | else | |
2176 | netif_carrier_off(port_to_dev(port)); | |
2177 | ||
2178 | txq_length = port->txqe - port->txqs; | |
2179 | port->txqe = 0; | |
2180 | port->txqs = 0; | |
2181 | } | |
2182 | ||
2183 | } | |
2184 | ||
2185 | static void | |
2186 | fst_closeport(struct fst_port_info *port) | |
2187 | { | |
2188 | if (port->card->state == FST_RUNNING) { | |
2189 | if (port->run) { | |
2190 | port->run = 0; | |
2191 | fst_op_lower(port, OPSTS_RTS | OPSTS_DTR); | |
2192 | ||
2193 | fst_issue_cmd(port, STOPPORT); | |
2194 | } else { | |
2195 | dbg(DBG_OPEN, "close: port not running\n"); | |
2196 | } | |
2197 | } | |
2198 | } | |
2199 | ||
2200 | static int | |
2201 | fst_open(struct net_device *dev) | |
2202 | { | |
2203 | int err; | |
2204 | struct fst_port_info *port; | |
2205 | ||
2206 | port = dev_to_port(dev); | |
2207 | if (!try_module_get(THIS_MODULE)) | |
2208 | return -EBUSY; | |
2209 | ||
2210 | if (port->mode != FST_RAW) { | |
2211 | err = hdlc_open(dev); | |
2212 | if (err) | |
2213 | return err; | |
2214 | } | |
2215 | ||
2216 | fst_openport(port); | |
2217 | netif_wake_queue(dev); | |
2218 | return 0; | |
2219 | } | |
2220 | ||
2221 | static int | |
2222 | fst_close(struct net_device *dev) | |
2223 | { | |
2224 | struct fst_port_info *port; | |
2225 | struct fst_card_info *card; | |
2226 | unsigned char tx_dma_done; | |
2227 | unsigned char rx_dma_done; | |
2228 | ||
2229 | port = dev_to_port(dev); | |
2230 | card = port->card; | |
2231 | ||
2232 | tx_dma_done = inb(card->pci_conf + DMACSR1); | |
2233 | rx_dma_done = inb(card->pci_conf + DMACSR0); | |
2234 | dbg(DBG_OPEN, | |
2235 | "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n", | |
2236 | card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress, | |
2237 | rx_dma_done); | |
2238 | ||
2239 | netif_stop_queue(dev); | |
2240 | fst_closeport(dev_to_port(dev)); | |
2241 | if (port->mode != FST_RAW) { | |
2242 | hdlc_close(dev); | |
2243 | } | |
2244 | module_put(THIS_MODULE); | |
2245 | return 0; | |
2246 | } | |
2247 | ||
2248 | static int | |
2249 | fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity) | |
2250 | { | |
2251 | /* | |
2252 | * Setting currently fixed in FarSync card so we check and forget | |
2253 | */ | |
2254 | if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT) | |
2255 | return -EINVAL; | |
2256 | return 0; | |
2257 | } | |
2258 | ||
2259 | static void | |
2260 | fst_tx_timeout(struct net_device *dev) | |
2261 | { | |
2262 | struct fst_port_info *port; | |
2263 | struct fst_card_info *card; | |
1da177e4 LT |
2264 | |
2265 | port = dev_to_port(dev); | |
2266 | card = port->card; | |
198191c4 KH |
2267 | dev->stats.tx_errors++; |
2268 | dev->stats.tx_aborted_errors++; | |
1da177e4 LT |
2269 | dbg(DBG_ASS, "Tx timeout card %d port %d\n", |
2270 | card->card_no, port->index); | |
2271 | fst_issue_cmd(port, ABORTTX); | |
2272 | ||
2273 | dev->trans_start = jiffies; | |
2274 | netif_wake_queue(dev); | |
2275 | port->start = 0; | |
2276 | } | |
2277 | ||
d71a6749 | 2278 | static netdev_tx_t |
1da177e4 LT |
2279 | fst_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2280 | { | |
2281 | struct fst_card_info *card; | |
2282 | struct fst_port_info *port; | |
1da177e4 LT |
2283 | unsigned long flags; |
2284 | int txq_length; | |
2285 | ||
2286 | port = dev_to_port(dev); | |
2287 | card = port->card; | |
2288 | dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len); | |
2289 | ||
2290 | /* Drop packet with error if we don't have carrier */ | |
2291 | if (!netif_carrier_ok(dev)) { | |
2292 | dev_kfree_skb(skb); | |
198191c4 KH |
2293 | dev->stats.tx_errors++; |
2294 | dev->stats.tx_carrier_errors++; | |
1da177e4 LT |
2295 | dbg(DBG_ASS, |
2296 | "Tried to transmit but no carrier on card %d port %d\n", | |
2297 | card->card_no, port->index); | |
ec634fe3 | 2298 | return NETDEV_TX_OK; |
1da177e4 LT |
2299 | } |
2300 | ||
2301 | /* Drop it if it's too big! MTU failure ? */ | |
2302 | if (skb->len > LEN_TX_BUFFER) { | |
2303 | dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len, | |
2304 | LEN_TX_BUFFER); | |
2305 | dev_kfree_skb(skb); | |
198191c4 | 2306 | dev->stats.tx_errors++; |
ec634fe3 | 2307 | return NETDEV_TX_OK; |
1da177e4 LT |
2308 | } |
2309 | ||
2310 | /* | |
2311 | * We are always going to queue the packet | |
2312 | * so that the bottom half is the only place we tx from | |
2313 | * Check there is room in the port txq | |
2314 | */ | |
2315 | spin_lock_irqsave(&card->card_lock, flags); | |
2316 | if ((txq_length = port->txqe - port->txqs) < 0) { | |
2317 | /* | |
2318 | * This is the case where the next free has wrapped but the | |
2319 | * last used hasn't | |
2320 | */ | |
2321 | txq_length = txq_length + FST_TXQ_DEPTH; | |
2322 | } | |
2323 | spin_unlock_irqrestore(&card->card_lock, flags); | |
2324 | if (txq_length > fst_txq_high) { | |
2325 | /* | |
2326 | * We have got enough buffers in the pipeline. Ask the network | |
2327 | * layer to stop sending frames down | |
2328 | */ | |
2329 | netif_stop_queue(dev); | |
2330 | port->start = 1; /* I'm using this to signal stop sent up */ | |
2331 | } | |
2332 | ||
2333 | if (txq_length == FST_TXQ_DEPTH - 1) { | |
2334 | /* | |
2335 | * This shouldn't have happened but such is life | |
2336 | */ | |
2337 | dev_kfree_skb(skb); | |
198191c4 | 2338 | dev->stats.tx_errors++; |
1da177e4 LT |
2339 | dbg(DBG_ASS, "Tx queue overflow card %d port %d\n", |
2340 | card->card_no, port->index); | |
ec634fe3 | 2341 | return NETDEV_TX_OK; |
1da177e4 LT |
2342 | } |
2343 | ||
2344 | /* | |
2345 | * queue the buffer | |
2346 | */ | |
2347 | spin_lock_irqsave(&card->card_lock, flags); | |
2348 | port->txq[port->txqe] = skb; | |
2349 | port->txqe++; | |
2350 | if (port->txqe == FST_TXQ_DEPTH) | |
2351 | port->txqe = 0; | |
2352 | spin_unlock_irqrestore(&card->card_lock, flags); | |
2353 | ||
2354 | /* Scehdule the bottom half which now does transmit processing */ | |
2355 | fst_q_work_item(&fst_work_txq, card->card_no); | |
2356 | tasklet_schedule(&fst_tx_task); | |
2357 | ||
ec634fe3 | 2358 | return NETDEV_TX_OK; |
1da177e4 LT |
2359 | } |
2360 | ||
2361 | /* | |
2362 | * Card setup having checked hardware resources. | |
2363 | * Should be pretty bizarre if we get an error here (kernel memory | |
2364 | * exhaustion is one possibility). If we do see a problem we report it | |
2365 | * via a printk and leave the corresponding interface and all that follow | |
2366 | * disabled. | |
2367 | */ | |
2368 | static char *type_strings[] __devinitdata = { | |
2369 | "no hardware", /* Should never be seen */ | |
2370 | "FarSync T2P", | |
2371 | "FarSync T4P", | |
2372 | "FarSync T1U", | |
2373 | "FarSync T2U", | |
2374 | "FarSync T4U", | |
2375 | "FarSync TE1" | |
2376 | }; | |
2377 | ||
2378 | static void __devinit | |
2379 | fst_init_card(struct fst_card_info *card) | |
2380 | { | |
2381 | int i; | |
2382 | int err; | |
2383 | ||
2384 | /* We're working on a number of ports based on the card ID. If the | |
2385 | * firmware detects something different later (should never happen) | |
2386 | * we'll have to revise it in some way then. | |
2387 | */ | |
2388 | for (i = 0; i < card->nports; i++) { | |
2389 | err = register_hdlc_device(card->ports[i].dev); | |
2390 | if (err < 0) { | |
2391 | int j; | |
2392 | printk_err ("Cannot register HDLC device for port %d" | |
2393 | " (errno %d)\n", i, -err ); | |
2394 | for (j = i; j < card->nports; j++) { | |
2395 | free_netdev(card->ports[j].dev); | |
2396 | card->ports[j].dev = NULL; | |
2397 | } | |
2398 | card->nports = i; | |
2399 | break; | |
2400 | } | |
2401 | } | |
2402 | ||
2403 | printk_info("%s-%s: %s IRQ%d, %d ports\n", | |
2404 | port_to_dev(&card->ports[0])->name, | |
2405 | port_to_dev(&card->ports[card->nports - 1])->name, | |
2406 | type_strings[card->type], card->irq, card->nports); | |
2407 | } | |
2408 | ||
991990a1 KH |
2409 | static const struct net_device_ops fst_ops = { |
2410 | .ndo_open = fst_open, | |
2411 | .ndo_stop = fst_close, | |
2412 | .ndo_change_mtu = hdlc_change_mtu, | |
2413 | .ndo_start_xmit = hdlc_start_xmit, | |
2414 | .ndo_do_ioctl = fst_ioctl, | |
2415 | .ndo_tx_timeout = fst_tx_timeout, | |
2416 | }; | |
2417 | ||
1da177e4 LT |
2418 | /* |
2419 | * Initialise card when detected. | |
2420 | * Returns 0 to indicate success, or errno otherwise. | |
2421 | */ | |
2422 | static int __devinit | |
2423 | fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
2424 | { | |
2425 | static int firsttime_done = 0; | |
2426 | static int no_of_cards_added = 0; | |
2427 | struct fst_card_info *card; | |
2428 | int err = 0; | |
2429 | int i; | |
2430 | ||
2431 | if (!firsttime_done) { | |
2432 | printk_info("FarSync WAN driver " FST_USER_VERSION | |
2433 | " (c) 2001-2004 FarSite Communications Ltd.\n"); | |
2434 | firsttime_done = 1; | |
2435 | dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask); | |
2436 | } | |
2437 | ||
2438 | /* | |
2439 | * We are going to be clever and allow certain cards not to be | |
2440 | * configured. An exclude list can be provided in /etc/modules.conf | |
2441 | */ | |
2442 | if (fst_excluded_cards != 0) { | |
2443 | /* | |
2444 | * There are cards to exclude | |
2445 | * | |
2446 | */ | |
2447 | for (i = 0; i < fst_excluded_cards; i++) { | |
2448 | if ((pdev->devfn) >> 3 == fst_excluded_list[i]) { | |
2449 | printk_info("FarSync PCI device %d not assigned\n", | |
2450 | (pdev->devfn) >> 3); | |
2451 | return -EBUSY; | |
2452 | } | |
2453 | } | |
2454 | } | |
2455 | ||
2456 | /* Allocate driver private data */ | |
dd00cc48 | 2457 | card = kzalloc(sizeof (struct fst_card_info), GFP_KERNEL); |
1da177e4 LT |
2458 | if (card == NULL) { |
2459 | printk_err("FarSync card found but insufficient memory for" | |
2460 | " driver storage\n"); | |
2461 | return -ENOMEM; | |
2462 | } | |
1da177e4 LT |
2463 | |
2464 | /* Try to enable the device */ | |
2465 | if ((err = pci_enable_device(pdev)) != 0) { | |
2466 | printk_err("Failed to enable card. Err %d\n", -err); | |
2467 | kfree(card); | |
2468 | return err; | |
2469 | } | |
2470 | ||
2471 | if ((err = pci_request_regions(pdev, "FarSync")) !=0) { | |
2472 | printk_err("Failed to allocate regions. Err %d\n", -err); | |
2473 | pci_disable_device(pdev); | |
2474 | kfree(card); | |
2475 | return err; | |
2476 | } | |
2477 | ||
2478 | /* Get virtual addresses of memory regions */ | |
2479 | card->pci_conf = pci_resource_start(pdev, 1); | |
2480 | card->phys_mem = pci_resource_start(pdev, 2); | |
2481 | card->phys_ctlmem = pci_resource_start(pdev, 3); | |
2482 | if ((card->mem = ioremap(card->phys_mem, FST_MEMSIZE)) == NULL) { | |
2483 | printk_err("Physical memory remap failed\n"); | |
2484 | pci_release_regions(pdev); | |
2485 | pci_disable_device(pdev); | |
2486 | kfree(card); | |
2487 | return -ENODEV; | |
2488 | } | |
2489 | if ((card->ctlmem = ioremap(card->phys_ctlmem, 0x10)) == NULL) { | |
2490 | printk_err("Control memory remap failed\n"); | |
2491 | pci_release_regions(pdev); | |
2492 | pci_disable_device(pdev); | |
2493 | kfree(card); | |
2494 | return -ENODEV; | |
2495 | } | |
2496 | dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem); | |
2497 | ||
2498 | /* Register the interrupt handler */ | |
1fb9df5d | 2499 | if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) { |
1da177e4 LT |
2500 | printk_err("Unable to register interrupt %d\n", card->irq); |
2501 | pci_release_regions(pdev); | |
2502 | pci_disable_device(pdev); | |
2503 | iounmap(card->ctlmem); | |
2504 | iounmap(card->mem); | |
2505 | kfree(card); | |
2506 | return -ENODEV; | |
2507 | } | |
2508 | ||
2509 | /* Record info we need */ | |
2510 | card->irq = pdev->irq; | |
2511 | card->type = ent->driver_data; | |
2512 | card->family = ((ent->driver_data == FST_TYPE_T2P) || | |
2513 | (ent->driver_data == FST_TYPE_T4P)) | |
2514 | ? FST_FAMILY_TXP : FST_FAMILY_TXU; | |
2515 | if ((ent->driver_data == FST_TYPE_T1U) || | |
2516 | (ent->driver_data == FST_TYPE_TE1)) | |
2517 | card->nports = 1; | |
2518 | else | |
2519 | card->nports = ((ent->driver_data == FST_TYPE_T2P) || | |
2520 | (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4; | |
2521 | ||
2522 | card->state = FST_UNINIT; | |
2523 | spin_lock_init ( &card->card_lock ); | |
2524 | ||
2525 | for ( i = 0 ; i < card->nports ; i++ ) { | |
2526 | struct net_device *dev = alloc_hdlcdev(&card->ports[i]); | |
2527 | hdlc_device *hdlc; | |
2528 | if (!dev) { | |
2529 | while (i--) | |
2530 | free_netdev(card->ports[i].dev); | |
2531 | printk_err ("FarSync: out of memory\n"); | |
2532 | free_irq(card->irq, card); | |
2533 | pci_release_regions(pdev); | |
2534 | pci_disable_device(pdev); | |
2535 | iounmap(card->ctlmem); | |
2536 | iounmap(card->mem); | |
2537 | kfree(card); | |
2538 | return -ENODEV; | |
2539 | } | |
2540 | card->ports[i].dev = dev; | |
2541 | card->ports[i].card = card; | |
2542 | card->ports[i].index = i; | |
2543 | card->ports[i].run = 0; | |
2544 | ||
2545 | hdlc = dev_to_hdlc(dev); | |
2546 | ||
2547 | /* Fill in the net device info */ | |
2548 | /* Since this is a PCI setup this is purely | |
2549 | * informational. Give them the buffer addresses | |
2550 | * and basic card I/O. | |
2551 | */ | |
2552 | dev->mem_start = card->phys_mem | |
2553 | + BUF_OFFSET ( txBuffer[i][0][0]); | |
2554 | dev->mem_end = card->phys_mem | |
2555 | + BUF_OFFSET ( txBuffer[i][NUM_TX_BUFFER][0]); | |
2556 | dev->base_addr = card->pci_conf; | |
2557 | dev->irq = card->irq; | |
2558 | ||
991990a1 KH |
2559 | dev->netdev_ops = &fst_ops; |
2560 | dev->tx_queue_len = FST_TX_QUEUE_LEN; | |
2561 | dev->watchdog_timeo = FST_TX_TIMEOUT; | |
1da177e4 LT |
2562 | hdlc->attach = fst_attach; |
2563 | hdlc->xmit = fst_start_xmit; | |
2564 | } | |
2565 | ||
2566 | card->device = pdev; | |
2567 | ||
2568 | dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type, | |
2569 | card->nports, card->irq); | |
2570 | dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n", | |
2571 | card->pci_conf, card->phys_mem, card->phys_ctlmem); | |
2572 | ||
2573 | /* Reset the card's processor */ | |
2574 | fst_cpureset(card); | |
2575 | card->state = FST_RESET; | |
2576 | ||
2577 | /* Initialise DMA (if required) */ | |
2578 | fst_init_dma(card); | |
2579 | ||
2580 | /* Record driver data for later use */ | |
2581 | pci_set_drvdata(pdev, card); | |
2582 | ||
2583 | /* Remainder of card setup */ | |
2584 | fst_card_array[no_of_cards_added] = card; | |
2585 | card->card_no = no_of_cards_added++; /* Record instance and bump it */ | |
2586 | fst_init_card(card); | |
2587 | if (card->family == FST_FAMILY_TXU) { | |
2588 | /* | |
2589 | * Allocate a dma buffer for transmit and receives | |
2590 | */ | |
2591 | card->rx_dma_handle_host = | |
2592 | pci_alloc_consistent(card->device, FST_MAX_MTU, | |
2593 | &card->rx_dma_handle_card); | |
2594 | if (card->rx_dma_handle_host == NULL) { | |
2595 | printk_err("Could not allocate rx dma buffer\n"); | |
2596 | fst_disable_intr(card); | |
2597 | pci_release_regions(pdev); | |
2598 | pci_disable_device(pdev); | |
2599 | iounmap(card->ctlmem); | |
2600 | iounmap(card->mem); | |
2601 | kfree(card); | |
2602 | return -ENOMEM; | |
2603 | } | |
2604 | card->tx_dma_handle_host = | |
2605 | pci_alloc_consistent(card->device, FST_MAX_MTU, | |
2606 | &card->tx_dma_handle_card); | |
2607 | if (card->tx_dma_handle_host == NULL) { | |
2608 | printk_err("Could not allocate tx dma buffer\n"); | |
2609 | fst_disable_intr(card); | |
2610 | pci_release_regions(pdev); | |
2611 | pci_disable_device(pdev); | |
2612 | iounmap(card->ctlmem); | |
2613 | iounmap(card->mem); | |
2614 | kfree(card); | |
2615 | return -ENOMEM; | |
2616 | } | |
2617 | } | |
2618 | return 0; /* Success */ | |
2619 | } | |
2620 | ||
2621 | /* | |
2622 | * Cleanup and close down a card | |
2623 | */ | |
2624 | static void __devexit | |
2625 | fst_remove_one(struct pci_dev *pdev) | |
2626 | { | |
2627 | struct fst_card_info *card; | |
2628 | int i; | |
2629 | ||
2630 | card = pci_get_drvdata(pdev); | |
2631 | ||
2632 | for (i = 0; i < card->nports; i++) { | |
2633 | struct net_device *dev = port_to_dev(&card->ports[i]); | |
2634 | unregister_hdlc_device(dev); | |
2635 | } | |
2636 | ||
2637 | fst_disable_intr(card); | |
2638 | free_irq(card->irq, card); | |
2639 | ||
2640 | iounmap(card->ctlmem); | |
2641 | iounmap(card->mem); | |
2642 | pci_release_regions(pdev); | |
2643 | if (card->family == FST_FAMILY_TXU) { | |
2644 | /* | |
2645 | * Free dma buffers | |
2646 | */ | |
2647 | pci_free_consistent(card->device, FST_MAX_MTU, | |
2648 | card->rx_dma_handle_host, | |
2649 | card->rx_dma_handle_card); | |
2650 | pci_free_consistent(card->device, FST_MAX_MTU, | |
2651 | card->tx_dma_handle_host, | |
2652 | card->tx_dma_handle_card); | |
2653 | } | |
2654 | fst_card_array[card->card_no] = NULL; | |
2655 | } | |
2656 | ||
2657 | static struct pci_driver fst_driver = { | |
2658 | .name = FST_NAME, | |
2659 | .id_table = fst_pci_dev_id, | |
2660 | .probe = fst_add_one, | |
2661 | .remove = __devexit_p(fst_remove_one), | |
2662 | .suspend = NULL, | |
2663 | .resume = NULL, | |
2664 | }; | |
2665 | ||
2666 | static int __init | |
2667 | fst_init(void) | |
2668 | { | |
2669 | int i; | |
2670 | ||
2671 | for (i = 0; i < FST_MAX_CARDS; i++) | |
2672 | fst_card_array[i] = NULL; | |
2673 | spin_lock_init(&fst_work_q_lock); | |
29917620 | 2674 | return pci_register_driver(&fst_driver); |
1da177e4 LT |
2675 | } |
2676 | ||
2677 | static void __exit | |
2678 | fst_cleanup_module(void) | |
2679 | { | |
2680 | printk_info("FarSync WAN driver unloading\n"); | |
2681 | pci_unregister_driver(&fst_driver); | |
2682 | } | |
2683 | ||
2684 | module_init(fst_init); | |
2685 | module_exit(fst_cleanup_module); |