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1da177e4 LT |
1 | /* |
2 | * FarSync X21 driver for Linux | |
3 | * | |
4 | * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards | |
5 | * | |
6 | * Copyright (C) 2001 FarSite Communications Ltd. | |
7 | * www.farsite.co.uk | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> | |
15 | * | |
16 | * For the most part this file only contains structures and information | |
17 | * that is visible to applications outside the driver. Shared memory | |
18 | * layout etc is internal to the driver and described within farsync.c. | |
19 | * Overlap exists in that the values used for some fields within the | |
20 | * ioctl interface extend into the cards firmware interface so values in | |
21 | * this file may not be changed arbitrarily. | |
22 | */ | |
23 | ||
24 | /* What's in a name | |
25 | * | |
26 | * The project name for this driver is Oscar. The driver is intended to be | |
27 | * used with the FarSite T-Series cards (T2P & T4P) running in the high | |
28 | * speed frame shifter mode. This is sometimes referred to as X.21 mode | |
29 | * which is a complete misnomer as the card continues to support V.24 and | |
30 | * V.35 as well as X.21. | |
31 | * | |
32 | * A short common prefix is useful for routines within the driver to avoid | |
33 | * conflict with other similar drivers and I chosen to use "fst_" for this | |
34 | * purpose (FarSite T-series). | |
35 | * | |
36 | * Finally the device driver needs a short network interface name. Since | |
37 | * "hdlc" is already in use I've chosen the even less informative "sync" | |
38 | * for the present. | |
39 | */ | |
40 | #define FST_NAME "fst" /* In debug/info etc */ | |
41 | #define FST_NDEV_NAME "sync" /* For net interface */ | |
42 | #define FST_DEV_NAME "farsync" /* For misc interfaces */ | |
43 | ||
44 | ||
45 | /* User version number | |
46 | * | |
47 | * This version number is incremented with each official release of the | |
48 | * package and is a simplified number for normal user reference. | |
49 | * Individual files are tracked by the version control system and may | |
50 | * have individual versions (or IDs) that move much faster than the | |
51 | * the release version as individual updates are tracked. | |
52 | */ | |
53 | #define FST_USER_VERSION "1.04" | |
54 | ||
55 | ||
56 | /* Ioctl call command values | |
1da177e4 LT |
57 | */ |
58 | #define FSTWRITE (SIOCDEVPRIVATE+10) | |
59 | #define FSTCPURESET (SIOCDEVPRIVATE+11) | |
60 | #define FSTCPURELEASE (SIOCDEVPRIVATE+12) | |
61 | #define FSTGETCONF (SIOCDEVPRIVATE+13) | |
62 | #define FSTSETCONF (SIOCDEVPRIVATE+14) | |
63 | ||
64 | ||
65 | /* FSTWRITE | |
66 | * | |
67 | * Used to write a block of data (firmware etc) before the card is running | |
68 | */ | |
69 | struct fstioc_write { | |
70 | unsigned int size; | |
71 | unsigned int offset; | |
72 | unsigned char data[0]; | |
73 | }; | |
74 | ||
75 | ||
76 | /* FSTCPURESET and FSTCPURELEASE | |
77 | * | |
78 | * These take no additional data. | |
79 | * FSTCPURESET forces the cards CPU into a reset state and holds it there. | |
80 | * FSTCPURELEASE releases the CPU from this reset state allowing it to run, | |
81 | * the reset vector should be setup before this ioctl is run. | |
82 | */ | |
83 | ||
84 | /* FSTGETCONF and FSTSETCONF | |
85 | * | |
86 | * Get and set a card/ports configuration. | |
87 | * In order to allow selective setting of items and for the kernel to | |
88 | * indicate a partial status response the first field "valid" is a bitmask | |
89 | * indicating which other fields in the structure are valid. | |
90 | * Many of the field names in this structure match those used in the | |
91 | * firmware shared memory configuration interface and come originally from | |
92 | * the NT header file Smc.h | |
93 | * | |
94 | * When used with FSTGETCONF this structure should be zeroed before use. | |
95 | * This is to allow for possible future expansion when some of the fields | |
96 | * might be used to indicate a different (expanded) structure. | |
97 | */ | |
98 | struct fstioc_info { | |
99 | unsigned int valid; /* Bits of structure that are valid */ | |
100 | unsigned int nports; /* Number of serial ports */ | |
101 | unsigned int type; /* Type index of card */ | |
102 | unsigned int state; /* State of card */ | |
103 | unsigned int index; /* Index of port ioctl was issued on */ | |
104 | unsigned int smcFirmwareVersion; | |
105 | unsigned long kernelVersion; /* What Kernel version we are working with */ | |
106 | unsigned short lineInterface; /* Physical interface type */ | |
107 | unsigned char proto; /* Line protocol */ | |
108 | unsigned char internalClock; /* 1 => internal clock, 0 => external */ | |
109 | unsigned int lineSpeed; /* Speed in bps */ | |
110 | unsigned int v24IpSts; /* V.24 control input status */ | |
111 | unsigned int v24OpSts; /* V.24 control output status */ | |
112 | unsigned short clockStatus; /* lsb: 0=> present, 1=> absent */ | |
113 | unsigned short cableStatus; /* lsb: 0=> present, 1=> absent */ | |
114 | unsigned short cardMode; /* lsb: LED id mode */ | |
115 | unsigned short debug; /* Debug flags */ | |
116 | unsigned char transparentMode; /* Not used always 0 */ | |
117 | unsigned char invertClock; /* Invert clock feature for syncing */ | |
118 | unsigned char startingSlot; /* Time slot to use for start of tx */ | |
119 | unsigned char clockSource; /* External or internal */ | |
120 | unsigned char framing; /* E1, T1 or J1 */ | |
121 | unsigned char structure; /* unframed, double, crc4, f4, f12, */ | |
122 | /* f24 f72 */ | |
123 | unsigned char interface; /* rj48c or bnc */ | |
124 | unsigned char coding; /* hdb3 b8zs */ | |
125 | unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */ | |
126 | unsigned char equalizer; /* short or lon haul settings */ | |
127 | unsigned char loopMode; /* various loopbacks */ | |
128 | unsigned char range; /* cable lengths */ | |
129 | unsigned char txBufferMode; /* tx elastic buffer depth */ | |
130 | unsigned char rxBufferMode; /* rx elastic buffer depth */ | |
131 | unsigned char losThreshold; /* Attenuation on LOS signal */ | |
132 | unsigned char idleCode; /* Value to send as idle timeslot */ | |
133 | unsigned int receiveBufferDelay; /* delay thro rx buffer timeslots */ | |
134 | unsigned int framingErrorCount; /* framing errors */ | |
135 | unsigned int codeViolationCount; /* code violations */ | |
136 | unsigned int crcErrorCount; /* CRC errors */ | |
137 | int lineAttenuation; /* in dB*/ | |
138 | unsigned short lossOfSignal; | |
139 | unsigned short receiveRemoteAlarm; | |
140 | unsigned short alarmIndicationSignal; | |
141 | }; | |
142 | ||
143 | /* "valid" bitmask */ | |
144 | #define FSTVAL_NONE 0x00000000 /* Nothing valid (firmware not running). | |
145 | * Slight misnomer. In fact nports, | |
146 | * type, state and index will be set | |
147 | * based on hardware detected. | |
148 | */ | |
149 | #define FSTVAL_OMODEM 0x0000001F /* First 5 bits correspond to the | |
150 | * output status bits defined for | |
151 | * v24OpSts | |
152 | */ | |
153 | #define FSTVAL_SPEED 0x00000020 /* internalClock, lineSpeed, clockStatus | |
154 | */ | |
155 | #define FSTVAL_CABLE 0x00000040 /* lineInterface, cableStatus */ | |
156 | #define FSTVAL_IMODEM 0x00000080 /* v24IpSts */ | |
157 | #define FSTVAL_CARD 0x00000100 /* nports, type, state, index, | |
158 | * smcFirmwareVersion | |
159 | */ | |
160 | #define FSTVAL_PROTO 0x00000200 /* proto */ | |
161 | #define FSTVAL_MODE 0x00000400 /* cardMode */ | |
162 | #define FSTVAL_PHASE 0x00000800 /* Clock phase */ | |
163 | #define FSTVAL_TE1 0x00001000 /* T1E1 Configuration */ | |
164 | #define FSTVAL_DEBUG 0x80000000 /* debug */ | |
165 | #define FSTVAL_ALL 0x00001FFF /* Note: does not include DEBUG flag */ | |
166 | ||
167 | /* "type" */ | |
168 | #define FST_TYPE_NONE 0 /* Probably should never happen */ | |
169 | #define FST_TYPE_T2P 1 /* T2P X21 2 port card */ | |
170 | #define FST_TYPE_T4P 2 /* T4P X21 4 port card */ | |
171 | #define FST_TYPE_T1U 3 /* T1U X21 1 port card */ | |
172 | #define FST_TYPE_T2U 4 /* T2U X21 2 port card */ | |
173 | #define FST_TYPE_T4U 5 /* T4U X21 4 port card */ | |
174 | #define FST_TYPE_TE1 6 /* T1E1 X21 1 port card */ | |
175 | ||
176 | /* "family" */ | |
177 | #define FST_FAMILY_TXP 0 /* T2P or T4P */ | |
178 | #define FST_FAMILY_TXU 1 /* T1U or T2U or T4U */ | |
179 | ||
180 | /* "state" */ | |
181 | #define FST_UNINIT 0 /* Raw uninitialised state following | |
182 | * system startup */ | |
183 | #define FST_RESET 1 /* Processor held in reset state */ | |
184 | #define FST_DOWNLOAD 2 /* Card being downloaded */ | |
185 | #define FST_STARTING 3 /* Released following download */ | |
186 | #define FST_RUNNING 4 /* Processor running */ | |
187 | #define FST_BADVERSION 5 /* Bad shared memory version detected */ | |
188 | #define FST_HALTED 6 /* Processor flagged a halt */ | |
189 | #define FST_IFAILED 7 /* Firmware issued initialisation failed | |
190 | * interrupt | |
191 | */ | |
192 | /* "lineInterface" */ | |
193 | #define V24 1 | |
194 | #define X21 2 | |
195 | #define V35 3 | |
196 | #define X21D 4 | |
197 | #define T1 5 | |
198 | #define E1 6 | |
199 | #define J1 7 | |
200 | ||
201 | /* "proto" */ | |
1da177e4 LT |
202 | #define FST_RAW 4 /* Two way raw packets */ |
203 | #define FST_GEN_HDLC 5 /* Using "Generic HDLC" module */ | |
204 | ||
205 | /* "internalClock" */ | |
206 | #define INTCLK 1 | |
207 | #define EXTCLK 0 | |
208 | ||
209 | /* "v24IpSts" bitmask */ | |
210 | #define IPSTS_CTS 0x00000001 /* Clear To Send (Indicate for X.21) */ | |
211 | #define IPSTS_INDICATE IPSTS_CTS | |
212 | #define IPSTS_DSR 0x00000002 /* Data Set Ready (T2P Port A) */ | |
213 | #define IPSTS_DCD 0x00000004 /* Data Carrier Detect */ | |
214 | #define IPSTS_RI 0x00000008 /* Ring Indicator (T2P Port A) */ | |
215 | #define IPSTS_TMI 0x00000010 /* Test Mode Indicator (Not Supported)*/ | |
216 | ||
217 | /* "v24OpSts" bitmask */ | |
218 | #define OPSTS_RTS 0x00000001 /* Request To Send (Control for X.21) */ | |
219 | #define OPSTS_CONTROL OPSTS_RTS | |
220 | #define OPSTS_DTR 0x00000002 /* Data Terminal Ready */ | |
221 | #define OPSTS_DSRS 0x00000004 /* Data Signalling Rate Select (Not | |
222 | * Supported) */ | |
223 | #define OPSTS_SS 0x00000008 /* Select Standby (Not Supported) */ | |
224 | #define OPSTS_LL 0x00000010 /* Maintenance Test (Not Supported) */ | |
225 | ||
226 | /* "cardMode" bitmask */ | |
227 | #define CARD_MODE_IDENTIFY 0x0001 | |
228 | ||
229 | /* | |
230 | * Constants for T1/E1 configuration | |
231 | */ | |
232 | ||
233 | /* | |
234 | * Clock source | |
235 | */ | |
236 | #define CLOCKING_SLAVE 0 | |
237 | #define CLOCKING_MASTER 1 | |
238 | ||
239 | /* | |
240 | * Framing | |
241 | */ | |
242 | #define FRAMING_E1 0 | |
243 | #define FRAMING_J1 1 | |
244 | #define FRAMING_T1 2 | |
245 | ||
246 | /* | |
247 | * Structure | |
248 | */ | |
249 | #define STRUCTURE_UNFRAMED 0 | |
250 | #define STRUCTURE_E1_DOUBLE 1 | |
251 | #define STRUCTURE_E1_CRC4 2 | |
252 | #define STRUCTURE_E1_CRC4M 3 | |
253 | #define STRUCTURE_T1_4 4 | |
254 | #define STRUCTURE_T1_12 5 | |
255 | #define STRUCTURE_T1_24 6 | |
256 | #define STRUCTURE_T1_72 7 | |
257 | ||
258 | /* | |
259 | * Interface | |
260 | */ | |
261 | #define INTERFACE_RJ48C 0 | |
262 | #define INTERFACE_BNC 1 | |
263 | ||
264 | /* | |
265 | * Coding | |
266 | */ | |
267 | ||
268 | #define CODING_HDB3 0 | |
269 | #define CODING_NRZ 1 | |
270 | #define CODING_CMI 2 | |
271 | #define CODING_CMI_HDB3 3 | |
272 | #define CODING_CMI_B8ZS 4 | |
273 | #define CODING_AMI 5 | |
274 | #define CODING_AMI_ZCS 6 | |
275 | #define CODING_B8ZS 7 | |
276 | ||
277 | /* | |
278 | * Line Build Out | |
279 | */ | |
280 | #define LBO_0dB 0 | |
281 | #define LBO_7dB5 1 | |
282 | #define LBO_15dB 2 | |
283 | #define LBO_22dB5 3 | |
284 | ||
285 | /* | |
286 | * Range for long haul t1 > 655ft | |
287 | */ | |
288 | #define RANGE_0_133_FT 0 | |
289 | #define RANGE_0_40_M RANGE_0_133_FT | |
290 | #define RANGE_133_266_FT 1 | |
291 | #define RANGE_40_81_M RANGE_133_266_FT | |
292 | #define RANGE_266_399_FT 2 | |
293 | #define RANGE_81_122_M RANGE_266_399_FT | |
294 | #define RANGE_399_533_FT 3 | |
295 | #define RANGE_122_162_M RANGE_399_533_FT | |
296 | #define RANGE_533_655_FT 4 | |
297 | #define RANGE_162_200_M RANGE_533_655_FT | |
298 | /* | |
299 | * Receive Equaliser | |
300 | */ | |
301 | #define EQUALIZER_SHORT 0 | |
302 | #define EQUALIZER_LONG 1 | |
303 | ||
304 | /* | |
305 | * Loop modes | |
306 | */ | |
307 | #define LOOP_NONE 0 | |
308 | #define LOOP_LOCAL 1 | |
309 | #define LOOP_PAYLOAD_EXC_TS0 2 | |
310 | #define LOOP_PAYLOAD_INC_TS0 3 | |
311 | #define LOOP_REMOTE 4 | |
312 | ||
313 | /* | |
314 | * Buffer modes | |
315 | */ | |
316 | #define BUFFER_2_FRAME 0 | |
317 | #define BUFFER_1_FRAME 1 | |
318 | #define BUFFER_96_BIT 2 | |
319 | #define BUFFER_NONE 3 | |
320 | ||
321 | /* Debug support | |
322 | * | |
323 | * These should only be enabled for development kernels, production code | |
324 | * should define FST_DEBUG=0 in order to exclude the code. | |
325 | * Setting FST_DEBUG=1 will include all the debug code but in a disabled | |
326 | * state, use the FSTSETCONF ioctl to enable specific debug actions, or | |
327 | * FST_DEBUG can be set to prime the debug selection. | |
328 | */ | |
329 | #define FST_DEBUG 0x0000 | |
330 | #if FST_DEBUG | |
331 | ||
332 | extern int fst_debug_mask; /* Bit mask of actions to debug, bits | |
333 | * listed below. Note: Bit 0 is used | |
334 | * to trigger the inclusion of this | |
335 | * code, without enabling any actions. | |
336 | */ | |
337 | #define DBG_INIT 0x0002 /* Card detection and initialisation */ | |
338 | #define DBG_OPEN 0x0004 /* Open and close sequences */ | |
339 | #define DBG_PCI 0x0008 /* PCI config operations */ | |
340 | #define DBG_IOCTL 0x0010 /* Ioctls and other config */ | |
341 | #define DBG_INTR 0x0020 /* Interrupt routines (be careful) */ | |
342 | #define DBG_TX 0x0040 /* Packet transmission */ | |
343 | #define DBG_RX 0x0080 /* Packet reception */ | |
344 | #define DBG_CMD 0x0100 /* Port command issuing */ | |
345 | ||
346 | #define DBG_ASS 0xFFFF /* Assert like statements. Code that | |
347 | * should never be reached, if you see | |
348 | * one of these then I've been an ass | |
349 | */ | |
350 | #endif /* FST_DEBUG */ | |
351 |