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1da177e4 LT |
1 | /* |
2 | * Hitachi SCA HD64570 and HD64572 common driver for Linux | |
3 | * | |
4 | * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of version 2 of the GNU General Public License | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * Sources of information: | |
11 | * Hitachi HD64570 SCA User's Manual | |
12 | * Hitachi HD64572 SCA-II User's Manual | |
13 | * | |
14 | * We use the following SCA memory map: | |
15 | * | |
16 | * Packet buffer descriptor rings - starting from winbase or win0base: | |
17 | * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring | |
18 | * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring | |
19 | * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used) | |
20 | * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used) | |
21 | * | |
22 | * Packet data buffers - starting from winbase + buff_offset: | |
23 | * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers | |
24 | * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers | |
25 | * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used) | |
26 | * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used) | |
27 | */ | |
28 | ||
29 | #include <linux/module.h> | |
30 | #include <linux/kernel.h> | |
31 | #include <linux/slab.h> | |
32 | #include <linux/jiffies.h> | |
33 | #include <linux/types.h> | |
34 | #include <linux/fcntl.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/in.h> | |
37 | #include <linux/string.h> | |
38 | #include <linux/errno.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/ioport.h> | |
41 | #include <linux/bitops.h> | |
42 | ||
43 | #include <asm/system.h> | |
44 | #include <asm/uaccess.h> | |
45 | #include <asm/io.h> | |
46 | ||
47 | #include <linux/netdevice.h> | |
48 | #include <linux/skbuff.h> | |
49 | ||
50 | #include <linux/hdlc.h> | |
51 | ||
52 | #if (!defined (__HD64570_H) && !defined (__HD64572_H)) || \ | |
53 | (defined (__HD64570_H) && defined (__HD64572_H)) | |
54 | #error Either hd64570.h or hd64572.h must be included | |
55 | #endif | |
56 | ||
57 | #define get_msci(port) (phy_node(port) ? MSCI1_OFFSET : MSCI0_OFFSET) | |
58 | #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET) | |
59 | #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET) | |
60 | ||
61 | #define SCA_INTR_MSCI(node) (node ? 0x10 : 0x01) | |
62 | #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02) | |
63 | #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04) | |
64 | ||
65 | #ifdef __HD64570_H /* HD64570 */ | |
66 | #define sca_outa(value, reg, card) sca_outw(value, reg, card) | |
67 | #define sca_ina(reg, card) sca_inw(reg, card) | |
68 | #define writea(value, ptr) writew(value, ptr) | |
69 | ||
70 | #else /* HD64572 */ | |
71 | #define sca_outa(value, reg, card) sca_outl(value, reg, card) | |
72 | #define sca_ina(reg, card) sca_inl(reg, card) | |
73 | #define writea(value, ptr) writel(value, ptr) | |
74 | #endif | |
75 | ||
76 | static inline struct net_device *port_to_dev(port_t *port) | |
77 | { | |
78 | return port->dev; | |
79 | } | |
80 | ||
81 | static inline int sca_intr_status(card_t *card) | |
82 | { | |
83 | u8 result = 0; | |
84 | ||
85 | #ifdef __HD64570_H /* HD64570 */ | |
86 | u8 isr0 = sca_in(ISR0, card); | |
87 | u8 isr1 = sca_in(ISR1, card); | |
88 | ||
89 | if (isr1 & 0x03) result |= SCA_INTR_DMAC_RX(0); | |
90 | if (isr1 & 0x0C) result |= SCA_INTR_DMAC_TX(0); | |
91 | if (isr1 & 0x30) result |= SCA_INTR_DMAC_RX(1); | |
92 | if (isr1 & 0xC0) result |= SCA_INTR_DMAC_TX(1); | |
93 | if (isr0 & 0x0F) result |= SCA_INTR_MSCI(0); | |
94 | if (isr0 & 0xF0) result |= SCA_INTR_MSCI(1); | |
95 | ||
96 | #else /* HD64572 */ | |
97 | u32 isr0 = sca_inl(ISR0, card); | |
98 | ||
99 | if (isr0 & 0x0000000F) result |= SCA_INTR_DMAC_RX(0); | |
100 | if (isr0 & 0x000000F0) result |= SCA_INTR_DMAC_TX(0); | |
101 | if (isr0 & 0x00000F00) result |= SCA_INTR_DMAC_RX(1); | |
102 | if (isr0 & 0x0000F000) result |= SCA_INTR_DMAC_TX(1); | |
103 | if (isr0 & 0x003E0000) result |= SCA_INTR_MSCI(0); | |
104 | if (isr0 & 0x3E000000) result |= SCA_INTR_MSCI(1); | |
105 | ||
106 | #endif /* HD64570 vs HD64572 */ | |
107 | ||
108 | if (!(result & SCA_INTR_DMAC_TX(0))) | |
109 | if (sca_in(DSR_TX(0), card) & DSR_EOM) | |
110 | result |= SCA_INTR_DMAC_TX(0); | |
111 | if (!(result & SCA_INTR_DMAC_TX(1))) | |
112 | if (sca_in(DSR_TX(1), card) & DSR_EOM) | |
113 | result |= SCA_INTR_DMAC_TX(1); | |
114 | ||
115 | return result; | |
116 | } | |
117 | ||
118 | static inline port_t* dev_to_port(struct net_device *dev) | |
119 | { | |
120 | return dev_to_hdlc(dev)->priv; | |
121 | } | |
122 | ||
123 | static inline u16 next_desc(port_t *port, u16 desc, int transmit) | |
124 | { | |
125 | return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers | |
126 | : port_to_card(port)->rx_ring_buffers); | |
127 | } | |
128 | ||
129 | ||
130 | ||
131 | static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit) | |
132 | { | |
133 | u16 rx_buffs = port_to_card(port)->rx_ring_buffers; | |
134 | u16 tx_buffs = port_to_card(port)->tx_ring_buffers; | |
135 | ||
136 | desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc. | |
137 | return log_node(port) * (rx_buffs + tx_buffs) + | |
138 | transmit * rx_buffs + desc; | |
139 | } | |
140 | ||
141 | ||
142 | ||
143 | static inline u16 desc_offset(port_t *port, u16 desc, int transmit) | |
144 | { | |
145 | /* Descriptor offset always fits in 16 bytes */ | |
146 | return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc); | |
147 | } | |
148 | ||
149 | ||
150 | ||
151 | static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, int transmit) | |
152 | { | |
153 | #ifdef PAGE0_ALWAYS_MAPPED | |
154 | return (pkt_desc __iomem *)(win0base(port_to_card(port)) | |
155 | + desc_offset(port, desc, transmit)); | |
156 | #else | |
157 | return (pkt_desc __iomem *)(winbase(port_to_card(port)) | |
158 | + desc_offset(port, desc, transmit)); | |
159 | #endif | |
160 | } | |
161 | ||
162 | ||
163 | ||
164 | static inline u32 buffer_offset(port_t *port, u16 desc, int transmit) | |
165 | { | |
166 | return port_to_card(port)->buff_offset + | |
167 | desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU; | |
168 | } | |
169 | ||
170 | ||
171 | ||
172 | static void sca_init_sync_port(port_t *port) | |
173 | { | |
174 | card_t *card = port_to_card(port); | |
175 | int transmit, i; | |
176 | ||
177 | port->rxin = 0; | |
178 | port->txin = 0; | |
179 | port->txlast = 0; | |
180 | ||
181 | #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) | |
182 | openwin(card, 0); | |
183 | #endif | |
184 | ||
185 | for (transmit = 0; transmit < 2; transmit++) { | |
186 | u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port); | |
187 | u16 buffs = transmit ? card->tx_ring_buffers | |
188 | : card->rx_ring_buffers; | |
189 | ||
190 | for (i = 0; i < buffs; i++) { | |
191 | pkt_desc __iomem *desc = desc_address(port, i, transmit); | |
192 | u16 chain_off = desc_offset(port, i + 1, transmit); | |
193 | u32 buff_off = buffer_offset(port, i, transmit); | |
194 | ||
195 | writea(chain_off, &desc->cp); | |
196 | writel(buff_off, &desc->bp); | |
197 | writew(0, &desc->len); | |
198 | writeb(0, &desc->stat); | |
199 | } | |
200 | ||
201 | /* DMA disable - to halt state */ | |
202 | sca_out(0, transmit ? DSR_TX(phy_node(port)) : | |
203 | DSR_RX(phy_node(port)), card); | |
204 | /* software ABORT - to initial state */ | |
205 | sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) : | |
206 | DCR_RX(phy_node(port)), card); | |
207 | ||
208 | #ifdef __HD64570_H | |
209 | sca_out(0, dmac + CPB, card); /* pointer base */ | |
210 | #endif | |
211 | /* current desc addr */ | |
212 | sca_outa(desc_offset(port, 0, transmit), dmac + CDAL, card); | |
213 | if (!transmit) | |
214 | sca_outa(desc_offset(port, buffs - 1, transmit), | |
215 | dmac + EDAL, card); | |
216 | else | |
217 | sca_outa(desc_offset(port, 0, transmit), dmac + EDAL, | |
218 | card); | |
219 | ||
220 | /* clear frame end interrupt counter */ | |
221 | sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) : | |
222 | DCR_RX(phy_node(port)), card); | |
223 | ||
224 | if (!transmit) { /* Receive */ | |
225 | /* set buffer length */ | |
226 | sca_outw(HDLC_MAX_MRU, dmac + BFLL, card); | |
227 | /* Chain mode, Multi-frame */ | |
228 | sca_out(0x14, DMR_RX(phy_node(port)), card); | |
229 | sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)), | |
230 | card); | |
231 | /* DMA enable */ | |
232 | sca_out(DSR_DE, DSR_RX(phy_node(port)), card); | |
233 | } else { /* Transmit */ | |
234 | /* Chain mode, Multi-frame */ | |
235 | sca_out(0x14, DMR_TX(phy_node(port)), card); | |
236 | /* enable underflow interrupts */ | |
237 | sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card); | |
238 | } | |
239 | } | |
240 | ||
241 | hdlc_set_carrier(!(sca_in(get_msci(port) + ST3, card) & ST3_DCD), | |
242 | port_to_dev(port)); | |
243 | } | |
244 | ||
245 | ||
246 | ||
247 | #ifdef NEED_SCA_MSCI_INTR | |
248 | /* MSCI interrupt service */ | |
249 | static inline void sca_msci_intr(port_t *port) | |
250 | { | |
251 | u16 msci = get_msci(port); | |
252 | card_t* card = port_to_card(port); | |
253 | u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */ | |
254 | ||
255 | /* Reset MSCI TX underrun and CDCD status bit */ | |
256 | sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card); | |
257 | ||
258 | if (stat & ST1_UDRN) { | |
259 | struct net_device_stats *stats = hdlc_stats(port_to_dev(port)); | |
260 | stats->tx_errors++; /* TX Underrun error detected */ | |
261 | stats->tx_fifo_errors++; | |
262 | } | |
263 | ||
264 | if (stat & ST1_CDCD) | |
265 | hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD), | |
266 | port_to_dev(port)); | |
267 | } | |
268 | #endif | |
269 | ||
270 | ||
271 | ||
272 | static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, u16 rxin) | |
273 | { | |
274 | struct net_device *dev = port_to_dev(port); | |
275 | struct net_device_stats *stats = hdlc_stats(dev); | |
276 | struct sk_buff *skb; | |
277 | u16 len; | |
278 | u32 buff; | |
279 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
280 | u32 maxlen; | |
281 | u8 page; | |
282 | #endif | |
283 | ||
284 | len = readw(&desc->len); | |
285 | skb = dev_alloc_skb(len); | |
286 | if (!skb) { | |
287 | stats->rx_dropped++; | |
288 | return; | |
289 | } | |
290 | ||
291 | buff = buffer_offset(port, rxin, 0); | |
292 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
293 | page = buff / winsize(card); | |
294 | buff = buff % winsize(card); | |
295 | maxlen = winsize(card) - buff; | |
296 | ||
297 | openwin(card, page); | |
298 | ||
299 | if (len > maxlen) { | |
300 | memcpy_fromio(skb->data, winbase(card) + buff, maxlen); | |
301 | openwin(card, page + 1); | |
302 | memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen); | |
303 | } else | |
304 | #endif | |
305 | memcpy_fromio(skb->data, winbase(card) + buff, len); | |
306 | ||
307 | #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) | |
308 | /* select pkt_desc table page back */ | |
309 | openwin(card, 0); | |
310 | #endif | |
311 | skb_put(skb, len); | |
312 | #ifdef DEBUG_PKT | |
313 | printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len); | |
314 | debug_frame(skb); | |
315 | #endif | |
316 | stats->rx_packets++; | |
317 | stats->rx_bytes += skb->len; | |
318 | dev->last_rx = jiffies; | |
319 | skb->protocol = hdlc_type_trans(skb, dev); | |
320 | netif_rx(skb); | |
321 | } | |
322 | ||
323 | ||
324 | ||
325 | /* Receive DMA interrupt service */ | |
326 | static inline void sca_rx_intr(port_t *port) | |
327 | { | |
328 | u16 dmac = get_dmac_rx(port); | |
329 | card_t *card = port_to_card(port); | |
330 | u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */ | |
331 | struct net_device_stats *stats = hdlc_stats(port_to_dev(port)); | |
332 | ||
333 | /* Reset DSR status bits */ | |
334 | sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, | |
335 | DSR_RX(phy_node(port)), card); | |
336 | ||
337 | if (stat & DSR_BOF) | |
338 | stats->rx_over_errors++; /* Dropped one or more frames */ | |
339 | ||
340 | while (1) { | |
341 | u32 desc_off = desc_offset(port, port->rxin, 0); | |
342 | pkt_desc __iomem *desc; | |
343 | u32 cda = sca_ina(dmac + CDAL, card); | |
344 | ||
345 | if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) | |
346 | break; /* No frame received */ | |
347 | ||
348 | desc = desc_address(port, port->rxin, 0); | |
349 | stat = readb(&desc->stat); | |
350 | if (!(stat & ST_RX_EOM)) | |
351 | port->rxpart = 1; /* partial frame received */ | |
352 | else if ((stat & ST_ERROR_MASK) || port->rxpart) { | |
353 | stats->rx_errors++; | |
354 | if (stat & ST_RX_OVERRUN) stats->rx_fifo_errors++; | |
355 | else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | | |
356 | ST_RX_RESBIT)) || port->rxpart) | |
357 | stats->rx_frame_errors++; | |
358 | else if (stat & ST_RX_CRC) stats->rx_crc_errors++; | |
359 | if (stat & ST_RX_EOM) | |
360 | port->rxpart = 0; /* received last fragment */ | |
361 | } else | |
362 | sca_rx(card, port, desc, port->rxin); | |
363 | ||
364 | /* Set new error descriptor address */ | |
365 | sca_outa(desc_off, dmac + EDAL, card); | |
366 | port->rxin = next_desc(port, port->rxin, 0); | |
367 | } | |
368 | ||
369 | /* make sure RX DMA is enabled */ | |
370 | sca_out(DSR_DE, DSR_RX(phy_node(port)), card); | |
371 | } | |
372 | ||
373 | ||
374 | ||
375 | /* Transmit DMA interrupt service */ | |
376 | static inline void sca_tx_intr(port_t *port) | |
377 | { | |
378 | struct net_device *dev = port_to_dev(port); | |
379 | struct net_device_stats *stats = hdlc_stats(dev); | |
380 | u16 dmac = get_dmac_tx(port); | |
381 | card_t* card = port_to_card(port); | |
382 | u8 stat; | |
383 | ||
384 | spin_lock(&port->lock); | |
385 | ||
386 | stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */ | |
387 | ||
388 | /* Reset DSR status bits */ | |
389 | sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, | |
390 | DSR_TX(phy_node(port)), card); | |
391 | ||
392 | while (1) { | |
393 | pkt_desc __iomem *desc; | |
394 | ||
395 | u32 desc_off = desc_offset(port, port->txlast, 1); | |
396 | u32 cda = sca_ina(dmac + CDAL, card); | |
397 | if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) | |
398 | break; /* Transmitter is/will_be sending this frame */ | |
399 | ||
400 | desc = desc_address(port, port->txlast, 1); | |
401 | stats->tx_packets++; | |
402 | stats->tx_bytes += readw(&desc->len); | |
403 | writeb(0, &desc->stat); /* Free descriptor */ | |
404 | port->txlast = next_desc(port, port->txlast, 1); | |
405 | } | |
406 | ||
407 | netif_wake_queue(dev); | |
408 | spin_unlock(&port->lock); | |
409 | } | |
410 | ||
411 | ||
412 | ||
413 | static irqreturn_t sca_intr(int irq, void* dev_id, struct pt_regs *regs) | |
414 | { | |
415 | card_t *card = dev_id; | |
416 | int i; | |
417 | u8 stat; | |
418 | int handled = 0; | |
419 | ||
420 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
421 | u8 page = sca_get_page(card); | |
422 | #endif | |
423 | ||
424 | while((stat = sca_intr_status(card)) != 0) { | |
425 | handled = 1; | |
426 | for (i = 0; i < 2; i++) { | |
427 | port_t *port = get_port(card, i); | |
428 | if (port) { | |
429 | if (stat & SCA_INTR_MSCI(i)) | |
430 | sca_msci_intr(port); | |
431 | ||
432 | if (stat & SCA_INTR_DMAC_RX(i)) | |
433 | sca_rx_intr(port); | |
434 | ||
435 | if (stat & SCA_INTR_DMAC_TX(i)) | |
436 | sca_tx_intr(port); | |
437 | } | |
438 | } | |
439 | } | |
440 | ||
441 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
442 | openwin(card, page); /* Restore original page */ | |
443 | #endif | |
444 | return IRQ_RETVAL(handled); | |
445 | } | |
446 | ||
447 | ||
448 | ||
449 | static void sca_set_port(port_t *port) | |
450 | { | |
451 | card_t* card = port_to_card(port); | |
452 | u16 msci = get_msci(port); | |
453 | u8 md2 = sca_in(msci + MD2, card); | |
454 | unsigned int tmc, br = 10, brv = 1024; | |
455 | ||
456 | ||
457 | if (port->settings.clock_rate > 0) { | |
458 | /* Try lower br for better accuracy*/ | |
459 | do { | |
460 | br--; | |
461 | brv >>= 1; /* brv = 2^9 = 512 max in specs */ | |
462 | ||
463 | /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ | |
464 | tmc = CLOCK_BASE / brv / port->settings.clock_rate; | |
465 | }while (br > 1 && tmc <= 128); | |
466 | ||
467 | if (tmc < 1) { | |
468 | tmc = 1; | |
469 | br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ | |
470 | brv = 1; | |
471 | } else if (tmc > 255) | |
472 | tmc = 256; /* tmc=0 means 256 - low baud rates */ | |
473 | ||
474 | port->settings.clock_rate = CLOCK_BASE / brv / tmc; | |
475 | } else { | |
476 | br = 9; /* Minimum clock rate */ | |
477 | tmc = 256; /* 8bit = 0 */ | |
478 | port->settings.clock_rate = CLOCK_BASE / (256 * 512); | |
479 | } | |
480 | ||
481 | port->rxs = (port->rxs & ~CLK_BRG_MASK) | br; | |
482 | port->txs = (port->txs & ~CLK_BRG_MASK) | br; | |
483 | port->tmc = tmc; | |
484 | ||
485 | /* baud divisor - time constant*/ | |
486 | #ifdef __HD64570_H | |
487 | sca_out(port->tmc, msci + TMC, card); | |
488 | #else | |
489 | sca_out(port->tmc, msci + TMCR, card); | |
490 | sca_out(port->tmc, msci + TMCT, card); | |
491 | #endif | |
492 | ||
493 | /* Set BRG bits */ | |
494 | sca_out(port->rxs, msci + RXS, card); | |
495 | sca_out(port->txs, msci + TXS, card); | |
496 | ||
497 | if (port->settings.loopback) | |
498 | md2 |= MD2_LOOPBACK; | |
499 | else | |
500 | md2 &= ~MD2_LOOPBACK; | |
501 | ||
502 | sca_out(md2, msci + MD2, card); | |
503 | ||
504 | } | |
505 | ||
506 | ||
507 | ||
508 | static void sca_open(struct net_device *dev) | |
509 | { | |
510 | port_t *port = dev_to_port(dev); | |
511 | card_t* card = port_to_card(port); | |
512 | u16 msci = get_msci(port); | |
513 | u8 md0, md2; | |
514 | ||
515 | switch(port->encoding) { | |
516 | case ENCODING_NRZ: md2 = MD2_NRZ; break; | |
517 | case ENCODING_NRZI: md2 = MD2_NRZI; break; | |
518 | case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break; | |
519 | case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break; | |
520 | default: md2 = MD2_MANCHESTER; | |
521 | } | |
522 | ||
523 | if (port->settings.loopback) | |
524 | md2 |= MD2_LOOPBACK; | |
525 | ||
526 | switch(port->parity) { | |
527 | case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break; | |
528 | case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break; | |
529 | #ifdef __HD64570_H | |
530 | case PARITY_CRC16_PR0_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU_0; break; | |
531 | #else | |
532 | case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break; | |
533 | #endif | |
534 | case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break; | |
535 | default: md0 = MD0_HDLC | MD0_CRC_NONE; | |
536 | } | |
537 | ||
538 | sca_out(CMD_RESET, msci + CMD, card); | |
539 | sca_out(md0, msci + MD0, card); | |
540 | sca_out(0x00, msci + MD1, card); /* no address field check */ | |
541 | sca_out(md2, msci + MD2, card); | |
542 | sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */ | |
543 | #ifdef __HD64570_H | |
544 | sca_out(CTL_IDLE, msci + CTL, card); | |
545 | #else | |
546 | /* Skip the rest of underrun frame */ | |
547 | sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card); | |
548 | #endif | |
549 | ||
550 | #ifdef __HD64570_H | |
551 | /* Allow at least 8 bytes before requesting RX DMA operation */ | |
552 | /* TX with higher priority and possibly with shorter transfers */ | |
553 | sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/ | |
554 | sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/ | |
555 | sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */ | |
556 | #else | |
557 | sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */ | |
558 | sca_out(0x3C, msci + TFS, card); /* +1 = TX start */ | |
559 | sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */ | |
560 | sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */ | |
561 | sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/ | |
562 | #endif | |
563 | ||
564 | /* We're using the following interrupts: | |
565 | - TXINT (DMAC completed all transmisions, underrun or DCD change) | |
566 | - all DMA interrupts | |
567 | */ | |
568 | ||
569 | hdlc_set_carrier(!(sca_in(msci + ST3, card) & ST3_DCD), dev); | |
570 | ||
571 | #ifdef __HD64570_H | |
572 | /* MSCI TX INT and RX INT A IRQ enable */ | |
573 | sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card); | |
574 | sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card); | |
575 | sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C), | |
576 | IER0, card); /* TXINT and RXINT */ | |
577 | /* enable DMA IRQ */ | |
578 | sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F), | |
579 | IER1, card); | |
580 | #else | |
581 | /* MSCI TXINT and RXINTA interrupt enable */ | |
582 | sca_outl(IE0_TXINT | IE0_RXINTA | IE0_UDRN | IE0_CDCD, msci + IE0, | |
583 | card); | |
584 | /* DMA & MSCI IRQ enable */ | |
585 | sca_outl(sca_inl(IER0, card) | | |
586 | (phy_node(port) ? 0x0A006600 : 0x000A0066), IER0, card); | |
587 | #endif | |
588 | ||
589 | #ifdef __HD64570_H | |
590 | sca_out(port->tmc, msci + TMC, card); /* Restore registers */ | |
591 | #else | |
592 | sca_out(port->tmc, msci + TMCR, card); | |
593 | sca_out(port->tmc, msci + TMCT, card); | |
594 | #endif | |
595 | sca_out(port->rxs, msci + RXS, card); | |
596 | sca_out(port->txs, msci + TXS, card); | |
597 | sca_out(CMD_TX_ENABLE, msci + CMD, card); | |
598 | sca_out(CMD_RX_ENABLE, msci + CMD, card); | |
599 | ||
600 | netif_start_queue(dev); | |
601 | } | |
602 | ||
603 | ||
604 | ||
605 | static void sca_close(struct net_device *dev) | |
606 | { | |
607 | port_t *port = dev_to_port(dev); | |
608 | card_t* card = port_to_card(port); | |
609 | ||
610 | /* reset channel */ | |
611 | sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port)); | |
612 | #ifdef __HD64570_H | |
613 | /* disable MSCI interrupts */ | |
614 | sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0), | |
615 | IER0, card); | |
616 | /* disable DMA interrupts */ | |
617 | sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0), | |
618 | IER1, card); | |
619 | #else | |
620 | /* disable DMA & MSCI IRQ */ | |
621 | sca_outl(sca_inl(IER0, card) & | |
622 | (phy_node(port) ? 0x00FF00FF : 0xFF00FF00), IER0, card); | |
623 | #endif | |
624 | netif_stop_queue(dev); | |
625 | } | |
626 | ||
627 | ||
628 | ||
629 | static int sca_attach(struct net_device *dev, unsigned short encoding, | |
630 | unsigned short parity) | |
631 | { | |
632 | if (encoding != ENCODING_NRZ && | |
633 | encoding != ENCODING_NRZI && | |
634 | encoding != ENCODING_FM_MARK && | |
635 | encoding != ENCODING_FM_SPACE && | |
636 | encoding != ENCODING_MANCHESTER) | |
637 | return -EINVAL; | |
638 | ||
639 | if (parity != PARITY_NONE && | |
640 | parity != PARITY_CRC16_PR0 && | |
641 | parity != PARITY_CRC16_PR1 && | |
642 | #ifdef __HD64570_H | |
643 | parity != PARITY_CRC16_PR0_CCITT && | |
644 | #else | |
645 | parity != PARITY_CRC32_PR1_CCITT && | |
646 | #endif | |
647 | parity != PARITY_CRC16_PR1_CCITT) | |
648 | return -EINVAL; | |
649 | ||
650 | dev_to_port(dev)->encoding = encoding; | |
651 | dev_to_port(dev)->parity = parity; | |
652 | return 0; | |
653 | } | |
654 | ||
655 | ||
656 | ||
657 | #ifdef DEBUG_RINGS | |
658 | static void sca_dump_rings(struct net_device *dev) | |
659 | { | |
660 | port_t *port = dev_to_port(dev); | |
661 | card_t *card = port_to_card(port); | |
662 | u16 cnt; | |
663 | #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) | |
664 | u8 page; | |
665 | #endif | |
666 | ||
667 | #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) | |
668 | page = sca_get_page(card); | |
669 | openwin(card, 0); | |
670 | #endif | |
671 | ||
672 | printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive", | |
673 | sca_ina(get_dmac_rx(port) + CDAL, card), | |
674 | sca_ina(get_dmac_rx(port) + EDAL, card), | |
675 | sca_in(DSR_RX(phy_node(port)), card), port->rxin, | |
676 | sca_in(DSR_RX(phy_node(port)), card) & DSR_DE?"":"in"); | |
677 | for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++) | |
678 | printk(" %02X", readb(&(desc_address(port, cnt, 0)->stat))); | |
679 | ||
680 | printk("\n" KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u " | |
681 | "last=%u %sactive", | |
682 | sca_ina(get_dmac_tx(port) + CDAL, card), | |
683 | sca_ina(get_dmac_tx(port) + EDAL, card), | |
684 | sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast, | |
685 | sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in"); | |
686 | ||
687 | for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++) | |
688 | printk(" %02X", readb(&(desc_address(port, cnt, 1)->stat))); | |
689 | printk("\n"); | |
690 | ||
691 | printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, " | |
692 | "ST: %02x %02x %02x %02x" | |
693 | #ifdef __HD64572_H | |
694 | " %02x" | |
695 | #endif | |
696 | ", FST: %02x CST: %02x %02x\n", | |
697 | sca_in(get_msci(port) + MD0, card), | |
698 | sca_in(get_msci(port) + MD1, card), | |
699 | sca_in(get_msci(port) + MD2, card), | |
700 | sca_in(get_msci(port) + ST0, card), | |
701 | sca_in(get_msci(port) + ST1, card), | |
702 | sca_in(get_msci(port) + ST2, card), | |
703 | sca_in(get_msci(port) + ST3, card), | |
704 | #ifdef __HD64572_H | |
705 | sca_in(get_msci(port) + ST4, card), | |
706 | #endif | |
707 | sca_in(get_msci(port) + FST, card), | |
708 | sca_in(get_msci(port) + CST0, card), | |
709 | sca_in(get_msci(port) + CST1, card)); | |
710 | ||
711 | #ifdef __HD64572_H | |
712 | printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card), | |
713 | sca_inl(ISR0, card), sca_inl(ISR1, card)); | |
714 | #else | |
715 | printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card), | |
716 | sca_in(ISR1, card), sca_in(ISR2, card)); | |
717 | #endif | |
718 | ||
719 | #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) | |
720 | openwin(card, page); /* Restore original page */ | |
721 | #endif | |
722 | } | |
723 | #endif /* DEBUG_RINGS */ | |
724 | ||
725 | ||
726 | ||
727 | static int sca_xmit(struct sk_buff *skb, struct net_device *dev) | |
728 | { | |
729 | port_t *port = dev_to_port(dev); | |
730 | card_t *card = port_to_card(port); | |
731 | pkt_desc __iomem *desc; | |
732 | u32 buff, len; | |
733 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
734 | u8 page; | |
735 | u32 maxlen; | |
736 | #endif | |
737 | ||
738 | spin_lock_irq(&port->lock); | |
739 | ||
740 | desc = desc_address(port, port->txin + 1, 1); | |
741 | if (readb(&desc->stat)) { /* allow 1 packet gap */ | |
742 | /* should never happen - previous xmit should stop queue */ | |
743 | #ifdef DEBUG_PKT | |
744 | printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name); | |
745 | #endif | |
746 | netif_stop_queue(dev); | |
747 | spin_unlock_irq(&port->lock); | |
748 | return 1; /* request packet to be queued */ | |
749 | } | |
750 | ||
751 | #ifdef DEBUG_PKT | |
752 | printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); | |
753 | debug_frame(skb); | |
754 | #endif | |
755 | ||
756 | desc = desc_address(port, port->txin, 1); | |
757 | buff = buffer_offset(port, port->txin, 1); | |
758 | len = skb->len; | |
759 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
760 | page = buff / winsize(card); | |
761 | buff = buff % winsize(card); | |
762 | maxlen = winsize(card) - buff; | |
763 | ||
764 | openwin(card, page); | |
765 | if (len > maxlen) { | |
766 | memcpy_toio(winbase(card) + buff, skb->data, maxlen); | |
767 | openwin(card, page + 1); | |
768 | memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen); | |
769 | } | |
770 | else | |
771 | #endif | |
772 | memcpy_toio(winbase(card) + buff, skb->data, len); | |
773 | ||
774 | #if !defined(PAGE0_ALWAYS_MAPPED) && !defined(ALL_PAGES_ALWAYS_MAPPED) | |
775 | openwin(card, 0); /* select pkt_desc table page back */ | |
776 | #endif | |
777 | writew(len, &desc->len); | |
778 | writeb(ST_TX_EOM, &desc->stat); | |
779 | dev->trans_start = jiffies; | |
780 | ||
781 | port->txin = next_desc(port, port->txin, 1); | |
782 | sca_outa(desc_offset(port, port->txin, 1), | |
783 | get_dmac_tx(port) + EDAL, card); | |
784 | ||
785 | sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */ | |
786 | ||
787 | desc = desc_address(port, port->txin + 1, 1); | |
788 | if (readb(&desc->stat)) /* allow 1 packet gap */ | |
789 | netif_stop_queue(dev); | |
790 | ||
791 | spin_unlock_irq(&port->lock); | |
792 | ||
793 | dev_kfree_skb(skb); | |
794 | return 0; | |
795 | } | |
796 | ||
797 | ||
798 | ||
799 | #ifdef NEED_DETECT_RAM | |
800 | static u32 __devinit sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize) | |
801 | { | |
802 | /* Round RAM size to 32 bits, fill from end to start */ | |
803 | u32 i = ramsize &= ~3; | |
804 | ||
805 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
806 | u32 size = winsize(card); | |
807 | ||
808 | openwin(card, (i - 4) / size); /* select last window */ | |
809 | #endif | |
810 | do { | |
811 | i -= 4; | |
812 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
813 | if ((i + 4) % size == 0) | |
814 | openwin(card, i / size); | |
815 | writel(i ^ 0x12345678, rambase + i % size); | |
816 | #else | |
817 | writel(i ^ 0x12345678, rambase + i); | |
818 | #endif | |
819 | }while (i > 0); | |
820 | ||
821 | for (i = 0; i < ramsize ; i += 4) { | |
822 | #ifndef ALL_PAGES_ALWAYS_MAPPED | |
823 | if (i % size == 0) | |
824 | openwin(card, i / size); | |
825 | ||
826 | if (readl(rambase + i % size) != (i ^ 0x12345678)) | |
827 | break; | |
828 | #else | |
829 | if (readl(rambase + i) != (i ^ 0x12345678)) | |
830 | break; | |
831 | #endif | |
832 | } | |
833 | ||
834 | return i; | |
835 | } | |
836 | #endif /* NEED_DETECT_RAM */ | |
837 | ||
838 | ||
839 | ||
840 | static void __devinit sca_init(card_t *card, int wait_states) | |
841 | { | |
842 | sca_out(wait_states, WCRL, card); /* Wait Control */ | |
843 | sca_out(wait_states, WCRM, card); | |
844 | sca_out(wait_states, WCRH, card); | |
845 | ||
846 | sca_out(0, DMER, card); /* DMA Master disable */ | |
847 | sca_out(0x03, PCR, card); /* DMA priority */ | |
848 | sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */ | |
849 | sca_out(0, DSR_TX(0), card); | |
850 | sca_out(0, DSR_RX(1), card); | |
851 | sca_out(0, DSR_TX(1), card); | |
852 | sca_out(DMER_DME, DMER, card); /* DMA Master enable */ | |
853 | } |