WAN: Remove dead code from PC300 driver, part #2
[deliverable/linux.git] / drivers / net / wan / pc300.h
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1/*
2 * pc300.h Cyclades-PC300(tm) Kernel API Definitions.
3 *
4 * Author: Ivan Passos <ivan@cyclades.com>
5 *
6 * Copyright: (c) 1999-2002 Cyclades Corp.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 * $Log: pc300.h,v $
14 * Revision 3.12 2002/03/07 14:17:09 henrique
15 * License data fixed
16 *
17 * Revision 3.11 2002/01/28 21:09:39 daniela
18 * Included ';' after pc300hw.bus.
19 *
20 * Revision 3.10 2002/01/17 17:58:52 ivan
21 * Support for PC300-TE/M (PMC).
22 *
23 * Revision 3.9 2001/09/28 13:30:53 daniela
24 * Renamed dma_start routine to rx_dma_start.
25 *
26 * Revision 3.8 2001/09/24 13:03:45 daniela
27 * Fixed BOF interrupt treatment. Created dma_start routine.
28 *
29 * Revision 3.7 2001/08/10 17:19:58 daniela
30 * Fixed IOCTLs defines.
31 *
32 * Revision 3.6 2001/07/18 19:24:42 daniela
33 * Included kernel version.
34 *
35 * Revision 3.5 2001/07/05 18:38:08 daniela
36 * DMA transmission bug fix.
37 *
38 * Revision 3.4 2001/06/26 17:10:40 daniela
39 * New configuration parameters (line code, CRC calculation and clock).
40 *
41 * Revision 3.3 2001/06/22 13:13:02 regina
42 * MLPPP implementation
43 *
44 * Revision 3.2 2001/06/18 17:56:09 daniela
45 * Increased DEF_MTU and TX_QUEUE_LEN.
46 *
47 * Revision 3.1 2001/06/15 12:41:10 regina
48 * upping major version number
49 *
50 * Revision 1.1.1.1 2001/06/13 20:25:06 daniela
51 * PC300 initial CVS version (3.4.0-pre1)
52 *
53 * Revision 2.3 2001/03/05 daniela
54 * Created struct pc300conf, to provide the hardware information to pc300util.
55 * Inclusion of 'alloc_ramsize' field on structure 'pc300hw'.
56 *
57 * Revision 2.2 2000/12/22 daniela
58 * Structures and defines to support pc300util: statistics, status,
59 * loopback tests, trace.
60 *
61 * Revision 2.1 2000/09/28 ivan
62 * Inclusion of 'iophys' and 'iosize' fields on structure 'pc300hw', to
63 * allow release of I/O region at module unload.
64 * Changed location of include files.
65 *
66 * Revision 2.0 2000/03/27 ivan
67 * Added support for the PC300/TE cards.
68 *
69 * Revision 1.1 2000/01/31 ivan
70 * Replaced 'pc300[drv|sca].h' former PC300 driver include files.
71 *
72 * Revision 1.0 1999/12/16 ivan
73 * First official release.
74 * Inclusion of 'nchan' field on structure 'pc300hw', to allow variable
75 * number of ports per card.
76 * Inclusion of 'if_ptr' field on structure 'pc300dev'.
77 *
78 * Revision 0.6 1999/11/17 ivan
79 * Changed X.25-specific function names to comply with adopted convention.
80 *
81 * Revision 0.5 1999/11/16 Daniela Squassoni
82 * X.25 support.
83 *
84 * Revision 0.4 1999/11/15 ivan
85 * Inclusion of 'clock' field on structure 'pc300hw'.
86 *
87 * Revision 0.3 1999/11/10 ivan
88 * IOCTL name changing.
89 * Inclusion of driver function prototypes.
90 *
91 * Revision 0.2 1999/11/03 ivan
92 * Inclusion of 'tx_skb' and union 'ifu' on structure 'pc300dev'.
93 *
94 * Revision 0.1 1999/01/15 ivan
95 * Initial version.
96 *
97 */
98
99#ifndef _PC300_H
100#define _PC300_H
101
102#include <linux/hdlc.h>
103#include "hd64572.h"
104#include "pc300-falc-lh.h"
105
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106typedef __u32 uclong; /* 32 bits, unsigned */
107typedef __u16 ucshort; /* 16 bits, unsigned */
108typedef __u8 ucchar; /* 8 bits, unsigned */
1da177e4 109
ea966165 110#define PC300_PROTO_MLPPP 1
1da177e4 111
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112#define PC300_MAXCHAN 2 /* Number of channels per card */
113
1da177e4 114#define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */
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115#define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */
116
117#define PC300_OSC_CLOCK 24576000
118#define PC300_PCI_CLOCK 33000000
119
120#define BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */
121#define DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */
122#define DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */
123
124#define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */
125#define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */
126
127/* DMA Buffer Offsets */
128#define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \
129 PC300_MAXCHAN * sizeof(pcsca_bd_t))
130#define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ)
131
132/* DMA Descriptor Offsets */
133#define DMA_TX_BD_BASE 0x0000
134#define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \
135 BD_DEF_LEN) * sizeof(pcsca_bd_t)))
136
137/* DMA Descriptor Macros */
138#define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \
139 ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t))
140#define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \
141 ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t))
142
143/* Macro to access the FALC registers (TE only) */
144#define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2))
145
146/***************************************
147 * Memory access functions/macros *
148 * (required to support Alpha systems) *
149 ***************************************/
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150#define cpc_writeb(port,val) {writeb((ucchar)(val),(port)); mb();}
151#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();}
152#define cpc_writel(port,val) {writel((uclong)(val),(port)); mb();}
153
154#define cpc_readb(port) readb(port)
155#define cpc_readw(port) readw(port)
156#define cpc_readl(port) readl(port)
157
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158/****** Data Structures *****************************************************/
159
160/*
161 * RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime
162 * registers. This structure can be used to access the 9050 registers
163 * (memory mapped).
164 */
165struct RUNTIME_9050 {
166 uclong loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
167 uclong loc_rom_range; /* 10h : Local ROM Range */
168 uclong loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
169 uclong loc_rom_base; /* 24h : Local ROM Base */
170 uclong loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
171 uclong rom_bus_descr; /* 38h : ROM Bus Descriptor */
172 uclong cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
173 uclong intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
174 uclong init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
175};
176
177#define PLX_9050_LINT1_ENABLE 0x01
178#define PLX_9050_LINT1_POL 0x02
179#define PLX_9050_LINT1_STATUS 0x04
180#define PLX_9050_LINT2_ENABLE 0x08
181#define PLX_9050_LINT2_POL 0x10
182#define PLX_9050_LINT2_STATUS 0x20
183#define PLX_9050_INTR_ENABLE 0x40
184#define PLX_9050_SW_INTR 0x80
185
186/* Masks to access the init_ctrl PLX register */
187#define PC300_CLKSEL_MASK (0x00000004UL)
188#define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3))
189#define PC300_CTYPE_MASK (0x00000800UL)
190
191/* CPLD Registers (base addr = falcbase, TE only) */
192/* CPLD v. 0 */
193#define CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */
194#define CPLD_REG2 0x144 /* Clock enable , LED control */
195/* CPLD v. 2 or higher */
196#define CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */
197#define CPLD_V2_REG2 0x104 /* Clock enable , LED control */
198#define CPLD_ID_REG 0x108 /* CPLD version */
199
200/* CPLD Register bit description: for the FALC bits, they should always be
201 set based on the channel (use (bit<<(2*ch)) to access the correct bit for
202 that channel) */
203#define CPLD_REG1_FALC_RESET 0x01
204#define CPLD_REG1_SCA_RESET 0x02
205#define CPLD_REG1_GLOBAL_CLK 0x08
206#define CPLD_REG1_FALC_DCD 0x10
207#define CPLD_REG1_FALC_CTS 0x20
208
209#define CPLD_REG2_FALC_TX_CLK 0x01
210#define CPLD_REG2_FALC_RX_CLK 0x02
211#define CPLD_REG2_FALC_LED1 0x10
212#define CPLD_REG2_FALC_LED2 0x20
213
214/* Structure with FALC-related fields (TE only) */
215#define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */
216
217typedef struct falc {
218 ucchar sync; /* If true FALC is synchronized */
219 ucchar active; /* if TRUE then already active */
220 ucchar loop_active; /* if TRUE a line loopback UP was received */
221 ucchar loop_gen; /* if TRUE a line loopback UP was issued */
222
223 ucchar num_channels;
224 ucchar offset; /* 1 for T1, 0 for E1 */
225 ucchar full_bandwidth;
226
227 ucchar xmb_cause;
228 ucchar multiframe_mode;
229
230 /* Statistics */
231 ucshort pden; /* Pulse Density violation count */
232 ucshort los; /* Loss of Signal count */
233 ucshort losr; /* Loss of Signal recovery count */
234 ucshort lfa; /* Loss of frame alignment count */
235 ucshort farec; /* Frame Alignment Recovery count */
236 ucshort lmfa; /* Loss of multiframe alignment count */
237 ucshort ais; /* Remote Alarm indication Signal count */
238 ucshort sec; /* One-second timer */
239 ucshort es; /* Errored second */
240 ucshort rai; /* remote alarm received */
241 ucshort bec;
242 ucshort fec;
243 ucshort cvc;
244 ucshort cec;
245 ucshort ebc;
246
247 /* Status */
248 ucchar red_alarm;
249 ucchar blue_alarm;
250 ucchar loss_fa;
251 ucchar yellow_alarm;
252 ucchar loss_mfa;
253 ucchar prbs;
254} falc_t;
255
256typedef struct falc_status {
257 ucchar sync; /* If true FALC is synchronized */
258 ucchar red_alarm;
259 ucchar blue_alarm;
260 ucchar loss_fa;
261 ucchar yellow_alarm;
262 ucchar loss_mfa;
263 ucchar prbs;
264} falc_status_t;
265
266typedef struct rsv_x21_status {
267 ucchar dcd;
268 ucchar dsr;
269 ucchar cts;
270 ucchar rts;
271 ucchar dtr;
272} rsv_x21_status_t;
273
274typedef struct pc300stats {
275 int hw_type;
276 uclong line_on;
277 uclong line_off;
278 struct net_device_stats gen_stats;
279 falc_t te_stats;
280} pc300stats_t;
281
282typedef struct pc300status {
283 int hw_type;
284 rsv_x21_status_t gen_status;
285 falc_status_t te_status;
286} pc300status_t;
287
288typedef struct pc300loopback {
289 char loop_type;
290 char loop_on;
291} pc300loopback_t;
292
293typedef struct pc300patterntst {
294 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */
295 ucshort num_errors;
296} pc300patterntst_t;
297
298typedef struct pc300dev {
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299 struct pc300ch *chan;
300 ucchar trace_on;
301 uclong line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
302 uclong line_off;
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303 char name[16];
304 struct net_device *dev;
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305#ifdef CONFIG_PC300_MLPPP
306 void *cpc_tty; /* information to PC300 TTY driver */
307#endif
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308}pc300dev_t;
309
310typedef struct pc300hw {
311 int type; /* RSV, X21, etc. */
312 int bus; /* Bus (PCI, PMC, etc.) */
313 int nchan; /* number of channels */
314 int irq; /* interrupt request level */
315 uclong clock; /* Board clock */
316 ucchar cpld_id; /* CPLD ID (TE only) */
317 ucshort cpld_reg1; /* CPLD reg 1 (TE only) */
318 ucshort cpld_reg2; /* CPLD reg 2 (TE only) */
319 ucshort gpioc_reg; /* PLX GPIOC reg */
320 ucshort intctl_reg; /* PLX Int Ctrl/Status reg */
321 uclong iophys; /* PLX registers I/O base */
322 uclong iosize; /* PLX registers I/O size */
323 uclong plxphys; /* PLX registers MMIO base (physical) */
324 void __iomem * plxbase; /* PLX registers MMIO base (virtual) */
325 uclong plxsize; /* PLX registers MMIO size */
326 uclong scaphys; /* SCA registers MMIO base (physical) */
327 void __iomem * scabase; /* SCA registers MMIO base (virtual) */
328 uclong scasize; /* SCA registers MMIO size */
329 uclong ramphys; /* On-board RAM MMIO base (physical) */
330 void __iomem * rambase; /* On-board RAM MMIO base (virtual) */
331 uclong alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
332 uclong ramsize; /* On-board RAM MMIO size */
333 uclong falcphys; /* FALC registers MMIO base (physical) */
334 void __iomem * falcbase;/* FALC registers MMIO base (virtual) */
335 uclong falcsize; /* FALC registers MMIO size */
336} pc300hw_t;
337
338typedef struct pc300chconf {
339 sync_serial_settings phys_settings; /* Clock type/rate (in bps),
340 loopback mode */
341 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */
342 uclong media; /* HW media (RS232, V.35, etc.) */
343 uclong proto; /* Protocol (PPP, X.25, etc.) */
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344
345 /* TE-specific parameters */
346 ucchar lcode; /* Line Code (AMI, B8ZS, etc.) */
347 ucchar fr_mode; /* Frame Mode (ESF, D4, etc.) */
348 ucchar lbo; /* Line Build Out */
349 ucchar rx_sens; /* Rx Sensitivity (long- or short-haul) */
350 uclong tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
351} pc300chconf_t;
352
353typedef struct pc300ch {
354 struct pc300 *card;
355 int channel;
356 pc300dev_t d;
357 pc300chconf_t conf;
358 ucchar tx_first_bd; /* First TX DMA block descr. w/ data */
359 ucchar tx_next_bd; /* Next free TX DMA block descriptor */
360 ucchar rx_first_bd; /* First free RX DMA block descriptor */
361 ucchar rx_last_bd; /* Last free RX DMA block descriptor */
362 ucchar nfree_tx_bd; /* Number of free TX DMA block descriptors */
363 falc_t falc; /* FALC structure (TE only) */
364} pc300ch_t;
365
366typedef struct pc300 {
367 pc300hw_t hw; /* hardware config. */
368 pc300ch_t chan[PC300_MAXCHAN];
1da177e4 369 spinlock_t card_lock;
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370} pc300_t;
371
372typedef struct pc300conf {
373 pc300hw_t hw;
374 pc300chconf_t conf;
375} pc300conf_t;
376
377/* DEV ioctl() commands */
378#define N_SPPP_IOCTLS 2
379
380enum pc300_ioctl_cmds {
381 SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS),
382 SIOCGPC300CONF,
383 SIOCSPC300CONF,
384 SIOCGPC300STATUS,
385 SIOCGPC300FALCSTATUS,
386 SIOCGPC300UTILSTATS,
387 SIOCGPC300UTILSTATUS,
388 SIOCSPC300TRACE,
389 SIOCSPC300LOOPBACK,
390 SIOCSPC300PATTERNTEST,
391};
392
393/* Loopback types - PC300/TE boards */
394enum pc300_loopback_cmds {
395 PC300LOCLOOP = 1,
396 PC300REMLOOP,
397 PC300PAYLOADLOOP,
398 PC300GENLOOPUP,
399 PC300GENLOOPDOWN,
400};
401
402/* Control Constant Definitions */
403#define PC300_RSV 0x01
404#define PC300_X21 0x02
405#define PC300_TE 0x03
406
407#define PC300_PCI 0x00
408#define PC300_PMC 0x01
409
410#define PC300_LC_AMI 0x01
411#define PC300_LC_B8ZS 0x02
412#define PC300_LC_NRZ 0x03
413#define PC300_LC_HDB3 0x04
414
415/* Framing (T1) */
416#define PC300_FR_ESF 0x01
417#define PC300_FR_D4 0x02
418#define PC300_FR_ESF_JAPAN 0x03
419
420/* Framing (E1) */
421#define PC300_FR_MF_CRC4 0x04
422#define PC300_FR_MF_NON_CRC4 0x05
423#define PC300_FR_UNFRAMED 0x06
424
425#define PC300_LBO_0_DB 0x00
426#define PC300_LBO_7_5_DB 0x01
427#define PC300_LBO_15_DB 0x02
428#define PC300_LBO_22_5_DB 0x03
429
430#define PC300_RX_SENS_SH 0x01
431#define PC300_RX_SENS_LH 0x02
432
433#define PC300_TX_TIMEOUT (2*HZ)
434#define PC300_TX_QUEUE_LEN 100
435#define PC300_DEF_MTU 1600
436
1da177e4 437/* Function Prototypes */
1da177e4 438int cpc_open(struct net_device *dev);
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439
440#endif /* _PC300_H */
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