Commit | Line | Data |
---|---|---|
5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
18 | #ifndef _CORE_H_ | |
19 | #define _CORE_H_ | |
20 | ||
21 | #include <linux/completion.h> | |
22 | #include <linux/if_ether.h> | |
23 | #include <linux/types.h> | |
24 | #include <linux/pci.h> | |
25 | ||
edb8236d | 26 | #include "htt.h" |
5e3dd157 KV |
27 | #include "htc.h" |
28 | #include "hw.h" | |
29 | #include "targaddrs.h" | |
30 | #include "wmi.h" | |
31 | #include "../ath.h" | |
32 | #include "../regd.h" | |
9702c686 | 33 | #include "../dfs_pattern_detector.h" |
5e3dd157 KV |
34 | |
35 | #define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB) | |
36 | #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) | |
37 | #define WO(_f) ((_f##_OFFSET) >> 2) | |
38 | ||
39 | #define ATH10K_SCAN_ID 0 | |
40 | #define WMI_READY_TIMEOUT (5 * HZ) | |
41 | #define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ) | |
2e1dea40 | 42 | #define ATH10K_NUM_CHANS 38 |
5e3dd157 KV |
43 | |
44 | /* Antenna noise floor */ | |
45 | #define ATH10K_DEFAULT_NOISE_FLOOR -95 | |
46 | ||
71098615 | 47 | #define ATH10K_MAX_NUM_MGMT_PENDING 128 |
5e00d31a | 48 | |
5a13e76e KV |
49 | /* number of failed packets */ |
50 | #define ATH10K_KICKOUT_THRESHOLD 50 | |
51 | ||
52 | /* | |
53 | * Use insanely high numbers to make sure that the firmware implementation | |
54 | * won't start, we have the same functionality already in hostapd. Unit | |
55 | * is seconds. | |
56 | */ | |
57 | #define ATH10K_KEEPALIVE_MIN_IDLE 3747 | |
58 | #define ATH10K_KEEPALIVE_MAX_IDLE 3895 | |
59 | #define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900 | |
60 | ||
5e3dd157 KV |
61 | struct ath10k; |
62 | ||
5e3dd157 KV |
63 | struct ath10k_skb_cb { |
64 | dma_addr_t paddr; | |
5e00d31a | 65 | u8 vdev_id; |
5e3dd157 KV |
66 | |
67 | struct { | |
5e3dd157 KV |
68 | u8 tid; |
69 | bool is_offchan; | |
a16942e6 MK |
70 | struct ath10k_htt_txbuf *txbuf; |
71 | u32 txbuf_paddr; | |
5e3dd157 | 72 | } __packed htt; |
748afc47 MK |
73 | |
74 | struct { | |
75 | bool dtim_zero; | |
76 | bool deliver_cab; | |
77 | } bcn; | |
5e3dd157 KV |
78 | } __packed; |
79 | ||
80 | static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb) | |
81 | { | |
82 | BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) > | |
83 | IEEE80211_TX_INFO_DRIVER_DATA_SIZE); | |
84 | return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; | |
85 | } | |
86 | ||
5e3dd157 KV |
87 | static inline u32 host_interest_item_address(u32 item_offset) |
88 | { | |
89 | return QCA988X_HOST_INTEREST_ADDRESS + item_offset; | |
90 | } | |
91 | ||
92 | struct ath10k_bmi { | |
93 | bool done_sent; | |
94 | }; | |
95 | ||
b3effe61 BM |
96 | #define ATH10K_MAX_MEM_REQS 16 |
97 | ||
98 | struct ath10k_mem_chunk { | |
99 | void *vaddr; | |
100 | dma_addr_t paddr; | |
101 | u32 len; | |
102 | u32 req_id; | |
103 | }; | |
104 | ||
5e3dd157 KV |
105 | struct ath10k_wmi { |
106 | enum ath10k_htc_ep_id eid; | |
107 | struct completion service_ready; | |
108 | struct completion unified_ready; | |
be8b3943 | 109 | wait_queue_head_t tx_credits_wq; |
ce42870e | 110 | struct wmi_cmd_map *cmd; |
6d1506e7 | 111 | struct wmi_vdev_param_map *vdev_param; |
226a339b | 112 | struct wmi_pdev_param_map *pdev_param; |
b3effe61 BM |
113 | |
114 | u32 num_mem_chunks; | |
115 | struct ath10k_mem_chunk mem_chunks[ATH10K_MAX_MEM_REQS]; | |
5e3dd157 KV |
116 | }; |
117 | ||
118 | struct ath10k_peer_stat { | |
119 | u8 peer_macaddr[ETH_ALEN]; | |
120 | u32 peer_rssi; | |
121 | u32 peer_tx_rate; | |
23c3aae4 | 122 | u32 peer_rx_rate; /* 10x only */ |
5e3dd157 KV |
123 | }; |
124 | ||
125 | struct ath10k_target_stats { | |
126 | /* PDEV stats */ | |
127 | s32 ch_noise_floor; | |
128 | u32 tx_frame_count; | |
129 | u32 rx_frame_count; | |
130 | u32 rx_clear_count; | |
131 | u32 cycle_count; | |
132 | u32 phy_err_count; | |
133 | u32 chan_tx_power; | |
52e346d1 CYY |
134 | u32 ack_rx_bad; |
135 | u32 rts_bad; | |
136 | u32 rts_good; | |
137 | u32 fcs_bad; | |
138 | u32 no_beacons; | |
139 | u32 mib_int_count; | |
5e3dd157 KV |
140 | |
141 | /* PDEV TX stats */ | |
142 | s32 comp_queued; | |
143 | s32 comp_delivered; | |
144 | s32 msdu_enqued; | |
145 | s32 mpdu_enqued; | |
146 | s32 wmm_drop; | |
147 | s32 local_enqued; | |
148 | s32 local_freed; | |
149 | s32 hw_queued; | |
150 | s32 hw_reaped; | |
151 | s32 underrun; | |
152 | s32 tx_abort; | |
153 | s32 mpdus_requed; | |
154 | u32 tx_ko; | |
155 | u32 data_rc; | |
156 | u32 self_triggers; | |
157 | u32 sw_retry_failure; | |
158 | u32 illgl_rate_phy_err; | |
159 | u32 pdev_cont_xretry; | |
160 | u32 pdev_tx_timeout; | |
161 | u32 pdev_resets; | |
162 | u32 phy_underrun; | |
163 | u32 txop_ovf; | |
164 | ||
165 | /* PDEV RX stats */ | |
166 | s32 mid_ppdu_route_change; | |
167 | s32 status_rcvd; | |
168 | s32 r0_frags; | |
169 | s32 r1_frags; | |
170 | s32 r2_frags; | |
171 | s32 r3_frags; | |
172 | s32 htt_msdus; | |
173 | s32 htt_mpdus; | |
174 | s32 loc_msdus; | |
175 | s32 loc_mpdus; | |
176 | s32 oversize_amsdu; | |
177 | s32 phy_errs; | |
178 | s32 phy_err_drop; | |
179 | s32 mpdu_errs; | |
180 | ||
181 | /* VDEV STATS */ | |
182 | ||
183 | /* PEER STATS */ | |
184 | u8 peers; | |
185 | struct ath10k_peer_stat peer_stat[TARGET_NUM_PEERS]; | |
186 | ||
187 | /* TODO: Beacon filter stats */ | |
188 | ||
189 | }; | |
190 | ||
9702c686 JD |
191 | struct ath10k_dfs_stats { |
192 | u32 phy_errors; | |
193 | u32 pulses_total; | |
194 | u32 pulses_detected; | |
195 | u32 pulses_discarded; | |
196 | u32 radar_detected; | |
197 | }; | |
198 | ||
5e3dd157 KV |
199 | #define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */ |
200 | ||
201 | struct ath10k_peer { | |
202 | struct list_head list; | |
203 | int vdev_id; | |
204 | u8 addr[ETH_ALEN]; | |
205 | DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS); | |
206 | struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; | |
207 | }; | |
208 | ||
9797febc MK |
209 | struct ath10k_sta { |
210 | struct ath10k_vif *arvif; | |
211 | ||
212 | /* the following are protected by ar->data_lock */ | |
213 | u32 changed; /* IEEE80211_RC_* */ | |
214 | u32 bw; | |
215 | u32 nss; | |
216 | u32 smps; | |
217 | ||
218 | struct work_struct update_wk; | |
219 | }; | |
220 | ||
5e3dd157 KV |
221 | #define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ) |
222 | ||
223 | struct ath10k_vif { | |
0579119f MK |
224 | struct list_head list; |
225 | ||
5e3dd157 KV |
226 | u32 vdev_id; |
227 | enum wmi_vdev_type vdev_type; | |
228 | enum wmi_vdev_subtype vdev_subtype; | |
229 | u32 beacon_interval; | |
230 | u32 dtim_period; | |
ed54388a | 231 | struct sk_buff *beacon; |
748afc47 MK |
232 | /* protected by data_lock */ |
233 | bool beacon_sent; | |
5e3dd157 KV |
234 | |
235 | struct ath10k *ar; | |
236 | struct ieee80211_vif *vif; | |
237 | ||
c930f744 MK |
238 | bool is_started; |
239 | bool is_up; | |
240 | u32 aid; | |
241 | u8 bssid[ETH_ALEN]; | |
242 | ||
cc4827b9 | 243 | struct work_struct wep_key_work; |
5e3dd157 | 244 | struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1]; |
cc4827b9 MK |
245 | u8 def_wep_key_idx; |
246 | u8 def_wep_key_newidx; | |
5e3dd157 KV |
247 | |
248 | u16 tx_seq_no; | |
249 | ||
250 | union { | |
251 | struct { | |
5e3dd157 KV |
252 | u32 uapsd; |
253 | } sta; | |
254 | struct { | |
255 | /* 127 stations; wmi limit */ | |
256 | u8 tim_bitmap[16]; | |
257 | u8 tim_len; | |
258 | u32 ssid_len; | |
259 | u8 ssid[IEEE80211_MAX_SSID_LEN]; | |
260 | bool hidden_ssid; | |
261 | /* P2P_IE with NoA attribute for P2P_GO case */ | |
262 | u32 noa_len; | |
263 | u8 *noa_data; | |
264 | } ap; | |
5e3dd157 | 265 | } u; |
51ab1a0a JD |
266 | |
267 | u8 fixed_rate; | |
268 | u8 fixed_nss; | |
9f81f725 | 269 | u8 force_sgi; |
e81bd104 MK |
270 | bool use_cts_prot; |
271 | int num_legacy_stations; | |
5e3dd157 KV |
272 | }; |
273 | ||
274 | struct ath10k_vif_iter { | |
275 | u32 vdev_id; | |
276 | struct ath10k_vif *arvif; | |
277 | }; | |
278 | ||
279 | struct ath10k_debug { | |
280 | struct dentry *debugfs_phy; | |
281 | ||
282 | struct ath10k_target_stats target_stats; | |
283 | u32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE]; | |
284 | ||
285 | struct completion event_stats_compl; | |
a3d135e5 KV |
286 | |
287 | unsigned long htt_stats_mask; | |
288 | struct delayed_work htt_stats_dwork; | |
9702c686 JD |
289 | struct ath10k_dfs_stats dfs_stats; |
290 | struct ath_dfs_pool_stats dfs_pool_stats; | |
f118a3e5 KV |
291 | |
292 | u32 fw_dbglog_mask; | |
5e3dd157 KV |
293 | }; |
294 | ||
f7843d7f MK |
295 | enum ath10k_state { |
296 | ATH10K_STATE_OFF = 0, | |
297 | ATH10K_STATE_ON, | |
affd3217 MK |
298 | |
299 | /* When doing firmware recovery the device is first powered down. | |
300 | * mac80211 is supposed to call in to start() hook later on. It is | |
301 | * however possible that driver unloading and firmware crash overlap. | |
302 | * mac80211 can wait on conf_mutex in stop() while the device is | |
303 | * stopped in ath10k_core_restart() work holding conf_mutex. The state | |
304 | * RESTARTED means that the device is up and mac80211 has started hw | |
305 | * reconfiguration. Once mac80211 is done with the reconfiguration we | |
306 | * set the state to STATE_ON in restart_complete(). */ | |
307 | ATH10K_STATE_RESTARTING, | |
308 | ATH10K_STATE_RESTARTED, | |
309 | ||
310 | /* The device has crashed while restarting hw. This state is like ON | |
311 | * but commands are blocked in HTC and -ECOMM response is given. This | |
312 | * prevents completion timeouts and makes the driver more responsive to | |
313 | * userspace commands. This is also prevents recursive recovery. */ | |
314 | ATH10K_STATE_WEDGED, | |
f7843d7f MK |
315 | }; |
316 | ||
0d9b0438 MK |
317 | enum ath10k_fw_features { |
318 | /* wmi_mgmt_rx_hdr contains extra RSSI information */ | |
319 | ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0, | |
320 | ||
ce42870e BM |
321 | /* firmware from 10X branch */ |
322 | ATH10K_FW_FEATURE_WMI_10X = 1, | |
323 | ||
5e00d31a BM |
324 | /* firmware support tx frame management over WMI, otherwise it's HTT */ |
325 | ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2, | |
326 | ||
d354181f BM |
327 | /* Firmware does not support P2P */ |
328 | ATH10K_FW_FEATURE_NO_P2P = 3, | |
329 | ||
0d9b0438 MK |
330 | /* keep last */ |
331 | ATH10K_FW_FEATURE_COUNT, | |
332 | }; | |
333 | ||
e8a50f8b MP |
334 | enum ath10k_dev_flags { |
335 | /* Indicates that ath10k device is during CAC phase of DFS */ | |
336 | ATH10K_CAC_RUNNING, | |
650b91fb | 337 | ATH10K_FLAG_FIRST_BOOT_DONE, |
e8a50f8b MP |
338 | }; |
339 | ||
5e3dd157 KV |
340 | struct ath10k { |
341 | struct ath_common ath_common; | |
342 | struct ieee80211_hw *hw; | |
343 | struct device *dev; | |
344 | u8 mac_addr[ETH_ALEN]; | |
345 | ||
e01ae68c | 346 | u32 chip_id; |
5e3dd157 KV |
347 | u32 target_version; |
348 | u8 fw_version_major; | |
349 | u32 fw_version_minor; | |
350 | u16 fw_version_release; | |
351 | u16 fw_version_build; | |
352 | u32 phy_capability; | |
353 | u32 hw_min_tx_power; | |
354 | u32 hw_max_tx_power; | |
355 | u32 ht_cap_info; | |
356 | u32 vht_cap_info; | |
8865bee4 | 357 | u32 num_rf_chains; |
5e3dd157 | 358 | |
0d9b0438 MK |
359 | DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT); |
360 | ||
5e3dd157 KV |
361 | struct targetdef *targetdef; |
362 | struct hostdef *hostdef; | |
363 | ||
364 | bool p2p; | |
365 | ||
366 | struct { | |
367 | void *priv; | |
5e3dd157 KV |
368 | const struct ath10k_hif_ops *ops; |
369 | } hif; | |
370 | ||
9042e17d | 371 | struct completion target_suspend; |
5e3dd157 KV |
372 | |
373 | struct ath10k_bmi bmi; | |
edb8236d | 374 | struct ath10k_wmi wmi; |
cd003fad | 375 | struct ath10k_htc htc; |
edb8236d | 376 | struct ath10k_htt htt; |
5e3dd157 KV |
377 | |
378 | struct ath10k_hw_params { | |
379 | u32 id; | |
380 | const char *name; | |
381 | u32 patch_load_addr; | |
382 | ||
383 | struct ath10k_hw_params_fw { | |
384 | const char *dir; | |
385 | const char *fw; | |
386 | const char *otp; | |
387 | const char *board; | |
388 | } fw; | |
389 | } hw_params; | |
390 | ||
36527916 | 391 | const struct firmware *board; |
958df3a0 KV |
392 | const void *board_data; |
393 | size_t board_len; | |
394 | ||
29385057 | 395 | const struct firmware *otp; |
958df3a0 KV |
396 | const void *otp_data; |
397 | size_t otp_len; | |
398 | ||
29385057 | 399 | const struct firmware *firmware; |
958df3a0 KV |
400 | const void *firmware_data; |
401 | size_t firmware_len; | |
29385057 | 402 | |
1a222435 KV |
403 | int fw_api; |
404 | ||
5e3dd157 KV |
405 | struct { |
406 | struct completion started; | |
407 | struct completion completed; | |
408 | struct completion on_channel; | |
409 | struct timer_list timeout; | |
410 | bool is_roc; | |
411 | bool in_progress; | |
412 | bool aborting; | |
413 | int vdev_id; | |
414 | int roc_freq; | |
415 | } scan; | |
416 | ||
417 | struct { | |
418 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; | |
419 | } mac; | |
420 | ||
421 | /* should never be NULL; needed for regular htt rx */ | |
422 | struct ieee80211_channel *rx_channel; | |
423 | ||
424 | /* valid during scan; needed for mgmt rx during scan */ | |
425 | struct ieee80211_channel *scan_channel; | |
426 | ||
c930f744 MK |
427 | /* current operating channel definition */ |
428 | struct cfg80211_chan_def chandef; | |
429 | ||
5e3dd157 | 430 | int free_vdev_map; |
1bbc0975 MK |
431 | bool promisc; |
432 | bool monitor; | |
5e3dd157 | 433 | int monitor_vdev_id; |
1bbc0975 | 434 | bool monitor_started; |
5e3dd157 | 435 | unsigned int filter_flags; |
e8a50f8b | 436 | unsigned long dev_flags; |
7d9b40b4 | 437 | u32 dfs_block_radar_events; |
5e3dd157 | 438 | |
d650097b MK |
439 | /* protected by conf_mutex */ |
440 | bool radar_enabled; | |
441 | int num_started_vdevs; | |
442 | ||
5e3dd157 KV |
443 | struct wmi_pdev_set_wmm_params_arg wmm_params; |
444 | struct completion install_key_done; | |
445 | ||
446 | struct completion vdev_setup_done; | |
447 | ||
448 | struct workqueue_struct *workqueue; | |
449 | ||
450 | /* prevents concurrent FW reconfiguration */ | |
451 | struct mutex conf_mutex; | |
452 | ||
453 | /* protects shared structure data */ | |
454 | spinlock_t data_lock; | |
455 | ||
0579119f | 456 | struct list_head arvifs; |
5e3dd157 KV |
457 | struct list_head peers; |
458 | wait_queue_head_t peer_mapping_wq; | |
459 | ||
0e759f36 BM |
460 | /* number of created peers; protected by data_lock */ |
461 | int num_peers; | |
462 | ||
5e3dd157 KV |
463 | struct work_struct offchan_tx_work; |
464 | struct sk_buff_head offchan_tx_queue; | |
465 | struct completion offchan_tx_completed; | |
466 | struct sk_buff *offchan_tx_skb; | |
467 | ||
5e00d31a BM |
468 | struct work_struct wmi_mgmt_tx_work; |
469 | struct sk_buff_head wmi_mgmt_tx_queue; | |
470 | ||
f7843d7f MK |
471 | enum ath10k_state state; |
472 | ||
affd3217 MK |
473 | struct work_struct restart_work; |
474 | ||
2e1dea40 MK |
475 | /* cycle count is reported twice for each visited channel during scan. |
476 | * access protected by data_lock */ | |
477 | u32 survey_last_rx_clear_count; | |
478 | u32 survey_last_cycle_count; | |
479 | struct survey_info survey[ATH10K_NUM_CHANS]; | |
480 | ||
9702c686 JD |
481 | struct dfs_pattern_detector *dfs_detector; |
482 | ||
5e3dd157 KV |
483 | #ifdef CONFIG_ATH10K_DEBUGFS |
484 | struct ath10k_debug debug; | |
485 | #endif | |
486 | }; | |
487 | ||
488 | struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev, | |
5e3dd157 KV |
489 | const struct ath10k_hif_ops *hif_ops); |
490 | void ath10k_core_destroy(struct ath10k *ar); | |
491 | ||
dd30a36e | 492 | int ath10k_core_start(struct ath10k *ar); |
00f5482b | 493 | int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt); |
dd30a36e | 494 | void ath10k_core_stop(struct ath10k *ar); |
e01ae68c | 495 | int ath10k_core_register(struct ath10k *ar, u32 chip_id); |
5e3dd157 KV |
496 | void ath10k_core_unregister(struct ath10k *ar); |
497 | ||
5e3dd157 | 498 | #endif /* _CORE_H_ */ |