[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / htt_tx.c

/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/etherdevice.h>
#include "htt.h"
#include "mac.h"
#include "hif.h"
#include "txrx.h"
#include "debug.h"

void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
{
	htt->num_pending_tx--;
	if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
		ieee80211_wake_queues(htt->ar->hw);
}

static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
{
	spin_lock_bh(&htt->tx_lock);
	__ath10k_htt_tx_dec_pending(htt);
	spin_unlock_bh(&htt->tx_lock);
}

static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
{
	int ret = 0;

	spin_lock_bh(&htt->tx_lock);

	if (htt->num_pending_tx >= htt->max_num_pending_tx) {
		ret = -EBUSY;
		goto exit;
	}

	htt->num_pending_tx++;
	if (htt->num_pending_tx == htt->max_num_pending_tx)
		ieee80211_stop_queues(htt->ar->hw);

exit:
	spin_unlock_bh(&htt->tx_lock);
	return ret;
}

int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt)
{
	struct ath10k *ar = htt->ar;
	int msdu_id;

	lockdep_assert_held(&htt->tx_lock);

	msdu_id = find_first_zero_bit(htt->used_msdu_ids,
				      htt->max_num_pending_tx);
	if (msdu_id == htt->max_num_pending_tx)
		return -ENOBUFS;

	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", msdu_id);
	__set_bit(msdu_id, htt->used_msdu_ids);
	return msdu_id;
}

void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
{
	struct ath10k *ar = htt->ar;

	lockdep_assert_held(&htt->tx_lock);

	if (!test_bit(msdu_id, htt->used_msdu_ids))
		ath10k_warn(ar, "trying to free unallocated msdu_id %d\n",
			    msdu_id);

	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
	__clear_bit(msdu_id, htt->used_msdu_ids);
}

int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
{
	struct ath10k *ar = htt->ar;

	spin_lock_init(&htt->tx_lock);

	if (test_bit(ATH10K_FW_FEATURE_WMI_10X, htt->ar->fw_features))
		htt->max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
	else
		htt->max_num_pending_tx = TARGET_NUM_MSDU_DESC;

	ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
		   htt->max_num_pending_tx);

	htt->pending_tx = kzalloc(sizeof(*htt->pending_tx) *
				  htt->max_num_pending_tx, GFP_KERNEL);
	if (!htt->pending_tx)
		return -ENOMEM;

	htt->used_msdu_ids = kzalloc(sizeof(unsigned long) *
				     BITS_TO_LONGS(htt->max_num_pending_tx),
				     GFP_KERNEL);
	if (!htt->used_msdu_ids) {
		kfree(htt->pending_tx);
		return -ENOMEM;
	}

	htt->tx_pool = dma_pool_create("ath10k htt tx pool", htt->ar->dev,
				       sizeof(struct ath10k_htt_txbuf), 4, 0);
	if (!htt->tx_pool) {
		kfree(htt->used_msdu_ids);
		kfree(htt->pending_tx);
		return -ENOMEM;
	}

	return 0;
}

static void ath10k_htt_tx_free_pending(struct ath10k_htt *htt)
{
	struct ath10k *ar = htt->ar;
	struct htt_tx_done tx_done = {0};
	int msdu_id;

	spin_lock_bh(&htt->tx_lock);
	for (msdu_id = 0; msdu_id < htt->max_num_pending_tx; msdu_id++) {
		if (!test_bit(msdu_id, htt->used_msdu_ids))
			continue;

		ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n",
			   msdu_id);

		tx_done.discard = 1;
		tx_done.msdu_id = msdu_id;

		ath10k_txrx_tx_unref(htt, &tx_done);
	}
	spin_unlock_bh(&htt->tx_lock);
}

void ath10k_htt_tx_free(struct ath10k_htt *htt)
{
	ath10k_htt_tx_free_pending(htt);
	kfree(htt->pending_tx);
	kfree(htt->used_msdu_ids);
	dma_pool_destroy(htt->tx_pool);
}

void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
{
	dev_kfree_skb_any(skb);
}

int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
{
	struct ath10k *ar = htt->ar;
	struct sk_buff *skb;
	struct htt_cmd *cmd;
	int len = 0;
	int ret;

	len += sizeof(cmd->hdr);
	len += sizeof(cmd->ver_req);

	skb = ath10k_htc_alloc_skb(ar, len);
	if (!skb)
		return -ENOMEM;

	skb_put(skb, len);
	cmd = (struct htt_cmd *)skb->data;
	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	if (ret) {
		dev_kfree_skb_any(skb);
		return ret;
	}

	return 0;
}

int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
{
	struct ath10k *ar = htt->ar;
	struct htt_stats_req *req;
	struct sk_buff *skb;
	struct htt_cmd *cmd;
	int len = 0, ret;

	len += sizeof(cmd->hdr);
	len += sizeof(cmd->stats_req);

	skb = ath10k_htc_alloc_skb(ar, len);
	if (!skb)
		return -ENOMEM;

	skb_put(skb, len);
	cmd = (struct htt_cmd *)skb->data;
	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;

	req = &cmd->stats_req;

	memset(req, 0, sizeof(*req));

	/* currently we support only max 8 bit masks so no need to worry
	 * about endian support */
	req->upload_types[0] = mask;
	req->reset_types[0] = mask;
	req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
	req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
	req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	if (ret) {
		ath10k_warn(ar, "failed to send htt type stats request: %d",
			    ret);
		dev_kfree_skb_any(skb);
		return ret;
	}

	return 0;
}

int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
{
	struct ath10k *ar = htt->ar;
	struct sk_buff *skb;
	struct htt_cmd *cmd;
	struct htt_rx_ring_setup_ring *ring;
	const int num_rx_ring = 1;
	u16 flags;
	u32 fw_idx;
	int len;
	int ret;

	/*
	 * the HW expects the buffer to be an integral number of 4-byte
	 * "words"
	 */
	BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
	BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);

	len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
	    + (sizeof(*ring) * num_rx_ring);
	skb = ath10k_htc_alloc_skb(ar, len);
	if (!skb)
		return -ENOMEM;

	skb_put(skb, len);

	cmd = (struct htt_cmd *)skb->data;
	ring = &cmd->rx_setup.rings[0];

	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
	cmd->rx_setup.hdr.num_rings = 1;

	/* FIXME: do we need all of this? */
	flags = 0;
	flags |= HTT_RX_RING_FLAGS_MAC80211_HDR;
	flags |= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
	flags |= HTT_RX_RING_FLAGS_PPDU_START;
	flags |= HTT_RX_RING_FLAGS_PPDU_END;
	flags |= HTT_RX_RING_FLAGS_MPDU_START;
	flags |= HTT_RX_RING_FLAGS_MPDU_END;
	flags |= HTT_RX_RING_FLAGS_MSDU_START;
	flags |= HTT_RX_RING_FLAGS_MSDU_END;
	flags |= HTT_RX_RING_FLAGS_RX_ATTENTION;
	flags |= HTT_RX_RING_FLAGS_FRAG_INFO;
	flags |= HTT_RX_RING_FLAGS_UNICAST_RX;
	flags |= HTT_RX_RING_FLAGS_MULTICAST_RX;
	flags |= HTT_RX_RING_FLAGS_CTRL_RX;
	flags |= HTT_RX_RING_FLAGS_MGMT_RX;
	flags |= HTT_RX_RING_FLAGS_NULL_RX;
	flags |= HTT_RX_RING_FLAGS_PHY_DATA_RX;

	fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);

	ring->fw_idx_shadow_reg_paddr =
		__cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
	ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
	ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
	ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
	ring->flags = __cpu_to_le16(flags);
	ring->fw_idx_init_val = __cpu_to_le16(fw_idx);

#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)

	ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
	ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
	ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
	ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
	ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
	ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
	ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
	ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
	ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
	ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));

#undef desc_offset

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	if (ret) {
		dev_kfree_skb_any(skb);
		return ret;
	}

	return 0;
}

int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
				u8 max_subfrms_ampdu,
				u8 max_subfrms_amsdu)
{
	struct ath10k *ar = htt->ar;
	struct htt_aggr_conf *aggr_conf;
	struct sk_buff *skb;
	struct htt_cmd *cmd;
	int len;
	int ret;

	/* Firmware defaults are: amsdu = 3 and ampdu = 64 */

	if (max_subfrms_ampdu == 0 || max_subfrms_ampdu > 64)
		return -EINVAL;

	if (max_subfrms_amsdu == 0 || max_subfrms_amsdu > 31)
		return -EINVAL;

	len = sizeof(cmd->hdr);
	len += sizeof(cmd->aggr_conf);

	skb = ath10k_htc_alloc_skb(ar, len);
	if (!skb)
		return -ENOMEM;

	skb_put(skb, len);
	cmd = (struct htt_cmd *)skb->data;
	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;

	aggr_conf = &cmd->aggr_conf;
	aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
	aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;

	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
		   aggr_conf->max_num_amsdu_subframes,
		   aggr_conf->max_num_ampdu_subframes);

	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	if (ret) {
		dev_kfree_skb_any(skb);
		return ret;
	}

	return 0;
}

int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
{
	struct ath10k *ar = htt->ar;
	struct device *dev = ar->dev;
	struct sk_buff *txdesc = NULL;
	struct htt_cmd *cmd;
	struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
	u8 vdev_id = skb_cb->vdev_id;
	int len = 0;
	int msdu_id = -1;
	int res;

	res = ath10k_htt_tx_inc_pending(htt);
	if (res)
		goto err;

	len += sizeof(cmd->hdr);
	len += sizeof(cmd->mgmt_tx);

	spin_lock_bh(&htt->tx_lock);
	res = ath10k_htt_tx_alloc_msdu_id(htt);
	if (res < 0) {
		spin_unlock_bh(&htt->tx_lock);
		goto err_tx_dec;
	}
	msdu_id = res;
	htt->pending_tx[msdu_id] = msdu;
	spin_unlock_bh(&htt->tx_lock);

	txdesc = ath10k_htc_alloc_skb(ar, len);
	if (!txdesc) {
		res = -ENOMEM;
		goto err_free_msdu_id;
	}

	skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
				       DMA_TO_DEVICE);
	res = dma_mapping_error(dev, skb_cb->paddr);
	if (res)
		goto err_free_txdesc;

	skb_put(txdesc, len);
	cmd = (struct htt_cmd *)txdesc->data;
	cmd->hdr.msg_type         = HTT_H2T_MSG_TYPE_MGMT_TX;
	cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
	cmd->mgmt_tx.len        = __cpu_to_le32(msdu->len);
	cmd->mgmt_tx.desc_id    = __cpu_to_le32(msdu_id);
	cmd->mgmt_tx.vdev_id    = __cpu_to_le32(vdev_id);
	memcpy(cmd->mgmt_tx.hdr, msdu->data,
	       min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));

	skb_cb->htt.txbuf = NULL;

	res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
	if (res)
		goto err_unmap_msdu;

	return 0;

err_unmap_msdu:
	dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
err_free_txdesc:
	dev_kfree_skb_any(txdesc);
err_free_msdu_id:
	spin_lock_bh(&htt->tx_lock);
	htt->pending_tx[msdu_id] = NULL;
	ath10k_htt_tx_free_msdu_id(htt, msdu_id);
	spin_unlock_bh(&htt->tx_lock);
err_tx_dec:
	ath10k_htt_tx_dec_pending(htt);
err:
	return res;
}

int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
{
	struct ath10k *ar = htt->ar;
	struct device *dev = ar->dev;
	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
	struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
	struct ath10k_hif_sg_item sg_items[2];
	struct htt_data_tx_desc_frag *frags;
	u8 vdev_id = skb_cb->vdev_id;
	u8 tid = skb_cb->htt.tid;
	int prefetch_len;
	int res;
	u8 flags0 = 0;
	u16 msdu_id, flags1 = 0;
	dma_addr_t paddr;
	u32 frags_paddr;
	bool use_frags;

	res = ath10k_htt_tx_inc_pending(htt);
	if (res)
		goto err;

	spin_lock_bh(&htt->tx_lock);
	res = ath10k_htt_tx_alloc_msdu_id(htt);
	if (res < 0) {
		spin_unlock_bh(&htt->tx_lock);
		goto err_tx_dec;
	}
	msdu_id = res;
	htt->pending_tx[msdu_id] = msdu;
	spin_unlock_bh(&htt->tx_lock);

	prefetch_len = min(htt->prefetch_len, msdu->len);
	prefetch_len = roundup(prefetch_len, 4);

	/* Since HTT 3.0 there is no separate mgmt tx command. However in case
	 * of mgmt tx using TX_FRM there is not tx fragment list. Instead of tx
	 * fragment list host driver specifies directly frame pointer. */
	use_frags = htt->target_version_major < 3 ||
		    !ieee80211_is_mgmt(hdr->frame_control);

	skb_cb->htt.txbuf = dma_pool_alloc(htt->tx_pool, GFP_ATOMIC,
					   &paddr);
	if (!skb_cb->htt.txbuf)
		goto err_free_msdu_id;
	skb_cb->htt.txbuf_paddr = paddr;

	skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
				       DMA_TO_DEVICE);
	res = dma_mapping_error(dev, skb_cb->paddr);
	if (res)
		goto err_free_txbuf;

	if (likely(use_frags)) {
		frags = skb_cb->htt.txbuf->frags;

		frags[0].paddr = __cpu_to_le32(skb_cb->paddr);
		frags[0].len = __cpu_to_le32(msdu->len);
		frags[1].paddr = 0;
		frags[1].len = 0;

		flags0 |= SM(ATH10K_HW_TXRX_NATIVE_WIFI,
			     HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);

		frags_paddr = skb_cb->htt.txbuf_paddr;
	} else {
		flags0 |= SM(ATH10K_HW_TXRX_MGMT,
			     HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);

		frags_paddr = skb_cb->paddr;
	}

	/* Normally all commands go through HTC which manages tx credits for
	 * each endpoint and notifies when tx is completed.
	 *
	 * HTT endpoint is creditless so there's no need to care about HTC
	 * flags. In that case it is trivial to fill the HTC header here.
	 *
	 * MSDU transmission is considered completed upon HTT event. This
	 * implies no relevant resources can be freed until after the event is
	 * received. That's why HTC tx completion handler itself is ignored by
	 * setting NULL to transfer_context for all sg items.
	 *
	 * There is simply no point in pushing HTT TX_FRM through HTC tx path
	 * as it's a waste of resources. By bypassing HTC it is possible to
	 * avoid extra memory allocations, compress data structures and thus
	 * improve performance. */

	skb_cb->htt.txbuf->htc_hdr.eid = htt->eid;
	skb_cb->htt.txbuf->htc_hdr.len = __cpu_to_le16(
			sizeof(skb_cb->htt.txbuf->cmd_hdr) +
			sizeof(skb_cb->htt.txbuf->cmd_tx) +
			prefetch_len);
	skb_cb->htt.txbuf->htc_hdr.flags = 0;

	if (!ieee80211_has_protected(hdr->frame_control))
		flags0 |= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;

	flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;

	flags1 |= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
	flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
	flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
	flags1 |= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;

	/* Prevent firmware from sending up tx inspection requests. There's
	 * nothing ath10k can do with frames requested for inspection so force
	 * it to simply rely a regular tx completion with discard status.
	 */
	flags1 |= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;

	skb_cb->htt.txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
	skb_cb->htt.txbuf->cmd_tx.flags0 = flags0;
	skb_cb->htt.txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
	skb_cb->htt.txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
	skb_cb->htt.txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
	skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
	skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le32(HTT_INVALID_PEERID);

	trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
	ath10k_dbg(ar, ATH10K_DBG_HTT,
		   "htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu\n",
		   flags0, flags1, msdu->len, msdu_id, frags_paddr,
		   (u32)skb_cb->paddr, vdev_id, tid);
	ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
			msdu->data, msdu->len);
	trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
	trace_ath10k_tx_payload(ar, msdu->data, msdu->len);

	sg_items[0].transfer_id = 0;
	sg_items[0].transfer_context = NULL;
	sg_items[0].vaddr = &skb_cb->htt.txbuf->htc_hdr;
	sg_items[0].paddr = skb_cb->htt.txbuf_paddr +
			    sizeof(skb_cb->htt.txbuf->frags);
	sg_items[0].len = sizeof(skb_cb->htt.txbuf->htc_hdr) +
			  sizeof(skb_cb->htt.txbuf->cmd_hdr) +
			  sizeof(skb_cb->htt.txbuf->cmd_tx);

	sg_items[1].transfer_id = 0;
	sg_items[1].transfer_context = NULL;
	sg_items[1].vaddr = msdu->data;
	sg_items[1].paddr = skb_cb->paddr;
	sg_items[1].len = prefetch_len;

	res = ath10k_hif_tx_sg(htt->ar,
			       htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
			       sg_items, ARRAY_SIZE(sg_items));
	if (res)
		goto err_unmap_msdu;

	return 0;

err_unmap_msdu:
	dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
err_free_txbuf:
	dma_pool_free(htt->tx_pool,
		      skb_cb->htt.txbuf,
		      skb_cb->htt.txbuf_paddr);
err_free_msdu_id:
	spin_lock_bh(&htt->tx_lock);
	htt->pending_tx[msdu_id] = NULL;
	ath10k_htt_tx_free_msdu_id(htt, msdu_id);
	spin_unlock_bh(&htt->tx_lock);
err_tx_dec:
	ath10k_htt_tx_dec_pending(htt);
err:
	return res;
}
Commit	Line	Data
5e3dd157 KV	1	/*
	2	* Copyright (c) 2005-2011 Atheros Communications Inc.
	3	* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
	4	*
	5	* Permission to use, copy, modify, and/or distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*/
	17
	18	#include <linux/etherdevice.h>
	19	#include "htt.h"
	20	#include "mac.h"
	21	#include "hif.h"
	22	#include "txrx.h"
	23	#include "debug.h"
	24
	25	void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
	26	{
	27	htt->num_pending_tx--;
	28	if (htt->num_pending_tx == htt->max_num_pending_tx - 1)
	29	ieee80211_wake_queues(htt->ar->hw);
	30	}
	31
	32	static void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt)
	33	{
	34	spin_lock_bh(&htt->tx_lock);
	35	__ath10k_htt_tx_dec_pending(htt);
	36	spin_unlock_bh(&htt->tx_lock);
	37	}
	38
	39	static int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt)
	40	{
	41	int ret = 0;
	42
	43	spin_lock_bh(&htt->tx_lock);
	44
	45	if (htt->num_pending_tx >= htt->max_num_pending_tx) {
	46	ret = -EBUSY;
	47	goto exit;
	48	}
	49
	50	htt->num_pending_tx++;
	51	if (htt->num_pending_tx == htt->max_num_pending_tx)
	52	ieee80211_stop_queues(htt->ar->hw);
	53
	54	exit:
	55	spin_unlock_bh(&htt->tx_lock);
	56	return ret;
	57	}
	58
	59	int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt)
	60	{
7aa7a72a	61	struct ath10k *ar = htt->ar;
5e3dd157 KV	62	int msdu_id;
	63
	64	lockdep_assert_held(&htt->tx_lock);
	65
	66	msdu_id = find_first_zero_bit(htt->used_msdu_ids,
	67	htt->max_num_pending_tx);
	68	if (msdu_id == htt->max_num_pending_tx)
	69	return -ENOBUFS;
	70
7aa7a72a	71	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", msdu_id);
5e3dd157 KV	72	__set_bit(msdu_id, htt->used_msdu_ids);
	73	return msdu_id;
	74	}
	75
	76	void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
	77	{
7aa7a72a MK	78	struct ath10k *ar = htt->ar;
7aa7a72a MK	79
5e3dd157 KV	80	lockdep_assert_held(&htt->tx_lock);
	81
	82	if (!test_bit(msdu_id, htt->used_msdu_ids))
7aa7a72a MK	83	ath10k_warn(ar, "trying to free unallocated msdu_id %d\n",
7aa7a72a MK	84	msdu_id);
5e3dd157	85
7aa7a72a	86	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
5e3dd157 KV	87	__clear_bit(msdu_id, htt->used_msdu_ids);
	88	}
	89
95bf21f9	90	int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
5e3dd157	91	{
7aa7a72a MK	92	struct ath10k *ar = htt->ar;
7aa7a72a MK	93
5e3dd157	94	spin_lock_init(&htt->tx_lock);
5e3dd157	95
60f85bea MK	96	if (test_bit(ATH10K_FW_FEATURE_WMI_10X, htt->ar->fw_features))
	97	htt->max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
	98	else
	99	htt->max_num_pending_tx = TARGET_NUM_MSDU_DESC;
5e3dd157	100
7aa7a72a	101	ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
5e3dd157 KV	102	htt->max_num_pending_tx);
	103
	104	htt->pending_tx = kzalloc(sizeof(htt->pending_tx)
	105	htt->max_num_pending_tx, GFP_KERNEL);
	106	if (!htt->pending_tx)
	107	return -ENOMEM;
	108
	109	htt->used_msdu_ids = kzalloc(sizeof(unsigned long) *
	110	BITS_TO_LONGS(htt->max_num_pending_tx),
	111	GFP_KERNEL);
	112	if (!htt->used_msdu_ids) {
	113	kfree(htt->pending_tx);
	114	return -ENOMEM;
	115	}
	116
a16942e6 MK	117	htt->tx_pool = dma_pool_create("ath10k htt tx pool", htt->ar->dev,
	118	sizeof(struct ath10k_htt_txbuf), 4, 0);
	119	if (!htt->tx_pool) {
	120	kfree(htt->used_msdu_ids);
	121	kfree(htt->pending_tx);
	122	return -ENOMEM;
	123	}
	124
5e3dd157 KV	125	return 0;
	126	}
	127
95bf21f9	128	static void ath10k_htt_tx_free_pending(struct ath10k_htt *htt)
5e3dd157	129	{
7aa7a72a	130	struct ath10k *ar = htt->ar;
0a89f8a0	131	struct htt_tx_done tx_done = {0};
5e3dd157 KV	132	int msdu_id;
5e3dd157 KV	133
45967089	134	spin_lock_bh(&htt->tx_lock);
5e3dd157 KV	135	for (msdu_id = 0; msdu_id < htt->max_num_pending_tx; msdu_id++) {
	136	if (!test_bit(msdu_id, htt->used_msdu_ids))
	137	continue;
	138
7aa7a72a	139	ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n",
5e3dd157 KV	140	msdu_id);
5e3dd157 KV	141
0a89f8a0 MK	142	tx_done.discard = 1;
0a89f8a0 MK	143	tx_done.msdu_id = msdu_id;
5e3dd157	144
0a89f8a0	145	ath10k_txrx_tx_unref(htt, &tx_done);
5e3dd157	146	}
45967089	147	spin_unlock_bh(&htt->tx_lock);
5e3dd157 KV	148	}
5e3dd157 KV	149
95bf21f9	150	void ath10k_htt_tx_free(struct ath10k_htt *htt)
5e3dd157	151	{
95bf21f9	152	ath10k_htt_tx_free_pending(htt);
5e3dd157 KV	153	kfree(htt->pending_tx);
5e3dd157 KV	154	kfree(htt->used_msdu_ids);
a16942e6	155	dma_pool_destroy(htt->tx_pool);
5e3dd157 KV	156	}
	157
	158	void ath10k_htt_htc_tx_complete(struct ath10k ar, struct sk_buff skb)
	159	{
0a89f8a0	160	dev_kfree_skb_any(skb);
5e3dd157 KV	161	}
	162
	163	int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
	164	{
7aa7a72a	165	struct ath10k *ar = htt->ar;
5e3dd157 KV	166	struct sk_buff *skb;
	167	struct htt_cmd *cmd;
	168	int len = 0;
	169	int ret;
	170
	171	len += sizeof(cmd->hdr);
	172	len += sizeof(cmd->ver_req);
	173
7aa7a72a	174	skb = ath10k_htc_alloc_skb(ar, len);
5e3dd157 KV	175	if (!skb)
	176	return -ENOMEM;
	177
	178	skb_put(skb, len);
	179	cmd = (struct htt_cmd *)skb->data;
	180	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_VERSION_REQ;
	181
cd003fad	182	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
5e3dd157 KV	183	if (ret) {
	184	dev_kfree_skb_any(skb);
	185	return ret;
	186	}
	187
	188	return 0;
	189	}
	190
a3d135e5 KV	191	int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
a3d135e5 KV	192	{
7aa7a72a	193	struct ath10k *ar = htt->ar;
a3d135e5 KV	194	struct htt_stats_req *req;
	195	struct sk_buff *skb;
	196	struct htt_cmd *cmd;
	197	int len = 0, ret;
	198
	199	len += sizeof(cmd->hdr);
	200	len += sizeof(cmd->stats_req);
	201
7aa7a72a	202	skb = ath10k_htc_alloc_skb(ar, len);
a3d135e5 KV	203	if (!skb)
	204	return -ENOMEM;
	205
	206	skb_put(skb, len);
	207	cmd = (struct htt_cmd *)skb->data;
	208	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_STATS_REQ;
	209
	210	req = &cmd->stats_req;
	211
	212	memset(req, 0, sizeof(*req));
	213
	214	/* currently we support only max 8 bit masks so no need to worry
	215	* about endian support */
	216	req->upload_types[0] = mask;
	217	req->reset_types[0] = mask;
	218	req->stat_type = HTT_STATS_REQ_CFG_STAT_TYPE_INVALID;
	219	req->cookie_lsb = cpu_to_le32(cookie & 0xffffffff);
	220	req->cookie_msb = cpu_to_le32((cookie & 0xffffffff00000000ULL) >> 32);
	221
a3d135e5 KV	222	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
a3d135e5 KV	223	if (ret) {
7aa7a72a MK	224	ath10k_warn(ar, "failed to send htt type stats request: %d",
7aa7a72a MK	225	ret);
a3d135e5 KV	226	dev_kfree_skb_any(skb);
	227	return ret;
	228	}
	229
	230	return 0;
	231	}
	232
5e3dd157 KV	233	int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
5e3dd157 KV	234	{
7aa7a72a	235	struct ath10k *ar = htt->ar;
5e3dd157 KV	236	struct sk_buff *skb;
	237	struct htt_cmd *cmd;
	238	struct htt_rx_ring_setup_ring *ring;
	239	const int num_rx_ring = 1;
	240	u16 flags;
	241	u32 fw_idx;
	242	int len;
	243	int ret;
	244
	245	/*
	246	* the HW expects the buffer to be an integral number of 4-byte
	247	* "words"
	248	*/
	249	BUILD_BUG_ON(!IS_ALIGNED(HTT_RX_BUF_SIZE, 4));
	250	BUILD_BUG_ON((HTT_RX_BUF_SIZE & HTT_MAX_CACHE_LINE_SIZE_MASK) != 0);
	251
	252	len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
	253	+ (sizeof(ring) num_rx_ring);
7aa7a72a	254	skb = ath10k_htc_alloc_skb(ar, len);
5e3dd157 KV	255	if (!skb)
	256	return -ENOMEM;
	257
	258	skb_put(skb, len);
	259
	260	cmd = (struct htt_cmd *)skb->data;
	261	ring = &cmd->rx_setup.rings[0];
	262
	263	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_RX_RING_CFG;
	264	cmd->rx_setup.hdr.num_rings = 1;
	265
	266	/* FIXME: do we need all of this? */
	267	flags = 0;
	268	flags \|= HTT_RX_RING_FLAGS_MAC80211_HDR;
	269	flags \|= HTT_RX_RING_FLAGS_MSDU_PAYLOAD;
	270	flags \|= HTT_RX_RING_FLAGS_PPDU_START;
	271	flags \|= HTT_RX_RING_FLAGS_PPDU_END;
	272	flags \|= HTT_RX_RING_FLAGS_MPDU_START;
	273	flags \|= HTT_RX_RING_FLAGS_MPDU_END;
	274	flags \|= HTT_RX_RING_FLAGS_MSDU_START;
	275	flags \|= HTT_RX_RING_FLAGS_MSDU_END;
	276	flags \|= HTT_RX_RING_FLAGS_RX_ATTENTION;
	277	flags \|= HTT_RX_RING_FLAGS_FRAG_INFO;
	278	flags \|= HTT_RX_RING_FLAGS_UNICAST_RX;
	279	flags \|= HTT_RX_RING_FLAGS_MULTICAST_RX;
	280	flags \|= HTT_RX_RING_FLAGS_CTRL_RX;
	281	flags \|= HTT_RX_RING_FLAGS_MGMT_RX;
	282	flags \|= HTT_RX_RING_FLAGS_NULL_RX;
	283	flags \|= HTT_RX_RING_FLAGS_PHY_DATA_RX;
	284
	285	fw_idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
	286
	287	ring->fw_idx_shadow_reg_paddr =
	288	__cpu_to_le32(htt->rx_ring.alloc_idx.paddr);
	289	ring->rx_ring_base_paddr = __cpu_to_le32(htt->rx_ring.base_paddr);
	290	ring->rx_ring_len = __cpu_to_le16(htt->rx_ring.size);
	291	ring->rx_ring_bufsize = __cpu_to_le16(HTT_RX_BUF_SIZE);
	292	ring->flags = __cpu_to_le16(flags);
	293	ring->fw_idx_init_val = __cpu_to_le16(fw_idx);
	294
	295	#define desc_offset(x) (offsetof(struct htt_rx_desc, x) / 4)
	296
	297	ring->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
	298	ring->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
	299	ring->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
	300	ring->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
	301	ring->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
	302	ring->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
	303	ring->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
	304	ring->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
	305	ring->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
	306	ring->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
	307
	308	#undef desc_offset
	309
cd003fad	310	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
5e3dd157 KV	311	if (ret) {
	312	dev_kfree_skb_any(skb);
	313	return ret;
	314	}
	315
	316	return 0;
	317	}
	318
d385623a JD	319	int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
	320	u8 max_subfrms_ampdu,
	321	u8 max_subfrms_amsdu)
	322	{
7aa7a72a	323	struct ath10k *ar = htt->ar;
d385623a JD	324	struct htt_aggr_conf *aggr_conf;
	325	struct sk_buff *skb;
	326	struct htt_cmd *cmd;
	327	int len;
	328	int ret;
	329
	330	/* Firmware defaults are: amsdu = 3 and ampdu = 64 */
	331
	332	if (max_subfrms_ampdu == 0 \|\| max_subfrms_ampdu > 64)
	333	return -EINVAL;
	334
	335	if (max_subfrms_amsdu == 0 \|\| max_subfrms_amsdu > 31)
	336	return -EINVAL;
	337
	338	len = sizeof(cmd->hdr);
	339	len += sizeof(cmd->aggr_conf);
	340
7aa7a72a	341	skb = ath10k_htc_alloc_skb(ar, len);
d385623a JD	342	if (!skb)
	343	return -ENOMEM;
	344
	345	skb_put(skb, len);
	346	cmd = (struct htt_cmd *)skb->data;
	347	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_AGGR_CFG;
	348
	349	aggr_conf = &cmd->aggr_conf;
	350	aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
	351	aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
	352
7aa7a72a	353	ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
d385623a JD	354	aggr_conf->max_num_amsdu_subframes,
	355	aggr_conf->max_num_ampdu_subframes);
	356
	357	ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
	358	if (ret) {
	359	dev_kfree_skb_any(skb);
	360	return ret;
	361	}
	362
	363	return 0;
	364	}
	365
5e3dd157 KV	366	int ath10k_htt_mgmt_tx(struct ath10k_htt htt, struct sk_buff msdu)
5e3dd157 KV	367	{
7aa7a72a MK	368	struct ath10k *ar = htt->ar;
7aa7a72a MK	369	struct device *dev = ar->dev;
5e3dd157 KV	370	struct sk_buff *txdesc = NULL;
5e3dd157 KV	371	struct htt_cmd *cmd;
1f8bb151	372	struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
5e00d31a	373	u8 vdev_id = skb_cb->vdev_id;
5e3dd157 KV	374	int len = 0;
	375	int msdu_id = -1;
	376	int res;
	377
5e3dd157 KV	378	res = ath10k_htt_tx_inc_pending(htt);
5e3dd157 KV	379	if (res)
2f3773bc	380	goto err;
5e3dd157 KV	381
	382	len += sizeof(cmd->hdr);
	383	len += sizeof(cmd->mgmt_tx);
	384
5e3dd157	385	spin_lock_bh(&htt->tx_lock);
2f3773bc MK	386	res = ath10k_htt_tx_alloc_msdu_id(htt);
2f3773bc MK	387	if (res < 0) {
5e3dd157	388	spin_unlock_bh(&htt->tx_lock);
2f3773bc	389	goto err_tx_dec;
5e3dd157	390	}
2f3773bc	391	msdu_id = res;
0a89f8a0	392	htt->pending_tx[msdu_id] = msdu;
5e3dd157 KV	393	spin_unlock_bh(&htt->tx_lock);
5e3dd157 KV	394
7aa7a72a	395	txdesc = ath10k_htc_alloc_skb(ar, len);
2f3773bc MK	396	if (!txdesc) {
	397	res = -ENOMEM;
	398	goto err_free_msdu_id;
	399	}
	400
767d34fc MK	401	skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
	402	DMA_TO_DEVICE);
	403	res = dma_mapping_error(dev, skb_cb->paddr);
5e3dd157	404	if (res)
2f3773bc	405	goto err_free_txdesc;
5e3dd157 KV	406
	407	skb_put(txdesc, len);
	408	cmd = (struct htt_cmd *)txdesc->data;
	409	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_MGMT_TX;
	410	cmd->mgmt_tx.msdu_paddr = __cpu_to_le32(ATH10K_SKB_CB(msdu)->paddr);
	411	cmd->mgmt_tx.len = __cpu_to_le32(msdu->len);
	412	cmd->mgmt_tx.desc_id = __cpu_to_le32(msdu_id);
	413	cmd->mgmt_tx.vdev_id = __cpu_to_le32(vdev_id);
	414	memcpy(cmd->mgmt_tx.hdr, msdu->data,
	415	min_t(int, msdu->len, HTT_MGMT_FRM_HDR_DOWNLOAD_LEN));
	416
a16942e6	417	skb_cb->htt.txbuf = NULL;
1f8bb151	418
cd003fad	419	res = ath10k_htc_send(&htt->ar->htc, htt->eid, txdesc);
5e3dd157	420	if (res)
2f3773bc	421	goto err_unmap_msdu;
5e3dd157 KV	422
	423	return 0;
	424
2f3773bc	425	err_unmap_msdu:
767d34fc	426	dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
2f3773bc MK	427	err_free_txdesc:
	428	dev_kfree_skb_any(txdesc);
	429	err_free_msdu_id:
	430	spin_lock_bh(&htt->tx_lock);
	431	htt->pending_tx[msdu_id] = NULL;
	432	ath10k_htt_tx_free_msdu_id(htt, msdu_id);
	433	spin_unlock_bh(&htt->tx_lock);
	434	err_tx_dec:
5e3dd157	435	ath10k_htt_tx_dec_pending(htt);
2f3773bc	436	err:
5e3dd157 KV	437	return res;
	438	}
	439
	440	int ath10k_htt_tx(struct ath10k_htt htt, struct sk_buff msdu)
	441	{
7aa7a72a MK	442	struct ath10k *ar = htt->ar;
7aa7a72a MK	443	struct device *dev = ar->dev;
5e3dd157	444	struct ieee80211_hdr hdr = (struct ieee80211_hdr )msdu->data;
1f8bb151	445	struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
a16942e6 MK	446	struct ath10k_hif_sg_item sg_items[2];
	447	struct htt_data_tx_desc_frag *frags;
	448	u8 vdev_id = skb_cb->vdev_id;
	449	u8 tid = skb_cb->htt.tid;
	450	int prefetch_len;
5e3dd157	451	int res;
a16942e6 MK	452	u8 flags0 = 0;
	453	u16 msdu_id, flags1 = 0;
	454	dma_addr_t paddr;
	455	u32 frags_paddr;
	456	bool use_frags;
5e3dd157 KV	457
	458	res = ath10k_htt_tx_inc_pending(htt);
	459	if (res)
2f3773bc MK	460	goto err;
	461
	462	spin_lock_bh(&htt->tx_lock);
	463	res = ath10k_htt_tx_alloc_msdu_id(htt);
	464	if (res < 0) {
	465	spin_unlock_bh(&htt->tx_lock);
	466	goto err_tx_dec;
	467	}
	468	msdu_id = res;
	469	htt->pending_tx[msdu_id] = msdu;
	470	spin_unlock_bh(&htt->tx_lock);
5e3dd157 KV	471
	472	prefetch_len = min(htt->prefetch_len, msdu->len);
	473	prefetch_len = roundup(prefetch_len, 4);
	474
961d4c38 MK	475	/* Since HTT 3.0 there is no separate mgmt tx command. However in case
	476	* of mgmt tx using TX_FRM there is not tx fragment list. Instead of tx
	477	* fragment list host driver specifies directly frame pointer. */
2f3773bc MK	478	use_frags = htt->target_version_major < 3 \|\|
	479	!ieee80211_is_mgmt(hdr->frame_control);
	480
a16942e6 MK	481	skb_cb->htt.txbuf = dma_pool_alloc(htt->tx_pool, GFP_ATOMIC,
	482	&paddr);
	483	if (!skb_cb->htt.txbuf)
	484	goto err_free_msdu_id;
	485	skb_cb->htt.txbuf_paddr = paddr;
5e3dd157	486
767d34fc MK	487	skb_cb->paddr = dma_map_single(dev, msdu->data, msdu->len,
	488	DMA_TO_DEVICE);
	489	res = dma_mapping_error(dev, skb_cb->paddr);
5e3dd157	490	if (res)
a16942e6	491	goto err_free_txbuf;
5e3dd157	492
a16942e6 MK	493	if (likely(use_frags)) {
a16942e6 MK	494	frags = skb_cb->htt.txbuf->frags;
5e3dd157	495
a16942e6 MK	496	frags[0].paddr = __cpu_to_le32(skb_cb->paddr);
	497	frags[0].len = __cpu_to_le32(msdu->len);
	498	frags[1].paddr = 0;
	499	frags[1].len = 0;
	500
	501	flags0 \|= SM(ATH10K_HW_TXRX_NATIVE_WIFI,
	502	HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
5e3dd157	503
a16942e6 MK	504	frags_paddr = skb_cb->htt.txbuf_paddr;
	505	} else {
	506	flags0 \|= SM(ATH10K_HW_TXRX_MGMT,
	507	HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE);
5e3dd157	508
a16942e6 MK	509	frags_paddr = skb_cb->paddr;
	510	}
	511
	512	/* Normally all commands go through HTC which manages tx credits for
	513	* each endpoint and notifies when tx is completed.
	514	*
	515	* HTT endpoint is creditless so there's no need to care about HTC
	516	* flags. In that case it is trivial to fill the HTC header here.
	517	*
	518	* MSDU transmission is considered completed upon HTT event. This
	519	* implies no relevant resources can be freed until after the event is
	520	* received. That's why HTC tx completion handler itself is ignored by
	521	* setting NULL to transfer_context for all sg items.
	522	*
	523	* There is simply no point in pushing HTT TX_FRM through HTC tx path
	524	* as it's a waste of resources. By bypassing HTC it is possible to
	525	* avoid extra memory allocations, compress data structures and thus
	526	* improve performance. */
	527
	528	skb_cb->htt.txbuf->htc_hdr.eid = htt->eid;
	529	skb_cb->htt.txbuf->htc_hdr.len = __cpu_to_le16(
	530	sizeof(skb_cb->htt.txbuf->cmd_hdr) +
	531	sizeof(skb_cb->htt.txbuf->cmd_tx) +
	532	prefetch_len);
	533	skb_cb->htt.txbuf->htc_hdr.flags = 0;
5e3dd157	534
5e3dd157 KV	535	if (!ieee80211_has_protected(hdr->frame_control))
5e3dd157 KV	536	flags0 \|= HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT;
961d4c38	537
a16942e6	538	flags0 \|= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
5e3dd157	539
5e3dd157 KV	540	flags1 \|= SM((u16)vdev_id, HTT_DATA_TX_DESC_FLAGS1_VDEV_ID);
5e3dd157 KV	541	flags1 \|= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID);
7c199997 MK	542	flags1 \|= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD;
7c199997 MK	543	flags1 \|= HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD;
5e3dd157	544
708b9bde MK	545	/* Prevent firmware from sending up tx inspection requests. There's
	546	* nothing ath10k can do with frames requested for inspection so force
	547	* it to simply rely a regular tx completion with discard status.
	548	*/
	549	flags1 \|= HTT_DATA_TX_DESC_FLAGS1_POSTPONED;
	550
a16942e6 MK	551	skb_cb->htt.txbuf->cmd_hdr.msg_type = HTT_H2T_MSG_TYPE_TX_FRM;
	552	skb_cb->htt.txbuf->cmd_tx.flags0 = flags0;
	553	skb_cb->htt.txbuf->cmd_tx.flags1 = __cpu_to_le16(flags1);
	554	skb_cb->htt.txbuf->cmd_tx.len = __cpu_to_le16(msdu->len);
	555	skb_cb->htt.txbuf->cmd_tx.id = __cpu_to_le16(msdu_id);
	556	skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
	557	skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le32(HTT_INVALID_PEERID);
	558
d1e50f47	559	trace_ath10k_htt_tx(ar, msdu_id, msdu->len, vdev_id, tid);
7aa7a72a	560	ath10k_dbg(ar, ATH10K_DBG_HTT,
a16942e6 MK	561	"htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu\n",
	562	flags0, flags1, msdu->len, msdu_id, frags_paddr,
	563	(u32)skb_cb->paddr, vdev_id, tid);
7aa7a72a	564	ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
a16942e6	565	msdu->data, msdu->len);
5ce8e7fd RM	566	trace_ath10k_tx_hdr(ar, msdu->data, msdu->len);
5ce8e7fd RM	567	trace_ath10k_tx_payload(ar, msdu->data, msdu->len);
5e3dd157	568
a16942e6 MK	569	sg_items[0].transfer_id = 0;
	570	sg_items[0].transfer_context = NULL;
	571	sg_items[0].vaddr = &skb_cb->htt.txbuf->htc_hdr;
	572	sg_items[0].paddr = skb_cb->htt.txbuf_paddr +
	573	sizeof(skb_cb->htt.txbuf->frags);
	574	sg_items[0].len = sizeof(skb_cb->htt.txbuf->htc_hdr) +
	575	sizeof(skb_cb->htt.txbuf->cmd_hdr) +
	576	sizeof(skb_cb->htt.txbuf->cmd_tx);
	577
	578	sg_items[1].transfer_id = 0;
	579	sg_items[1].transfer_context = NULL;
	580	sg_items[1].vaddr = msdu->data;
	581	sg_items[1].paddr = skb_cb->paddr;
	582	sg_items[1].len = prefetch_len;
	583
	584	res = ath10k_hif_tx_sg(htt->ar,
	585	htt->ar->htc.endpoint[htt->eid].ul_pipe_id,
	586	sg_items, ARRAY_SIZE(sg_items));
5e3dd157	587	if (res)
1f8bb151	588	goto err_unmap_msdu;
5e3dd157 KV	589
5e3dd157 KV	590	return 0;
2f3773bc	591
2f3773bc	592	err_unmap_msdu:
767d34fc	593	dma_unmap_single(dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
a16942e6 MK	594	err_free_txbuf:
	595	dma_pool_free(htt->tx_pool,
	596	skb_cb->htt.txbuf,
	597	skb_cb->htt.txbuf_paddr);
2f3773bc MK	598	err_free_msdu_id:
	599	spin_lock_bh(&htt->tx_lock);
	600	htt->pending_tx[msdu_id] = NULL;
	601	ath10k_htt_tx_free_msdu_id(htt, msdu_id);
	602	spin_unlock_bh(&htt->tx_lock);
	603	err_tx_dec:
5e3dd157	604	ath10k_htt_tx_dec_pending(htt);
2f3773bc	605	err:
5e3dd157 KV	606	return res;
5e3dd157 KV	607	}