[deliverable/linux.git] / drivers / net / wireless / ath / ath10k / hw.h

/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef _HW_H_
#define _HW_H_

#include "targaddrs.h"

#define ATH10K_FW_DIR			"ath10k"

/* QCA988X 1.0 definitions (unsupported) */
#define QCA988X_HW_1_0_CHIP_ID_REV	0x0

/* QCA988X 2.0 definitions */
#define QCA988X_HW_2_0_VERSION		0x4100016c
#define QCA988X_HW_2_0_CHIP_ID_REV	0x2
#define QCA988X_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA988X/hw2.0"
#define QCA988X_HW_2_0_FW_FILE		"firmware.bin"
#define QCA988X_HW_2_0_OTP_FILE		"otp.bin"
#define QCA988X_HW_2_0_BOARD_DATA_FILE	"board.bin"
#define QCA988X_HW_2_0_PATCH_LOAD_ADDR	0x1234

#define ATH10K_FW_API2_FILE		"firmware-2.bin"
#define ATH10K_FW_API3_FILE		"firmware-3.bin"

#define ATH10K_FW_UTF_FILE		"utf.bin"

/* includes also the null byte */
#define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"

#define REG_DUMP_COUNT_QCA988X 60

#define QCA988X_CAL_DATA_LEN		2116

struct ath10k_fw_ie {
	__le32 id;
	__le32 len;
	u8 data[0];
};

enum ath10k_fw_ie_type {
	ATH10K_FW_IE_FW_VERSION = 0,
	ATH10K_FW_IE_TIMESTAMP = 1,
	ATH10K_FW_IE_FEATURES = 2,
	ATH10K_FW_IE_FW_IMAGE = 3,
	ATH10K_FW_IE_OTP_IMAGE = 4,

	/* WMI "operations" interface version, 32 bit value. Supported from
	 * FW API 4 and above.
	 */
	ATH10K_FW_IE_WMI_OP_VERSION = 5,
};

enum ath10k_fw_wmi_op_version {
	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,

	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
	ATH10K_FW_WMI_OP_VERSION_TLV = 4,

	/* keep last */
	ATH10K_FW_WMI_OP_VERSION_MAX,
};

/* Known pecularities:
 *  - current FW doesn't support raw rx mode (last tested v599)
 *  - current FW dumps upon raw tx mode (last tested v599)
 *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
 *  - raw have FCS, nwifi doesn't
 *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
 *    param, llc/snap) are aligned to 4byte boundaries each */
enum ath10k_hw_txrx_mode {
	ATH10K_HW_TXRX_RAW = 0,
	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
	ATH10K_HW_TXRX_ETHERNET = 2,

	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
	ATH10K_HW_TXRX_MGMT = 3,
};

enum ath10k_mcast2ucast_mode {
	ATH10K_MCAST2UCAST_DISABLED = 0,
	ATH10K_MCAST2UCAST_ENABLED = 1,
};

struct ath10k_pktlog_hdr {
	__le16 flags;
	__le16 missed_cnt;
	__le16 log_type;
	__le16 size;
	__le32 timestamp;
	u8 payload[0];
} __packed;

/* Target specific defines for MAIN firmware */
#define TARGET_NUM_VDEVS			8
#define TARGET_NUM_PEER_AST			2
#define TARGET_NUM_WDS_ENTRIES			32
#define TARGET_DMA_BURST_SIZE			0
#define TARGET_MAC_AGGR_DELIM			0
#define TARGET_AST_SKID_LIMIT			16
#define TARGET_NUM_STATIONS			16
#define TARGET_NUM_PEERS			((TARGET_NUM_STATIONS) + \
						 (TARGET_NUM_VDEVS))
#define TARGET_NUM_OFFLOAD_PEERS		0
#define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
#define TARGET_NUM_PEER_KEYS			2
#define TARGET_NUM_TIDS				((TARGET_NUM_PEERS) * 2)
#define TARGET_TX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
#define TARGET_RX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
#define TARGET_RX_TIMEOUT_LO_PRI		100
#define TARGET_RX_TIMEOUT_HI_PRI		40

/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
 * avoid a very expensive re-alignment in mac80211. */
#define TARGET_RX_DECAP_MODE			ATH10K_HW_TXRX_NATIVE_WIFI

#define TARGET_SCAN_MAX_PENDING_REQS		4
#define TARGET_BMISS_OFFLOAD_MAX_VDEV		3
#define TARGET_ROAM_OFFLOAD_MAX_VDEV		3
#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES	8
#define TARGET_GTK_OFFLOAD_MAX_VDEV		3
#define TARGET_NUM_MCAST_GROUPS			0
#define TARGET_NUM_MCAST_TABLE_ELEMS		0
#define TARGET_MCAST2UCAST_MODE			ATH10K_MCAST2UCAST_DISABLED
#define TARGET_TX_DBG_LOG_SIZE			1024
#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
#define TARGET_VOW_CONFIG			0
#define TARGET_NUM_MSDU_DESC			(1024 + 400)
#define TARGET_MAX_FRAG_ENTRIES			0

/* Target specific defines for 10.X firmware */
#define TARGET_10X_NUM_VDEVS			16
#define TARGET_10X_NUM_PEER_AST			2
#define TARGET_10X_NUM_WDS_ENTRIES		32
#define TARGET_10X_DMA_BURST_SIZE		0
#define TARGET_10X_MAC_AGGR_DELIM		0
#define TARGET_10X_AST_SKID_LIMIT		16
#define TARGET_10X_NUM_STATIONS			128
#define TARGET_10X_NUM_PEERS			((TARGET_10X_NUM_STATIONS) + \
						 (TARGET_10X_NUM_VDEVS))
#define TARGET_10X_NUM_OFFLOAD_PEERS		0
#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS	0
#define TARGET_10X_NUM_PEER_KEYS		2
#define TARGET_10X_NUM_TIDS_MAX			256
#define TARGET_10X_NUM_TIDS			min((TARGET_10X_NUM_TIDS_MAX), \
						    (TARGET_10X_NUM_PEERS) * 2)
#define TARGET_10X_TX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
#define TARGET_10X_RX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
#define TARGET_10X_RX_TIMEOUT_LO_PRI		100
#define TARGET_10X_RX_TIMEOUT_HI_PRI		40
#define TARGET_10X_RX_DECAP_MODE		ATH10K_HW_TXRX_NATIVE_WIFI
#define TARGET_10X_SCAN_MAX_PENDING_REQS	4
#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV	2
#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV	2
#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES	8
#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV		3
#define TARGET_10X_NUM_MCAST_GROUPS		0
#define TARGET_10X_NUM_MCAST_TABLE_ELEMS	0
#define TARGET_10X_MCAST2UCAST_MODE		ATH10K_MCAST2UCAST_DISABLED
#define TARGET_10X_TX_DBG_LOG_SIZE		1024
#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
#define TARGET_10X_VOW_CONFIG			0
#define TARGET_10X_NUM_MSDU_DESC		(1024 + 400)
#define TARGET_10X_MAX_FRAG_ENTRIES		0

/* Target specific defines for WMI-TLV firmware */
#define TARGET_TLV_NUM_VDEVS			3
#define TARGET_TLV_NUM_STATIONS			32
#define TARGET_TLV_NUM_PEERS			((TARGET_TLV_NUM_STATIONS) + \
						 (TARGET_TLV_NUM_VDEVS) + \
						 2)
#define TARGET_TLV_NUM_TIDS			((TARGET_TLV_NUM_PEERS) * 2)
#define TARGET_TLV_NUM_MSDU_DESC		(1024 + 32)

/* Number of Copy Engines supported */
#define CE_COUNT 8

/*
 * Total number of PCIe MSI interrupts requested for all interrupt sources.
 * PCIe standard forces this to be a power of 2.
 * Some Host OS's limit MSI requests that can be granted to 8
 * so for now we abide by this limit and avoid requesting more
 * than that.
 */
#define MSI_NUM_REQUEST_LOG2	3
#define MSI_NUM_REQUEST		(1<<MSI_NUM_REQUEST_LOG2)

/*
 * Granted MSIs are assigned as follows:
 * Firmware uses the first
 * Remaining MSIs, if any, are used by Copy Engines
 * This mapping is known to both Target firmware and Host software.
 * It may be changed as long as Host and Target are kept in sync.
 */
/* MSI for firmware (errors, etc.) */
#define MSI_ASSIGN_FW		0

/* MSIs for Copy Engines */
#define MSI_ASSIGN_CE_INITIAL	1
#define MSI_ASSIGN_CE_MAX	7

/* as of IP3.7.1 */
#define RTC_STATE_V_ON				3

#define RTC_STATE_COLD_RESET_MASK		0x00000400
#define RTC_STATE_V_LSB				0
#define RTC_STATE_V_MASK			0x00000007
#define RTC_STATE_ADDRESS			0x0000
#define PCIE_SOC_WAKE_V_MASK			0x00000001
#define PCIE_SOC_WAKE_ADDRESS			0x0004
#define PCIE_SOC_WAKE_RESET			0x00000000
#define SOC_GLOBAL_RESET_ADDRESS		0x0008

#define RTC_SOC_BASE_ADDRESS			0x00004000
#define RTC_WMAC_BASE_ADDRESS			0x00005000
#define MAC_COEX_BASE_ADDRESS			0x00006000
#define BT_COEX_BASE_ADDRESS			0x00007000
#define SOC_PCIE_BASE_ADDRESS			0x00008000
#define SOC_CORE_BASE_ADDRESS			0x00009000
#define WLAN_UART_BASE_ADDRESS			0x0000c000
#define WLAN_SI_BASE_ADDRESS			0x00010000
#define WLAN_GPIO_BASE_ADDRESS			0x00014000
#define WLAN_ANALOG_INTF_BASE_ADDRESS		0x0001c000
#define WLAN_MAC_BASE_ADDRESS			0x00020000
#define EFUSE_BASE_ADDRESS			0x00030000
#define FPGA_REG_BASE_ADDRESS			0x00039000
#define WLAN_UART2_BASE_ADDRESS			0x00054c00
#define CE_WRAPPER_BASE_ADDRESS			0x00057000
#define CE0_BASE_ADDRESS			0x00057400
#define CE1_BASE_ADDRESS			0x00057800
#define CE2_BASE_ADDRESS			0x00057c00
#define CE3_BASE_ADDRESS			0x00058000
#define CE4_BASE_ADDRESS			0x00058400
#define CE5_BASE_ADDRESS			0x00058800
#define CE6_BASE_ADDRESS			0x00058c00
#define CE7_BASE_ADDRESS			0x00059000
#define DBI_BASE_ADDRESS			0x00060000
#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000
#define PCIE_LOCAL_BASE_ADDRESS			0x00080000

#define SOC_RESET_CONTROL_ADDRESS		0x00000000
#define SOC_RESET_CONTROL_OFFSET		0x00000000
#define SOC_RESET_CONTROL_SI0_RST_MASK		0x00000001
#define SOC_RESET_CONTROL_CE_RST_MASK		0x00040000
#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK	0x00000040
#define SOC_CPU_CLOCK_OFFSET			0x00000020
#define SOC_CPU_CLOCK_STANDARD_LSB		0
#define SOC_CPU_CLOCK_STANDARD_MASK		0x00000003
#define SOC_CLOCK_CONTROL_OFFSET		0x00000028
#define SOC_CLOCK_CONTROL_SI0_CLK_MASK		0x00000001
#define SOC_SYSTEM_SLEEP_OFFSET			0x000000c4
#define SOC_LPO_CAL_OFFSET			0x000000e0
#define SOC_LPO_CAL_ENABLE_LSB			20
#define SOC_LPO_CAL_ENABLE_MASK			0x00100000
#define SOC_LF_TIMER_CONTROL0_ADDRESS		0x00000050
#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK	0x00000004

#define SOC_CHIP_ID_ADDRESS			0x000000ec
#define SOC_CHIP_ID_REV_LSB			8
#define SOC_CHIP_ID_REV_MASK			0x00000f00

#define WLAN_RESET_CONTROL_COLD_RST_MASK	0x00000008
#define WLAN_RESET_CONTROL_WARM_RST_MASK	0x00000004
#define WLAN_SYSTEM_SLEEP_DISABLE_LSB		0
#define WLAN_SYSTEM_SLEEP_DISABLE_MASK		0x00000001

#define WLAN_GPIO_PIN0_ADDRESS			0x00000028
#define WLAN_GPIO_PIN0_CONFIG_MASK		0x00007800
#define WLAN_GPIO_PIN1_ADDRESS			0x0000002c
#define WLAN_GPIO_PIN1_CONFIG_MASK		0x00007800
#define WLAN_GPIO_PIN10_ADDRESS			0x00000050
#define WLAN_GPIO_PIN11_ADDRESS			0x00000054
#define WLAN_GPIO_PIN12_ADDRESS			0x00000058
#define WLAN_GPIO_PIN13_ADDRESS			0x0000005c

#define CLOCK_GPIO_OFFSET			0xffffffff
#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB		0
#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK		0

#define SI_CONFIG_OFFSET			0x00000000
#define SI_CONFIG_BIDIR_OD_DATA_LSB		18
#define SI_CONFIG_BIDIR_OD_DATA_MASK		0x00040000
#define SI_CONFIG_I2C_LSB			16
#define SI_CONFIG_I2C_MASK			0x00010000
#define SI_CONFIG_POS_SAMPLE_LSB		7
#define SI_CONFIG_POS_SAMPLE_MASK		0x00000080
#define SI_CONFIG_INACTIVE_DATA_LSB		5
#define SI_CONFIG_INACTIVE_DATA_MASK		0x00000020
#define SI_CONFIG_INACTIVE_CLK_LSB		4
#define SI_CONFIG_INACTIVE_CLK_MASK		0x00000010
#define SI_CONFIG_DIVIDER_LSB			0
#define SI_CONFIG_DIVIDER_MASK			0x0000000f
#define SI_CS_OFFSET				0x00000004
#define SI_CS_DONE_ERR_MASK			0x00000400
#define SI_CS_DONE_INT_MASK			0x00000200
#define SI_CS_START_LSB				8
#define SI_CS_START_MASK			0x00000100
#define SI_CS_RX_CNT_LSB			4
#define SI_CS_RX_CNT_MASK			0x000000f0
#define SI_CS_TX_CNT_LSB			0
#define SI_CS_TX_CNT_MASK			0x0000000f

#define SI_TX_DATA0_OFFSET			0x00000008
#define SI_TX_DATA1_OFFSET			0x0000000c
#define SI_RX_DATA0_OFFSET			0x00000010
#define SI_RX_DATA1_OFFSET			0x00000014

#define CORE_CTRL_CPU_INTR_MASK			0x00002000
#define CORE_CTRL_PCIE_REG_31_MASK		0x00000800
#define CORE_CTRL_ADDRESS			0x0000
#define PCIE_INTR_ENABLE_ADDRESS		0x0008
#define PCIE_INTR_CAUSE_ADDRESS			0x000c
#define PCIE_INTR_CLR_ADDRESS			0x0014
#define SCRATCH_3_ADDRESS			0x0030
#define CPU_INTR_ADDRESS			0x0010

/* Firmware indications to the Host via SCRATCH_3 register. */
#define FW_INDICATOR_ADDRESS	(SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
#define FW_IND_EVENT_PENDING			1
#define FW_IND_INITIALIZED			2

/* HOST_REG interrupt from firmware */
#define PCIE_INTR_FIRMWARE_MASK			0x00000400
#define PCIE_INTR_CE_MASK_ALL			0x0007f800

#define DRAM_BASE_ADDRESS			0x00400000

#define MISSING 0

#define SYSTEM_SLEEP_OFFSET			SOC_SYSTEM_SLEEP_OFFSET
#define WLAN_SYSTEM_SLEEP_OFFSET		SOC_SYSTEM_SLEEP_OFFSET
#define WLAN_RESET_CONTROL_OFFSET		SOC_RESET_CONTROL_OFFSET
#define CLOCK_CONTROL_OFFSET			SOC_CLOCK_CONTROL_OFFSET
#define CLOCK_CONTROL_SI0_CLK_MASK		SOC_CLOCK_CONTROL_SI0_CLK_MASK
#define RESET_CONTROL_MBOX_RST_MASK		MISSING
#define RESET_CONTROL_SI0_RST_MASK		SOC_RESET_CONTROL_SI0_RST_MASK
#define GPIO_BASE_ADDRESS			WLAN_GPIO_BASE_ADDRESS
#define GPIO_PIN0_OFFSET			WLAN_GPIO_PIN0_ADDRESS
#define GPIO_PIN1_OFFSET			WLAN_GPIO_PIN1_ADDRESS
#define GPIO_PIN0_CONFIG_MASK			WLAN_GPIO_PIN0_CONFIG_MASK
#define GPIO_PIN1_CONFIG_MASK			WLAN_GPIO_PIN1_CONFIG_MASK
#define SI_BASE_ADDRESS				WLAN_SI_BASE_ADDRESS
#define SCRATCH_BASE_ADDRESS			SOC_CORE_BASE_ADDRESS
#define LOCAL_SCRATCH_OFFSET			0x18
#define CPU_CLOCK_OFFSET			SOC_CPU_CLOCK_OFFSET
#define LPO_CAL_OFFSET				SOC_LPO_CAL_OFFSET
#define GPIO_PIN10_OFFSET			WLAN_GPIO_PIN10_ADDRESS
#define GPIO_PIN11_OFFSET			WLAN_GPIO_PIN11_ADDRESS
#define GPIO_PIN12_OFFSET			WLAN_GPIO_PIN12_ADDRESS
#define GPIO_PIN13_OFFSET			WLAN_GPIO_PIN13_ADDRESS
#define CPU_CLOCK_STANDARD_LSB			SOC_CPU_CLOCK_STANDARD_LSB
#define CPU_CLOCK_STANDARD_MASK			SOC_CPU_CLOCK_STANDARD_MASK
#define LPO_CAL_ENABLE_LSB			SOC_LPO_CAL_ENABLE_LSB
#define LPO_CAL_ENABLE_MASK			SOC_LPO_CAL_ENABLE_MASK
#define ANALOG_INTF_BASE_ADDRESS		WLAN_ANALOG_INTF_BASE_ADDRESS
#define MBOX_BASE_ADDRESS			MISSING
#define INT_STATUS_ENABLE_ERROR_LSB		MISSING
#define INT_STATUS_ENABLE_ERROR_MASK		MISSING
#define INT_STATUS_ENABLE_CPU_LSB		MISSING
#define INT_STATUS_ENABLE_CPU_MASK		MISSING
#define INT_STATUS_ENABLE_COUNTER_LSB		MISSING
#define INT_STATUS_ENABLE_COUNTER_MASK		MISSING
#define INT_STATUS_ENABLE_MBOX_DATA_LSB		MISSING
#define INT_STATUS_ENABLE_MBOX_DATA_MASK	MISSING
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB	MISSING
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK	MISSING
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB	MISSING
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK	MISSING
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB	MISSING
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK	MISSING
#define INT_STATUS_ENABLE_ADDRESS		MISSING
#define CPU_INT_STATUS_ENABLE_BIT_LSB		MISSING
#define CPU_INT_STATUS_ENABLE_BIT_MASK		MISSING
#define HOST_INT_STATUS_ADDRESS			MISSING
#define CPU_INT_STATUS_ADDRESS			MISSING
#define ERROR_INT_STATUS_ADDRESS		MISSING
#define ERROR_INT_STATUS_WAKEUP_MASK		MISSING
#define ERROR_INT_STATUS_WAKEUP_LSB		MISSING
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK	MISSING
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB	MISSING
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK	MISSING
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB	MISSING
#define COUNT_DEC_ADDRESS			MISSING
#define HOST_INT_STATUS_CPU_MASK		MISSING
#define HOST_INT_STATUS_CPU_LSB			MISSING
#define HOST_INT_STATUS_ERROR_MASK		MISSING
#define HOST_INT_STATUS_ERROR_LSB		MISSING
#define HOST_INT_STATUS_COUNTER_MASK		MISSING
#define HOST_INT_STATUS_COUNTER_LSB		MISSING
#define RX_LOOKAHEAD_VALID_ADDRESS		MISSING
#define WINDOW_DATA_ADDRESS			MISSING
#define WINDOW_READ_ADDR_ADDRESS		MISSING
#define WINDOW_WRITE_ADDR_ADDRESS		MISSING

#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)

#endif /* _HW_H_ */
Commit	Line	Data
5e3dd157 KV	1	/*
	2	* Copyright (c) 2005-2011 Atheros Communications Inc.
	3	* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
	4	*
	5	* Permission to use, copy, modify, and/or distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*/
	17
	18	#ifndef _HW_H_
	19	#define _HW_H_
	20
	21	#include "targaddrs.h"
	22
a58227ef KV	23	#define ATH10K_FW_DIR "ath10k"
a58227ef KV	24
e01ae68c KV	25	/* QCA988X 1.0 definitions (unsupported) */
	26	#define QCA988X_HW_1_0_CHIP_ID_REV 0x0
	27
5e3dd157 KV	28	/* QCA988X 2.0 definitions */
5e3dd157 KV	29	#define QCA988X_HW_2_0_VERSION 0x4100016c
e01ae68c	30	#define QCA988X_HW_2_0_CHIP_ID_REV 0x2
a58227ef	31	#define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
5e3dd157 KV	32	#define QCA988X_HW_2_0_FW_FILE "firmware.bin"
	33	#define QCA988X_HW_2_0_OTP_FILE "otp.bin"
	34	#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
	35	#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
	36
1a222435	37	#define ATH10K_FW_API2_FILE "firmware-2.bin"
24c88f78	38	#define ATH10K_FW_API3_FILE "firmware-3.bin"
1a222435	39
43d2a30f KV	40	#define ATH10K_FW_UTF_FILE "utf.bin"
43d2a30f KV	41
1a222435 KV	42	/* includes also the null byte */
	43	#define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
	44
384914b2 BG	45	#define REG_DUMP_COUNT_QCA988X 60
384914b2 BG	46
7869b4fa KV	47	#define QCA988X_CAL_DATA_LEN 2116
7869b4fa KV	48
1a222435 KV	49	struct ath10k_fw_ie {
	50	__le32 id;
	51	__le32 len;
	52	u8 data[0];
	53	};
	54
	55	enum ath10k_fw_ie_type {
	56	ATH10K_FW_IE_FW_VERSION = 0,
	57	ATH10K_FW_IE_TIMESTAMP = 1,
	58	ATH10K_FW_IE_FEATURES = 2,
	59	ATH10K_FW_IE_FW_IMAGE = 3,
	60	ATH10K_FW_IE_OTP_IMAGE = 4,
202e86e6 KV	61
	62	/* WMI "operations" interface version, 32 bit value. Supported from
	63	* FW API 4 and above.
	64	*/
	65	ATH10K_FW_IE_WMI_OP_VERSION = 5,
	66	};
	67
	68	enum ath10k_fw_wmi_op_version {
	69	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
	70
	71	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
	72	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
	73	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
ca996ec5	74	ATH10K_FW_WMI_OP_VERSION_TLV = 4,
202e86e6 KV	75
	76	/* keep last */
	77	ATH10K_FW_WMI_OP_VERSION_MAX,
1a222435 KV	78	};
1a222435 KV	79
5e3dd157 KV	80	/* Known pecularities:
	81	* - current FW doesn't support raw rx mode (last tested v599)
	82	* - current FW dumps upon raw tx mode (last tested v599)
	83	* - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
	84	* - raw have FCS, nwifi doesn't
	85	* - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
	86	* param, llc/snap) are aligned to 4byte boundaries each */
	87	enum ath10k_hw_txrx_mode {
	88	ATH10K_HW_TXRX_RAW = 0,
	89	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
	90	ATH10K_HW_TXRX_ETHERNET = 2,
961d4c38 MK	91
	92	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
	93	ATH10K_HW_TXRX_MGMT = 3,
5e3dd157 KV	94	};
	95
	96	enum ath10k_mcast2ucast_mode {
	97	ATH10K_MCAST2UCAST_DISABLED = 0,
	98	ATH10K_MCAST2UCAST_ENABLED = 1,
	99	};
	100
bfdd7937 RM	101	struct ath10k_pktlog_hdr {
	102	__le16 flags;
	103	__le16 missed_cnt;
	104	__le16 log_type;
	105	__le16 size;
	106	__le32 timestamp;
	107	u8 payload[0];
	108	} __packed;
	109
ec6a73f0	110	/* Target specific defines for MAIN firmware */
5e3dd157 KV	111	#define TARGET_NUM_VDEVS 8
	112	#define TARGET_NUM_PEER_AST 2
	113	#define TARGET_NUM_WDS_ENTRIES 32
	114	#define TARGET_DMA_BURST_SIZE 0
	115	#define TARGET_MAC_AGGR_DELIM 0
	116	#define TARGET_AST_SKID_LIMIT 16
cfd1061e MK	117	#define TARGET_NUM_STATIONS 16
	118	#define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \
	119	(TARGET_NUM_VDEVS))
5e3dd157 KV	120	#define TARGET_NUM_OFFLOAD_PEERS 0
	121	#define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
	122	#define TARGET_NUM_PEER_KEYS 2
cfd1061e	123	#define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2)
5e3dd157 KV	124	#define TARGET_TX_CHAIN_MASK (BIT(0) \| BIT(1) \| BIT(2))
	125	#define TARGET_RX_CHAIN_MASK (BIT(0) \| BIT(1) \| BIT(2))
	126	#define TARGET_RX_TIMEOUT_LO_PRI 100
	127	#define TARGET_RX_TIMEOUT_HI_PRI 40
4d316c79 MK	128
	129	/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
	130	* avoid a very expensive re-alignment in mac80211. */
	131	#define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
	132
5e3dd157 KV	133	#define TARGET_SCAN_MAX_PENDING_REQS 4
	134	#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
	135	#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
	136	#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
	137	#define TARGET_GTK_OFFLOAD_MAX_VDEV 3
	138	#define TARGET_NUM_MCAST_GROUPS 0
	139	#define TARGET_NUM_MCAST_TABLE_ELEMS 0
	140	#define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
	141	#define TARGET_TX_DBG_LOG_SIZE 1024
	142	#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
	143	#define TARGET_VOW_CONFIG 0
	144	#define TARGET_NUM_MSDU_DESC (1024 + 400)
	145	#define TARGET_MAX_FRAG_ENTRIES 0
	146
ec6a73f0 BM	147	/* Target specific defines for 10.X firmware */
	148	#define TARGET_10X_NUM_VDEVS 16
	149	#define TARGET_10X_NUM_PEER_AST 2
	150	#define TARGET_10X_NUM_WDS_ENTRIES 32
	151	#define TARGET_10X_DMA_BURST_SIZE 0
	152	#define TARGET_10X_MAC_AGGR_DELIM 0
	153	#define TARGET_10X_AST_SKID_LIMIT 16
cfd1061e MK	154	#define TARGET_10X_NUM_STATIONS 128
	155	#define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \
	156	(TARGET_10X_NUM_VDEVS))
ec6a73f0 BM	157	#define TARGET_10X_NUM_OFFLOAD_PEERS 0
	158	#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
	159	#define TARGET_10X_NUM_PEER_KEYS 2
cfd1061e MK	160	#define TARGET_10X_NUM_TIDS_MAX 256
	161	#define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
	162	(TARGET_10X_NUM_PEERS) * 2)
ec6a73f0 BM	163	#define TARGET_10X_TX_CHAIN_MASK (BIT(0) \| BIT(1) \| BIT(2))
	164	#define TARGET_10X_RX_CHAIN_MASK (BIT(0) \| BIT(1) \| BIT(2))
	165	#define TARGET_10X_RX_TIMEOUT_LO_PRI 100
	166	#define TARGET_10X_RX_TIMEOUT_HI_PRI 40
0d1a28f2	167	#define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
ec6a73f0 BM	168	#define TARGET_10X_SCAN_MAX_PENDING_REQS 4
	169	#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
	170	#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
	171	#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
	172	#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
	173	#define TARGET_10X_NUM_MCAST_GROUPS 0
	174	#define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
	175	#define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
	176	#define TARGET_10X_TX_DBG_LOG_SIZE 1024
	177	#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
	178	#define TARGET_10X_VOW_CONFIG 0
	179	#define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
	180	#define TARGET_10X_MAX_FRAG_ENTRIES 0
5e3dd157	181
ca996ec5 MK	182	/* Target specific defines for WMI-TLV firmware */
	183	#define TARGET_TLV_NUM_VDEVS 3
	184	#define TARGET_TLV_NUM_STATIONS 32
	185	#define TARGET_TLV_NUM_PEERS ((TARGET_TLV_NUM_STATIONS) + \
	186	(TARGET_TLV_NUM_VDEVS) + \
	187	2)
	188	#define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2)
	189	#define TARGET_TLV_NUM_MSDU_DESC (1024 + 32)
	190
5e3dd157 KV	191	/* Number of Copy Engines supported */
	192	#define CE_COUNT 8
	193
	194	/*
	195	* Total number of PCIe MSI interrupts requested for all interrupt sources.
	196	* PCIe standard forces this to be a power of 2.
	197	* Some Host OS's limit MSI requests that can be granted to 8
	198	* so for now we abide by this limit and avoid requesting more
	199	* than that.
	200	*/
	201	#define MSI_NUM_REQUEST_LOG2 3
	202	#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
	203
	204	/*
	205	* Granted MSIs are assigned as follows:
	206	* Firmware uses the first
	207	* Remaining MSIs, if any, are used by Copy Engines
	208	* This mapping is known to both Target firmware and Host software.
	209	* It may be changed as long as Host and Target are kept in sync.
	210	*/
	211	/* MSI for firmware (errors, etc.) */
	212	#define MSI_ASSIGN_FW 0
	213
	214	/* MSIs for Copy Engines */
	215	#define MSI_ASSIGN_CE_INITIAL 1
	216	#define MSI_ASSIGN_CE_MAX 7
	217
	218	/* as of IP3.7.1 */
	219	#define RTC_STATE_V_ON 3
	220
	221	#define RTC_STATE_COLD_RESET_MASK 0x00000400
	222	#define RTC_STATE_V_LSB 0
	223	#define RTC_STATE_V_MASK 0x00000007
	224	#define RTC_STATE_ADDRESS 0x0000
	225	#define PCIE_SOC_WAKE_V_MASK 0x00000001
	226	#define PCIE_SOC_WAKE_ADDRESS 0x0004
	227	#define PCIE_SOC_WAKE_RESET 0x00000000
	228	#define SOC_GLOBAL_RESET_ADDRESS 0x0008
	229
	230	#define RTC_SOC_BASE_ADDRESS 0x00004000
	231	#define RTC_WMAC_BASE_ADDRESS 0x00005000
	232	#define MAC_COEX_BASE_ADDRESS 0x00006000
	233	#define BT_COEX_BASE_ADDRESS 0x00007000
	234	#define SOC_PCIE_BASE_ADDRESS 0x00008000
	235	#define SOC_CORE_BASE_ADDRESS 0x00009000
	236	#define WLAN_UART_BASE_ADDRESS 0x0000c000
	237	#define WLAN_SI_BASE_ADDRESS 0x00010000
	238	#define WLAN_GPIO_BASE_ADDRESS 0x00014000
	239	#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
	240	#define WLAN_MAC_BASE_ADDRESS 0x00020000
	241	#define EFUSE_BASE_ADDRESS 0x00030000
	242	#define FPGA_REG_BASE_ADDRESS 0x00039000
	243	#define WLAN_UART2_BASE_ADDRESS 0x00054c00
	244	#define CE_WRAPPER_BASE_ADDRESS 0x00057000
	245	#define CE0_BASE_ADDRESS 0x00057400
	246	#define CE1_BASE_ADDRESS 0x00057800
	247	#define CE2_BASE_ADDRESS 0x00057c00
	248	#define CE3_BASE_ADDRESS 0x00058000
	249	#define CE4_BASE_ADDRESS 0x00058400
	250	#define CE5_BASE_ADDRESS 0x00058800
	251	#define CE6_BASE_ADDRESS 0x00058c00
	252	#define CE7_BASE_ADDRESS 0x00059000
	253	#define DBI_BASE_ADDRESS 0x00060000
	254	#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
255	#define PCIE_LOCAL_BASE_ADDRESS 0x00080000
256
fc36e3ff	257	#define SOC_RESET_CONTROL_ADDRESS 0x00000000
5e3dd157 KV	258	#define SOC_RESET_CONTROL_OFFSET 0x00000000
5e3dd157 KV	259	#define SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001
fc36e3ff MK	260	#define SOC_RESET_CONTROL_CE_RST_MASK 0x00040000
fc36e3ff MK	261	#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
5e3dd157 KV	262	#define SOC_CPU_CLOCK_OFFSET 0x00000020
	263	#define SOC_CPU_CLOCK_STANDARD_LSB 0
	264	#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
	265	#define SOC_CLOCK_CONTROL_OFFSET 0x00000028
	266	#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
	267	#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
	268	#define SOC_LPO_CAL_OFFSET 0x000000e0
	269	#define SOC_LPO_CAL_ENABLE_LSB 20
	270	#define SOC_LPO_CAL_ENABLE_MASK 0x00100000
fc36e3ff MK	271	#define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
fc36e3ff MK	272	#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
5e3dd157	273
e01ae68c KV	274	#define SOC_CHIP_ID_ADDRESS 0x000000ec
	275	#define SOC_CHIP_ID_REV_LSB 8
	276	#define SOC_CHIP_ID_REV_MASK 0x00000f00
	277
5e3dd157 KV	278	#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
	279	#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
	280	#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
	281	#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
	282
	283	#define WLAN_GPIO_PIN0_ADDRESS 0x00000028
	284	#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
	285	#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
	286	#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
	287	#define WLAN_GPIO_PIN10_ADDRESS 0x00000050
	288	#define WLAN_GPIO_PIN11_ADDRESS 0x00000054
	289	#define WLAN_GPIO_PIN12_ADDRESS 0x00000058
	290	#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
	291
	292	#define CLOCK_GPIO_OFFSET 0xffffffff
	293	#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
	294	#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
	295
	296	#define SI_CONFIG_OFFSET 0x00000000
	297	#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
	298	#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
	299	#define SI_CONFIG_I2C_LSB 16
	300	#define SI_CONFIG_I2C_MASK 0x00010000
	301	#define SI_CONFIG_POS_SAMPLE_LSB 7
	302	#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
	303	#define SI_CONFIG_INACTIVE_DATA_LSB 5
	304	#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
	305	#define SI_CONFIG_INACTIVE_CLK_LSB 4
	306	#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
	307	#define SI_CONFIG_DIVIDER_LSB 0
	308	#define SI_CONFIG_DIVIDER_MASK 0x0000000f
	309	#define SI_CS_OFFSET 0x00000004
	310	#define SI_CS_DONE_ERR_MASK 0x00000400
	311	#define SI_CS_DONE_INT_MASK 0x00000200
	312	#define SI_CS_START_LSB 8
	313	#define SI_CS_START_MASK 0x00000100
	314	#define SI_CS_RX_CNT_LSB 4
	315	#define SI_CS_RX_CNT_MASK 0x000000f0
	316	#define SI_CS_TX_CNT_LSB 0
	317	#define SI_CS_TX_CNT_MASK 0x0000000f
	318
	319	#define SI_TX_DATA0_OFFSET 0x00000008
	320	#define SI_TX_DATA1_OFFSET 0x0000000c
	321	#define SI_RX_DATA0_OFFSET 0x00000010
	322	#define SI_RX_DATA1_OFFSET 0x00000014
	323
	324	#define CORE_CTRL_CPU_INTR_MASK 0x00002000
7c0f0e3c	325	#define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
5e3dd157 KV	326	#define CORE_CTRL_ADDRESS 0x0000
5e3dd157 KV	327	#define PCIE_INTR_ENABLE_ADDRESS 0x0008
e539887b	328	#define PCIE_INTR_CAUSE_ADDRESS 0x000c
5e3dd157 KV	329	#define PCIE_INTR_CLR_ADDRESS 0x0014
5e3dd157 KV	330	#define SCRATCH_3_ADDRESS 0x0030
fc36e3ff	331	#define CPU_INTR_ADDRESS 0x0010
5e3dd157 KV	332
	333	/* Firmware indications to the Host via SCRATCH_3 register. */
	334	#define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
	335	#define FW_IND_EVENT_PENDING 1
	336	#define FW_IND_INITIALIZED 2
	337
	338	/* HOST_REG interrupt from firmware */
	339	#define PCIE_INTR_FIRMWARE_MASK 0x00000400
	340	#define PCIE_INTR_CE_MASK_ALL 0x0007f800
	341
	342	#define DRAM_BASE_ADDRESS 0x00400000
	343
	344	#define MISSING 0
	345
	346	#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
	347	#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
	348	#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
	349	#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
	350	#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
	351	#define RESET_CONTROL_MBOX_RST_MASK MISSING
	352	#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
	353	#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
	354	#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
	355	#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
	356	#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
	357	#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
	358	#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
	359	#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
	360	#define LOCAL_SCRATCH_OFFSET 0x18
	361	#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
	362	#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
	363	#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
	364	#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
	365	#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
	366	#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
	367	#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
	368	#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
	369	#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
	370	#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
	371	#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
	372	#define MBOX_BASE_ADDRESS MISSING
	373	#define INT_STATUS_ENABLE_ERROR_LSB MISSING
	374	#define INT_STATUS_ENABLE_ERROR_MASK MISSING
	375	#define INT_STATUS_ENABLE_CPU_LSB MISSING
	376	#define INT_STATUS_ENABLE_CPU_MASK MISSING
	377	#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
	378	#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
	379	#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
	380	#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
	381	#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
	382	#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
	383	#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
	384	#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
	385	#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
	386	#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
	387	#define INT_STATUS_ENABLE_ADDRESS MISSING
	388	#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
	389	#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
	390	#define HOST_INT_STATUS_ADDRESS MISSING
	391	#define CPU_INT_STATUS_ADDRESS MISSING
	392	#define ERROR_INT_STATUS_ADDRESS MISSING
	393	#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
	394	#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
	395	#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
396	#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
397	#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
398	#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
399	#define COUNT_DEC_ADDRESS MISSING
400	#define HOST_INT_STATUS_CPU_MASK MISSING
401	#define HOST_INT_STATUS_CPU_LSB MISSING
402	#define HOST_INT_STATUS_ERROR_MASK MISSING
403	#define HOST_INT_STATUS_ERROR_LSB MISSING
404	#define HOST_INT_STATUS_COUNTER_MASK MISSING
405	#define HOST_INT_STATUS_COUNTER_LSB MISSING
406	#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
407	#define WINDOW_DATA_ADDRESS MISSING
408	#define WINDOW_READ_ADDR_ADDRESS MISSING
409	#define WINDOW_WRITE_ADDR_ADDRESS MISSING
410
411	#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
412
413	#endif /* _HW_H_ */