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5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
18 | #include <linux/pci.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/spinlock.h> | |
650b91fb | 22 | #include <linux/bitops.h> |
5e3dd157 KV |
23 | |
24 | #include "core.h" | |
25 | #include "debug.h" | |
26 | ||
27 | #include "targaddrs.h" | |
28 | #include "bmi.h" | |
29 | ||
30 | #include "hif.h" | |
31 | #include "htc.h" | |
32 | ||
33 | #include "ce.h" | |
34 | #include "pci.h" | |
35 | ||
cfe9c45b MK |
36 | enum ath10k_pci_irq_mode { |
37 | ATH10K_PCI_IRQ_AUTO = 0, | |
38 | ATH10K_PCI_IRQ_LEGACY = 1, | |
39 | ATH10K_PCI_IRQ_MSI = 2, | |
40 | }; | |
41 | ||
35098463 KV |
42 | enum ath10k_pci_reset_mode { |
43 | ATH10K_PCI_RESET_AUTO = 0, | |
44 | ATH10K_PCI_RESET_WARM_ONLY = 1, | |
45 | }; | |
46 | ||
cfe9c45b | 47 | static unsigned int ath10k_pci_irq_mode = ATH10K_PCI_IRQ_AUTO; |
35098463 | 48 | static unsigned int ath10k_pci_reset_mode = ATH10K_PCI_RESET_AUTO; |
cfe9c45b | 49 | |
cfe9c45b MK |
50 | module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644); |
51 | MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)"); | |
52 | ||
35098463 KV |
53 | module_param_named(reset_mode, ath10k_pci_reset_mode, uint, 0644); |
54 | MODULE_PARM_DESC(reset_mode, "0: auto, 1: warm only (default: 0)"); | |
55 | ||
0399eca8 KV |
56 | /* how long wait to wait for target to initialise, in ms */ |
57 | #define ATH10K_PCI_TARGET_WAIT 3000 | |
61c95cea | 58 | #define ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS 3 |
0399eca8 | 59 | |
5e3dd157 KV |
60 | #define QCA988X_2_0_DEVICE_ID (0x003c) |
61 | ||
9baa3c34 | 62 | static const struct pci_device_id ath10k_pci_id_table[] = { |
5e3dd157 KV |
63 | { PCI_VDEVICE(ATHEROS, QCA988X_2_0_DEVICE_ID) }, /* PCI-E QCA988X V2 */ |
64 | {0} | |
65 | }; | |
66 | ||
7505f7c3 MK |
67 | static const struct ath10k_pci_supp_chip ath10k_pci_supp_chips[] = { |
68 | /* QCA988X pre 2.0 chips are not supported because they need some nasty | |
69 | * hacks. ath10k doesn't have them and these devices crash horribly | |
70 | * because of that. | |
71 | */ | |
72 | { QCA988X_2_0_DEVICE_ID, QCA988X_HW_2_0_CHIP_ID_REV }, | |
73 | }; | |
74 | ||
728f95ee | 75 | static void ath10k_pci_buffer_cleanup(struct ath10k *ar); |
fc36e3ff MK |
76 | static int ath10k_pci_cold_reset(struct ath10k *ar); |
77 | static int ath10k_pci_warm_reset(struct ath10k *ar); | |
d7fb47f5 | 78 | static int ath10k_pci_wait_for_target_init(struct ath10k *ar); |
fc15ca13 MK |
79 | static int ath10k_pci_init_irq(struct ath10k *ar); |
80 | static int ath10k_pci_deinit_irq(struct ath10k *ar); | |
81 | static int ath10k_pci_request_irq(struct ath10k *ar); | |
82 | static void ath10k_pci_free_irq(struct ath10k *ar); | |
85622cde MK |
83 | static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, |
84 | struct ath10k_ce_pipe *rx_pipe, | |
85 | struct bmi_xfer *xfer); | |
5e3dd157 KV |
86 | |
87 | static const struct ce_attr host_ce_config_wlan[] = { | |
48e9c225 KV |
88 | /* CE0: host->target HTC control and raw streams */ |
89 | { | |
90 | .flags = CE_ATTR_FLAGS, | |
91 | .src_nentries = 16, | |
92 | .src_sz_max = 256, | |
93 | .dest_nentries = 0, | |
94 | }, | |
95 | ||
96 | /* CE1: target->host HTT + HTC control */ | |
97 | { | |
98 | .flags = CE_ATTR_FLAGS, | |
99 | .src_nentries = 0, | |
100 | .src_sz_max = 512, | |
101 | .dest_nentries = 512, | |
102 | }, | |
103 | ||
104 | /* CE2: target->host WMI */ | |
105 | { | |
106 | .flags = CE_ATTR_FLAGS, | |
107 | .src_nentries = 0, | |
108 | .src_sz_max = 2048, | |
109 | .dest_nentries = 32, | |
110 | }, | |
111 | ||
112 | /* CE3: host->target WMI */ | |
113 | { | |
114 | .flags = CE_ATTR_FLAGS, | |
115 | .src_nentries = 32, | |
116 | .src_sz_max = 2048, | |
117 | .dest_nentries = 0, | |
118 | }, | |
119 | ||
120 | /* CE4: host->target HTT */ | |
121 | { | |
122 | .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR, | |
123 | .src_nentries = CE_HTT_H2T_MSG_SRC_NENTRIES, | |
124 | .src_sz_max = 256, | |
125 | .dest_nentries = 0, | |
126 | }, | |
127 | ||
128 | /* CE5: unused */ | |
129 | { | |
130 | .flags = CE_ATTR_FLAGS, | |
131 | .src_nentries = 0, | |
132 | .src_sz_max = 0, | |
133 | .dest_nentries = 0, | |
134 | }, | |
135 | ||
136 | /* CE6: target autonomous hif_memcpy */ | |
137 | { | |
138 | .flags = CE_ATTR_FLAGS, | |
139 | .src_nentries = 0, | |
140 | .src_sz_max = 0, | |
141 | .dest_nentries = 0, | |
142 | }, | |
143 | ||
144 | /* CE7: ce_diag, the Diagnostic Window */ | |
145 | { | |
146 | .flags = CE_ATTR_FLAGS, | |
147 | .src_nentries = 2, | |
148 | .src_sz_max = DIAG_TRANSFER_LIMIT, | |
149 | .dest_nentries = 2, | |
150 | }, | |
5e3dd157 KV |
151 | }; |
152 | ||
153 | /* Target firmware's Copy Engine configuration. */ | |
154 | static const struct ce_pipe_config target_ce_config_wlan[] = { | |
d88effba KV |
155 | /* CE0: host->target HTC control and raw streams */ |
156 | { | |
0fdc14e4 MK |
157 | .pipenum = __cpu_to_le32(0), |
158 | .pipedir = __cpu_to_le32(PIPEDIR_OUT), | |
159 | .nentries = __cpu_to_le32(32), | |
160 | .nbytes_max = __cpu_to_le32(256), | |
161 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), | |
162 | .reserved = __cpu_to_le32(0), | |
d88effba KV |
163 | }, |
164 | ||
165 | /* CE1: target->host HTT + HTC control */ | |
166 | { | |
0fdc14e4 MK |
167 | .pipenum = __cpu_to_le32(1), |
168 | .pipedir = __cpu_to_le32(PIPEDIR_IN), | |
169 | .nentries = __cpu_to_le32(32), | |
170 | .nbytes_max = __cpu_to_le32(512), | |
171 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), | |
172 | .reserved = __cpu_to_le32(0), | |
d88effba KV |
173 | }, |
174 | ||
175 | /* CE2: target->host WMI */ | |
176 | { | |
0fdc14e4 MK |
177 | .pipenum = __cpu_to_le32(2), |
178 | .pipedir = __cpu_to_le32(PIPEDIR_IN), | |
179 | .nentries = __cpu_to_le32(32), | |
180 | .nbytes_max = __cpu_to_le32(2048), | |
181 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), | |
182 | .reserved = __cpu_to_le32(0), | |
d88effba KV |
183 | }, |
184 | ||
185 | /* CE3: host->target WMI */ | |
186 | { | |
0fdc14e4 MK |
187 | .pipenum = __cpu_to_le32(3), |
188 | .pipedir = __cpu_to_le32(PIPEDIR_OUT), | |
189 | .nentries = __cpu_to_le32(32), | |
190 | .nbytes_max = __cpu_to_le32(2048), | |
191 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), | |
192 | .reserved = __cpu_to_le32(0), | |
d88effba KV |
193 | }, |
194 | ||
195 | /* CE4: host->target HTT */ | |
196 | { | |
0fdc14e4 MK |
197 | .pipenum = __cpu_to_le32(4), |
198 | .pipedir = __cpu_to_le32(PIPEDIR_OUT), | |
199 | .nentries = __cpu_to_le32(256), | |
200 | .nbytes_max = __cpu_to_le32(256), | |
201 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), | |
202 | .reserved = __cpu_to_le32(0), | |
d88effba KV |
203 | }, |
204 | ||
5e3dd157 | 205 | /* NB: 50% of src nentries, since tx has 2 frags */ |
d88effba KV |
206 | |
207 | /* CE5: unused */ | |
208 | { | |
0fdc14e4 MK |
209 | .pipenum = __cpu_to_le32(5), |
210 | .pipedir = __cpu_to_le32(PIPEDIR_OUT), | |
211 | .nentries = __cpu_to_le32(32), | |
212 | .nbytes_max = __cpu_to_le32(2048), | |
213 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), | |
214 | .reserved = __cpu_to_le32(0), | |
d88effba KV |
215 | }, |
216 | ||
217 | /* CE6: Reserved for target autonomous hif_memcpy */ | |
218 | { | |
0fdc14e4 MK |
219 | .pipenum = __cpu_to_le32(6), |
220 | .pipedir = __cpu_to_le32(PIPEDIR_INOUT), | |
221 | .nentries = __cpu_to_le32(32), | |
222 | .nbytes_max = __cpu_to_le32(4096), | |
223 | .flags = __cpu_to_le32(CE_ATTR_FLAGS), | |
224 | .reserved = __cpu_to_le32(0), | |
d88effba KV |
225 | }, |
226 | ||
5e3dd157 KV |
227 | /* CE7 used only by Host */ |
228 | }; | |
229 | ||
d7bfb7aa MK |
230 | /* |
231 | * Map from service/endpoint to Copy Engine. | |
232 | * This table is derived from the CE_PCI TABLE, above. | |
233 | * It is passed to the Target at startup for use by firmware. | |
234 | */ | |
235 | static const struct service_to_pipe target_service_to_ce_map_wlan[] = { | |
236 | { | |
0fdc14e4 MK |
237 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), |
238 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ | |
239 | __cpu_to_le32(3), | |
d7bfb7aa MK |
240 | }, |
241 | { | |
0fdc14e4 MK |
242 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO), |
243 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ | |
244 | __cpu_to_le32(2), | |
d7bfb7aa MK |
245 | }, |
246 | { | |
0fdc14e4 MK |
247 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), |
248 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ | |
249 | __cpu_to_le32(3), | |
d7bfb7aa MK |
250 | }, |
251 | { | |
0fdc14e4 MK |
252 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK), |
253 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ | |
254 | __cpu_to_le32(2), | |
d7bfb7aa MK |
255 | }, |
256 | { | |
0fdc14e4 MK |
257 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), |
258 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ | |
259 | __cpu_to_le32(3), | |
d7bfb7aa MK |
260 | }, |
261 | { | |
0fdc14e4 MK |
262 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE), |
263 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ | |
264 | __cpu_to_le32(2), | |
d7bfb7aa MK |
265 | }, |
266 | { | |
0fdc14e4 MK |
267 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), |
268 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ | |
269 | __cpu_to_le32(3), | |
d7bfb7aa MK |
270 | }, |
271 | { | |
0fdc14e4 MK |
272 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI), |
273 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ | |
274 | __cpu_to_le32(2), | |
d7bfb7aa MK |
275 | }, |
276 | { | |
0fdc14e4 MK |
277 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), |
278 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ | |
279 | __cpu_to_le32(3), | |
d7bfb7aa MK |
280 | }, |
281 | { | |
0fdc14e4 MK |
282 | __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL), |
283 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ | |
284 | __cpu_to_le32(2), | |
d7bfb7aa MK |
285 | }, |
286 | { | |
0fdc14e4 MK |
287 | __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), |
288 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ | |
289 | __cpu_to_le32(0), | |
d7bfb7aa MK |
290 | }, |
291 | { | |
0fdc14e4 MK |
292 | __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL), |
293 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ | |
294 | __cpu_to_le32(1), | |
d7bfb7aa | 295 | }, |
0fdc14e4 MK |
296 | { /* not used */ |
297 | __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), | |
298 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ | |
299 | __cpu_to_le32(0), | |
d7bfb7aa | 300 | }, |
0fdc14e4 MK |
301 | { /* not used */ |
302 | __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS), | |
303 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ | |
304 | __cpu_to_le32(1), | |
d7bfb7aa MK |
305 | }, |
306 | { | |
0fdc14e4 MK |
307 | __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), |
308 | __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ | |
309 | __cpu_to_le32(4), | |
d7bfb7aa MK |
310 | }, |
311 | { | |
0fdc14e4 MK |
312 | __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG), |
313 | __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ | |
314 | __cpu_to_le32(1), | |
d7bfb7aa MK |
315 | }, |
316 | ||
317 | /* (Additions here) */ | |
318 | ||
0fdc14e4 MK |
319 | { /* must be last */ |
320 | __cpu_to_le32(0), | |
321 | __cpu_to_le32(0), | |
322 | __cpu_to_le32(0), | |
d7bfb7aa MK |
323 | }, |
324 | }; | |
325 | ||
e539887b MK |
326 | static bool ath10k_pci_irq_pending(struct ath10k *ar) |
327 | { | |
328 | u32 cause; | |
329 | ||
330 | /* Check if the shared legacy irq is for us */ | |
331 | cause = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + | |
332 | PCIE_INTR_CAUSE_ADDRESS); | |
333 | if (cause & (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL)) | |
334 | return true; | |
335 | ||
336 | return false; | |
337 | } | |
338 | ||
2685218b MK |
339 | static void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar) |
340 | { | |
341 | /* IMPORTANT: INTR_CLR register has to be set after | |
342 | * INTR_ENABLE is set to 0, otherwise interrupt can not be | |
343 | * really cleared. */ | |
344 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, | |
345 | 0); | |
346 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_CLR_ADDRESS, | |
347 | PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); | |
348 | ||
349 | /* IMPORTANT: this extra read transaction is required to | |
350 | * flush the posted write buffer. */ | |
cfbc06a9 KV |
351 | (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + |
352 | PCIE_INTR_ENABLE_ADDRESS); | |
2685218b MK |
353 | } |
354 | ||
355 | static void ath10k_pci_enable_legacy_irq(struct ath10k *ar) | |
356 | { | |
357 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + | |
358 | PCIE_INTR_ENABLE_ADDRESS, | |
359 | PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); | |
360 | ||
361 | /* IMPORTANT: this extra read transaction is required to | |
362 | * flush the posted write buffer. */ | |
cfbc06a9 KV |
363 | (void)ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + |
364 | PCIE_INTR_ENABLE_ADDRESS); | |
2685218b MK |
365 | } |
366 | ||
403d627b | 367 | static inline const char *ath10k_pci_get_irq_method(struct ath10k *ar) |
ab977bd0 | 368 | { |
ab977bd0 MK |
369 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
370 | ||
403d627b MK |
371 | if (ar_pci->num_msi_intrs > 1) |
372 | return "msi-x"; | |
d8bb26b9 KV |
373 | |
374 | if (ar_pci->num_msi_intrs == 1) | |
403d627b | 375 | return "msi"; |
d8bb26b9 KV |
376 | |
377 | return "legacy"; | |
ab977bd0 MK |
378 | } |
379 | ||
728f95ee | 380 | static int __ath10k_pci_rx_post_buf(struct ath10k_pci_pipe *pipe) |
ab977bd0 | 381 | { |
728f95ee | 382 | struct ath10k *ar = pipe->hif_ce_state; |
ab977bd0 | 383 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
728f95ee MK |
384 | struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; |
385 | struct sk_buff *skb; | |
386 | dma_addr_t paddr; | |
ab977bd0 MK |
387 | int ret; |
388 | ||
728f95ee MK |
389 | lockdep_assert_held(&ar_pci->ce_lock); |
390 | ||
391 | skb = dev_alloc_skb(pipe->buf_sz); | |
392 | if (!skb) | |
393 | return -ENOMEM; | |
394 | ||
395 | WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb"); | |
396 | ||
397 | paddr = dma_map_single(ar->dev, skb->data, | |
398 | skb->len + skb_tailroom(skb), | |
399 | DMA_FROM_DEVICE); | |
400 | if (unlikely(dma_mapping_error(ar->dev, paddr))) { | |
7aa7a72a | 401 | ath10k_warn(ar, "failed to dma map pci rx buf\n"); |
728f95ee MK |
402 | dev_kfree_skb_any(skb); |
403 | return -EIO; | |
404 | } | |
405 | ||
406 | ATH10K_SKB_CB(skb)->paddr = paddr; | |
407 | ||
408 | ret = __ath10k_ce_rx_post_buf(ce_pipe, skb, paddr); | |
ab977bd0 | 409 | if (ret) { |
7aa7a72a | 410 | ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); |
728f95ee MK |
411 | dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb), |
412 | DMA_FROM_DEVICE); | |
413 | dev_kfree_skb_any(skb); | |
ab977bd0 MK |
414 | return ret; |
415 | } | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
728f95ee | 420 | static void __ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) |
ab977bd0 | 421 | { |
728f95ee MK |
422 | struct ath10k *ar = pipe->hif_ce_state; |
423 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
424 | struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl; | |
425 | int ret, num; | |
426 | ||
427 | lockdep_assert_held(&ar_pci->ce_lock); | |
428 | ||
429 | if (pipe->buf_sz == 0) | |
430 | return; | |
431 | ||
432 | if (!ce_pipe->dest_ring) | |
433 | return; | |
434 | ||
435 | num = __ath10k_ce_rx_num_free_bufs(ce_pipe); | |
436 | while (num--) { | |
437 | ret = __ath10k_pci_rx_post_buf(pipe); | |
438 | if (ret) { | |
7aa7a72a | 439 | ath10k_warn(ar, "failed to post pci rx buf: %d\n", ret); |
728f95ee MK |
440 | mod_timer(&ar_pci->rx_post_retry, jiffies + |
441 | ATH10K_PCI_RX_POST_RETRY_MS); | |
442 | break; | |
443 | } | |
444 | } | |
445 | } | |
446 | ||
447 | static void ath10k_pci_rx_post_pipe(struct ath10k_pci_pipe *pipe) | |
448 | { | |
449 | struct ath10k *ar = pipe->hif_ce_state; | |
450 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
451 | ||
452 | spin_lock_bh(&ar_pci->ce_lock); | |
453 | __ath10k_pci_rx_post_pipe(pipe); | |
454 | spin_unlock_bh(&ar_pci->ce_lock); | |
455 | } | |
456 | ||
457 | static void ath10k_pci_rx_post(struct ath10k *ar) | |
458 | { | |
459 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
460 | int i; | |
461 | ||
462 | spin_lock_bh(&ar_pci->ce_lock); | |
463 | for (i = 0; i < CE_COUNT; i++) | |
464 | __ath10k_pci_rx_post_pipe(&ar_pci->pipe_info[i]); | |
465 | spin_unlock_bh(&ar_pci->ce_lock); | |
466 | } | |
467 | ||
468 | static void ath10k_pci_rx_replenish_retry(unsigned long ptr) | |
469 | { | |
470 | struct ath10k *ar = (void *)ptr; | |
471 | ||
472 | ath10k_pci_rx_post(ar); | |
ab977bd0 MK |
473 | } |
474 | ||
5e3dd157 KV |
475 | /* |
476 | * Diagnostic read/write access is provided for startup/config/debug usage. | |
477 | * Caller must guarantee proper alignment, when applicable, and single user | |
478 | * at any moment. | |
479 | */ | |
480 | static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, void *data, | |
481 | int nbytes) | |
482 | { | |
483 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
484 | int ret = 0; | |
485 | u32 buf; | |
486 | unsigned int completed_nbytes, orig_nbytes, remaining_bytes; | |
487 | unsigned int id; | |
488 | unsigned int flags; | |
2aa39115 | 489 | struct ath10k_ce_pipe *ce_diag; |
5e3dd157 KV |
490 | /* Host buffer address in CE space */ |
491 | u32 ce_data; | |
492 | dma_addr_t ce_data_base = 0; | |
493 | void *data_buf = NULL; | |
494 | int i; | |
495 | ||
eef25405 KV |
496 | spin_lock_bh(&ar_pci->ce_lock); |
497 | ||
5e3dd157 KV |
498 | ce_diag = ar_pci->ce_diag; |
499 | ||
500 | /* | |
501 | * Allocate a temporary bounce buffer to hold caller's data | |
502 | * to be DMA'ed from Target. This guarantees | |
503 | * 1) 4-byte alignment | |
504 | * 2) Buffer in DMA-able space | |
505 | */ | |
506 | orig_nbytes = nbytes; | |
68c03249 MK |
507 | data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, |
508 | orig_nbytes, | |
509 | &ce_data_base, | |
510 | GFP_ATOMIC); | |
5e3dd157 KV |
511 | |
512 | if (!data_buf) { | |
513 | ret = -ENOMEM; | |
514 | goto done; | |
515 | } | |
516 | memset(data_buf, 0, orig_nbytes); | |
517 | ||
518 | remaining_bytes = orig_nbytes; | |
519 | ce_data = ce_data_base; | |
520 | while (remaining_bytes) { | |
521 | nbytes = min_t(unsigned int, remaining_bytes, | |
522 | DIAG_TRANSFER_LIMIT); | |
523 | ||
eef25405 | 524 | ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, ce_data); |
5e3dd157 KV |
525 | if (ret != 0) |
526 | goto done; | |
527 | ||
528 | /* Request CE to send from Target(!) address to Host buffer */ | |
529 | /* | |
530 | * The address supplied by the caller is in the | |
531 | * Target CPU virtual address space. | |
532 | * | |
533 | * In order to use this address with the diagnostic CE, | |
534 | * convert it from Target CPU virtual address space | |
535 | * to CE address space | |
536 | */ | |
5e3dd157 KV |
537 | address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, |
538 | address); | |
5e3dd157 | 539 | |
eef25405 KV |
540 | ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)address, nbytes, 0, |
541 | 0); | |
5e3dd157 KV |
542 | if (ret) |
543 | goto done; | |
544 | ||
545 | i = 0; | |
eef25405 KV |
546 | while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf, |
547 | &completed_nbytes, | |
548 | &id) != 0) { | |
5e3dd157 KV |
549 | mdelay(1); |
550 | if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { | |
551 | ret = -EBUSY; | |
552 | goto done; | |
553 | } | |
554 | } | |
555 | ||
556 | if (nbytes != completed_nbytes) { | |
557 | ret = -EIO; | |
558 | goto done; | |
559 | } | |
560 | ||
cfbc06a9 | 561 | if (buf != (u32)address) { |
5e3dd157 KV |
562 | ret = -EIO; |
563 | goto done; | |
564 | } | |
565 | ||
566 | i = 0; | |
eef25405 KV |
567 | while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf, |
568 | &completed_nbytes, | |
569 | &id, &flags) != 0) { | |
5e3dd157 KV |
570 | mdelay(1); |
571 | ||
572 | if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { | |
573 | ret = -EBUSY; | |
574 | goto done; | |
575 | } | |
576 | } | |
577 | ||
578 | if (nbytes != completed_nbytes) { | |
579 | ret = -EIO; | |
580 | goto done; | |
581 | } | |
582 | ||
583 | if (buf != ce_data) { | |
584 | ret = -EIO; | |
585 | goto done; | |
586 | } | |
587 | ||
588 | remaining_bytes -= nbytes; | |
589 | address += nbytes; | |
590 | ce_data += nbytes; | |
591 | } | |
592 | ||
593 | done: | |
0fdc14e4 MK |
594 | if (ret == 0) |
595 | memcpy(data, data_buf, orig_nbytes); | |
596 | else | |
7aa7a72a | 597 | ath10k_warn(ar, "failed to read diag value at 0x%x: %d\n", |
50f87a67 | 598 | address, ret); |
5e3dd157 KV |
599 | |
600 | if (data_buf) | |
68c03249 MK |
601 | dma_free_coherent(ar->dev, orig_nbytes, data_buf, |
602 | ce_data_base); | |
5e3dd157 | 603 | |
eef25405 KV |
604 | spin_unlock_bh(&ar_pci->ce_lock); |
605 | ||
5e3dd157 KV |
606 | return ret; |
607 | } | |
608 | ||
3d29a3e0 KV |
609 | static int ath10k_pci_diag_read32(struct ath10k *ar, u32 address, u32 *value) |
610 | { | |
0fdc14e4 MK |
611 | __le32 val = 0; |
612 | int ret; | |
613 | ||
614 | ret = ath10k_pci_diag_read_mem(ar, address, &val, sizeof(val)); | |
615 | *value = __le32_to_cpu(val); | |
616 | ||
617 | return ret; | |
3d29a3e0 KV |
618 | } |
619 | ||
620 | static int __ath10k_pci_diag_read_hi(struct ath10k *ar, void *dest, | |
621 | u32 src, u32 len) | |
622 | { | |
623 | u32 host_addr, addr; | |
624 | int ret; | |
625 | ||
626 | host_addr = host_interest_item_address(src); | |
627 | ||
628 | ret = ath10k_pci_diag_read32(ar, host_addr, &addr); | |
629 | if (ret != 0) { | |
7aa7a72a | 630 | ath10k_warn(ar, "failed to get memcpy hi address for firmware address %d: %d\n", |
3d29a3e0 KV |
631 | src, ret); |
632 | return ret; | |
633 | } | |
634 | ||
635 | ret = ath10k_pci_diag_read_mem(ar, addr, dest, len); | |
636 | if (ret != 0) { | |
7aa7a72a | 637 | ath10k_warn(ar, "failed to memcpy firmware memory from %d (%d B): %d\n", |
3d29a3e0 KV |
638 | addr, len, ret); |
639 | return ret; | |
640 | } | |
641 | ||
642 | return 0; | |
643 | } | |
644 | ||
645 | #define ath10k_pci_diag_read_hi(ar, dest, src, len) \ | |
8cc7f26c | 646 | __ath10k_pci_diag_read_hi(ar, dest, HI_ITEM(src), len) |
3d29a3e0 | 647 | |
5e3dd157 KV |
648 | static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, |
649 | const void *data, int nbytes) | |
650 | { | |
651 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
652 | int ret = 0; | |
653 | u32 buf; | |
654 | unsigned int completed_nbytes, orig_nbytes, remaining_bytes; | |
655 | unsigned int id; | |
656 | unsigned int flags; | |
2aa39115 | 657 | struct ath10k_ce_pipe *ce_diag; |
5e3dd157 KV |
658 | void *data_buf = NULL; |
659 | u32 ce_data; /* Host buffer address in CE space */ | |
660 | dma_addr_t ce_data_base = 0; | |
661 | int i; | |
662 | ||
eef25405 KV |
663 | spin_lock_bh(&ar_pci->ce_lock); |
664 | ||
5e3dd157 KV |
665 | ce_diag = ar_pci->ce_diag; |
666 | ||
667 | /* | |
668 | * Allocate a temporary bounce buffer to hold caller's data | |
669 | * to be DMA'ed to Target. This guarantees | |
670 | * 1) 4-byte alignment | |
671 | * 2) Buffer in DMA-able space | |
672 | */ | |
673 | orig_nbytes = nbytes; | |
68c03249 MK |
674 | data_buf = (unsigned char *)dma_alloc_coherent(ar->dev, |
675 | orig_nbytes, | |
676 | &ce_data_base, | |
677 | GFP_ATOMIC); | |
5e3dd157 KV |
678 | if (!data_buf) { |
679 | ret = -ENOMEM; | |
680 | goto done; | |
681 | } | |
682 | ||
683 | /* Copy caller's data to allocated DMA buf */ | |
0fdc14e4 | 684 | memcpy(data_buf, data, orig_nbytes); |
5e3dd157 KV |
685 | |
686 | /* | |
687 | * The address supplied by the caller is in the | |
688 | * Target CPU virtual address space. | |
689 | * | |
690 | * In order to use this address with the diagnostic CE, | |
691 | * convert it from | |
692 | * Target CPU virtual address space | |
693 | * to | |
694 | * CE address space | |
695 | */ | |
5e3dd157 | 696 | address = TARG_CPU_SPACE_TO_CE_SPACE(ar, ar_pci->mem, address); |
5e3dd157 KV |
697 | |
698 | remaining_bytes = orig_nbytes; | |
699 | ce_data = ce_data_base; | |
700 | while (remaining_bytes) { | |
701 | /* FIXME: check cast */ | |
702 | nbytes = min_t(int, remaining_bytes, DIAG_TRANSFER_LIMIT); | |
703 | ||
704 | /* Set up to receive directly into Target(!) address */ | |
eef25405 | 705 | ret = __ath10k_ce_rx_post_buf(ce_diag, NULL, address); |
5e3dd157 KV |
706 | if (ret != 0) |
707 | goto done; | |
708 | ||
709 | /* | |
710 | * Request CE to send caller-supplied data that | |
711 | * was copied to bounce buffer to Target(!) address. | |
712 | */ | |
eef25405 KV |
713 | ret = ath10k_ce_send_nolock(ce_diag, NULL, (u32)ce_data, |
714 | nbytes, 0, 0); | |
5e3dd157 KV |
715 | if (ret != 0) |
716 | goto done; | |
717 | ||
718 | i = 0; | |
eef25405 KV |
719 | while (ath10k_ce_completed_send_next_nolock(ce_diag, NULL, &buf, |
720 | &completed_nbytes, | |
721 | &id) != 0) { | |
5e3dd157 KV |
722 | mdelay(1); |
723 | ||
724 | if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { | |
725 | ret = -EBUSY; | |
726 | goto done; | |
727 | } | |
728 | } | |
729 | ||
730 | if (nbytes != completed_nbytes) { | |
731 | ret = -EIO; | |
732 | goto done; | |
733 | } | |
734 | ||
735 | if (buf != ce_data) { | |
736 | ret = -EIO; | |
737 | goto done; | |
738 | } | |
739 | ||
740 | i = 0; | |
eef25405 KV |
741 | while (ath10k_ce_completed_recv_next_nolock(ce_diag, NULL, &buf, |
742 | &completed_nbytes, | |
743 | &id, &flags) != 0) { | |
5e3dd157 KV |
744 | mdelay(1); |
745 | ||
746 | if (i++ > DIAG_ACCESS_CE_TIMEOUT_MS) { | |
747 | ret = -EBUSY; | |
748 | goto done; | |
749 | } | |
750 | } | |
751 | ||
752 | if (nbytes != completed_nbytes) { | |
753 | ret = -EIO; | |
754 | goto done; | |
755 | } | |
756 | ||
757 | if (buf != address) { | |
758 | ret = -EIO; | |
759 | goto done; | |
760 | } | |
761 | ||
762 | remaining_bytes -= nbytes; | |
763 | address += nbytes; | |
764 | ce_data += nbytes; | |
765 | } | |
766 | ||
767 | done: | |
768 | if (data_buf) { | |
68c03249 MK |
769 | dma_free_coherent(ar->dev, orig_nbytes, data_buf, |
770 | ce_data_base); | |
5e3dd157 KV |
771 | } |
772 | ||
773 | if (ret != 0) | |
7aa7a72a | 774 | ath10k_warn(ar, "failed to write diag value at 0x%x: %d\n", |
50f87a67 | 775 | address, ret); |
5e3dd157 | 776 | |
eef25405 KV |
777 | spin_unlock_bh(&ar_pci->ce_lock); |
778 | ||
5e3dd157 KV |
779 | return ret; |
780 | } | |
781 | ||
0fdc14e4 MK |
782 | static int ath10k_pci_diag_write32(struct ath10k *ar, u32 address, u32 value) |
783 | { | |
784 | __le32 val = __cpu_to_le32(value); | |
785 | ||
786 | return ath10k_pci_diag_write_mem(ar, address, &val, sizeof(val)); | |
787 | } | |
788 | ||
c0c378f9 | 789 | static bool ath10k_pci_is_awake(struct ath10k *ar) |
5e3dd157 | 790 | { |
c0c378f9 MK |
791 | u32 val = ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS); |
792 | ||
793 | return RTC_STATE_V_GET(val) == RTC_STATE_V_ON; | |
5e3dd157 KV |
794 | } |
795 | ||
c0c378f9 | 796 | static int ath10k_pci_wake_wait(struct ath10k *ar) |
5e3dd157 | 797 | { |
5e3dd157 KV |
798 | int tot_delay = 0; |
799 | int curr_delay = 5; | |
800 | ||
c0c378f9 MK |
801 | while (tot_delay < PCIE_WAKE_TIMEOUT) { |
802 | if (ath10k_pci_is_awake(ar)) | |
3aebe54b | 803 | return 0; |
5e3dd157 KV |
804 | |
805 | udelay(curr_delay); | |
806 | tot_delay += curr_delay; | |
807 | ||
808 | if (curr_delay < 50) | |
809 | curr_delay += 5; | |
810 | } | |
c0c378f9 MK |
811 | |
812 | return -ETIMEDOUT; | |
5e3dd157 KV |
813 | } |
814 | ||
c0c378f9 | 815 | static int ath10k_pci_wake(struct ath10k *ar) |
5e3dd157 | 816 | { |
c0c378f9 MK |
817 | ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS, |
818 | PCIE_SOC_WAKE_V_MASK); | |
819 | return ath10k_pci_wake_wait(ar); | |
820 | } | |
5e3dd157 | 821 | |
c0c378f9 MK |
822 | static void ath10k_pci_sleep(struct ath10k *ar) |
823 | { | |
824 | ath10k_pci_reg_write32(ar, PCIE_SOC_WAKE_ADDRESS, | |
825 | PCIE_SOC_WAKE_RESET); | |
5e3dd157 KV |
826 | } |
827 | ||
5e3dd157 | 828 | /* Called by lower (CE) layer when a send to Target completes. */ |
5440ce25 | 829 | static void ath10k_pci_ce_send_done(struct ath10k_ce_pipe *ce_state) |
5e3dd157 KV |
830 | { |
831 | struct ath10k *ar = ce_state->ar; | |
832 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2f5280da | 833 | struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current; |
1cb86d47 MK |
834 | struct sk_buff_head list; |
835 | struct sk_buff *skb; | |
5440ce25 MK |
836 | u32 ce_data; |
837 | unsigned int nbytes; | |
838 | unsigned int transfer_id; | |
5e3dd157 | 839 | |
1cb86d47 MK |
840 | __skb_queue_head_init(&list); |
841 | while (ath10k_ce_completed_send_next(ce_state, (void **)&skb, &ce_data, | |
842 | &nbytes, &transfer_id) == 0) { | |
a16942e6 | 843 | /* no need to call tx completion for NULL pointers */ |
1cb86d47 | 844 | if (skb == NULL) |
726346fc MK |
845 | continue; |
846 | ||
1cb86d47 | 847 | __skb_queue_tail(&list, skb); |
5440ce25 | 848 | } |
1cb86d47 MK |
849 | |
850 | while ((skb = __skb_dequeue(&list))) | |
851 | cb->tx_completion(ar, skb); | |
5e3dd157 KV |
852 | } |
853 | ||
854 | /* Called by lower (CE) layer when data is received from the Target. */ | |
5440ce25 | 855 | static void ath10k_pci_ce_recv_data(struct ath10k_ce_pipe *ce_state) |
5e3dd157 KV |
856 | { |
857 | struct ath10k *ar = ce_state->ar; | |
858 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
87263e5b | 859 | struct ath10k_pci_pipe *pipe_info = &ar_pci->pipe_info[ce_state->id]; |
2f5280da | 860 | struct ath10k_hif_cb *cb = &ar_pci->msg_callbacks_current; |
5e3dd157 | 861 | struct sk_buff *skb; |
1cb86d47 | 862 | struct sk_buff_head list; |
5440ce25 MK |
863 | void *transfer_context; |
864 | u32 ce_data; | |
2f5280da | 865 | unsigned int nbytes, max_nbytes; |
5440ce25 MK |
866 | unsigned int transfer_id; |
867 | unsigned int flags; | |
5e3dd157 | 868 | |
1cb86d47 | 869 | __skb_queue_head_init(&list); |
5440ce25 MK |
870 | while (ath10k_ce_completed_recv_next(ce_state, &transfer_context, |
871 | &ce_data, &nbytes, &transfer_id, | |
872 | &flags) == 0) { | |
5e3dd157 | 873 | skb = transfer_context; |
2f5280da | 874 | max_nbytes = skb->len + skb_tailroom(skb); |
5e3dd157 | 875 | dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, |
2f5280da MK |
876 | max_nbytes, DMA_FROM_DEVICE); |
877 | ||
878 | if (unlikely(max_nbytes < nbytes)) { | |
7aa7a72a | 879 | ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)", |
2f5280da MK |
880 | nbytes, max_nbytes); |
881 | dev_kfree_skb_any(skb); | |
882 | continue; | |
883 | } | |
5e3dd157 | 884 | |
2f5280da | 885 | skb_put(skb, nbytes); |
1cb86d47 MK |
886 | __skb_queue_tail(&list, skb); |
887 | } | |
a360e54c | 888 | |
1cb86d47 | 889 | while ((skb = __skb_dequeue(&list))) { |
a360e54c MK |
890 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci rx ce pipe %d len %d\n", |
891 | ce_state->id, skb->len); | |
892 | ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci rx: ", | |
893 | skb->data, skb->len); | |
894 | ||
5f07ea4c | 895 | cb->rx_completion(ar, skb); |
2f5280da | 896 | } |
c29a380e | 897 | |
728f95ee | 898 | ath10k_pci_rx_post_pipe(pipe_info); |
5e3dd157 KV |
899 | } |
900 | ||
726346fc MK |
901 | static int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id, |
902 | struct ath10k_hif_sg_item *items, int n_items) | |
5e3dd157 | 903 | { |
5e3dd157 | 904 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
726346fc MK |
905 | struct ath10k_pci_pipe *pci_pipe = &ar_pci->pipe_info[pipe_id]; |
906 | struct ath10k_ce_pipe *ce_pipe = pci_pipe->ce_hdl; | |
907 | struct ath10k_ce_ring *src_ring = ce_pipe->src_ring; | |
7147a131 MK |
908 | unsigned int nentries_mask; |
909 | unsigned int sw_index; | |
910 | unsigned int write_index; | |
08b8aa09 | 911 | int err, i = 0; |
5e3dd157 | 912 | |
726346fc | 913 | spin_lock_bh(&ar_pci->ce_lock); |
5e3dd157 | 914 | |
7147a131 MK |
915 | nentries_mask = src_ring->nentries_mask; |
916 | sw_index = src_ring->sw_index; | |
917 | write_index = src_ring->write_index; | |
918 | ||
726346fc MK |
919 | if (unlikely(CE_RING_DELTA(nentries_mask, |
920 | write_index, sw_index - 1) < n_items)) { | |
921 | err = -ENOBUFS; | |
08b8aa09 | 922 | goto err; |
726346fc | 923 | } |
5e3dd157 | 924 | |
726346fc | 925 | for (i = 0; i < n_items - 1; i++) { |
7aa7a72a | 926 | ath10k_dbg(ar, ATH10K_DBG_PCI, |
726346fc MK |
927 | "pci tx item %d paddr 0x%08x len %d n_items %d\n", |
928 | i, items[i].paddr, items[i].len, n_items); | |
7aa7a72a | 929 | ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", |
726346fc | 930 | items[i].vaddr, items[i].len); |
5e3dd157 | 931 | |
726346fc MK |
932 | err = ath10k_ce_send_nolock(ce_pipe, |
933 | items[i].transfer_context, | |
934 | items[i].paddr, | |
935 | items[i].len, | |
936 | items[i].transfer_id, | |
937 | CE_SEND_FLAG_GATHER); | |
938 | if (err) | |
08b8aa09 | 939 | goto err; |
726346fc MK |
940 | } |
941 | ||
942 | /* `i` is equal to `n_items -1` after for() */ | |
943 | ||
7aa7a72a | 944 | ath10k_dbg(ar, ATH10K_DBG_PCI, |
726346fc MK |
945 | "pci tx item %d paddr 0x%08x len %d n_items %d\n", |
946 | i, items[i].paddr, items[i].len, n_items); | |
7aa7a72a | 947 | ath10k_dbg_dump(ar, ATH10K_DBG_PCI_DUMP, NULL, "pci tx data: ", |
726346fc MK |
948 | items[i].vaddr, items[i].len); |
949 | ||
950 | err = ath10k_ce_send_nolock(ce_pipe, | |
951 | items[i].transfer_context, | |
952 | items[i].paddr, | |
953 | items[i].len, | |
954 | items[i].transfer_id, | |
955 | 0); | |
956 | if (err) | |
08b8aa09 MK |
957 | goto err; |
958 | ||
959 | spin_unlock_bh(&ar_pci->ce_lock); | |
960 | return 0; | |
961 | ||
962 | err: | |
963 | for (; i > 0; i--) | |
964 | __ath10k_ce_send_revert(ce_pipe); | |
726346fc | 965 | |
726346fc MK |
966 | spin_unlock_bh(&ar_pci->ce_lock); |
967 | return err; | |
5e3dd157 KV |
968 | } |
969 | ||
eef25405 KV |
970 | static int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf, |
971 | size_t buf_len) | |
972 | { | |
973 | return ath10k_pci_diag_read_mem(ar, address, buf, buf_len); | |
974 | } | |
975 | ||
5e3dd157 KV |
976 | static u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe) |
977 | { | |
978 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
50f87a67 | 979 | |
7aa7a72a | 980 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get free queue number\n"); |
50f87a67 | 981 | |
3efcb3b4 | 982 | return ath10k_ce_num_free_src_entries(ar_pci->pipe_info[pipe].ce_hdl); |
5e3dd157 KV |
983 | } |
984 | ||
384914b2 BG |
985 | static void ath10k_pci_dump_registers(struct ath10k *ar, |
986 | struct ath10k_fw_crash_data *crash_data) | |
5e3dd157 | 987 | { |
0fdc14e4 MK |
988 | __le32 reg_dump_values[REG_DUMP_COUNT_QCA988X] = {}; |
989 | int i, ret; | |
5e3dd157 | 990 | |
384914b2 | 991 | lockdep_assert_held(&ar->data_lock); |
5e3dd157 | 992 | |
3d29a3e0 KV |
993 | ret = ath10k_pci_diag_read_hi(ar, ®_dump_values[0], |
994 | hi_failure_state, | |
0fdc14e4 | 995 | REG_DUMP_COUNT_QCA988X * sizeof(__le32)); |
1d2b48d6 | 996 | if (ret) { |
7aa7a72a | 997 | ath10k_err(ar, "failed to read firmware dump area: %d\n", ret); |
5e3dd157 KV |
998 | return; |
999 | } | |
1000 | ||
1001 | BUILD_BUG_ON(REG_DUMP_COUNT_QCA988X % 4); | |
1002 | ||
7aa7a72a | 1003 | ath10k_err(ar, "firmware register dump:\n"); |
5e3dd157 | 1004 | for (i = 0; i < REG_DUMP_COUNT_QCA988X; i += 4) |
7aa7a72a | 1005 | ath10k_err(ar, "[%02d]: 0x%08X 0x%08X 0x%08X 0x%08X\n", |
5e3dd157 | 1006 | i, |
0fdc14e4 MK |
1007 | __le32_to_cpu(reg_dump_values[i]), |
1008 | __le32_to_cpu(reg_dump_values[i + 1]), | |
1009 | __le32_to_cpu(reg_dump_values[i + 2]), | |
1010 | __le32_to_cpu(reg_dump_values[i + 3])); | |
affd3217 | 1011 | |
1bbb119d MK |
1012 | if (!crash_data) |
1013 | return; | |
1014 | ||
384914b2 | 1015 | for (i = 0; i < REG_DUMP_COUNT_QCA988X; i++) |
0fdc14e4 | 1016 | crash_data->registers[i] = reg_dump_values[i]; |
384914b2 BG |
1017 | } |
1018 | ||
0e9848c0 | 1019 | static void ath10k_pci_fw_crashed_dump(struct ath10k *ar) |
384914b2 BG |
1020 | { |
1021 | struct ath10k_fw_crash_data *crash_data; | |
1022 | char uuid[50]; | |
1023 | ||
1024 | spin_lock_bh(&ar->data_lock); | |
1025 | ||
f51dbe73 BG |
1026 | ar->stats.fw_crash_counter++; |
1027 | ||
384914b2 BG |
1028 | crash_data = ath10k_debug_get_new_fw_crash_data(ar); |
1029 | ||
1030 | if (crash_data) | |
1031 | scnprintf(uuid, sizeof(uuid), "%pUl", &crash_data->uuid); | |
1032 | else | |
1033 | scnprintf(uuid, sizeof(uuid), "n/a"); | |
1034 | ||
7aa7a72a | 1035 | ath10k_err(ar, "firmware crashed! (uuid %s)\n", uuid); |
8a0c797e | 1036 | ath10k_print_driver_info(ar); |
384914b2 BG |
1037 | ath10k_pci_dump_registers(ar, crash_data); |
1038 | ||
384914b2 | 1039 | spin_unlock_bh(&ar->data_lock); |
affd3217 | 1040 | |
5e90de86 | 1041 | queue_work(ar->workqueue, &ar->restart_work); |
5e3dd157 KV |
1042 | } |
1043 | ||
1044 | static void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe, | |
1045 | int force) | |
1046 | { | |
7aa7a72a | 1047 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif send complete check\n"); |
50f87a67 | 1048 | |
5e3dd157 KV |
1049 | if (!force) { |
1050 | int resources; | |
1051 | /* | |
1052 | * Decide whether to actually poll for completions, or just | |
1053 | * wait for a later chance. | |
1054 | * If there seem to be plenty of resources left, then just wait | |
1055 | * since checking involves reading a CE register, which is a | |
1056 | * relatively expensive operation. | |
1057 | */ | |
1058 | resources = ath10k_pci_hif_get_free_queue_number(ar, pipe); | |
1059 | ||
1060 | /* | |
1061 | * If at least 50% of the total resources are still available, | |
1062 | * don't bother checking again yet. | |
1063 | */ | |
1064 | if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1)) | |
1065 | return; | |
1066 | } | |
1067 | ath10k_ce_per_engine_service(ar, pipe); | |
1068 | } | |
1069 | ||
e799bbff MK |
1070 | static void ath10k_pci_hif_set_callbacks(struct ath10k *ar, |
1071 | struct ath10k_hif_cb *callbacks) | |
5e3dd157 KV |
1072 | { |
1073 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
1074 | ||
7aa7a72a | 1075 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif set callbacks\n"); |
5e3dd157 KV |
1076 | |
1077 | memcpy(&ar_pci->msg_callbacks_current, callbacks, | |
1078 | sizeof(ar_pci->msg_callbacks_current)); | |
1079 | } | |
1080 | ||
96a9d0dc | 1081 | static void ath10k_pci_kill_tasklet(struct ath10k *ar) |
5e3dd157 KV |
1082 | { |
1083 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
5e3dd157 | 1084 | int i; |
5e3dd157 | 1085 | |
5e3dd157 | 1086 | tasklet_kill(&ar_pci->intr_tq); |
103d4f5e | 1087 | tasklet_kill(&ar_pci->msi_fw_err); |
5e3dd157 KV |
1088 | |
1089 | for (i = 0; i < CE_COUNT; i++) | |
1090 | tasklet_kill(&ar_pci->pipe_info[i].intr); | |
728f95ee MK |
1091 | |
1092 | del_timer_sync(&ar_pci->rx_post_retry); | |
96a9d0dc MK |
1093 | } |
1094 | ||
5e3dd157 KV |
1095 | static int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, |
1096 | u16 service_id, u8 *ul_pipe, | |
1097 | u8 *dl_pipe, int *ul_is_polled, | |
1098 | int *dl_is_polled) | |
1099 | { | |
7c6aa25d MK |
1100 | const struct service_to_pipe *entry; |
1101 | bool ul_set = false, dl_set = false; | |
1102 | int i; | |
5e3dd157 | 1103 | |
7aa7a72a | 1104 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif map service\n"); |
50f87a67 | 1105 | |
5e3dd157 KV |
1106 | /* polling for received messages not supported */ |
1107 | *dl_is_polled = 0; | |
1108 | ||
7c6aa25d MK |
1109 | for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) { |
1110 | entry = &target_service_to_ce_map_wlan[i]; | |
5e3dd157 | 1111 | |
0fdc14e4 | 1112 | if (__le32_to_cpu(entry->service_id) != service_id) |
7c6aa25d | 1113 | continue; |
5e3dd157 | 1114 | |
0fdc14e4 | 1115 | switch (__le32_to_cpu(entry->pipedir)) { |
7c6aa25d MK |
1116 | case PIPEDIR_NONE: |
1117 | break; | |
1118 | case PIPEDIR_IN: | |
1119 | WARN_ON(dl_set); | |
0fdc14e4 | 1120 | *dl_pipe = __le32_to_cpu(entry->pipenum); |
7c6aa25d MK |
1121 | dl_set = true; |
1122 | break; | |
1123 | case PIPEDIR_OUT: | |
1124 | WARN_ON(ul_set); | |
0fdc14e4 | 1125 | *ul_pipe = __le32_to_cpu(entry->pipenum); |
7c6aa25d MK |
1126 | ul_set = true; |
1127 | break; | |
1128 | case PIPEDIR_INOUT: | |
1129 | WARN_ON(dl_set); | |
1130 | WARN_ON(ul_set); | |
0fdc14e4 MK |
1131 | *dl_pipe = __le32_to_cpu(entry->pipenum); |
1132 | *ul_pipe = __le32_to_cpu(entry->pipenum); | |
7c6aa25d MK |
1133 | dl_set = true; |
1134 | ul_set = true; | |
1135 | break; | |
1136 | } | |
5e3dd157 | 1137 | } |
5e3dd157 | 1138 | |
7c6aa25d MK |
1139 | if (WARN_ON(!ul_set || !dl_set)) |
1140 | return -ENOENT; | |
5e3dd157 | 1141 | |
5e3dd157 KV |
1142 | *ul_is_polled = |
1143 | (host_ce_config_wlan[*ul_pipe].flags & CE_ATTR_DIS_INTR) != 0; | |
1144 | ||
7c6aa25d | 1145 | return 0; |
5e3dd157 KV |
1146 | } |
1147 | ||
1148 | static void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, | |
5b07e07f | 1149 | u8 *ul_pipe, u8 *dl_pipe) |
5e3dd157 KV |
1150 | { |
1151 | int ul_is_polled, dl_is_polled; | |
1152 | ||
7aa7a72a | 1153 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci hif get default pipe\n"); |
50f87a67 | 1154 | |
5e3dd157 KV |
1155 | (void)ath10k_pci_hif_map_service_to_pipe(ar, |
1156 | ATH10K_HTC_SVC_ID_RSVD_CTRL, | |
1157 | ul_pipe, | |
1158 | dl_pipe, | |
1159 | &ul_is_polled, | |
1160 | &dl_is_polled); | |
1161 | } | |
1162 | ||
7c0f0e3c | 1163 | static void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar) |
5e3dd157 | 1164 | { |
7c0f0e3c MK |
1165 | u32 val; |
1166 | ||
1167 | val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS); | |
1168 | val &= ~CORE_CTRL_PCIE_REG_31_MASK; | |
1169 | ||
1170 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val); | |
1171 | } | |
1172 | ||
1173 | static void ath10k_pci_irq_msi_fw_unmask(struct ath10k *ar) | |
1174 | { | |
1175 | u32 val; | |
1176 | ||
1177 | val = ath10k_pci_read32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS); | |
1178 | val |= CORE_CTRL_PCIE_REG_31_MASK; | |
1179 | ||
1180 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + CORE_CTRL_ADDRESS, val); | |
1181 | } | |
5e3dd157 | 1182 | |
7c0f0e3c MK |
1183 | static void ath10k_pci_irq_disable(struct ath10k *ar) |
1184 | { | |
ec5ba4d3 | 1185 | ath10k_ce_disable_interrupts(ar); |
e75db4e3 | 1186 | ath10k_pci_disable_and_clear_legacy_irq(ar); |
7c0f0e3c MK |
1187 | ath10k_pci_irq_msi_fw_mask(ar); |
1188 | } | |
1189 | ||
1190 | static void ath10k_pci_irq_sync(struct ath10k *ar) | |
1191 | { | |
1192 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
1193 | int i; | |
5e3dd157 | 1194 | |
ec5ba4d3 MK |
1195 | for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++) |
1196 | synchronize_irq(ar_pci->pdev->irq + i); | |
5e3dd157 KV |
1197 | } |
1198 | ||
ec5ba4d3 | 1199 | static void ath10k_pci_irq_enable(struct ath10k *ar) |
5e3dd157 | 1200 | { |
ec5ba4d3 | 1201 | ath10k_ce_enable_interrupts(ar); |
e75db4e3 | 1202 | ath10k_pci_enable_legacy_irq(ar); |
7c0f0e3c | 1203 | ath10k_pci_irq_msi_fw_unmask(ar); |
5e3dd157 KV |
1204 | } |
1205 | ||
1206 | static int ath10k_pci_hif_start(struct ath10k *ar) | |
1207 | { | |
7aa7a72a | 1208 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n"); |
5e3dd157 | 1209 | |
ec5ba4d3 | 1210 | ath10k_pci_irq_enable(ar); |
728f95ee | 1211 | ath10k_pci_rx_post(ar); |
50f87a67 | 1212 | |
5e3dd157 KV |
1213 | return 0; |
1214 | } | |
1215 | ||
099ac7ce | 1216 | static void ath10k_pci_rx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) |
5e3dd157 KV |
1217 | { |
1218 | struct ath10k *ar; | |
099ac7ce MK |
1219 | struct ath10k_ce_pipe *ce_pipe; |
1220 | struct ath10k_ce_ring *ce_ring; | |
1221 | struct sk_buff *skb; | |
1222 | int i; | |
5e3dd157 | 1223 | |
099ac7ce MK |
1224 | ar = pci_pipe->hif_ce_state; |
1225 | ce_pipe = pci_pipe->ce_hdl; | |
1226 | ce_ring = ce_pipe->dest_ring; | |
5e3dd157 | 1227 | |
099ac7ce | 1228 | if (!ce_ring) |
5e3dd157 KV |
1229 | return; |
1230 | ||
099ac7ce MK |
1231 | if (!pci_pipe->buf_sz) |
1232 | return; | |
5e3dd157 | 1233 | |
099ac7ce MK |
1234 | for (i = 0; i < ce_ring->nentries; i++) { |
1235 | skb = ce_ring->per_transfer_context[i]; | |
1236 | if (!skb) | |
1237 | continue; | |
1238 | ||
1239 | ce_ring->per_transfer_context[i] = NULL; | |
1240 | ||
1241 | dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr, | |
1242 | skb->len + skb_tailroom(skb), | |
5e3dd157 | 1243 | DMA_FROM_DEVICE); |
099ac7ce | 1244 | dev_kfree_skb_any(skb); |
5e3dd157 KV |
1245 | } |
1246 | } | |
1247 | ||
099ac7ce | 1248 | static void ath10k_pci_tx_pipe_cleanup(struct ath10k_pci_pipe *pci_pipe) |
5e3dd157 KV |
1249 | { |
1250 | struct ath10k *ar; | |
1251 | struct ath10k_pci *ar_pci; | |
099ac7ce MK |
1252 | struct ath10k_ce_pipe *ce_pipe; |
1253 | struct ath10k_ce_ring *ce_ring; | |
1254 | struct ce_desc *ce_desc; | |
1255 | struct sk_buff *skb; | |
5e3dd157 | 1256 | unsigned int id; |
099ac7ce | 1257 | int i; |
5e3dd157 | 1258 | |
099ac7ce MK |
1259 | ar = pci_pipe->hif_ce_state; |
1260 | ar_pci = ath10k_pci_priv(ar); | |
1261 | ce_pipe = pci_pipe->ce_hdl; | |
1262 | ce_ring = ce_pipe->src_ring; | |
5e3dd157 | 1263 | |
099ac7ce | 1264 | if (!ce_ring) |
5e3dd157 KV |
1265 | return; |
1266 | ||
099ac7ce MK |
1267 | if (!pci_pipe->buf_sz) |
1268 | return; | |
5e3dd157 | 1269 | |
099ac7ce MK |
1270 | ce_desc = ce_ring->shadow_base; |
1271 | if (WARN_ON(!ce_desc)) | |
1272 | return; | |
1273 | ||
1274 | for (i = 0; i < ce_ring->nentries; i++) { | |
1275 | skb = ce_ring->per_transfer_context[i]; | |
1276 | if (!skb) | |
2415fc16 | 1277 | continue; |
2415fc16 | 1278 | |
099ac7ce MK |
1279 | ce_ring->per_transfer_context[i] = NULL; |
1280 | id = MS(__le16_to_cpu(ce_desc[i].flags), | |
1281 | CE_DESC_FLAGS_META_DATA); | |
1282 | ||
d84a512d | 1283 | ar_pci->msg_callbacks_current.tx_completion(ar, skb); |
5e3dd157 KV |
1284 | } |
1285 | } | |
1286 | ||
1287 | /* | |
1288 | * Cleanup residual buffers for device shutdown: | |
1289 | * buffers that were enqueued for receive | |
1290 | * buffers that were to be sent | |
1291 | * Note: Buffers that had completed but which were | |
1292 | * not yet processed are on a completion queue. They | |
1293 | * are handled when the completion thread shuts down. | |
1294 | */ | |
1295 | static void ath10k_pci_buffer_cleanup(struct ath10k *ar) | |
1296 | { | |
1297 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
1298 | int pipe_num; | |
1299 | ||
fad6ed78 | 1300 | for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) { |
87263e5b | 1301 | struct ath10k_pci_pipe *pipe_info; |
5e3dd157 KV |
1302 | |
1303 | pipe_info = &ar_pci->pipe_info[pipe_num]; | |
1304 | ath10k_pci_rx_pipe_cleanup(pipe_info); | |
1305 | ath10k_pci_tx_pipe_cleanup(pipe_info); | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | static void ath10k_pci_ce_deinit(struct ath10k *ar) | |
1310 | { | |
25d0dbcb | 1311 | int i; |
5e3dd157 | 1312 | |
25d0dbcb MK |
1313 | for (i = 0; i < CE_COUNT; i++) |
1314 | ath10k_ce_deinit_pipe(ar, i); | |
5e3dd157 KV |
1315 | } |
1316 | ||
728f95ee | 1317 | static void ath10k_pci_flush(struct ath10k *ar) |
5e3dd157 | 1318 | { |
5d1aa946 | 1319 | ath10k_pci_kill_tasklet(ar); |
728f95ee MK |
1320 | ath10k_pci_buffer_cleanup(ar); |
1321 | } | |
5e3dd157 | 1322 | |
5e3dd157 KV |
1323 | static void ath10k_pci_hif_stop(struct ath10k *ar) |
1324 | { | |
7aa7a72a | 1325 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n"); |
5e3dd157 | 1326 | |
10d23db4 MK |
1327 | /* Most likely the device has HTT Rx ring configured. The only way to |
1328 | * prevent the device from accessing (and possible corrupting) host | |
1329 | * memory is to reset the chip now. | |
e75db4e3 MK |
1330 | * |
1331 | * There's also no known way of masking MSI interrupts on the device. | |
1332 | * For ranged MSI the CE-related interrupts can be masked. However | |
1333 | * regardless how many MSI interrupts are assigned the first one | |
1334 | * is always used for firmware indications (crashes) and cannot be | |
1335 | * masked. To prevent the device from asserting the interrupt reset it | |
1336 | * before proceeding with cleanup. | |
10d23db4 | 1337 | */ |
fc36e3ff | 1338 | ath10k_pci_warm_reset(ar); |
e75db4e3 MK |
1339 | |
1340 | ath10k_pci_irq_disable(ar); | |
7c0f0e3c | 1341 | ath10k_pci_irq_sync(ar); |
e75db4e3 | 1342 | ath10k_pci_flush(ar); |
5e3dd157 KV |
1343 | } |
1344 | ||
1345 | static int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, | |
1346 | void *req, u32 req_len, | |
1347 | void *resp, u32 *resp_len) | |
1348 | { | |
1349 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2aa39115 MK |
1350 | struct ath10k_pci_pipe *pci_tx = &ar_pci->pipe_info[BMI_CE_NUM_TO_TARG]; |
1351 | struct ath10k_pci_pipe *pci_rx = &ar_pci->pipe_info[BMI_CE_NUM_TO_HOST]; | |
1352 | struct ath10k_ce_pipe *ce_tx = pci_tx->ce_hdl; | |
1353 | struct ath10k_ce_pipe *ce_rx = pci_rx->ce_hdl; | |
5e3dd157 KV |
1354 | dma_addr_t req_paddr = 0; |
1355 | dma_addr_t resp_paddr = 0; | |
1356 | struct bmi_xfer xfer = {}; | |
1357 | void *treq, *tresp = NULL; | |
1358 | int ret = 0; | |
1359 | ||
85622cde MK |
1360 | might_sleep(); |
1361 | ||
5e3dd157 KV |
1362 | if (resp && !resp_len) |
1363 | return -EINVAL; | |
1364 | ||
1365 | if (resp && resp_len && *resp_len == 0) | |
1366 | return -EINVAL; | |
1367 | ||
1368 | treq = kmemdup(req, req_len, GFP_KERNEL); | |
1369 | if (!treq) | |
1370 | return -ENOMEM; | |
1371 | ||
1372 | req_paddr = dma_map_single(ar->dev, treq, req_len, DMA_TO_DEVICE); | |
1373 | ret = dma_mapping_error(ar->dev, req_paddr); | |
1374 | if (ret) | |
1375 | goto err_dma; | |
1376 | ||
1377 | if (resp && resp_len) { | |
1378 | tresp = kzalloc(*resp_len, GFP_KERNEL); | |
1379 | if (!tresp) { | |
1380 | ret = -ENOMEM; | |
1381 | goto err_req; | |
1382 | } | |
1383 | ||
1384 | resp_paddr = dma_map_single(ar->dev, tresp, *resp_len, | |
1385 | DMA_FROM_DEVICE); | |
1386 | ret = dma_mapping_error(ar->dev, resp_paddr); | |
1387 | if (ret) | |
1388 | goto err_req; | |
1389 | ||
1390 | xfer.wait_for_resp = true; | |
1391 | xfer.resp_len = 0; | |
1392 | ||
728f95ee | 1393 | ath10k_ce_rx_post_buf(ce_rx, &xfer, resp_paddr); |
5e3dd157 KV |
1394 | } |
1395 | ||
5e3dd157 KV |
1396 | ret = ath10k_ce_send(ce_tx, &xfer, req_paddr, req_len, -1, 0); |
1397 | if (ret) | |
1398 | goto err_resp; | |
1399 | ||
85622cde MK |
1400 | ret = ath10k_pci_bmi_wait(ce_tx, ce_rx, &xfer); |
1401 | if (ret) { | |
5e3dd157 KV |
1402 | u32 unused_buffer; |
1403 | unsigned int unused_nbytes; | |
1404 | unsigned int unused_id; | |
1405 | ||
5e3dd157 KV |
1406 | ath10k_ce_cancel_send_next(ce_tx, NULL, &unused_buffer, |
1407 | &unused_nbytes, &unused_id); | |
1408 | } else { | |
1409 | /* non-zero means we did not time out */ | |
1410 | ret = 0; | |
1411 | } | |
1412 | ||
1413 | err_resp: | |
1414 | if (resp) { | |
1415 | u32 unused_buffer; | |
1416 | ||
1417 | ath10k_ce_revoke_recv_next(ce_rx, NULL, &unused_buffer); | |
1418 | dma_unmap_single(ar->dev, resp_paddr, | |
1419 | *resp_len, DMA_FROM_DEVICE); | |
1420 | } | |
1421 | err_req: | |
1422 | dma_unmap_single(ar->dev, req_paddr, req_len, DMA_TO_DEVICE); | |
1423 | ||
1424 | if (ret == 0 && resp_len) { | |
1425 | *resp_len = min(*resp_len, xfer.resp_len); | |
1426 | memcpy(resp, tresp, xfer.resp_len); | |
1427 | } | |
1428 | err_dma: | |
1429 | kfree(treq); | |
1430 | kfree(tresp); | |
1431 | ||
1432 | return ret; | |
1433 | } | |
1434 | ||
5440ce25 | 1435 | static void ath10k_pci_bmi_send_done(struct ath10k_ce_pipe *ce_state) |
5e3dd157 | 1436 | { |
5440ce25 MK |
1437 | struct bmi_xfer *xfer; |
1438 | u32 ce_data; | |
1439 | unsigned int nbytes; | |
1440 | unsigned int transfer_id; | |
1441 | ||
1442 | if (ath10k_ce_completed_send_next(ce_state, (void **)&xfer, &ce_data, | |
1443 | &nbytes, &transfer_id)) | |
1444 | return; | |
5e3dd157 | 1445 | |
2374b186 | 1446 | xfer->tx_done = true; |
5e3dd157 KV |
1447 | } |
1448 | ||
5440ce25 | 1449 | static void ath10k_pci_bmi_recv_data(struct ath10k_ce_pipe *ce_state) |
5e3dd157 | 1450 | { |
7aa7a72a | 1451 | struct ath10k *ar = ce_state->ar; |
5440ce25 MK |
1452 | struct bmi_xfer *xfer; |
1453 | u32 ce_data; | |
1454 | unsigned int nbytes; | |
1455 | unsigned int transfer_id; | |
1456 | unsigned int flags; | |
1457 | ||
1458 | if (ath10k_ce_completed_recv_next(ce_state, (void **)&xfer, &ce_data, | |
1459 | &nbytes, &transfer_id, &flags)) | |
1460 | return; | |
5e3dd157 | 1461 | |
04ed9dfe MK |
1462 | if (WARN_ON_ONCE(!xfer)) |
1463 | return; | |
1464 | ||
5e3dd157 | 1465 | if (!xfer->wait_for_resp) { |
7aa7a72a | 1466 | ath10k_warn(ar, "unexpected: BMI data received; ignoring\n"); |
5e3dd157 KV |
1467 | return; |
1468 | } | |
1469 | ||
1470 | xfer->resp_len = nbytes; | |
2374b186 | 1471 | xfer->rx_done = true; |
5e3dd157 KV |
1472 | } |
1473 | ||
85622cde MK |
1474 | static int ath10k_pci_bmi_wait(struct ath10k_ce_pipe *tx_pipe, |
1475 | struct ath10k_ce_pipe *rx_pipe, | |
1476 | struct bmi_xfer *xfer) | |
1477 | { | |
1478 | unsigned long timeout = jiffies + BMI_COMMUNICATION_TIMEOUT_HZ; | |
1479 | ||
1480 | while (time_before_eq(jiffies, timeout)) { | |
1481 | ath10k_pci_bmi_send_done(tx_pipe); | |
1482 | ath10k_pci_bmi_recv_data(rx_pipe); | |
1483 | ||
2374b186 | 1484 | if (xfer->tx_done && (xfer->rx_done == xfer->wait_for_resp)) |
85622cde MK |
1485 | return 0; |
1486 | ||
1487 | schedule(); | |
1488 | } | |
5e3dd157 | 1489 | |
85622cde MK |
1490 | return -ETIMEDOUT; |
1491 | } | |
5e3dd157 KV |
1492 | |
1493 | /* | |
1494 | * Send an interrupt to the device to wake up the Target CPU | |
1495 | * so it has an opportunity to notice any changed state. | |
1496 | */ | |
1497 | static int ath10k_pci_wake_target_cpu(struct ath10k *ar) | |
1498 | { | |
9e264945 | 1499 | u32 addr, val; |
5e3dd157 | 1500 | |
9e264945 MK |
1501 | addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS; |
1502 | val = ath10k_pci_read32(ar, addr); | |
1503 | val |= CORE_CTRL_CPU_INTR_MASK; | |
1504 | ath10k_pci_write32(ar, addr, val); | |
5e3dd157 | 1505 | |
1d2b48d6 | 1506 | return 0; |
5e3dd157 KV |
1507 | } |
1508 | ||
1509 | static int ath10k_pci_init_config(struct ath10k *ar) | |
1510 | { | |
1511 | u32 interconnect_targ_addr; | |
1512 | u32 pcie_state_targ_addr = 0; | |
1513 | u32 pipe_cfg_targ_addr = 0; | |
1514 | u32 svc_to_pipe_map = 0; | |
1515 | u32 pcie_config_flags = 0; | |
1516 | u32 ealloc_value; | |
1517 | u32 ealloc_targ_addr; | |
1518 | u32 flag2_value; | |
1519 | u32 flag2_targ_addr; | |
1520 | int ret = 0; | |
1521 | ||
1522 | /* Download to Target the CE Config and the service-to-CE map */ | |
1523 | interconnect_targ_addr = | |
1524 | host_interest_item_address(HI_ITEM(hi_interconnect_state)); | |
1525 | ||
1526 | /* Supply Target-side CE configuration */ | |
9e264945 MK |
1527 | ret = ath10k_pci_diag_read32(ar, interconnect_targ_addr, |
1528 | &pcie_state_targ_addr); | |
5e3dd157 | 1529 | if (ret != 0) { |
7aa7a72a | 1530 | ath10k_err(ar, "Failed to get pcie state addr: %d\n", ret); |
5e3dd157 KV |
1531 | return ret; |
1532 | } | |
1533 | ||
1534 | if (pcie_state_targ_addr == 0) { | |
1535 | ret = -EIO; | |
7aa7a72a | 1536 | ath10k_err(ar, "Invalid pcie state addr\n"); |
5e3dd157 KV |
1537 | return ret; |
1538 | } | |
1539 | ||
9e264945 | 1540 | ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + |
5e3dd157 | 1541 | offsetof(struct pcie_state, |
9e264945 MK |
1542 | pipe_cfg_addr)), |
1543 | &pipe_cfg_targ_addr); | |
5e3dd157 | 1544 | if (ret != 0) { |
7aa7a72a | 1545 | ath10k_err(ar, "Failed to get pipe cfg addr: %d\n", ret); |
5e3dd157 KV |
1546 | return ret; |
1547 | } | |
1548 | ||
1549 | if (pipe_cfg_targ_addr == 0) { | |
1550 | ret = -EIO; | |
7aa7a72a | 1551 | ath10k_err(ar, "Invalid pipe cfg addr\n"); |
5e3dd157 KV |
1552 | return ret; |
1553 | } | |
1554 | ||
1555 | ret = ath10k_pci_diag_write_mem(ar, pipe_cfg_targ_addr, | |
5b07e07f KV |
1556 | target_ce_config_wlan, |
1557 | sizeof(target_ce_config_wlan)); | |
5e3dd157 KV |
1558 | |
1559 | if (ret != 0) { | |
7aa7a72a | 1560 | ath10k_err(ar, "Failed to write pipe cfg: %d\n", ret); |
5e3dd157 KV |
1561 | return ret; |
1562 | } | |
1563 | ||
9e264945 | 1564 | ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + |
5e3dd157 | 1565 | offsetof(struct pcie_state, |
9e264945 MK |
1566 | svc_to_pipe_map)), |
1567 | &svc_to_pipe_map); | |
5e3dd157 | 1568 | if (ret != 0) { |
7aa7a72a | 1569 | ath10k_err(ar, "Failed to get svc/pipe map: %d\n", ret); |
5e3dd157 KV |
1570 | return ret; |
1571 | } | |
1572 | ||
1573 | if (svc_to_pipe_map == 0) { | |
1574 | ret = -EIO; | |
7aa7a72a | 1575 | ath10k_err(ar, "Invalid svc_to_pipe map\n"); |
5e3dd157 KV |
1576 | return ret; |
1577 | } | |
1578 | ||
1579 | ret = ath10k_pci_diag_write_mem(ar, svc_to_pipe_map, | |
5b07e07f KV |
1580 | target_service_to_ce_map_wlan, |
1581 | sizeof(target_service_to_ce_map_wlan)); | |
5e3dd157 | 1582 | if (ret != 0) { |
7aa7a72a | 1583 | ath10k_err(ar, "Failed to write svc/pipe map: %d\n", ret); |
5e3dd157 KV |
1584 | return ret; |
1585 | } | |
1586 | ||
9e264945 | 1587 | ret = ath10k_pci_diag_read32(ar, (pcie_state_targ_addr + |
5e3dd157 | 1588 | offsetof(struct pcie_state, |
9e264945 MK |
1589 | config_flags)), |
1590 | &pcie_config_flags); | |
5e3dd157 | 1591 | if (ret != 0) { |
7aa7a72a | 1592 | ath10k_err(ar, "Failed to get pcie config_flags: %d\n", ret); |
5e3dd157 KV |
1593 | return ret; |
1594 | } | |
1595 | ||
1596 | pcie_config_flags &= ~PCIE_CONFIG_FLAG_ENABLE_L1; | |
1597 | ||
9e264945 MK |
1598 | ret = ath10k_pci_diag_write32(ar, (pcie_state_targ_addr + |
1599 | offsetof(struct pcie_state, | |
1600 | config_flags)), | |
1601 | pcie_config_flags); | |
5e3dd157 | 1602 | if (ret != 0) { |
7aa7a72a | 1603 | ath10k_err(ar, "Failed to write pcie config_flags: %d\n", ret); |
5e3dd157 KV |
1604 | return ret; |
1605 | } | |
1606 | ||
1607 | /* configure early allocation */ | |
1608 | ealloc_targ_addr = host_interest_item_address(HI_ITEM(hi_early_alloc)); | |
1609 | ||
9e264945 | 1610 | ret = ath10k_pci_diag_read32(ar, ealloc_targ_addr, &ealloc_value); |
5e3dd157 | 1611 | if (ret != 0) { |
7aa7a72a | 1612 | ath10k_err(ar, "Faile to get early alloc val: %d\n", ret); |
5e3dd157 KV |
1613 | return ret; |
1614 | } | |
1615 | ||
1616 | /* first bank is switched to IRAM */ | |
1617 | ealloc_value |= ((HI_EARLY_ALLOC_MAGIC << HI_EARLY_ALLOC_MAGIC_SHIFT) & | |
1618 | HI_EARLY_ALLOC_MAGIC_MASK); | |
1619 | ealloc_value |= ((1 << HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) & | |
1620 | HI_EARLY_ALLOC_IRAM_BANKS_MASK); | |
1621 | ||
9e264945 | 1622 | ret = ath10k_pci_diag_write32(ar, ealloc_targ_addr, ealloc_value); |
5e3dd157 | 1623 | if (ret != 0) { |
7aa7a72a | 1624 | ath10k_err(ar, "Failed to set early alloc val: %d\n", ret); |
5e3dd157 KV |
1625 | return ret; |
1626 | } | |
1627 | ||
1628 | /* Tell Target to proceed with initialization */ | |
1629 | flag2_targ_addr = host_interest_item_address(HI_ITEM(hi_option_flag2)); | |
1630 | ||
9e264945 | 1631 | ret = ath10k_pci_diag_read32(ar, flag2_targ_addr, &flag2_value); |
5e3dd157 | 1632 | if (ret != 0) { |
7aa7a72a | 1633 | ath10k_err(ar, "Failed to get option val: %d\n", ret); |
5e3dd157 KV |
1634 | return ret; |
1635 | } | |
1636 | ||
1637 | flag2_value |= HI_OPTION_EARLY_CFG_DONE; | |
1638 | ||
9e264945 | 1639 | ret = ath10k_pci_diag_write32(ar, flag2_targ_addr, flag2_value); |
5e3dd157 | 1640 | if (ret != 0) { |
7aa7a72a | 1641 | ath10k_err(ar, "Failed to set option val: %d\n", ret); |
5e3dd157 KV |
1642 | return ret; |
1643 | } | |
1644 | ||
1645 | return 0; | |
1646 | } | |
1647 | ||
84cbf3a7 | 1648 | static int ath10k_pci_alloc_pipes(struct ath10k *ar) |
25d0dbcb | 1649 | { |
84cbf3a7 MK |
1650 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
1651 | struct ath10k_pci_pipe *pipe; | |
25d0dbcb MK |
1652 | int i, ret; |
1653 | ||
1654 | for (i = 0; i < CE_COUNT; i++) { | |
84cbf3a7 MK |
1655 | pipe = &ar_pci->pipe_info[i]; |
1656 | pipe->ce_hdl = &ar_pci->ce_states[i]; | |
1657 | pipe->pipe_num = i; | |
1658 | pipe->hif_ce_state = ar; | |
1659 | ||
1660 | ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i], | |
1661 | ath10k_pci_ce_send_done, | |
1662 | ath10k_pci_ce_recv_data); | |
25d0dbcb | 1663 | if (ret) { |
7aa7a72a | 1664 | ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n", |
25d0dbcb MK |
1665 | i, ret); |
1666 | return ret; | |
1667 | } | |
84cbf3a7 MK |
1668 | |
1669 | /* Last CE is Diagnostic Window */ | |
1670 | if (i == CE_COUNT - 1) { | |
1671 | ar_pci->ce_diag = pipe->ce_hdl; | |
1672 | continue; | |
1673 | } | |
1674 | ||
1675 | pipe->buf_sz = (size_t)(host_ce_config_wlan[i].src_sz_max); | |
25d0dbcb MK |
1676 | } |
1677 | ||
1678 | return 0; | |
1679 | } | |
1680 | ||
84cbf3a7 | 1681 | static void ath10k_pci_free_pipes(struct ath10k *ar) |
25d0dbcb MK |
1682 | { |
1683 | int i; | |
5e3dd157 | 1684 | |
25d0dbcb MK |
1685 | for (i = 0; i < CE_COUNT; i++) |
1686 | ath10k_ce_free_pipe(ar, i); | |
1687 | } | |
5e3dd157 | 1688 | |
84cbf3a7 | 1689 | static int ath10k_pci_init_pipes(struct ath10k *ar) |
5e3dd157 | 1690 | { |
84cbf3a7 | 1691 | int i, ret; |
5e3dd157 | 1692 | |
84cbf3a7 MK |
1693 | for (i = 0; i < CE_COUNT; i++) { |
1694 | ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]); | |
25d0dbcb | 1695 | if (ret) { |
7aa7a72a | 1696 | ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n", |
84cbf3a7 | 1697 | i, ret); |
25d0dbcb | 1698 | return ret; |
5e3dd157 | 1699 | } |
5e3dd157 KV |
1700 | } |
1701 | ||
5e3dd157 KV |
1702 | return 0; |
1703 | } | |
1704 | ||
5c771e74 | 1705 | static bool ath10k_pci_has_fw_crashed(struct ath10k *ar) |
5e3dd157 | 1706 | { |
5c771e74 MK |
1707 | return ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS) & |
1708 | FW_IND_EVENT_PENDING; | |
1709 | } | |
5e3dd157 | 1710 | |
5c771e74 MK |
1711 | static void ath10k_pci_fw_crashed_clear(struct ath10k *ar) |
1712 | { | |
1713 | u32 val; | |
5e3dd157 | 1714 | |
5c771e74 MK |
1715 | val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); |
1716 | val &= ~FW_IND_EVENT_PENDING; | |
1717 | ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, val); | |
5e3dd157 KV |
1718 | } |
1719 | ||
de01357b MK |
1720 | /* this function effectively clears target memory controller assert line */ |
1721 | static void ath10k_pci_warm_reset_si0(struct ath10k *ar) | |
1722 | { | |
1723 | u32 val; | |
1724 | ||
1725 | val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); | |
1726 | ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, | |
1727 | val | SOC_RESET_CONTROL_SI0_RST_MASK); | |
1728 | val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); | |
1729 | ||
1730 | msleep(10); | |
1731 | ||
1732 | val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); | |
1733 | ath10k_pci_soc_write32(ar, SOC_RESET_CONTROL_ADDRESS, | |
1734 | val & ~SOC_RESET_CONTROL_SI0_RST_MASK); | |
1735 | val = ath10k_pci_soc_read32(ar, SOC_RESET_CONTROL_ADDRESS); | |
1736 | ||
1737 | msleep(10); | |
1738 | } | |
1739 | ||
61c1648b | 1740 | static void ath10k_pci_warm_reset_cpu(struct ath10k *ar) |
fc36e3ff | 1741 | { |
fc36e3ff MK |
1742 | u32 val; |
1743 | ||
b39712ce | 1744 | ath10k_pci_write32(ar, FW_INDICATOR_ADDRESS, 0); |
fc36e3ff | 1745 | |
fc36e3ff | 1746 | val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + |
61c1648b MK |
1747 | SOC_RESET_CONTROL_ADDRESS); |
1748 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, | |
1749 | val | SOC_RESET_CONTROL_CPU_WARM_RST_MASK); | |
1750 | } | |
1751 | ||
1752 | static void ath10k_pci_warm_reset_ce(struct ath10k *ar) | |
1753 | { | |
1754 | u32 val; | |
fc36e3ff | 1755 | |
fc36e3ff MK |
1756 | val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + |
1757 | SOC_RESET_CONTROL_ADDRESS); | |
61c1648b | 1758 | |
fc36e3ff MK |
1759 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, |
1760 | val | SOC_RESET_CONTROL_CE_RST_MASK); | |
fc36e3ff | 1761 | msleep(10); |
fc36e3ff MK |
1762 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + SOC_RESET_CONTROL_ADDRESS, |
1763 | val & ~SOC_RESET_CONTROL_CE_RST_MASK); | |
61c1648b MK |
1764 | } |
1765 | ||
1766 | static void ath10k_pci_warm_reset_clear_lf(struct ath10k *ar) | |
1767 | { | |
1768 | u32 val; | |
1769 | ||
fc36e3ff | 1770 | val = ath10k_pci_read32(ar, RTC_SOC_BASE_ADDRESS + |
61c1648b MK |
1771 | SOC_LF_TIMER_CONTROL0_ADDRESS); |
1772 | ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + | |
1773 | SOC_LF_TIMER_CONTROL0_ADDRESS, | |
1774 | val & ~SOC_LF_TIMER_CONTROL0_ENABLE_MASK); | |
1775 | } | |
fc36e3ff | 1776 | |
61c1648b MK |
1777 | static int ath10k_pci_warm_reset(struct ath10k *ar) |
1778 | { | |
1779 | int ret; | |
1780 | ||
1781 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset\n"); | |
de01357b | 1782 | |
61c1648b MK |
1783 | spin_lock_bh(&ar->data_lock); |
1784 | ar->stats.fw_warm_reset_counter++; | |
1785 | spin_unlock_bh(&ar->data_lock); | |
fc36e3ff | 1786 | |
61c1648b | 1787 | ath10k_pci_irq_disable(ar); |
fc36e3ff | 1788 | |
61c1648b MK |
1789 | /* Make sure the target CPU is not doing anything dangerous, e.g. if it |
1790 | * were to access copy engine while host performs copy engine reset | |
1791 | * then it is possible for the device to confuse pci-e controller to | |
1792 | * the point of bringing host system to a complete stop (i.e. hang). | |
1793 | */ | |
1794 | ath10k_pci_warm_reset_si0(ar); | |
1795 | ath10k_pci_warm_reset_cpu(ar); | |
1796 | ath10k_pci_init_pipes(ar); | |
1797 | ath10k_pci_wait_for_target_init(ar); | |
fc36e3ff | 1798 | |
61c1648b MK |
1799 | ath10k_pci_warm_reset_clear_lf(ar); |
1800 | ath10k_pci_warm_reset_ce(ar); | |
1801 | ath10k_pci_warm_reset_cpu(ar); | |
1802 | ath10k_pci_init_pipes(ar); | |
fc36e3ff | 1803 | |
61c1648b MK |
1804 | ret = ath10k_pci_wait_for_target_init(ar); |
1805 | if (ret) { | |
1806 | ath10k_warn(ar, "failed to wait for target init: %d\n", ret); | |
1807 | return ret; | |
1808 | } | |
fc36e3ff | 1809 | |
7aa7a72a | 1810 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot warm reset complete\n"); |
fc36e3ff | 1811 | |
c0c378f9 | 1812 | return 0; |
fc36e3ff MK |
1813 | } |
1814 | ||
0bc14d06 MK |
1815 | static int ath10k_pci_chip_reset(struct ath10k *ar) |
1816 | { | |
1817 | int i, ret; | |
1818 | u32 val; | |
1819 | ||
1820 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset\n"); | |
1821 | ||
1822 | /* Some hardware revisions (e.g. CUS223v2) has issues with cold reset. | |
1823 | * It is thus preferred to use warm reset which is safer but may not be | |
1824 | * able to recover the device from all possible fail scenarios. | |
1825 | * | |
1826 | * Warm reset doesn't always work on first try so attempt it a few | |
1827 | * times before giving up. | |
1828 | */ | |
1829 | for (i = 0; i < ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS; i++) { | |
1830 | ret = ath10k_pci_warm_reset(ar); | |
1831 | if (ret) { | |
1832 | ath10k_warn(ar, "failed to warm reset attempt %d of %d: %d\n", | |
1833 | i + 1, ATH10K_PCI_NUM_WARM_RESET_ATTEMPTS, | |
1834 | ret); | |
1835 | continue; | |
1836 | } | |
1837 | ||
1838 | /* FIXME: Sometimes copy engine doesn't recover after warm | |
1839 | * reset. In most cases this needs cold reset. In some of these | |
1840 | * cases the device is in such a state that a cold reset may | |
1841 | * lock up the host. | |
1842 | * | |
1843 | * Reading any host interest register via copy engine is | |
1844 | * sufficient to verify if device is capable of booting | |
1845 | * firmware blob. | |
1846 | */ | |
1847 | ret = ath10k_pci_init_pipes(ar); | |
1848 | if (ret) { | |
1849 | ath10k_warn(ar, "failed to init copy engine: %d\n", | |
1850 | ret); | |
1851 | continue; | |
1852 | } | |
1853 | ||
1854 | ret = ath10k_pci_diag_read32(ar, QCA988X_HOST_INTEREST_ADDRESS, | |
1855 | &val); | |
1856 | if (ret) { | |
1857 | ath10k_warn(ar, "failed to poke copy engine: %d\n", | |
1858 | ret); | |
1859 | continue; | |
1860 | } | |
1861 | ||
1862 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (warm)\n"); | |
1863 | return 0; | |
1864 | } | |
1865 | ||
1866 | if (ath10k_pci_reset_mode == ATH10K_PCI_RESET_WARM_ONLY) { | |
1867 | ath10k_warn(ar, "refusing cold reset as requested\n"); | |
1868 | return -EPERM; | |
1869 | } | |
1870 | ||
1871 | ret = ath10k_pci_cold_reset(ar); | |
1872 | if (ret) { | |
1873 | ath10k_warn(ar, "failed to cold reset: %d\n", ret); | |
1874 | return ret; | |
1875 | } | |
1876 | ||
1877 | ret = ath10k_pci_wait_for_target_init(ar); | |
1878 | if (ret) { | |
1879 | ath10k_warn(ar, "failed to wait for target after cold reset: %d\n", | |
1880 | ret); | |
1881 | return ret; | |
1882 | } | |
1883 | ||
1884 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip reset complete (cold)\n"); | |
1885 | ||
1886 | return 0; | |
1887 | } | |
1888 | ||
1889 | static int ath10k_pci_hif_power_up(struct ath10k *ar) | |
8c5c5368 MK |
1890 | { |
1891 | int ret; | |
1892 | ||
0bc14d06 MK |
1893 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power up\n"); |
1894 | ||
707b1bbd BM |
1895 | ret = ath10k_pci_wake(ar); |
1896 | if (ret) { | |
1897 | ath10k_err(ar, "failed to wake up target: %d\n", ret); | |
1898 | return ret; | |
1899 | } | |
1900 | ||
8c5c5368 MK |
1901 | /* |
1902 | * Bring the target up cleanly. | |
1903 | * | |
1904 | * The target may be in an undefined state with an AUX-powered Target | |
1905 | * and a Host in WoW mode. If the Host crashes, loses power, or is | |
1906 | * restarted (without unloading the driver) then the Target is left | |
1907 | * (aux) powered and running. On a subsequent driver load, the Target | |
1908 | * is in an unexpected state. We try to catch that here in order to | |
1909 | * reset the Target and retry the probe. | |
1910 | */ | |
0bc14d06 | 1911 | ret = ath10k_pci_chip_reset(ar); |
5b2589fc | 1912 | if (ret) { |
0bc14d06 | 1913 | ath10k_err(ar, "failed to reset chip: %d\n", ret); |
707b1bbd | 1914 | goto err_sleep; |
5b2589fc | 1915 | } |
8c5c5368 | 1916 | |
84cbf3a7 | 1917 | ret = ath10k_pci_init_pipes(ar); |
1d2b48d6 | 1918 | if (ret) { |
7aa7a72a | 1919 | ath10k_err(ar, "failed to initialize CE: %d\n", ret); |
707b1bbd | 1920 | goto err_sleep; |
ab977bd0 MK |
1921 | } |
1922 | ||
98563d5a MK |
1923 | ret = ath10k_pci_init_config(ar); |
1924 | if (ret) { | |
7aa7a72a | 1925 | ath10k_err(ar, "failed to setup init config: %d\n", ret); |
5c771e74 | 1926 | goto err_ce; |
98563d5a | 1927 | } |
8c5c5368 MK |
1928 | |
1929 | ret = ath10k_pci_wake_target_cpu(ar); | |
1930 | if (ret) { | |
7aa7a72a | 1931 | ath10k_err(ar, "could not wake up target CPU: %d\n", ret); |
5c771e74 | 1932 | goto err_ce; |
8c5c5368 MK |
1933 | } |
1934 | ||
1935 | return 0; | |
1936 | ||
1937 | err_ce: | |
1938 | ath10k_pci_ce_deinit(ar); | |
61c95cea | 1939 | |
707b1bbd BM |
1940 | err_sleep: |
1941 | ath10k_pci_sleep(ar); | |
61c95cea MK |
1942 | return ret; |
1943 | } | |
1944 | ||
8c5c5368 MK |
1945 | static void ath10k_pci_hif_power_down(struct ath10k *ar) |
1946 | { | |
7aa7a72a | 1947 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n"); |
50f87a67 | 1948 | |
c011b281 MK |
1949 | /* Currently hif_power_up performs effectively a reset and hif_stop |
1950 | * resets the chip as well so there's no point in resetting here. | |
1951 | */ | |
707b1bbd BM |
1952 | |
1953 | ath10k_pci_sleep(ar); | |
8c5c5368 MK |
1954 | } |
1955 | ||
8cd13cad MK |
1956 | #ifdef CONFIG_PM |
1957 | ||
1958 | #define ATH10K_PCI_PM_CONTROL 0x44 | |
1959 | ||
1960 | static int ath10k_pci_hif_suspend(struct ath10k *ar) | |
1961 | { | |
1962 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
1963 | struct pci_dev *pdev = ar_pci->pdev; | |
1964 | u32 val; | |
1965 | ||
1966 | pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val); | |
1967 | ||
1968 | if ((val & 0x000000ff) != 0x3) { | |
1969 | pci_save_state(pdev); | |
1970 | pci_disable_device(pdev); | |
1971 | pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL, | |
1972 | (val & 0xffffff00) | 0x03); | |
1973 | } | |
1974 | ||
1975 | return 0; | |
1976 | } | |
1977 | ||
1978 | static int ath10k_pci_hif_resume(struct ath10k *ar) | |
1979 | { | |
1980 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
1981 | struct pci_dev *pdev = ar_pci->pdev; | |
1982 | u32 val; | |
1983 | ||
1984 | pci_read_config_dword(pdev, ATH10K_PCI_PM_CONTROL, &val); | |
1985 | ||
1986 | if ((val & 0x000000ff) != 0) { | |
1987 | pci_restore_state(pdev); | |
1988 | pci_write_config_dword(pdev, ATH10K_PCI_PM_CONTROL, | |
1989 | val & 0xffffff00); | |
1990 | /* | |
1991 | * Suspend/Resume resets the PCI configuration space, | |
1992 | * so we have to re-disable the RETRY_TIMEOUT register (0x41) | |
1993 | * to keep PCI Tx retries from interfering with C3 CPU state | |
1994 | */ | |
1995 | pci_read_config_dword(pdev, 0x40, &val); | |
1996 | ||
1997 | if ((val & 0x0000ff00) != 0) | |
1998 | pci_write_config_dword(pdev, 0x40, val & 0xffff00ff); | |
1999 | } | |
2000 | ||
2001 | return 0; | |
2002 | } | |
2003 | #endif | |
2004 | ||
5e3dd157 | 2005 | static const struct ath10k_hif_ops ath10k_pci_hif_ops = { |
726346fc | 2006 | .tx_sg = ath10k_pci_hif_tx_sg, |
eef25405 | 2007 | .diag_read = ath10k_pci_hif_diag_read, |
9f65ad25 | 2008 | .diag_write = ath10k_pci_diag_write_mem, |
5e3dd157 KV |
2009 | .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg, |
2010 | .start = ath10k_pci_hif_start, | |
2011 | .stop = ath10k_pci_hif_stop, | |
2012 | .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe, | |
2013 | .get_default_pipe = ath10k_pci_hif_get_default_pipe, | |
2014 | .send_complete_check = ath10k_pci_hif_send_complete_check, | |
e799bbff | 2015 | .set_callbacks = ath10k_pci_hif_set_callbacks, |
5e3dd157 | 2016 | .get_free_queue_number = ath10k_pci_hif_get_free_queue_number, |
8c5c5368 MK |
2017 | .power_up = ath10k_pci_hif_power_up, |
2018 | .power_down = ath10k_pci_hif_power_down, | |
077a3804 YL |
2019 | .read32 = ath10k_pci_read32, |
2020 | .write32 = ath10k_pci_write32, | |
8cd13cad MK |
2021 | #ifdef CONFIG_PM |
2022 | .suspend = ath10k_pci_hif_suspend, | |
2023 | .resume = ath10k_pci_hif_resume, | |
2024 | #endif | |
5e3dd157 KV |
2025 | }; |
2026 | ||
2027 | static void ath10k_pci_ce_tasklet(unsigned long ptr) | |
2028 | { | |
87263e5b | 2029 | struct ath10k_pci_pipe *pipe = (struct ath10k_pci_pipe *)ptr; |
5e3dd157 KV |
2030 | struct ath10k_pci *ar_pci = pipe->ar_pci; |
2031 | ||
2032 | ath10k_ce_per_engine_service(ar_pci->ar, pipe->pipe_num); | |
2033 | } | |
2034 | ||
2035 | static void ath10k_msi_err_tasklet(unsigned long data) | |
2036 | { | |
2037 | struct ath10k *ar = (struct ath10k *)data; | |
2038 | ||
5c771e74 | 2039 | if (!ath10k_pci_has_fw_crashed(ar)) { |
7aa7a72a | 2040 | ath10k_warn(ar, "received unsolicited fw crash interrupt\n"); |
5c771e74 MK |
2041 | return; |
2042 | } | |
2043 | ||
2044 | ath10k_pci_fw_crashed_clear(ar); | |
2045 | ath10k_pci_fw_crashed_dump(ar); | |
5e3dd157 KV |
2046 | } |
2047 | ||
2048 | /* | |
2049 | * Handler for a per-engine interrupt on a PARTICULAR CE. | |
2050 | * This is used in cases where each CE has a private MSI interrupt. | |
2051 | */ | |
2052 | static irqreturn_t ath10k_pci_per_engine_handler(int irq, void *arg) | |
2053 | { | |
2054 | struct ath10k *ar = arg; | |
2055 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2056 | int ce_id = irq - ar_pci->pdev->irq - MSI_ASSIGN_CE_INITIAL; | |
2057 | ||
e5742672 | 2058 | if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_pci->pipe_info)) { |
7aa7a72a MK |
2059 | ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq, |
2060 | ce_id); | |
5e3dd157 KV |
2061 | return IRQ_HANDLED; |
2062 | } | |
2063 | ||
2064 | /* | |
2065 | * NOTE: We are able to derive ce_id from irq because we | |
2066 | * use a one-to-one mapping for CE's 0..5. | |
2067 | * CE's 6 & 7 do not use interrupts at all. | |
2068 | * | |
2069 | * This mapping must be kept in sync with the mapping | |
2070 | * used by firmware. | |
2071 | */ | |
2072 | tasklet_schedule(&ar_pci->pipe_info[ce_id].intr); | |
2073 | return IRQ_HANDLED; | |
2074 | } | |
2075 | ||
2076 | static irqreturn_t ath10k_pci_msi_fw_handler(int irq, void *arg) | |
2077 | { | |
2078 | struct ath10k *ar = arg; | |
2079 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2080 | ||
2081 | tasklet_schedule(&ar_pci->msi_fw_err); | |
2082 | return IRQ_HANDLED; | |
2083 | } | |
2084 | ||
2085 | /* | |
2086 | * Top-level interrupt handler for all PCI interrupts from a Target. | |
2087 | * When a block of MSI interrupts is allocated, this top-level handler | |
2088 | * is not used; instead, we directly call the correct sub-handler. | |
2089 | */ | |
2090 | static irqreturn_t ath10k_pci_interrupt_handler(int irq, void *arg) | |
2091 | { | |
2092 | struct ath10k *ar = arg; | |
2093 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2094 | ||
2095 | if (ar_pci->num_msi_intrs == 0) { | |
e539887b MK |
2096 | if (!ath10k_pci_irq_pending(ar)) |
2097 | return IRQ_NONE; | |
2098 | ||
2685218b | 2099 | ath10k_pci_disable_and_clear_legacy_irq(ar); |
5e3dd157 KV |
2100 | } |
2101 | ||
2102 | tasklet_schedule(&ar_pci->intr_tq); | |
2103 | ||
2104 | return IRQ_HANDLED; | |
2105 | } | |
2106 | ||
5c771e74 | 2107 | static void ath10k_pci_tasklet(unsigned long data) |
ab977bd0 MK |
2108 | { |
2109 | struct ath10k *ar = (struct ath10k *)data; | |
5c771e74 | 2110 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
ab977bd0 | 2111 | |
5c771e74 MK |
2112 | if (ath10k_pci_has_fw_crashed(ar)) { |
2113 | ath10k_pci_fw_crashed_clear(ar); | |
0e9848c0 | 2114 | ath10k_pci_fw_crashed_dump(ar); |
ab977bd0 MK |
2115 | return; |
2116 | } | |
2117 | ||
5e3dd157 KV |
2118 | ath10k_ce_per_engine_service_any(ar); |
2119 | ||
2685218b MK |
2120 | /* Re-enable legacy irq that was disabled in the irq handler */ |
2121 | if (ar_pci->num_msi_intrs == 0) | |
2122 | ath10k_pci_enable_legacy_irq(ar); | |
5e3dd157 KV |
2123 | } |
2124 | ||
fc15ca13 | 2125 | static int ath10k_pci_request_irq_msix(struct ath10k *ar) |
5e3dd157 KV |
2126 | { |
2127 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
fc15ca13 | 2128 | int ret, i; |
5e3dd157 KV |
2129 | |
2130 | ret = request_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, | |
2131 | ath10k_pci_msi_fw_handler, | |
2132 | IRQF_SHARED, "ath10k_pci", ar); | |
591ecdb8 | 2133 | if (ret) { |
7aa7a72a | 2134 | ath10k_warn(ar, "failed to request MSI-X fw irq %d: %d\n", |
591ecdb8 | 2135 | ar_pci->pdev->irq + MSI_ASSIGN_FW, ret); |
5e3dd157 | 2136 | return ret; |
591ecdb8 | 2137 | } |
5e3dd157 KV |
2138 | |
2139 | for (i = MSI_ASSIGN_CE_INITIAL; i <= MSI_ASSIGN_CE_MAX; i++) { | |
2140 | ret = request_irq(ar_pci->pdev->irq + i, | |
2141 | ath10k_pci_per_engine_handler, | |
2142 | IRQF_SHARED, "ath10k_pci", ar); | |
2143 | if (ret) { | |
7aa7a72a | 2144 | ath10k_warn(ar, "failed to request MSI-X ce irq %d: %d\n", |
5e3dd157 KV |
2145 | ar_pci->pdev->irq + i, ret); |
2146 | ||
87b1423b MK |
2147 | for (i--; i >= MSI_ASSIGN_CE_INITIAL; i--) |
2148 | free_irq(ar_pci->pdev->irq + i, ar); | |
5e3dd157 | 2149 | |
87b1423b | 2150 | free_irq(ar_pci->pdev->irq + MSI_ASSIGN_FW, ar); |
5e3dd157 KV |
2151 | return ret; |
2152 | } | |
2153 | } | |
2154 | ||
5e3dd157 KV |
2155 | return 0; |
2156 | } | |
2157 | ||
fc15ca13 | 2158 | static int ath10k_pci_request_irq_msi(struct ath10k *ar) |
5e3dd157 KV |
2159 | { |
2160 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2161 | int ret; | |
2162 | ||
5e3dd157 KV |
2163 | ret = request_irq(ar_pci->pdev->irq, |
2164 | ath10k_pci_interrupt_handler, | |
2165 | IRQF_SHARED, "ath10k_pci", ar); | |
fc15ca13 | 2166 | if (ret) { |
7aa7a72a | 2167 | ath10k_warn(ar, "failed to request MSI irq %d: %d\n", |
fc15ca13 | 2168 | ar_pci->pdev->irq, ret); |
5e3dd157 KV |
2169 | return ret; |
2170 | } | |
2171 | ||
5e3dd157 KV |
2172 | return 0; |
2173 | } | |
2174 | ||
fc15ca13 | 2175 | static int ath10k_pci_request_irq_legacy(struct ath10k *ar) |
5e3dd157 KV |
2176 | { |
2177 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2178 | int ret; | |
2179 | ||
2180 | ret = request_irq(ar_pci->pdev->irq, | |
2181 | ath10k_pci_interrupt_handler, | |
2182 | IRQF_SHARED, "ath10k_pci", ar); | |
f3782744 | 2183 | if (ret) { |
7aa7a72a | 2184 | ath10k_warn(ar, "failed to request legacy irq %d: %d\n", |
fc15ca13 | 2185 | ar_pci->pdev->irq, ret); |
5e3dd157 | 2186 | return ret; |
f3782744 | 2187 | } |
5e3dd157 | 2188 | |
5e3dd157 KV |
2189 | return 0; |
2190 | } | |
2191 | ||
fc15ca13 MK |
2192 | static int ath10k_pci_request_irq(struct ath10k *ar) |
2193 | { | |
2194 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
5e3dd157 | 2195 | |
fc15ca13 MK |
2196 | switch (ar_pci->num_msi_intrs) { |
2197 | case 0: | |
2198 | return ath10k_pci_request_irq_legacy(ar); | |
2199 | case 1: | |
2200 | return ath10k_pci_request_irq_msi(ar); | |
2201 | case MSI_NUM_REQUEST: | |
2202 | return ath10k_pci_request_irq_msix(ar); | |
2203 | } | |
5e3dd157 | 2204 | |
7aa7a72a | 2205 | ath10k_warn(ar, "unknown irq configuration upon request\n"); |
fc15ca13 | 2206 | return -EINVAL; |
5e3dd157 KV |
2207 | } |
2208 | ||
fc15ca13 MK |
2209 | static void ath10k_pci_free_irq(struct ath10k *ar) |
2210 | { | |
2211 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2212 | int i; | |
2213 | ||
2214 | /* There's at least one interrupt irregardless whether its legacy INTR | |
2215 | * or MSI or MSI-X */ | |
2216 | for (i = 0; i < max(1, ar_pci->num_msi_intrs); i++) | |
2217 | free_irq(ar_pci->pdev->irq + i, ar); | |
2218 | } | |
2219 | ||
2220 | static void ath10k_pci_init_irq_tasklets(struct ath10k *ar) | |
5e3dd157 KV |
2221 | { |
2222 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
5e3dd157 KV |
2223 | int i; |
2224 | ||
fc15ca13 | 2225 | tasklet_init(&ar_pci->intr_tq, ath10k_pci_tasklet, (unsigned long)ar); |
5e3dd157 | 2226 | tasklet_init(&ar_pci->msi_fw_err, ath10k_msi_err_tasklet, |
fc15ca13 | 2227 | (unsigned long)ar); |
5e3dd157 KV |
2228 | |
2229 | for (i = 0; i < CE_COUNT; i++) { | |
2230 | ar_pci->pipe_info[i].ar_pci = ar_pci; | |
fc15ca13 | 2231 | tasklet_init(&ar_pci->pipe_info[i].intr, ath10k_pci_ce_tasklet, |
5e3dd157 KV |
2232 | (unsigned long)&ar_pci->pipe_info[i]); |
2233 | } | |
fc15ca13 MK |
2234 | } |
2235 | ||
2236 | static int ath10k_pci_init_irq(struct ath10k *ar) | |
2237 | { | |
2238 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2239 | int ret; | |
5e3dd157 | 2240 | |
fc15ca13 | 2241 | ath10k_pci_init_irq_tasklets(ar); |
5e3dd157 | 2242 | |
403d627b | 2243 | if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_AUTO) |
7aa7a72a MK |
2244 | ath10k_info(ar, "limiting irq mode to: %d\n", |
2245 | ath10k_pci_irq_mode); | |
5e3dd157 | 2246 | |
fc15ca13 | 2247 | /* Try MSI-X */ |
0edf2577 | 2248 | if (ath10k_pci_irq_mode == ATH10K_PCI_IRQ_AUTO) { |
cfe9c45b | 2249 | ar_pci->num_msi_intrs = MSI_NUM_REQUEST; |
5ad6867c | 2250 | ret = pci_enable_msi_range(ar_pci->pdev, ar_pci->num_msi_intrs, |
5b07e07f | 2251 | ar_pci->num_msi_intrs); |
5ad6867c | 2252 | if (ret > 0) |
cfe9c45b | 2253 | return 0; |
5e3dd157 | 2254 | |
cfe9c45b | 2255 | /* fall-through */ |
5e3dd157 KV |
2256 | } |
2257 | ||
fc15ca13 | 2258 | /* Try MSI */ |
cfe9c45b MK |
2259 | if (ath10k_pci_irq_mode != ATH10K_PCI_IRQ_LEGACY) { |
2260 | ar_pci->num_msi_intrs = 1; | |
2261 | ret = pci_enable_msi(ar_pci->pdev); | |
5e3dd157 | 2262 | if (ret == 0) |
cfe9c45b | 2263 | return 0; |
5e3dd157 | 2264 | |
cfe9c45b | 2265 | /* fall-through */ |
5e3dd157 KV |
2266 | } |
2267 | ||
fc15ca13 MK |
2268 | /* Try legacy irq |
2269 | * | |
2270 | * A potential race occurs here: The CORE_BASE write | |
2271 | * depends on target correctly decoding AXI address but | |
2272 | * host won't know when target writes BAR to CORE_CTRL. | |
2273 | * This write might get lost if target has NOT written BAR. | |
2274 | * For now, fix the race by repeating the write in below | |
2275 | * synchronization checking. */ | |
2276 | ar_pci->num_msi_intrs = 0; | |
5e3dd157 | 2277 | |
fc15ca13 MK |
2278 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, |
2279 | PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL); | |
fc15ca13 MK |
2280 | |
2281 | return 0; | |
5e3dd157 KV |
2282 | } |
2283 | ||
c0c378f9 | 2284 | static void ath10k_pci_deinit_irq_legacy(struct ath10k *ar) |
5e3dd157 | 2285 | { |
fc15ca13 MK |
2286 | ath10k_pci_write32(ar, SOC_CORE_BASE_ADDRESS + PCIE_INTR_ENABLE_ADDRESS, |
2287 | 0); | |
5e3dd157 KV |
2288 | } |
2289 | ||
fc15ca13 | 2290 | static int ath10k_pci_deinit_irq(struct ath10k *ar) |
5e3dd157 KV |
2291 | { |
2292 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
5e3dd157 | 2293 | |
fc15ca13 MK |
2294 | switch (ar_pci->num_msi_intrs) { |
2295 | case 0: | |
c0c378f9 MK |
2296 | ath10k_pci_deinit_irq_legacy(ar); |
2297 | return 0; | |
fc15ca13 MK |
2298 | case 1: |
2299 | /* fall-through */ | |
2300 | case MSI_NUM_REQUEST: | |
5e3dd157 | 2301 | pci_disable_msi(ar_pci->pdev); |
fc15ca13 | 2302 | return 0; |
bb8b621a AG |
2303 | default: |
2304 | pci_disable_msi(ar_pci->pdev); | |
fc15ca13 MK |
2305 | } |
2306 | ||
7aa7a72a | 2307 | ath10k_warn(ar, "unknown irq configuration upon deinit\n"); |
fc15ca13 | 2308 | return -EINVAL; |
5e3dd157 KV |
2309 | } |
2310 | ||
d7fb47f5 | 2311 | static int ath10k_pci_wait_for_target_init(struct ath10k *ar) |
5e3dd157 KV |
2312 | { |
2313 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
0399eca8 | 2314 | unsigned long timeout; |
0399eca8 | 2315 | u32 val; |
5e3dd157 | 2316 | |
7aa7a72a | 2317 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot waiting target to initialise\n"); |
5e3dd157 | 2318 | |
0399eca8 KV |
2319 | timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT); |
2320 | ||
2321 | do { | |
2322 | val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS); | |
2323 | ||
7aa7a72a MK |
2324 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target indicator %x\n", |
2325 | val); | |
50f87a67 | 2326 | |
0399eca8 KV |
2327 | /* target should never return this */ |
2328 | if (val == 0xffffffff) | |
2329 | continue; | |
2330 | ||
7710cd2e MK |
2331 | /* the device has crashed so don't bother trying anymore */ |
2332 | if (val & FW_IND_EVENT_PENDING) | |
2333 | break; | |
2334 | ||
0399eca8 KV |
2335 | if (val & FW_IND_INITIALIZED) |
2336 | break; | |
2337 | ||
5e3dd157 KV |
2338 | if (ar_pci->num_msi_intrs == 0) |
2339 | /* Fix potential race by repeating CORE_BASE writes */ | |
a428249d | 2340 | ath10k_pci_enable_legacy_irq(ar); |
0399eca8 | 2341 | |
5e3dd157 | 2342 | mdelay(10); |
0399eca8 | 2343 | } while (time_before(jiffies, timeout)); |
5e3dd157 | 2344 | |
a428249d | 2345 | ath10k_pci_disable_and_clear_legacy_irq(ar); |
7c0f0e3c | 2346 | ath10k_pci_irq_msi_fw_mask(ar); |
a428249d | 2347 | |
6a4f6e1d | 2348 | if (val == 0xffffffff) { |
7aa7a72a | 2349 | ath10k_err(ar, "failed to read device register, device is gone\n"); |
c0c378f9 | 2350 | return -EIO; |
6a4f6e1d MK |
2351 | } |
2352 | ||
7710cd2e | 2353 | if (val & FW_IND_EVENT_PENDING) { |
7aa7a72a | 2354 | ath10k_warn(ar, "device has crashed during init\n"); |
5c771e74 | 2355 | ath10k_pci_fw_crashed_clear(ar); |
0e9848c0 | 2356 | ath10k_pci_fw_crashed_dump(ar); |
c0c378f9 | 2357 | return -ECOMM; |
7710cd2e MK |
2358 | } |
2359 | ||
6a4f6e1d | 2360 | if (!(val & FW_IND_INITIALIZED)) { |
7aa7a72a | 2361 | ath10k_err(ar, "failed to receive initialized event from target: %08x\n", |
0399eca8 | 2362 | val); |
c0c378f9 | 2363 | return -ETIMEDOUT; |
5e3dd157 KV |
2364 | } |
2365 | ||
7aa7a72a | 2366 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot target initialised\n"); |
c0c378f9 | 2367 | return 0; |
5e3dd157 KV |
2368 | } |
2369 | ||
fc36e3ff | 2370 | static int ath10k_pci_cold_reset(struct ath10k *ar) |
5e3dd157 | 2371 | { |
c0c378f9 | 2372 | int i; |
5e3dd157 KV |
2373 | u32 val; |
2374 | ||
7aa7a72a | 2375 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n"); |
5e3dd157 | 2376 | |
f51dbe73 BG |
2377 | spin_lock_bh(&ar->data_lock); |
2378 | ||
2379 | ar->stats.fw_cold_reset_counter++; | |
2380 | ||
2381 | spin_unlock_bh(&ar->data_lock); | |
2382 | ||
5e3dd157 | 2383 | /* Put Target, including PCIe, into RESET. */ |
e479ed43 | 2384 | val = ath10k_pci_reg_read32(ar, SOC_GLOBAL_RESET_ADDRESS); |
5e3dd157 | 2385 | val |= 1; |
e479ed43 | 2386 | ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); |
5e3dd157 KV |
2387 | |
2388 | for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { | |
e479ed43 | 2389 | if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) & |
5e3dd157 KV |
2390 | RTC_STATE_COLD_RESET_MASK) |
2391 | break; | |
2392 | msleep(1); | |
2393 | } | |
2394 | ||
2395 | /* Pull Target, including PCIe, out of RESET. */ | |
2396 | val &= ~1; | |
e479ed43 | 2397 | ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val); |
5e3dd157 KV |
2398 | |
2399 | for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) { | |
e479ed43 | 2400 | if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) & |
5e3dd157 KV |
2401 | RTC_STATE_COLD_RESET_MASK)) |
2402 | break; | |
2403 | msleep(1); | |
2404 | } | |
2405 | ||
7aa7a72a | 2406 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n"); |
50f87a67 | 2407 | |
5b2589fc | 2408 | return 0; |
5e3dd157 KV |
2409 | } |
2410 | ||
2986e3ef | 2411 | static int ath10k_pci_claim(struct ath10k *ar) |
5e3dd157 | 2412 | { |
2986e3ef MK |
2413 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); |
2414 | struct pci_dev *pdev = ar_pci->pdev; | |
2415 | u32 lcr_val; | |
2416 | int ret; | |
5e3dd157 KV |
2417 | |
2418 | pci_set_drvdata(pdev, ar); | |
2419 | ||
5e3dd157 KV |
2420 | ret = pci_enable_device(pdev); |
2421 | if (ret) { | |
7aa7a72a | 2422 | ath10k_err(ar, "failed to enable pci device: %d\n", ret); |
2986e3ef | 2423 | return ret; |
5e3dd157 KV |
2424 | } |
2425 | ||
5e3dd157 KV |
2426 | ret = pci_request_region(pdev, BAR_NUM, "ath"); |
2427 | if (ret) { | |
7aa7a72a | 2428 | ath10k_err(ar, "failed to request region BAR%d: %d\n", BAR_NUM, |
2986e3ef | 2429 | ret); |
5e3dd157 KV |
2430 | goto err_device; |
2431 | } | |
2432 | ||
2986e3ef | 2433 | /* Target expects 32 bit DMA. Enforce it. */ |
5e3dd157 KV |
2434 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
2435 | if (ret) { | |
7aa7a72a | 2436 | ath10k_err(ar, "failed to set dma mask to 32-bit: %d\n", ret); |
5e3dd157 KV |
2437 | goto err_region; |
2438 | } | |
2439 | ||
2440 | ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
2441 | if (ret) { | |
7aa7a72a | 2442 | ath10k_err(ar, "failed to set consistent dma mask to 32-bit: %d\n", |
2986e3ef | 2443 | ret); |
5e3dd157 KV |
2444 | goto err_region; |
2445 | } | |
2446 | ||
5e3dd157 KV |
2447 | pci_set_master(pdev); |
2448 | ||
2986e3ef | 2449 | /* Workaround: Disable ASPM */ |
5e3dd157 KV |
2450 | pci_read_config_dword(pdev, 0x80, &lcr_val); |
2451 | pci_write_config_dword(pdev, 0x80, (lcr_val & 0xffffff00)); | |
2452 | ||
2453 | /* Arrange for access to Target SoC registers. */ | |
2986e3ef MK |
2454 | ar_pci->mem = pci_iomap(pdev, BAR_NUM, 0); |
2455 | if (!ar_pci->mem) { | |
7aa7a72a | 2456 | ath10k_err(ar, "failed to iomap BAR%d\n", BAR_NUM); |
5e3dd157 KV |
2457 | ret = -EIO; |
2458 | goto err_master; | |
2459 | } | |
2460 | ||
7aa7a72a | 2461 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot pci_mem 0x%p\n", ar_pci->mem); |
2986e3ef MK |
2462 | return 0; |
2463 | ||
2464 | err_master: | |
2465 | pci_clear_master(pdev); | |
2466 | ||
2467 | err_region: | |
2468 | pci_release_region(pdev, BAR_NUM); | |
2469 | ||
2470 | err_device: | |
2471 | pci_disable_device(pdev); | |
2472 | ||
2473 | return ret; | |
2474 | } | |
2475 | ||
2476 | static void ath10k_pci_release(struct ath10k *ar) | |
2477 | { | |
2478 | struct ath10k_pci *ar_pci = ath10k_pci_priv(ar); | |
2479 | struct pci_dev *pdev = ar_pci->pdev; | |
2480 | ||
2481 | pci_iounmap(pdev, ar_pci->mem); | |
2482 | pci_release_region(pdev, BAR_NUM); | |
2483 | pci_clear_master(pdev); | |
2484 | pci_disable_device(pdev); | |
2485 | } | |
2486 | ||
7505f7c3 MK |
2487 | static bool ath10k_pci_chip_is_supported(u32 dev_id, u32 chip_id) |
2488 | { | |
2489 | const struct ath10k_pci_supp_chip *supp_chip; | |
2490 | int i; | |
2491 | u32 rev_id = MS(chip_id, SOC_CHIP_ID_REV); | |
2492 | ||
2493 | for (i = 0; i < ARRAY_SIZE(ath10k_pci_supp_chips); i++) { | |
2494 | supp_chip = &ath10k_pci_supp_chips[i]; | |
2495 | ||
2496 | if (supp_chip->dev_id == dev_id && | |
2497 | supp_chip->rev_id == rev_id) | |
2498 | return true; | |
2499 | } | |
2500 | ||
2501 | return false; | |
2502 | } | |
2503 | ||
2986e3ef MK |
2504 | static int ath10k_pci_probe(struct pci_dev *pdev, |
2505 | const struct pci_device_id *pci_dev) | |
2506 | { | |
2507 | int ret = 0; | |
2508 | struct ath10k *ar; | |
2509 | struct ath10k_pci *ar_pci; | |
2510 | u32 chip_id; | |
2511 | ||
2986e3ef | 2512 | ar = ath10k_core_create(sizeof(*ar_pci), &pdev->dev, |
e07db352 | 2513 | ATH10K_BUS_PCI, |
2986e3ef MK |
2514 | &ath10k_pci_hif_ops); |
2515 | if (!ar) { | |
7aa7a72a | 2516 | dev_err(&pdev->dev, "failed to allocate core\n"); |
2986e3ef MK |
2517 | return -ENOMEM; |
2518 | } | |
2519 | ||
7aa7a72a MK |
2520 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci probe\n"); |
2521 | ||
2986e3ef MK |
2522 | ar_pci = ath10k_pci_priv(ar); |
2523 | ar_pci->pdev = pdev; | |
2524 | ar_pci->dev = &pdev->dev; | |
2525 | ar_pci->ar = ar; | |
5e3dd157 KV |
2526 | |
2527 | spin_lock_init(&ar_pci->ce_lock); | |
728f95ee MK |
2528 | setup_timer(&ar_pci->rx_post_retry, ath10k_pci_rx_replenish_retry, |
2529 | (unsigned long)ar); | |
5e3dd157 | 2530 | |
2986e3ef | 2531 | ret = ath10k_pci_claim(ar); |
e01ae68c | 2532 | if (ret) { |
7aa7a72a | 2533 | ath10k_err(ar, "failed to claim device: %d\n", ret); |
2986e3ef | 2534 | goto err_core_destroy; |
e01ae68c KV |
2535 | } |
2536 | ||
c0c378f9 | 2537 | ret = ath10k_pci_wake(ar); |
e01ae68c | 2538 | if (ret) { |
7aa7a72a | 2539 | ath10k_err(ar, "failed to wake up: %d\n", ret); |
2986e3ef | 2540 | goto err_release; |
e01ae68c | 2541 | } |
e01ae68c | 2542 | |
233eb97f | 2543 | chip_id = ath10k_pci_soc_read32(ar, SOC_CHIP_ID_ADDRESS); |
c0c378f9 | 2544 | if (chip_id == 0xffffffff) { |
7aa7a72a | 2545 | ath10k_err(ar, "failed to get chip id\n"); |
c0c378f9 MK |
2546 | goto err_sleep; |
2547 | } | |
e01ae68c | 2548 | |
7505f7c3 MK |
2549 | if (!ath10k_pci_chip_is_supported(pdev->device, chip_id)) { |
2550 | ath10k_err(ar, "device %04x with chip_id %08x isn't supported\n", | |
2551 | pdev->device, chip_id); | |
2552 | goto err_sleep; | |
2553 | } | |
2554 | ||
84cbf3a7 | 2555 | ret = ath10k_pci_alloc_pipes(ar); |
25d0dbcb | 2556 | if (ret) { |
7aa7a72a MK |
2557 | ath10k_err(ar, "failed to allocate copy engine pipes: %d\n", |
2558 | ret); | |
c0c378f9 | 2559 | goto err_sleep; |
25d0dbcb MK |
2560 | } |
2561 | ||
403d627b | 2562 | ath10k_pci_ce_deinit(ar); |
7c0f0e3c | 2563 | ath10k_pci_irq_disable(ar); |
24cfade1 | 2564 | |
403d627b | 2565 | ret = ath10k_pci_init_irq(ar); |
5e3dd157 | 2566 | if (ret) { |
7aa7a72a | 2567 | ath10k_err(ar, "failed to init irqs: %d\n", ret); |
84cbf3a7 | 2568 | goto err_free_pipes; |
5e3dd157 KV |
2569 | } |
2570 | ||
7aa7a72a | 2571 | ath10k_info(ar, "pci irq %s interrupts %d irq_mode %d reset_mode %d\n", |
403d627b MK |
2572 | ath10k_pci_get_irq_method(ar), ar_pci->num_msi_intrs, |
2573 | ath10k_pci_irq_mode, ath10k_pci_reset_mode); | |
2574 | ||
5c771e74 MK |
2575 | ret = ath10k_pci_request_irq(ar); |
2576 | if (ret) { | |
7aa7a72a | 2577 | ath10k_warn(ar, "failed to request irqs: %d\n", ret); |
5c771e74 MK |
2578 | goto err_deinit_irq; |
2579 | } | |
2580 | ||
707b1bbd BM |
2581 | ath10k_pci_sleep(ar); |
2582 | ||
e01ae68c | 2583 | ret = ath10k_core_register(ar, chip_id); |
5e3dd157 | 2584 | if (ret) { |
7aa7a72a | 2585 | ath10k_err(ar, "failed to register driver core: %d\n", ret); |
5c771e74 | 2586 | goto err_free_irq; |
5e3dd157 KV |
2587 | } |
2588 | ||
2589 | return 0; | |
2590 | ||
5c771e74 MK |
2591 | err_free_irq: |
2592 | ath10k_pci_free_irq(ar); | |
21396271 | 2593 | ath10k_pci_kill_tasklet(ar); |
5c771e74 | 2594 | |
403d627b MK |
2595 | err_deinit_irq: |
2596 | ath10k_pci_deinit_irq(ar); | |
2597 | ||
84cbf3a7 MK |
2598 | err_free_pipes: |
2599 | ath10k_pci_free_pipes(ar); | |
2986e3ef | 2600 | |
c0c378f9 MK |
2601 | err_sleep: |
2602 | ath10k_pci_sleep(ar); | |
2986e3ef MK |
2603 | |
2604 | err_release: | |
2605 | ath10k_pci_release(ar); | |
2606 | ||
e7b54194 | 2607 | err_core_destroy: |
5e3dd157 | 2608 | ath10k_core_destroy(ar); |
5e3dd157 KV |
2609 | |
2610 | return ret; | |
2611 | } | |
2612 | ||
2613 | static void ath10k_pci_remove(struct pci_dev *pdev) | |
2614 | { | |
2615 | struct ath10k *ar = pci_get_drvdata(pdev); | |
2616 | struct ath10k_pci *ar_pci; | |
2617 | ||
7aa7a72a | 2618 | ath10k_dbg(ar, ATH10K_DBG_PCI, "pci remove\n"); |
5e3dd157 KV |
2619 | |
2620 | if (!ar) | |
2621 | return; | |
2622 | ||
2623 | ar_pci = ath10k_pci_priv(ar); | |
2624 | ||
2625 | if (!ar_pci) | |
2626 | return; | |
2627 | ||
5e3dd157 | 2628 | ath10k_core_unregister(ar); |
5c771e74 | 2629 | ath10k_pci_free_irq(ar); |
21396271 | 2630 | ath10k_pci_kill_tasklet(ar); |
403d627b MK |
2631 | ath10k_pci_deinit_irq(ar); |
2632 | ath10k_pci_ce_deinit(ar); | |
84cbf3a7 | 2633 | ath10k_pci_free_pipes(ar); |
2986e3ef | 2634 | ath10k_pci_release(ar); |
5e3dd157 | 2635 | ath10k_core_destroy(ar); |
5e3dd157 KV |
2636 | } |
2637 | ||
5e3dd157 KV |
2638 | MODULE_DEVICE_TABLE(pci, ath10k_pci_id_table); |
2639 | ||
2640 | static struct pci_driver ath10k_pci_driver = { | |
2641 | .name = "ath10k_pci", | |
2642 | .id_table = ath10k_pci_id_table, | |
2643 | .probe = ath10k_pci_probe, | |
2644 | .remove = ath10k_pci_remove, | |
5e3dd157 KV |
2645 | }; |
2646 | ||
2647 | static int __init ath10k_pci_init(void) | |
2648 | { | |
2649 | int ret; | |
2650 | ||
2651 | ret = pci_register_driver(&ath10k_pci_driver); | |
2652 | if (ret) | |
7aa7a72a MK |
2653 | printk(KERN_ERR "failed to register ath10k pci driver: %d\n", |
2654 | ret); | |
5e3dd157 KV |
2655 | |
2656 | return ret; | |
2657 | } | |
2658 | module_init(ath10k_pci_init); | |
2659 | ||
2660 | static void __exit ath10k_pci_exit(void) | |
2661 | { | |
2662 | pci_unregister_driver(&ath10k_pci_driver); | |
2663 | } | |
2664 | ||
2665 | module_exit(ath10k_pci_exit); | |
2666 | ||
2667 | MODULE_AUTHOR("Qualcomm Atheros"); | |
2668 | MODULE_DESCRIPTION("Driver support for Atheros QCA988X PCIe devices"); | |
2669 | MODULE_LICENSE("Dual BSD/GPL"); | |
8026cae7 BM |
2670 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_FW_FILE); |
2671 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API2_FILE); | |
2672 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" ATH10K_FW_API3_FILE); | |
5e3dd157 | 2673 | MODULE_FIRMWARE(QCA988X_HW_2_0_FW_DIR "/" QCA988X_HW_2_0_BOARD_DATA_FILE); |