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5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
18 | #ifndef _PCI_H_ | |
19 | #define _PCI_H_ | |
20 | ||
21 | #include <linux/interrupt.h> | |
22 | ||
23 | #include "hw.h" | |
24 | #include "ce.h" | |
25 | ||
5e3dd157 KV |
26 | /* |
27 | * maximum number of bytes that can be handled atomically by DiagRead/DiagWrite | |
28 | */ | |
29 | #define DIAG_TRANSFER_LIMIT 2048 | |
30 | ||
31 | /* | |
32 | * maximum number of bytes that can be | |
33 | * handled atomically by DiagRead/DiagWrite | |
34 | */ | |
35 | #define DIAG_TRANSFER_LIMIT 2048 | |
36 | ||
37 | struct bmi_xfer { | |
2374b186 MK |
38 | bool tx_done; |
39 | bool rx_done; | |
5e3dd157 KV |
40 | bool wait_for_resp; |
41 | u32 resp_len; | |
42 | }; | |
43 | ||
5e3dd157 KV |
44 | /* |
45 | * PCI-specific Target state | |
46 | * | |
47 | * NOTE: Structure is shared between Host software and Target firmware! | |
48 | * | |
49 | * Much of this may be of interest to the Host so | |
50 | * HOST_INTEREST->hi_interconnect_state points here | |
51 | * (and all members are 32-bit quantities in order to | |
52 | * facilitate Host access). In particular, Host software is | |
53 | * required to initialize pipe_cfg_addr and svc_to_pipe_map. | |
54 | */ | |
55 | struct pcie_state { | |
56 | /* Pipe configuration Target address */ | |
57 | /* NB: ce_pipe_config[CE_COUNT] */ | |
58 | u32 pipe_cfg_addr; | |
59 | ||
60 | /* Service to pipe map Target address */ | |
61 | /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */ | |
62 | u32 svc_to_pipe_map; | |
63 | ||
64 | /* number of MSI interrupts requested */ | |
65 | u32 msi_requested; | |
66 | ||
67 | /* number of MSI interrupts granted */ | |
68 | u32 msi_granted; | |
69 | ||
70 | /* Message Signalled Interrupt address */ | |
71 | u32 msi_addr; | |
72 | ||
73 | /* Base data */ | |
74 | u32 msi_data; | |
75 | ||
76 | /* | |
77 | * Data for firmware interrupt; | |
78 | * MSI data for other interrupts are | |
79 | * in various SoC registers | |
80 | */ | |
81 | u32 msi_fw_intr_data; | |
82 | ||
83 | /* PCIE_PWR_METHOD_* */ | |
84 | u32 power_mgmt_method; | |
85 | ||
86 | /* PCIE_CONFIG_FLAG_* */ | |
87 | u32 config_flags; | |
88 | }; | |
89 | ||
90 | /* PCIE_CONFIG_FLAG definitions */ | |
91 | #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001 | |
92 | ||
93 | /* Host software's Copy Engine configuration. */ | |
94 | #define CE_ATTR_FLAGS 0 | |
95 | ||
96 | /* | |
97 | * Configuration information for a Copy Engine pipe. | |
98 | * Passed from Host to Target during startup (one per CE). | |
99 | * | |
100 | * NOTE: Structure is shared between Host software and Target firmware! | |
101 | */ | |
102 | struct ce_pipe_config { | |
0fdc14e4 MK |
103 | __le32 pipenum; |
104 | __le32 pipedir; | |
105 | __le32 nentries; | |
106 | __le32 nbytes_max; | |
107 | __le32 flags; | |
108 | __le32 reserved; | |
5e3dd157 KV |
109 | }; |
110 | ||
111 | /* | |
112 | * Directions for interconnect pipe configuration. | |
113 | * These definitions may be used during configuration and are shared | |
114 | * between Host and Target. | |
115 | * | |
116 | * Pipe Directions are relative to the Host, so PIPEDIR_IN means | |
117 | * "coming IN over air through Target to Host" as with a WiFi Rx operation. | |
118 | * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air" | |
119 | * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man" | |
120 | * Target since things that are "PIPEDIR_OUT" are coming IN to the Target | |
121 | * over the interconnect. | |
122 | */ | |
123 | #define PIPEDIR_NONE 0 | |
124 | #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */ | |
125 | #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */ | |
126 | #define PIPEDIR_INOUT 3 /* bidirectional */ | |
127 | ||
128 | /* Establish a mapping between a service/direction and a pipe. */ | |
129 | struct service_to_pipe { | |
0fdc14e4 MK |
130 | __le32 service_id; |
131 | __le32 pipedir; | |
132 | __le32 pipenum; | |
5e3dd157 KV |
133 | }; |
134 | ||
5e3dd157 | 135 | /* Per-pipe state. */ |
87263e5b | 136 | struct ath10k_pci_pipe { |
5e3dd157 | 137 | /* Handle of underlying Copy Engine */ |
2aa39115 | 138 | struct ath10k_ce_pipe *ce_hdl; |
5e3dd157 KV |
139 | |
140 | /* Our pipe number; facilitiates use of pipe_info ptrs. */ | |
141 | u8 pipe_num; | |
142 | ||
143 | /* Convenience back pointer to hif_ce_state. */ | |
144 | struct ath10k *hif_ce_state; | |
145 | ||
146 | size_t buf_sz; | |
147 | ||
148 | /* protects compl_free and num_send_allowed */ | |
149 | spinlock_t pipe_lock; | |
150 | ||
5e3dd157 KV |
151 | struct ath10k_pci *ar_pci; |
152 | struct tasklet_struct intr; | |
153 | }; | |
154 | ||
7505f7c3 MK |
155 | struct ath10k_pci_supp_chip { |
156 | u32 dev_id; | |
157 | u32 rev_id; | |
158 | }; | |
159 | ||
5e3dd157 KV |
160 | struct ath10k_pci { |
161 | struct pci_dev *pdev; | |
162 | struct device *dev; | |
163 | struct ath10k *ar; | |
164 | void __iomem *mem; | |
aeae5b4c | 165 | size_t mem_len; |
5e3dd157 | 166 | |
5e3dd157 KV |
167 | /* |
168 | * Number of MSI interrupts granted, 0 --> using legacy PCI line | |
169 | * interrupts. | |
170 | */ | |
171 | int num_msi_intrs; | |
172 | ||
173 | struct tasklet_struct intr_tq; | |
174 | struct tasklet_struct msi_fw_err; | |
175 | ||
87263e5b | 176 | struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX]; |
5e3dd157 KV |
177 | |
178 | struct ath10k_hif_cb msg_callbacks_current; | |
179 | ||
5e3dd157 | 180 | /* Copy Engine used for Diagnostic Accesses */ |
2aa39115 | 181 | struct ath10k_ce_pipe *ce_diag; |
5e3dd157 KV |
182 | |
183 | /* FIXME: document what this really protects */ | |
184 | spinlock_t ce_lock; | |
185 | ||
186 | /* Map CE id to ce_state */ | |
2aa39115 | 187 | struct ath10k_ce_pipe ce_states[CE_COUNT_MAX]; |
728f95ee | 188 | struct timer_list rx_post_retry; |
76d870ed JD |
189 | |
190 | /* Due to HW quirks it is recommended to disable ASPM during device | |
191 | * bootup. To do that the original PCI-E Link Control is stored before | |
192 | * device bootup is executed and re-programmed later. | |
193 | */ | |
194 | u16 link_ctl; | |
77258d40 MK |
195 | |
196 | /* Protects ps_awake and ps_wake_refcount */ | |
197 | spinlock_t ps_lock; | |
198 | ||
199 | /* The device has a special powersave-oriented register. When device is | |
200 | * considered asleep it drains less power and driver is forbidden from | |
201 | * accessing most MMIO registers. If host were to access them without | |
202 | * waking up the device might scribble over host memory or return | |
203 | * 0xdeadbeef readouts. | |
204 | */ | |
205 | unsigned long ps_wake_refcount; | |
206 | ||
207 | /* Waking up takes some time (up to 2ms in some cases) so it can be bad | |
208 | * for latency. To mitigate this the device isn't immediately allowed | |
209 | * to sleep after all references are undone - instead there's a grace | |
210 | * period after which the powersave register is updated unless some | |
211 | * activity to/from device happened in the meantime. | |
212 | * | |
213 | * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC. | |
214 | */ | |
215 | struct timer_list ps_timer; | |
216 | ||
217 | /* MMIO registers are used to communicate with the device. With | |
218 | * intensive traffic accessing powersave register would be a bit | |
219 | * wasteful overhead and would needlessly stall CPU. It is far more | |
220 | * efficient to rely on a variable in RAM and update it only upon | |
221 | * powersave register state changes. | |
222 | */ | |
223 | bool ps_awake; | |
5e3dd157 KV |
224 | }; |
225 | ||
226 | static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar) | |
227 | { | |
e7b54194 | 228 | return (struct ath10k_pci *)ar->drv_priv; |
5e3dd157 KV |
229 | } |
230 | ||
728f95ee | 231 | #define ATH10K_PCI_RX_POST_RETRY_MS 50 |
5e3dd157 | 232 | #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */ |
6c3d7d78 | 233 | #define PCIE_WAKE_TIMEOUT 10000 /* 10ms */ |
5e3dd157 KV |
234 | |
235 | #define BAR_NUM 0 | |
236 | ||
237 | #define CDC_WAR_MAGIC_STR 0xceef0000 | |
238 | #define CDC_WAR_DATA_CE 4 | |
239 | ||
5e3dd157 KV |
240 | /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */ |
241 | #define DIAG_ACCESS_CE_TIMEOUT_MS 10 | |
242 | ||
77258d40 MK |
243 | void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value); |
244 | void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val); | |
245 | void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val); | |
233eb97f | 246 | |
77258d40 MK |
247 | u32 ath10k_pci_read32(struct ath10k *ar, u32 offset); |
248 | u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr); | |
249 | u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr); | |
233eb97f | 250 | |
77258d40 MK |
251 | /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too |
252 | * frequently. To avoid this put SoC to sleep after a very conservative grace | |
253 | * period. Adjust with great care. | |
254 | */ | |
255 | #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60 | |
5e3dd157 KV |
256 | |
257 | #endif /* _PCI_H_ */ |